1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 2ab4382d2SGreg Kroah-Hartman /* 3f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports 4ab4382d2SGreg Kroah-Hartman * 5ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6ab4382d2SGreg Kroah-Hartman * 7ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de> 8ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix 9ab4382d2SGreg Kroah-Hartman */ 10ab4382d2SGreg Kroah-Hartman 11ab4382d2SGreg Kroah-Hartman #include <linux/module.h> 12ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h> 13ab4382d2SGreg Kroah-Hartman #include <linux/init.h> 14ab4382d2SGreg Kroah-Hartman #include <linux/console.h> 15ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h> 16ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h> 17ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 18ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h> 19ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 20ab4382d2SGreg Kroah-Hartman #include <linux/serial.h> 21ab4382d2SGreg Kroah-Hartman #include <linux/clk.h> 22ab4382d2SGreg Kroah-Hartman #include <linux/delay.h> 23bd78ecd6SAhmad Fatoum #include <linux/ktime.h> 24fcfed1beSAnson Huang #include <linux/pinctrl/consumer.h> 25ab4382d2SGreg Kroah-Hartman #include <linux/rational.h> 26ab4382d2SGreg Kroah-Hartman #include <linux/slab.h> 2722698aa2SShawn Guo #include <linux/of.h> 2822698aa2SShawn Guo #include <linux/of_device.h> 29e32a9f8fSSachin Kamat #include <linux/io.h> 30b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h> 31ab4382d2SGreg Kroah-Hartman 32ab4382d2SGreg Kroah-Hartman #include <asm/irq.h> 33c6547c2eSSascha Hauer #include <linux/dma/imx-dma.h> 34ab4382d2SGreg Kroah-Hartman 3558362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h" 3658362d5bSUwe Kleine-König 37ab4382d2SGreg Kroah-Hartman /* Register definitions */ 38ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */ 39ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */ 40ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */ 41ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */ 42ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */ 43ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */ 44ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */ 45ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */ 46ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */ 47ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */ 48ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */ 49ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */ 50ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */ 51ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */ 52fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 53fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 54fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 55ab4382d2SGreg Kroah-Hartman 56ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/ 5755d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16) 58ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15) 59ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14) 60ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13) 61ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12) 62ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11) 63ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10) 6426c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0) 6525985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 66ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 67ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 68ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 69b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 70ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 71302e8dccSUwe Kleine-König #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 72ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */ 73ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 74ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 75ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */ 76302e8dccSUwe Kleine-König #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 77fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 78b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 79ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */ 80ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */ 81ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 82ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 83ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */ 84ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */ 85ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */ 86ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */ 87ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */ 88ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */ 89ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */ 90ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 9101f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 92ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 93ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */ 94ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */ 95ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 96ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */ 97ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 98ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */ 99ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */ 100ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */ 101b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 102ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 103ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 104ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 10527e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 106fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 107ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 108ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */ 109ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 110ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 111ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 112ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 113ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 114ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 115b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 116ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */ 117ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 118ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 119ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 120ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 121ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 1227be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 123ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 124ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 125ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 126ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 127ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */ 128ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 129ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */ 130ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 131ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 132ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 13386a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 13427e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */ 135ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 136ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 137ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 138ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 139ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 140ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 141ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */ 14290ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 14390ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 144ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 145ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */ 14690ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 147ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 148ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */ 149ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */ 150ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */ 151ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */ 152ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */ 153ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */ 154ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 155ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 156ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */ 157ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */ 158ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */ 159ab4382d2SGreg Kroah-Hartman 160ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */ 161ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207 162ab4382d2SGreg Kroah-Hartman #define MINOR_START 16 163ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc" 164ab4382d2SGreg Kroah-Hartman 165ab4382d2SGreg Kroah-Hartman /* 166ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals 167ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ 168ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before 169ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped. 170ab4382d2SGreg Kroah-Hartman */ 171ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000) 172ab4382d2SGreg Kroah-Hartman 173ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart" 174ab4382d2SGreg Kroah-Hartman 175ab4382d2SGreg Kroah-Hartman #define UART_NR 8 176ab4382d2SGreg Kroah-Hartman 177f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 178fe6b540aSShawn Guo enum imx_uart_type { 179fe6b540aSShawn Guo IMX1_UART, 180fe6b540aSShawn Guo IMX21_UART, 1811c06bde6SMartyn Welch IMX53_UART, 182a496e628SHuang Shijie IMX6Q_UART, 183fe6b540aSShawn Guo }; 184fe6b540aSShawn Guo 185fe6b540aSShawn Guo /* device type dependent stuff */ 186fe6b540aSShawn Guo struct imx_uart_data { 187fe6b540aSShawn Guo unsigned uts_reg; 188fe6b540aSShawn Guo enum imx_uart_type devtype; 189fe6b540aSShawn Guo }; 190fe6b540aSShawn Guo 191cb1a6092SUwe Kleine-König enum imx_tx_state { 192cb1a6092SUwe Kleine-König OFF, 193cb1a6092SUwe Kleine-König WAIT_AFTER_RTS, 194cb1a6092SUwe Kleine-König SEND, 195cb1a6092SUwe Kleine-König WAIT_AFTER_SEND, 196cb1a6092SUwe Kleine-König }; 197cb1a6092SUwe Kleine-König 198ab4382d2SGreg Kroah-Hartman struct imx_port { 199ab4382d2SGreg Kroah-Hartman struct uart_port port; 200ab4382d2SGreg Kroah-Hartman struct timer_list timer; 201ab4382d2SGreg Kroah-Hartman unsigned int old_status; 202ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1; 2037b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1; 20420ff2fe6SHuang Shijie unsigned int dte_mode:1; 2055a08a487SGeorge Hilliard unsigned int inverted_tx:1; 2065a08a487SGeorge Hilliard unsigned int inverted_rx:1; 2073a9465faSSascha Hauer struct clk *clk_ipg; 2083a9465faSSascha Hauer struct clk *clk_per; 2097d0b066fSUwe Kleine-König const struct imx_uart_data *devdata; 210b4cdc8f6SHuang Shijie 21158362d5bSUwe Kleine-König struct mctrl_gpios *gpios; 21258362d5bSUwe Kleine-König 2133a0ab62fSUwe Kleine-König /* shadow registers */ 2143a0ab62fSUwe Kleine-König unsigned int ucr1; 2153a0ab62fSUwe Kleine-König unsigned int ucr2; 2163a0ab62fSUwe Kleine-König unsigned int ucr3; 2173a0ab62fSUwe Kleine-König unsigned int ucr4; 2183a0ab62fSUwe Kleine-König unsigned int ufcr; 2193a0ab62fSUwe Kleine-König 220b4cdc8f6SHuang Shijie /* DMA fields */ 221b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1; 222b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1; 223b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1; 224b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx; 225b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2]; 226b4cdc8f6SHuang Shijie void *rx_buf; 2279d297239SNandor Han struct circ_buf rx_ring; 228db0a196bSFabien Lahoudere unsigned int rx_buf_size; 229db0a196bSFabien Lahoudere unsigned int rx_period_length; 2309d297239SNandor Han unsigned int rx_periods; 2319d297239SNandor Han dma_cookie_t rx_cookie; 2327cb92fd2SHuang Shijie unsigned int tx_bytes; 233b4cdc8f6SHuang Shijie unsigned int dma_tx_nents; 23490bb6bd3SShenwei Wang unsigned int saved_reg[10]; 235c868cbb7SEduardo Valentin bool context_saved; 236cb1a6092SUwe Kleine-König 237cb1a6092SUwe Kleine-König enum imx_tx_state tx_state; 238bd78ecd6SAhmad Fatoum struct hrtimer trigger_start_tx; 239bd78ecd6SAhmad Fatoum struct hrtimer trigger_stop_tx; 240ab4382d2SGreg Kroah-Hartman }; 241ab4382d2SGreg Kroah-Hartman 2420ad5a814SDirk Behme struct imx_port_ucrs { 2430ad5a814SDirk Behme unsigned int ucr1; 2440ad5a814SDirk Behme unsigned int ucr2; 2450ad5a814SDirk Behme unsigned int ucr3; 2460ad5a814SDirk Behme }; 2470ad5a814SDirk Behme 248fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = { 249fe6b540aSShawn Guo [IMX1_UART] = { 250fe6b540aSShawn Guo .uts_reg = IMX1_UTS, 251fe6b540aSShawn Guo .devtype = IMX1_UART, 252fe6b540aSShawn Guo }, 253fe6b540aSShawn Guo [IMX21_UART] = { 254fe6b540aSShawn Guo .uts_reg = IMX21_UTS, 255fe6b540aSShawn Guo .devtype = IMX21_UART, 256fe6b540aSShawn Guo }, 2571c06bde6SMartyn Welch [IMX53_UART] = { 2581c06bde6SMartyn Welch .uts_reg = IMX21_UTS, 2591c06bde6SMartyn Welch .devtype = IMX53_UART, 2601c06bde6SMartyn Welch }, 261a496e628SHuang Shijie [IMX6Q_UART] = { 262a496e628SHuang Shijie .uts_reg = IMX21_UTS, 263a496e628SHuang Shijie .devtype = IMX6Q_UART, 264a496e628SHuang Shijie }, 265fe6b540aSShawn Guo }; 266fe6b540aSShawn Guo 267ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = { 268a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 2691c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 27022698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 27122698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 27222698aa2SShawn Guo { /* sentinel */ } 27322698aa2SShawn Guo }; 27422698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 27522698aa2SShawn Guo 27627c84426SUwe Kleine-König static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 27727c84426SUwe Kleine-König { 2783a0ab62fSUwe Kleine-König switch (offset) { 2793a0ab62fSUwe Kleine-König case UCR1: 2803a0ab62fSUwe Kleine-König sport->ucr1 = val; 2813a0ab62fSUwe Kleine-König break; 2823a0ab62fSUwe Kleine-König case UCR2: 2833a0ab62fSUwe Kleine-König sport->ucr2 = val; 2843a0ab62fSUwe Kleine-König break; 2853a0ab62fSUwe Kleine-König case UCR3: 2863a0ab62fSUwe Kleine-König sport->ucr3 = val; 2873a0ab62fSUwe Kleine-König break; 2883a0ab62fSUwe Kleine-König case UCR4: 2893a0ab62fSUwe Kleine-König sport->ucr4 = val; 2903a0ab62fSUwe Kleine-König break; 2913a0ab62fSUwe Kleine-König case UFCR: 2923a0ab62fSUwe Kleine-König sport->ufcr = val; 2933a0ab62fSUwe Kleine-König break; 2943a0ab62fSUwe Kleine-König default: 2953a0ab62fSUwe Kleine-König break; 2963a0ab62fSUwe Kleine-König } 29727c84426SUwe Kleine-König writel(val, sport->port.membase + offset); 29827c84426SUwe Kleine-König } 29927c84426SUwe Kleine-König 30027c84426SUwe Kleine-König static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 30127c84426SUwe Kleine-König { 3023a0ab62fSUwe Kleine-König switch (offset) { 3033a0ab62fSUwe Kleine-König case UCR1: 3043a0ab62fSUwe Kleine-König return sport->ucr1; 3053a0ab62fSUwe Kleine-König break; 3063a0ab62fSUwe Kleine-König case UCR2: 3073a0ab62fSUwe Kleine-König /* 3083a0ab62fSUwe Kleine-König * UCR2_SRST is the only bit in the cached registers that might 3093a0ab62fSUwe Kleine-König * differ from the value that was last written. As it only 310728e74a4SUwe Kleine-König * automatically becomes one after being cleared, reread 311728e74a4SUwe Kleine-König * conditionally. 3123a0ab62fSUwe Kleine-König */ 3130aa821d8SStefan Agner if (!(sport->ucr2 & UCR2_SRST)) 3143a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + offset); 3153a0ab62fSUwe Kleine-König return sport->ucr2; 3163a0ab62fSUwe Kleine-König break; 3173a0ab62fSUwe Kleine-König case UCR3: 3183a0ab62fSUwe Kleine-König return sport->ucr3; 3193a0ab62fSUwe Kleine-König break; 3203a0ab62fSUwe Kleine-König case UCR4: 3213a0ab62fSUwe Kleine-König return sport->ucr4; 3223a0ab62fSUwe Kleine-König break; 3233a0ab62fSUwe Kleine-König case UFCR: 3243a0ab62fSUwe Kleine-König return sport->ufcr; 3253a0ab62fSUwe Kleine-König break; 3263a0ab62fSUwe Kleine-König default: 32727c84426SUwe Kleine-König return readl(sport->port.membase + offset); 32827c84426SUwe Kleine-König } 3293a0ab62fSUwe Kleine-König } 33027c84426SUwe Kleine-König 3319d1a50a2SUwe Kleine-König static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 332fe6b540aSShawn Guo { 333fe6b540aSShawn Guo return sport->devdata->uts_reg; 334fe6b540aSShawn Guo } 335fe6b540aSShawn Guo 3369d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx1(struct imx_port *sport) 337fe6b540aSShawn Guo { 338fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART; 339fe6b540aSShawn Guo } 340fe6b540aSShawn Guo 3419d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx21(struct imx_port *sport) 342fe6b540aSShawn Guo { 343fe6b540aSShawn Guo return sport->devdata->devtype == IMX21_UART; 344fe6b540aSShawn Guo } 345fe6b540aSShawn Guo 3469d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx53(struct imx_port *sport) 3471c06bde6SMartyn Welch { 3481c06bde6SMartyn Welch return sport->devdata->devtype == IMX53_UART; 3491c06bde6SMartyn Welch } 3501c06bde6SMartyn Welch 3519d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx6q(struct imx_port *sport) 352a496e628SHuang Shijie { 353a496e628SHuang Shijie return sport->devdata->devtype == IMX6Q_UART; 354a496e628SHuang Shijie } 355ab4382d2SGreg Kroah-Hartman /* 35644a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers 35744a75411Sfabio.estevam@freescale.com */ 3580db4f9b9SFugang Duan #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 3599d1a50a2SUwe Kleine-König static void imx_uart_ucrs_save(struct imx_port *sport, 36044a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 36144a75411Sfabio.estevam@freescale.com { 36244a75411Sfabio.estevam@freescale.com /* save control registers */ 36327c84426SUwe Kleine-König ucr->ucr1 = imx_uart_readl(sport, UCR1); 36427c84426SUwe Kleine-König ucr->ucr2 = imx_uart_readl(sport, UCR2); 36527c84426SUwe Kleine-König ucr->ucr3 = imx_uart_readl(sport, UCR3); 36644a75411Sfabio.estevam@freescale.com } 36744a75411Sfabio.estevam@freescale.com 3689d1a50a2SUwe Kleine-König static void imx_uart_ucrs_restore(struct imx_port *sport, 36944a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr) 37044a75411Sfabio.estevam@freescale.com { 37144a75411Sfabio.estevam@freescale.com /* restore control registers */ 37227c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr1, UCR1); 37327c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr2, UCR2); 37427c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr3, UCR3); 37544a75411Sfabio.estevam@freescale.com } 376e8bfa760SFabio Estevam #endif 37744a75411Sfabio.estevam@freescale.com 3784e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */ 3799d1a50a2SUwe Kleine-König static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 38058362d5bSUwe Kleine-König { 381bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 38258362d5bSUwe Kleine-König 383a0983c74SIan Jamison sport->port.mctrl |= TIOCM_RTS; 384a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 38558362d5bSUwe Kleine-König } 38658362d5bSUwe Kleine-König 3874e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */ 3889d1a50a2SUwe Kleine-König static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 38958362d5bSUwe Kleine-König { 390bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC; 391bc2be239SFabio Estevam *ucr2 |= UCR2_CTS; 39258362d5bSUwe Kleine-König 393a0983c74SIan Jamison sport->port.mctrl &= ~TIOCM_RTS; 394a0983c74SIan Jamison mctrl_gpio_set(sport->gpios, sport->port.mctrl); 39558362d5bSUwe Kleine-König } 39658362d5bSUwe Kleine-König 397bd78ecd6SAhmad Fatoum static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec) 398bd78ecd6SAhmad Fatoum { 399f751ae1cSJiri Slaby hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL); 400bd78ecd6SAhmad Fatoum } 401bd78ecd6SAhmad Fatoum 4026aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4039d1a50a2SUwe Kleine-König static void imx_uart_start_rx(struct uart_port *port) 40476821e22SUwe Kleine-König { 40576821e22SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 40676821e22SUwe Kleine-König unsigned int ucr1, ucr2; 40776821e22SUwe Kleine-König 40876821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 40976821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 41076821e22SUwe Kleine-König 41176821e22SUwe Kleine-König ucr2 |= UCR2_RXEN; 41276821e22SUwe Kleine-König 41376821e22SUwe Kleine-König if (sport->dma_is_enabled) { 41476821e22SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 41576821e22SUwe Kleine-König } else { 41676821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 41781ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 41876821e22SUwe Kleine-König } 41976821e22SUwe Kleine-König 42076821e22SUwe Kleine-König /* Write UCR2 first as it includes RXEN */ 42176821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 42276821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 42376821e22SUwe Kleine-König } 42476821e22SUwe Kleine-König 42576821e22SUwe Kleine-König /* called with port.lock taken and irqs off */ 4269d1a50a2SUwe Kleine-König static void imx_uart_stop_tx(struct uart_port *port) 427ab4382d2SGreg Kroah-Hartman { 428ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 429cb1a6092SUwe Kleine-König u32 ucr1, ucr4, usr2; 430cb1a6092SUwe Kleine-König 431cb1a6092SUwe Kleine-König if (sport->tx_state == OFF) 432cb1a6092SUwe Kleine-König return; 433ab4382d2SGreg Kroah-Hartman 4349ce4f8f3SGreg Kroah-Hartman /* 4359ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running 4369ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish. 4379ce4f8f3SGreg Kroah-Hartman */ 438686351f3SUwe Kleine-König if (sport->dma_is_txing) 4399ce4f8f3SGreg Kroah-Hartman return; 440b4cdc8f6SHuang Shijie 4414444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 442c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); 44317b8f2a3SUwe Kleine-König 444cb1a6092SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 445cb1a6092SUwe Kleine-König if (!(usr2 & USR2_TXDC)) { 446cb1a6092SUwe Kleine-König /* The shifter is still busy, so retry once TC triggers */ 447cb1a6092SUwe Kleine-König return; 448cb1a6092SUwe Kleine-König } 449cb1a6092SUwe Kleine-König 450cb1a6092SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 451cb1a6092SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 452cb1a6092SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 453cb1a6092SUwe Kleine-König 454cb1a6092SUwe Kleine-König /* in rs485 mode disable transmitter */ 455cb1a6092SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 456cb1a6092SUwe Kleine-König if (sport->tx_state == SEND) { 457cb1a6092SUwe Kleine-König sport->tx_state = WAIT_AFTER_SEND; 458582e9a24SHarald Seiler 459582e9a24SHarald Seiler if (port->rs485.delay_rts_after_send > 0) { 460bd78ecd6SAhmad Fatoum start_hrtimer_ms(&sport->trigger_stop_tx, 461bd78ecd6SAhmad Fatoum port->rs485.delay_rts_after_send); 462bd78ecd6SAhmad Fatoum return; 463cb1a6092SUwe Kleine-König } 464cb1a6092SUwe Kleine-König 465582e9a24SHarald Seiler /* continue without any delay */ 466582e9a24SHarald Seiler } 467582e9a24SHarald Seiler 468cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_RTS || 469bd78ecd6SAhmad Fatoum sport->tx_state == WAIT_AFTER_SEND) { 470cb1a6092SUwe Kleine-König u32 ucr2; 471cb1a6092SUwe Kleine-König 472bd78ecd6SAhmad Fatoum hrtimer_try_to_cancel(&sport->trigger_start_tx); 473cb1a6092SUwe Kleine-König 474cb1a6092SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 47517b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 4769d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 4771a613626SFabio Estevam else 4789d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 4794444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 48017b8f2a3SUwe Kleine-König 4819d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 48276821e22SUwe Kleine-König 483cb1a6092SUwe Kleine-König sport->tx_state = OFF; 484cb1a6092SUwe Kleine-König } 485cb1a6092SUwe Kleine-König } else { 486cb1a6092SUwe Kleine-König sport->tx_state = OFF; 48717b8f2a3SUwe Kleine-König } 488ab4382d2SGreg Kroah-Hartman } 489ab4382d2SGreg Kroah-Hartman 4906aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 4919d1a50a2SUwe Kleine-König static void imx_uart_stop_rx(struct uart_port *port) 492ab4382d2SGreg Kroah-Hartman { 493ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 494028e0838SFugang Duan u32 ucr1, ucr2, ucr4; 495ab4382d2SGreg Kroah-Hartman 4964444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 49776821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 498028e0838SFugang Duan ucr4 = imx_uart_readl(sport, UCR4); 49976821e22SUwe Kleine-König 50076821e22SUwe Kleine-König if (sport->dma_is_enabled) { 50176821e22SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 50276821e22SUwe Kleine-König } else { 50376821e22SUwe Kleine-König ucr1 &= ~UCR1_RRDYEN; 50481ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 505028e0838SFugang Duan ucr4 &= ~UCR4_OREN; 50676821e22SUwe Kleine-König } 50776821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 508028e0838SFugang Duan imx_uart_writel(sport, ucr4, UCR4); 50976821e22SUwe Kleine-König 51076821e22SUwe Kleine-König ucr2 &= ~UCR2_RXEN; 51176821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 512ab4382d2SGreg Kroah-Hartman } 513ab4382d2SGreg Kroah-Hartman 5146aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5159d1a50a2SUwe Kleine-König static void imx_uart_enable_ms(struct uart_port *port) 516ab4382d2SGreg Kroah-Hartman { 517ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 518ab4382d2SGreg Kroah-Hartman 519ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies); 52058362d5bSUwe Kleine-König 52158362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios); 522ab4382d2SGreg Kroah-Hartman } 523ab4382d2SGreg Kroah-Hartman 5249d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport); 5256aed2a88SUwe Kleine-König 5266aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 5279d1a50a2SUwe Kleine-König static inline void imx_uart_transmit_buffer(struct imx_port *sport) 528ab4382d2SGreg Kroah-Hartman { 529ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit; 530ab4382d2SGreg Kroah-Hartman 5315e42e9a3SPeter Hurley if (sport->port.x_char) { 5325e42e9a3SPeter Hurley /* Send next char */ 53327c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.x_char, URTX0); 5347e2fb5aaSJiada Wang sport->port.icount.tx++; 5357e2fb5aaSJiada Wang sport->port.x_char = 0; 5365e42e9a3SPeter Hurley return; 5375e42e9a3SPeter Hurley } 5385e42e9a3SPeter Hurley 5395e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 5409d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 5415e42e9a3SPeter Hurley return; 5425e42e9a3SPeter Hurley } 5435e42e9a3SPeter Hurley 54491a1a909SJiada Wang if (sport->dma_is_enabled) { 5454444dcf1SUwe Kleine-König u32 ucr1; 54691a1a909SJiada Wang /* 54791a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled 54891a1a909SJiada Wang * and the TX IRQ is disabled. 54991a1a909SJiada Wang **/ 5504444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 551c514a6f8SSergey Organov ucr1 &= ~UCR1_TRDYEN; 55291a1a909SJiada Wang if (sport->dma_is_txing) { 5534444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 5544444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 55591a1a909SJiada Wang } else { 5564444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 5579d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 55891a1a909SJiada Wang } 55991a1a909SJiada Wang 5605aabd3b0SIan Jamison return; 5610c549223SUwe Kleine-König } 5625aabd3b0SIan Jamison 5635aabd3b0SIan Jamison while (!uart_circ_empty(xmit) && 5649d1a50a2SUwe Kleine-König !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 565ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail] 566ab4382d2SGreg Kroah-Hartman * out the port here */ 56727c84426SUwe Kleine-König imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 568ab4382d2SGreg Kroah-Hartman xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 569ab4382d2SGreg Kroah-Hartman sport->port.icount.tx++; 570ab4382d2SGreg Kroah-Hartman } 571ab4382d2SGreg Kroah-Hartman 572ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 573ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port); 574ab4382d2SGreg Kroah-Hartman 575ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit)) 5769d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port); 577ab4382d2SGreg Kroah-Hartman } 578ab4382d2SGreg Kroah-Hartman 5799d1a50a2SUwe Kleine-König static void imx_uart_dma_tx_callback(void *data) 580b4cdc8f6SHuang Shijie { 581b4cdc8f6SHuang Shijie struct imx_port *sport = data; 582b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0]; 583b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 584b4cdc8f6SHuang Shijie unsigned long flags; 5854444dcf1SUwe Kleine-König u32 ucr1; 586b4cdc8f6SHuang Shijie 58742f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags); 58842f752b3SDirk Behme 589b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 590b4cdc8f6SHuang Shijie 5914444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 5924444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 5934444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 594a2c718ceSDirk Behme 59542f752b3SDirk Behme /* update the stat */ 59642f752b3SDirk Behme xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 59742f752b3SDirk Behme sport->port.icount.tx += sport->tx_bytes; 59842f752b3SDirk Behme 59942f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 60042f752b3SDirk Behme 601b4cdc8f6SHuang Shijie sport->dma_is_txing = 0; 602b4cdc8f6SHuang Shijie 603d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 604b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port); 6059ce4f8f3SGreg Kroah-Hartman 6060bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 6079d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 60818665414SUwe Kleine-König else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 60918665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 61018665414SUwe Kleine-König ucr4 |= UCR4_TCEN; 61118665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 61218665414SUwe Kleine-König } 61364432a85SUwe Kleine-König 6140bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 615b4cdc8f6SHuang Shijie } 616b4cdc8f6SHuang Shijie 6176aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6189d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport) 619b4cdc8f6SHuang Shijie { 620b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit; 621b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl; 622b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 623b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx; 624b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 62518665414SUwe Kleine-König u32 ucr1, ucr4; 626b4cdc8f6SHuang Shijie int ret; 627b4cdc8f6SHuang Shijie 62842f752b3SDirk Behme if (sport->dma_is_txing) 629b4cdc8f6SHuang Shijie return; 630b4cdc8f6SHuang Shijie 63118665414SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 63218665414SUwe Kleine-König ucr4 &= ~UCR4_TCEN; 63318665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 63418665414SUwe Kleine-König 635b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit); 636b4cdc8f6SHuang Shijie 637f7670783SFugang Duan if (xmit->tail < xmit->head || xmit->head == 0) { 6387942f857SDirk Behme sport->dma_tx_nents = 1; 6397942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 6407942f857SDirk Behme } else { 641b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2; 642b4cdc8f6SHuang Shijie sg_init_table(sgl, 2); 643b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail, 644b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail); 645b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head); 646b4cdc8f6SHuang Shijie } 647b4cdc8f6SHuang Shijie 648b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 649b4cdc8f6SHuang Shijie if (ret == 0) { 650b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n"); 651b4cdc8f6SHuang Shijie return; 652b4cdc8f6SHuang Shijie } 653596fd8dfSPeng Fan desc = dmaengine_prep_slave_sg(chan, sgl, ret, 654b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 655b4cdc8f6SHuang Shijie if (!desc) { 65624649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 65724649821SDirk Behme DMA_TO_DEVICE); 658b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 659b4cdc8f6SHuang Shijie return; 660b4cdc8f6SHuang Shijie } 6619d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_tx_callback; 662b4cdc8f6SHuang Shijie desc->callback_param = sport; 663b4cdc8f6SHuang Shijie 664b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 665b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit)); 666a2c718ceSDirk Behme 6674444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 6684444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN; 6694444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 670a2c718ceSDirk Behme 671b4cdc8f6SHuang Shijie /* fire it */ 672b4cdc8f6SHuang Shijie sport->dma_is_txing = 1; 673b4cdc8f6SHuang Shijie dmaengine_submit(desc); 674b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 675b4cdc8f6SHuang Shijie return; 676b4cdc8f6SHuang Shijie } 677b4cdc8f6SHuang Shijie 6786aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 6799d1a50a2SUwe Kleine-König static void imx_uart_start_tx(struct uart_port *port) 680ab4382d2SGreg Kroah-Hartman { 681ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 6824444dcf1SUwe Kleine-König u32 ucr1; 683ab4382d2SGreg Kroah-Hartman 68448669b69SUwe Kleine-König if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 68548669b69SUwe Kleine-König return; 68648669b69SUwe Kleine-König 687cb1a6092SUwe Kleine-König /* 688cb1a6092SUwe Kleine-König * We cannot simply do nothing here if sport->tx_state == SEND already 689cb1a6092SUwe Kleine-König * because UCR1_TXMPTYEN might already have been cleared in 690cb1a6092SUwe Kleine-König * imx_uart_stop_tx(), but tx_state is still SEND. 691cb1a6092SUwe Kleine-König */ 6924444dcf1SUwe Kleine-König 693cb1a6092SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) { 694cb1a6092SUwe Kleine-König if (sport->tx_state == OFF) { 695cb1a6092SUwe Kleine-König u32 ucr2 = imx_uart_readl(sport, UCR2); 69617b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 6979d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 6981a613626SFabio Estevam else 6999d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 7004444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 70117b8f2a3SUwe Kleine-König 70276821e22SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 7039d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 70476821e22SUwe Kleine-König 705cb1a6092SUwe Kleine-König sport->tx_state = WAIT_AFTER_RTS; 706582e9a24SHarald Seiler 707582e9a24SHarald Seiler if (port->rs485.delay_rts_before_send > 0) { 708bd78ecd6SAhmad Fatoum start_hrtimer_ms(&sport->trigger_start_tx, 709bd78ecd6SAhmad Fatoum port->rs485.delay_rts_before_send); 710bd78ecd6SAhmad Fatoum return; 711cb1a6092SUwe Kleine-König } 712cb1a6092SUwe Kleine-König 713582e9a24SHarald Seiler /* continue without any delay */ 714582e9a24SHarald Seiler } 715582e9a24SHarald Seiler 716bd78ecd6SAhmad Fatoum if (sport->tx_state == WAIT_AFTER_SEND 717bd78ecd6SAhmad Fatoum || sport->tx_state == WAIT_AFTER_RTS) { 718cb1a6092SUwe Kleine-König 719bd78ecd6SAhmad Fatoum hrtimer_try_to_cancel(&sport->trigger_stop_tx); 720bd78ecd6SAhmad Fatoum 72118665414SUwe Kleine-König /* 722cb1a6092SUwe Kleine-König * Enable transmitter and shifter empty irq only if DMA 723cb1a6092SUwe Kleine-König * is off. In the DMA case this is done in the 724cb1a6092SUwe Kleine-König * tx-callback. 72518665414SUwe Kleine-König */ 72618665414SUwe Kleine-König if (!sport->dma_is_enabled) { 72718665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4); 7284444dcf1SUwe Kleine-König ucr4 |= UCR4_TCEN; 7294444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 73017b8f2a3SUwe Kleine-König } 731cb1a6092SUwe Kleine-König 732cb1a6092SUwe Kleine-König sport->tx_state = SEND; 733cb1a6092SUwe Kleine-König } 734cb1a6092SUwe Kleine-König } else { 735cb1a6092SUwe Kleine-König sport->tx_state = SEND; 73618665414SUwe Kleine-König } 73717b8f2a3SUwe Kleine-König 738b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) { 7394444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 740c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); 741b4cdc8f6SHuang Shijie } 742ab4382d2SGreg Kroah-Hartman 743b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 74491a1a909SJiada Wang if (sport->port.x_char) { 74591a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and 74691a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */ 7474444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 7484444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 749c514a6f8SSergey Organov ucr1 |= UCR1_TRDYEN; 7504444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 75191a1a909SJiada Wang return; 75291a1a909SJiada Wang } 75391a1a909SJiada Wang 7545e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) && 7555e42e9a3SPeter Hurley !uart_tx_stopped(port)) 7569d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport); 757b4cdc8f6SHuang Shijie return; 758b4cdc8f6SHuang Shijie } 759ab4382d2SGreg Kroah-Hartman } 760ab4382d2SGreg Kroah-Hartman 761101aa46bSUwe Kleine-König static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id) 762ab4382d2SGreg Kroah-Hartman { 763ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 7644444dcf1SUwe Kleine-König u32 usr1; 765ab4382d2SGreg Kroah-Hartman 76627c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD, USR1); 7674444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 7684444dcf1SUwe Kleine-König uart_handle_cts_change(&sport->port, !!usr1); 769ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 770ab4382d2SGreg Kroah-Hartman 771ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 772ab4382d2SGreg Kroah-Hartman } 773ab4382d2SGreg Kroah-Hartman 774101aa46bSUwe Kleine-König static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 775101aa46bSUwe Kleine-König { 776101aa46bSUwe Kleine-König struct imx_port *sport = dev_id; 777101aa46bSUwe Kleine-König irqreturn_t ret; 778101aa46bSUwe Kleine-König 779101aa46bSUwe Kleine-König spin_lock(&sport->port.lock); 780101aa46bSUwe Kleine-König 781101aa46bSUwe Kleine-König ret = __imx_uart_rtsint(irq, dev_id); 782101aa46bSUwe Kleine-König 783101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock); 784101aa46bSUwe Kleine-König 785101aa46bSUwe Kleine-König return ret; 786101aa46bSUwe Kleine-König } 787101aa46bSUwe Kleine-König 7889d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_txint(int irq, void *dev_id) 789ab4382d2SGreg Kroah-Hartman { 790ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 791ab4382d2SGreg Kroah-Hartman 792c974991dSjun qian spin_lock(&sport->port.lock); 7939d1a50a2SUwe Kleine-König imx_uart_transmit_buffer(sport); 794c974991dSjun qian spin_unlock(&sport->port.lock); 795ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 796ab4382d2SGreg Kroah-Hartman } 797ab4382d2SGreg Kroah-Hartman 798101aa46bSUwe Kleine-König static irqreturn_t __imx_uart_rxint(int irq, void *dev_id) 799ab4382d2SGreg Kroah-Hartman { 800ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 801ab4382d2SGreg Kroah-Hartman unsigned int rx, flg, ignored = 0; 80292a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port; 803ab4382d2SGreg Kroah-Hartman 80427c84426SUwe Kleine-König while (imx_uart_readl(sport, USR2) & USR2_RDR) { 8054444dcf1SUwe Kleine-König u32 usr2; 8064444dcf1SUwe Kleine-König 807ab4382d2SGreg Kroah-Hartman flg = TTY_NORMAL; 808ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++; 809ab4382d2SGreg Kroah-Hartman 81027c84426SUwe Kleine-König rx = imx_uart_readl(sport, URXD0); 811ab4382d2SGreg Kroah-Hartman 8124444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 8134444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 81427c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 815ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port)) 816ab4382d2SGreg Kroah-Hartman continue; 817ab4382d2SGreg Kroah-Hartman } 818ab4382d2SGreg Kroah-Hartman 819ab4382d2SGreg Kroah-Hartman if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 820ab4382d2SGreg Kroah-Hartman continue; 821ab4382d2SGreg Kroah-Hartman 822019dc9eaSHui Wang if (unlikely(rx & URXD_ERR)) { 823019dc9eaSHui Wang if (rx & URXD_BRK) 824019dc9eaSHui Wang sport->port.icount.brk++; 825019dc9eaSHui Wang else if (rx & URXD_PRERR) 826ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++; 827ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 828ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++; 829ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 830ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++; 831ab4382d2SGreg Kroah-Hartman 832ab4382d2SGreg Kroah-Hartman if (rx & sport->port.ignore_status_mask) { 833ab4382d2SGreg Kroah-Hartman if (++ignored > 100) 834ab4382d2SGreg Kroah-Hartman goto out; 835ab4382d2SGreg Kroah-Hartman continue; 836ab4382d2SGreg Kroah-Hartman } 837ab4382d2SGreg Kroah-Hartman 8388d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF); 839ab4382d2SGreg Kroah-Hartman 840019dc9eaSHui Wang if (rx & URXD_BRK) 841019dc9eaSHui Wang flg = TTY_BREAK; 842019dc9eaSHui Wang else if (rx & URXD_PRERR) 843ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY; 844ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR) 845ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME; 846ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN) 847ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN; 848ab4382d2SGreg Kroah-Hartman 849ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0; 850ab4382d2SGreg Kroah-Hartman } 851ab4382d2SGreg Kroah-Hartman 85255d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 85355d8693aSJiada Wang goto out; 85455d8693aSJiada Wang 8559b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0) 8569b289932SManfred Schlaegl sport->port.icount.buf_overrun++; 857ab4382d2SGreg Kroah-Hartman } 858ab4382d2SGreg Kroah-Hartman 859ab4382d2SGreg Kroah-Hartman out: 8602e124b4aSJiri Slaby tty_flip_buffer_push(port); 861101aa46bSUwe Kleine-König 862ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED; 863ab4382d2SGreg Kroah-Hartman } 864ab4382d2SGreg Kroah-Hartman 865101aa46bSUwe Kleine-König static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 866101aa46bSUwe Kleine-König { 867101aa46bSUwe Kleine-König struct imx_port *sport = dev_id; 868101aa46bSUwe Kleine-König irqreturn_t ret; 869101aa46bSUwe Kleine-König 870101aa46bSUwe Kleine-König spin_lock(&sport->port.lock); 871101aa46bSUwe Kleine-König 872101aa46bSUwe Kleine-König ret = __imx_uart_rxint(irq, dev_id); 873101aa46bSUwe Kleine-König 874101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock); 875101aa46bSUwe Kleine-König 876101aa46bSUwe Kleine-König return ret; 877101aa46bSUwe Kleine-König } 878101aa46bSUwe Kleine-König 8799d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport); 880b4cdc8f6SHuang Shijie 88166f95884SUwe Kleine-König /* 88266f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted. 88366f95884SUwe Kleine-König */ 8849d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 88566f95884SUwe Kleine-König { 88666f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR; 88727c84426SUwe Kleine-König unsigned usr1 = imx_uart_readl(sport, USR1); 88827c84426SUwe Kleine-König unsigned usr2 = imx_uart_readl(sport, USR2); 88966f95884SUwe Kleine-König 89066f95884SUwe Kleine-König if (usr1 & USR1_RTSS) 89166f95884SUwe Kleine-König tmp |= TIOCM_CTS; 89266f95884SUwe Kleine-König 89366f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */ 8944b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN)) 89566f95884SUwe Kleine-König tmp |= TIOCM_CAR; 89666f95884SUwe Kleine-König 89766f95884SUwe Kleine-König if (sport->dte_mode) 89827c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 89966f95884SUwe Kleine-König tmp |= TIOCM_RI; 90066f95884SUwe Kleine-König 90166f95884SUwe Kleine-König return tmp; 90266f95884SUwe Kleine-König } 90366f95884SUwe Kleine-König 90466f95884SUwe Kleine-König /* 90566f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called. 90666f95884SUwe Kleine-König */ 9079d1a50a2SUwe Kleine-König static void imx_uart_mctrl_check(struct imx_port *sport) 90866f95884SUwe Kleine-König { 90966f95884SUwe Kleine-König unsigned int status, changed; 91066f95884SUwe Kleine-König 9119d1a50a2SUwe Kleine-König status = imx_uart_get_hwmctrl(sport); 91266f95884SUwe Kleine-König changed = status ^ sport->old_status; 91366f95884SUwe Kleine-König 91466f95884SUwe Kleine-König if (changed == 0) 91566f95884SUwe Kleine-König return; 91666f95884SUwe Kleine-König 91766f95884SUwe Kleine-König sport->old_status = status; 91866f95884SUwe Kleine-König 91966f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI) 92066f95884SUwe Kleine-König sport->port.icount.rng++; 92166f95884SUwe Kleine-König if (changed & TIOCM_DSR) 92266f95884SUwe Kleine-König sport->port.icount.dsr++; 92366f95884SUwe Kleine-König if (changed & TIOCM_CAR) 92466f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 92566f95884SUwe Kleine-König if (changed & TIOCM_CTS) 92666f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 92766f95884SUwe Kleine-König 92866f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 92966f95884SUwe Kleine-König } 93066f95884SUwe Kleine-König 9319d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_int(int irq, void *dev_id) 932ab4382d2SGreg Kroah-Hartman { 933ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id; 93443776896SUwe Kleine-König unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 9354d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE; 936ab4382d2SGreg Kroah-Hartman 9379baedb7bSJohan Hovold spin_lock(&sport->port.lock); 938101aa46bSUwe Kleine-König 93927c84426SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 94027c84426SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 94127c84426SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 94227c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 94327c84426SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 94427c84426SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 945ab4382d2SGreg Kroah-Hartman 94643776896SUwe Kleine-König /* 94743776896SUwe Kleine-König * Even if a condition is true that can trigger an irq only handle it if 94843776896SUwe Kleine-König * the respective irq source is enabled. This prevents some undesired 94943776896SUwe Kleine-König * actions, for example if a character that sits in the RX FIFO and that 95043776896SUwe Kleine-König * should be fetched via DMA is tried to be fetched using PIO. Or the 95143776896SUwe Kleine-König * receiver is currently off and so reading from URXD0 results in an 95243776896SUwe Kleine-König * exception. So just mask the (raw) status bits for disabled irqs. 95343776896SUwe Kleine-König */ 95443776896SUwe Kleine-König if ((ucr1 & UCR1_RRDYEN) == 0) 95543776896SUwe Kleine-König usr1 &= ~USR1_RRDY; 95643776896SUwe Kleine-König if ((ucr2 & UCR2_ATEN) == 0) 95743776896SUwe Kleine-König usr1 &= ~USR1_AGTIM; 958c514a6f8SSergey Organov if ((ucr1 & UCR1_TRDYEN) == 0) 95943776896SUwe Kleine-König usr1 &= ~USR1_TRDY; 96043776896SUwe Kleine-König if ((ucr4 & UCR4_TCEN) == 0) 96143776896SUwe Kleine-König usr2 &= ~USR2_TXDC; 96243776896SUwe Kleine-König if ((ucr3 & UCR3_DTRDEN) == 0) 96343776896SUwe Kleine-König usr1 &= ~USR1_DTRD; 96443776896SUwe Kleine-König if ((ucr1 & UCR1_RTSDEN) == 0) 96543776896SUwe Kleine-König usr1 &= ~USR1_RTSD; 96643776896SUwe Kleine-König if ((ucr3 & UCR3_AWAKEN) == 0) 96743776896SUwe Kleine-König usr1 &= ~USR1_AWAKE; 96843776896SUwe Kleine-König if ((ucr4 & UCR4_OREN) == 0) 96943776896SUwe Kleine-König usr2 &= ~USR2_ORE; 97043776896SUwe Kleine-König 97143776896SUwe Kleine-König if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 972d1d996afSMatthias Schiffer imx_uart_writel(sport, USR1_AGTIM, USR1); 973d1d996afSMatthias Schiffer 974101aa46bSUwe Kleine-König __imx_uart_rxint(irq, dev_id); 9754d845a62SUwe Kleine-König ret = IRQ_HANDLED; 976b4cdc8f6SHuang Shijie } 977ab4382d2SGreg Kroah-Hartman 97843776896SUwe Kleine-König if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 979101aa46bSUwe Kleine-König imx_uart_transmit_buffer(sport); 9804d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9814d845a62SUwe Kleine-König } 982ab4382d2SGreg Kroah-Hartman 9830399fd61SUwe Kleine-König if (usr1 & USR1_DTRD) { 98427c84426SUwe Kleine-König imx_uart_writel(sport, USR1_DTRD, USR1); 98527e16501SUwe Kleine-König 9869d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 98727e16501SUwe Kleine-König 98827e16501SUwe Kleine-König ret = IRQ_HANDLED; 98927e16501SUwe Kleine-König } 99027e16501SUwe Kleine-König 9910399fd61SUwe Kleine-König if (usr1 & USR1_RTSD) { 992101aa46bSUwe Kleine-König __imx_uart_rtsint(irq, dev_id); 9934d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9944d845a62SUwe Kleine-König } 995ab4382d2SGreg Kroah-Hartman 9960399fd61SUwe Kleine-König if (usr1 & USR1_AWAKE) { 99727c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 9984d845a62SUwe Kleine-König ret = IRQ_HANDLED; 9994d845a62SUwe Kleine-König } 1000db1a9b55SFabio Estevam 10010399fd61SUwe Kleine-König if (usr2 & USR2_ORE) { 1002f1f836e4SAlexander Stein sport->port.icount.overrun++; 100327c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 10044d845a62SUwe Kleine-König ret = IRQ_HANDLED; 1005f1f836e4SAlexander Stein } 1006f1f836e4SAlexander Stein 10079baedb7bSJohan Hovold spin_unlock(&sport->port.lock); 1008101aa46bSUwe Kleine-König 10094d845a62SUwe Kleine-König return ret; 1010ab4382d2SGreg Kroah-Hartman } 1011ab4382d2SGreg Kroah-Hartman 1012ab4382d2SGreg Kroah-Hartman /* 1013ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy. 1014ab4382d2SGreg Kroah-Hartman */ 10159d1a50a2SUwe Kleine-König static unsigned int imx_uart_tx_empty(struct uart_port *port) 1016ab4382d2SGreg Kroah-Hartman { 1017ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10181ce43e58SHuang Shijie unsigned int ret; 1019ab4382d2SGreg Kroah-Hartman 102027c84426SUwe Kleine-König ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 10211ce43e58SHuang Shijie 10221ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */ 1023686351f3SUwe Kleine-König if (sport->dma_is_txing) 10241ce43e58SHuang Shijie ret = 0; 10251ce43e58SHuang Shijie 10261ce43e58SHuang Shijie return ret; 1027ab4382d2SGreg Kroah-Hartman } 1028ab4382d2SGreg Kroah-Hartman 10296aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 10309d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_mctrl(struct uart_port *port) 103158362d5bSUwe Kleine-König { 103258362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 10339d1a50a2SUwe Kleine-König unsigned int ret = imx_uart_get_hwmctrl(sport); 103458362d5bSUwe Kleine-König 103558362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret); 103658362d5bSUwe Kleine-König 103758362d5bSUwe Kleine-König return ret; 103858362d5bSUwe Kleine-König } 103958362d5bSUwe Kleine-König 10406aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 10419d1a50a2SUwe Kleine-König static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1042ab4382d2SGreg Kroah-Hartman { 1043ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10444444dcf1SUwe Kleine-König u32 ucr3, uts; 1045ab4382d2SGreg Kroah-Hartman 104617b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) { 10474444dcf1SUwe Kleine-König u32 ucr2; 10484444dcf1SUwe Kleine-König 1049197540dcSSergey Organov /* 1050197540dcSSergey Organov * Turn off autoRTS if RTS is lowered and restore autoRTS 1051197540dcSSergey Organov * setting if RTS is raised. 1052197540dcSSergey Organov */ 10534444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 10544444dcf1SUwe Kleine-König ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 1055197540dcSSergey Organov if (mctrl & TIOCM_RTS) { 1056197540dcSSergey Organov ucr2 |= UCR2_CTS; 1057197540dcSSergey Organov /* 1058197540dcSSergey Organov * UCR2_IRTS is unset if and only if the port is 1059197540dcSSergey Organov * configured for CRTSCTS, so we use inverted UCR2_IRTS 1060197540dcSSergey Organov * to get the state to restore to. 1061197540dcSSergey Organov */ 1062197540dcSSergey Organov if (!(ucr2 & UCR2_IRTS)) 1063197540dcSSergey Organov ucr2 |= UCR2_CTSC; 1064197540dcSSergey Organov } 10654444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 106617b8f2a3SUwe Kleine-König } 10676b471a98SHuang Shijie 10684444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 106990ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR)) 10704444dcf1SUwe Kleine-König ucr3 |= UCR3_DSR; 10714444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 107290ebc483SUwe Kleine-König 10739d1a50a2SUwe Kleine-König uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 10746b471a98SHuang Shijie if (mctrl & TIOCM_LOOP) 10754444dcf1SUwe Kleine-König uts |= UTS_LOOP; 10769d1a50a2SUwe Kleine-König imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 107758362d5bSUwe Kleine-König 107858362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl); 1079ab4382d2SGreg Kroah-Hartman } 1080ab4382d2SGreg Kroah-Hartman 1081ab4382d2SGreg Kroah-Hartman /* 1082ab4382d2SGreg Kroah-Hartman * Interrupts always disabled. 1083ab4382d2SGreg Kroah-Hartman */ 10849d1a50a2SUwe Kleine-König static void imx_uart_break_ctl(struct uart_port *port, int break_state) 1085ab4382d2SGreg Kroah-Hartman { 1086ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 10874444dcf1SUwe Kleine-König unsigned long flags; 10884444dcf1SUwe Kleine-König u32 ucr1; 1089ab4382d2SGreg Kroah-Hartman 1090ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags); 1091ab4382d2SGreg Kroah-Hartman 10924444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1093ab4382d2SGreg Kroah-Hartman 1094ab4382d2SGreg Kroah-Hartman if (break_state != 0) 10954444dcf1SUwe Kleine-König ucr1 |= UCR1_SNDBRK; 1096ab4382d2SGreg Kroah-Hartman 10974444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1098ab4382d2SGreg Kroah-Hartman 1099ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1100ab4382d2SGreg Kroah-Hartman } 1101ab4382d2SGreg Kroah-Hartman 1102cc568849SUwe Kleine-König /* 1103cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the 1104cc568849SUwe Kleine-König * modem status signals. 1105cc568849SUwe Kleine-König */ 11069d1a50a2SUwe Kleine-König static void imx_uart_timeout(struct timer_list *t) 1107cc568849SUwe Kleine-König { 1108e99e88a9SKees Cook struct imx_port *sport = from_timer(sport, t, timer); 1109cc568849SUwe Kleine-König unsigned long flags; 1110cc568849SUwe Kleine-König 1111cc568849SUwe Kleine-König if (sport->port.state) { 1112cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 11139d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport); 1114cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 1115cc568849SUwe Kleine-König 1116cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1117cc568849SUwe Kleine-König } 1118cc568849SUwe Kleine-König } 1119cc568849SUwe Kleine-König 1120b4cdc8f6SHuang Shijie /* 1121905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1122b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full. 1123905c0decSLucas Stach * [2] the aging timer expires 1124b4cdc8f6SHuang Shijie * 1125905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO 1126905c0decSLucas Stach * for at least 8 byte durations. 1127b4cdc8f6SHuang Shijie */ 11289d1a50a2SUwe Kleine-König static void imx_uart_dma_rx_callback(void *data) 1129b4cdc8f6SHuang Shijie { 1130b4cdc8f6SHuang Shijie struct imx_port *sport = data; 1131b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1132b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 11337cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port; 1134b4cdc8f6SHuang Shijie struct dma_tx_state state; 11359d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring; 1136b4cdc8f6SHuang Shijie enum dma_status status; 11379d297239SNandor Han unsigned int w_bytes = 0; 11389d297239SNandor Han unsigned int r_bytes; 11399d297239SNandor Han unsigned int bd_size; 1140b4cdc8f6SHuang Shijie 1141fb7f1bf8SRobin Gong status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1142392bceedSPhilipp Zabel 11439d297239SNandor Han if (status == DMA_ERROR) { 11449d1a50a2SUwe Kleine-König imx_uart_clear_rx_errors(sport); 11459d297239SNandor Han return; 11469d297239SNandor Han } 1147b4cdc8f6SHuang Shijie 11489b289932SManfred Schlaegl if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1149976b39cdSLucas Stach 1150976b39cdSLucas Stach /* 11519d297239SNandor Han * The state-residue variable represents the empty space 11529d297239SNandor Han * relative to the entire buffer. Taking this in consideration 11539d297239SNandor Han * the head is always calculated base on the buffer total 11549d297239SNandor Han * length - DMA transaction residue. The UART script from the 11559d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor, 11569d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 11579d297239SNandor Han * Taking this in consideration the tail is always at the 11589d297239SNandor Han * beginning of the buffer descriptor that contains the head. 1159976b39cdSLucas Stach */ 11609d297239SNandor Han 11619d297239SNandor Han /* Calculate the head */ 11629d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue; 11639d297239SNandor Han 11649d297239SNandor Han /* Calculate the tail. */ 11659d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods; 11669d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 11679d297239SNandor Han 11689d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) && 11699d297239SNandor Han rx_ring->head > rx_ring->tail) { 11709d297239SNandor Han 11719d297239SNandor Han /* Move data from tail to head */ 11729d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail; 11739d297239SNandor Han 11749d297239SNandor Han /* CPU claims ownership of RX DMA buffer */ 11759d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 11769d297239SNandor Han DMA_FROM_DEVICE); 11779d297239SNandor Han 11789d297239SNandor Han w_bytes = tty_insert_flip_string(port, 11799d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes); 11809d297239SNandor Han 11819d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */ 11829d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1, 11839d297239SNandor Han DMA_FROM_DEVICE); 11849d297239SNandor Han 11859d297239SNandor Han if (w_bytes != r_bytes) 11869d297239SNandor Han sport->port.icount.buf_overrun++; 11879d297239SNandor Han 11889d297239SNandor Han sport->port.icount.rx += w_bytes; 11899d297239SNandor Han } else { 11909d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl)); 11919d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail); 1192ee5e7c10SRobin Gong } 11939d297239SNandor Han } 11949d297239SNandor Han 11959d297239SNandor Han if (w_bytes) { 11969d297239SNandor Han tty_flip_buffer_push(port); 11979d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 11989d297239SNandor Han } 11999d297239SNandor Han } 12009d297239SNandor Han 12019d1a50a2SUwe Kleine-König static int imx_uart_start_rx_dma(struct imx_port *sport) 1202b4cdc8f6SHuang Shijie { 1203b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl; 1204b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx; 1205b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1206b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc; 1207b4cdc8f6SHuang Shijie int ret; 1208b4cdc8f6SHuang Shijie 12099d297239SNandor Han sport->rx_ring.head = 0; 12109d297239SNandor Han sport->rx_ring.tail = 0; 12119d297239SNandor Han 1212db0a196bSFabien Lahoudere sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); 1213b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1214b4cdc8f6SHuang Shijie if (ret == 0) { 1215b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n"); 1216b4cdc8f6SHuang Shijie return -EINVAL; 1217b4cdc8f6SHuang Shijie } 12189d297239SNandor Han 12199d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 12209d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 12219d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 12229d297239SNandor Han 1223b4cdc8f6SHuang Shijie if (!desc) { 122424649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1225b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1226b4cdc8f6SHuang Shijie return -EINVAL; 1227b4cdc8f6SHuang Shijie } 12289d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_rx_callback; 1229b4cdc8f6SHuang Shijie desc->callback_param = sport; 1230b4cdc8f6SHuang Shijie 1231b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n"); 12324139fd76SRomain Perier sport->dma_is_rxing = 1; 12339d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc); 1234b4cdc8f6SHuang Shijie dma_async_issue_pending(chan); 1235b4cdc8f6SHuang Shijie return 0; 1236b4cdc8f6SHuang Shijie } 1237b4cdc8f6SHuang Shijie 12389d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport) 123941d98b5dSNandor Han { 124045ca673eSTroy Kisky struct tty_port *port = &sport->port.state->port; 12414444dcf1SUwe Kleine-König u32 usr1, usr2; 124241d98b5dSNandor Han 12434444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1); 12444444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2); 124541d98b5dSNandor Han 12464444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) { 124741d98b5dSNandor Han sport->port.icount.brk++; 124827c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2); 124945ca673eSTroy Kisky uart_handle_break(&sport->port); 125045ca673eSTroy Kisky if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 125145ca673eSTroy Kisky sport->port.icount.buf_overrun++; 125245ca673eSTroy Kisky tty_flip_buffer_push(port); 125345ca673eSTroy Kisky } else { 12544444dcf1SUwe Kleine-König if (usr1 & USR1_FRAMERR) { 125541d98b5dSNandor Han sport->port.icount.frame++; 125627c84426SUwe Kleine-König imx_uart_writel(sport, USR1_FRAMERR, USR1); 12574444dcf1SUwe Kleine-König } else if (usr1 & USR1_PARITYERR) { 125841d98b5dSNandor Han sport->port.icount.parity++; 125927c84426SUwe Kleine-König imx_uart_writel(sport, USR1_PARITYERR, USR1); 126041d98b5dSNandor Han } 126145ca673eSTroy Kisky } 126241d98b5dSNandor Han 12634444dcf1SUwe Kleine-König if (usr2 & USR2_ORE) { 126441d98b5dSNandor Han sport->port.icount.overrun++; 126527c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 126641d98b5dSNandor Han } 126741d98b5dSNandor Han 126841d98b5dSNandor Han } 126941d98b5dSNandor Han 1270cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */ 12717a637784STomasz Moń #define RXTL_DEFAULT 8 /* 8 characters or aging timer */ 1272184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */ 1273184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */ 1274cc32382dSLucas Stach 12759d1a50a2SUwe Kleine-König static void imx_uart_setup_ufcr(struct imx_port *sport, 1276cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl) 1277cc32382dSLucas Stach { 1278cc32382dSLucas Stach unsigned int val; 1279cc32382dSLucas Stach 1280cc32382dSLucas Stach /* set receiver / transmitter trigger level */ 128127c84426SUwe Kleine-König val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1282cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl; 128327c84426SUwe Kleine-König imx_uart_writel(sport, val, UFCR); 1284cc32382dSLucas Stach } 1285cc32382dSLucas Stach 1286b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport) 1287b4cdc8f6SHuang Shijie { 1288b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) { 1289e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 1290b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx); 1291b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL; 12929d297239SNandor Han sport->rx_cookie = -EINVAL; 1293b4cdc8f6SHuang Shijie kfree(sport->rx_buf); 1294b4cdc8f6SHuang Shijie sport->rx_buf = NULL; 1295b4cdc8f6SHuang Shijie } 1296b4cdc8f6SHuang Shijie 1297b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) { 1298e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 1299b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx); 1300b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL; 1301b4cdc8f6SHuang Shijie } 1302b4cdc8f6SHuang Shijie } 1303b4cdc8f6SHuang Shijie 1304b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport) 1305b4cdc8f6SHuang Shijie { 1306b09c74aeSHuang Shijie struct dma_slave_config slave_config = {}; 1307b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev; 1308b4cdc8f6SHuang Shijie int ret; 1309b4cdc8f6SHuang Shijie 1310b4cdc8f6SHuang Shijie /* Prepare for RX : */ 1311b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1312b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) { 1313b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n"); 1314b4cdc8f6SHuang Shijie ret = -EINVAL; 1315b4cdc8f6SHuang Shijie goto err; 1316b4cdc8f6SHuang Shijie } 1317b4cdc8f6SHuang Shijie 1318b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM; 1319b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0; 1320b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1321184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */ 1322184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1; 1323b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1324b4cdc8f6SHuang Shijie if (ret) { 1325b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n"); 1326b4cdc8f6SHuang Shijie goto err; 1327b4cdc8f6SHuang Shijie } 1328b4cdc8f6SHuang Shijie 1329db0a196bSFabien Lahoudere sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; 1330db0a196bSFabien Lahoudere sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); 1331b4cdc8f6SHuang Shijie if (!sport->rx_buf) { 1332b4cdc8f6SHuang Shijie ret = -ENOMEM; 1333b4cdc8f6SHuang Shijie goto err; 1334b4cdc8f6SHuang Shijie } 13359d297239SNandor Han sport->rx_ring.buf = sport->rx_buf; 1336b4cdc8f6SHuang Shijie 1337b4cdc8f6SHuang Shijie /* Prepare for TX : */ 1338b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1339b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) { 1340b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n"); 1341b4cdc8f6SHuang Shijie ret = -EINVAL; 1342b4cdc8f6SHuang Shijie goto err; 1343b4cdc8f6SHuang Shijie } 1344b4cdc8f6SHuang Shijie 1345b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV; 1346b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0; 1347b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1348184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA; 1349b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1350b4cdc8f6SHuang Shijie if (ret) { 1351b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration."); 1352b4cdc8f6SHuang Shijie goto err; 1353b4cdc8f6SHuang Shijie } 1354b4cdc8f6SHuang Shijie 1355b4cdc8f6SHuang Shijie return 0; 1356b4cdc8f6SHuang Shijie err: 1357b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1358b4cdc8f6SHuang Shijie return ret; 1359b4cdc8f6SHuang Shijie } 1360b4cdc8f6SHuang Shijie 13619d1a50a2SUwe Kleine-König static void imx_uart_enable_dma(struct imx_port *sport) 1362b4cdc8f6SHuang Shijie { 13634444dcf1SUwe Kleine-König u32 ucr1; 1364b4cdc8f6SHuang Shijie 13659d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 136602b0abd3SUwe Kleine-König 1367b4cdc8f6SHuang Shijie /* set UCR1 */ 13684444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 13694444dcf1SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 13704444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1371b4cdc8f6SHuang Shijie 1372b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1; 1373b4cdc8f6SHuang Shijie } 1374b4cdc8f6SHuang Shijie 13759d1a50a2SUwe Kleine-König static void imx_uart_disable_dma(struct imx_port *sport) 1376b4cdc8f6SHuang Shijie { 1377676a31d8SSebastian Reichel u32 ucr1; 1378b4cdc8f6SHuang Shijie 1379b4cdc8f6SHuang Shijie /* clear UCR1 */ 13804444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 13814444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 13824444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1383b4cdc8f6SHuang Shijie 13849d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1385184bd70bSLucas Stach 1386b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0; 1387b4cdc8f6SHuang Shijie } 1388b4cdc8f6SHuang Shijie 1389ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */ 1390ab4382d2SGreg Kroah-Hartman #define CTSTL 16 1391ab4382d2SGreg Kroah-Hartman 13929d1a50a2SUwe Kleine-König static int imx_uart_startup(struct uart_port *port) 1393ab4382d2SGreg Kroah-Hartman { 1394ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1395458e2c82SFabio Estevam int retval, i; 13964444dcf1SUwe Kleine-König unsigned long flags; 13974238c00bSUwe Kleine-König int dma_is_inited = 0; 13985a08a487SGeorge Hilliard u32 ucr1, ucr2, ucr3, ucr4; 1399ab4382d2SGreg Kroah-Hartman 140028eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per); 140128eb4274SHuang Shijie if (retval) 1402cb0f0a5fSFabio Estevam return retval; 140328eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 14040c375501SHuang Shijie if (retval) { 14050c375501SHuang Shijie clk_disable_unprepare(sport->clk_per); 1406cb0f0a5fSFabio Estevam return retval; 14070c375501SHuang Shijie } 140828eb4274SHuang Shijie 14099d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1410ab4382d2SGreg Kroah-Hartman 1411ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before 1412ab4382d2SGreg Kroah-Hartman * requesting IRQs 1413ab4382d2SGreg Kroah-Hartman */ 14144444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4); 1415ab4382d2SGreg Kroah-Hartman 1416ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */ 14174444dcf1SUwe Kleine-König ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 14184444dcf1SUwe Kleine-König ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1419ab4382d2SGreg Kroah-Hartman 14204444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1421ab4382d2SGreg Kroah-Hartman 14227e11577eSLucas Stach /* Can we enable the DMA support? */ 14234238c00bSUwe Kleine-König if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 14244238c00bSUwe Kleine-König dma_is_inited = 1; 14257e11577eSLucas Stach 142653794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 1427772f8991SHuang Shijie /* Reset fifo's and state machines */ 1428458e2c82SFabio Estevam i = 100; 1429458e2c82SFabio Estevam 14304444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 14314444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 14324444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1433458e2c82SFabio Estevam 143427c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1435458e2c82SFabio Estevam udelay(1); 1436ab4382d2SGreg Kroah-Hartman 1437ab4382d2SGreg Kroah-Hartman /* 1438ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts 1439ab4382d2SGreg Kroah-Hartman */ 144027c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 144127c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2); 1442ab4382d2SGreg Kroah-Hartman 14434444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 14444444dcf1SUwe Kleine-König ucr1 |= UCR1_UARTEN; 14456376cd39SNandor Han if (sport->have_rtscts) 14464444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 1447ab4382d2SGreg Kroah-Hartman 14484444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1449ab4382d2SGreg Kroah-Hartman 14505a08a487SGeorge Hilliard ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR); 14513ee82c6eSJohan Hovold if (!dma_is_inited) 14524444dcf1SUwe Kleine-König ucr4 |= UCR4_OREN; 14535a08a487SGeorge Hilliard if (sport->inverted_rx) 14545a08a487SGeorge Hilliard ucr4 |= UCR4_INVR; 14554444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4); 14566f026d6bSJiada Wang 14575a08a487SGeorge Hilliard ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT; 14585a08a487SGeorge Hilliard /* 14595a08a487SGeorge Hilliard * configure tx polarity before enabling tx 14605a08a487SGeorge Hilliard */ 14615a08a487SGeorge Hilliard if (sport->inverted_tx) 14625a08a487SGeorge Hilliard ucr3 |= UCR3_INVT; 14635a08a487SGeorge Hilliard 14645a08a487SGeorge Hilliard if (!imx_uart_is_imx1(sport)) { 14655a08a487SGeorge Hilliard ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 14665a08a487SGeorge Hilliard 14675a08a487SGeorge Hilliard if (sport->dte_mode) 14685a08a487SGeorge Hilliard /* disable broken interrupts */ 14695a08a487SGeorge Hilliard ucr3 &= ~(UCR3_RI | UCR3_DCD); 14705a08a487SGeorge Hilliard } 14715a08a487SGeorge Hilliard imx_uart_writel(sport, ucr3, UCR3); 14725a08a487SGeorge Hilliard 14734444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 14744444dcf1SUwe Kleine-König ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1475bff09b09SLucas Stach if (!sport->have_rtscts) 14764444dcf1SUwe Kleine-König ucr2 |= UCR2_IRTS; 147716804d68SUwe Kleine-König /* 147816804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled, 147916804d68SUwe Kleine-König * we're using RTSD instead. 148016804d68SUwe Kleine-König */ 14819d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 14824444dcf1SUwe Kleine-König ucr2 &= ~UCR2_RTSEN; 14834444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1484ab4382d2SGreg Kroah-Hartman 1485ab4382d2SGreg Kroah-Hartman /* 1486ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts 1487ab4382d2SGreg Kroah-Hartman */ 14889d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 148918a42088SPeter Senna Tschudin 149076821e22SUwe Kleine-König if (dma_is_inited) { 14919d1a50a2SUwe Kleine-König imx_uart_enable_dma(sport); 14929d1a50a2SUwe Kleine-König imx_uart_start_rx_dma(sport); 149376821e22SUwe Kleine-König } else { 149476821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 149576821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN; 149676821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 149781ca8e82SUwe Kleine-König 149881ca8e82SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 149981ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN; 150081ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 150176821e22SUwe Kleine-König } 150218a42088SPeter Senna Tschudin 1503ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1504ab4382d2SGreg Kroah-Hartman 1505ab4382d2SGreg Kroah-Hartman return 0; 1506ab4382d2SGreg Kroah-Hartman } 1507ab4382d2SGreg Kroah-Hartman 15089d1a50a2SUwe Kleine-König static void imx_uart_shutdown(struct uart_port *port) 1509ab4382d2SGreg Kroah-Hartman { 1510ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 15119ec1882dSXinyu Chen unsigned long flags; 1512339c7a87SSebastian Reichel u32 ucr1, ucr2, ucr4; 1513ab4382d2SGreg Kroah-Hartman 1514b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) { 1515e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx); 15167722c240SSebastian Reichel if (sport->dma_is_txing) { 15177722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 15187722c240SSebastian Reichel sport->dma_tx_nents, DMA_TO_DEVICE); 15197722c240SSebastian Reichel sport->dma_is_txing = 0; 15207722c240SSebastian Reichel } 1521e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx); 15227722c240SSebastian Reichel if (sport->dma_is_rxing) { 15237722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 15247722c240SSebastian Reichel 1, DMA_FROM_DEVICE); 15257722c240SSebastian Reichel sport->dma_is_rxing = 0; 15267722c240SSebastian Reichel } 15279d297239SNandor Han 152873631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags); 15299d1a50a2SUwe Kleine-König imx_uart_stop_tx(port); 15309d1a50a2SUwe Kleine-König imx_uart_stop_rx(port); 15319d1a50a2SUwe Kleine-König imx_uart_disable_dma(sport); 153273631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags); 1533b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport); 1534b4cdc8f6SHuang Shijie } 1535b4cdc8f6SHuang Shijie 153658362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios); 153758362d5bSUwe Kleine-König 15389ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 15394444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 15400fdf1787SSebastian Reichel ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 15414444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 15429ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 1543ab4382d2SGreg Kroah-Hartman 1544ab4382d2SGreg Kroah-Hartman /* 1545ab4382d2SGreg Kroah-Hartman * Stop our timer. 1546ab4382d2SGreg Kroah-Hartman */ 1547ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer); 1548ab4382d2SGreg Kroah-Hartman 1549ab4382d2SGreg Kroah-Hartman /* 1550ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition. 1551ab4382d2SGreg Kroah-Hartman */ 1552ab4382d2SGreg Kroah-Hartman 15539ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1554edd64f30SMatthias Schiffer 15554444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 1556c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 15574444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 1558edd64f30SMatthias Schiffer 1559edd64f30SMatthias Schiffer ucr4 = imx_uart_readl(sport, UCR4); 1560028e0838SFugang Duan ucr4 &= ~UCR4_TCEN; 1561edd64f30SMatthias Schiffer imx_uart_writel(sport, ucr4, UCR4); 1562edd64f30SMatthias Schiffer 15639ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 156428eb4274SHuang Shijie 156528eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per); 156628eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg); 1567ab4382d2SGreg Kroah-Hartman } 1568ab4382d2SGreg Kroah-Hartman 15696aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */ 15709d1a50a2SUwe Kleine-König static void imx_uart_flush_buffer(struct uart_port *port) 1571eb56b7edSHuang Shijie { 1572eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port; 157382e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0]; 15744444dcf1SUwe Kleine-König u32 ucr2; 15754f86a95dSFabio Estevam int i = 100, ubir, ubmr, uts; 1576eb56b7edSHuang Shijie 157782e86ae9SDirk Behme if (!sport->dma_chan_tx) 157882e86ae9SDirk Behme return; 157982e86ae9SDirk Behme 1580eb56b7edSHuang Shijie sport->tx_bytes = 0; 1581eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx); 158282e86ae9SDirk Behme if (sport->dma_is_txing) { 15834444dcf1SUwe Kleine-König u32 ucr1; 15844444dcf1SUwe Kleine-König 158582e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 158682e86ae9SDirk Behme DMA_TO_DEVICE); 15874444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 15884444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN; 15894444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 15900f7bdbd2SMartyn Welch sport->dma_is_txing = 0; 1591eb56b7edSHuang Shijie } 1592934084a9SFabio Estevam 1593934084a9SFabio Estevam /* 1594934084a9SFabio Estevam * According to the Reference Manual description of the UART SRST bit: 1595263763c1SMartyn Welch * 1596934084a9SFabio Estevam * "Reset the transmit and receive state machines, 1597934084a9SFabio Estevam * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1598263763c1SMartyn Welch * and UTS[6-3]". 1599263763c1SMartyn Welch * 1600263763c1SMartyn Welch * We don't need to restore the old values from USR1, USR2, URXD and 1601263763c1SMartyn Welch * UTXD. UBRC is read only, so only save/restore the other three 1602263763c1SMartyn Welch * registers. 1603934084a9SFabio Estevam */ 160427c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR); 160527c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR); 160627c84426SUwe Kleine-König uts = imx_uart_readl(sport, IMX21_UTS); 1607934084a9SFabio Estevam 16084444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 16094444dcf1SUwe Kleine-König ucr2 &= ~UCR2_SRST; 16104444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 1611934084a9SFabio Estevam 161227c84426SUwe Kleine-König while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1613934084a9SFabio Estevam udelay(1); 1614934084a9SFabio Estevam 1615934084a9SFabio Estevam /* Restore the registers */ 161627c84426SUwe Kleine-König imx_uart_writel(sport, ubir, UBIR); 161727c84426SUwe Kleine-König imx_uart_writel(sport, ubmr, UBMR); 161827c84426SUwe Kleine-König imx_uart_writel(sport, uts, IMX21_UTS); 1619eb56b7edSHuang Shijie } 1620eb56b7edSHuang Shijie 1621ab4382d2SGreg Kroah-Hartman static void 16229d1a50a2SUwe Kleine-König imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1623ab4382d2SGreg Kroah-Hartman struct ktermios *old) 1624ab4382d2SGreg Kroah-Hartman { 1625ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1626ab4382d2SGreg Kroah-Hartman unsigned long flags; 162785f30fbfSSergey Organov u32 ucr2, old_ucr2, ufcr; 162858362d5bSUwe Kleine-König unsigned int baud, quot; 1629ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 16304444dcf1SUwe Kleine-König unsigned long div; 1631d47bcb4aSSergey Organov unsigned long num, denom, old_ubir, old_ubmr; 1632ab4382d2SGreg Kroah-Hartman uint64_t tdiv64; 1633ab4382d2SGreg Kroah-Hartman 1634ab4382d2SGreg Kroah-Hartman /* 1635ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8. 1636ab4382d2SGreg Kroah-Hartman */ 1637ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 && 1638ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) { 1639ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE; 1640ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize; 1641ab4382d2SGreg Kroah-Hartman old_csize = CS8; 1642ab4382d2SGreg Kroah-Hartman } 1643ab4382d2SGreg Kroah-Hartman 16444e828c3eSSergey Organov del_timer_sync(&sport->timer); 16454e828c3eSSergey Organov 16464e828c3eSSergey Organov /* 16474e828c3eSSergey Organov * Ask the core to calculate the divisor for us. 16484e828c3eSSergey Organov */ 16494e828c3eSSergey Organov baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 16504e828c3eSSergey Organov quot = uart_get_divisor(port, baud); 16514e828c3eSSergey Organov 16524e828c3eSSergey Organov spin_lock_irqsave(&sport->port.lock, flags); 16534e828c3eSSergey Organov 1654011bd05dSSergey Organov /* 1655011bd05dSSergey Organov * Read current UCR2 and save it for future use, then clear all the bits 1656011bd05dSSergey Organov * except those we will or may need to preserve. 1657011bd05dSSergey Organov */ 1658011bd05dSSergey Organov old_ucr2 = imx_uart_readl(sport, UCR2); 1659011bd05dSSergey Organov ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS); 1660011bd05dSSergey Organov 1661011bd05dSSergey Organov ucr2 |= UCR2_SRST | UCR2_IRTS; 166241ffa48eSSergey Organov if ((termios->c_cflag & CSIZE) == CS8) 166341ffa48eSSergey Organov ucr2 |= UCR2_WS; 1664ab4382d2SGreg Kroah-Hartman 1665ddf89e75SSergey Organov if (!sport->have_rtscts) 1666ddf89e75SSergey Organov termios->c_cflag &= ~CRTSCTS; 166717b8f2a3SUwe Kleine-König 166812fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) { 166917b8f2a3SUwe Kleine-König /* 167017b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep 167117b8f2a3SUwe Kleine-König * it under manual control and keep transmitter 167217b8f2a3SUwe Kleine-König * disabled. 167317b8f2a3SUwe Kleine-König */ 167458362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 16759d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 16761a613626SFabio Estevam else 16779d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 167858362d5bSUwe Kleine-König 1679b777b5deSSergey Organov } else if (termios->c_cflag & CRTSCTS) { 1680b777b5deSSergey Organov /* 1681b777b5deSSergey Organov * Only let receiver control RTS output if we were not requested 1682b777b5deSSergey Organov * to have RTS inactive (which then should take precedence). 1683b777b5deSSergey Organov */ 1684b777b5deSSergey Organov if (ucr2 & UCR2_CTS) 1685b777b5deSSergey Organov ucr2 |= UCR2_CTSC; 1686b777b5deSSergey Organov } 1687ddf89e75SSergey Organov 1688ddf89e75SSergey Organov if (termios->c_cflag & CRTSCTS) 1689ddf89e75SSergey Organov ucr2 &= ~UCR2_IRTS; 1690ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB) 1691ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB; 1692ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) { 1693ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN; 1694ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD) 1695ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE; 1696ab4382d2SGreg Kroah-Hartman } 1697ab4382d2SGreg Kroah-Hartman 1698ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0; 1699ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK) 1700ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1701ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK)) 1702ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK; 1703ab4382d2SGreg Kroah-Hartman 1704ab4382d2SGreg Kroah-Hartman /* 1705ab4382d2SGreg Kroah-Hartman * Characters to ignore 1706ab4382d2SGreg Kroah-Hartman */ 1707ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0; 1708ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1709865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1710ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) { 1711ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK; 1712ab4382d2SGreg Kroah-Hartman /* 1713ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators, 1714ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support). 1715ab4382d2SGreg Kroah-Hartman */ 1716ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR) 1717ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN; 1718ab4382d2SGreg Kroah-Hartman } 1719ab4382d2SGreg Kroah-Hartman 172055d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0) 172155d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ; 172255d8693aSJiada Wang 1723ab4382d2SGreg Kroah-Hartman /* 1724ab4382d2SGreg Kroah-Hartman * Update the per-port timeout. 1725ab4382d2SGreg Kroah-Hartman */ 1726ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud); 1727ab4382d2SGreg Kroah-Hartman 172809bd00f6SHubert Feurstein /* custom-baudrate handling */ 172909bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16); 173009bd00f6SHubert Feurstein if (baud == 38400 && quot != div) 173109bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16); 173209bd00f6SHubert Feurstein 1733ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16); 1734ab4382d2SGreg Kroah-Hartman if (div > 7) 1735ab4382d2SGreg Kroah-Hartman div = 7; 1736ab4382d2SGreg Kroah-Hartman if (!div) 1737ab4382d2SGreg Kroah-Hartman div = 1; 1738ab4382d2SGreg Kroah-Hartman 1739ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk, 1740ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom); 1741ab4382d2SGreg Kroah-Hartman 1742ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk; 1743ab4382d2SGreg Kroah-Hartman tdiv64 *= num; 1744ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div); 1745ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios, 1746ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64); 1747ab4382d2SGreg Kroah-Hartman 1748ab4382d2SGreg Kroah-Hartman num -= 1; 1749ab4382d2SGreg Kroah-Hartman denom -= 1; 1750ab4382d2SGreg Kroah-Hartman 175127c84426SUwe Kleine-König ufcr = imx_uart_readl(sport, UFCR); 1752ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 175327c84426SUwe Kleine-König imx_uart_writel(sport, ufcr, UFCR); 1754ab4382d2SGreg Kroah-Hartman 1755d47bcb4aSSergey Organov /* 1756d47bcb4aSSergey Organov * Two registers below should always be written both and in this 1757d47bcb4aSSergey Organov * particular order. One consequence is that we need to check if any of 1758d47bcb4aSSergey Organov * them changes and then update both. We do need the check for change 1759d47bcb4aSSergey Organov * as even writing the same values seem to "restart" 1760d47bcb4aSSergey Organov * transmission/receiving logic in the hardware, that leads to data 1761d47bcb4aSSergey Organov * breakage even when rate doesn't in fact change. E.g., user switches 1762d47bcb4aSSergey Organov * RTS/CTS handshake and suddenly gets broken bytes. 1763d47bcb4aSSergey Organov */ 1764d47bcb4aSSergey Organov old_ubir = imx_uart_readl(sport, UBIR); 1765d47bcb4aSSergey Organov old_ubmr = imx_uart_readl(sport, UBMR); 1766d47bcb4aSSergey Organov if (old_ubir != num || old_ubmr != denom) { 176727c84426SUwe Kleine-König imx_uart_writel(sport, num, UBIR); 176827c84426SUwe Kleine-König imx_uart_writel(sport, denom, UBMR); 1769d47bcb4aSSergey Organov } 1770ab4382d2SGreg Kroah-Hartman 17719d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 177227c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.uartclk / div / 1000, 177327c84426SUwe Kleine-König IMX21_ONEMS); 1774ab4382d2SGreg Kroah-Hartman 1775011bd05dSSergey Organov imx_uart_writel(sport, ucr2, UCR2); 1776ab4382d2SGreg Kroah-Hartman 1777ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 17789d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port); 1779ab4382d2SGreg Kroah-Hartman 1780ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags); 1781ab4382d2SGreg Kroah-Hartman } 1782ab4382d2SGreg Kroah-Hartman 17839d1a50a2SUwe Kleine-König static const char *imx_uart_type(struct uart_port *port) 1784ab4382d2SGreg Kroah-Hartman { 1785ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1786ab4382d2SGreg Kroah-Hartman 1787ab4382d2SGreg Kroah-Hartman return sport->port.type == PORT_IMX ? "IMX" : NULL; 1788ab4382d2SGreg Kroah-Hartman } 1789ab4382d2SGreg Kroah-Hartman 1790ab4382d2SGreg Kroah-Hartman /* 1791ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port. 1792ab4382d2SGreg Kroah-Hartman */ 17939d1a50a2SUwe Kleine-König static void imx_uart_config_port(struct uart_port *port, int flags) 1794ab4382d2SGreg Kroah-Hartman { 1795ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1796ab4382d2SGreg Kroah-Hartman 1797da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE) 1798ab4382d2SGreg Kroah-Hartman sport->port.type = PORT_IMX; 1799ab4382d2SGreg Kroah-Hartman } 1800ab4382d2SGreg Kroah-Hartman 1801ab4382d2SGreg Kroah-Hartman /* 1802ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL). 1803ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and 1804ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN 1805ab4382d2SGreg Kroah-Hartman */ 1806ab4382d2SGreg Kroah-Hartman static int 18079d1a50a2SUwe Kleine-König imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1808ab4382d2SGreg Kroah-Hartman { 1809ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1810ab4382d2SGreg Kroah-Hartman int ret = 0; 1811ab4382d2SGreg Kroah-Hartman 1812ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1813ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1814ab4382d2SGreg Kroah-Hartman if (sport->port.irq != ser->irq) 1815ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1816ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM) 1817ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1818ab4382d2SGreg Kroah-Hartman if (sport->port.uartclk / 16 != ser->baud_base) 1819ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1820a50c44ceSOlof Johansson if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1821ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1822ab4382d2SGreg Kroah-Hartman if (sport->port.iobase != ser->port) 1823ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1824ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0) 1825ab4382d2SGreg Kroah-Hartman ret = -EINVAL; 1826ab4382d2SGreg Kroah-Hartman return ret; 1827ab4382d2SGreg Kroah-Hartman } 1828ab4382d2SGreg Kroah-Hartman 182901f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 18306b8bdad9SDaniel Thompson 18319d1a50a2SUwe Kleine-König static int imx_uart_poll_init(struct uart_port *port) 18326b8bdad9SDaniel Thompson { 18336b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port; 18346b8bdad9SDaniel Thompson unsigned long flags; 18354444dcf1SUwe Kleine-König u32 ucr1, ucr2; 18366b8bdad9SDaniel Thompson int retval; 18376b8bdad9SDaniel Thompson 18386b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg); 18396b8bdad9SDaniel Thompson if (retval) 18406b8bdad9SDaniel Thompson return retval; 18416b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per); 18426b8bdad9SDaniel Thompson if (retval) 18436b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg); 18446b8bdad9SDaniel Thompson 18459d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 18466b8bdad9SDaniel Thompson 18476b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags); 18486b8bdad9SDaniel Thompson 184976821e22SUwe Kleine-König /* 185076821e22SUwe Kleine-König * Be careful about the order of enabling bits here. First enable the 185176821e22SUwe Kleine-König * receiver (UARTEN + RXEN) and only then the corresponding irqs. 185276821e22SUwe Kleine-König * This prevents that a character that already sits in the RX fifo is 185376821e22SUwe Kleine-König * triggering an irq but the try to fetch it from there results in an 185476821e22SUwe Kleine-König * exception because UARTEN or RXEN is still off. 185576821e22SUwe Kleine-König */ 18564444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 185776821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 185876821e22SUwe Kleine-König 18599d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 18604444dcf1SUwe Kleine-König ucr1 |= IMX1_UCR1_UARTCLKEN; 18616b8bdad9SDaniel Thompson 186276821e22SUwe Kleine-König ucr1 |= UCR1_UARTEN; 1863c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); 186476821e22SUwe Kleine-König 1865aef1b6a2SMingrui Ren ucr2 |= UCR2_RXEN | UCR2_TXEN; 186681ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN; 186776821e22SUwe Kleine-König 186876821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 18694444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 18706b8bdad9SDaniel Thompson 187176821e22SUwe Kleine-König /* now enable irqs */ 187276821e22SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 187381ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 187476821e22SUwe Kleine-König 18756b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags); 18766b8bdad9SDaniel Thompson 18776b8bdad9SDaniel Thompson return 0; 18786b8bdad9SDaniel Thompson } 18796b8bdad9SDaniel Thompson 18809d1a50a2SUwe Kleine-König static int imx_uart_poll_get_char(struct uart_port *port) 188101f56abdSSaleem Abdulrasool { 188227c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 188327c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 188426c47412SDirk Behme return NO_POLL_CHAR; 188501f56abdSSaleem Abdulrasool 188627c84426SUwe Kleine-König return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 188701f56abdSSaleem Abdulrasool } 188801f56abdSSaleem Abdulrasool 18899d1a50a2SUwe Kleine-König static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 189001f56abdSSaleem Abdulrasool { 189127c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 189201f56abdSSaleem Abdulrasool unsigned int status; 189301f56abdSSaleem Abdulrasool 189401f56abdSSaleem Abdulrasool /* drain */ 189501f56abdSSaleem Abdulrasool do { 189627c84426SUwe Kleine-König status = imx_uart_readl(sport, USR1); 189701f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY); 189801f56abdSSaleem Abdulrasool 189901f56abdSSaleem Abdulrasool /* write */ 190027c84426SUwe Kleine-König imx_uart_writel(sport, c, URTX0); 190101f56abdSSaleem Abdulrasool 190201f56abdSSaleem Abdulrasool /* flush */ 190301f56abdSSaleem Abdulrasool do { 190427c84426SUwe Kleine-König status = imx_uart_readl(sport, USR2); 190501f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC); 190601f56abdSSaleem Abdulrasool } 190701f56abdSSaleem Abdulrasool #endif 190801f56abdSSaleem Abdulrasool 19096aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off or from .probe without locking */ 19109d1a50a2SUwe Kleine-König static int imx_uart_rs485_config(struct uart_port *port, 191117b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf) 191217b8f2a3SUwe Kleine-König { 191317b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port; 19144444dcf1SUwe Kleine-König u32 ucr2; 191517b8f2a3SUwe Kleine-König 191617b8f2a3SUwe Kleine-König /* RTS is required to control the transmitter */ 19177b7e8e8eSFabio Estevam if (!sport->have_rtscts && !sport->have_rtsgpio) 191817b8f2a3SUwe Kleine-König rs485conf->flags &= ~SER_RS485_ENABLED; 191917b8f2a3SUwe Kleine-König 192017b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) { 19216d215f83SStefan Agner /* Enable receiver if low-active RTS signal is requested */ 19226d215f83SStefan Agner if (sport->have_rtscts && !sport->have_rtsgpio && 19236d215f83SStefan Agner !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 19246d215f83SStefan Agner rs485conf->flags |= SER_RS485_RX_DURING_TX; 19256d215f83SStefan Agner 192617b8f2a3SUwe Kleine-König /* disable transmitter */ 19274444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 192817b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 19299d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2); 19301a613626SFabio Estevam else 19319d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2); 19324444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2); 193317b8f2a3SUwe Kleine-König } 193417b8f2a3SUwe Kleine-König 19357d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 19367d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) || 193776821e22SUwe Kleine-König rs485conf->flags & SER_RS485_RX_DURING_TX) 19389d1a50a2SUwe Kleine-König imx_uart_start_rx(port); 19397d1cadcaSBaruch Siach 194017b8f2a3SUwe Kleine-König return 0; 194117b8f2a3SUwe Kleine-König } 194217b8f2a3SUwe Kleine-König 19439d1a50a2SUwe Kleine-König static const struct uart_ops imx_uart_pops = { 19449d1a50a2SUwe Kleine-König .tx_empty = imx_uart_tx_empty, 19459d1a50a2SUwe Kleine-König .set_mctrl = imx_uart_set_mctrl, 19469d1a50a2SUwe Kleine-König .get_mctrl = imx_uart_get_mctrl, 19479d1a50a2SUwe Kleine-König .stop_tx = imx_uart_stop_tx, 19489d1a50a2SUwe Kleine-König .start_tx = imx_uart_start_tx, 19499d1a50a2SUwe Kleine-König .stop_rx = imx_uart_stop_rx, 19509d1a50a2SUwe Kleine-König .enable_ms = imx_uart_enable_ms, 19519d1a50a2SUwe Kleine-König .break_ctl = imx_uart_break_ctl, 19529d1a50a2SUwe Kleine-König .startup = imx_uart_startup, 19539d1a50a2SUwe Kleine-König .shutdown = imx_uart_shutdown, 19549d1a50a2SUwe Kleine-König .flush_buffer = imx_uart_flush_buffer, 19559d1a50a2SUwe Kleine-König .set_termios = imx_uart_set_termios, 19569d1a50a2SUwe Kleine-König .type = imx_uart_type, 19579d1a50a2SUwe Kleine-König .config_port = imx_uart_config_port, 19589d1a50a2SUwe Kleine-König .verify_port = imx_uart_verify_port, 195901f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL) 19609d1a50a2SUwe Kleine-König .poll_init = imx_uart_poll_init, 19619d1a50a2SUwe Kleine-König .poll_get_char = imx_uart_poll_get_char, 19629d1a50a2SUwe Kleine-König .poll_put_char = imx_uart_poll_put_char, 196301f56abdSSaleem Abdulrasool #endif 1964ab4382d2SGreg Kroah-Hartman }; 1965ab4382d2SGreg Kroah-Hartman 19669d1a50a2SUwe Kleine-König static struct imx_port *imx_uart_ports[UART_NR]; 1967ab4382d2SGreg Kroah-Hartman 19680db4f9b9SFugang Duan #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 19693f8bab17SJiri Slaby static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch) 1970ab4382d2SGreg Kroah-Hartman { 1971ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port; 1972ab4382d2SGreg Kroah-Hartman 19739d1a50a2SUwe Kleine-König while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1974ab4382d2SGreg Kroah-Hartman barrier(); 1975ab4382d2SGreg Kroah-Hartman 197627c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0); 1977ab4382d2SGreg Kroah-Hartman } 1978ab4382d2SGreg Kroah-Hartman 1979ab4382d2SGreg Kroah-Hartman /* 1980ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering 1981ab4382d2SGreg Kroah-Hartman */ 1982ab4382d2SGreg Kroah-Hartman static void 19839d1a50a2SUwe Kleine-König imx_uart_console_write(struct console *co, const char *s, unsigned int count) 1984ab4382d2SGreg Kroah-Hartman { 19859d1a50a2SUwe Kleine-König struct imx_port *sport = imx_uart_ports[co->index]; 19860ad5a814SDirk Behme struct imx_port_ucrs old_ucr; 198718ee37e1SJohan Hovold unsigned long flags; 19880ad5a814SDirk Behme unsigned int ucr1; 1989677fe555SThomas Gleixner int locked = 1; 19909ec1882dSXinyu Chen 1991677fe555SThomas Gleixner if (sport->port.sysrq) 1992677fe555SThomas Gleixner locked = 0; 1993677fe555SThomas Gleixner else if (oops_in_progress) 1994677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags); 1995677fe555SThomas Gleixner else 19969ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags); 1997ab4382d2SGreg Kroah-Hartman 1998ab4382d2SGreg Kroah-Hartman /* 19990ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts 2000ab4382d2SGreg Kroah-Hartman */ 20019d1a50a2SUwe Kleine-König imx_uart_ucrs_save(sport, &old_ucr); 20020ad5a814SDirk Behme ucr1 = old_ucr.ucr1; 2003ab4382d2SGreg Kroah-Hartman 20049d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport)) 2005fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN; 2006ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN; 2007c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); 2008ab4382d2SGreg Kroah-Hartman 200927c84426SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2010ab4382d2SGreg Kroah-Hartman 201127c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 2012ab4382d2SGreg Kroah-Hartman 20139d1a50a2SUwe Kleine-König uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 2014ab4382d2SGreg Kroah-Hartman 2015ab4382d2SGreg Kroah-Hartman /* 2016ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty 20170ad5a814SDirk Behme * and restore UCR1/2/3 2018ab4382d2SGreg Kroah-Hartman */ 201927c84426SUwe Kleine-König while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 2020ab4382d2SGreg Kroah-Hartman 20219d1a50a2SUwe Kleine-König imx_uart_ucrs_restore(sport, &old_ucr); 20229ec1882dSXinyu Chen 2023677fe555SThomas Gleixner if (locked) 20249ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags); 2025ab4382d2SGreg Kroah-Hartman } 2026ab4382d2SGreg Kroah-Hartman 2027ab4382d2SGreg Kroah-Hartman /* 2028ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader), 2029ab4382d2SGreg Kroah-Hartman * try to determine the current setup. 2030ab4382d2SGreg Kroah-Hartman */ 20316d0d1b5aSStefan Agner static void 20329d1a50a2SUwe Kleine-König imx_uart_console_get_options(struct imx_port *sport, int *baud, 2033ab4382d2SGreg Kroah-Hartman int *parity, int *bits) 2034ab4382d2SGreg Kroah-Hartman { 2035ab4382d2SGreg Kroah-Hartman 203627c84426SUwe Kleine-König if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 2037ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */ 2038ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk; 2039ab4382d2SGreg Kroah-Hartman unsigned int baud_raw; 2040ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv; 2041ab4382d2SGreg Kroah-Hartman 204227c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2); 2043ab4382d2SGreg Kroah-Hartman 2044ab4382d2SGreg Kroah-Hartman *parity = 'n'; 2045ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) { 2046ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE) 2047ab4382d2SGreg Kroah-Hartman *parity = 'o'; 2048ab4382d2SGreg Kroah-Hartman else 2049ab4382d2SGreg Kroah-Hartman *parity = 'e'; 2050ab4382d2SGreg Kroah-Hartman } 2051ab4382d2SGreg Kroah-Hartman 2052ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS) 2053ab4382d2SGreg Kroah-Hartman *bits = 8; 2054ab4382d2SGreg Kroah-Hartman else 2055ab4382d2SGreg Kroah-Hartman *bits = 7; 2056ab4382d2SGreg Kroah-Hartman 205727c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR) & 0xffff; 205827c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 2059ab4382d2SGreg Kroah-Hartman 206027c84426SUwe Kleine-König ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 2061ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6) 2062ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7; 2063ab4382d2SGreg Kroah-Hartman else 2064ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv; 2065ab4382d2SGreg Kroah-Hartman 20663a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per); 2067ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv; 2068ab4382d2SGreg Kroah-Hartman 2069ab4382d2SGreg Kroah-Hartman { /* 2070ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of 2071ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2072ab4382d2SGreg Kroah-Hartman * without need of float support or long long division, 2073ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow 2074ab4382d2SGreg Kroah-Hartman */ 2075ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1; 2076ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1); 2077ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div; 2078ab4382d2SGreg Kroah-Hartman 2079ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul; 2080ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div; 2081ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100; 2082ab4382d2SGreg Kroah-Hartman } 2083ab4382d2SGreg Kroah-Hartman 2084ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw) 2085f5a9e5f7SFabio Estevam dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", 2086ab4382d2SGreg Kroah-Hartman baud_raw, *baud); 2087ab4382d2SGreg Kroah-Hartman } 2088ab4382d2SGreg Kroah-Hartman } 2089ab4382d2SGreg Kroah-Hartman 20906d0d1b5aSStefan Agner static int 20919d1a50a2SUwe Kleine-König imx_uart_console_setup(struct console *co, char *options) 2092ab4382d2SGreg Kroah-Hartman { 2093ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2094ab4382d2SGreg Kroah-Hartman int baud = 9600; 2095ab4382d2SGreg Kroah-Hartman int bits = 8; 2096ab4382d2SGreg Kroah-Hartman int parity = 'n'; 2097ab4382d2SGreg Kroah-Hartman int flow = 'n'; 20981cf93e0dSHuang Shijie int retval; 2099ab4382d2SGreg Kroah-Hartman 2100ab4382d2SGreg Kroah-Hartman /* 2101ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and 2102ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have 2103ab4382d2SGreg Kroah-Hartman * console support. 2104ab4382d2SGreg Kroah-Hartman */ 21059d1a50a2SUwe Kleine-König if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2106ab4382d2SGreg Kroah-Hartman co->index = 0; 21079d1a50a2SUwe Kleine-König sport = imx_uart_ports[co->index]; 2108ab4382d2SGreg Kroah-Hartman if (sport == NULL) 2109ab4382d2SGreg Kroah-Hartman return -ENODEV; 2110ab4382d2SGreg Kroah-Hartman 21111cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */ 21121cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg); 21131cf93e0dSHuang Shijie if (retval) 21141cf93e0dSHuang Shijie goto error_console; 21151cf93e0dSHuang Shijie 2116ab4382d2SGreg Kroah-Hartman if (options) 2117ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow); 2118ab4382d2SGreg Kroah-Hartman else 21199d1a50a2SUwe Kleine-König imx_uart_console_get_options(sport, &baud, &parity, &bits); 2120ab4382d2SGreg Kroah-Hartman 21219d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2122ab4382d2SGreg Kroah-Hartman 21231cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 21241cf93e0dSHuang Shijie 21250c727a42SFabio Estevam if (retval) { 2126e67c139cSFugang Duan clk_disable_unprepare(sport->clk_ipg); 21270c727a42SFabio Estevam goto error_console; 21280c727a42SFabio Estevam } 21290c727a42SFabio Estevam 2130e67c139cSFugang Duan retval = clk_prepare_enable(sport->clk_per); 21310c727a42SFabio Estevam if (retval) 2132e67c139cSFugang Duan clk_disable_unprepare(sport->clk_ipg); 21331cf93e0dSHuang Shijie 21341cf93e0dSHuang Shijie error_console: 21351cf93e0dSHuang Shijie return retval; 2136ab4382d2SGreg Kroah-Hartman } 2137ab4382d2SGreg Kroah-Hartman 21389768a37cSFrancesco Dolcini static int 21399768a37cSFrancesco Dolcini imx_uart_console_exit(struct console *co) 21409768a37cSFrancesco Dolcini { 21419768a37cSFrancesco Dolcini struct imx_port *sport = imx_uart_ports[co->index]; 21429768a37cSFrancesco Dolcini 21439768a37cSFrancesco Dolcini clk_disable_unprepare(sport->clk_per); 21449768a37cSFrancesco Dolcini clk_disable_unprepare(sport->clk_ipg); 21459768a37cSFrancesco Dolcini 21469768a37cSFrancesco Dolcini return 0; 21479768a37cSFrancesco Dolcini } 21489768a37cSFrancesco Dolcini 21499d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver; 21509d1a50a2SUwe Kleine-König static struct console imx_uart_console = { 2151ab4382d2SGreg Kroah-Hartman .name = DEV_NAME, 21529d1a50a2SUwe Kleine-König .write = imx_uart_console_write, 2153ab4382d2SGreg Kroah-Hartman .device = uart_console_device, 21549d1a50a2SUwe Kleine-König .setup = imx_uart_console_setup, 21559768a37cSFrancesco Dolcini .exit = imx_uart_console_exit, 2156ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER, 2157ab4382d2SGreg Kroah-Hartman .index = -1, 21589d1a50a2SUwe Kleine-König .data = &imx_uart_uart_driver, 2159ab4382d2SGreg Kroah-Hartman }; 2160ab4382d2SGreg Kroah-Hartman 21619d1a50a2SUwe Kleine-König #define IMX_CONSOLE &imx_uart_console 2162913c6c0eSLucas Stach 2163ab4382d2SGreg Kroah-Hartman #else 2164ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL 2165ab4382d2SGreg Kroah-Hartman #endif 2166ab4382d2SGreg Kroah-Hartman 21679d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver = { 2168ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE, 2169ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME, 2170ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME, 2171ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR, 2172ab4382d2SGreg Kroah-Hartman .minor = MINOR_START, 21739d1a50a2SUwe Kleine-König .nr = ARRAY_SIZE(imx_uart_ports), 2174ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE, 2175ab4382d2SGreg Kroah-Hartman }; 2176ab4382d2SGreg Kroah-Hartman 2177bd78ecd6SAhmad Fatoum static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t) 2178cb1a6092SUwe Kleine-König { 2179bd78ecd6SAhmad Fatoum struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx); 2180cb1a6092SUwe Kleine-König unsigned long flags; 2181cb1a6092SUwe Kleine-König 2182cb1a6092SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 2183cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_RTS) 2184cb1a6092SUwe Kleine-König imx_uart_start_tx(&sport->port); 2185cb1a6092SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 2186bd78ecd6SAhmad Fatoum 2187bd78ecd6SAhmad Fatoum return HRTIMER_NORESTART; 2188cb1a6092SUwe Kleine-König } 2189cb1a6092SUwe Kleine-König 2190bd78ecd6SAhmad Fatoum static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t) 2191cb1a6092SUwe Kleine-König { 2192bd78ecd6SAhmad Fatoum struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx); 2193cb1a6092SUwe Kleine-König unsigned long flags; 2194cb1a6092SUwe Kleine-König 2195cb1a6092SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags); 2196cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_SEND) 2197cb1a6092SUwe Kleine-König imx_uart_stop_tx(&sport->port); 2198cb1a6092SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags); 2199bd78ecd6SAhmad Fatoum 2200bd78ecd6SAhmad Fatoum return HRTIMER_NORESTART; 2201cb1a6092SUwe Kleine-König } 2202cb1a6092SUwe Kleine-König 2203*00d7a00eSIlpo Järvinen static const struct serial_rs485 imx_no_rs485 = {}; /* No RS485 if no RTS */ 2204*00d7a00eSIlpo Järvinen static const struct serial_rs485 imx_rs485_supported = { 2205*00d7a00eSIlpo Järvinen .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | 2206*00d7a00eSIlpo Järvinen SER_RS485_RX_DURING_TX, 2207*00d7a00eSIlpo Järvinen .delay_rts_before_send = 1, 2208*00d7a00eSIlpo Järvinen .delay_rts_after_send = 1, 2209*00d7a00eSIlpo Järvinen }; 2210*00d7a00eSIlpo Järvinen 2211db0a196bSFabien Lahoudere /* Default RX DMA buffer configuration */ 2212db0a196bSFabien Lahoudere #define RX_DMA_PERIODS 16 2213db0a196bSFabien Lahoudere #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4) 2214db0a196bSFabien Lahoudere 22159d1a50a2SUwe Kleine-König static int imx_uart_probe(struct platform_device *pdev) 2216ab4382d2SGreg Kroah-Hartman { 22174661f46eSFabio Estevam struct device_node *np = pdev->dev.of_node; 2218ab4382d2SGreg Kroah-Hartman struct imx_port *sport; 2219ab4382d2SGreg Kroah-Hartman void __iomem *base; 2220db0a196bSFabien Lahoudere u32 dma_buf_conf[2]; 22214444dcf1SUwe Kleine-König int ret = 0; 22224444dcf1SUwe Kleine-König u32 ucr1; 2223ab4382d2SGreg Kroah-Hartman struct resource *res; 2224842633bdSUwe Kleine-König int txirq, rxirq, rtsirq; 2225ab4382d2SGreg Kroah-Hartman 222642d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2227ab4382d2SGreg Kroah-Hartman if (!sport) 2228ab4382d2SGreg Kroah-Hartman return -ENOMEM; 2229ab4382d2SGreg Kroah-Hartman 22304661f46eSFabio Estevam sport->devdata = of_device_get_match_data(&pdev->dev); 22314661f46eSFabio Estevam 22324661f46eSFabio Estevam ret = of_alias_get_id(np, "serial"); 22334661f46eSFabio Estevam if (ret < 0) { 22344661f46eSFabio Estevam dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 223542d34191SSachin Kamat return ret; 22364661f46eSFabio Estevam } 22374661f46eSFabio Estevam sport->port.line = ret; 22384661f46eSFabio Estevam 22394661f46eSFabio Estevam if (of_get_property(np, "uart-has-rtscts", NULL) || 22404661f46eSFabio Estevam of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 22414661f46eSFabio Estevam sport->have_rtscts = 1; 22424661f46eSFabio Estevam 22434661f46eSFabio Estevam if (of_get_property(np, "fsl,dte-mode", NULL)) 22444661f46eSFabio Estevam sport->dte_mode = 1; 22454661f46eSFabio Estevam 22464661f46eSFabio Estevam if (of_get_property(np, "rts-gpios", NULL)) 22474661f46eSFabio Estevam sport->have_rtsgpio = 1; 22484661f46eSFabio Estevam 22494661f46eSFabio Estevam if (of_get_property(np, "fsl,inverted-tx", NULL)) 22504661f46eSFabio Estevam sport->inverted_tx = 1; 22514661f46eSFabio Estevam 22524661f46eSFabio Estevam if (of_get_property(np, "fsl,inverted-rx", NULL)) 22534661f46eSFabio Estevam sport->inverted_rx = 1; 225422698aa2SShawn Guo 2255db0a196bSFabien Lahoudere if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) { 2256db0a196bSFabien Lahoudere sport->rx_period_length = dma_buf_conf[0]; 2257db0a196bSFabien Lahoudere sport->rx_periods = dma_buf_conf[1]; 2258db0a196bSFabien Lahoudere } else { 2259db0a196bSFabien Lahoudere sport->rx_period_length = RX_DMA_PERIOD_LEN; 2260db0a196bSFabien Lahoudere sport->rx_periods = RX_DMA_PERIODS; 2261db0a196bSFabien Lahoudere } 2262db0a196bSFabien Lahoudere 22639d1a50a2SUwe Kleine-König if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 226456734448SGeert Uytterhoeven dev_err(&pdev->dev, "serial%d out of range\n", 226556734448SGeert Uytterhoeven sport->port.line); 226656734448SGeert Uytterhoeven return -EINVAL; 226756734448SGeert Uytterhoeven } 226856734448SGeert Uytterhoeven 2269ab4382d2SGreg Kroah-Hartman res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2270da82f997SAlexander Shiyan base = devm_ioremap_resource(&pdev->dev, res); 2271da82f997SAlexander Shiyan if (IS_ERR(base)) 2272da82f997SAlexander Shiyan return PTR_ERR(base); 2273ab4382d2SGreg Kroah-Hartman 2274842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0); 2275aa49d8e8SAnson Huang if (rxirq < 0) 2276aa49d8e8SAnson Huang return rxirq; 227731a8d8faSAnson Huang txirq = platform_get_irq_optional(pdev, 1); 227831a8d8faSAnson Huang rtsirq = platform_get_irq_optional(pdev, 2); 2279842633bdSUwe Kleine-König 2280ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev; 2281ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start; 2282ab4382d2SGreg Kroah-Hartman sport->port.membase = base; 22835b109564SZheng Yongjun sport->port.type = PORT_IMX; 2284ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM; 2285842633bdSUwe Kleine-König sport->port.irq = rxirq; 2286ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32; 2287aa3479d2SDmitry Safonov sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); 22889d1a50a2SUwe Kleine-König sport->port.ops = &imx_uart_pops; 22899d1a50a2SUwe Kleine-König sport->port.rs485_config = imx_uart_rs485_config; 2290*00d7a00eSIlpo Järvinen /* RTS is required to control the RS485 transmitter */ 2291*00d7a00eSIlpo Järvinen if (sport->have_rtscts || sport->have_rtsgpio) 2292*00d7a00eSIlpo Järvinen sport->port.rs485_supported = &imx_rs485_supported; 2293*00d7a00eSIlpo Järvinen else 2294*00d7a00eSIlpo Järvinen sport->port.rs485_supported = &imx_no_rs485; 2295ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF; 22969d1a50a2SUwe Kleine-König timer_setup(&sport->timer, imx_uart_timeout, 0); 2297ab4382d2SGreg Kroah-Hartman 229858362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0); 229958362d5bSUwe Kleine-König if (IS_ERR(sport->gpios)) 230058362d5bSUwe Kleine-König return PTR_ERR(sport->gpios); 230158362d5bSUwe Kleine-König 23023a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 23033a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) { 23043a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg); 2305833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 230642d34191SSachin Kamat return ret; 2307ab4382d2SGreg Kroah-Hartman } 2308ab4382d2SGreg Kroah-Hartman 23093a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per"); 23103a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) { 23113a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per); 2312833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 231342d34191SSachin Kamat return ret; 23143a9465faSSascha Hauer } 23153a9465faSSascha Hauer 23163a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per); 2317ab4382d2SGreg Kroah-Hartman 23188a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */ 23198a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg); 23201e512d45SUwe Kleine-König if (ret) { 23211e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 23228a61f0c7SFabio Estevam return ret; 23231e512d45SUwe Kleine-König } 23248a61f0c7SFabio Estevam 23253a0ab62fSUwe Kleine-König /* initialize shadow register values */ 23263a0ab62fSUwe Kleine-König sport->ucr1 = readl(sport->port.membase + UCR1); 23273a0ab62fSUwe Kleine-König sport->ucr2 = readl(sport->port.membase + UCR2); 23283a0ab62fSUwe Kleine-König sport->ucr3 = readl(sport->port.membase + UCR3); 23293a0ab62fSUwe Kleine-König sport->ucr4 = readl(sport->port.membase + UCR4); 23303a0ab62fSUwe Kleine-König sport->ufcr = readl(sport->port.membase + UFCR); 23313a0ab62fSUwe Kleine-König 2332c150c0f3SLukas Wunner ret = uart_get_rs485_mode(&sport->port); 2333c150c0f3SLukas Wunner if (ret) { 2334c150c0f3SLukas Wunner clk_disable_unprepare(sport->clk_ipg); 2335c150c0f3SLukas Wunner return ret; 2336c150c0f3SLukas Wunner } 2337743f93f8SLukas Wunner 2338b8f3bff0SLukas Wunner if (sport->port.rs485.flags & SER_RS485_ENABLED && 23395d7f77ecSphil eichinger (!sport->have_rtscts && !sport->have_rtsgpio)) 2340b8f3bff0SLukas Wunner dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2341b8f3bff0SLukas Wunner 23426d215f83SStefan Agner /* 23436d215f83SStefan Agner * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 23446d215f83SStefan Agner * signal cannot be set low during transmission in case the 23456d215f83SStefan Agner * receiver is off (limitation of the i.MX UART IP). 23466d215f83SStefan Agner */ 23476d215f83SStefan Agner if (sport->port.rs485.flags & SER_RS485_ENABLED && 23486d215f83SStefan Agner sport->have_rtscts && !sport->have_rtsgpio && 23496d215f83SStefan Agner (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 23506d215f83SStefan Agner !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 23516d215f83SStefan Agner dev_err(&pdev->dev, 23526d215f83SStefan Agner "low-active RTS not possible when receiver is off, enabling receiver\n"); 23536d215f83SStefan Agner 23548322b1f5SIlpo Järvinen uart_rs485_config(&sport->port); 2355b8f3bff0SLukas Wunner 23568a61f0c7SFabio Estevam /* Disable interrupts before requesting them */ 23574444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1); 23585f0e708cSYe Bin ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN); 23594444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 23608a61f0c7SFabio Estevam 23619d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2362e61c38d8SUwe Kleine-König /* 2363e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2364e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2365e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective 2366e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs. 2367e61c38d8SUwe Kleine-König */ 23684444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 23694444dcf1SUwe Kleine-König if (!(ufcr & UFCR_DCEDTE)) 23704444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2371e61c38d8SUwe Kleine-König 2372e61c38d8SUwe Kleine-König /* 2373e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2374e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared 2375e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable. 2376e61c38d8SUwe Kleine-König */ 237727c84426SUwe Kleine-König imx_uart_writel(sport, 237827c84426SUwe Kleine-König IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 237927c84426SUwe Kleine-König UCR3); 2380e61c38d8SUwe Kleine-König 2381e61c38d8SUwe Kleine-König } else { 23824444dcf1SUwe Kleine-König u32 ucr3 = UCR3_DSR; 23834444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR); 23844444dcf1SUwe Kleine-König if (ufcr & UFCR_DCEDTE) 23854444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 23866df765dcSUwe Kleine-König 23879d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport)) 23886df765dcSUwe Kleine-König ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 238927c84426SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2390e61c38d8SUwe Kleine-König } 2391e61c38d8SUwe Kleine-König 23928a61f0c7SFabio Estevam clk_disable_unprepare(sport->clk_ipg); 23938a61f0c7SFabio Estevam 2394bd78ecd6SAhmad Fatoum hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2395bd78ecd6SAhmad Fatoum hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2396bd78ecd6SAhmad Fatoum sport->trigger_start_tx.function = imx_trigger_start_tx; 2397bd78ecd6SAhmad Fatoum sport->trigger_stop_tx.function = imx_trigger_stop_tx; 2398cb1a6092SUwe Kleine-König 2399c0d1c6b0SFabio Estevam /* 2400c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2401c0d1c6b0SFabio Estevam * chips only have one interrupt. 2402c0d1c6b0SFabio Estevam */ 2403842633bdSUwe Kleine-König if (txirq > 0) { 24049d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2405c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 24061e512d45SUwe Kleine-König if (ret) { 24071e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n", 24081e512d45SUwe Kleine-König ret); 2409c0d1c6b0SFabio Estevam return ret; 24101e512d45SUwe Kleine-König } 2411c0d1c6b0SFabio Estevam 24129d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2413c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 24141e512d45SUwe Kleine-König if (ret) { 24151e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n", 24161e512d45SUwe Kleine-König ret); 2417c0d1c6b0SFabio Estevam return ret; 24181e512d45SUwe Kleine-König } 24197e620984SUwe Kleine-König 24207e620984SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, 24217e620984SUwe Kleine-König dev_name(&pdev->dev), sport); 24227e620984SUwe Kleine-König if (ret) { 24237e620984SUwe Kleine-König dev_err(&pdev->dev, "failed to request rts irq: %d\n", 24247e620984SUwe Kleine-König ret); 24257e620984SUwe Kleine-König return ret; 24267e620984SUwe Kleine-König } 2427c0d1c6b0SFabio Estevam } else { 24289d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2429c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport); 24301e512d45SUwe Kleine-König if (ret) { 24311e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2432c0d1c6b0SFabio Estevam return ret; 2433c0d1c6b0SFabio Estevam } 24341e512d45SUwe Kleine-König } 2435c0d1c6b0SFabio Estevam 24369d1a50a2SUwe Kleine-König imx_uart_ports[sport->port.line] = sport; 2437ab4382d2SGreg Kroah-Hartman 24380a86a86bSRichard Zhao platform_set_drvdata(pdev, sport); 2439ab4382d2SGreg Kroah-Hartman 24409d1a50a2SUwe Kleine-König return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2441ab4382d2SGreg Kroah-Hartman } 2442ab4382d2SGreg Kroah-Hartman 24439d1a50a2SUwe Kleine-König static int imx_uart_remove(struct platform_device *pdev) 2444ab4382d2SGreg Kroah-Hartman { 2445ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev); 2446ab4382d2SGreg Kroah-Hartman 24479d1a50a2SUwe Kleine-König return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2448ab4382d2SGreg Kroah-Hartman } 2449ab4382d2SGreg Kroah-Hartman 24509d1a50a2SUwe Kleine-König static void imx_uart_restore_context(struct imx_port *sport) 2451c868cbb7SEduardo Valentin { 245207b5e16eSAnson Huang unsigned long flags; 245307b5e16eSAnson Huang 245407b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 245507b5e16eSAnson Huang if (!sport->context_saved) { 245607b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2457c868cbb7SEduardo Valentin return; 245807b5e16eSAnson Huang } 2459c868cbb7SEduardo Valentin 246027c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[4], UFCR); 246127c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[5], UESC); 246227c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[6], UTIM); 246327c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[7], UBIR); 246427c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[8], UBMR); 246527c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 246627c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[0], UCR1); 246727c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 246827c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[2], UCR3); 246927c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2470c868cbb7SEduardo Valentin sport->context_saved = false; 247107b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2472c868cbb7SEduardo Valentin } 2473c868cbb7SEduardo Valentin 24749d1a50a2SUwe Kleine-König static void imx_uart_save_context(struct imx_port *sport) 2475c868cbb7SEduardo Valentin { 247607b5e16eSAnson Huang unsigned long flags; 247707b5e16eSAnson Huang 2478c868cbb7SEduardo Valentin /* Save necessary regs */ 247907b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags); 248027c84426SUwe Kleine-König sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 248127c84426SUwe Kleine-König sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 248227c84426SUwe Kleine-König sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 248327c84426SUwe Kleine-König sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 248427c84426SUwe Kleine-König sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 248527c84426SUwe Kleine-König sport->saved_reg[5] = imx_uart_readl(sport, UESC); 248627c84426SUwe Kleine-König sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 248727c84426SUwe Kleine-König sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 248827c84426SUwe Kleine-König sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 248927c84426SUwe Kleine-König sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2490c868cbb7SEduardo Valentin sport->context_saved = true; 249107b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags); 2492c868cbb7SEduardo Valentin } 2493c868cbb7SEduardo Valentin 24949d1a50a2SUwe Kleine-König static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2495189550b8SEduardo Valentin { 24964444dcf1SUwe Kleine-König u32 ucr3; 2497189550b8SEduardo Valentin 24984444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3); 249909df0b34SMartin Kaiser if (on) { 250027c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1); 25014444dcf1SUwe Kleine-König ucr3 |= UCR3_AWAKEN; 25024444dcf1SUwe Kleine-König } else { 25034444dcf1SUwe Kleine-König ucr3 &= ~UCR3_AWAKEN; 250409df0b34SMartin Kaiser } 25054444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3); 2506bc85734bSEduardo Valentin 250738b1f0fbSFabio Estevam if (sport->have_rtscts) { 25084444dcf1SUwe Kleine-König u32 ucr1 = imx_uart_readl(sport, UCR1); 2509c67643b4SFugang Duan if (on) { 2510c67643b4SFugang Duan imx_uart_writel(sport, USR1_RTSD, USR1); 25114444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN; 2512c67643b4SFugang Duan } else { 25134444dcf1SUwe Kleine-König ucr1 &= ~UCR1_RTSDEN; 2514c67643b4SFugang Duan } 25154444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1); 2516189550b8SEduardo Valentin } 251738b1f0fbSFabio Estevam } 2518189550b8SEduardo Valentin 25199d1a50a2SUwe Kleine-König static int imx_uart_suspend_noirq(struct device *dev) 252090bb6bd3SShenwei Wang { 2521a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 252290bb6bd3SShenwei Wang 25239d1a50a2SUwe Kleine-König imx_uart_save_context(sport); 252490bb6bd3SShenwei Wang 252590bb6bd3SShenwei Wang clk_disable(sport->clk_ipg); 252690bb6bd3SShenwei Wang 2527fcfed1beSAnson Huang pinctrl_pm_select_sleep_state(dev); 2528fcfed1beSAnson Huang 252990bb6bd3SShenwei Wang return 0; 253090bb6bd3SShenwei Wang } 253190bb6bd3SShenwei Wang 25329d1a50a2SUwe Kleine-König static int imx_uart_resume_noirq(struct device *dev) 253390bb6bd3SShenwei Wang { 2534a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 253590bb6bd3SShenwei Wang int ret; 253690bb6bd3SShenwei Wang 2537fcfed1beSAnson Huang pinctrl_pm_select_default_state(dev); 2538fcfed1beSAnson Huang 253990bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg); 254090bb6bd3SShenwei Wang if (ret) 254190bb6bd3SShenwei Wang return ret; 254290bb6bd3SShenwei Wang 25439d1a50a2SUwe Kleine-König imx_uart_restore_context(sport); 254490bb6bd3SShenwei Wang 254590bb6bd3SShenwei Wang return 0; 254690bb6bd3SShenwei Wang } 254790bb6bd3SShenwei Wang 25489d1a50a2SUwe Kleine-König static int imx_uart_suspend(struct device *dev) 254990bb6bd3SShenwei Wang { 2550a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 255109df0b34SMartin Kaiser int ret; 255290bb6bd3SShenwei Wang 25539d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 255481b289ccSMaxim Yu. Osipov disable_irq(sport->port.irq); 255590bb6bd3SShenwei Wang 255609df0b34SMartin Kaiser ret = clk_prepare_enable(sport->clk_ipg); 255709df0b34SMartin Kaiser if (ret) 255809df0b34SMartin Kaiser return ret; 255909df0b34SMartin Kaiser 256009df0b34SMartin Kaiser /* enable wakeup from i.MX UART */ 25619d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, true); 256209df0b34SMartin Kaiser 256309df0b34SMartin Kaiser return 0; 256490bb6bd3SShenwei Wang } 256590bb6bd3SShenwei Wang 25669d1a50a2SUwe Kleine-König static int imx_uart_resume(struct device *dev) 256790bb6bd3SShenwei Wang { 2568a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 256990bb6bd3SShenwei Wang 257090bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */ 25719d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, false); 257290bb6bd3SShenwei Wang 25739d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 257481b289ccSMaxim Yu. Osipov enable_irq(sport->port.irq); 257590bb6bd3SShenwei Wang 257609df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 257729add68dSMartin Fuzzey 257890bb6bd3SShenwei Wang return 0; 257990bb6bd3SShenwei Wang } 258090bb6bd3SShenwei Wang 25819d1a50a2SUwe Kleine-König static int imx_uart_freeze(struct device *dev) 258294be6d74SPhilipp Zabel { 2583a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 258494be6d74SPhilipp Zabel 25859d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port); 258694be6d74SPhilipp Zabel 258709df0b34SMartin Kaiser return clk_prepare_enable(sport->clk_ipg); 258894be6d74SPhilipp Zabel } 258994be6d74SPhilipp Zabel 25909d1a50a2SUwe Kleine-König static int imx_uart_thaw(struct device *dev) 259194be6d74SPhilipp Zabel { 2592a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev); 259394be6d74SPhilipp Zabel 25949d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port); 259594be6d74SPhilipp Zabel 259609df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg); 259794be6d74SPhilipp Zabel 259894be6d74SPhilipp Zabel return 0; 259994be6d74SPhilipp Zabel } 260094be6d74SPhilipp Zabel 26019d1a50a2SUwe Kleine-König static const struct dev_pm_ops imx_uart_pm_ops = { 26029d1a50a2SUwe Kleine-König .suspend_noirq = imx_uart_suspend_noirq, 26039d1a50a2SUwe Kleine-König .resume_noirq = imx_uart_resume_noirq, 26049d1a50a2SUwe Kleine-König .freeze_noirq = imx_uart_suspend_noirq, 26059d1a50a2SUwe Kleine-König .restore_noirq = imx_uart_resume_noirq, 26069d1a50a2SUwe Kleine-König .suspend = imx_uart_suspend, 26079d1a50a2SUwe Kleine-König .resume = imx_uart_resume, 26089d1a50a2SUwe Kleine-König .freeze = imx_uart_freeze, 26099d1a50a2SUwe Kleine-König .thaw = imx_uart_thaw, 26109d1a50a2SUwe Kleine-König .restore = imx_uart_thaw, 261190bb6bd3SShenwei Wang }; 261290bb6bd3SShenwei Wang 26139d1a50a2SUwe Kleine-König static struct platform_driver imx_uart_platform_driver = { 26149d1a50a2SUwe Kleine-König .probe = imx_uart_probe, 26159d1a50a2SUwe Kleine-König .remove = imx_uart_remove, 2616ab4382d2SGreg Kroah-Hartman 2617ab4382d2SGreg Kroah-Hartman .driver = { 2618ab4382d2SGreg Kroah-Hartman .name = "imx-uart", 261922698aa2SShawn Guo .of_match_table = imx_uart_dt_ids, 26209d1a50a2SUwe Kleine-König .pm = &imx_uart_pm_ops, 2621ab4382d2SGreg Kroah-Hartman }, 2622ab4382d2SGreg Kroah-Hartman }; 2623ab4382d2SGreg Kroah-Hartman 26249d1a50a2SUwe Kleine-König static int __init imx_uart_init(void) 2625ab4382d2SGreg Kroah-Hartman { 26269d1a50a2SUwe Kleine-König int ret = uart_register_driver(&imx_uart_uart_driver); 2627ab4382d2SGreg Kroah-Hartman 2628ab4382d2SGreg Kroah-Hartman if (ret) 2629ab4382d2SGreg Kroah-Hartman return ret; 2630ab4382d2SGreg Kroah-Hartman 26319d1a50a2SUwe Kleine-König ret = platform_driver_register(&imx_uart_platform_driver); 2632ab4382d2SGreg Kroah-Hartman if (ret != 0) 26339d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2634ab4382d2SGreg Kroah-Hartman 2635f227824eSUwe Kleine-König return ret; 2636ab4382d2SGreg Kroah-Hartman } 2637ab4382d2SGreg Kroah-Hartman 26389d1a50a2SUwe Kleine-König static void __exit imx_uart_exit(void) 2639ab4382d2SGreg Kroah-Hartman { 26409d1a50a2SUwe Kleine-König platform_driver_unregister(&imx_uart_platform_driver); 26419d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver); 2642ab4382d2SGreg Kroah-Hartman } 2643ab4382d2SGreg Kroah-Hartman 26449d1a50a2SUwe Kleine-König module_init(imx_uart_init); 26459d1a50a2SUwe Kleine-König module_exit(imx_uart_exit); 2646ab4382d2SGreg Kroah-Hartman 2647ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer"); 2648ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver"); 2649ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL"); 2650ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart"); 2651