1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale lpuart serial port driver 4 * 5 * Copyright 2012-2014 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/console.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dmapool.h> 13 #include <linux/io.h> 14 #include <linux/irq.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/of_dma.h> 19 #include <linux/serial_core.h> 20 #include <linux/slab.h> 21 #include <linux/tty_flip.h> 22 23 /* All registers are 8-bit width */ 24 #define UARTBDH 0x00 25 #define UARTBDL 0x01 26 #define UARTCR1 0x02 27 #define UARTCR2 0x03 28 #define UARTSR1 0x04 29 #define UARTCR3 0x06 30 #define UARTDR 0x07 31 #define UARTCR4 0x0a 32 #define UARTCR5 0x0b 33 #define UARTMODEM 0x0d 34 #define UARTPFIFO 0x10 35 #define UARTCFIFO 0x11 36 #define UARTSFIFO 0x12 37 #define UARTTWFIFO 0x13 38 #define UARTTCFIFO 0x14 39 #define UARTRWFIFO 0x15 40 41 #define UARTBDH_LBKDIE 0x80 42 #define UARTBDH_RXEDGIE 0x40 43 #define UARTBDH_SBR_MASK 0x1f 44 45 #define UARTCR1_LOOPS 0x80 46 #define UARTCR1_RSRC 0x20 47 #define UARTCR1_M 0x10 48 #define UARTCR1_WAKE 0x08 49 #define UARTCR1_ILT 0x04 50 #define UARTCR1_PE 0x02 51 #define UARTCR1_PT 0x01 52 53 #define UARTCR2_TIE 0x80 54 #define UARTCR2_TCIE 0x40 55 #define UARTCR2_RIE 0x20 56 #define UARTCR2_ILIE 0x10 57 #define UARTCR2_TE 0x08 58 #define UARTCR2_RE 0x04 59 #define UARTCR2_RWU 0x02 60 #define UARTCR2_SBK 0x01 61 62 #define UARTSR1_TDRE 0x80 63 #define UARTSR1_TC 0x40 64 #define UARTSR1_RDRF 0x20 65 #define UARTSR1_IDLE 0x10 66 #define UARTSR1_OR 0x08 67 #define UARTSR1_NF 0x04 68 #define UARTSR1_FE 0x02 69 #define UARTSR1_PE 0x01 70 71 #define UARTCR3_R8 0x80 72 #define UARTCR3_T8 0x40 73 #define UARTCR3_TXDIR 0x20 74 #define UARTCR3_TXINV 0x10 75 #define UARTCR3_ORIE 0x08 76 #define UARTCR3_NEIE 0x04 77 #define UARTCR3_FEIE 0x02 78 #define UARTCR3_PEIE 0x01 79 80 #define UARTCR4_MAEN1 0x80 81 #define UARTCR4_MAEN2 0x40 82 #define UARTCR4_M10 0x20 83 #define UARTCR4_BRFA_MASK 0x1f 84 #define UARTCR4_BRFA_OFF 0 85 86 #define UARTCR5_TDMAS 0x80 87 #define UARTCR5_RDMAS 0x20 88 89 #define UARTMODEM_RXRTSE 0x08 90 #define UARTMODEM_TXRTSPOL 0x04 91 #define UARTMODEM_TXRTSE 0x02 92 #define UARTMODEM_TXCTSE 0x01 93 94 #define UARTPFIFO_TXFE 0x80 95 #define UARTPFIFO_FIFOSIZE_MASK 0x7 96 #define UARTPFIFO_TXSIZE_OFF 4 97 #define UARTPFIFO_RXFE 0x08 98 #define UARTPFIFO_RXSIZE_OFF 0 99 100 #define UARTCFIFO_TXFLUSH 0x80 101 #define UARTCFIFO_RXFLUSH 0x40 102 #define UARTCFIFO_RXOFE 0x04 103 #define UARTCFIFO_TXOFE 0x02 104 #define UARTCFIFO_RXUFE 0x01 105 106 #define UARTSFIFO_TXEMPT 0x80 107 #define UARTSFIFO_RXEMPT 0x40 108 #define UARTSFIFO_RXOF 0x04 109 #define UARTSFIFO_TXOF 0x02 110 #define UARTSFIFO_RXUF 0x01 111 112 /* 32-bit register definition */ 113 #define UARTBAUD 0x00 114 #define UARTSTAT 0x04 115 #define UARTCTRL 0x08 116 #define UARTDATA 0x0C 117 #define UARTMATCH 0x10 118 #define UARTMODIR 0x14 119 #define UARTFIFO 0x18 120 #define UARTWATER 0x1c 121 122 #define UARTBAUD_MAEN1 0x80000000 123 #define UARTBAUD_MAEN2 0x40000000 124 #define UARTBAUD_M10 0x20000000 125 #define UARTBAUD_TDMAE 0x00800000 126 #define UARTBAUD_RDMAE 0x00200000 127 #define UARTBAUD_MATCFG 0x00400000 128 #define UARTBAUD_BOTHEDGE 0x00020000 129 #define UARTBAUD_RESYNCDIS 0x00010000 130 #define UARTBAUD_LBKDIE 0x00008000 131 #define UARTBAUD_RXEDGIE 0x00004000 132 #define UARTBAUD_SBNS 0x00002000 133 #define UARTBAUD_SBR 0x00000000 134 #define UARTBAUD_SBR_MASK 0x1fff 135 #define UARTBAUD_OSR_MASK 0x1f 136 #define UARTBAUD_OSR_SHIFT 24 137 138 #define UARTSTAT_LBKDIF 0x80000000 139 #define UARTSTAT_RXEDGIF 0x40000000 140 #define UARTSTAT_MSBF 0x20000000 141 #define UARTSTAT_RXINV 0x10000000 142 #define UARTSTAT_RWUID 0x08000000 143 #define UARTSTAT_BRK13 0x04000000 144 #define UARTSTAT_LBKDE 0x02000000 145 #define UARTSTAT_RAF 0x01000000 146 #define UARTSTAT_TDRE 0x00800000 147 #define UARTSTAT_TC 0x00400000 148 #define UARTSTAT_RDRF 0x00200000 149 #define UARTSTAT_IDLE 0x00100000 150 #define UARTSTAT_OR 0x00080000 151 #define UARTSTAT_NF 0x00040000 152 #define UARTSTAT_FE 0x00020000 153 #define UARTSTAT_PE 0x00010000 154 #define UARTSTAT_MA1F 0x00008000 155 #define UARTSTAT_M21F 0x00004000 156 157 #define UARTCTRL_R8T9 0x80000000 158 #define UARTCTRL_R9T8 0x40000000 159 #define UARTCTRL_TXDIR 0x20000000 160 #define UARTCTRL_TXINV 0x10000000 161 #define UARTCTRL_ORIE 0x08000000 162 #define UARTCTRL_NEIE 0x04000000 163 #define UARTCTRL_FEIE 0x02000000 164 #define UARTCTRL_PEIE 0x01000000 165 #define UARTCTRL_TIE 0x00800000 166 #define UARTCTRL_TCIE 0x00400000 167 #define UARTCTRL_RIE 0x00200000 168 #define UARTCTRL_ILIE 0x00100000 169 #define UARTCTRL_TE 0x00080000 170 #define UARTCTRL_RE 0x00040000 171 #define UARTCTRL_RWU 0x00020000 172 #define UARTCTRL_SBK 0x00010000 173 #define UARTCTRL_MA1IE 0x00008000 174 #define UARTCTRL_MA2IE 0x00004000 175 #define UARTCTRL_IDLECFG 0x00000100 176 #define UARTCTRL_LOOPS 0x00000080 177 #define UARTCTRL_DOZEEN 0x00000040 178 #define UARTCTRL_RSRC 0x00000020 179 #define UARTCTRL_M 0x00000010 180 #define UARTCTRL_WAKE 0x00000008 181 #define UARTCTRL_ILT 0x00000004 182 #define UARTCTRL_PE 0x00000002 183 #define UARTCTRL_PT 0x00000001 184 185 #define UARTDATA_NOISY 0x00008000 186 #define UARTDATA_PARITYE 0x00004000 187 #define UARTDATA_FRETSC 0x00002000 188 #define UARTDATA_RXEMPT 0x00001000 189 #define UARTDATA_IDLINE 0x00000800 190 #define UARTDATA_MASK 0x3ff 191 192 #define UARTMODIR_IREN 0x00020000 193 #define UARTMODIR_TXCTSSRC 0x00000020 194 #define UARTMODIR_TXCTSC 0x00000010 195 #define UARTMODIR_RXRTSE 0x00000008 196 #define UARTMODIR_TXRTSPOL 0x00000004 197 #define UARTMODIR_TXRTSE 0x00000002 198 #define UARTMODIR_TXCTSE 0x00000001 199 200 #define UARTFIFO_TXEMPT 0x00800000 201 #define UARTFIFO_RXEMPT 0x00400000 202 #define UARTFIFO_TXOF 0x00020000 203 #define UARTFIFO_RXUF 0x00010000 204 #define UARTFIFO_TXFLUSH 0x00008000 205 #define UARTFIFO_RXFLUSH 0x00004000 206 #define UARTFIFO_TXOFE 0x00000200 207 #define UARTFIFO_RXUFE 0x00000100 208 #define UARTFIFO_TXFE 0x00000080 209 #define UARTFIFO_FIFOSIZE_MASK 0x7 210 #define UARTFIFO_TXSIZE_OFF 4 211 #define UARTFIFO_RXFE 0x00000008 212 #define UARTFIFO_RXSIZE_OFF 0 213 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0)) 214 215 #define UARTWATER_COUNT_MASK 0xff 216 #define UARTWATER_TXCNT_OFF 8 217 #define UARTWATER_RXCNT_OFF 24 218 #define UARTWATER_WATER_MASK 0xff 219 #define UARTWATER_TXWATER_OFF 0 220 #define UARTWATER_RXWATER_OFF 16 221 222 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 223 #define DMA_RX_TIMEOUT (10) 224 225 #define DRIVER_NAME "fsl-lpuart" 226 #define DEV_NAME "ttyLP" 227 #define UART_NR 6 228 229 /* IMX lpuart has four extra unused regs located at the beginning */ 230 #define IMX_REG_OFF 0x10 231 232 static DEFINE_IDA(fsl_lpuart_ida); 233 234 enum lpuart_type { 235 VF610_LPUART, 236 LS1021A_LPUART, 237 IMX7ULP_LPUART, 238 IMX8QXP_LPUART, 239 }; 240 241 struct lpuart_port { 242 struct uart_port port; 243 enum lpuart_type devtype; 244 struct clk *ipg_clk; 245 struct clk *baud_clk; 246 unsigned int txfifo_size; 247 unsigned int rxfifo_size; 248 249 bool lpuart_dma_tx_use; 250 bool lpuart_dma_rx_use; 251 struct dma_chan *dma_tx_chan; 252 struct dma_chan *dma_rx_chan; 253 struct dma_async_tx_descriptor *dma_tx_desc; 254 struct dma_async_tx_descriptor *dma_rx_desc; 255 dma_cookie_t dma_tx_cookie; 256 dma_cookie_t dma_rx_cookie; 257 unsigned int dma_tx_bytes; 258 unsigned int dma_rx_bytes; 259 bool dma_tx_in_progress; 260 unsigned int dma_rx_timeout; 261 struct timer_list lpuart_timer; 262 struct scatterlist rx_sgl, tx_sgl[2]; 263 struct circ_buf rx_ring; 264 int rx_dma_rng_buf_len; 265 unsigned int dma_tx_nents; 266 wait_queue_head_t dma_wait; 267 }; 268 269 struct lpuart_soc_data { 270 enum lpuart_type devtype; 271 char iotype; 272 u8 reg_off; 273 }; 274 275 static const struct lpuart_soc_data vf_data = { 276 .devtype = VF610_LPUART, 277 .iotype = UPIO_MEM, 278 }; 279 280 static const struct lpuart_soc_data ls_data = { 281 .devtype = LS1021A_LPUART, 282 .iotype = UPIO_MEM32BE, 283 }; 284 285 static struct lpuart_soc_data imx7ulp_data = { 286 .devtype = IMX7ULP_LPUART, 287 .iotype = UPIO_MEM32, 288 .reg_off = IMX_REG_OFF, 289 }; 290 291 static struct lpuart_soc_data imx8qxp_data = { 292 .devtype = IMX8QXP_LPUART, 293 .iotype = UPIO_MEM32, 294 .reg_off = IMX_REG_OFF, 295 }; 296 297 static const struct of_device_id lpuart_dt_ids[] = { 298 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 299 { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, }, 300 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, 301 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, 302 { /* sentinel */ } 303 }; 304 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 305 306 /* Forward declare this for the dma callbacks*/ 307 static void lpuart_dma_tx_complete(void *arg); 308 309 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) 310 { 311 return sport->devtype == IMX8QXP_LPUART; 312 } 313 314 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 315 { 316 switch (port->iotype) { 317 case UPIO_MEM32: 318 return readl(port->membase + off); 319 case UPIO_MEM32BE: 320 return ioread32be(port->membase + off); 321 default: 322 return 0; 323 } 324 } 325 326 static inline void lpuart32_write(struct uart_port *port, u32 val, 327 u32 off) 328 { 329 switch (port->iotype) { 330 case UPIO_MEM32: 331 writel(val, port->membase + off); 332 break; 333 case UPIO_MEM32BE: 334 iowrite32be(val, port->membase + off); 335 break; 336 } 337 } 338 339 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) 340 { 341 int ret = 0; 342 343 if (is_en) { 344 ret = clk_prepare_enable(sport->ipg_clk); 345 if (ret) 346 return ret; 347 348 ret = clk_prepare_enable(sport->baud_clk); 349 if (ret) { 350 clk_disable_unprepare(sport->ipg_clk); 351 return ret; 352 } 353 } else { 354 clk_disable_unprepare(sport->baud_clk); 355 clk_disable_unprepare(sport->ipg_clk); 356 } 357 358 return 0; 359 } 360 361 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) 362 { 363 if (is_imx8qxp_lpuart(sport)) 364 return clk_get_rate(sport->baud_clk); 365 366 return clk_get_rate(sport->ipg_clk); 367 } 368 369 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true) 370 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false) 371 372 static void lpuart_stop_tx(struct uart_port *port) 373 { 374 unsigned char temp; 375 376 temp = readb(port->membase + UARTCR2); 377 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 378 writeb(temp, port->membase + UARTCR2); 379 } 380 381 static void lpuart32_stop_tx(struct uart_port *port) 382 { 383 unsigned long temp; 384 385 temp = lpuart32_read(port, UARTCTRL); 386 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 387 lpuart32_write(port, temp, UARTCTRL); 388 } 389 390 static void lpuart_stop_rx(struct uart_port *port) 391 { 392 unsigned char temp; 393 394 temp = readb(port->membase + UARTCR2); 395 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 396 } 397 398 static void lpuart32_stop_rx(struct uart_port *port) 399 { 400 unsigned long temp; 401 402 temp = lpuart32_read(port, UARTCTRL); 403 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); 404 } 405 406 static void lpuart_dma_tx(struct lpuart_port *sport) 407 { 408 struct circ_buf *xmit = &sport->port.state->xmit; 409 struct scatterlist *sgl = sport->tx_sgl; 410 struct device *dev = sport->port.dev; 411 int ret; 412 413 if (sport->dma_tx_in_progress) 414 return; 415 416 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 417 418 if (xmit->tail < xmit->head || xmit->head == 0) { 419 sport->dma_tx_nents = 1; 420 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 421 } else { 422 sport->dma_tx_nents = 2; 423 sg_init_table(sgl, 2); 424 sg_set_buf(sgl, xmit->buf + xmit->tail, 425 UART_XMIT_SIZE - xmit->tail); 426 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 427 } 428 429 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 430 if (!ret) { 431 dev_err(dev, "DMA mapping error for TX.\n"); 432 return; 433 } 434 435 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl, 436 ret, DMA_MEM_TO_DEV, 437 DMA_PREP_INTERRUPT); 438 if (!sport->dma_tx_desc) { 439 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 440 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 441 return; 442 } 443 444 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 445 sport->dma_tx_desc->callback_param = sport; 446 sport->dma_tx_in_progress = true; 447 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 448 dma_async_issue_pending(sport->dma_tx_chan); 449 } 450 451 static bool lpuart_stopped_or_empty(struct uart_port *port) 452 { 453 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); 454 } 455 456 static void lpuart_dma_tx_complete(void *arg) 457 { 458 struct lpuart_port *sport = arg; 459 struct scatterlist *sgl = &sport->tx_sgl[0]; 460 struct circ_buf *xmit = &sport->port.state->xmit; 461 unsigned long flags; 462 463 spin_lock_irqsave(&sport->port.lock, flags); 464 465 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 466 467 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 468 469 sport->port.icount.tx += sport->dma_tx_bytes; 470 sport->dma_tx_in_progress = false; 471 spin_unlock_irqrestore(&sport->port.lock, flags); 472 473 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 474 uart_write_wakeup(&sport->port); 475 476 if (waitqueue_active(&sport->dma_wait)) { 477 wake_up(&sport->dma_wait); 478 return; 479 } 480 481 spin_lock_irqsave(&sport->port.lock, flags); 482 483 if (!lpuart_stopped_or_empty(&sport->port)) 484 lpuart_dma_tx(sport); 485 486 spin_unlock_irqrestore(&sport->port.lock, flags); 487 } 488 489 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) 490 { 491 switch (sport->port.iotype) { 492 case UPIO_MEM32: 493 return sport->port.mapbase + UARTDATA; 494 case UPIO_MEM32BE: 495 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; 496 } 497 return sport->port.mapbase + UARTDR; 498 } 499 500 static int lpuart_dma_tx_request(struct uart_port *port) 501 { 502 struct lpuart_port *sport = container_of(port, 503 struct lpuart_port, port); 504 struct dma_slave_config dma_tx_sconfig = {}; 505 int ret; 506 507 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); 508 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 509 dma_tx_sconfig.dst_maxburst = 1; 510 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 511 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 512 513 if (ret) { 514 dev_err(sport->port.dev, 515 "DMA slave config failed, err = %d\n", ret); 516 return ret; 517 } 518 519 return 0; 520 } 521 522 static bool lpuart_is_32(struct lpuart_port *sport) 523 { 524 return sport->port.iotype == UPIO_MEM32 || 525 sport->port.iotype == UPIO_MEM32BE; 526 } 527 528 static void lpuart_flush_buffer(struct uart_port *port) 529 { 530 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 531 u32 val; 532 533 if (sport->lpuart_dma_tx_use) { 534 if (sport->dma_tx_in_progress) { 535 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 536 sport->dma_tx_nents, DMA_TO_DEVICE); 537 sport->dma_tx_in_progress = false; 538 } 539 dmaengine_terminate_all(sport->dma_tx_chan); 540 } 541 542 if (lpuart_is_32(sport)) { 543 val = lpuart32_read(&sport->port, UARTFIFO); 544 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 545 lpuart32_write(&sport->port, val, UARTFIFO); 546 } else { 547 val = readb(sport->port.membase + UARTCFIFO); 548 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; 549 writeb(val, sport->port.membase + UARTCFIFO); 550 } 551 } 552 553 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset, 554 u8 bit) 555 { 556 while (!(readb(port->membase + offset) & bit)) 557 cpu_relax(); 558 } 559 560 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset, 561 u32 bit) 562 { 563 while (!(lpuart32_read(port, offset) & bit)) 564 cpu_relax(); 565 } 566 567 #if defined(CONFIG_CONSOLE_POLL) 568 569 static int lpuart_poll_init(struct uart_port *port) 570 { 571 struct lpuart_port *sport = container_of(port, 572 struct lpuart_port, port); 573 unsigned long flags; 574 unsigned char temp; 575 576 sport->port.fifosize = 0; 577 578 spin_lock_irqsave(&sport->port.lock, flags); 579 /* Disable Rx & Tx */ 580 writeb(0, sport->port.membase + UARTCR2); 581 582 temp = readb(sport->port.membase + UARTPFIFO); 583 /* Enable Rx and Tx FIFO */ 584 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 585 sport->port.membase + UARTPFIFO); 586 587 /* flush Tx and Rx FIFO */ 588 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 589 sport->port.membase + UARTCFIFO); 590 591 /* explicitly clear RDRF */ 592 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 593 readb(sport->port.membase + UARTDR); 594 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 595 } 596 597 writeb(0, sport->port.membase + UARTTWFIFO); 598 writeb(1, sport->port.membase + UARTRWFIFO); 599 600 /* Enable Rx and Tx */ 601 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 602 spin_unlock_irqrestore(&sport->port.lock, flags); 603 604 return 0; 605 } 606 607 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 608 { 609 /* drain */ 610 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 611 writeb(c, port->membase + UARTDR); 612 } 613 614 static int lpuart_poll_get_char(struct uart_port *port) 615 { 616 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 617 return NO_POLL_CHAR; 618 619 return readb(port->membase + UARTDR); 620 } 621 622 static int lpuart32_poll_init(struct uart_port *port) 623 { 624 unsigned long flags; 625 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 626 u32 temp; 627 628 sport->port.fifosize = 0; 629 630 spin_lock_irqsave(&sport->port.lock, flags); 631 632 /* Disable Rx & Tx */ 633 lpuart32_write(&sport->port, UARTCTRL, 0); 634 635 temp = lpuart32_read(&sport->port, UARTFIFO); 636 637 /* Enable Rx and Tx FIFO */ 638 lpuart32_write(&sport->port, UARTFIFO, 639 temp | UARTFIFO_RXFE | UARTFIFO_TXFE); 640 641 /* flush Tx and Rx FIFO */ 642 lpuart32_write(&sport->port, UARTFIFO, 643 UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH); 644 645 /* explicitly clear RDRF */ 646 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { 647 lpuart32_read(&sport->port, UARTDATA); 648 lpuart32_write(&sport->port, UARTFIFO, UARTFIFO_RXUF); 649 } 650 651 /* Enable Rx and Tx */ 652 lpuart32_write(&sport->port, UARTCTRL, UARTCTRL_RE | UARTCTRL_TE); 653 spin_unlock_irqrestore(&sport->port.lock, flags); 654 655 return 0; 656 } 657 658 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 659 { 660 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 661 lpuart32_write(port, UARTDATA, c); 662 } 663 664 static int lpuart32_poll_get_char(struct uart_port *port) 665 { 666 if (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_RDRF)) 667 return NO_POLL_CHAR; 668 669 return lpuart32_read(port, UARTDATA); 670 } 671 #endif 672 673 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 674 { 675 struct circ_buf *xmit = &sport->port.state->xmit; 676 677 if (sport->port.x_char) { 678 writeb(sport->port.x_char, sport->port.membase + UARTDR); 679 sport->port.icount.tx++; 680 sport->port.x_char = 0; 681 return; 682 } 683 684 if (lpuart_stopped_or_empty(&sport->port)) { 685 lpuart_stop_tx(&sport->port); 686 return; 687 } 688 689 while (!uart_circ_empty(xmit) && 690 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 691 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 692 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 693 sport->port.icount.tx++; 694 } 695 696 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 697 uart_write_wakeup(&sport->port); 698 699 if (uart_circ_empty(xmit)) 700 lpuart_stop_tx(&sport->port); 701 } 702 703 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 704 { 705 struct circ_buf *xmit = &sport->port.state->xmit; 706 unsigned long txcnt; 707 708 if (sport->port.x_char) { 709 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 710 sport->port.icount.tx++; 711 sport->port.x_char = 0; 712 return; 713 } 714 715 if (lpuart_stopped_or_empty(&sport->port)) { 716 lpuart32_stop_tx(&sport->port); 717 return; 718 } 719 720 txcnt = lpuart32_read(&sport->port, UARTWATER); 721 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 722 txcnt &= UARTWATER_COUNT_MASK; 723 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 724 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); 725 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 726 sport->port.icount.tx++; 727 txcnt = lpuart32_read(&sport->port, UARTWATER); 728 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 729 txcnt &= UARTWATER_COUNT_MASK; 730 } 731 732 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 733 uart_write_wakeup(&sport->port); 734 735 if (uart_circ_empty(xmit)) 736 lpuart32_stop_tx(&sport->port); 737 } 738 739 static void lpuart_start_tx(struct uart_port *port) 740 { 741 struct lpuart_port *sport = container_of(port, 742 struct lpuart_port, port); 743 unsigned char temp; 744 745 temp = readb(port->membase + UARTCR2); 746 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 747 748 if (sport->lpuart_dma_tx_use) { 749 if (!lpuart_stopped_or_empty(port)) 750 lpuart_dma_tx(sport); 751 } else { 752 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 753 lpuart_transmit_buffer(sport); 754 } 755 } 756 757 static void lpuart32_start_tx(struct uart_port *port) 758 { 759 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 760 unsigned long temp; 761 762 if (sport->lpuart_dma_tx_use) { 763 if (!lpuart_stopped_or_empty(port)) 764 lpuart_dma_tx(sport); 765 } else { 766 temp = lpuart32_read(port, UARTCTRL); 767 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); 768 769 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 770 lpuart32_transmit_buffer(sport); 771 } 772 } 773 774 /* return TIOCSER_TEMT when transmitter is not busy */ 775 static unsigned int lpuart_tx_empty(struct uart_port *port) 776 { 777 struct lpuart_port *sport = container_of(port, 778 struct lpuart_port, port); 779 unsigned char sr1 = readb(port->membase + UARTSR1); 780 unsigned char sfifo = readb(port->membase + UARTSFIFO); 781 782 if (sport->dma_tx_in_progress) 783 return 0; 784 785 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 786 return TIOCSER_TEMT; 787 788 return 0; 789 } 790 791 static unsigned int lpuart32_tx_empty(struct uart_port *port) 792 { 793 struct lpuart_port *sport = container_of(port, 794 struct lpuart_port, port); 795 unsigned long stat = lpuart32_read(port, UARTSTAT); 796 unsigned long sfifo = lpuart32_read(port, UARTFIFO); 797 798 if (sport->dma_tx_in_progress) 799 return 0; 800 801 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) 802 return TIOCSER_TEMT; 803 804 return 0; 805 } 806 807 static void lpuart_txint(struct lpuart_port *sport) 808 { 809 unsigned long flags; 810 811 spin_lock_irqsave(&sport->port.lock, flags); 812 lpuart_transmit_buffer(sport); 813 spin_unlock_irqrestore(&sport->port.lock, flags); 814 } 815 816 static void lpuart_rxint(struct lpuart_port *sport) 817 { 818 unsigned int flg, ignored = 0, overrun = 0; 819 struct tty_port *port = &sport->port.state->port; 820 unsigned long flags; 821 unsigned char rx, sr; 822 823 spin_lock_irqsave(&sport->port.lock, flags); 824 825 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 826 flg = TTY_NORMAL; 827 sport->port.icount.rx++; 828 /* 829 * to clear the FE, OR, NF, FE, PE flags, 830 * read SR1 then read DR 831 */ 832 sr = readb(sport->port.membase + UARTSR1); 833 rx = readb(sport->port.membase + UARTDR); 834 835 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 836 continue; 837 838 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 839 if (sr & UARTSR1_PE) 840 sport->port.icount.parity++; 841 else if (sr & UARTSR1_FE) 842 sport->port.icount.frame++; 843 844 if (sr & UARTSR1_OR) 845 overrun++; 846 847 if (sr & sport->port.ignore_status_mask) { 848 if (++ignored > 100) 849 goto out; 850 continue; 851 } 852 853 sr &= sport->port.read_status_mask; 854 855 if (sr & UARTSR1_PE) 856 flg = TTY_PARITY; 857 else if (sr & UARTSR1_FE) 858 flg = TTY_FRAME; 859 860 if (sr & UARTSR1_OR) 861 flg = TTY_OVERRUN; 862 863 sport->port.sysrq = 0; 864 } 865 866 tty_insert_flip_char(port, rx, flg); 867 } 868 869 out: 870 if (overrun) { 871 sport->port.icount.overrun += overrun; 872 873 /* 874 * Overruns cause FIFO pointers to become missaligned. 875 * Flushing the receive FIFO reinitializes the pointers. 876 */ 877 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 878 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); 879 } 880 881 spin_unlock_irqrestore(&sport->port.lock, flags); 882 883 tty_flip_buffer_push(port); 884 } 885 886 static void lpuart32_txint(struct lpuart_port *sport) 887 { 888 unsigned long flags; 889 890 spin_lock_irqsave(&sport->port.lock, flags); 891 lpuart32_transmit_buffer(sport); 892 spin_unlock_irqrestore(&sport->port.lock, flags); 893 } 894 895 static void lpuart32_rxint(struct lpuart_port *sport) 896 { 897 unsigned int flg, ignored = 0; 898 struct tty_port *port = &sport->port.state->port; 899 unsigned long flags; 900 unsigned long rx, sr; 901 902 spin_lock_irqsave(&sport->port.lock, flags); 903 904 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 905 flg = TTY_NORMAL; 906 sport->port.icount.rx++; 907 /* 908 * to clear the FE, OR, NF, FE, PE flags, 909 * read STAT then read DATA reg 910 */ 911 sr = lpuart32_read(&sport->port, UARTSTAT); 912 rx = lpuart32_read(&sport->port, UARTDATA); 913 rx &= 0x3ff; 914 915 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 916 continue; 917 918 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 919 if (sr & UARTSTAT_PE) 920 sport->port.icount.parity++; 921 else if (sr & UARTSTAT_FE) 922 sport->port.icount.frame++; 923 924 if (sr & UARTSTAT_OR) 925 sport->port.icount.overrun++; 926 927 if (sr & sport->port.ignore_status_mask) { 928 if (++ignored > 100) 929 goto out; 930 continue; 931 } 932 933 sr &= sport->port.read_status_mask; 934 935 if (sr & UARTSTAT_PE) 936 flg = TTY_PARITY; 937 else if (sr & UARTSTAT_FE) 938 flg = TTY_FRAME; 939 940 if (sr & UARTSTAT_OR) 941 flg = TTY_OVERRUN; 942 943 sport->port.sysrq = 0; 944 } 945 946 tty_insert_flip_char(port, rx, flg); 947 } 948 949 out: 950 spin_unlock_irqrestore(&sport->port.lock, flags); 951 952 tty_flip_buffer_push(port); 953 } 954 955 static irqreturn_t lpuart_int(int irq, void *dev_id) 956 { 957 struct lpuart_port *sport = dev_id; 958 unsigned char sts; 959 960 sts = readb(sport->port.membase + UARTSR1); 961 962 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) 963 lpuart_rxint(sport); 964 965 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) 966 lpuart_txint(sport); 967 968 return IRQ_HANDLED; 969 } 970 971 static irqreturn_t lpuart32_int(int irq, void *dev_id) 972 { 973 struct lpuart_port *sport = dev_id; 974 unsigned long sts, rxcount; 975 976 sts = lpuart32_read(&sport->port, UARTSTAT); 977 rxcount = lpuart32_read(&sport->port, UARTWATER); 978 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 979 980 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) 981 lpuart32_rxint(sport); 982 983 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) 984 lpuart32_txint(sport); 985 986 lpuart32_write(&sport->port, sts, UARTSTAT); 987 return IRQ_HANDLED; 988 } 989 990 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 991 { 992 struct tty_port *port = &sport->port.state->port; 993 struct dma_tx_state state; 994 enum dma_status dmastat; 995 struct circ_buf *ring = &sport->rx_ring; 996 unsigned long flags; 997 int count = 0; 998 999 if (lpuart_is_32(sport)) { 1000 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); 1001 1002 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { 1003 /* Read DR to clear the error flags */ 1004 lpuart32_read(&sport->port, UARTDATA); 1005 1006 if (sr & UARTSTAT_PE) 1007 sport->port.icount.parity++; 1008 else if (sr & UARTSTAT_FE) 1009 sport->port.icount.frame++; 1010 } 1011 } else { 1012 unsigned char sr = readb(sport->port.membase + UARTSR1); 1013 1014 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 1015 unsigned char cr2; 1016 1017 /* Disable receiver during this operation... */ 1018 cr2 = readb(sport->port.membase + UARTCR2); 1019 cr2 &= ~UARTCR2_RE; 1020 writeb(cr2, sport->port.membase + UARTCR2); 1021 1022 /* Read DR to clear the error flags */ 1023 readb(sport->port.membase + UARTDR); 1024 1025 if (sr & UARTSR1_PE) 1026 sport->port.icount.parity++; 1027 else if (sr & UARTSR1_FE) 1028 sport->port.icount.frame++; 1029 /* 1030 * At this point parity/framing error is 1031 * cleared However, since the DMA already read 1032 * the data register and we had to read it 1033 * again after reading the status register to 1034 * properly clear the flags, the FIFO actually 1035 * underflowed... This requires a clearing of 1036 * the FIFO... 1037 */ 1038 if (readb(sport->port.membase + UARTSFIFO) & 1039 UARTSFIFO_RXUF) { 1040 writeb(UARTSFIFO_RXUF, 1041 sport->port.membase + UARTSFIFO); 1042 writeb(UARTCFIFO_RXFLUSH, 1043 sport->port.membase + UARTCFIFO); 1044 } 1045 1046 cr2 |= UARTCR2_RE; 1047 writeb(cr2, sport->port.membase + UARTCR2); 1048 } 1049 } 1050 1051 async_tx_ack(sport->dma_rx_desc); 1052 1053 spin_lock_irqsave(&sport->port.lock, flags); 1054 1055 dmastat = dmaengine_tx_status(sport->dma_rx_chan, 1056 sport->dma_rx_cookie, 1057 &state); 1058 1059 if (dmastat == DMA_ERROR) { 1060 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1061 spin_unlock_irqrestore(&sport->port.lock, flags); 1062 return; 1063 } 1064 1065 /* CPU claims ownership of RX DMA buffer */ 1066 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1067 1068 /* 1069 * ring->head points to the end of data already written by the DMA. 1070 * ring->tail points to the beginning of data to be read by the 1071 * framework. 1072 * The current transfer size should not be larger than the dma buffer 1073 * length. 1074 */ 1075 ring->head = sport->rx_sgl.length - state.residue; 1076 BUG_ON(ring->head > sport->rx_sgl.length); 1077 /* 1078 * At this point ring->head may point to the first byte right after the 1079 * last byte of the dma buffer: 1080 * 0 <= ring->head <= sport->rx_sgl.length 1081 * 1082 * However ring->tail must always points inside the dma buffer: 1083 * 0 <= ring->tail <= sport->rx_sgl.length - 1 1084 * 1085 * Since we use a ring buffer, we have to handle the case 1086 * where head is lower than tail. In such a case, we first read from 1087 * tail to the end of the buffer then reset tail. 1088 */ 1089 if (ring->head < ring->tail) { 1090 count = sport->rx_sgl.length - ring->tail; 1091 1092 tty_insert_flip_string(port, ring->buf + ring->tail, count); 1093 ring->tail = 0; 1094 sport->port.icount.rx += count; 1095 } 1096 1097 /* Finally we read data from tail to head */ 1098 if (ring->tail < ring->head) { 1099 count = ring->head - ring->tail; 1100 tty_insert_flip_string(port, ring->buf + ring->tail, count); 1101 /* Wrap ring->head if needed */ 1102 if (ring->head >= sport->rx_sgl.length) 1103 ring->head = 0; 1104 ring->tail = ring->head; 1105 sport->port.icount.rx += count; 1106 } 1107 1108 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1, 1109 DMA_FROM_DEVICE); 1110 1111 spin_unlock_irqrestore(&sport->port.lock, flags); 1112 1113 tty_flip_buffer_push(port); 1114 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 1115 } 1116 1117 static void lpuart_dma_rx_complete(void *arg) 1118 { 1119 struct lpuart_port *sport = arg; 1120 1121 lpuart_copy_rx_to_tty(sport); 1122 } 1123 1124 static void lpuart_timer_func(struct timer_list *t) 1125 { 1126 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); 1127 1128 lpuart_copy_rx_to_tty(sport); 1129 } 1130 1131 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 1132 { 1133 struct dma_slave_config dma_rx_sconfig = {}; 1134 struct circ_buf *ring = &sport->rx_ring; 1135 int ret, nent; 1136 int bits, baud; 1137 struct tty_port *port = &sport->port.state->port; 1138 struct tty_struct *tty = port->tty; 1139 struct ktermios *termios = &tty->termios; 1140 1141 baud = tty_get_baud_rate(tty); 1142 1143 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; 1144 if (termios->c_cflag & PARENB) 1145 bits++; 1146 1147 /* 1148 * Calculate length of one DMA buffer size to keep latency below 1149 * 10ms at any baud rate. 1150 */ 1151 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 1152 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 1153 if (sport->rx_dma_rng_buf_len < 16) 1154 sport->rx_dma_rng_buf_len = 16; 1155 1156 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1157 if (!ring->buf) 1158 return -ENOMEM; 1159 1160 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1161 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1162 1163 if (!nent) { 1164 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1165 return -EINVAL; 1166 } 1167 1168 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); 1169 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1170 dma_rx_sconfig.src_maxburst = 1; 1171 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1172 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig); 1173 1174 if (ret < 0) { 1175 dev_err(sport->port.dev, 1176 "DMA Rx slave config failed, err = %d\n", ret); 1177 return ret; 1178 } 1179 1180 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan, 1181 sg_dma_address(&sport->rx_sgl), 1182 sport->rx_sgl.length, 1183 sport->rx_sgl.length / 2, 1184 DMA_DEV_TO_MEM, 1185 DMA_PREP_INTERRUPT); 1186 if (!sport->dma_rx_desc) { 1187 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1188 return -EFAULT; 1189 } 1190 1191 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1192 sport->dma_rx_desc->callback_param = sport; 1193 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1194 dma_async_issue_pending(sport->dma_rx_chan); 1195 1196 if (lpuart_is_32(sport)) { 1197 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); 1198 1199 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); 1200 } else { 1201 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1202 sport->port.membase + UARTCR5); 1203 } 1204 1205 return 0; 1206 } 1207 1208 static void lpuart_dma_rx_free(struct uart_port *port) 1209 { 1210 struct lpuart_port *sport = container_of(port, 1211 struct lpuart_port, port); 1212 1213 if (sport->dma_rx_chan) 1214 dmaengine_terminate_all(sport->dma_rx_chan); 1215 1216 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1217 kfree(sport->rx_ring.buf); 1218 sport->rx_ring.tail = 0; 1219 sport->rx_ring.head = 0; 1220 sport->dma_rx_desc = NULL; 1221 sport->dma_rx_cookie = -EINVAL; 1222 } 1223 1224 static int lpuart_config_rs485(struct uart_port *port, 1225 struct serial_rs485 *rs485) 1226 { 1227 struct lpuart_port *sport = container_of(port, 1228 struct lpuart_port, port); 1229 1230 u8 modem = readb(sport->port.membase + UARTMODEM) & 1231 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1232 writeb(modem, sport->port.membase + UARTMODEM); 1233 1234 /* clear unsupported configurations */ 1235 rs485->delay_rts_before_send = 0; 1236 rs485->delay_rts_after_send = 0; 1237 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1238 1239 if (rs485->flags & SER_RS485_ENABLED) { 1240 /* Enable auto RS-485 RTS mode */ 1241 modem |= UARTMODEM_TXRTSE; 1242 1243 /* 1244 * RTS needs to be logic HIGH either during transer _or_ after 1245 * transfer, other variants are not supported by the hardware. 1246 */ 1247 1248 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1249 SER_RS485_RTS_AFTER_SEND))) 1250 rs485->flags |= SER_RS485_RTS_ON_SEND; 1251 1252 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1253 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1254 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1255 1256 /* 1257 * The hardware defaults to RTS logic HIGH while transfer. 1258 * Switch polarity in case RTS shall be logic HIGH 1259 * after transfer. 1260 * Note: UART is assumed to be active high. 1261 */ 1262 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1263 modem &= ~UARTMODEM_TXRTSPOL; 1264 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1265 modem |= UARTMODEM_TXRTSPOL; 1266 } 1267 1268 /* Store the new configuration */ 1269 sport->port.rs485 = *rs485; 1270 1271 writeb(modem, sport->port.membase + UARTMODEM); 1272 return 0; 1273 } 1274 1275 static int lpuart32_config_rs485(struct uart_port *port, 1276 struct serial_rs485 *rs485) 1277 { 1278 struct lpuart_port *sport = container_of(port, 1279 struct lpuart_port, port); 1280 1281 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) 1282 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1283 lpuart32_write(&sport->port, modem, UARTMODIR); 1284 1285 /* clear unsupported configurations */ 1286 rs485->delay_rts_before_send = 0; 1287 rs485->delay_rts_after_send = 0; 1288 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1289 1290 if (rs485->flags & SER_RS485_ENABLED) { 1291 /* Enable auto RS-485 RTS mode */ 1292 modem |= UARTMODEM_TXRTSE; 1293 1294 /* 1295 * RTS needs to be logic HIGH either during transer _or_ after 1296 * transfer, other variants are not supported by the hardware. 1297 */ 1298 1299 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1300 SER_RS485_RTS_AFTER_SEND))) 1301 rs485->flags |= SER_RS485_RTS_ON_SEND; 1302 1303 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1304 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1305 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1306 1307 /* 1308 * The hardware defaults to RTS logic HIGH while transfer. 1309 * Switch polarity in case RTS shall be logic HIGH 1310 * after transfer. 1311 * Note: UART is assumed to be active high. 1312 */ 1313 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1314 modem &= ~UARTMODEM_TXRTSPOL; 1315 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1316 modem |= UARTMODEM_TXRTSPOL; 1317 } 1318 1319 /* Store the new configuration */ 1320 sport->port.rs485 = *rs485; 1321 1322 lpuart32_write(&sport->port, modem, UARTMODIR); 1323 return 0; 1324 } 1325 1326 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1327 { 1328 unsigned int temp = 0; 1329 unsigned char reg; 1330 1331 reg = readb(port->membase + UARTMODEM); 1332 if (reg & UARTMODEM_TXCTSE) 1333 temp |= TIOCM_CTS; 1334 1335 if (reg & UARTMODEM_RXRTSE) 1336 temp |= TIOCM_RTS; 1337 1338 return temp; 1339 } 1340 1341 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1342 { 1343 unsigned int temp = 0; 1344 unsigned long reg; 1345 1346 reg = lpuart32_read(port, UARTMODIR); 1347 if (reg & UARTMODIR_TXCTSE) 1348 temp |= TIOCM_CTS; 1349 1350 if (reg & UARTMODIR_RXRTSE) 1351 temp |= TIOCM_RTS; 1352 1353 return temp; 1354 } 1355 1356 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1357 { 1358 unsigned char temp; 1359 struct lpuart_port *sport = container_of(port, 1360 struct lpuart_port, port); 1361 1362 /* Make sure RXRTSE bit is not set when RS485 is enabled */ 1363 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { 1364 temp = readb(sport->port.membase + UARTMODEM) & 1365 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1366 1367 if (mctrl & TIOCM_RTS) 1368 temp |= UARTMODEM_RXRTSE; 1369 1370 if (mctrl & TIOCM_CTS) 1371 temp |= UARTMODEM_TXCTSE; 1372 1373 writeb(temp, port->membase + UARTMODEM); 1374 } 1375 } 1376 1377 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1378 { 1379 1380 } 1381 1382 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1383 { 1384 unsigned char temp; 1385 1386 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1387 1388 if (break_state != 0) 1389 temp |= UARTCR2_SBK; 1390 1391 writeb(temp, port->membase + UARTCR2); 1392 } 1393 1394 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1395 { 1396 unsigned long temp; 1397 1398 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; 1399 1400 if (break_state != 0) 1401 temp |= UARTCTRL_SBK; 1402 1403 lpuart32_write(port, temp, UARTCTRL); 1404 } 1405 1406 static void lpuart_setup_watermark(struct lpuart_port *sport) 1407 { 1408 unsigned char val, cr2; 1409 unsigned char cr2_saved; 1410 1411 cr2 = readb(sport->port.membase + UARTCR2); 1412 cr2_saved = cr2; 1413 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1414 UARTCR2_RIE | UARTCR2_RE); 1415 writeb(cr2, sport->port.membase + UARTCR2); 1416 1417 val = readb(sport->port.membase + UARTPFIFO); 1418 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1419 sport->port.membase + UARTPFIFO); 1420 1421 /* flush Tx and Rx FIFO */ 1422 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1423 sport->port.membase + UARTCFIFO); 1424 1425 /* explicitly clear RDRF */ 1426 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1427 readb(sport->port.membase + UARTDR); 1428 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1429 } 1430 1431 writeb(0, sport->port.membase + UARTTWFIFO); 1432 writeb(1, sport->port.membase + UARTRWFIFO); 1433 1434 /* Restore cr2 */ 1435 writeb(cr2_saved, sport->port.membase + UARTCR2); 1436 } 1437 1438 static void lpuart_setup_watermark_enable(struct lpuart_port *sport) 1439 { 1440 unsigned char cr2; 1441 1442 lpuart_setup_watermark(sport); 1443 1444 cr2 = readb(sport->port.membase + UARTCR2); 1445 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE; 1446 writeb(cr2, sport->port.membase + UARTCR2); 1447 } 1448 1449 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1450 { 1451 unsigned long val, ctrl; 1452 unsigned long ctrl_saved; 1453 1454 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1455 ctrl_saved = ctrl; 1456 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1457 UARTCTRL_RIE | UARTCTRL_RE); 1458 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1459 1460 /* enable FIFO mode */ 1461 val = lpuart32_read(&sport->port, UARTFIFO); 1462 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1463 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1464 lpuart32_write(&sport->port, val, UARTFIFO); 1465 1466 /* set the watermark */ 1467 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1468 lpuart32_write(&sport->port, val, UARTWATER); 1469 1470 /* Restore cr2 */ 1471 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1472 } 1473 1474 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) 1475 { 1476 u32 temp; 1477 1478 lpuart32_setup_watermark(sport); 1479 1480 temp = lpuart32_read(&sport->port, UARTCTRL); 1481 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE; 1482 lpuart32_write(&sport->port, temp, UARTCTRL); 1483 } 1484 1485 static void rx_dma_timer_init(struct lpuart_port *sport) 1486 { 1487 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); 1488 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1489 add_timer(&sport->lpuart_timer); 1490 } 1491 1492 static void lpuart_tx_dma_startup(struct lpuart_port *sport) 1493 { 1494 u32 uartbaud; 1495 1496 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) { 1497 init_waitqueue_head(&sport->dma_wait); 1498 sport->lpuart_dma_tx_use = true; 1499 if (lpuart_is_32(sport)) { 1500 uartbaud = lpuart32_read(&sport->port, UARTBAUD); 1501 lpuart32_write(&sport->port, 1502 uartbaud | UARTBAUD_TDMAE, UARTBAUD); 1503 } else { 1504 writeb(readb(sport->port.membase + UARTCR5) | 1505 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 1506 } 1507 } else { 1508 sport->lpuart_dma_tx_use = false; 1509 } 1510 } 1511 1512 static void lpuart_rx_dma_startup(struct lpuart_port *sport) 1513 { 1514 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) { 1515 /* set Rx DMA timeout */ 1516 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1517 if (!sport->dma_rx_timeout) 1518 sport->dma_rx_timeout = 1; 1519 1520 sport->lpuart_dma_rx_use = true; 1521 rx_dma_timer_init(sport); 1522 } else { 1523 sport->lpuart_dma_rx_use = false; 1524 } 1525 } 1526 1527 static int lpuart_startup(struct uart_port *port) 1528 { 1529 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1530 unsigned long flags; 1531 unsigned char temp; 1532 1533 /* determine FIFO size and enable FIFO mode */ 1534 temp = readb(sport->port.membase + UARTPFIFO); 1535 1536 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & 1537 UARTPFIFO_FIFOSIZE_MASK); 1538 sport->port.fifosize = sport->txfifo_size; 1539 1540 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & 1541 UARTPFIFO_FIFOSIZE_MASK); 1542 1543 spin_lock_irqsave(&sport->port.lock, flags); 1544 1545 lpuart_setup_watermark_enable(sport); 1546 1547 lpuart_rx_dma_startup(sport); 1548 lpuart_tx_dma_startup(sport); 1549 1550 spin_unlock_irqrestore(&sport->port.lock, flags); 1551 1552 return 0; 1553 } 1554 1555 static void lpuart32_configure(struct lpuart_port *sport) 1556 { 1557 unsigned long temp; 1558 1559 if (sport->lpuart_dma_rx_use) { 1560 /* RXWATER must be 0 */ 1561 temp = lpuart32_read(&sport->port, UARTWATER); 1562 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF); 1563 lpuart32_write(&sport->port, temp, UARTWATER); 1564 } 1565 temp = lpuart32_read(&sport->port, UARTCTRL); 1566 if (!sport->lpuart_dma_rx_use) 1567 temp |= UARTCTRL_RIE; 1568 if (!sport->lpuart_dma_tx_use) 1569 temp |= UARTCTRL_TIE; 1570 lpuart32_write(&sport->port, temp, UARTCTRL); 1571 } 1572 1573 static int lpuart32_startup(struct uart_port *port) 1574 { 1575 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1576 unsigned long flags; 1577 unsigned long temp; 1578 1579 /* determine FIFO size */ 1580 temp = lpuart32_read(&sport->port, UARTFIFO); 1581 1582 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & 1583 UARTFIFO_FIFOSIZE_MASK); 1584 sport->port.fifosize = sport->txfifo_size; 1585 1586 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & 1587 UARTFIFO_FIFOSIZE_MASK); 1588 1589 spin_lock_irqsave(&sport->port.lock, flags); 1590 1591 lpuart32_setup_watermark_enable(sport); 1592 1593 1594 lpuart_rx_dma_startup(sport); 1595 lpuart_tx_dma_startup(sport); 1596 1597 lpuart32_configure(sport); 1598 1599 spin_unlock_irqrestore(&sport->port.lock, flags); 1600 return 0; 1601 } 1602 1603 static void lpuart_dma_shutdown(struct lpuart_port *sport) 1604 { 1605 if (sport->lpuart_dma_rx_use) { 1606 del_timer_sync(&sport->lpuart_timer); 1607 lpuart_dma_rx_free(&sport->port); 1608 } 1609 1610 if (sport->lpuart_dma_tx_use) { 1611 if (wait_event_interruptible(sport->dma_wait, 1612 !sport->dma_tx_in_progress) != false) { 1613 sport->dma_tx_in_progress = false; 1614 dmaengine_terminate_all(sport->dma_tx_chan); 1615 } 1616 } 1617 } 1618 1619 static void lpuart_shutdown(struct uart_port *port) 1620 { 1621 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1622 unsigned char temp; 1623 unsigned long flags; 1624 1625 spin_lock_irqsave(&port->lock, flags); 1626 1627 /* disable Rx/Tx and interrupts */ 1628 temp = readb(port->membase + UARTCR2); 1629 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1630 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1631 writeb(temp, port->membase + UARTCR2); 1632 1633 spin_unlock_irqrestore(&port->lock, flags); 1634 1635 lpuart_dma_shutdown(sport); 1636 } 1637 1638 static void lpuart32_shutdown(struct uart_port *port) 1639 { 1640 struct lpuart_port *sport = 1641 container_of(port, struct lpuart_port, port); 1642 unsigned long temp; 1643 unsigned long flags; 1644 1645 spin_lock_irqsave(&port->lock, flags); 1646 1647 /* disable Rx/Tx and interrupts */ 1648 temp = lpuart32_read(port, UARTCTRL); 1649 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1650 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1651 lpuart32_write(port, temp, UARTCTRL); 1652 1653 spin_unlock_irqrestore(&port->lock, flags); 1654 1655 lpuart_dma_shutdown(sport); 1656 } 1657 1658 static void 1659 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1660 struct ktermios *old) 1661 { 1662 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1663 unsigned long flags; 1664 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1665 unsigned int baud; 1666 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1667 unsigned int sbr, brfa; 1668 1669 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1670 old_cr2 = readb(sport->port.membase + UARTCR2); 1671 cr3 = readb(sport->port.membase + UARTCR3); 1672 cr4 = readb(sport->port.membase + UARTCR4); 1673 bdh = readb(sport->port.membase + UARTBDH); 1674 modem = readb(sport->port.membase + UARTMODEM); 1675 /* 1676 * only support CS8 and CS7, and for CS7 must enable PE. 1677 * supported mode: 1678 * - (7,e/o,1) 1679 * - (8,n,1) 1680 * - (8,m/s,1) 1681 * - (8,e/o,1) 1682 */ 1683 while ((termios->c_cflag & CSIZE) != CS8 && 1684 (termios->c_cflag & CSIZE) != CS7) { 1685 termios->c_cflag &= ~CSIZE; 1686 termios->c_cflag |= old_csize; 1687 old_csize = CS8; 1688 } 1689 1690 if ((termios->c_cflag & CSIZE) == CS8 || 1691 (termios->c_cflag & CSIZE) == CS7) 1692 cr1 = old_cr1 & ~UARTCR1_M; 1693 1694 if (termios->c_cflag & CMSPAR) { 1695 if ((termios->c_cflag & CSIZE) != CS8) { 1696 termios->c_cflag &= ~CSIZE; 1697 termios->c_cflag |= CS8; 1698 } 1699 cr1 |= UARTCR1_M; 1700 } 1701 1702 /* 1703 * When auto RS-485 RTS mode is enabled, 1704 * hardware flow control need to be disabled. 1705 */ 1706 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1707 termios->c_cflag &= ~CRTSCTS; 1708 1709 if (termios->c_cflag & CRTSCTS) 1710 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE; 1711 else 1712 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1713 1714 termios->c_cflag &= ~CSTOPB; 1715 1716 /* parity must be enabled when CS7 to match 8-bits format */ 1717 if ((termios->c_cflag & CSIZE) == CS7) 1718 termios->c_cflag |= PARENB; 1719 1720 if (termios->c_cflag & PARENB) { 1721 if (termios->c_cflag & CMSPAR) { 1722 cr1 &= ~UARTCR1_PE; 1723 if (termios->c_cflag & PARODD) 1724 cr3 |= UARTCR3_T8; 1725 else 1726 cr3 &= ~UARTCR3_T8; 1727 } else { 1728 cr1 |= UARTCR1_PE; 1729 if ((termios->c_cflag & CSIZE) == CS8) 1730 cr1 |= UARTCR1_M; 1731 if (termios->c_cflag & PARODD) 1732 cr1 |= UARTCR1_PT; 1733 else 1734 cr1 &= ~UARTCR1_PT; 1735 } 1736 } else { 1737 cr1 &= ~UARTCR1_PE; 1738 } 1739 1740 /* ask the core to calculate the divisor */ 1741 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1742 1743 /* 1744 * Need to update the Ring buffer length according to the selected 1745 * baud rate and restart Rx DMA path. 1746 * 1747 * Since timer function acqures sport->port.lock, need to stop before 1748 * acquring same lock because otherwise del_timer_sync() can deadlock. 1749 */ 1750 if (old && sport->lpuart_dma_rx_use) { 1751 del_timer_sync(&sport->lpuart_timer); 1752 lpuart_dma_rx_free(&sport->port); 1753 } 1754 1755 spin_lock_irqsave(&sport->port.lock, flags); 1756 1757 sport->port.read_status_mask = 0; 1758 if (termios->c_iflag & INPCK) 1759 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; 1760 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1761 sport->port.read_status_mask |= UARTSR1_FE; 1762 1763 /* characters to ignore */ 1764 sport->port.ignore_status_mask = 0; 1765 if (termios->c_iflag & IGNPAR) 1766 sport->port.ignore_status_mask |= UARTSR1_PE; 1767 if (termios->c_iflag & IGNBRK) { 1768 sport->port.ignore_status_mask |= UARTSR1_FE; 1769 /* 1770 * if we're ignoring parity and break indicators, 1771 * ignore overruns too (for real raw support). 1772 */ 1773 if (termios->c_iflag & IGNPAR) 1774 sport->port.ignore_status_mask |= UARTSR1_OR; 1775 } 1776 1777 /* update the per-port timeout */ 1778 uart_update_timeout(port, termios->c_cflag, baud); 1779 1780 /* wait transmit engin complete */ 1781 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 1782 1783 /* disable transmit and receive */ 1784 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1785 sport->port.membase + UARTCR2); 1786 1787 sbr = sport->port.uartclk / (16 * baud); 1788 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1789 bdh &= ~UARTBDH_SBR_MASK; 1790 bdh |= (sbr >> 8) & 0x1F; 1791 cr4 &= ~UARTCR4_BRFA_MASK; 1792 brfa &= UARTCR4_BRFA_MASK; 1793 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1794 writeb(bdh, sport->port.membase + UARTBDH); 1795 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1796 writeb(cr3, sport->port.membase + UARTCR3); 1797 writeb(cr1, sport->port.membase + UARTCR1); 1798 writeb(modem, sport->port.membase + UARTMODEM); 1799 1800 /* restore control register */ 1801 writeb(old_cr2, sport->port.membase + UARTCR2); 1802 1803 if (old && sport->lpuart_dma_rx_use) { 1804 if (!lpuart_start_rx_dma(sport)) 1805 rx_dma_timer_init(sport); 1806 else 1807 sport->lpuart_dma_rx_use = false; 1808 } 1809 1810 spin_unlock_irqrestore(&sport->port.lock, flags); 1811 } 1812 1813 static void 1814 lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate) 1815 { 1816 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; 1817 u32 clk = sport->port.uartclk; 1818 1819 /* 1820 * The idea is to use the best OSR (over-sampling rate) possible. 1821 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 1822 * Loop to find the best OSR value possible, one that generates minimum 1823 * baud_diff iterate through the rest of the supported values of OSR. 1824 * 1825 * Calculation Formula: 1826 * Baud Rate = baud clock / ((OSR+1) × SBR) 1827 */ 1828 baud_diff = baudrate; 1829 osr = 0; 1830 sbr = 0; 1831 1832 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 1833 /* calculate the temporary sbr value */ 1834 tmp_sbr = (clk / (baudrate * tmp_osr)); 1835 if (tmp_sbr == 0) 1836 tmp_sbr = 1; 1837 1838 /* 1839 * calculate the baud rate difference based on the temporary 1840 * osr and sbr values 1841 */ 1842 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 1843 1844 /* select best values between sbr and sbr+1 */ 1845 tmp = clk / (tmp_osr * (tmp_sbr + 1)); 1846 if (tmp_diff > (baudrate - tmp)) { 1847 tmp_diff = baudrate - tmp; 1848 tmp_sbr++; 1849 } 1850 1851 if (tmp_diff <= baud_diff) { 1852 baud_diff = tmp_diff; 1853 osr = tmp_osr; 1854 sbr = tmp_sbr; 1855 1856 if (!baud_diff) 1857 break; 1858 } 1859 } 1860 1861 /* handle buadrate outside acceptable rate */ 1862 if (baud_diff > ((baudrate / 100) * 3)) 1863 dev_warn(sport->port.dev, 1864 "unacceptable baud rate difference of more than 3%%\n"); 1865 1866 tmp = lpuart32_read(&sport->port, UARTBAUD); 1867 1868 if ((osr > 3) && (osr < 8)) 1869 tmp |= UARTBAUD_BOTHEDGE; 1870 1871 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 1872 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; 1873 1874 tmp &= ~UARTBAUD_SBR_MASK; 1875 tmp |= sbr & UARTBAUD_SBR_MASK; 1876 1877 if (!sport->lpuart_dma_rx_use) 1878 tmp &= ~UARTBAUD_RDMAE; 1879 if (!sport->lpuart_dma_tx_use) 1880 tmp &= ~UARTBAUD_TDMAE; 1881 1882 lpuart32_write(&sport->port, tmp, UARTBAUD); 1883 } 1884 1885 static void 1886 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 1887 struct ktermios *old) 1888 { 1889 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1890 unsigned long flags; 1891 unsigned long ctrl, old_ctrl, modem; 1892 unsigned int baud; 1893 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1894 1895 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); 1896 modem = lpuart32_read(&sport->port, UARTMODIR); 1897 /* 1898 * only support CS8 and CS7, and for CS7 must enable PE. 1899 * supported mode: 1900 * - (7,e/o,1) 1901 * - (8,n,1) 1902 * - (8,m/s,1) 1903 * - (8,e/o,1) 1904 */ 1905 while ((termios->c_cflag & CSIZE) != CS8 && 1906 (termios->c_cflag & CSIZE) != CS7) { 1907 termios->c_cflag &= ~CSIZE; 1908 termios->c_cflag |= old_csize; 1909 old_csize = CS8; 1910 } 1911 1912 if ((termios->c_cflag & CSIZE) == CS8 || 1913 (termios->c_cflag & CSIZE) == CS7) 1914 ctrl = old_ctrl & ~UARTCTRL_M; 1915 1916 if (termios->c_cflag & CMSPAR) { 1917 if ((termios->c_cflag & CSIZE) != CS8) { 1918 termios->c_cflag &= ~CSIZE; 1919 termios->c_cflag |= CS8; 1920 } 1921 ctrl |= UARTCTRL_M; 1922 } 1923 1924 /* 1925 * When auto RS-485 RTS mode is enabled, 1926 * hardware flow control need to be disabled. 1927 */ 1928 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1929 termios->c_cflag &= ~CRTSCTS; 1930 1931 if (termios->c_cflag & CRTSCTS) { 1932 modem |= (UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 1933 } else { 1934 termios->c_cflag &= ~CRTSCTS; 1935 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 1936 } 1937 1938 if (termios->c_cflag & CSTOPB) 1939 termios->c_cflag &= ~CSTOPB; 1940 1941 /* parity must be enabled when CS7 to match 8-bits format */ 1942 if ((termios->c_cflag & CSIZE) == CS7) 1943 termios->c_cflag |= PARENB; 1944 1945 if ((termios->c_cflag & PARENB)) { 1946 if (termios->c_cflag & CMSPAR) { 1947 ctrl &= ~UARTCTRL_PE; 1948 ctrl |= UARTCTRL_M; 1949 } else { 1950 ctrl |= UARTCTRL_PE; 1951 if ((termios->c_cflag & CSIZE) == CS8) 1952 ctrl |= UARTCTRL_M; 1953 if (termios->c_cflag & PARODD) 1954 ctrl |= UARTCTRL_PT; 1955 else 1956 ctrl &= ~UARTCTRL_PT; 1957 } 1958 } else { 1959 ctrl &= ~UARTCTRL_PE; 1960 } 1961 1962 /* ask the core to calculate the divisor */ 1963 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); 1964 1965 /* 1966 * Need to update the Ring buffer length according to the selected 1967 * baud rate and restart Rx DMA path. 1968 * 1969 * Since timer function acqures sport->port.lock, need to stop before 1970 * acquring same lock because otherwise del_timer_sync() can deadlock. 1971 */ 1972 if (old && sport->lpuart_dma_rx_use) { 1973 del_timer_sync(&sport->lpuart_timer); 1974 lpuart_dma_rx_free(&sport->port); 1975 } 1976 1977 spin_lock_irqsave(&sport->port.lock, flags); 1978 1979 sport->port.read_status_mask = 0; 1980 if (termios->c_iflag & INPCK) 1981 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; 1982 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1983 sport->port.read_status_mask |= UARTSTAT_FE; 1984 1985 /* characters to ignore */ 1986 sport->port.ignore_status_mask = 0; 1987 if (termios->c_iflag & IGNPAR) 1988 sport->port.ignore_status_mask |= UARTSTAT_PE; 1989 if (termios->c_iflag & IGNBRK) { 1990 sport->port.ignore_status_mask |= UARTSTAT_FE; 1991 /* 1992 * if we're ignoring parity and break indicators, 1993 * ignore overruns too (for real raw support). 1994 */ 1995 if (termios->c_iflag & IGNPAR) 1996 sport->port.ignore_status_mask |= UARTSTAT_OR; 1997 } 1998 1999 /* update the per-port timeout */ 2000 uart_update_timeout(port, termios->c_cflag, baud); 2001 2002 /* wait transmit engin complete */ 2003 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2004 2005 /* disable transmit and receive */ 2006 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 2007 UARTCTRL); 2008 2009 lpuart32_serial_setbrg(sport, baud); 2010 lpuart32_write(&sport->port, modem, UARTMODIR); 2011 lpuart32_write(&sport->port, ctrl, UARTCTRL); 2012 /* restore control register */ 2013 2014 if (old && sport->lpuart_dma_rx_use) { 2015 if (!lpuart_start_rx_dma(sport)) 2016 rx_dma_timer_init(sport); 2017 else 2018 sport->lpuart_dma_rx_use = false; 2019 } 2020 2021 spin_unlock_irqrestore(&sport->port.lock, flags); 2022 } 2023 2024 static const char *lpuart_type(struct uart_port *port) 2025 { 2026 return "FSL_LPUART"; 2027 } 2028 2029 static void lpuart_release_port(struct uart_port *port) 2030 { 2031 /* nothing to do */ 2032 } 2033 2034 static int lpuart_request_port(struct uart_port *port) 2035 { 2036 return 0; 2037 } 2038 2039 /* configure/autoconfigure the port */ 2040 static void lpuart_config_port(struct uart_port *port, int flags) 2041 { 2042 if (flags & UART_CONFIG_TYPE) 2043 port->type = PORT_LPUART; 2044 } 2045 2046 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 2047 { 2048 int ret = 0; 2049 2050 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 2051 ret = -EINVAL; 2052 if (port->irq != ser->irq) 2053 ret = -EINVAL; 2054 if (ser->io_type != UPIO_MEM) 2055 ret = -EINVAL; 2056 if (port->uartclk / 16 != ser->baud_base) 2057 ret = -EINVAL; 2058 if (port->iobase != ser->port) 2059 ret = -EINVAL; 2060 if (ser->hub6 != 0) 2061 ret = -EINVAL; 2062 return ret; 2063 } 2064 2065 static const struct uart_ops lpuart_pops = { 2066 .tx_empty = lpuart_tx_empty, 2067 .set_mctrl = lpuart_set_mctrl, 2068 .get_mctrl = lpuart_get_mctrl, 2069 .stop_tx = lpuart_stop_tx, 2070 .start_tx = lpuart_start_tx, 2071 .stop_rx = lpuart_stop_rx, 2072 .break_ctl = lpuart_break_ctl, 2073 .startup = lpuart_startup, 2074 .shutdown = lpuart_shutdown, 2075 .set_termios = lpuart_set_termios, 2076 .type = lpuart_type, 2077 .request_port = lpuart_request_port, 2078 .release_port = lpuart_release_port, 2079 .config_port = lpuart_config_port, 2080 .verify_port = lpuart_verify_port, 2081 .flush_buffer = lpuart_flush_buffer, 2082 #if defined(CONFIG_CONSOLE_POLL) 2083 .poll_init = lpuart_poll_init, 2084 .poll_get_char = lpuart_poll_get_char, 2085 .poll_put_char = lpuart_poll_put_char, 2086 #endif 2087 }; 2088 2089 static const struct uart_ops lpuart32_pops = { 2090 .tx_empty = lpuart32_tx_empty, 2091 .set_mctrl = lpuart32_set_mctrl, 2092 .get_mctrl = lpuart32_get_mctrl, 2093 .stop_tx = lpuart32_stop_tx, 2094 .start_tx = lpuart32_start_tx, 2095 .stop_rx = lpuart32_stop_rx, 2096 .break_ctl = lpuart32_break_ctl, 2097 .startup = lpuart32_startup, 2098 .shutdown = lpuart32_shutdown, 2099 .set_termios = lpuart32_set_termios, 2100 .type = lpuart_type, 2101 .request_port = lpuart_request_port, 2102 .release_port = lpuart_release_port, 2103 .config_port = lpuart_config_port, 2104 .verify_port = lpuart_verify_port, 2105 .flush_buffer = lpuart_flush_buffer, 2106 #if defined(CONFIG_CONSOLE_POLL) 2107 .poll_init = lpuart32_poll_init, 2108 .poll_get_char = lpuart32_poll_get_char, 2109 .poll_put_char = lpuart32_poll_put_char, 2110 #endif 2111 }; 2112 2113 static struct lpuart_port *lpuart_ports[UART_NR]; 2114 2115 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 2116 static void lpuart_console_putchar(struct uart_port *port, int ch) 2117 { 2118 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 2119 writeb(ch, port->membase + UARTDR); 2120 } 2121 2122 static void lpuart32_console_putchar(struct uart_port *port, int ch) 2123 { 2124 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 2125 lpuart32_write(port, ch, UARTDATA); 2126 } 2127 2128 static void 2129 lpuart_console_write(struct console *co, const char *s, unsigned int count) 2130 { 2131 struct lpuart_port *sport = lpuart_ports[co->index]; 2132 unsigned char old_cr2, cr2; 2133 unsigned long flags; 2134 int locked = 1; 2135 2136 if (sport->port.sysrq || oops_in_progress) 2137 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2138 else 2139 spin_lock_irqsave(&sport->port.lock, flags); 2140 2141 /* first save CR2 and then disable interrupts */ 2142 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 2143 cr2 |= UARTCR2_TE | UARTCR2_RE; 2144 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 2145 writeb(cr2, sport->port.membase + UARTCR2); 2146 2147 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 2148 2149 /* wait for transmitter finish complete and restore CR2 */ 2150 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 2151 2152 writeb(old_cr2, sport->port.membase + UARTCR2); 2153 2154 if (locked) 2155 spin_unlock_irqrestore(&sport->port.lock, flags); 2156 } 2157 2158 static void 2159 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 2160 { 2161 struct lpuart_port *sport = lpuart_ports[co->index]; 2162 unsigned long old_cr, cr; 2163 unsigned long flags; 2164 int locked = 1; 2165 2166 if (sport->port.sysrq || oops_in_progress) 2167 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2168 else 2169 spin_lock_irqsave(&sport->port.lock, flags); 2170 2171 /* first save CR2 and then disable interrupts */ 2172 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 2173 cr |= UARTCTRL_TE | UARTCTRL_RE; 2174 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 2175 lpuart32_write(&sport->port, cr, UARTCTRL); 2176 2177 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 2178 2179 /* wait for transmitter finish complete and restore CR2 */ 2180 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2181 2182 lpuart32_write(&sport->port, old_cr, UARTCTRL); 2183 2184 if (locked) 2185 spin_unlock_irqrestore(&sport->port.lock, flags); 2186 } 2187 2188 /* 2189 * if the port was already initialised (eg, by a boot loader), 2190 * try to determine the current setup. 2191 */ 2192 static void __init 2193 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 2194 int *parity, int *bits) 2195 { 2196 unsigned char cr, bdh, bdl, brfa; 2197 unsigned int sbr, uartclk, baud_raw; 2198 2199 cr = readb(sport->port.membase + UARTCR2); 2200 cr &= UARTCR2_TE | UARTCR2_RE; 2201 if (!cr) 2202 return; 2203 2204 /* ok, the port was enabled */ 2205 2206 cr = readb(sport->port.membase + UARTCR1); 2207 2208 *parity = 'n'; 2209 if (cr & UARTCR1_PE) { 2210 if (cr & UARTCR1_PT) 2211 *parity = 'o'; 2212 else 2213 *parity = 'e'; 2214 } 2215 2216 if (cr & UARTCR1_M) 2217 *bits = 9; 2218 else 2219 *bits = 8; 2220 2221 bdh = readb(sport->port.membase + UARTBDH); 2222 bdh &= UARTBDH_SBR_MASK; 2223 bdl = readb(sport->port.membase + UARTBDL); 2224 sbr = bdh; 2225 sbr <<= 8; 2226 sbr |= bdl; 2227 brfa = readb(sport->port.membase + UARTCR4); 2228 brfa &= UARTCR4_BRFA_MASK; 2229 2230 uartclk = lpuart_get_baud_clk_rate(sport); 2231 /* 2232 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2233 */ 2234 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 2235 2236 if (*baud != baud_raw) 2237 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2238 "from %d to %d\n", baud_raw, *baud); 2239 } 2240 2241 static void __init 2242 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 2243 int *parity, int *bits) 2244 { 2245 unsigned long cr, bd; 2246 unsigned int sbr, uartclk, baud_raw; 2247 2248 cr = lpuart32_read(&sport->port, UARTCTRL); 2249 cr &= UARTCTRL_TE | UARTCTRL_RE; 2250 if (!cr) 2251 return; 2252 2253 /* ok, the port was enabled */ 2254 2255 cr = lpuart32_read(&sport->port, UARTCTRL); 2256 2257 *parity = 'n'; 2258 if (cr & UARTCTRL_PE) { 2259 if (cr & UARTCTRL_PT) 2260 *parity = 'o'; 2261 else 2262 *parity = 'e'; 2263 } 2264 2265 if (cr & UARTCTRL_M) 2266 *bits = 9; 2267 else 2268 *bits = 8; 2269 2270 bd = lpuart32_read(&sport->port, UARTBAUD); 2271 bd &= UARTBAUD_SBR_MASK; 2272 sbr = bd; 2273 uartclk = lpuart_get_baud_clk_rate(sport); 2274 /* 2275 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2276 */ 2277 baud_raw = uartclk / (16 * sbr); 2278 2279 if (*baud != baud_raw) 2280 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2281 "from %d to %d\n", baud_raw, *baud); 2282 } 2283 2284 static int __init lpuart_console_setup(struct console *co, char *options) 2285 { 2286 struct lpuart_port *sport; 2287 int baud = 115200; 2288 int bits = 8; 2289 int parity = 'n'; 2290 int flow = 'n'; 2291 2292 /* 2293 * check whether an invalid uart number has been specified, and 2294 * if so, search for the first available port that does have 2295 * console support. 2296 */ 2297 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2298 co->index = 0; 2299 2300 sport = lpuart_ports[co->index]; 2301 if (sport == NULL) 2302 return -ENODEV; 2303 2304 if (options) 2305 uart_parse_options(options, &baud, &parity, &bits, &flow); 2306 else 2307 if (lpuart_is_32(sport)) 2308 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2309 else 2310 lpuart_console_get_options(sport, &baud, &parity, &bits); 2311 2312 if (lpuart_is_32(sport)) 2313 lpuart32_setup_watermark(sport); 2314 else 2315 lpuart_setup_watermark(sport); 2316 2317 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2318 } 2319 2320 static struct uart_driver lpuart_reg; 2321 static struct console lpuart_console = { 2322 .name = DEV_NAME, 2323 .write = lpuart_console_write, 2324 .device = uart_console_device, 2325 .setup = lpuart_console_setup, 2326 .flags = CON_PRINTBUFFER, 2327 .index = -1, 2328 .data = &lpuart_reg, 2329 }; 2330 2331 static struct console lpuart32_console = { 2332 .name = DEV_NAME, 2333 .write = lpuart32_console_write, 2334 .device = uart_console_device, 2335 .setup = lpuart_console_setup, 2336 .flags = CON_PRINTBUFFER, 2337 .index = -1, 2338 .data = &lpuart_reg, 2339 }; 2340 2341 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2342 { 2343 struct earlycon_device *dev = con->data; 2344 2345 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2346 } 2347 2348 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2349 { 2350 struct earlycon_device *dev = con->data; 2351 2352 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2353 } 2354 2355 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2356 const char *opt) 2357 { 2358 if (!device->port.membase) 2359 return -ENODEV; 2360 2361 device->con->write = lpuart_early_write; 2362 return 0; 2363 } 2364 2365 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2366 const char *opt) 2367 { 2368 if (!device->port.membase) 2369 return -ENODEV; 2370 2371 if (device->port.iotype != UPIO_MEM32) 2372 device->port.iotype = UPIO_MEM32BE; 2373 2374 device->con->write = lpuart32_early_write; 2375 return 0; 2376 } 2377 2378 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2379 const char *opt) 2380 { 2381 if (!device->port.membase) 2382 return -ENODEV; 2383 2384 device->port.iotype = UPIO_MEM32; 2385 device->port.membase += IMX_REG_OFF; 2386 device->con->write = lpuart32_early_write; 2387 2388 return 0; 2389 } 2390 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2391 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2392 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2393 2394 #define LPUART_CONSOLE (&lpuart_console) 2395 #define LPUART32_CONSOLE (&lpuart32_console) 2396 #else 2397 #define LPUART_CONSOLE NULL 2398 #define LPUART32_CONSOLE NULL 2399 #endif 2400 2401 static struct uart_driver lpuart_reg = { 2402 .owner = THIS_MODULE, 2403 .driver_name = DRIVER_NAME, 2404 .dev_name = DEV_NAME, 2405 .nr = ARRAY_SIZE(lpuart_ports), 2406 .cons = LPUART_CONSOLE, 2407 }; 2408 2409 static int lpuart_probe(struct platform_device *pdev) 2410 { 2411 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids, 2412 &pdev->dev); 2413 const struct lpuart_soc_data *sdata = of_id->data; 2414 struct device_node *np = pdev->dev.of_node; 2415 struct lpuart_port *sport; 2416 struct resource *res; 2417 int ret; 2418 2419 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2420 if (!sport) 2421 return -ENOMEM; 2422 2423 ret = of_alias_get_id(np, "serial"); 2424 if (ret < 0) { 2425 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL); 2426 if (ret < 0) { 2427 dev_err(&pdev->dev, "port line is full, add device failed\n"); 2428 return ret; 2429 } 2430 } 2431 if (ret >= ARRAY_SIZE(lpuart_ports)) { 2432 dev_err(&pdev->dev, "serial%d out of range\n", ret); 2433 return -EINVAL; 2434 } 2435 sport->port.line = ret; 2436 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2437 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 2438 if (IS_ERR(sport->port.membase)) 2439 return PTR_ERR(sport->port.membase); 2440 2441 sport->port.membase += sdata->reg_off; 2442 sport->port.mapbase = res->start; 2443 sport->port.dev = &pdev->dev; 2444 sport->port.type = PORT_LPUART; 2445 sport->devtype = sdata->devtype; 2446 ret = platform_get_irq(pdev, 0); 2447 if (ret < 0) 2448 return ret; 2449 sport->port.irq = ret; 2450 sport->port.iotype = sdata->iotype; 2451 if (lpuart_is_32(sport)) 2452 sport->port.ops = &lpuart32_pops; 2453 else 2454 sport->port.ops = &lpuart_pops; 2455 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); 2456 sport->port.flags = UPF_BOOT_AUTOCONF; 2457 2458 if (lpuart_is_32(sport)) 2459 sport->port.rs485_config = lpuart32_config_rs485; 2460 else 2461 sport->port.rs485_config = lpuart_config_rs485; 2462 2463 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 2464 if (IS_ERR(sport->ipg_clk)) { 2465 ret = PTR_ERR(sport->ipg_clk); 2466 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); 2467 return ret; 2468 } 2469 2470 sport->baud_clk = NULL; 2471 if (is_imx8qxp_lpuart(sport)) { 2472 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); 2473 if (IS_ERR(sport->baud_clk)) { 2474 ret = PTR_ERR(sport->baud_clk); 2475 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); 2476 return ret; 2477 } 2478 } 2479 2480 ret = lpuart_enable_clks(sport); 2481 if (ret) 2482 return ret; 2483 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); 2484 2485 lpuart_ports[sport->port.line] = sport; 2486 2487 platform_set_drvdata(pdev, &sport->port); 2488 2489 if (lpuart_is_32(sport)) { 2490 lpuart_reg.cons = LPUART32_CONSOLE; 2491 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0, 2492 DRIVER_NAME, sport); 2493 } else { 2494 lpuart_reg.cons = LPUART_CONSOLE; 2495 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0, 2496 DRIVER_NAME, sport); 2497 } 2498 2499 if (ret) 2500 goto failed_irq_request; 2501 2502 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2503 if (ret) 2504 goto failed_attach_port; 2505 2506 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2507 2508 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX) 2509 dev_err(&pdev->dev, "driver doesn't support RX during TX\n"); 2510 2511 if (sport->port.rs485.delay_rts_before_send || 2512 sport->port.rs485.delay_rts_after_send) 2513 dev_err(&pdev->dev, "driver doesn't support RTS delays\n"); 2514 2515 sport->port.rs485_config(&sport->port, &sport->port.rs485); 2516 2517 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx"); 2518 if (!sport->dma_tx_chan) 2519 dev_info(sport->port.dev, "DMA tx channel request failed, " 2520 "operating without tx DMA\n"); 2521 2522 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx"); 2523 if (!sport->dma_rx_chan) 2524 dev_info(sport->port.dev, "DMA rx channel request failed, " 2525 "operating without rx DMA\n"); 2526 2527 return 0; 2528 2529 failed_attach_port: 2530 failed_irq_request: 2531 lpuart_disable_clks(sport); 2532 return ret; 2533 } 2534 2535 static int lpuart_remove(struct platform_device *pdev) 2536 { 2537 struct lpuart_port *sport = platform_get_drvdata(pdev); 2538 2539 uart_remove_one_port(&lpuart_reg, &sport->port); 2540 2541 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); 2542 2543 lpuart_disable_clks(sport); 2544 2545 if (sport->dma_tx_chan) 2546 dma_release_channel(sport->dma_tx_chan); 2547 2548 if (sport->dma_rx_chan) 2549 dma_release_channel(sport->dma_rx_chan); 2550 2551 return 0; 2552 } 2553 2554 #ifdef CONFIG_PM_SLEEP 2555 static int lpuart_suspend(struct device *dev) 2556 { 2557 struct lpuart_port *sport = dev_get_drvdata(dev); 2558 unsigned long temp; 2559 bool irq_wake; 2560 2561 if (lpuart_is_32(sport)) { 2562 /* disable Rx/Tx and interrupts */ 2563 temp = lpuart32_read(&sport->port, UARTCTRL); 2564 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2565 lpuart32_write(&sport->port, temp, UARTCTRL); 2566 } else { 2567 /* disable Rx/Tx and interrupts */ 2568 temp = readb(sport->port.membase + UARTCR2); 2569 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2570 writeb(temp, sport->port.membase + UARTCR2); 2571 } 2572 2573 uart_suspend_port(&lpuart_reg, &sport->port); 2574 2575 /* uart_suspend_port() might set wakeup flag */ 2576 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2577 2578 if (sport->lpuart_dma_rx_use) { 2579 /* 2580 * EDMA driver during suspend will forcefully release any 2581 * non-idle DMA channels. If port wakeup is enabled or if port 2582 * is console port or 'no_console_suspend' is set the Rx DMA 2583 * cannot resume as as expected, hence gracefully release the 2584 * Rx DMA path before suspend and start Rx DMA path on resume. 2585 */ 2586 if (irq_wake) { 2587 del_timer_sync(&sport->lpuart_timer); 2588 lpuart_dma_rx_free(&sport->port); 2589 } 2590 2591 /* Disable Rx DMA to use UART port as wakeup source */ 2592 if (lpuart_is_32(sport)) { 2593 temp = lpuart32_read(&sport->port, UARTBAUD); 2594 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, 2595 UARTBAUD); 2596 } else { 2597 writeb(readb(sport->port.membase + UARTCR5) & 2598 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 2599 } 2600 } 2601 2602 if (sport->lpuart_dma_tx_use) { 2603 sport->dma_tx_in_progress = false; 2604 dmaengine_terminate_all(sport->dma_tx_chan); 2605 } 2606 2607 if (sport->port.suspended && !irq_wake) 2608 lpuart_disable_clks(sport); 2609 2610 return 0; 2611 } 2612 2613 static int lpuart_resume(struct device *dev) 2614 { 2615 struct lpuart_port *sport = dev_get_drvdata(dev); 2616 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2617 2618 if (sport->port.suspended && !irq_wake) 2619 lpuart_enable_clks(sport); 2620 2621 if (lpuart_is_32(sport)) 2622 lpuart32_setup_watermark_enable(sport); 2623 else 2624 lpuart_setup_watermark_enable(sport); 2625 2626 if (sport->lpuart_dma_rx_use) { 2627 if (irq_wake) { 2628 if (!lpuart_start_rx_dma(sport)) 2629 rx_dma_timer_init(sport); 2630 else 2631 sport->lpuart_dma_rx_use = false; 2632 } 2633 } 2634 2635 lpuart_tx_dma_startup(sport); 2636 2637 if (lpuart_is_32(sport)) 2638 lpuart32_configure(sport); 2639 2640 uart_resume_port(&lpuart_reg, &sport->port); 2641 2642 return 0; 2643 } 2644 #endif 2645 2646 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2647 2648 static struct platform_driver lpuart_driver = { 2649 .probe = lpuart_probe, 2650 .remove = lpuart_remove, 2651 .driver = { 2652 .name = "fsl-lpuart", 2653 .of_match_table = lpuart_dt_ids, 2654 .pm = &lpuart_pm_ops, 2655 }, 2656 }; 2657 2658 static int __init lpuart_serial_init(void) 2659 { 2660 int ret = uart_register_driver(&lpuart_reg); 2661 2662 if (ret) 2663 return ret; 2664 2665 ret = platform_driver_register(&lpuart_driver); 2666 if (ret) 2667 uart_unregister_driver(&lpuart_reg); 2668 2669 return ret; 2670 } 2671 2672 static void __exit lpuart_serial_exit(void) 2673 { 2674 ida_destroy(&fsl_lpuart_ida); 2675 platform_driver_unregister(&lpuart_driver); 2676 uart_unregister_driver(&lpuart_reg); 2677 } 2678 2679 module_init(lpuart_serial_init); 2680 module_exit(lpuart_serial_exit); 2681 2682 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2683 MODULE_LICENSE("GPL v2"); 2684