1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale lpuart serial port driver 4 * 5 * Copyright 2012-2014 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/console.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dmapool.h> 13 #include <linux/io.h> 14 #include <linux/irq.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/of_dma.h> 19 #include <linux/serial_core.h> 20 #include <linux/slab.h> 21 #include <linux/tty_flip.h> 22 23 /* All registers are 8-bit width */ 24 #define UARTBDH 0x00 25 #define UARTBDL 0x01 26 #define UARTCR1 0x02 27 #define UARTCR2 0x03 28 #define UARTSR1 0x04 29 #define UARTCR3 0x06 30 #define UARTDR 0x07 31 #define UARTCR4 0x0a 32 #define UARTCR5 0x0b 33 #define UARTMODEM 0x0d 34 #define UARTPFIFO 0x10 35 #define UARTCFIFO 0x11 36 #define UARTSFIFO 0x12 37 #define UARTTWFIFO 0x13 38 #define UARTTCFIFO 0x14 39 #define UARTRWFIFO 0x15 40 41 #define UARTBDH_LBKDIE 0x80 42 #define UARTBDH_RXEDGIE 0x40 43 #define UARTBDH_SBR_MASK 0x1f 44 45 #define UARTCR1_LOOPS 0x80 46 #define UARTCR1_RSRC 0x20 47 #define UARTCR1_M 0x10 48 #define UARTCR1_WAKE 0x08 49 #define UARTCR1_ILT 0x04 50 #define UARTCR1_PE 0x02 51 #define UARTCR1_PT 0x01 52 53 #define UARTCR2_TIE 0x80 54 #define UARTCR2_TCIE 0x40 55 #define UARTCR2_RIE 0x20 56 #define UARTCR2_ILIE 0x10 57 #define UARTCR2_TE 0x08 58 #define UARTCR2_RE 0x04 59 #define UARTCR2_RWU 0x02 60 #define UARTCR2_SBK 0x01 61 62 #define UARTSR1_TDRE 0x80 63 #define UARTSR1_TC 0x40 64 #define UARTSR1_RDRF 0x20 65 #define UARTSR1_IDLE 0x10 66 #define UARTSR1_OR 0x08 67 #define UARTSR1_NF 0x04 68 #define UARTSR1_FE 0x02 69 #define UARTSR1_PE 0x01 70 71 #define UARTCR3_R8 0x80 72 #define UARTCR3_T8 0x40 73 #define UARTCR3_TXDIR 0x20 74 #define UARTCR3_TXINV 0x10 75 #define UARTCR3_ORIE 0x08 76 #define UARTCR3_NEIE 0x04 77 #define UARTCR3_FEIE 0x02 78 #define UARTCR3_PEIE 0x01 79 80 #define UARTCR4_MAEN1 0x80 81 #define UARTCR4_MAEN2 0x40 82 #define UARTCR4_M10 0x20 83 #define UARTCR4_BRFA_MASK 0x1f 84 #define UARTCR4_BRFA_OFF 0 85 86 #define UARTCR5_TDMAS 0x80 87 #define UARTCR5_RDMAS 0x20 88 89 #define UARTMODEM_RXRTSE 0x08 90 #define UARTMODEM_TXRTSPOL 0x04 91 #define UARTMODEM_TXRTSE 0x02 92 #define UARTMODEM_TXCTSE 0x01 93 94 #define UARTPFIFO_TXFE 0x80 95 #define UARTPFIFO_FIFOSIZE_MASK 0x7 96 #define UARTPFIFO_TXSIZE_OFF 4 97 #define UARTPFIFO_RXFE 0x08 98 #define UARTPFIFO_RXSIZE_OFF 0 99 100 #define UARTCFIFO_TXFLUSH 0x80 101 #define UARTCFIFO_RXFLUSH 0x40 102 #define UARTCFIFO_RXOFE 0x04 103 #define UARTCFIFO_TXOFE 0x02 104 #define UARTCFIFO_RXUFE 0x01 105 106 #define UARTSFIFO_TXEMPT 0x80 107 #define UARTSFIFO_RXEMPT 0x40 108 #define UARTSFIFO_RXOF 0x04 109 #define UARTSFIFO_TXOF 0x02 110 #define UARTSFIFO_RXUF 0x01 111 112 /* 32-bit register definition */ 113 #define UARTBAUD 0x00 114 #define UARTSTAT 0x04 115 #define UARTCTRL 0x08 116 #define UARTDATA 0x0C 117 #define UARTMATCH 0x10 118 #define UARTMODIR 0x14 119 #define UARTFIFO 0x18 120 #define UARTWATER 0x1c 121 122 #define UARTBAUD_MAEN1 0x80000000 123 #define UARTBAUD_MAEN2 0x40000000 124 #define UARTBAUD_M10 0x20000000 125 #define UARTBAUD_TDMAE 0x00800000 126 #define UARTBAUD_RDMAE 0x00200000 127 #define UARTBAUD_MATCFG 0x00400000 128 #define UARTBAUD_BOTHEDGE 0x00020000 129 #define UARTBAUD_RESYNCDIS 0x00010000 130 #define UARTBAUD_LBKDIE 0x00008000 131 #define UARTBAUD_RXEDGIE 0x00004000 132 #define UARTBAUD_SBNS 0x00002000 133 #define UARTBAUD_SBR 0x00000000 134 #define UARTBAUD_SBR_MASK 0x1fff 135 #define UARTBAUD_OSR_MASK 0x1f 136 #define UARTBAUD_OSR_SHIFT 24 137 138 #define UARTSTAT_LBKDIF 0x80000000 139 #define UARTSTAT_RXEDGIF 0x40000000 140 #define UARTSTAT_MSBF 0x20000000 141 #define UARTSTAT_RXINV 0x10000000 142 #define UARTSTAT_RWUID 0x08000000 143 #define UARTSTAT_BRK13 0x04000000 144 #define UARTSTAT_LBKDE 0x02000000 145 #define UARTSTAT_RAF 0x01000000 146 #define UARTSTAT_TDRE 0x00800000 147 #define UARTSTAT_TC 0x00400000 148 #define UARTSTAT_RDRF 0x00200000 149 #define UARTSTAT_IDLE 0x00100000 150 #define UARTSTAT_OR 0x00080000 151 #define UARTSTAT_NF 0x00040000 152 #define UARTSTAT_FE 0x00020000 153 #define UARTSTAT_PE 0x00010000 154 #define UARTSTAT_MA1F 0x00008000 155 #define UARTSTAT_M21F 0x00004000 156 157 #define UARTCTRL_R8T9 0x80000000 158 #define UARTCTRL_R9T8 0x40000000 159 #define UARTCTRL_TXDIR 0x20000000 160 #define UARTCTRL_TXINV 0x10000000 161 #define UARTCTRL_ORIE 0x08000000 162 #define UARTCTRL_NEIE 0x04000000 163 #define UARTCTRL_FEIE 0x02000000 164 #define UARTCTRL_PEIE 0x01000000 165 #define UARTCTRL_TIE 0x00800000 166 #define UARTCTRL_TCIE 0x00400000 167 #define UARTCTRL_RIE 0x00200000 168 #define UARTCTRL_ILIE 0x00100000 169 #define UARTCTRL_TE 0x00080000 170 #define UARTCTRL_RE 0x00040000 171 #define UARTCTRL_RWU 0x00020000 172 #define UARTCTRL_SBK 0x00010000 173 #define UARTCTRL_MA1IE 0x00008000 174 #define UARTCTRL_MA2IE 0x00004000 175 #define UARTCTRL_IDLECFG 0x00000100 176 #define UARTCTRL_LOOPS 0x00000080 177 #define UARTCTRL_DOZEEN 0x00000040 178 #define UARTCTRL_RSRC 0x00000020 179 #define UARTCTRL_M 0x00000010 180 #define UARTCTRL_WAKE 0x00000008 181 #define UARTCTRL_ILT 0x00000004 182 #define UARTCTRL_PE 0x00000002 183 #define UARTCTRL_PT 0x00000001 184 185 #define UARTDATA_NOISY 0x00008000 186 #define UARTDATA_PARITYE 0x00004000 187 #define UARTDATA_FRETSC 0x00002000 188 #define UARTDATA_RXEMPT 0x00001000 189 #define UARTDATA_IDLINE 0x00000800 190 #define UARTDATA_MASK 0x3ff 191 192 #define UARTMODIR_IREN 0x00020000 193 #define UARTMODIR_TXCTSSRC 0x00000020 194 #define UARTMODIR_TXCTSC 0x00000010 195 #define UARTMODIR_RXRTSE 0x00000008 196 #define UARTMODIR_TXRTSPOL 0x00000004 197 #define UARTMODIR_TXRTSE 0x00000002 198 #define UARTMODIR_TXCTSE 0x00000001 199 200 #define UARTFIFO_TXEMPT 0x00800000 201 #define UARTFIFO_RXEMPT 0x00400000 202 #define UARTFIFO_TXOF 0x00020000 203 #define UARTFIFO_RXUF 0x00010000 204 #define UARTFIFO_TXFLUSH 0x00008000 205 #define UARTFIFO_RXFLUSH 0x00004000 206 #define UARTFIFO_TXOFE 0x00000200 207 #define UARTFIFO_RXUFE 0x00000100 208 #define UARTFIFO_TXFE 0x00000080 209 #define UARTFIFO_FIFOSIZE_MASK 0x7 210 #define UARTFIFO_TXSIZE_OFF 4 211 #define UARTFIFO_RXFE 0x00000008 212 #define UARTFIFO_RXSIZE_OFF 0 213 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0)) 214 215 #define UARTWATER_COUNT_MASK 0xff 216 #define UARTWATER_TXCNT_OFF 8 217 #define UARTWATER_RXCNT_OFF 24 218 #define UARTWATER_WATER_MASK 0xff 219 #define UARTWATER_TXWATER_OFF 0 220 #define UARTWATER_RXWATER_OFF 16 221 222 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 223 #define DMA_RX_TIMEOUT (10) 224 225 #define DRIVER_NAME "fsl-lpuart" 226 #define DEV_NAME "ttyLP" 227 #define UART_NR 6 228 229 /* IMX lpuart has four extra unused regs located at the beginning */ 230 #define IMX_REG_OFF 0x10 231 232 static DEFINE_IDA(fsl_lpuart_ida); 233 234 enum lpuart_type { 235 VF610_LPUART, 236 LS1021A_LPUART, 237 LS1028A_LPUART, 238 IMX7ULP_LPUART, 239 IMX8QXP_LPUART, 240 }; 241 242 struct lpuart_port { 243 struct uart_port port; 244 enum lpuart_type devtype; 245 struct clk *ipg_clk; 246 struct clk *baud_clk; 247 unsigned int txfifo_size; 248 unsigned int rxfifo_size; 249 250 bool lpuart_dma_tx_use; 251 bool lpuart_dma_rx_use; 252 struct dma_chan *dma_tx_chan; 253 struct dma_chan *dma_rx_chan; 254 struct dma_async_tx_descriptor *dma_tx_desc; 255 struct dma_async_tx_descriptor *dma_rx_desc; 256 dma_cookie_t dma_tx_cookie; 257 dma_cookie_t dma_rx_cookie; 258 unsigned int dma_tx_bytes; 259 unsigned int dma_rx_bytes; 260 bool dma_tx_in_progress; 261 unsigned int dma_rx_timeout; 262 struct timer_list lpuart_timer; 263 struct scatterlist rx_sgl, tx_sgl[2]; 264 struct circ_buf rx_ring; 265 int rx_dma_rng_buf_len; 266 unsigned int dma_tx_nents; 267 wait_queue_head_t dma_wait; 268 bool id_allocated; 269 }; 270 271 struct lpuart_soc_data { 272 enum lpuart_type devtype; 273 char iotype; 274 u8 reg_off; 275 }; 276 277 static const struct lpuart_soc_data vf_data = { 278 .devtype = VF610_LPUART, 279 .iotype = UPIO_MEM, 280 }; 281 282 static const struct lpuart_soc_data ls1021a_data = { 283 .devtype = LS1021A_LPUART, 284 .iotype = UPIO_MEM32BE, 285 }; 286 287 static const struct lpuart_soc_data ls1028a_data = { 288 .devtype = LS1028A_LPUART, 289 .iotype = UPIO_MEM32, 290 }; 291 292 static struct lpuart_soc_data imx7ulp_data = { 293 .devtype = IMX7ULP_LPUART, 294 .iotype = UPIO_MEM32, 295 .reg_off = IMX_REG_OFF, 296 }; 297 298 static struct lpuart_soc_data imx8qxp_data = { 299 .devtype = IMX8QXP_LPUART, 300 .iotype = UPIO_MEM32, 301 .reg_off = IMX_REG_OFF, 302 }; 303 304 static const struct of_device_id lpuart_dt_ids[] = { 305 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 306 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, }, 307 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, }, 308 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, 309 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, 310 { /* sentinel */ } 311 }; 312 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 313 314 /* Forward declare this for the dma callbacks*/ 315 static void lpuart_dma_tx_complete(void *arg); 316 317 static inline bool is_ls1028a_lpuart(struct lpuart_port *sport) 318 { 319 return sport->devtype == LS1028A_LPUART; 320 } 321 322 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) 323 { 324 return sport->devtype == IMX8QXP_LPUART; 325 } 326 327 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 328 { 329 switch (port->iotype) { 330 case UPIO_MEM32: 331 return readl(port->membase + off); 332 case UPIO_MEM32BE: 333 return ioread32be(port->membase + off); 334 default: 335 return 0; 336 } 337 } 338 339 static inline void lpuart32_write(struct uart_port *port, u32 val, 340 u32 off) 341 { 342 switch (port->iotype) { 343 case UPIO_MEM32: 344 writel(val, port->membase + off); 345 break; 346 case UPIO_MEM32BE: 347 iowrite32be(val, port->membase + off); 348 break; 349 } 350 } 351 352 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) 353 { 354 int ret = 0; 355 356 if (is_en) { 357 ret = clk_prepare_enable(sport->ipg_clk); 358 if (ret) 359 return ret; 360 361 ret = clk_prepare_enable(sport->baud_clk); 362 if (ret) { 363 clk_disable_unprepare(sport->ipg_clk); 364 return ret; 365 } 366 } else { 367 clk_disable_unprepare(sport->baud_clk); 368 clk_disable_unprepare(sport->ipg_clk); 369 } 370 371 return 0; 372 } 373 374 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) 375 { 376 if (is_imx8qxp_lpuart(sport)) 377 return clk_get_rate(sport->baud_clk); 378 379 return clk_get_rate(sport->ipg_clk); 380 } 381 382 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true) 383 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false) 384 385 static void lpuart_stop_tx(struct uart_port *port) 386 { 387 unsigned char temp; 388 389 temp = readb(port->membase + UARTCR2); 390 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 391 writeb(temp, port->membase + UARTCR2); 392 } 393 394 static void lpuart32_stop_tx(struct uart_port *port) 395 { 396 unsigned long temp; 397 398 temp = lpuart32_read(port, UARTCTRL); 399 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 400 lpuart32_write(port, temp, UARTCTRL); 401 } 402 403 static void lpuart_stop_rx(struct uart_port *port) 404 { 405 unsigned char temp; 406 407 temp = readb(port->membase + UARTCR2); 408 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 409 } 410 411 static void lpuart32_stop_rx(struct uart_port *port) 412 { 413 unsigned long temp; 414 415 temp = lpuart32_read(port, UARTCTRL); 416 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); 417 } 418 419 static void lpuart_dma_tx(struct lpuart_port *sport) 420 { 421 struct circ_buf *xmit = &sport->port.state->xmit; 422 struct scatterlist *sgl = sport->tx_sgl; 423 struct device *dev = sport->port.dev; 424 struct dma_chan *chan = sport->dma_tx_chan; 425 int ret; 426 427 if (sport->dma_tx_in_progress) 428 return; 429 430 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 431 432 if (xmit->tail < xmit->head || xmit->head == 0) { 433 sport->dma_tx_nents = 1; 434 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 435 } else { 436 sport->dma_tx_nents = 2; 437 sg_init_table(sgl, 2); 438 sg_set_buf(sgl, xmit->buf + xmit->tail, 439 UART_XMIT_SIZE - xmit->tail); 440 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 441 } 442 443 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, 444 DMA_TO_DEVICE); 445 if (!ret) { 446 dev_err(dev, "DMA mapping error for TX.\n"); 447 return; 448 } 449 450 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, 451 ret, DMA_MEM_TO_DEV, 452 DMA_PREP_INTERRUPT); 453 if (!sport->dma_tx_desc) { 454 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 455 DMA_TO_DEVICE); 456 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 457 return; 458 } 459 460 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 461 sport->dma_tx_desc->callback_param = sport; 462 sport->dma_tx_in_progress = true; 463 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 464 dma_async_issue_pending(chan); 465 } 466 467 static bool lpuart_stopped_or_empty(struct uart_port *port) 468 { 469 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); 470 } 471 472 static void lpuart_dma_tx_complete(void *arg) 473 { 474 struct lpuart_port *sport = arg; 475 struct scatterlist *sgl = &sport->tx_sgl[0]; 476 struct circ_buf *xmit = &sport->port.state->xmit; 477 struct dma_chan *chan = sport->dma_tx_chan; 478 unsigned long flags; 479 480 spin_lock_irqsave(&sport->port.lock, flags); 481 482 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 483 DMA_TO_DEVICE); 484 485 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 486 487 sport->port.icount.tx += sport->dma_tx_bytes; 488 sport->dma_tx_in_progress = false; 489 spin_unlock_irqrestore(&sport->port.lock, flags); 490 491 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 492 uart_write_wakeup(&sport->port); 493 494 if (waitqueue_active(&sport->dma_wait)) { 495 wake_up(&sport->dma_wait); 496 return; 497 } 498 499 spin_lock_irqsave(&sport->port.lock, flags); 500 501 if (!lpuart_stopped_or_empty(&sport->port)) 502 lpuart_dma_tx(sport); 503 504 spin_unlock_irqrestore(&sport->port.lock, flags); 505 } 506 507 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) 508 { 509 switch (sport->port.iotype) { 510 case UPIO_MEM32: 511 return sport->port.mapbase + UARTDATA; 512 case UPIO_MEM32BE: 513 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; 514 } 515 return sport->port.mapbase + UARTDR; 516 } 517 518 static int lpuart_dma_tx_request(struct uart_port *port) 519 { 520 struct lpuart_port *sport = container_of(port, 521 struct lpuart_port, port); 522 struct dma_slave_config dma_tx_sconfig = {}; 523 int ret; 524 525 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); 526 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 527 dma_tx_sconfig.dst_maxburst = 1; 528 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 529 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 530 531 if (ret) { 532 dev_err(sport->port.dev, 533 "DMA slave config failed, err = %d\n", ret); 534 return ret; 535 } 536 537 return 0; 538 } 539 540 static bool lpuart_is_32(struct lpuart_port *sport) 541 { 542 return sport->port.iotype == UPIO_MEM32 || 543 sport->port.iotype == UPIO_MEM32BE; 544 } 545 546 static void lpuart_flush_buffer(struct uart_port *port) 547 { 548 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 549 struct dma_chan *chan = sport->dma_tx_chan; 550 u32 val; 551 552 if (sport->lpuart_dma_tx_use) { 553 if (sport->dma_tx_in_progress) { 554 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], 555 sport->dma_tx_nents, DMA_TO_DEVICE); 556 sport->dma_tx_in_progress = false; 557 } 558 dmaengine_terminate_all(chan); 559 } 560 561 if (lpuart_is_32(sport)) { 562 val = lpuart32_read(&sport->port, UARTFIFO); 563 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 564 lpuart32_write(&sport->port, val, UARTFIFO); 565 } else { 566 val = readb(sport->port.membase + UARTCFIFO); 567 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; 568 writeb(val, sport->port.membase + UARTCFIFO); 569 } 570 } 571 572 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset, 573 u8 bit) 574 { 575 while (!(readb(port->membase + offset) & bit)) 576 cpu_relax(); 577 } 578 579 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset, 580 u32 bit) 581 { 582 while (!(lpuart32_read(port, offset) & bit)) 583 cpu_relax(); 584 } 585 586 #if defined(CONFIG_CONSOLE_POLL) 587 588 static int lpuart_poll_init(struct uart_port *port) 589 { 590 struct lpuart_port *sport = container_of(port, 591 struct lpuart_port, port); 592 unsigned long flags; 593 unsigned char temp; 594 595 sport->port.fifosize = 0; 596 597 spin_lock_irqsave(&sport->port.lock, flags); 598 /* Disable Rx & Tx */ 599 writeb(0, sport->port.membase + UARTCR2); 600 601 temp = readb(sport->port.membase + UARTPFIFO); 602 /* Enable Rx and Tx FIFO */ 603 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 604 sport->port.membase + UARTPFIFO); 605 606 /* flush Tx and Rx FIFO */ 607 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 608 sport->port.membase + UARTCFIFO); 609 610 /* explicitly clear RDRF */ 611 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 612 readb(sport->port.membase + UARTDR); 613 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 614 } 615 616 writeb(0, sport->port.membase + UARTTWFIFO); 617 writeb(1, sport->port.membase + UARTRWFIFO); 618 619 /* Enable Rx and Tx */ 620 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 621 spin_unlock_irqrestore(&sport->port.lock, flags); 622 623 return 0; 624 } 625 626 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 627 { 628 /* drain */ 629 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 630 writeb(c, port->membase + UARTDR); 631 } 632 633 static int lpuart_poll_get_char(struct uart_port *port) 634 { 635 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 636 return NO_POLL_CHAR; 637 638 return readb(port->membase + UARTDR); 639 } 640 641 static int lpuart32_poll_init(struct uart_port *port) 642 { 643 unsigned long flags; 644 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 645 u32 temp; 646 647 sport->port.fifosize = 0; 648 649 spin_lock_irqsave(&sport->port.lock, flags); 650 651 /* Disable Rx & Tx */ 652 lpuart32_write(&sport->port, UARTCTRL, 0); 653 654 temp = lpuart32_read(&sport->port, UARTFIFO); 655 656 /* Enable Rx and Tx FIFO */ 657 lpuart32_write(&sport->port, UARTFIFO, 658 temp | UARTFIFO_RXFE | UARTFIFO_TXFE); 659 660 /* flush Tx and Rx FIFO */ 661 lpuart32_write(&sport->port, UARTFIFO, 662 UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH); 663 664 /* explicitly clear RDRF */ 665 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { 666 lpuart32_read(&sport->port, UARTDATA); 667 lpuart32_write(&sport->port, UARTFIFO, UARTFIFO_RXUF); 668 } 669 670 /* Enable Rx and Tx */ 671 lpuart32_write(&sport->port, UARTCTRL, UARTCTRL_RE | UARTCTRL_TE); 672 spin_unlock_irqrestore(&sport->port.lock, flags); 673 674 return 0; 675 } 676 677 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 678 { 679 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 680 lpuart32_write(port, UARTDATA, c); 681 } 682 683 static int lpuart32_poll_get_char(struct uart_port *port) 684 { 685 if (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_RDRF)) 686 return NO_POLL_CHAR; 687 688 return lpuart32_read(port, UARTDATA); 689 } 690 #endif 691 692 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 693 { 694 struct circ_buf *xmit = &sport->port.state->xmit; 695 696 if (sport->port.x_char) { 697 writeb(sport->port.x_char, sport->port.membase + UARTDR); 698 sport->port.icount.tx++; 699 sport->port.x_char = 0; 700 return; 701 } 702 703 if (lpuart_stopped_or_empty(&sport->port)) { 704 lpuart_stop_tx(&sport->port); 705 return; 706 } 707 708 while (!uart_circ_empty(xmit) && 709 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 710 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 711 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 712 sport->port.icount.tx++; 713 } 714 715 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 716 uart_write_wakeup(&sport->port); 717 718 if (uart_circ_empty(xmit)) 719 lpuart_stop_tx(&sport->port); 720 } 721 722 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 723 { 724 struct circ_buf *xmit = &sport->port.state->xmit; 725 unsigned long txcnt; 726 727 if (sport->port.x_char) { 728 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 729 sport->port.icount.tx++; 730 sport->port.x_char = 0; 731 return; 732 } 733 734 if (lpuart_stopped_or_empty(&sport->port)) { 735 lpuart32_stop_tx(&sport->port); 736 return; 737 } 738 739 txcnt = lpuart32_read(&sport->port, UARTWATER); 740 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 741 txcnt &= UARTWATER_COUNT_MASK; 742 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 743 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); 744 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 745 sport->port.icount.tx++; 746 txcnt = lpuart32_read(&sport->port, UARTWATER); 747 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 748 txcnt &= UARTWATER_COUNT_MASK; 749 } 750 751 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 752 uart_write_wakeup(&sport->port); 753 754 if (uart_circ_empty(xmit)) 755 lpuart32_stop_tx(&sport->port); 756 } 757 758 static void lpuart_start_tx(struct uart_port *port) 759 { 760 struct lpuart_port *sport = container_of(port, 761 struct lpuart_port, port); 762 unsigned char temp; 763 764 temp = readb(port->membase + UARTCR2); 765 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 766 767 if (sport->lpuart_dma_tx_use) { 768 if (!lpuart_stopped_or_empty(port)) 769 lpuart_dma_tx(sport); 770 } else { 771 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 772 lpuart_transmit_buffer(sport); 773 } 774 } 775 776 static void lpuart32_start_tx(struct uart_port *port) 777 { 778 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 779 unsigned long temp; 780 781 if (sport->lpuart_dma_tx_use) { 782 if (!lpuart_stopped_or_empty(port)) 783 lpuart_dma_tx(sport); 784 } else { 785 temp = lpuart32_read(port, UARTCTRL); 786 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); 787 788 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 789 lpuart32_transmit_buffer(sport); 790 } 791 } 792 793 /* return TIOCSER_TEMT when transmitter is not busy */ 794 static unsigned int lpuart_tx_empty(struct uart_port *port) 795 { 796 struct lpuart_port *sport = container_of(port, 797 struct lpuart_port, port); 798 unsigned char sr1 = readb(port->membase + UARTSR1); 799 unsigned char sfifo = readb(port->membase + UARTSFIFO); 800 801 if (sport->dma_tx_in_progress) 802 return 0; 803 804 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 805 return TIOCSER_TEMT; 806 807 return 0; 808 } 809 810 static unsigned int lpuart32_tx_empty(struct uart_port *port) 811 { 812 struct lpuart_port *sport = container_of(port, 813 struct lpuart_port, port); 814 unsigned long stat = lpuart32_read(port, UARTSTAT); 815 unsigned long sfifo = lpuart32_read(port, UARTFIFO); 816 817 if (sport->dma_tx_in_progress) 818 return 0; 819 820 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) 821 return TIOCSER_TEMT; 822 823 return 0; 824 } 825 826 static void lpuart_txint(struct lpuart_port *sport) 827 { 828 unsigned long flags; 829 830 spin_lock_irqsave(&sport->port.lock, flags); 831 lpuart_transmit_buffer(sport); 832 spin_unlock_irqrestore(&sport->port.lock, flags); 833 } 834 835 static void lpuart_rxint(struct lpuart_port *sport) 836 { 837 unsigned int flg, ignored = 0, overrun = 0; 838 struct tty_port *port = &sport->port.state->port; 839 unsigned long flags; 840 unsigned char rx, sr; 841 842 spin_lock_irqsave(&sport->port.lock, flags); 843 844 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 845 flg = TTY_NORMAL; 846 sport->port.icount.rx++; 847 /* 848 * to clear the FE, OR, NF, FE, PE flags, 849 * read SR1 then read DR 850 */ 851 sr = readb(sport->port.membase + UARTSR1); 852 rx = readb(sport->port.membase + UARTDR); 853 854 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 855 continue; 856 857 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 858 if (sr & UARTSR1_PE) 859 sport->port.icount.parity++; 860 else if (sr & UARTSR1_FE) 861 sport->port.icount.frame++; 862 863 if (sr & UARTSR1_OR) 864 overrun++; 865 866 if (sr & sport->port.ignore_status_mask) { 867 if (++ignored > 100) 868 goto out; 869 continue; 870 } 871 872 sr &= sport->port.read_status_mask; 873 874 if (sr & UARTSR1_PE) 875 flg = TTY_PARITY; 876 else if (sr & UARTSR1_FE) 877 flg = TTY_FRAME; 878 879 if (sr & UARTSR1_OR) 880 flg = TTY_OVERRUN; 881 882 sport->port.sysrq = 0; 883 } 884 885 tty_insert_flip_char(port, rx, flg); 886 } 887 888 out: 889 if (overrun) { 890 sport->port.icount.overrun += overrun; 891 892 /* 893 * Overruns cause FIFO pointers to become missaligned. 894 * Flushing the receive FIFO reinitializes the pointers. 895 */ 896 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 897 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); 898 } 899 900 spin_unlock_irqrestore(&sport->port.lock, flags); 901 902 tty_flip_buffer_push(port); 903 } 904 905 static void lpuart32_txint(struct lpuart_port *sport) 906 { 907 unsigned long flags; 908 909 spin_lock_irqsave(&sport->port.lock, flags); 910 lpuart32_transmit_buffer(sport); 911 spin_unlock_irqrestore(&sport->port.lock, flags); 912 } 913 914 static void lpuart32_rxint(struct lpuart_port *sport) 915 { 916 unsigned int flg, ignored = 0; 917 struct tty_port *port = &sport->port.state->port; 918 unsigned long flags; 919 unsigned long rx, sr; 920 921 spin_lock_irqsave(&sport->port.lock, flags); 922 923 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 924 flg = TTY_NORMAL; 925 sport->port.icount.rx++; 926 /* 927 * to clear the FE, OR, NF, FE, PE flags, 928 * read STAT then read DATA reg 929 */ 930 sr = lpuart32_read(&sport->port, UARTSTAT); 931 rx = lpuart32_read(&sport->port, UARTDATA); 932 rx &= 0x3ff; 933 934 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 935 continue; 936 937 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 938 if (sr & UARTSTAT_PE) 939 sport->port.icount.parity++; 940 else if (sr & UARTSTAT_FE) 941 sport->port.icount.frame++; 942 943 if (sr & UARTSTAT_OR) 944 sport->port.icount.overrun++; 945 946 if (sr & sport->port.ignore_status_mask) { 947 if (++ignored > 100) 948 goto out; 949 continue; 950 } 951 952 sr &= sport->port.read_status_mask; 953 954 if (sr & UARTSTAT_PE) 955 flg = TTY_PARITY; 956 else if (sr & UARTSTAT_FE) 957 flg = TTY_FRAME; 958 959 if (sr & UARTSTAT_OR) 960 flg = TTY_OVERRUN; 961 962 sport->port.sysrq = 0; 963 } 964 965 tty_insert_flip_char(port, rx, flg); 966 } 967 968 out: 969 spin_unlock_irqrestore(&sport->port.lock, flags); 970 971 tty_flip_buffer_push(port); 972 } 973 974 static irqreturn_t lpuart_int(int irq, void *dev_id) 975 { 976 struct lpuart_port *sport = dev_id; 977 unsigned char sts; 978 979 sts = readb(sport->port.membase + UARTSR1); 980 981 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) 982 lpuart_rxint(sport); 983 984 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) 985 lpuart_txint(sport); 986 987 return IRQ_HANDLED; 988 } 989 990 static irqreturn_t lpuart32_int(int irq, void *dev_id) 991 { 992 struct lpuart_port *sport = dev_id; 993 unsigned long sts, rxcount; 994 995 sts = lpuart32_read(&sport->port, UARTSTAT); 996 rxcount = lpuart32_read(&sport->port, UARTWATER); 997 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 998 999 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) 1000 lpuart32_rxint(sport); 1001 1002 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) 1003 lpuart32_txint(sport); 1004 1005 lpuart32_write(&sport->port, sts, UARTSTAT); 1006 return IRQ_HANDLED; 1007 } 1008 1009 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 1010 { 1011 struct tty_port *port = &sport->port.state->port; 1012 struct dma_tx_state state; 1013 enum dma_status dmastat; 1014 struct dma_chan *chan = sport->dma_rx_chan; 1015 struct circ_buf *ring = &sport->rx_ring; 1016 unsigned long flags; 1017 int count = 0; 1018 1019 if (lpuart_is_32(sport)) { 1020 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); 1021 1022 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { 1023 /* Read DR to clear the error flags */ 1024 lpuart32_read(&sport->port, UARTDATA); 1025 1026 if (sr & UARTSTAT_PE) 1027 sport->port.icount.parity++; 1028 else if (sr & UARTSTAT_FE) 1029 sport->port.icount.frame++; 1030 } 1031 } else { 1032 unsigned char sr = readb(sport->port.membase + UARTSR1); 1033 1034 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 1035 unsigned char cr2; 1036 1037 /* Disable receiver during this operation... */ 1038 cr2 = readb(sport->port.membase + UARTCR2); 1039 cr2 &= ~UARTCR2_RE; 1040 writeb(cr2, sport->port.membase + UARTCR2); 1041 1042 /* Read DR to clear the error flags */ 1043 readb(sport->port.membase + UARTDR); 1044 1045 if (sr & UARTSR1_PE) 1046 sport->port.icount.parity++; 1047 else if (sr & UARTSR1_FE) 1048 sport->port.icount.frame++; 1049 /* 1050 * At this point parity/framing error is 1051 * cleared However, since the DMA already read 1052 * the data register and we had to read it 1053 * again after reading the status register to 1054 * properly clear the flags, the FIFO actually 1055 * underflowed... This requires a clearing of 1056 * the FIFO... 1057 */ 1058 if (readb(sport->port.membase + UARTSFIFO) & 1059 UARTSFIFO_RXUF) { 1060 writeb(UARTSFIFO_RXUF, 1061 sport->port.membase + UARTSFIFO); 1062 writeb(UARTCFIFO_RXFLUSH, 1063 sport->port.membase + UARTCFIFO); 1064 } 1065 1066 cr2 |= UARTCR2_RE; 1067 writeb(cr2, sport->port.membase + UARTCR2); 1068 } 1069 } 1070 1071 async_tx_ack(sport->dma_rx_desc); 1072 1073 spin_lock_irqsave(&sport->port.lock, flags); 1074 1075 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1076 if (dmastat == DMA_ERROR) { 1077 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1078 spin_unlock_irqrestore(&sport->port.lock, flags); 1079 return; 1080 } 1081 1082 /* CPU claims ownership of RX DMA buffer */ 1083 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, 1084 DMA_FROM_DEVICE); 1085 1086 /* 1087 * ring->head points to the end of data already written by the DMA. 1088 * ring->tail points to the beginning of data to be read by the 1089 * framework. 1090 * The current transfer size should not be larger than the dma buffer 1091 * length. 1092 */ 1093 ring->head = sport->rx_sgl.length - state.residue; 1094 BUG_ON(ring->head > sport->rx_sgl.length); 1095 /* 1096 * At this point ring->head may point to the first byte right after the 1097 * last byte of the dma buffer: 1098 * 0 <= ring->head <= sport->rx_sgl.length 1099 * 1100 * However ring->tail must always points inside the dma buffer: 1101 * 0 <= ring->tail <= sport->rx_sgl.length - 1 1102 * 1103 * Since we use a ring buffer, we have to handle the case 1104 * where head is lower than tail. In such a case, we first read from 1105 * tail to the end of the buffer then reset tail. 1106 */ 1107 if (ring->head < ring->tail) { 1108 count = sport->rx_sgl.length - ring->tail; 1109 1110 tty_insert_flip_string(port, ring->buf + ring->tail, count); 1111 ring->tail = 0; 1112 sport->port.icount.rx += count; 1113 } 1114 1115 /* Finally we read data from tail to head */ 1116 if (ring->tail < ring->head) { 1117 count = ring->head - ring->tail; 1118 tty_insert_flip_string(port, ring->buf + ring->tail, count); 1119 /* Wrap ring->head if needed */ 1120 if (ring->head >= sport->rx_sgl.length) 1121 ring->head = 0; 1122 ring->tail = ring->head; 1123 sport->port.icount.rx += count; 1124 } 1125 1126 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, 1127 DMA_FROM_DEVICE); 1128 1129 spin_unlock_irqrestore(&sport->port.lock, flags); 1130 1131 tty_flip_buffer_push(port); 1132 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 1133 } 1134 1135 static void lpuart_dma_rx_complete(void *arg) 1136 { 1137 struct lpuart_port *sport = arg; 1138 1139 lpuart_copy_rx_to_tty(sport); 1140 } 1141 1142 static void lpuart_timer_func(struct timer_list *t) 1143 { 1144 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); 1145 1146 lpuart_copy_rx_to_tty(sport); 1147 } 1148 1149 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 1150 { 1151 struct dma_slave_config dma_rx_sconfig = {}; 1152 struct circ_buf *ring = &sport->rx_ring; 1153 int ret, nent; 1154 int bits, baud; 1155 struct tty_port *port = &sport->port.state->port; 1156 struct tty_struct *tty = port->tty; 1157 struct ktermios *termios = &tty->termios; 1158 struct dma_chan *chan = sport->dma_rx_chan; 1159 1160 baud = tty_get_baud_rate(tty); 1161 1162 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; 1163 if (termios->c_cflag & PARENB) 1164 bits++; 1165 1166 /* 1167 * Calculate length of one DMA buffer size to keep latency below 1168 * 10ms at any baud rate. 1169 */ 1170 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 1171 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 1172 if (sport->rx_dma_rng_buf_len < 16) 1173 sport->rx_dma_rng_buf_len = 16; 1174 1175 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1176 if (!ring->buf) 1177 return -ENOMEM; 1178 1179 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1180 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, 1181 DMA_FROM_DEVICE); 1182 1183 if (!nent) { 1184 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1185 return -EINVAL; 1186 } 1187 1188 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); 1189 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1190 dma_rx_sconfig.src_maxburst = 1; 1191 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1192 ret = dmaengine_slave_config(chan, &dma_rx_sconfig); 1193 1194 if (ret < 0) { 1195 dev_err(sport->port.dev, 1196 "DMA Rx slave config failed, err = %d\n", ret); 1197 return ret; 1198 } 1199 1200 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, 1201 sg_dma_address(&sport->rx_sgl), 1202 sport->rx_sgl.length, 1203 sport->rx_sgl.length / 2, 1204 DMA_DEV_TO_MEM, 1205 DMA_PREP_INTERRUPT); 1206 if (!sport->dma_rx_desc) { 1207 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1208 return -EFAULT; 1209 } 1210 1211 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1212 sport->dma_rx_desc->callback_param = sport; 1213 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1214 dma_async_issue_pending(chan); 1215 1216 if (lpuart_is_32(sport)) { 1217 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); 1218 1219 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); 1220 } else { 1221 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1222 sport->port.membase + UARTCR5); 1223 } 1224 1225 return 0; 1226 } 1227 1228 static void lpuart_dma_rx_free(struct uart_port *port) 1229 { 1230 struct lpuart_port *sport = container_of(port, 1231 struct lpuart_port, port); 1232 struct dma_chan *chan = sport->dma_rx_chan; 1233 1234 if (chan) 1235 dmaengine_terminate_all(chan); 1236 1237 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1238 kfree(sport->rx_ring.buf); 1239 sport->rx_ring.tail = 0; 1240 sport->rx_ring.head = 0; 1241 sport->dma_rx_desc = NULL; 1242 sport->dma_rx_cookie = -EINVAL; 1243 } 1244 1245 static int lpuart_config_rs485(struct uart_port *port, 1246 struct serial_rs485 *rs485) 1247 { 1248 struct lpuart_port *sport = container_of(port, 1249 struct lpuart_port, port); 1250 1251 u8 modem = readb(sport->port.membase + UARTMODEM) & 1252 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1253 writeb(modem, sport->port.membase + UARTMODEM); 1254 1255 /* clear unsupported configurations */ 1256 rs485->delay_rts_before_send = 0; 1257 rs485->delay_rts_after_send = 0; 1258 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1259 1260 if (rs485->flags & SER_RS485_ENABLED) { 1261 /* Enable auto RS-485 RTS mode */ 1262 modem |= UARTMODEM_TXRTSE; 1263 1264 /* 1265 * RTS needs to be logic HIGH either during transer _or_ after 1266 * transfer, other variants are not supported by the hardware. 1267 */ 1268 1269 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1270 SER_RS485_RTS_AFTER_SEND))) 1271 rs485->flags |= SER_RS485_RTS_ON_SEND; 1272 1273 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1274 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1275 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1276 1277 /* 1278 * The hardware defaults to RTS logic HIGH while transfer. 1279 * Switch polarity in case RTS shall be logic HIGH 1280 * after transfer. 1281 * Note: UART is assumed to be active high. 1282 */ 1283 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1284 modem &= ~UARTMODEM_TXRTSPOL; 1285 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1286 modem |= UARTMODEM_TXRTSPOL; 1287 } 1288 1289 /* Store the new configuration */ 1290 sport->port.rs485 = *rs485; 1291 1292 writeb(modem, sport->port.membase + UARTMODEM); 1293 return 0; 1294 } 1295 1296 static int lpuart32_config_rs485(struct uart_port *port, 1297 struct serial_rs485 *rs485) 1298 { 1299 struct lpuart_port *sport = container_of(port, 1300 struct lpuart_port, port); 1301 1302 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) 1303 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1304 lpuart32_write(&sport->port, modem, UARTMODIR); 1305 1306 /* clear unsupported configurations */ 1307 rs485->delay_rts_before_send = 0; 1308 rs485->delay_rts_after_send = 0; 1309 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1310 1311 if (rs485->flags & SER_RS485_ENABLED) { 1312 /* Enable auto RS-485 RTS mode */ 1313 modem |= UARTMODEM_TXRTSE; 1314 1315 /* 1316 * RTS needs to be logic HIGH either during transer _or_ after 1317 * transfer, other variants are not supported by the hardware. 1318 */ 1319 1320 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1321 SER_RS485_RTS_AFTER_SEND))) 1322 rs485->flags |= SER_RS485_RTS_ON_SEND; 1323 1324 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1325 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1326 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1327 1328 /* 1329 * The hardware defaults to RTS logic HIGH while transfer. 1330 * Switch polarity in case RTS shall be logic HIGH 1331 * after transfer. 1332 * Note: UART is assumed to be active high. 1333 */ 1334 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1335 modem &= ~UARTMODEM_TXRTSPOL; 1336 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1337 modem |= UARTMODEM_TXRTSPOL; 1338 } 1339 1340 /* Store the new configuration */ 1341 sport->port.rs485 = *rs485; 1342 1343 lpuart32_write(&sport->port, modem, UARTMODIR); 1344 return 0; 1345 } 1346 1347 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1348 { 1349 unsigned int temp = 0; 1350 unsigned char reg; 1351 1352 reg = readb(port->membase + UARTMODEM); 1353 if (reg & UARTMODEM_TXCTSE) 1354 temp |= TIOCM_CTS; 1355 1356 if (reg & UARTMODEM_RXRTSE) 1357 temp |= TIOCM_RTS; 1358 1359 return temp; 1360 } 1361 1362 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1363 { 1364 unsigned int temp = 0; 1365 unsigned long reg; 1366 1367 reg = lpuart32_read(port, UARTMODIR); 1368 if (reg & UARTMODIR_TXCTSE) 1369 temp |= TIOCM_CTS; 1370 1371 if (reg & UARTMODIR_RXRTSE) 1372 temp |= TIOCM_RTS; 1373 1374 return temp; 1375 } 1376 1377 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1378 { 1379 unsigned char temp; 1380 struct lpuart_port *sport = container_of(port, 1381 struct lpuart_port, port); 1382 1383 /* Make sure RXRTSE bit is not set when RS485 is enabled */ 1384 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { 1385 temp = readb(sport->port.membase + UARTMODEM) & 1386 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1387 1388 if (mctrl & TIOCM_RTS) 1389 temp |= UARTMODEM_RXRTSE; 1390 1391 if (mctrl & TIOCM_CTS) 1392 temp |= UARTMODEM_TXCTSE; 1393 1394 writeb(temp, port->membase + UARTMODEM); 1395 } 1396 } 1397 1398 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1399 { 1400 1401 } 1402 1403 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1404 { 1405 unsigned char temp; 1406 1407 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1408 1409 if (break_state != 0) 1410 temp |= UARTCR2_SBK; 1411 1412 writeb(temp, port->membase + UARTCR2); 1413 } 1414 1415 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1416 { 1417 unsigned long temp; 1418 1419 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; 1420 1421 if (break_state != 0) 1422 temp |= UARTCTRL_SBK; 1423 1424 lpuart32_write(port, temp, UARTCTRL); 1425 } 1426 1427 static void lpuart_setup_watermark(struct lpuart_port *sport) 1428 { 1429 unsigned char val, cr2; 1430 unsigned char cr2_saved; 1431 1432 cr2 = readb(sport->port.membase + UARTCR2); 1433 cr2_saved = cr2; 1434 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1435 UARTCR2_RIE | UARTCR2_RE); 1436 writeb(cr2, sport->port.membase + UARTCR2); 1437 1438 val = readb(sport->port.membase + UARTPFIFO); 1439 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1440 sport->port.membase + UARTPFIFO); 1441 1442 /* flush Tx and Rx FIFO */ 1443 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1444 sport->port.membase + UARTCFIFO); 1445 1446 /* explicitly clear RDRF */ 1447 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1448 readb(sport->port.membase + UARTDR); 1449 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1450 } 1451 1452 writeb(0, sport->port.membase + UARTTWFIFO); 1453 writeb(1, sport->port.membase + UARTRWFIFO); 1454 1455 /* Restore cr2 */ 1456 writeb(cr2_saved, sport->port.membase + UARTCR2); 1457 } 1458 1459 static void lpuart_setup_watermark_enable(struct lpuart_port *sport) 1460 { 1461 unsigned char cr2; 1462 1463 lpuart_setup_watermark(sport); 1464 1465 cr2 = readb(sport->port.membase + UARTCR2); 1466 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE; 1467 writeb(cr2, sport->port.membase + UARTCR2); 1468 } 1469 1470 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1471 { 1472 unsigned long val, ctrl; 1473 unsigned long ctrl_saved; 1474 1475 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1476 ctrl_saved = ctrl; 1477 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1478 UARTCTRL_RIE | UARTCTRL_RE); 1479 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1480 1481 /* enable FIFO mode */ 1482 val = lpuart32_read(&sport->port, UARTFIFO); 1483 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1484 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1485 lpuart32_write(&sport->port, val, UARTFIFO); 1486 1487 /* set the watermark */ 1488 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1489 lpuart32_write(&sport->port, val, UARTWATER); 1490 1491 /* Restore cr2 */ 1492 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1493 } 1494 1495 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) 1496 { 1497 u32 temp; 1498 1499 lpuart32_setup_watermark(sport); 1500 1501 temp = lpuart32_read(&sport->port, UARTCTRL); 1502 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE; 1503 lpuart32_write(&sport->port, temp, UARTCTRL); 1504 } 1505 1506 static void rx_dma_timer_init(struct lpuart_port *sport) 1507 { 1508 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); 1509 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1510 add_timer(&sport->lpuart_timer); 1511 } 1512 1513 static void lpuart_request_dma(struct lpuart_port *sport) 1514 { 1515 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); 1516 if (IS_ERR(sport->dma_tx_chan)) { 1517 dev_info_once(sport->port.dev, 1518 "DMA tx channel request failed, operating without tx DMA (%ld)\n", 1519 PTR_ERR(sport->dma_tx_chan)); 1520 sport->dma_tx_chan = NULL; 1521 } 1522 1523 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); 1524 if (IS_ERR(sport->dma_rx_chan)) { 1525 dev_info_once(sport->port.dev, 1526 "DMA rx channel request failed, operating without rx DMA (%ld)\n", 1527 PTR_ERR(sport->dma_rx_chan)); 1528 sport->dma_rx_chan = NULL; 1529 } 1530 } 1531 1532 static void lpuart_tx_dma_startup(struct lpuart_port *sport) 1533 { 1534 u32 uartbaud; 1535 int ret; 1536 1537 if (!sport->dma_tx_chan) 1538 goto err; 1539 1540 ret = lpuart_dma_tx_request(&sport->port); 1541 if (ret) 1542 goto err; 1543 1544 init_waitqueue_head(&sport->dma_wait); 1545 sport->lpuart_dma_tx_use = true; 1546 if (lpuart_is_32(sport)) { 1547 uartbaud = lpuart32_read(&sport->port, UARTBAUD); 1548 lpuart32_write(&sport->port, 1549 uartbaud | UARTBAUD_TDMAE, UARTBAUD); 1550 } else { 1551 writeb(readb(sport->port.membase + UARTCR5) | 1552 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 1553 } 1554 1555 return; 1556 1557 err: 1558 sport->lpuart_dma_tx_use = false; 1559 } 1560 1561 static void lpuart_rx_dma_startup(struct lpuart_port *sport) 1562 { 1563 int ret; 1564 1565 if (!sport->dma_rx_chan) 1566 goto err; 1567 1568 ret = lpuart_start_rx_dma(sport); 1569 if (ret) 1570 goto err; 1571 1572 /* set Rx DMA timeout */ 1573 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1574 if (!sport->dma_rx_timeout) 1575 sport->dma_rx_timeout = 1; 1576 1577 sport->lpuart_dma_rx_use = true; 1578 rx_dma_timer_init(sport); 1579 1580 return; 1581 1582 err: 1583 sport->lpuart_dma_rx_use = false; 1584 } 1585 1586 static int lpuart_startup(struct uart_port *port) 1587 { 1588 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1589 unsigned long flags; 1590 unsigned char temp; 1591 1592 /* determine FIFO size and enable FIFO mode */ 1593 temp = readb(sport->port.membase + UARTPFIFO); 1594 1595 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & 1596 UARTPFIFO_FIFOSIZE_MASK); 1597 sport->port.fifosize = sport->txfifo_size; 1598 1599 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & 1600 UARTPFIFO_FIFOSIZE_MASK); 1601 1602 lpuart_request_dma(sport); 1603 1604 spin_lock_irqsave(&sport->port.lock, flags); 1605 1606 lpuart_setup_watermark_enable(sport); 1607 1608 lpuart_rx_dma_startup(sport); 1609 lpuart_tx_dma_startup(sport); 1610 1611 spin_unlock_irqrestore(&sport->port.lock, flags); 1612 1613 return 0; 1614 } 1615 1616 static void lpuart32_configure(struct lpuart_port *sport) 1617 { 1618 unsigned long temp; 1619 1620 if (sport->lpuart_dma_rx_use) { 1621 /* RXWATER must be 0 */ 1622 temp = lpuart32_read(&sport->port, UARTWATER); 1623 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF); 1624 lpuart32_write(&sport->port, temp, UARTWATER); 1625 } 1626 temp = lpuart32_read(&sport->port, UARTCTRL); 1627 if (!sport->lpuart_dma_rx_use) 1628 temp |= UARTCTRL_RIE; 1629 if (!sport->lpuart_dma_tx_use) 1630 temp |= UARTCTRL_TIE; 1631 lpuart32_write(&sport->port, temp, UARTCTRL); 1632 } 1633 1634 static int lpuart32_startup(struct uart_port *port) 1635 { 1636 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1637 unsigned long flags; 1638 unsigned long temp; 1639 1640 /* determine FIFO size */ 1641 temp = lpuart32_read(&sport->port, UARTFIFO); 1642 1643 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & 1644 UARTFIFO_FIFOSIZE_MASK); 1645 sport->port.fifosize = sport->txfifo_size; 1646 1647 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & 1648 UARTFIFO_FIFOSIZE_MASK); 1649 1650 /* 1651 * The LS1028A has a fixed length of 16 words. Although it supports the 1652 * RX/TXSIZE fields their encoding is different. Eg the reference manual 1653 * states 0b101 is 16 words. 1654 */ 1655 if (is_ls1028a_lpuart(sport)) { 1656 sport->rxfifo_size = 16; 1657 sport->txfifo_size = 16; 1658 sport->port.fifosize = sport->txfifo_size; 1659 } 1660 1661 lpuart_request_dma(sport); 1662 1663 spin_lock_irqsave(&sport->port.lock, flags); 1664 1665 lpuart32_setup_watermark_enable(sport); 1666 1667 lpuart_rx_dma_startup(sport); 1668 lpuart_tx_dma_startup(sport); 1669 1670 lpuart32_configure(sport); 1671 1672 spin_unlock_irqrestore(&sport->port.lock, flags); 1673 return 0; 1674 } 1675 1676 static void lpuart_dma_shutdown(struct lpuart_port *sport) 1677 { 1678 if (sport->lpuart_dma_rx_use) { 1679 del_timer_sync(&sport->lpuart_timer); 1680 lpuart_dma_rx_free(&sport->port); 1681 } 1682 1683 if (sport->lpuart_dma_tx_use) { 1684 if (wait_event_interruptible(sport->dma_wait, 1685 !sport->dma_tx_in_progress) != false) { 1686 sport->dma_tx_in_progress = false; 1687 dmaengine_terminate_all(sport->dma_tx_chan); 1688 } 1689 } 1690 1691 if (sport->dma_tx_chan) 1692 dma_release_channel(sport->dma_tx_chan); 1693 if (sport->dma_rx_chan) 1694 dma_release_channel(sport->dma_rx_chan); 1695 } 1696 1697 static void lpuart_shutdown(struct uart_port *port) 1698 { 1699 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1700 unsigned char temp; 1701 unsigned long flags; 1702 1703 spin_lock_irqsave(&port->lock, flags); 1704 1705 /* disable Rx/Tx and interrupts */ 1706 temp = readb(port->membase + UARTCR2); 1707 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1708 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1709 writeb(temp, port->membase + UARTCR2); 1710 1711 spin_unlock_irqrestore(&port->lock, flags); 1712 1713 lpuart_dma_shutdown(sport); 1714 } 1715 1716 static void lpuart32_shutdown(struct uart_port *port) 1717 { 1718 struct lpuart_port *sport = 1719 container_of(port, struct lpuart_port, port); 1720 unsigned long temp; 1721 unsigned long flags; 1722 1723 spin_lock_irqsave(&port->lock, flags); 1724 1725 /* disable Rx/Tx and interrupts */ 1726 temp = lpuart32_read(port, UARTCTRL); 1727 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1728 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1729 lpuart32_write(port, temp, UARTCTRL); 1730 1731 spin_unlock_irqrestore(&port->lock, flags); 1732 1733 lpuart_dma_shutdown(sport); 1734 } 1735 1736 static void 1737 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1738 struct ktermios *old) 1739 { 1740 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1741 unsigned long flags; 1742 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1743 unsigned int baud; 1744 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1745 unsigned int sbr, brfa; 1746 1747 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1748 old_cr2 = readb(sport->port.membase + UARTCR2); 1749 cr3 = readb(sport->port.membase + UARTCR3); 1750 cr4 = readb(sport->port.membase + UARTCR4); 1751 bdh = readb(sport->port.membase + UARTBDH); 1752 modem = readb(sport->port.membase + UARTMODEM); 1753 /* 1754 * only support CS8 and CS7, and for CS7 must enable PE. 1755 * supported mode: 1756 * - (7,e/o,1) 1757 * - (8,n,1) 1758 * - (8,m/s,1) 1759 * - (8,e/o,1) 1760 */ 1761 while ((termios->c_cflag & CSIZE) != CS8 && 1762 (termios->c_cflag & CSIZE) != CS7) { 1763 termios->c_cflag &= ~CSIZE; 1764 termios->c_cflag |= old_csize; 1765 old_csize = CS8; 1766 } 1767 1768 if ((termios->c_cflag & CSIZE) == CS8 || 1769 (termios->c_cflag & CSIZE) == CS7) 1770 cr1 = old_cr1 & ~UARTCR1_M; 1771 1772 if (termios->c_cflag & CMSPAR) { 1773 if ((termios->c_cflag & CSIZE) != CS8) { 1774 termios->c_cflag &= ~CSIZE; 1775 termios->c_cflag |= CS8; 1776 } 1777 cr1 |= UARTCR1_M; 1778 } 1779 1780 /* 1781 * When auto RS-485 RTS mode is enabled, 1782 * hardware flow control need to be disabled. 1783 */ 1784 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1785 termios->c_cflag &= ~CRTSCTS; 1786 1787 if (termios->c_cflag & CRTSCTS) 1788 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE; 1789 else 1790 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1791 1792 termios->c_cflag &= ~CSTOPB; 1793 1794 /* parity must be enabled when CS7 to match 8-bits format */ 1795 if ((termios->c_cflag & CSIZE) == CS7) 1796 termios->c_cflag |= PARENB; 1797 1798 if (termios->c_cflag & PARENB) { 1799 if (termios->c_cflag & CMSPAR) { 1800 cr1 &= ~UARTCR1_PE; 1801 if (termios->c_cflag & PARODD) 1802 cr3 |= UARTCR3_T8; 1803 else 1804 cr3 &= ~UARTCR3_T8; 1805 } else { 1806 cr1 |= UARTCR1_PE; 1807 if ((termios->c_cflag & CSIZE) == CS8) 1808 cr1 |= UARTCR1_M; 1809 if (termios->c_cflag & PARODD) 1810 cr1 |= UARTCR1_PT; 1811 else 1812 cr1 &= ~UARTCR1_PT; 1813 } 1814 } else { 1815 cr1 &= ~UARTCR1_PE; 1816 } 1817 1818 /* ask the core to calculate the divisor */ 1819 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1820 1821 /* 1822 * Need to update the Ring buffer length according to the selected 1823 * baud rate and restart Rx DMA path. 1824 * 1825 * Since timer function acqures sport->port.lock, need to stop before 1826 * acquring same lock because otherwise del_timer_sync() can deadlock. 1827 */ 1828 if (old && sport->lpuart_dma_rx_use) { 1829 del_timer_sync(&sport->lpuart_timer); 1830 lpuart_dma_rx_free(&sport->port); 1831 } 1832 1833 spin_lock_irqsave(&sport->port.lock, flags); 1834 1835 sport->port.read_status_mask = 0; 1836 if (termios->c_iflag & INPCK) 1837 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; 1838 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1839 sport->port.read_status_mask |= UARTSR1_FE; 1840 1841 /* characters to ignore */ 1842 sport->port.ignore_status_mask = 0; 1843 if (termios->c_iflag & IGNPAR) 1844 sport->port.ignore_status_mask |= UARTSR1_PE; 1845 if (termios->c_iflag & IGNBRK) { 1846 sport->port.ignore_status_mask |= UARTSR1_FE; 1847 /* 1848 * if we're ignoring parity and break indicators, 1849 * ignore overruns too (for real raw support). 1850 */ 1851 if (termios->c_iflag & IGNPAR) 1852 sport->port.ignore_status_mask |= UARTSR1_OR; 1853 } 1854 1855 /* update the per-port timeout */ 1856 uart_update_timeout(port, termios->c_cflag, baud); 1857 1858 /* wait transmit engin complete */ 1859 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 1860 1861 /* disable transmit and receive */ 1862 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1863 sport->port.membase + UARTCR2); 1864 1865 sbr = sport->port.uartclk / (16 * baud); 1866 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1867 bdh &= ~UARTBDH_SBR_MASK; 1868 bdh |= (sbr >> 8) & 0x1F; 1869 cr4 &= ~UARTCR4_BRFA_MASK; 1870 brfa &= UARTCR4_BRFA_MASK; 1871 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1872 writeb(bdh, sport->port.membase + UARTBDH); 1873 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1874 writeb(cr3, sport->port.membase + UARTCR3); 1875 writeb(cr1, sport->port.membase + UARTCR1); 1876 writeb(modem, sport->port.membase + UARTMODEM); 1877 1878 /* restore control register */ 1879 writeb(old_cr2, sport->port.membase + UARTCR2); 1880 1881 if (old && sport->lpuart_dma_rx_use) { 1882 if (!lpuart_start_rx_dma(sport)) 1883 rx_dma_timer_init(sport); 1884 else 1885 sport->lpuart_dma_rx_use = false; 1886 } 1887 1888 spin_unlock_irqrestore(&sport->port.lock, flags); 1889 } 1890 1891 static void __lpuart32_serial_setbrg(struct uart_port *port, 1892 unsigned int baudrate, bool use_rx_dma, 1893 bool use_tx_dma) 1894 { 1895 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; 1896 u32 clk = port->uartclk; 1897 1898 /* 1899 * The idea is to use the best OSR (over-sampling rate) possible. 1900 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 1901 * Loop to find the best OSR value possible, one that generates minimum 1902 * baud_diff iterate through the rest of the supported values of OSR. 1903 * 1904 * Calculation Formula: 1905 * Baud Rate = baud clock / ((OSR+1) × SBR) 1906 */ 1907 baud_diff = baudrate; 1908 osr = 0; 1909 sbr = 0; 1910 1911 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 1912 /* calculate the temporary sbr value */ 1913 tmp_sbr = (clk / (baudrate * tmp_osr)); 1914 if (tmp_sbr == 0) 1915 tmp_sbr = 1; 1916 1917 /* 1918 * calculate the baud rate difference based on the temporary 1919 * osr and sbr values 1920 */ 1921 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 1922 1923 /* select best values between sbr and sbr+1 */ 1924 tmp = clk / (tmp_osr * (tmp_sbr + 1)); 1925 if (tmp_diff > (baudrate - tmp)) { 1926 tmp_diff = baudrate - tmp; 1927 tmp_sbr++; 1928 } 1929 1930 if (tmp_diff <= baud_diff) { 1931 baud_diff = tmp_diff; 1932 osr = tmp_osr; 1933 sbr = tmp_sbr; 1934 1935 if (!baud_diff) 1936 break; 1937 } 1938 } 1939 1940 /* handle buadrate outside acceptable rate */ 1941 if (baud_diff > ((baudrate / 100) * 3)) 1942 dev_warn(port->dev, 1943 "unacceptable baud rate difference of more than 3%%\n"); 1944 1945 tmp = lpuart32_read(port, UARTBAUD); 1946 1947 if ((osr > 3) && (osr < 8)) 1948 tmp |= UARTBAUD_BOTHEDGE; 1949 1950 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 1951 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; 1952 1953 tmp &= ~UARTBAUD_SBR_MASK; 1954 tmp |= sbr & UARTBAUD_SBR_MASK; 1955 1956 if (!use_rx_dma) 1957 tmp &= ~UARTBAUD_RDMAE; 1958 if (!use_tx_dma) 1959 tmp &= ~UARTBAUD_TDMAE; 1960 1961 lpuart32_write(port, tmp, UARTBAUD); 1962 } 1963 1964 static void lpuart32_serial_setbrg(struct lpuart_port *sport, 1965 unsigned int baudrate) 1966 { 1967 __lpuart32_serial_setbrg(&sport->port, baudrate, 1968 sport->lpuart_dma_rx_use, 1969 sport->lpuart_dma_tx_use); 1970 } 1971 1972 1973 static void 1974 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 1975 struct ktermios *old) 1976 { 1977 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1978 unsigned long flags; 1979 unsigned long ctrl, old_ctrl, modem; 1980 unsigned int baud; 1981 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1982 1983 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); 1984 modem = lpuart32_read(&sport->port, UARTMODIR); 1985 /* 1986 * only support CS8 and CS7, and for CS7 must enable PE. 1987 * supported mode: 1988 * - (7,e/o,1) 1989 * - (8,n,1) 1990 * - (8,m/s,1) 1991 * - (8,e/o,1) 1992 */ 1993 while ((termios->c_cflag & CSIZE) != CS8 && 1994 (termios->c_cflag & CSIZE) != CS7) { 1995 termios->c_cflag &= ~CSIZE; 1996 termios->c_cflag |= old_csize; 1997 old_csize = CS8; 1998 } 1999 2000 if ((termios->c_cflag & CSIZE) == CS8 || 2001 (termios->c_cflag & CSIZE) == CS7) 2002 ctrl = old_ctrl & ~UARTCTRL_M; 2003 2004 if (termios->c_cflag & CMSPAR) { 2005 if ((termios->c_cflag & CSIZE) != CS8) { 2006 termios->c_cflag &= ~CSIZE; 2007 termios->c_cflag |= CS8; 2008 } 2009 ctrl |= UARTCTRL_M; 2010 } 2011 2012 /* 2013 * When auto RS-485 RTS mode is enabled, 2014 * hardware flow control need to be disabled. 2015 */ 2016 if (sport->port.rs485.flags & SER_RS485_ENABLED) 2017 termios->c_cflag &= ~CRTSCTS; 2018 2019 if (termios->c_cflag & CRTSCTS) { 2020 modem |= (UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 2021 } else { 2022 termios->c_cflag &= ~CRTSCTS; 2023 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 2024 } 2025 2026 if (termios->c_cflag & CSTOPB) 2027 termios->c_cflag &= ~CSTOPB; 2028 2029 /* parity must be enabled when CS7 to match 8-bits format */ 2030 if ((termios->c_cflag & CSIZE) == CS7) 2031 termios->c_cflag |= PARENB; 2032 2033 if ((termios->c_cflag & PARENB)) { 2034 if (termios->c_cflag & CMSPAR) { 2035 ctrl &= ~UARTCTRL_PE; 2036 ctrl |= UARTCTRL_M; 2037 } else { 2038 ctrl |= UARTCTRL_PE; 2039 if ((termios->c_cflag & CSIZE) == CS8) 2040 ctrl |= UARTCTRL_M; 2041 if (termios->c_cflag & PARODD) 2042 ctrl |= UARTCTRL_PT; 2043 else 2044 ctrl &= ~UARTCTRL_PT; 2045 } 2046 } else { 2047 ctrl &= ~UARTCTRL_PE; 2048 } 2049 2050 /* ask the core to calculate the divisor */ 2051 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); 2052 2053 /* 2054 * Need to update the Ring buffer length according to the selected 2055 * baud rate and restart Rx DMA path. 2056 * 2057 * Since timer function acqures sport->port.lock, need to stop before 2058 * acquring same lock because otherwise del_timer_sync() can deadlock. 2059 */ 2060 if (old && sport->lpuart_dma_rx_use) { 2061 del_timer_sync(&sport->lpuart_timer); 2062 lpuart_dma_rx_free(&sport->port); 2063 } 2064 2065 spin_lock_irqsave(&sport->port.lock, flags); 2066 2067 sport->port.read_status_mask = 0; 2068 if (termios->c_iflag & INPCK) 2069 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; 2070 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2071 sport->port.read_status_mask |= UARTSTAT_FE; 2072 2073 /* characters to ignore */ 2074 sport->port.ignore_status_mask = 0; 2075 if (termios->c_iflag & IGNPAR) 2076 sport->port.ignore_status_mask |= UARTSTAT_PE; 2077 if (termios->c_iflag & IGNBRK) { 2078 sport->port.ignore_status_mask |= UARTSTAT_FE; 2079 /* 2080 * if we're ignoring parity and break indicators, 2081 * ignore overruns too (for real raw support). 2082 */ 2083 if (termios->c_iflag & IGNPAR) 2084 sport->port.ignore_status_mask |= UARTSTAT_OR; 2085 } 2086 2087 /* update the per-port timeout */ 2088 uart_update_timeout(port, termios->c_cflag, baud); 2089 2090 /* wait transmit engin complete */ 2091 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2092 2093 /* disable transmit and receive */ 2094 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 2095 UARTCTRL); 2096 2097 lpuart32_serial_setbrg(sport, baud); 2098 lpuart32_write(&sport->port, modem, UARTMODIR); 2099 lpuart32_write(&sport->port, ctrl, UARTCTRL); 2100 /* restore control register */ 2101 2102 if (old && sport->lpuart_dma_rx_use) { 2103 if (!lpuart_start_rx_dma(sport)) 2104 rx_dma_timer_init(sport); 2105 else 2106 sport->lpuart_dma_rx_use = false; 2107 } 2108 2109 spin_unlock_irqrestore(&sport->port.lock, flags); 2110 } 2111 2112 static const char *lpuart_type(struct uart_port *port) 2113 { 2114 return "FSL_LPUART"; 2115 } 2116 2117 static void lpuart_release_port(struct uart_port *port) 2118 { 2119 /* nothing to do */ 2120 } 2121 2122 static int lpuart_request_port(struct uart_port *port) 2123 { 2124 return 0; 2125 } 2126 2127 /* configure/autoconfigure the port */ 2128 static void lpuart_config_port(struct uart_port *port, int flags) 2129 { 2130 if (flags & UART_CONFIG_TYPE) 2131 port->type = PORT_LPUART; 2132 } 2133 2134 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 2135 { 2136 int ret = 0; 2137 2138 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 2139 ret = -EINVAL; 2140 if (port->irq != ser->irq) 2141 ret = -EINVAL; 2142 if (ser->io_type != UPIO_MEM) 2143 ret = -EINVAL; 2144 if (port->uartclk / 16 != ser->baud_base) 2145 ret = -EINVAL; 2146 if (port->iobase != ser->port) 2147 ret = -EINVAL; 2148 if (ser->hub6 != 0) 2149 ret = -EINVAL; 2150 return ret; 2151 } 2152 2153 static const struct uart_ops lpuart_pops = { 2154 .tx_empty = lpuart_tx_empty, 2155 .set_mctrl = lpuart_set_mctrl, 2156 .get_mctrl = lpuart_get_mctrl, 2157 .stop_tx = lpuart_stop_tx, 2158 .start_tx = lpuart_start_tx, 2159 .stop_rx = lpuart_stop_rx, 2160 .break_ctl = lpuart_break_ctl, 2161 .startup = lpuart_startup, 2162 .shutdown = lpuart_shutdown, 2163 .set_termios = lpuart_set_termios, 2164 .type = lpuart_type, 2165 .request_port = lpuart_request_port, 2166 .release_port = lpuart_release_port, 2167 .config_port = lpuart_config_port, 2168 .verify_port = lpuart_verify_port, 2169 .flush_buffer = lpuart_flush_buffer, 2170 #if defined(CONFIG_CONSOLE_POLL) 2171 .poll_init = lpuart_poll_init, 2172 .poll_get_char = lpuart_poll_get_char, 2173 .poll_put_char = lpuart_poll_put_char, 2174 #endif 2175 }; 2176 2177 static const struct uart_ops lpuart32_pops = { 2178 .tx_empty = lpuart32_tx_empty, 2179 .set_mctrl = lpuart32_set_mctrl, 2180 .get_mctrl = lpuart32_get_mctrl, 2181 .stop_tx = lpuart32_stop_tx, 2182 .start_tx = lpuart32_start_tx, 2183 .stop_rx = lpuart32_stop_rx, 2184 .break_ctl = lpuart32_break_ctl, 2185 .startup = lpuart32_startup, 2186 .shutdown = lpuart32_shutdown, 2187 .set_termios = lpuart32_set_termios, 2188 .type = lpuart_type, 2189 .request_port = lpuart_request_port, 2190 .release_port = lpuart_release_port, 2191 .config_port = lpuart_config_port, 2192 .verify_port = lpuart_verify_port, 2193 .flush_buffer = lpuart_flush_buffer, 2194 #if defined(CONFIG_CONSOLE_POLL) 2195 .poll_init = lpuart32_poll_init, 2196 .poll_get_char = lpuart32_poll_get_char, 2197 .poll_put_char = lpuart32_poll_put_char, 2198 #endif 2199 }; 2200 2201 static struct lpuart_port *lpuart_ports[UART_NR]; 2202 2203 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 2204 static void lpuart_console_putchar(struct uart_port *port, int ch) 2205 { 2206 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 2207 writeb(ch, port->membase + UARTDR); 2208 } 2209 2210 static void lpuart32_console_putchar(struct uart_port *port, int ch) 2211 { 2212 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 2213 lpuart32_write(port, ch, UARTDATA); 2214 } 2215 2216 static void 2217 lpuart_console_write(struct console *co, const char *s, unsigned int count) 2218 { 2219 struct lpuart_port *sport = lpuart_ports[co->index]; 2220 unsigned char old_cr2, cr2; 2221 unsigned long flags; 2222 int locked = 1; 2223 2224 if (sport->port.sysrq || oops_in_progress) 2225 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2226 else 2227 spin_lock_irqsave(&sport->port.lock, flags); 2228 2229 /* first save CR2 and then disable interrupts */ 2230 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 2231 cr2 |= UARTCR2_TE | UARTCR2_RE; 2232 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 2233 writeb(cr2, sport->port.membase + UARTCR2); 2234 2235 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 2236 2237 /* wait for transmitter finish complete and restore CR2 */ 2238 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 2239 2240 writeb(old_cr2, sport->port.membase + UARTCR2); 2241 2242 if (locked) 2243 spin_unlock_irqrestore(&sport->port.lock, flags); 2244 } 2245 2246 static void 2247 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 2248 { 2249 struct lpuart_port *sport = lpuart_ports[co->index]; 2250 unsigned long old_cr, cr; 2251 unsigned long flags; 2252 int locked = 1; 2253 2254 if (sport->port.sysrq || oops_in_progress) 2255 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2256 else 2257 spin_lock_irqsave(&sport->port.lock, flags); 2258 2259 /* first save CR2 and then disable interrupts */ 2260 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 2261 cr |= UARTCTRL_TE | UARTCTRL_RE; 2262 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 2263 lpuart32_write(&sport->port, cr, UARTCTRL); 2264 2265 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 2266 2267 /* wait for transmitter finish complete and restore CR2 */ 2268 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2269 2270 lpuart32_write(&sport->port, old_cr, UARTCTRL); 2271 2272 if (locked) 2273 spin_unlock_irqrestore(&sport->port.lock, flags); 2274 } 2275 2276 /* 2277 * if the port was already initialised (eg, by a boot loader), 2278 * try to determine the current setup. 2279 */ 2280 static void __init 2281 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 2282 int *parity, int *bits) 2283 { 2284 unsigned char cr, bdh, bdl, brfa; 2285 unsigned int sbr, uartclk, baud_raw; 2286 2287 cr = readb(sport->port.membase + UARTCR2); 2288 cr &= UARTCR2_TE | UARTCR2_RE; 2289 if (!cr) 2290 return; 2291 2292 /* ok, the port was enabled */ 2293 2294 cr = readb(sport->port.membase + UARTCR1); 2295 2296 *parity = 'n'; 2297 if (cr & UARTCR1_PE) { 2298 if (cr & UARTCR1_PT) 2299 *parity = 'o'; 2300 else 2301 *parity = 'e'; 2302 } 2303 2304 if (cr & UARTCR1_M) 2305 *bits = 9; 2306 else 2307 *bits = 8; 2308 2309 bdh = readb(sport->port.membase + UARTBDH); 2310 bdh &= UARTBDH_SBR_MASK; 2311 bdl = readb(sport->port.membase + UARTBDL); 2312 sbr = bdh; 2313 sbr <<= 8; 2314 sbr |= bdl; 2315 brfa = readb(sport->port.membase + UARTCR4); 2316 brfa &= UARTCR4_BRFA_MASK; 2317 2318 uartclk = lpuart_get_baud_clk_rate(sport); 2319 /* 2320 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2321 */ 2322 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 2323 2324 if (*baud != baud_raw) 2325 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2326 "from %d to %d\n", baud_raw, *baud); 2327 } 2328 2329 static void __init 2330 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 2331 int *parity, int *bits) 2332 { 2333 unsigned long cr, bd; 2334 unsigned int sbr, uartclk, baud_raw; 2335 2336 cr = lpuart32_read(&sport->port, UARTCTRL); 2337 cr &= UARTCTRL_TE | UARTCTRL_RE; 2338 if (!cr) 2339 return; 2340 2341 /* ok, the port was enabled */ 2342 2343 cr = lpuart32_read(&sport->port, UARTCTRL); 2344 2345 *parity = 'n'; 2346 if (cr & UARTCTRL_PE) { 2347 if (cr & UARTCTRL_PT) 2348 *parity = 'o'; 2349 else 2350 *parity = 'e'; 2351 } 2352 2353 if (cr & UARTCTRL_M) 2354 *bits = 9; 2355 else 2356 *bits = 8; 2357 2358 bd = lpuart32_read(&sport->port, UARTBAUD); 2359 bd &= UARTBAUD_SBR_MASK; 2360 sbr = bd; 2361 uartclk = lpuart_get_baud_clk_rate(sport); 2362 /* 2363 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2364 */ 2365 baud_raw = uartclk / (16 * sbr); 2366 2367 if (*baud != baud_raw) 2368 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2369 "from %d to %d\n", baud_raw, *baud); 2370 } 2371 2372 static int __init lpuart_console_setup(struct console *co, char *options) 2373 { 2374 struct lpuart_port *sport; 2375 int baud = 115200; 2376 int bits = 8; 2377 int parity = 'n'; 2378 int flow = 'n'; 2379 2380 /* 2381 * check whether an invalid uart number has been specified, and 2382 * if so, search for the first available port that does have 2383 * console support. 2384 */ 2385 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2386 co->index = 0; 2387 2388 sport = lpuart_ports[co->index]; 2389 if (sport == NULL) 2390 return -ENODEV; 2391 2392 if (options) 2393 uart_parse_options(options, &baud, &parity, &bits, &flow); 2394 else 2395 if (lpuart_is_32(sport)) 2396 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2397 else 2398 lpuart_console_get_options(sport, &baud, &parity, &bits); 2399 2400 if (lpuart_is_32(sport)) 2401 lpuart32_setup_watermark(sport); 2402 else 2403 lpuart_setup_watermark(sport); 2404 2405 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2406 } 2407 2408 static struct uart_driver lpuart_reg; 2409 static struct console lpuart_console = { 2410 .name = DEV_NAME, 2411 .write = lpuart_console_write, 2412 .device = uart_console_device, 2413 .setup = lpuart_console_setup, 2414 .flags = CON_PRINTBUFFER, 2415 .index = -1, 2416 .data = &lpuart_reg, 2417 }; 2418 2419 static struct console lpuart32_console = { 2420 .name = DEV_NAME, 2421 .write = lpuart32_console_write, 2422 .device = uart_console_device, 2423 .setup = lpuart_console_setup, 2424 .flags = CON_PRINTBUFFER, 2425 .index = -1, 2426 .data = &lpuart_reg, 2427 }; 2428 2429 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2430 { 2431 struct earlycon_device *dev = con->data; 2432 2433 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2434 } 2435 2436 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2437 { 2438 struct earlycon_device *dev = con->data; 2439 2440 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2441 } 2442 2443 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2444 const char *opt) 2445 { 2446 if (!device->port.membase) 2447 return -ENODEV; 2448 2449 device->con->write = lpuart_early_write; 2450 return 0; 2451 } 2452 2453 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2454 const char *opt) 2455 { 2456 if (!device->port.membase) 2457 return -ENODEV; 2458 2459 if (device->port.iotype != UPIO_MEM32) 2460 device->port.iotype = UPIO_MEM32BE; 2461 2462 device->con->write = lpuart32_early_write; 2463 return 0; 2464 } 2465 2466 static int __init ls1028a_early_console_setup(struct earlycon_device *device, 2467 const char *opt) 2468 { 2469 u32 cr; 2470 2471 if (!device->port.membase) 2472 return -ENODEV; 2473 2474 device->port.iotype = UPIO_MEM32; 2475 device->con->write = lpuart32_early_write; 2476 2477 /* set the baudrate */ 2478 if (device->port.uartclk && device->baud) 2479 __lpuart32_serial_setbrg(&device->port, device->baud, 2480 false, false); 2481 2482 /* enable transmitter */ 2483 cr = lpuart32_read(&device->port, UARTCTRL); 2484 cr |= UARTCTRL_TE; 2485 lpuart32_write(&device->port, cr, UARTCTRL); 2486 2487 return 0; 2488 } 2489 2490 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2491 const char *opt) 2492 { 2493 if (!device->port.membase) 2494 return -ENODEV; 2495 2496 device->port.iotype = UPIO_MEM32; 2497 device->port.membase += IMX_REG_OFF; 2498 device->con->write = lpuart32_early_write; 2499 2500 return 0; 2501 } 2502 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2503 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2504 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup); 2505 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2506 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2507 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2508 2509 #define LPUART_CONSOLE (&lpuart_console) 2510 #define LPUART32_CONSOLE (&lpuart32_console) 2511 #else 2512 #define LPUART_CONSOLE NULL 2513 #define LPUART32_CONSOLE NULL 2514 #endif 2515 2516 static struct uart_driver lpuart_reg = { 2517 .owner = THIS_MODULE, 2518 .driver_name = DRIVER_NAME, 2519 .dev_name = DEV_NAME, 2520 .nr = ARRAY_SIZE(lpuart_ports), 2521 .cons = LPUART_CONSOLE, 2522 }; 2523 2524 static int lpuart_probe(struct platform_device *pdev) 2525 { 2526 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids, 2527 &pdev->dev); 2528 const struct lpuart_soc_data *sdata = of_id->data; 2529 struct device_node *np = pdev->dev.of_node; 2530 struct lpuart_port *sport; 2531 struct resource *res; 2532 int ret; 2533 2534 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2535 if (!sport) 2536 return -ENOMEM; 2537 2538 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2539 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 2540 if (IS_ERR(sport->port.membase)) 2541 return PTR_ERR(sport->port.membase); 2542 2543 sport->port.membase += sdata->reg_off; 2544 sport->port.mapbase = res->start; 2545 sport->port.dev = &pdev->dev; 2546 sport->port.type = PORT_LPUART; 2547 sport->devtype = sdata->devtype; 2548 ret = platform_get_irq(pdev, 0); 2549 if (ret < 0) 2550 return ret; 2551 sport->port.irq = ret; 2552 sport->port.iotype = sdata->iotype; 2553 if (lpuart_is_32(sport)) 2554 sport->port.ops = &lpuart32_pops; 2555 else 2556 sport->port.ops = &lpuart_pops; 2557 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); 2558 sport->port.flags = UPF_BOOT_AUTOCONF; 2559 2560 if (lpuart_is_32(sport)) 2561 sport->port.rs485_config = lpuart32_config_rs485; 2562 else 2563 sport->port.rs485_config = lpuart_config_rs485; 2564 2565 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 2566 if (IS_ERR(sport->ipg_clk)) { 2567 ret = PTR_ERR(sport->ipg_clk); 2568 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); 2569 return ret; 2570 } 2571 2572 sport->baud_clk = NULL; 2573 if (is_imx8qxp_lpuart(sport)) { 2574 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); 2575 if (IS_ERR(sport->baud_clk)) { 2576 ret = PTR_ERR(sport->baud_clk); 2577 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); 2578 return ret; 2579 } 2580 } 2581 2582 ret = of_alias_get_id(np, "serial"); 2583 if (ret < 0) { 2584 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL); 2585 if (ret < 0) { 2586 dev_err(&pdev->dev, "port line is full, add device failed\n"); 2587 return ret; 2588 } 2589 sport->id_allocated = true; 2590 } 2591 if (ret >= ARRAY_SIZE(lpuart_ports)) { 2592 dev_err(&pdev->dev, "serial%d out of range\n", ret); 2593 ret = -EINVAL; 2594 goto failed_out_of_range; 2595 } 2596 sport->port.line = ret; 2597 2598 ret = lpuart_enable_clks(sport); 2599 if (ret) 2600 goto failed_clock_enable; 2601 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); 2602 2603 lpuart_ports[sport->port.line] = sport; 2604 2605 platform_set_drvdata(pdev, &sport->port); 2606 2607 if (lpuart_is_32(sport)) { 2608 lpuart_reg.cons = LPUART32_CONSOLE; 2609 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0, 2610 DRIVER_NAME, sport); 2611 } else { 2612 lpuart_reg.cons = LPUART_CONSOLE; 2613 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0, 2614 DRIVER_NAME, sport); 2615 } 2616 2617 if (ret) 2618 goto failed_irq_request; 2619 2620 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2621 if (ret) 2622 goto failed_attach_port; 2623 2624 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2625 2626 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX) 2627 dev_err(&pdev->dev, "driver doesn't support RX during TX\n"); 2628 2629 if (sport->port.rs485.delay_rts_before_send || 2630 sport->port.rs485.delay_rts_after_send) 2631 dev_err(&pdev->dev, "driver doesn't support RTS delays\n"); 2632 2633 sport->port.rs485_config(&sport->port, &sport->port.rs485); 2634 2635 return 0; 2636 2637 failed_attach_port: 2638 failed_irq_request: 2639 lpuart_disable_clks(sport); 2640 failed_clock_enable: 2641 failed_out_of_range: 2642 if (sport->id_allocated) 2643 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); 2644 return ret; 2645 } 2646 2647 static int lpuart_remove(struct platform_device *pdev) 2648 { 2649 struct lpuart_port *sport = platform_get_drvdata(pdev); 2650 2651 uart_remove_one_port(&lpuart_reg, &sport->port); 2652 2653 if (sport->id_allocated) 2654 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); 2655 2656 lpuart_disable_clks(sport); 2657 2658 if (sport->dma_tx_chan) 2659 dma_release_channel(sport->dma_tx_chan); 2660 2661 if (sport->dma_rx_chan) 2662 dma_release_channel(sport->dma_rx_chan); 2663 2664 return 0; 2665 } 2666 2667 #ifdef CONFIG_PM_SLEEP 2668 static int lpuart_suspend(struct device *dev) 2669 { 2670 struct lpuart_port *sport = dev_get_drvdata(dev); 2671 unsigned long temp; 2672 bool irq_wake; 2673 2674 if (lpuart_is_32(sport)) { 2675 /* disable Rx/Tx and interrupts */ 2676 temp = lpuart32_read(&sport->port, UARTCTRL); 2677 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2678 lpuart32_write(&sport->port, temp, UARTCTRL); 2679 } else { 2680 /* disable Rx/Tx and interrupts */ 2681 temp = readb(sport->port.membase + UARTCR2); 2682 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2683 writeb(temp, sport->port.membase + UARTCR2); 2684 } 2685 2686 uart_suspend_port(&lpuart_reg, &sport->port); 2687 2688 /* uart_suspend_port() might set wakeup flag */ 2689 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2690 2691 if (sport->lpuart_dma_rx_use) { 2692 /* 2693 * EDMA driver during suspend will forcefully release any 2694 * non-idle DMA channels. If port wakeup is enabled or if port 2695 * is console port or 'no_console_suspend' is set the Rx DMA 2696 * cannot resume as as expected, hence gracefully release the 2697 * Rx DMA path before suspend and start Rx DMA path on resume. 2698 */ 2699 if (irq_wake) { 2700 del_timer_sync(&sport->lpuart_timer); 2701 lpuart_dma_rx_free(&sport->port); 2702 } 2703 2704 /* Disable Rx DMA to use UART port as wakeup source */ 2705 if (lpuart_is_32(sport)) { 2706 temp = lpuart32_read(&sport->port, UARTBAUD); 2707 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, 2708 UARTBAUD); 2709 } else { 2710 writeb(readb(sport->port.membase + UARTCR5) & 2711 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 2712 } 2713 } 2714 2715 if (sport->lpuart_dma_tx_use) { 2716 sport->dma_tx_in_progress = false; 2717 dmaengine_terminate_all(sport->dma_tx_chan); 2718 } 2719 2720 if (sport->port.suspended && !irq_wake) 2721 lpuart_disable_clks(sport); 2722 2723 return 0; 2724 } 2725 2726 static int lpuart_resume(struct device *dev) 2727 { 2728 struct lpuart_port *sport = dev_get_drvdata(dev); 2729 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2730 2731 if (sport->port.suspended && !irq_wake) 2732 lpuart_enable_clks(sport); 2733 2734 if (lpuart_is_32(sport)) 2735 lpuart32_setup_watermark_enable(sport); 2736 else 2737 lpuart_setup_watermark_enable(sport); 2738 2739 if (sport->lpuart_dma_rx_use) { 2740 if (irq_wake) { 2741 if (!lpuart_start_rx_dma(sport)) 2742 rx_dma_timer_init(sport); 2743 else 2744 sport->lpuart_dma_rx_use = false; 2745 } 2746 } 2747 2748 lpuart_tx_dma_startup(sport); 2749 2750 if (lpuart_is_32(sport)) 2751 lpuart32_configure(sport); 2752 2753 uart_resume_port(&lpuart_reg, &sport->port); 2754 2755 return 0; 2756 } 2757 #endif 2758 2759 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2760 2761 static struct platform_driver lpuart_driver = { 2762 .probe = lpuart_probe, 2763 .remove = lpuart_remove, 2764 .driver = { 2765 .name = "fsl-lpuart", 2766 .of_match_table = lpuart_dt_ids, 2767 .pm = &lpuart_pm_ops, 2768 }, 2769 }; 2770 2771 static int __init lpuart_serial_init(void) 2772 { 2773 int ret = uart_register_driver(&lpuart_reg); 2774 2775 if (ret) 2776 return ret; 2777 2778 ret = platform_driver_register(&lpuart_driver); 2779 if (ret) 2780 uart_unregister_driver(&lpuart_reg); 2781 2782 return ret; 2783 } 2784 2785 static void __exit lpuart_serial_exit(void) 2786 { 2787 ida_destroy(&fsl_lpuart_ida); 2788 platform_driver_unregister(&lpuart_driver); 2789 uart_unregister_driver(&lpuart_reg); 2790 } 2791 2792 module_init(lpuart_serial_init); 2793 module_exit(lpuart_serial_exit); 2794 2795 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2796 MODULE_LICENSE("GPL v2"); 2797