1 /* 2 * Freescale lpuart serial port driver 3 * 4 * Copyright 2012-2014 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 13 #define SUPPORT_SYSRQ 14 #endif 15 16 #include <linux/clk.h> 17 #include <linux/console.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/dmaengine.h> 20 #include <linux/dmapool.h> 21 #include <linux/io.h> 22 #include <linux/irq.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/of_dma.h> 27 #include <linux/serial_core.h> 28 #include <linux/slab.h> 29 #include <linux/tty_flip.h> 30 31 /* All registers are 8-bit width */ 32 #define UARTBDH 0x00 33 #define UARTBDL 0x01 34 #define UARTCR1 0x02 35 #define UARTCR2 0x03 36 #define UARTSR1 0x04 37 #define UARTCR3 0x06 38 #define UARTDR 0x07 39 #define UARTCR4 0x0a 40 #define UARTCR5 0x0b 41 #define UARTMODEM 0x0d 42 #define UARTPFIFO 0x10 43 #define UARTCFIFO 0x11 44 #define UARTSFIFO 0x12 45 #define UARTTWFIFO 0x13 46 #define UARTTCFIFO 0x14 47 #define UARTRWFIFO 0x15 48 49 #define UARTBDH_LBKDIE 0x80 50 #define UARTBDH_RXEDGIE 0x40 51 #define UARTBDH_SBR_MASK 0x1f 52 53 #define UARTCR1_LOOPS 0x80 54 #define UARTCR1_RSRC 0x20 55 #define UARTCR1_M 0x10 56 #define UARTCR1_WAKE 0x08 57 #define UARTCR1_ILT 0x04 58 #define UARTCR1_PE 0x02 59 #define UARTCR1_PT 0x01 60 61 #define UARTCR2_TIE 0x80 62 #define UARTCR2_TCIE 0x40 63 #define UARTCR2_RIE 0x20 64 #define UARTCR2_ILIE 0x10 65 #define UARTCR2_TE 0x08 66 #define UARTCR2_RE 0x04 67 #define UARTCR2_RWU 0x02 68 #define UARTCR2_SBK 0x01 69 70 #define UARTSR1_TDRE 0x80 71 #define UARTSR1_TC 0x40 72 #define UARTSR1_RDRF 0x20 73 #define UARTSR1_IDLE 0x10 74 #define UARTSR1_OR 0x08 75 #define UARTSR1_NF 0x04 76 #define UARTSR1_FE 0x02 77 #define UARTSR1_PE 0x01 78 79 #define UARTCR3_R8 0x80 80 #define UARTCR3_T8 0x40 81 #define UARTCR3_TXDIR 0x20 82 #define UARTCR3_TXINV 0x10 83 #define UARTCR3_ORIE 0x08 84 #define UARTCR3_NEIE 0x04 85 #define UARTCR3_FEIE 0x02 86 #define UARTCR3_PEIE 0x01 87 88 #define UARTCR4_MAEN1 0x80 89 #define UARTCR4_MAEN2 0x40 90 #define UARTCR4_M10 0x20 91 #define UARTCR4_BRFA_MASK 0x1f 92 #define UARTCR4_BRFA_OFF 0 93 94 #define UARTCR5_TDMAS 0x80 95 #define UARTCR5_RDMAS 0x20 96 97 #define UARTMODEM_RXRTSE 0x08 98 #define UARTMODEM_TXRTSPOL 0x04 99 #define UARTMODEM_TXRTSE 0x02 100 #define UARTMODEM_TXCTSE 0x01 101 102 #define UARTPFIFO_TXFE 0x80 103 #define UARTPFIFO_FIFOSIZE_MASK 0x7 104 #define UARTPFIFO_TXSIZE_OFF 4 105 #define UARTPFIFO_RXFE 0x08 106 #define UARTPFIFO_RXSIZE_OFF 0 107 108 #define UARTCFIFO_TXFLUSH 0x80 109 #define UARTCFIFO_RXFLUSH 0x40 110 #define UARTCFIFO_RXOFE 0x04 111 #define UARTCFIFO_TXOFE 0x02 112 #define UARTCFIFO_RXUFE 0x01 113 114 #define UARTSFIFO_TXEMPT 0x80 115 #define UARTSFIFO_RXEMPT 0x40 116 #define UARTSFIFO_RXOF 0x04 117 #define UARTSFIFO_TXOF 0x02 118 #define UARTSFIFO_RXUF 0x01 119 120 /* 32-bit register defination */ 121 #define UARTBAUD 0x00 122 #define UARTSTAT 0x04 123 #define UARTCTRL 0x08 124 #define UARTDATA 0x0C 125 #define UARTMATCH 0x10 126 #define UARTMODIR 0x14 127 #define UARTFIFO 0x18 128 #define UARTWATER 0x1c 129 130 #define UARTBAUD_MAEN1 0x80000000 131 #define UARTBAUD_MAEN2 0x40000000 132 #define UARTBAUD_M10 0x20000000 133 #define UARTBAUD_TDMAE 0x00800000 134 #define UARTBAUD_RDMAE 0x00200000 135 #define UARTBAUD_MATCFG 0x00400000 136 #define UARTBAUD_BOTHEDGE 0x00020000 137 #define UARTBAUD_RESYNCDIS 0x00010000 138 #define UARTBAUD_LBKDIE 0x00008000 139 #define UARTBAUD_RXEDGIE 0x00004000 140 #define UARTBAUD_SBNS 0x00002000 141 #define UARTBAUD_SBR 0x00000000 142 #define UARTBAUD_SBR_MASK 0x1fff 143 144 #define UARTSTAT_LBKDIF 0x80000000 145 #define UARTSTAT_RXEDGIF 0x40000000 146 #define UARTSTAT_MSBF 0x20000000 147 #define UARTSTAT_RXINV 0x10000000 148 #define UARTSTAT_RWUID 0x08000000 149 #define UARTSTAT_BRK13 0x04000000 150 #define UARTSTAT_LBKDE 0x02000000 151 #define UARTSTAT_RAF 0x01000000 152 #define UARTSTAT_TDRE 0x00800000 153 #define UARTSTAT_TC 0x00400000 154 #define UARTSTAT_RDRF 0x00200000 155 #define UARTSTAT_IDLE 0x00100000 156 #define UARTSTAT_OR 0x00080000 157 #define UARTSTAT_NF 0x00040000 158 #define UARTSTAT_FE 0x00020000 159 #define UARTSTAT_PE 0x00010000 160 #define UARTSTAT_MA1F 0x00008000 161 #define UARTSTAT_M21F 0x00004000 162 163 #define UARTCTRL_R8T9 0x80000000 164 #define UARTCTRL_R9T8 0x40000000 165 #define UARTCTRL_TXDIR 0x20000000 166 #define UARTCTRL_TXINV 0x10000000 167 #define UARTCTRL_ORIE 0x08000000 168 #define UARTCTRL_NEIE 0x04000000 169 #define UARTCTRL_FEIE 0x02000000 170 #define UARTCTRL_PEIE 0x01000000 171 #define UARTCTRL_TIE 0x00800000 172 #define UARTCTRL_TCIE 0x00400000 173 #define UARTCTRL_RIE 0x00200000 174 #define UARTCTRL_ILIE 0x00100000 175 #define UARTCTRL_TE 0x00080000 176 #define UARTCTRL_RE 0x00040000 177 #define UARTCTRL_RWU 0x00020000 178 #define UARTCTRL_SBK 0x00010000 179 #define UARTCTRL_MA1IE 0x00008000 180 #define UARTCTRL_MA2IE 0x00004000 181 #define UARTCTRL_IDLECFG 0x00000100 182 #define UARTCTRL_LOOPS 0x00000080 183 #define UARTCTRL_DOZEEN 0x00000040 184 #define UARTCTRL_RSRC 0x00000020 185 #define UARTCTRL_M 0x00000010 186 #define UARTCTRL_WAKE 0x00000008 187 #define UARTCTRL_ILT 0x00000004 188 #define UARTCTRL_PE 0x00000002 189 #define UARTCTRL_PT 0x00000001 190 191 #define UARTDATA_NOISY 0x00008000 192 #define UARTDATA_PARITYE 0x00004000 193 #define UARTDATA_FRETSC 0x00002000 194 #define UARTDATA_RXEMPT 0x00001000 195 #define UARTDATA_IDLINE 0x00000800 196 #define UARTDATA_MASK 0x3ff 197 198 #define UARTMODIR_IREN 0x00020000 199 #define UARTMODIR_TXCTSSRC 0x00000020 200 #define UARTMODIR_TXCTSC 0x00000010 201 #define UARTMODIR_RXRTSE 0x00000008 202 #define UARTMODIR_TXRTSPOL 0x00000004 203 #define UARTMODIR_TXRTSE 0x00000002 204 #define UARTMODIR_TXCTSE 0x00000001 205 206 #define UARTFIFO_TXEMPT 0x00800000 207 #define UARTFIFO_RXEMPT 0x00400000 208 #define UARTFIFO_TXOF 0x00020000 209 #define UARTFIFO_RXUF 0x00010000 210 #define UARTFIFO_TXFLUSH 0x00008000 211 #define UARTFIFO_RXFLUSH 0x00004000 212 #define UARTFIFO_TXOFE 0x00000200 213 #define UARTFIFO_RXUFE 0x00000100 214 #define UARTFIFO_TXFE 0x00000080 215 #define UARTFIFO_FIFOSIZE_MASK 0x7 216 #define UARTFIFO_TXSIZE_OFF 4 217 #define UARTFIFO_RXFE 0x00000008 218 #define UARTFIFO_RXSIZE_OFF 0 219 220 #define UARTWATER_COUNT_MASK 0xff 221 #define UARTWATER_TXCNT_OFF 8 222 #define UARTWATER_RXCNT_OFF 24 223 #define UARTWATER_WATER_MASK 0xff 224 #define UARTWATER_TXWATER_OFF 0 225 #define UARTWATER_RXWATER_OFF 16 226 227 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 228 #define DMA_RX_TIMEOUT (10) 229 230 #define DRIVER_NAME "fsl-lpuart" 231 #define DEV_NAME "ttyLP" 232 #define UART_NR 6 233 234 struct lpuart_port { 235 struct uart_port port; 236 struct clk *clk; 237 unsigned int txfifo_size; 238 unsigned int rxfifo_size; 239 bool lpuart32; 240 241 bool lpuart_dma_tx_use; 242 bool lpuart_dma_rx_use; 243 struct dma_chan *dma_tx_chan; 244 struct dma_chan *dma_rx_chan; 245 struct dma_async_tx_descriptor *dma_tx_desc; 246 struct dma_async_tx_descriptor *dma_rx_desc; 247 dma_cookie_t dma_tx_cookie; 248 dma_cookie_t dma_rx_cookie; 249 unsigned int dma_tx_bytes; 250 unsigned int dma_rx_bytes; 251 bool dma_tx_in_progress; 252 unsigned int dma_rx_timeout; 253 struct timer_list lpuart_timer; 254 struct scatterlist rx_sgl, tx_sgl[2]; 255 struct circ_buf rx_ring; 256 int rx_dma_rng_buf_len; 257 unsigned int dma_tx_nents; 258 wait_queue_head_t dma_wait; 259 }; 260 261 static const struct of_device_id lpuart_dt_ids[] = { 262 { 263 .compatible = "fsl,vf610-lpuart", 264 }, 265 { 266 .compatible = "fsl,ls1021a-lpuart", 267 }, 268 { /* sentinel */ } 269 }; 270 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 271 272 /* Forward declare this for the dma callbacks*/ 273 static void lpuart_dma_tx_complete(void *arg); 274 275 static u32 lpuart32_read(void __iomem *addr) 276 { 277 return ioread32be(addr); 278 } 279 280 static void lpuart32_write(u32 val, void __iomem *addr) 281 { 282 iowrite32be(val, addr); 283 } 284 285 static void lpuart_stop_tx(struct uart_port *port) 286 { 287 unsigned char temp; 288 289 temp = readb(port->membase + UARTCR2); 290 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 291 writeb(temp, port->membase + UARTCR2); 292 } 293 294 static void lpuart32_stop_tx(struct uart_port *port) 295 { 296 unsigned long temp; 297 298 temp = lpuart32_read(port->membase + UARTCTRL); 299 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 300 lpuart32_write(temp, port->membase + UARTCTRL); 301 } 302 303 static void lpuart_stop_rx(struct uart_port *port) 304 { 305 unsigned char temp; 306 307 temp = readb(port->membase + UARTCR2); 308 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 309 } 310 311 static void lpuart32_stop_rx(struct uart_port *port) 312 { 313 unsigned long temp; 314 315 temp = lpuart32_read(port->membase + UARTCTRL); 316 lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL); 317 } 318 319 static void lpuart_dma_tx(struct lpuart_port *sport) 320 { 321 struct circ_buf *xmit = &sport->port.state->xmit; 322 struct scatterlist *sgl = sport->tx_sgl; 323 struct device *dev = sport->port.dev; 324 int ret; 325 326 if (sport->dma_tx_in_progress) 327 return; 328 329 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 330 331 if (xmit->tail < xmit->head || xmit->head == 0) { 332 sport->dma_tx_nents = 1; 333 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 334 } else { 335 sport->dma_tx_nents = 2; 336 sg_init_table(sgl, 2); 337 sg_set_buf(sgl, xmit->buf + xmit->tail, 338 UART_XMIT_SIZE - xmit->tail); 339 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 340 } 341 342 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 343 if (!ret) { 344 dev_err(dev, "DMA mapping error for TX.\n"); 345 return; 346 } 347 348 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl, 349 sport->dma_tx_nents, 350 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 351 if (!sport->dma_tx_desc) { 352 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 353 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 354 return; 355 } 356 357 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 358 sport->dma_tx_desc->callback_param = sport; 359 sport->dma_tx_in_progress = true; 360 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 361 dma_async_issue_pending(sport->dma_tx_chan); 362 } 363 364 static void lpuart_dma_tx_complete(void *arg) 365 { 366 struct lpuart_port *sport = arg; 367 struct scatterlist *sgl = &sport->tx_sgl[0]; 368 struct circ_buf *xmit = &sport->port.state->xmit; 369 unsigned long flags; 370 371 spin_lock_irqsave(&sport->port.lock, flags); 372 373 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 374 375 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 376 377 sport->port.icount.tx += sport->dma_tx_bytes; 378 sport->dma_tx_in_progress = false; 379 spin_unlock_irqrestore(&sport->port.lock, flags); 380 381 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 382 uart_write_wakeup(&sport->port); 383 384 if (waitqueue_active(&sport->dma_wait)) { 385 wake_up(&sport->dma_wait); 386 return; 387 } 388 389 spin_lock_irqsave(&sport->port.lock, flags); 390 391 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 392 lpuart_dma_tx(sport); 393 394 spin_unlock_irqrestore(&sport->port.lock, flags); 395 } 396 397 static int lpuart_dma_tx_request(struct uart_port *port) 398 { 399 struct lpuart_port *sport = container_of(port, 400 struct lpuart_port, port); 401 struct dma_slave_config dma_tx_sconfig = {}; 402 int ret; 403 404 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR; 405 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 406 dma_tx_sconfig.dst_maxburst = 1; 407 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 408 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 409 410 if (ret) { 411 dev_err(sport->port.dev, 412 "DMA slave config failed, err = %d\n", ret); 413 return ret; 414 } 415 416 return 0; 417 } 418 419 static void lpuart_flush_buffer(struct uart_port *port) 420 { 421 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 422 423 if (sport->lpuart_dma_tx_use) { 424 if (sport->dma_tx_in_progress) { 425 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 426 sport->dma_tx_nents, DMA_TO_DEVICE); 427 sport->dma_tx_in_progress = false; 428 } 429 dmaengine_terminate_all(sport->dma_tx_chan); 430 } 431 } 432 433 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 434 { 435 struct circ_buf *xmit = &sport->port.state->xmit; 436 437 while (!uart_circ_empty(xmit) && 438 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 439 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 440 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 441 sport->port.icount.tx++; 442 } 443 444 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 445 uart_write_wakeup(&sport->port); 446 447 if (uart_circ_empty(xmit)) 448 lpuart_stop_tx(&sport->port); 449 } 450 451 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 452 { 453 struct circ_buf *xmit = &sport->port.state->xmit; 454 unsigned long txcnt; 455 456 txcnt = lpuart32_read(sport->port.membase + UARTWATER); 457 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 458 txcnt &= UARTWATER_COUNT_MASK; 459 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 460 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA); 461 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 462 sport->port.icount.tx++; 463 txcnt = lpuart32_read(sport->port.membase + UARTWATER); 464 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 465 txcnt &= UARTWATER_COUNT_MASK; 466 } 467 468 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 469 uart_write_wakeup(&sport->port); 470 471 if (uart_circ_empty(xmit)) 472 lpuart32_stop_tx(&sport->port); 473 } 474 475 static void lpuart_start_tx(struct uart_port *port) 476 { 477 struct lpuart_port *sport = container_of(port, 478 struct lpuart_port, port); 479 struct circ_buf *xmit = &sport->port.state->xmit; 480 unsigned char temp; 481 482 temp = readb(port->membase + UARTCR2); 483 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 484 485 if (sport->lpuart_dma_tx_use) { 486 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) 487 lpuart_dma_tx(sport); 488 } else { 489 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 490 lpuart_transmit_buffer(sport); 491 } 492 } 493 494 static void lpuart32_start_tx(struct uart_port *port) 495 { 496 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 497 unsigned long temp; 498 499 temp = lpuart32_read(port->membase + UARTCTRL); 500 lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL); 501 502 if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE) 503 lpuart32_transmit_buffer(sport); 504 } 505 506 /* return TIOCSER_TEMT when transmitter is not busy */ 507 static unsigned int lpuart_tx_empty(struct uart_port *port) 508 { 509 struct lpuart_port *sport = container_of(port, 510 struct lpuart_port, port); 511 unsigned char sr1 = readb(port->membase + UARTSR1); 512 unsigned char sfifo = readb(port->membase + UARTSFIFO); 513 514 if (sport->dma_tx_in_progress) 515 return 0; 516 517 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 518 return TIOCSER_TEMT; 519 520 return 0; 521 } 522 523 static unsigned int lpuart32_tx_empty(struct uart_port *port) 524 { 525 return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ? 526 TIOCSER_TEMT : 0; 527 } 528 529 static irqreturn_t lpuart_txint(int irq, void *dev_id) 530 { 531 struct lpuart_port *sport = dev_id; 532 struct circ_buf *xmit = &sport->port.state->xmit; 533 unsigned long flags; 534 535 spin_lock_irqsave(&sport->port.lock, flags); 536 if (sport->port.x_char) { 537 if (sport->lpuart32) 538 lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA); 539 else 540 writeb(sport->port.x_char, sport->port.membase + UARTDR); 541 goto out; 542 } 543 544 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 545 if (sport->lpuart32) 546 lpuart32_stop_tx(&sport->port); 547 else 548 lpuart_stop_tx(&sport->port); 549 goto out; 550 } 551 552 if (sport->lpuart32) 553 lpuart32_transmit_buffer(sport); 554 else 555 lpuart_transmit_buffer(sport); 556 557 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 558 uart_write_wakeup(&sport->port); 559 560 out: 561 spin_unlock_irqrestore(&sport->port.lock, flags); 562 return IRQ_HANDLED; 563 } 564 565 static irqreturn_t lpuart_rxint(int irq, void *dev_id) 566 { 567 struct lpuart_port *sport = dev_id; 568 unsigned int flg, ignored = 0; 569 struct tty_port *port = &sport->port.state->port; 570 unsigned long flags; 571 unsigned char rx, sr; 572 573 spin_lock_irqsave(&sport->port.lock, flags); 574 575 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 576 flg = TTY_NORMAL; 577 sport->port.icount.rx++; 578 /* 579 * to clear the FE, OR, NF, FE, PE flags, 580 * read SR1 then read DR 581 */ 582 sr = readb(sport->port.membase + UARTSR1); 583 rx = readb(sport->port.membase + UARTDR); 584 585 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 586 continue; 587 588 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 589 if (sr & UARTSR1_PE) 590 sport->port.icount.parity++; 591 else if (sr & UARTSR1_FE) 592 sport->port.icount.frame++; 593 594 if (sr & UARTSR1_OR) 595 sport->port.icount.overrun++; 596 597 if (sr & sport->port.ignore_status_mask) { 598 if (++ignored > 100) 599 goto out; 600 continue; 601 } 602 603 sr &= sport->port.read_status_mask; 604 605 if (sr & UARTSR1_PE) 606 flg = TTY_PARITY; 607 else if (sr & UARTSR1_FE) 608 flg = TTY_FRAME; 609 610 if (sr & UARTSR1_OR) 611 flg = TTY_OVERRUN; 612 613 #ifdef SUPPORT_SYSRQ 614 sport->port.sysrq = 0; 615 #endif 616 } 617 618 tty_insert_flip_char(port, rx, flg); 619 } 620 621 out: 622 spin_unlock_irqrestore(&sport->port.lock, flags); 623 624 tty_flip_buffer_push(port); 625 return IRQ_HANDLED; 626 } 627 628 static irqreturn_t lpuart32_rxint(int irq, void *dev_id) 629 { 630 struct lpuart_port *sport = dev_id; 631 unsigned int flg, ignored = 0; 632 struct tty_port *port = &sport->port.state->port; 633 unsigned long flags; 634 unsigned long rx, sr; 635 636 spin_lock_irqsave(&sport->port.lock, flags); 637 638 while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) { 639 flg = TTY_NORMAL; 640 sport->port.icount.rx++; 641 /* 642 * to clear the FE, OR, NF, FE, PE flags, 643 * read STAT then read DATA reg 644 */ 645 sr = lpuart32_read(sport->port.membase + UARTSTAT); 646 rx = lpuart32_read(sport->port.membase + UARTDATA); 647 rx &= 0x3ff; 648 649 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 650 continue; 651 652 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 653 if (sr & UARTSTAT_PE) 654 sport->port.icount.parity++; 655 else if (sr & UARTSTAT_FE) 656 sport->port.icount.frame++; 657 658 if (sr & UARTSTAT_OR) 659 sport->port.icount.overrun++; 660 661 if (sr & sport->port.ignore_status_mask) { 662 if (++ignored > 100) 663 goto out; 664 continue; 665 } 666 667 sr &= sport->port.read_status_mask; 668 669 if (sr & UARTSTAT_PE) 670 flg = TTY_PARITY; 671 else if (sr & UARTSTAT_FE) 672 flg = TTY_FRAME; 673 674 if (sr & UARTSTAT_OR) 675 flg = TTY_OVERRUN; 676 677 #ifdef SUPPORT_SYSRQ 678 sport->port.sysrq = 0; 679 #endif 680 } 681 682 tty_insert_flip_char(port, rx, flg); 683 } 684 685 out: 686 spin_unlock_irqrestore(&sport->port.lock, flags); 687 688 tty_flip_buffer_push(port); 689 return IRQ_HANDLED; 690 } 691 692 static irqreturn_t lpuart_int(int irq, void *dev_id) 693 { 694 struct lpuart_port *sport = dev_id; 695 unsigned char sts; 696 697 sts = readb(sport->port.membase + UARTSR1); 698 699 if (sts & UARTSR1_RDRF) 700 lpuart_rxint(irq, dev_id); 701 702 if (sts & UARTSR1_TDRE) 703 lpuart_txint(irq, dev_id); 704 705 return IRQ_HANDLED; 706 } 707 708 static irqreturn_t lpuart32_int(int irq, void *dev_id) 709 { 710 struct lpuart_port *sport = dev_id; 711 unsigned long sts, rxcount; 712 713 sts = lpuart32_read(sport->port.membase + UARTSTAT); 714 rxcount = lpuart32_read(sport->port.membase + UARTWATER); 715 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 716 717 if (sts & UARTSTAT_RDRF || rxcount > 0) 718 lpuart32_rxint(irq, dev_id); 719 720 if ((sts & UARTSTAT_TDRE) && 721 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE)) 722 lpuart_txint(irq, dev_id); 723 724 lpuart32_write(sts, sport->port.membase + UARTSTAT); 725 return IRQ_HANDLED; 726 } 727 728 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 729 { 730 struct tty_port *port = &sport->port.state->port; 731 struct dma_tx_state state; 732 enum dma_status dmastat; 733 struct circ_buf *ring = &sport->rx_ring; 734 unsigned long flags; 735 int count = 0; 736 unsigned char sr; 737 738 sr = readb(sport->port.membase + UARTSR1); 739 740 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 741 /* Read DR to clear the error flags */ 742 readb(sport->port.membase + UARTDR); 743 744 if (sr & UARTSR1_PE) 745 sport->port.icount.parity++; 746 else if (sr & UARTSR1_FE) 747 sport->port.icount.frame++; 748 } 749 750 async_tx_ack(sport->dma_rx_desc); 751 752 spin_lock_irqsave(&sport->port.lock, flags); 753 754 dmastat = dmaengine_tx_status(sport->dma_rx_chan, 755 sport->dma_rx_cookie, 756 &state); 757 758 if (dmastat == DMA_ERROR) { 759 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 760 spin_unlock_irqrestore(&sport->port.lock, flags); 761 return; 762 } 763 764 /* CPU claims ownership of RX DMA buffer */ 765 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 766 767 /* 768 * ring->head points to the end of data already written by the DMA. 769 * ring->tail points to the beginning of data to be read by the 770 * framework. 771 * The current transfer size should not be larger than the dma buffer 772 * length. 773 */ 774 ring->head = sport->rx_sgl.length - state.residue; 775 BUG_ON(ring->head > sport->rx_sgl.length); 776 /* 777 * At this point ring->head may point to the first byte right after the 778 * last byte of the dma buffer: 779 * 0 <= ring->head <= sport->rx_sgl.length 780 * 781 * However ring->tail must always points inside the dma buffer: 782 * 0 <= ring->tail <= sport->rx_sgl.length - 1 783 * 784 * Since we use a ring buffer, we have to handle the case 785 * where head is lower than tail. In such a case, we first read from 786 * tail to the end of the buffer then reset tail. 787 */ 788 if (ring->head < ring->tail) { 789 count = sport->rx_sgl.length - ring->tail; 790 791 tty_insert_flip_string(port, ring->buf + ring->tail, count); 792 ring->tail = 0; 793 sport->port.icount.rx += count; 794 } 795 796 /* Finally we read data from tail to head */ 797 if (ring->tail < ring->head) { 798 count = ring->head - ring->tail; 799 tty_insert_flip_string(port, ring->buf + ring->tail, count); 800 /* Wrap ring->head if needed */ 801 if (ring->head >= sport->rx_sgl.length) 802 ring->head = 0; 803 ring->tail = ring->head; 804 sport->port.icount.rx += count; 805 } 806 807 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1, 808 DMA_FROM_DEVICE); 809 810 spin_unlock_irqrestore(&sport->port.lock, flags); 811 812 tty_flip_buffer_push(port); 813 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 814 } 815 816 static void lpuart_dma_rx_complete(void *arg) 817 { 818 struct lpuart_port *sport = arg; 819 820 lpuart_copy_rx_to_tty(sport); 821 } 822 823 static void lpuart_timer_func(unsigned long data) 824 { 825 struct lpuart_port *sport = (struct lpuart_port *)data; 826 827 lpuart_copy_rx_to_tty(sport); 828 } 829 830 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 831 { 832 struct dma_slave_config dma_rx_sconfig = {}; 833 struct circ_buf *ring = &sport->rx_ring; 834 int ret, nent; 835 int bits, baud; 836 struct tty_struct *tty = tty_port_tty_get(&sport->port.state->port); 837 struct ktermios *termios = &tty->termios; 838 839 baud = tty_get_baud_rate(tty); 840 841 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; 842 if (termios->c_cflag & PARENB) 843 bits++; 844 845 /* 846 * Calculate length of one DMA buffer size to keep latency below 847 * 10ms at any baud rate. 848 */ 849 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 850 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 851 if (sport->rx_dma_rng_buf_len < 16) 852 sport->rx_dma_rng_buf_len = 16; 853 854 ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 855 if (!ring->buf) { 856 dev_err(sport->port.dev, "Ring buf alloc failed\n"); 857 return -ENOMEM; 858 } 859 860 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 861 sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 862 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 863 864 if (!nent) { 865 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 866 return -EINVAL; 867 } 868 869 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR; 870 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 871 dma_rx_sconfig.src_maxburst = 1; 872 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 873 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig); 874 875 if (ret < 0) { 876 dev_err(sport->port.dev, 877 "DMA Rx slave config failed, err = %d\n", ret); 878 return ret; 879 } 880 881 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan, 882 sg_dma_address(&sport->rx_sgl), 883 sport->rx_sgl.length, 884 sport->rx_sgl.length / 2, 885 DMA_DEV_TO_MEM, 886 DMA_PREP_INTERRUPT); 887 if (!sport->dma_rx_desc) { 888 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 889 return -EFAULT; 890 } 891 892 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 893 sport->dma_rx_desc->callback_param = sport; 894 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 895 dma_async_issue_pending(sport->dma_rx_chan); 896 897 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 898 sport->port.membase + UARTCR5); 899 900 return 0; 901 } 902 903 static void lpuart_dma_rx_free(struct uart_port *port) 904 { 905 struct lpuart_port *sport = container_of(port, 906 struct lpuart_port, port); 907 908 if (sport->dma_rx_chan) 909 dmaengine_terminate_all(sport->dma_rx_chan); 910 911 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 912 kfree(sport->rx_ring.buf); 913 sport->rx_ring.tail = 0; 914 sport->rx_ring.head = 0; 915 sport->dma_rx_desc = NULL; 916 sport->dma_rx_cookie = -EINVAL; 917 } 918 919 static int lpuart_config_rs485(struct uart_port *port, 920 struct serial_rs485 *rs485) 921 { 922 struct lpuart_port *sport = container_of(port, 923 struct lpuart_port, port); 924 925 u8 modem = readb(sport->port.membase + UARTMODEM) & 926 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 927 writeb(modem, sport->port.membase + UARTMODEM); 928 929 if (rs485->flags & SER_RS485_ENABLED) { 930 /* Enable auto RS-485 RTS mode */ 931 modem |= UARTMODEM_TXRTSE; 932 933 /* 934 * RTS needs to be logic HIGH either during transer _or_ after 935 * transfer, other variants are not supported by the hardware. 936 */ 937 938 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 939 SER_RS485_RTS_AFTER_SEND))) 940 rs485->flags |= SER_RS485_RTS_ON_SEND; 941 942 if (rs485->flags & SER_RS485_RTS_ON_SEND && 943 rs485->flags & SER_RS485_RTS_AFTER_SEND) 944 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 945 946 /* 947 * The hardware defaults to RTS logic HIGH while transfer. 948 * Switch polarity in case RTS shall be logic HIGH 949 * after transfer. 950 * Note: UART is assumed to be active high. 951 */ 952 if (rs485->flags & SER_RS485_RTS_ON_SEND) 953 modem &= ~UARTMODEM_TXRTSPOL; 954 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 955 modem |= UARTMODEM_TXRTSPOL; 956 } 957 958 /* Store the new configuration */ 959 sport->port.rs485 = *rs485; 960 961 writeb(modem, sport->port.membase + UARTMODEM); 962 return 0; 963 } 964 965 static unsigned int lpuart_get_mctrl(struct uart_port *port) 966 { 967 unsigned int temp = 0; 968 unsigned char reg; 969 970 reg = readb(port->membase + UARTMODEM); 971 if (reg & UARTMODEM_TXCTSE) 972 temp |= TIOCM_CTS; 973 974 if (reg & UARTMODEM_RXRTSE) 975 temp |= TIOCM_RTS; 976 977 return temp; 978 } 979 980 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 981 { 982 unsigned int temp = 0; 983 unsigned long reg; 984 985 reg = lpuart32_read(port->membase + UARTMODIR); 986 if (reg & UARTMODIR_TXCTSE) 987 temp |= TIOCM_CTS; 988 989 if (reg & UARTMODIR_RXRTSE) 990 temp |= TIOCM_RTS; 991 992 return temp; 993 } 994 995 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 996 { 997 unsigned char temp; 998 struct lpuart_port *sport = container_of(port, 999 struct lpuart_port, port); 1000 1001 /* Make sure RXRTSE bit is not set when RS485 is enabled */ 1002 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { 1003 temp = readb(sport->port.membase + UARTMODEM) & 1004 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1005 1006 if (mctrl & TIOCM_RTS) 1007 temp |= UARTMODEM_RXRTSE; 1008 1009 if (mctrl & TIOCM_CTS) 1010 temp |= UARTMODEM_TXCTSE; 1011 1012 writeb(temp, port->membase + UARTMODEM); 1013 } 1014 } 1015 1016 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1017 { 1018 unsigned long temp; 1019 1020 temp = lpuart32_read(port->membase + UARTMODIR) & 1021 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 1022 1023 if (mctrl & TIOCM_RTS) 1024 temp |= UARTMODIR_RXRTSE; 1025 1026 if (mctrl & TIOCM_CTS) 1027 temp |= UARTMODIR_TXCTSE; 1028 1029 lpuart32_write(temp, port->membase + UARTMODIR); 1030 } 1031 1032 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1033 { 1034 unsigned char temp; 1035 1036 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1037 1038 if (break_state != 0) 1039 temp |= UARTCR2_SBK; 1040 1041 writeb(temp, port->membase + UARTCR2); 1042 } 1043 1044 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1045 { 1046 unsigned long temp; 1047 1048 temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK; 1049 1050 if (break_state != 0) 1051 temp |= UARTCTRL_SBK; 1052 1053 lpuart32_write(temp, port->membase + UARTCTRL); 1054 } 1055 1056 static void lpuart_setup_watermark(struct lpuart_port *sport) 1057 { 1058 unsigned char val, cr2; 1059 unsigned char cr2_saved; 1060 1061 cr2 = readb(sport->port.membase + UARTCR2); 1062 cr2_saved = cr2; 1063 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1064 UARTCR2_RIE | UARTCR2_RE); 1065 writeb(cr2, sport->port.membase + UARTCR2); 1066 1067 val = readb(sport->port.membase + UARTPFIFO); 1068 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1069 sport->port.membase + UARTPFIFO); 1070 1071 /* flush Tx and Rx FIFO */ 1072 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1073 sport->port.membase + UARTCFIFO); 1074 1075 /* explicitly clear RDRF */ 1076 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1077 readb(sport->port.membase + UARTDR); 1078 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1079 } 1080 1081 writeb(0, sport->port.membase + UARTTWFIFO); 1082 writeb(1, sport->port.membase + UARTRWFIFO); 1083 1084 /* Restore cr2 */ 1085 writeb(cr2_saved, sport->port.membase + UARTCR2); 1086 } 1087 1088 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1089 { 1090 unsigned long val, ctrl; 1091 unsigned long ctrl_saved; 1092 1093 ctrl = lpuart32_read(sport->port.membase + UARTCTRL); 1094 ctrl_saved = ctrl; 1095 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1096 UARTCTRL_RIE | UARTCTRL_RE); 1097 lpuart32_write(ctrl, sport->port.membase + UARTCTRL); 1098 1099 /* enable FIFO mode */ 1100 val = lpuart32_read(sport->port.membase + UARTFIFO); 1101 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1102 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1103 lpuart32_write(val, sport->port.membase + UARTFIFO); 1104 1105 /* set the watermark */ 1106 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1107 lpuart32_write(val, sport->port.membase + UARTWATER); 1108 1109 /* Restore cr2 */ 1110 lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL); 1111 } 1112 1113 static void rx_dma_timer_init(struct lpuart_port *sport) 1114 { 1115 setup_timer(&sport->lpuart_timer, lpuart_timer_func, 1116 (unsigned long)sport); 1117 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1118 add_timer(&sport->lpuart_timer); 1119 } 1120 1121 static int lpuart_startup(struct uart_port *port) 1122 { 1123 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1124 int ret; 1125 unsigned long flags; 1126 unsigned char temp; 1127 1128 /* determine FIFO size and enable FIFO mode */ 1129 temp = readb(sport->port.membase + UARTPFIFO); 1130 1131 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) & 1132 UARTPFIFO_FIFOSIZE_MASK) + 1); 1133 1134 sport->port.fifosize = sport->txfifo_size; 1135 1136 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) & 1137 UARTPFIFO_FIFOSIZE_MASK) + 1); 1138 1139 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0, 1140 DRIVER_NAME, sport); 1141 if (ret) 1142 return ret; 1143 1144 spin_lock_irqsave(&sport->port.lock, flags); 1145 1146 lpuart_setup_watermark(sport); 1147 1148 temp = readb(sport->port.membase + UARTCR2); 1149 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 1150 writeb(temp, sport->port.membase + UARTCR2); 1151 1152 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) { 1153 /* set Rx DMA timeout */ 1154 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1155 if (!sport->dma_rx_timeout) 1156 sport->dma_rx_timeout = 1; 1157 1158 sport->lpuart_dma_rx_use = true; 1159 rx_dma_timer_init(sport); 1160 } else { 1161 sport->lpuart_dma_rx_use = false; 1162 } 1163 1164 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) { 1165 init_waitqueue_head(&sport->dma_wait); 1166 sport->lpuart_dma_tx_use = true; 1167 temp = readb(port->membase + UARTCR5); 1168 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5); 1169 } else { 1170 sport->lpuart_dma_tx_use = false; 1171 } 1172 1173 spin_unlock_irqrestore(&sport->port.lock, flags); 1174 1175 return 0; 1176 } 1177 1178 static int lpuart32_startup(struct uart_port *port) 1179 { 1180 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1181 int ret; 1182 unsigned long flags; 1183 unsigned long temp; 1184 1185 /* determine FIFO size */ 1186 temp = lpuart32_read(sport->port.membase + UARTFIFO); 1187 1188 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) & 1189 UARTFIFO_FIFOSIZE_MASK) - 1); 1190 1191 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) & 1192 UARTFIFO_FIFOSIZE_MASK) - 1); 1193 1194 ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0, 1195 DRIVER_NAME, sport); 1196 if (ret) 1197 return ret; 1198 1199 spin_lock_irqsave(&sport->port.lock, flags); 1200 1201 lpuart32_setup_watermark(sport); 1202 1203 temp = lpuart32_read(sport->port.membase + UARTCTRL); 1204 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE); 1205 temp |= UARTCTRL_ILIE; 1206 lpuart32_write(temp, sport->port.membase + UARTCTRL); 1207 1208 spin_unlock_irqrestore(&sport->port.lock, flags); 1209 return 0; 1210 } 1211 1212 static void lpuart_shutdown(struct uart_port *port) 1213 { 1214 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1215 unsigned char temp; 1216 unsigned long flags; 1217 1218 spin_lock_irqsave(&port->lock, flags); 1219 1220 /* disable Rx/Tx and interrupts */ 1221 temp = readb(port->membase + UARTCR2); 1222 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1223 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1224 writeb(temp, port->membase + UARTCR2); 1225 1226 spin_unlock_irqrestore(&port->lock, flags); 1227 1228 devm_free_irq(port->dev, port->irq, sport); 1229 1230 if (sport->lpuart_dma_rx_use) { 1231 del_timer_sync(&sport->lpuart_timer); 1232 lpuart_dma_rx_free(&sport->port); 1233 } 1234 1235 if (sport->lpuart_dma_tx_use) { 1236 if (wait_event_interruptible(sport->dma_wait, 1237 !sport->dma_tx_in_progress) != false) { 1238 sport->dma_tx_in_progress = false; 1239 dmaengine_terminate_all(sport->dma_tx_chan); 1240 } 1241 1242 lpuart_stop_tx(port); 1243 } 1244 } 1245 1246 static void lpuart32_shutdown(struct uart_port *port) 1247 { 1248 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1249 unsigned long temp; 1250 unsigned long flags; 1251 1252 spin_lock_irqsave(&port->lock, flags); 1253 1254 /* disable Rx/Tx and interrupts */ 1255 temp = lpuart32_read(port->membase + UARTCTRL); 1256 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1257 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1258 lpuart32_write(temp, port->membase + UARTCTRL); 1259 1260 spin_unlock_irqrestore(&port->lock, flags); 1261 1262 devm_free_irq(port->dev, port->irq, sport); 1263 } 1264 1265 static void 1266 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1267 struct ktermios *old) 1268 { 1269 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1270 unsigned long flags; 1271 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1272 unsigned int baud; 1273 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1274 unsigned int sbr, brfa; 1275 1276 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1277 old_cr2 = readb(sport->port.membase + UARTCR2); 1278 cr3 = readb(sport->port.membase + UARTCR3); 1279 cr4 = readb(sport->port.membase + UARTCR4); 1280 bdh = readb(sport->port.membase + UARTBDH); 1281 modem = readb(sport->port.membase + UARTMODEM); 1282 /* 1283 * only support CS8 and CS7, and for CS7 must enable PE. 1284 * supported mode: 1285 * - (7,e/o,1) 1286 * - (8,n,1) 1287 * - (8,m/s,1) 1288 * - (8,e/o,1) 1289 */ 1290 while ((termios->c_cflag & CSIZE) != CS8 && 1291 (termios->c_cflag & CSIZE) != CS7) { 1292 termios->c_cflag &= ~CSIZE; 1293 termios->c_cflag |= old_csize; 1294 old_csize = CS8; 1295 } 1296 1297 if ((termios->c_cflag & CSIZE) == CS8 || 1298 (termios->c_cflag & CSIZE) == CS7) 1299 cr1 = old_cr1 & ~UARTCR1_M; 1300 1301 if (termios->c_cflag & CMSPAR) { 1302 if ((termios->c_cflag & CSIZE) != CS8) { 1303 termios->c_cflag &= ~CSIZE; 1304 termios->c_cflag |= CS8; 1305 } 1306 cr1 |= UARTCR1_M; 1307 } 1308 1309 /* 1310 * When auto RS-485 RTS mode is enabled, 1311 * hardware flow control need to be disabled. 1312 */ 1313 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1314 termios->c_cflag &= ~CRTSCTS; 1315 1316 if (termios->c_cflag & CRTSCTS) { 1317 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1318 } else { 1319 termios->c_cflag &= ~CRTSCTS; 1320 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1321 } 1322 1323 if (termios->c_cflag & CSTOPB) 1324 termios->c_cflag &= ~CSTOPB; 1325 1326 /* parity must be enabled when CS7 to match 8-bits format */ 1327 if ((termios->c_cflag & CSIZE) == CS7) 1328 termios->c_cflag |= PARENB; 1329 1330 if ((termios->c_cflag & PARENB)) { 1331 if (termios->c_cflag & CMSPAR) { 1332 cr1 &= ~UARTCR1_PE; 1333 if (termios->c_cflag & PARODD) 1334 cr3 |= UARTCR3_T8; 1335 else 1336 cr3 &= ~UARTCR3_T8; 1337 } else { 1338 cr1 |= UARTCR1_PE; 1339 if ((termios->c_cflag & CSIZE) == CS8) 1340 cr1 |= UARTCR1_M; 1341 if (termios->c_cflag & PARODD) 1342 cr1 |= UARTCR1_PT; 1343 else 1344 cr1 &= ~UARTCR1_PT; 1345 } 1346 } 1347 1348 /* ask the core to calculate the divisor */ 1349 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1350 1351 spin_lock_irqsave(&sport->port.lock, flags); 1352 1353 sport->port.read_status_mask = 0; 1354 if (termios->c_iflag & INPCK) 1355 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE); 1356 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1357 sport->port.read_status_mask |= UARTSR1_FE; 1358 1359 /* characters to ignore */ 1360 sport->port.ignore_status_mask = 0; 1361 if (termios->c_iflag & IGNPAR) 1362 sport->port.ignore_status_mask |= UARTSR1_PE; 1363 if (termios->c_iflag & IGNBRK) { 1364 sport->port.ignore_status_mask |= UARTSR1_FE; 1365 /* 1366 * if we're ignoring parity and break indicators, 1367 * ignore overruns too (for real raw support). 1368 */ 1369 if (termios->c_iflag & IGNPAR) 1370 sport->port.ignore_status_mask |= UARTSR1_OR; 1371 } 1372 1373 /* update the per-port timeout */ 1374 uart_update_timeout(port, termios->c_cflag, baud); 1375 1376 /* wait transmit engin complete */ 1377 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1378 barrier(); 1379 1380 /* disable transmit and receive */ 1381 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1382 sport->port.membase + UARTCR2); 1383 1384 sbr = sport->port.uartclk / (16 * baud); 1385 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1386 bdh &= ~UARTBDH_SBR_MASK; 1387 bdh |= (sbr >> 8) & 0x1F; 1388 cr4 &= ~UARTCR4_BRFA_MASK; 1389 brfa &= UARTCR4_BRFA_MASK; 1390 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1391 writeb(bdh, sport->port.membase + UARTBDH); 1392 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1393 writeb(cr3, sport->port.membase + UARTCR3); 1394 writeb(cr1, sport->port.membase + UARTCR1); 1395 writeb(modem, sport->port.membase + UARTMODEM); 1396 1397 /* restore control register */ 1398 writeb(old_cr2, sport->port.membase + UARTCR2); 1399 1400 /* 1401 * If new baud rate is set, we will also need to update the Ring buffer 1402 * length according to the selected baud rate and restart Rx DMA path. 1403 */ 1404 if (old) { 1405 if (sport->lpuart_dma_rx_use) { 1406 del_timer_sync(&sport->lpuart_timer); 1407 lpuart_dma_rx_free(&sport->port); 1408 } 1409 1410 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) { 1411 sport->lpuart_dma_rx_use = true; 1412 rx_dma_timer_init(sport); 1413 } else { 1414 sport->lpuart_dma_rx_use = false; 1415 } 1416 } 1417 1418 spin_unlock_irqrestore(&sport->port.lock, flags); 1419 } 1420 1421 static void 1422 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 1423 struct ktermios *old) 1424 { 1425 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1426 unsigned long flags; 1427 unsigned long ctrl, old_ctrl, bd, modem; 1428 unsigned int baud; 1429 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1430 unsigned int sbr; 1431 1432 ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL); 1433 bd = lpuart32_read(sport->port.membase + UARTBAUD); 1434 modem = lpuart32_read(sport->port.membase + UARTMODIR); 1435 /* 1436 * only support CS8 and CS7, and for CS7 must enable PE. 1437 * supported mode: 1438 * - (7,e/o,1) 1439 * - (8,n,1) 1440 * - (8,m/s,1) 1441 * - (8,e/o,1) 1442 */ 1443 while ((termios->c_cflag & CSIZE) != CS8 && 1444 (termios->c_cflag & CSIZE) != CS7) { 1445 termios->c_cflag &= ~CSIZE; 1446 termios->c_cflag |= old_csize; 1447 old_csize = CS8; 1448 } 1449 1450 if ((termios->c_cflag & CSIZE) == CS8 || 1451 (termios->c_cflag & CSIZE) == CS7) 1452 ctrl = old_ctrl & ~UARTCTRL_M; 1453 1454 if (termios->c_cflag & CMSPAR) { 1455 if ((termios->c_cflag & CSIZE) != CS8) { 1456 termios->c_cflag &= ~CSIZE; 1457 termios->c_cflag |= CS8; 1458 } 1459 ctrl |= UARTCTRL_M; 1460 } 1461 1462 if (termios->c_cflag & CRTSCTS) { 1463 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1464 } else { 1465 termios->c_cflag &= ~CRTSCTS; 1466 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1467 } 1468 1469 if (termios->c_cflag & CSTOPB) 1470 termios->c_cflag &= ~CSTOPB; 1471 1472 /* parity must be enabled when CS7 to match 8-bits format */ 1473 if ((termios->c_cflag & CSIZE) == CS7) 1474 termios->c_cflag |= PARENB; 1475 1476 if ((termios->c_cflag & PARENB)) { 1477 if (termios->c_cflag & CMSPAR) { 1478 ctrl &= ~UARTCTRL_PE; 1479 ctrl |= UARTCTRL_M; 1480 } else { 1481 ctrl |= UARTCR1_PE; 1482 if ((termios->c_cflag & CSIZE) == CS8) 1483 ctrl |= UARTCTRL_M; 1484 if (termios->c_cflag & PARODD) 1485 ctrl |= UARTCTRL_PT; 1486 else 1487 ctrl &= ~UARTCTRL_PT; 1488 } 1489 } 1490 1491 /* ask the core to calculate the divisor */ 1492 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1493 1494 spin_lock_irqsave(&sport->port.lock, flags); 1495 1496 sport->port.read_status_mask = 0; 1497 if (termios->c_iflag & INPCK) 1498 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE); 1499 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1500 sport->port.read_status_mask |= UARTSTAT_FE; 1501 1502 /* characters to ignore */ 1503 sport->port.ignore_status_mask = 0; 1504 if (termios->c_iflag & IGNPAR) 1505 sport->port.ignore_status_mask |= UARTSTAT_PE; 1506 if (termios->c_iflag & IGNBRK) { 1507 sport->port.ignore_status_mask |= UARTSTAT_FE; 1508 /* 1509 * if we're ignoring parity and break indicators, 1510 * ignore overruns too (for real raw support). 1511 */ 1512 if (termios->c_iflag & IGNPAR) 1513 sport->port.ignore_status_mask |= UARTSTAT_OR; 1514 } 1515 1516 /* update the per-port timeout */ 1517 uart_update_timeout(port, termios->c_cflag, baud); 1518 1519 /* wait transmit engin complete */ 1520 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC)) 1521 barrier(); 1522 1523 /* disable transmit and receive */ 1524 lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 1525 sport->port.membase + UARTCTRL); 1526 1527 sbr = sport->port.uartclk / (16 * baud); 1528 bd &= ~UARTBAUD_SBR_MASK; 1529 bd |= sbr & UARTBAUD_SBR_MASK; 1530 bd |= UARTBAUD_BOTHEDGE; 1531 bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); 1532 lpuart32_write(bd, sport->port.membase + UARTBAUD); 1533 lpuart32_write(modem, sport->port.membase + UARTMODIR); 1534 lpuart32_write(ctrl, sport->port.membase + UARTCTRL); 1535 /* restore control register */ 1536 1537 spin_unlock_irqrestore(&sport->port.lock, flags); 1538 } 1539 1540 static const char *lpuart_type(struct uart_port *port) 1541 { 1542 return "FSL_LPUART"; 1543 } 1544 1545 static void lpuart_release_port(struct uart_port *port) 1546 { 1547 /* nothing to do */ 1548 } 1549 1550 static int lpuart_request_port(struct uart_port *port) 1551 { 1552 return 0; 1553 } 1554 1555 /* configure/autoconfigure the port */ 1556 static void lpuart_config_port(struct uart_port *port, int flags) 1557 { 1558 if (flags & UART_CONFIG_TYPE) 1559 port->type = PORT_LPUART; 1560 } 1561 1562 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 1563 { 1564 int ret = 0; 1565 1566 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 1567 ret = -EINVAL; 1568 if (port->irq != ser->irq) 1569 ret = -EINVAL; 1570 if (ser->io_type != UPIO_MEM) 1571 ret = -EINVAL; 1572 if (port->uartclk / 16 != ser->baud_base) 1573 ret = -EINVAL; 1574 if (port->iobase != ser->port) 1575 ret = -EINVAL; 1576 if (ser->hub6 != 0) 1577 ret = -EINVAL; 1578 return ret; 1579 } 1580 1581 static const struct uart_ops lpuart_pops = { 1582 .tx_empty = lpuart_tx_empty, 1583 .set_mctrl = lpuart_set_mctrl, 1584 .get_mctrl = lpuart_get_mctrl, 1585 .stop_tx = lpuart_stop_tx, 1586 .start_tx = lpuart_start_tx, 1587 .stop_rx = lpuart_stop_rx, 1588 .break_ctl = lpuart_break_ctl, 1589 .startup = lpuart_startup, 1590 .shutdown = lpuart_shutdown, 1591 .set_termios = lpuart_set_termios, 1592 .type = lpuart_type, 1593 .request_port = lpuart_request_port, 1594 .release_port = lpuart_release_port, 1595 .config_port = lpuart_config_port, 1596 .verify_port = lpuart_verify_port, 1597 .flush_buffer = lpuart_flush_buffer, 1598 }; 1599 1600 static const struct uart_ops lpuart32_pops = { 1601 .tx_empty = lpuart32_tx_empty, 1602 .set_mctrl = lpuart32_set_mctrl, 1603 .get_mctrl = lpuart32_get_mctrl, 1604 .stop_tx = lpuart32_stop_tx, 1605 .start_tx = lpuart32_start_tx, 1606 .stop_rx = lpuart32_stop_rx, 1607 .break_ctl = lpuart32_break_ctl, 1608 .startup = lpuart32_startup, 1609 .shutdown = lpuart32_shutdown, 1610 .set_termios = lpuart32_set_termios, 1611 .type = lpuart_type, 1612 .request_port = lpuart_request_port, 1613 .release_port = lpuart_release_port, 1614 .config_port = lpuart_config_port, 1615 .verify_port = lpuart_verify_port, 1616 .flush_buffer = lpuart_flush_buffer, 1617 }; 1618 1619 static struct lpuart_port *lpuart_ports[UART_NR]; 1620 1621 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 1622 static void lpuart_console_putchar(struct uart_port *port, int ch) 1623 { 1624 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) 1625 barrier(); 1626 1627 writeb(ch, port->membase + UARTDR); 1628 } 1629 1630 static void lpuart32_console_putchar(struct uart_port *port, int ch) 1631 { 1632 while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)) 1633 barrier(); 1634 1635 lpuart32_write(ch, port->membase + UARTDATA); 1636 } 1637 1638 static void 1639 lpuart_console_write(struct console *co, const char *s, unsigned int count) 1640 { 1641 struct lpuart_port *sport = lpuart_ports[co->index]; 1642 unsigned char old_cr2, cr2; 1643 1644 /* first save CR2 and then disable interrupts */ 1645 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 1646 cr2 |= (UARTCR2_TE | UARTCR2_RE); 1647 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1648 writeb(cr2, sport->port.membase + UARTCR2); 1649 1650 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 1651 1652 /* wait for transmitter finish complete and restore CR2 */ 1653 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1654 barrier(); 1655 1656 writeb(old_cr2, sport->port.membase + UARTCR2); 1657 } 1658 1659 static void 1660 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 1661 { 1662 struct lpuart_port *sport = lpuart_ports[co->index]; 1663 unsigned long old_cr, cr; 1664 1665 /* first save CR2 and then disable interrupts */ 1666 cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL); 1667 cr |= (UARTCTRL_TE | UARTCTRL_RE); 1668 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1669 lpuart32_write(cr, sport->port.membase + UARTCTRL); 1670 1671 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 1672 1673 /* wait for transmitter finish complete and restore CR2 */ 1674 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC)) 1675 barrier(); 1676 1677 lpuart32_write(old_cr, sport->port.membase + UARTCTRL); 1678 } 1679 1680 /* 1681 * if the port was already initialised (eg, by a boot loader), 1682 * try to determine the current setup. 1683 */ 1684 static void __init 1685 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 1686 int *parity, int *bits) 1687 { 1688 unsigned char cr, bdh, bdl, brfa; 1689 unsigned int sbr, uartclk, baud_raw; 1690 1691 cr = readb(sport->port.membase + UARTCR2); 1692 cr &= UARTCR2_TE | UARTCR2_RE; 1693 if (!cr) 1694 return; 1695 1696 /* ok, the port was enabled */ 1697 1698 cr = readb(sport->port.membase + UARTCR1); 1699 1700 *parity = 'n'; 1701 if (cr & UARTCR1_PE) { 1702 if (cr & UARTCR1_PT) 1703 *parity = 'o'; 1704 else 1705 *parity = 'e'; 1706 } 1707 1708 if (cr & UARTCR1_M) 1709 *bits = 9; 1710 else 1711 *bits = 8; 1712 1713 bdh = readb(sport->port.membase + UARTBDH); 1714 bdh &= UARTBDH_SBR_MASK; 1715 bdl = readb(sport->port.membase + UARTBDL); 1716 sbr = bdh; 1717 sbr <<= 8; 1718 sbr |= bdl; 1719 brfa = readb(sport->port.membase + UARTCR4); 1720 brfa &= UARTCR4_BRFA_MASK; 1721 1722 uartclk = clk_get_rate(sport->clk); 1723 /* 1724 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 1725 */ 1726 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 1727 1728 if (*baud != baud_raw) 1729 printk(KERN_INFO "Serial: Console lpuart rounded baud rate" 1730 "from %d to %d\n", baud_raw, *baud); 1731 } 1732 1733 static void __init 1734 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 1735 int *parity, int *bits) 1736 { 1737 unsigned long cr, bd; 1738 unsigned int sbr, uartclk, baud_raw; 1739 1740 cr = lpuart32_read(sport->port.membase + UARTCTRL); 1741 cr &= UARTCTRL_TE | UARTCTRL_RE; 1742 if (!cr) 1743 return; 1744 1745 /* ok, the port was enabled */ 1746 1747 cr = lpuart32_read(sport->port.membase + UARTCTRL); 1748 1749 *parity = 'n'; 1750 if (cr & UARTCTRL_PE) { 1751 if (cr & UARTCTRL_PT) 1752 *parity = 'o'; 1753 else 1754 *parity = 'e'; 1755 } 1756 1757 if (cr & UARTCTRL_M) 1758 *bits = 9; 1759 else 1760 *bits = 8; 1761 1762 bd = lpuart32_read(sport->port.membase + UARTBAUD); 1763 bd &= UARTBAUD_SBR_MASK; 1764 sbr = bd; 1765 uartclk = clk_get_rate(sport->clk); 1766 /* 1767 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 1768 */ 1769 baud_raw = uartclk / (16 * sbr); 1770 1771 if (*baud != baud_raw) 1772 printk(KERN_INFO "Serial: Console lpuart rounded baud rate" 1773 "from %d to %d\n", baud_raw, *baud); 1774 } 1775 1776 static int __init lpuart_console_setup(struct console *co, char *options) 1777 { 1778 struct lpuart_port *sport; 1779 int baud = 115200; 1780 int bits = 8; 1781 int parity = 'n'; 1782 int flow = 'n'; 1783 1784 /* 1785 * check whether an invalid uart number has been specified, and 1786 * if so, search for the first available port that does have 1787 * console support. 1788 */ 1789 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 1790 co->index = 0; 1791 1792 sport = lpuart_ports[co->index]; 1793 if (sport == NULL) 1794 return -ENODEV; 1795 1796 if (options) 1797 uart_parse_options(options, &baud, &parity, &bits, &flow); 1798 else 1799 if (sport->lpuart32) 1800 lpuart32_console_get_options(sport, &baud, &parity, &bits); 1801 else 1802 lpuart_console_get_options(sport, &baud, &parity, &bits); 1803 1804 if (sport->lpuart32) 1805 lpuart32_setup_watermark(sport); 1806 else 1807 lpuart_setup_watermark(sport); 1808 1809 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 1810 } 1811 1812 static struct uart_driver lpuart_reg; 1813 static struct console lpuart_console = { 1814 .name = DEV_NAME, 1815 .write = lpuart_console_write, 1816 .device = uart_console_device, 1817 .setup = lpuart_console_setup, 1818 .flags = CON_PRINTBUFFER, 1819 .index = -1, 1820 .data = &lpuart_reg, 1821 }; 1822 1823 static struct console lpuart32_console = { 1824 .name = DEV_NAME, 1825 .write = lpuart32_console_write, 1826 .device = uart_console_device, 1827 .setup = lpuart_console_setup, 1828 .flags = CON_PRINTBUFFER, 1829 .index = -1, 1830 .data = &lpuart_reg, 1831 }; 1832 1833 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 1834 { 1835 struct earlycon_device *dev = con->data; 1836 1837 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 1838 } 1839 1840 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 1841 { 1842 struct earlycon_device *dev = con->data; 1843 1844 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 1845 } 1846 1847 static int __init lpuart_early_console_setup(struct earlycon_device *device, 1848 const char *opt) 1849 { 1850 if (!device->port.membase) 1851 return -ENODEV; 1852 1853 device->con->write = lpuart_early_write; 1854 return 0; 1855 } 1856 1857 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 1858 const char *opt) 1859 { 1860 if (!device->port.membase) 1861 return -ENODEV; 1862 1863 device->con->write = lpuart32_early_write; 1864 return 0; 1865 } 1866 1867 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 1868 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 1869 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 1870 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 1871 1872 #define LPUART_CONSOLE (&lpuart_console) 1873 #define LPUART32_CONSOLE (&lpuart32_console) 1874 #else 1875 #define LPUART_CONSOLE NULL 1876 #define LPUART32_CONSOLE NULL 1877 #endif 1878 1879 static struct uart_driver lpuart_reg = { 1880 .owner = THIS_MODULE, 1881 .driver_name = DRIVER_NAME, 1882 .dev_name = DEV_NAME, 1883 .nr = ARRAY_SIZE(lpuart_ports), 1884 .cons = LPUART_CONSOLE, 1885 }; 1886 1887 static int lpuart_probe(struct platform_device *pdev) 1888 { 1889 struct device_node *np = pdev->dev.of_node; 1890 struct lpuart_port *sport; 1891 struct resource *res; 1892 int ret; 1893 1894 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1895 if (!sport) 1896 return -ENOMEM; 1897 1898 pdev->dev.coherent_dma_mask = 0; 1899 1900 ret = of_alias_get_id(np, "serial"); 1901 if (ret < 0) { 1902 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1903 return ret; 1904 } 1905 sport->port.line = ret; 1906 sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart"); 1907 1908 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1909 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 1910 if (IS_ERR(sport->port.membase)) 1911 return PTR_ERR(sport->port.membase); 1912 1913 sport->port.mapbase = res->start; 1914 sport->port.dev = &pdev->dev; 1915 sport->port.type = PORT_LPUART; 1916 sport->port.iotype = UPIO_MEM; 1917 ret = platform_get_irq(pdev, 0); 1918 if (ret < 0) { 1919 dev_err(&pdev->dev, "cannot obtain irq\n"); 1920 return ret; 1921 } 1922 sport->port.irq = ret; 1923 1924 if (sport->lpuart32) 1925 sport->port.ops = &lpuart32_pops; 1926 else 1927 sport->port.ops = &lpuart_pops; 1928 sport->port.flags = UPF_BOOT_AUTOCONF; 1929 1930 sport->port.rs485_config = lpuart_config_rs485; 1931 1932 sport->clk = devm_clk_get(&pdev->dev, "ipg"); 1933 if (IS_ERR(sport->clk)) { 1934 ret = PTR_ERR(sport->clk); 1935 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret); 1936 return ret; 1937 } 1938 1939 ret = clk_prepare_enable(sport->clk); 1940 if (ret) { 1941 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret); 1942 return ret; 1943 } 1944 1945 sport->port.uartclk = clk_get_rate(sport->clk); 1946 1947 lpuart_ports[sport->port.line] = sport; 1948 1949 platform_set_drvdata(pdev, &sport->port); 1950 1951 if (sport->lpuart32) 1952 lpuart_reg.cons = LPUART32_CONSOLE; 1953 else 1954 lpuart_reg.cons = LPUART_CONSOLE; 1955 1956 ret = uart_add_one_port(&lpuart_reg, &sport->port); 1957 if (ret) { 1958 clk_disable_unprepare(sport->clk); 1959 return ret; 1960 } 1961 1962 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx"); 1963 if (!sport->dma_tx_chan) 1964 dev_info(sport->port.dev, "DMA tx channel request failed, " 1965 "operating without tx DMA\n"); 1966 1967 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx"); 1968 if (!sport->dma_rx_chan) 1969 dev_info(sport->port.dev, "DMA rx channel request failed, " 1970 "operating without rx DMA\n"); 1971 1972 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) { 1973 sport->port.rs485.flags |= SER_RS485_ENABLED; 1974 sport->port.rs485.flags |= SER_RS485_RTS_ON_SEND; 1975 writeb(UARTMODEM_TXRTSE, sport->port.membase + UARTMODEM); 1976 } 1977 1978 return 0; 1979 } 1980 1981 static int lpuart_remove(struct platform_device *pdev) 1982 { 1983 struct lpuart_port *sport = platform_get_drvdata(pdev); 1984 1985 uart_remove_one_port(&lpuart_reg, &sport->port); 1986 1987 clk_disable_unprepare(sport->clk); 1988 1989 if (sport->dma_tx_chan) 1990 dma_release_channel(sport->dma_tx_chan); 1991 1992 if (sport->dma_rx_chan) 1993 dma_release_channel(sport->dma_rx_chan); 1994 1995 return 0; 1996 } 1997 1998 #ifdef CONFIG_PM_SLEEP 1999 static int lpuart_suspend(struct device *dev) 2000 { 2001 struct lpuart_port *sport = dev_get_drvdata(dev); 2002 unsigned long temp; 2003 2004 if (sport->lpuart32) { 2005 /* disable Rx/Tx and interrupts */ 2006 temp = lpuart32_read(sport->port.membase + UARTCTRL); 2007 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2008 lpuart32_write(temp, sport->port.membase + UARTCTRL); 2009 } else { 2010 /* disable Rx/Tx and interrupts */ 2011 temp = readb(sport->port.membase + UARTCR2); 2012 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2013 writeb(temp, sport->port.membase + UARTCR2); 2014 } 2015 2016 uart_suspend_port(&lpuart_reg, &sport->port); 2017 2018 if (sport->lpuart_dma_rx_use) { 2019 /* 2020 * EDMA driver during suspend will forcefully release any 2021 * non-idle DMA channels. If port wakeup is enabled or if port 2022 * is console port or 'no_console_suspend' is set the Rx DMA 2023 * cannot resume as as expected, hence gracefully release the 2024 * Rx DMA path before suspend and start Rx DMA path on resume. 2025 */ 2026 if (sport->port.irq_wake) { 2027 del_timer_sync(&sport->lpuart_timer); 2028 lpuart_dma_rx_free(&sport->port); 2029 } 2030 2031 /* Disable Rx DMA to use UART port as wakeup source */ 2032 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS, 2033 sport->port.membase + UARTCR5); 2034 } 2035 2036 if (sport->lpuart_dma_tx_use) { 2037 sport->dma_tx_in_progress = false; 2038 dmaengine_terminate_all(sport->dma_tx_chan); 2039 } 2040 2041 if (sport->port.suspended && !sport->port.irq_wake) 2042 clk_disable_unprepare(sport->clk); 2043 2044 return 0; 2045 } 2046 2047 static int lpuart_resume(struct device *dev) 2048 { 2049 struct lpuart_port *sport = dev_get_drvdata(dev); 2050 unsigned long temp; 2051 2052 if (sport->port.suspended && !sport->port.irq_wake) 2053 clk_prepare_enable(sport->clk); 2054 2055 if (sport->lpuart32) { 2056 lpuart32_setup_watermark(sport); 2057 temp = lpuart32_read(sport->port.membase + UARTCTRL); 2058 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | 2059 UARTCTRL_TE | UARTCTRL_ILIE); 2060 lpuart32_write(temp, sport->port.membase + UARTCTRL); 2061 } else { 2062 lpuart_setup_watermark(sport); 2063 temp = readb(sport->port.membase + UARTCR2); 2064 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 2065 writeb(temp, sport->port.membase + UARTCR2); 2066 } 2067 2068 if (sport->lpuart_dma_rx_use) { 2069 if (sport->port.irq_wake) { 2070 if (!lpuart_start_rx_dma(sport)) { 2071 sport->lpuart_dma_rx_use = true; 2072 rx_dma_timer_init(sport); 2073 } else { 2074 sport->lpuart_dma_rx_use = false; 2075 } 2076 } 2077 } 2078 2079 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) { 2080 init_waitqueue_head(&sport->dma_wait); 2081 sport->lpuart_dma_tx_use = true; 2082 writeb(readb(sport->port.membase + UARTCR5) | 2083 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 2084 } else { 2085 sport->lpuart_dma_tx_use = false; 2086 } 2087 2088 uart_resume_port(&lpuart_reg, &sport->port); 2089 2090 return 0; 2091 } 2092 #endif 2093 2094 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2095 2096 static struct platform_driver lpuart_driver = { 2097 .probe = lpuart_probe, 2098 .remove = lpuart_remove, 2099 .driver = { 2100 .name = "fsl-lpuart", 2101 .of_match_table = lpuart_dt_ids, 2102 .pm = &lpuart_pm_ops, 2103 }, 2104 }; 2105 2106 static int __init lpuart_serial_init(void) 2107 { 2108 int ret = uart_register_driver(&lpuart_reg); 2109 2110 if (ret) 2111 return ret; 2112 2113 ret = platform_driver_register(&lpuart_driver); 2114 if (ret) 2115 uart_unregister_driver(&lpuart_reg); 2116 2117 return ret; 2118 } 2119 2120 static void __exit lpuart_serial_exit(void) 2121 { 2122 platform_driver_unregister(&lpuart_driver); 2123 uart_unregister_driver(&lpuart_reg); 2124 } 2125 2126 module_init(lpuart_serial_init); 2127 module_exit(lpuart_serial_exit); 2128 2129 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2130 MODULE_LICENSE("GPL v2"); 2131