1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale lpuart serial port driver 4 * 5 * Copyright 2012-2014 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/console.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/dmapool.h> 14 #include <linux/io.h> 15 #include <linux/irq.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/of_dma.h> 20 #include <linux/serial_core.h> 21 #include <linux/slab.h> 22 #include <linux/tty_flip.h> 23 24 /* All registers are 8-bit width */ 25 #define UARTBDH 0x00 26 #define UARTBDL 0x01 27 #define UARTCR1 0x02 28 #define UARTCR2 0x03 29 #define UARTSR1 0x04 30 #define UARTCR3 0x06 31 #define UARTDR 0x07 32 #define UARTCR4 0x0a 33 #define UARTCR5 0x0b 34 #define UARTMODEM 0x0d 35 #define UARTPFIFO 0x10 36 #define UARTCFIFO 0x11 37 #define UARTSFIFO 0x12 38 #define UARTTWFIFO 0x13 39 #define UARTTCFIFO 0x14 40 #define UARTRWFIFO 0x15 41 42 #define UARTBDH_LBKDIE 0x80 43 #define UARTBDH_RXEDGIE 0x40 44 #define UARTBDH_SBR_MASK 0x1f 45 46 #define UARTCR1_LOOPS 0x80 47 #define UARTCR1_RSRC 0x20 48 #define UARTCR1_M 0x10 49 #define UARTCR1_WAKE 0x08 50 #define UARTCR1_ILT 0x04 51 #define UARTCR1_PE 0x02 52 #define UARTCR1_PT 0x01 53 54 #define UARTCR2_TIE 0x80 55 #define UARTCR2_TCIE 0x40 56 #define UARTCR2_RIE 0x20 57 #define UARTCR2_ILIE 0x10 58 #define UARTCR2_TE 0x08 59 #define UARTCR2_RE 0x04 60 #define UARTCR2_RWU 0x02 61 #define UARTCR2_SBK 0x01 62 63 #define UARTSR1_TDRE 0x80 64 #define UARTSR1_TC 0x40 65 #define UARTSR1_RDRF 0x20 66 #define UARTSR1_IDLE 0x10 67 #define UARTSR1_OR 0x08 68 #define UARTSR1_NF 0x04 69 #define UARTSR1_FE 0x02 70 #define UARTSR1_PE 0x01 71 72 #define UARTCR3_R8 0x80 73 #define UARTCR3_T8 0x40 74 #define UARTCR3_TXDIR 0x20 75 #define UARTCR3_TXINV 0x10 76 #define UARTCR3_ORIE 0x08 77 #define UARTCR3_NEIE 0x04 78 #define UARTCR3_FEIE 0x02 79 #define UARTCR3_PEIE 0x01 80 81 #define UARTCR4_MAEN1 0x80 82 #define UARTCR4_MAEN2 0x40 83 #define UARTCR4_M10 0x20 84 #define UARTCR4_BRFA_MASK 0x1f 85 #define UARTCR4_BRFA_OFF 0 86 87 #define UARTCR5_TDMAS 0x80 88 #define UARTCR5_RDMAS 0x20 89 90 #define UARTMODEM_RXRTSE 0x08 91 #define UARTMODEM_TXRTSPOL 0x04 92 #define UARTMODEM_TXRTSE 0x02 93 #define UARTMODEM_TXCTSE 0x01 94 95 #define UARTPFIFO_TXFE 0x80 96 #define UARTPFIFO_FIFOSIZE_MASK 0x7 97 #define UARTPFIFO_TXSIZE_OFF 4 98 #define UARTPFIFO_RXFE 0x08 99 #define UARTPFIFO_RXSIZE_OFF 0 100 101 #define UARTCFIFO_TXFLUSH 0x80 102 #define UARTCFIFO_RXFLUSH 0x40 103 #define UARTCFIFO_RXOFE 0x04 104 #define UARTCFIFO_TXOFE 0x02 105 #define UARTCFIFO_RXUFE 0x01 106 107 #define UARTSFIFO_TXEMPT 0x80 108 #define UARTSFIFO_RXEMPT 0x40 109 #define UARTSFIFO_RXOF 0x04 110 #define UARTSFIFO_TXOF 0x02 111 #define UARTSFIFO_RXUF 0x01 112 113 /* 32-bit global registers only for i.MX7ULP/i.MX8x 114 * Used to reset all internal logic and registers, except the Global Register. 115 */ 116 #define UART_GLOBAL 0x8 117 118 /* 32-bit register definition */ 119 #define UARTBAUD 0x00 120 #define UARTSTAT 0x04 121 #define UARTCTRL 0x08 122 #define UARTDATA 0x0C 123 #define UARTMATCH 0x10 124 #define UARTMODIR 0x14 125 #define UARTFIFO 0x18 126 #define UARTWATER 0x1c 127 128 #define UARTBAUD_MAEN1 0x80000000 129 #define UARTBAUD_MAEN2 0x40000000 130 #define UARTBAUD_M10 0x20000000 131 #define UARTBAUD_TDMAE 0x00800000 132 #define UARTBAUD_RDMAE 0x00200000 133 #define UARTBAUD_MATCFG 0x00400000 134 #define UARTBAUD_BOTHEDGE 0x00020000 135 #define UARTBAUD_RESYNCDIS 0x00010000 136 #define UARTBAUD_LBKDIE 0x00008000 137 #define UARTBAUD_RXEDGIE 0x00004000 138 #define UARTBAUD_SBNS 0x00002000 139 #define UARTBAUD_SBR 0x00000000 140 #define UARTBAUD_SBR_MASK 0x1fff 141 #define UARTBAUD_OSR_MASK 0x1f 142 #define UARTBAUD_OSR_SHIFT 24 143 144 #define UARTSTAT_LBKDIF 0x80000000 145 #define UARTSTAT_RXEDGIF 0x40000000 146 #define UARTSTAT_MSBF 0x20000000 147 #define UARTSTAT_RXINV 0x10000000 148 #define UARTSTAT_RWUID 0x08000000 149 #define UARTSTAT_BRK13 0x04000000 150 #define UARTSTAT_LBKDE 0x02000000 151 #define UARTSTAT_RAF 0x01000000 152 #define UARTSTAT_TDRE 0x00800000 153 #define UARTSTAT_TC 0x00400000 154 #define UARTSTAT_RDRF 0x00200000 155 #define UARTSTAT_IDLE 0x00100000 156 #define UARTSTAT_OR 0x00080000 157 #define UARTSTAT_NF 0x00040000 158 #define UARTSTAT_FE 0x00020000 159 #define UARTSTAT_PE 0x00010000 160 #define UARTSTAT_MA1F 0x00008000 161 #define UARTSTAT_M21F 0x00004000 162 163 #define UARTCTRL_R8T9 0x80000000 164 #define UARTCTRL_R9T8 0x40000000 165 #define UARTCTRL_TXDIR 0x20000000 166 #define UARTCTRL_TXINV 0x10000000 167 #define UARTCTRL_ORIE 0x08000000 168 #define UARTCTRL_NEIE 0x04000000 169 #define UARTCTRL_FEIE 0x02000000 170 #define UARTCTRL_PEIE 0x01000000 171 #define UARTCTRL_TIE 0x00800000 172 #define UARTCTRL_TCIE 0x00400000 173 #define UARTCTRL_RIE 0x00200000 174 #define UARTCTRL_ILIE 0x00100000 175 #define UARTCTRL_TE 0x00080000 176 #define UARTCTRL_RE 0x00040000 177 #define UARTCTRL_RWU 0x00020000 178 #define UARTCTRL_SBK 0x00010000 179 #define UARTCTRL_MA1IE 0x00008000 180 #define UARTCTRL_MA2IE 0x00004000 181 #define UARTCTRL_IDLECFG 0x00000100 182 #define UARTCTRL_LOOPS 0x00000080 183 #define UARTCTRL_DOZEEN 0x00000040 184 #define UARTCTRL_RSRC 0x00000020 185 #define UARTCTRL_M 0x00000010 186 #define UARTCTRL_WAKE 0x00000008 187 #define UARTCTRL_ILT 0x00000004 188 #define UARTCTRL_PE 0x00000002 189 #define UARTCTRL_PT 0x00000001 190 191 #define UARTDATA_NOISY 0x00008000 192 #define UARTDATA_PARITYE 0x00004000 193 #define UARTDATA_FRETSC 0x00002000 194 #define UARTDATA_RXEMPT 0x00001000 195 #define UARTDATA_IDLINE 0x00000800 196 #define UARTDATA_MASK 0x3ff 197 198 #define UARTMODIR_IREN 0x00020000 199 #define UARTMODIR_TXCTSSRC 0x00000020 200 #define UARTMODIR_TXCTSC 0x00000010 201 #define UARTMODIR_RXRTSE 0x00000008 202 #define UARTMODIR_TXRTSPOL 0x00000004 203 #define UARTMODIR_TXRTSE 0x00000002 204 #define UARTMODIR_TXCTSE 0x00000001 205 206 #define UARTFIFO_TXEMPT 0x00800000 207 #define UARTFIFO_RXEMPT 0x00400000 208 #define UARTFIFO_TXOF 0x00020000 209 #define UARTFIFO_RXUF 0x00010000 210 #define UARTFIFO_TXFLUSH 0x00008000 211 #define UARTFIFO_RXFLUSH 0x00004000 212 #define UARTFIFO_TXOFE 0x00000200 213 #define UARTFIFO_RXUFE 0x00000100 214 #define UARTFIFO_TXFE 0x00000080 215 #define UARTFIFO_FIFOSIZE_MASK 0x7 216 #define UARTFIFO_TXSIZE_OFF 4 217 #define UARTFIFO_RXFE 0x00000008 218 #define UARTFIFO_RXSIZE_OFF 0 219 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0)) 220 221 #define UARTWATER_COUNT_MASK 0xff 222 #define UARTWATER_TXCNT_OFF 8 223 #define UARTWATER_RXCNT_OFF 24 224 #define UARTWATER_WATER_MASK 0xff 225 #define UARTWATER_TXWATER_OFF 0 226 #define UARTWATER_RXWATER_OFF 16 227 228 #define UART_GLOBAL_RST 0x2 229 #define GLOBAL_RST_MIN_US 20 230 #define GLOBAL_RST_MAX_US 40 231 232 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 233 #define DMA_RX_TIMEOUT (10) 234 235 #define DRIVER_NAME "fsl-lpuart" 236 #define DEV_NAME "ttyLP" 237 #define UART_NR 6 238 239 /* IMX lpuart has four extra unused regs located at the beginning */ 240 #define IMX_REG_OFF 0x10 241 242 static DEFINE_IDA(fsl_lpuart_ida); 243 244 enum lpuart_type { 245 VF610_LPUART, 246 LS1021A_LPUART, 247 LS1028A_LPUART, 248 IMX7ULP_LPUART, 249 IMX8QXP_LPUART, 250 IMXRT1050_LPUART, 251 }; 252 253 struct lpuart_port { 254 struct uart_port port; 255 enum lpuart_type devtype; 256 struct clk *ipg_clk; 257 struct clk *baud_clk; 258 unsigned int txfifo_size; 259 unsigned int rxfifo_size; 260 261 bool lpuart_dma_tx_use; 262 bool lpuart_dma_rx_use; 263 struct dma_chan *dma_tx_chan; 264 struct dma_chan *dma_rx_chan; 265 struct dma_async_tx_descriptor *dma_tx_desc; 266 struct dma_async_tx_descriptor *dma_rx_desc; 267 dma_cookie_t dma_tx_cookie; 268 dma_cookie_t dma_rx_cookie; 269 unsigned int dma_tx_bytes; 270 unsigned int dma_rx_bytes; 271 bool dma_tx_in_progress; 272 unsigned int dma_rx_timeout; 273 struct timer_list lpuart_timer; 274 struct scatterlist rx_sgl, tx_sgl[2]; 275 struct circ_buf rx_ring; 276 int rx_dma_rng_buf_len; 277 unsigned int dma_tx_nents; 278 wait_queue_head_t dma_wait; 279 bool id_allocated; 280 }; 281 282 struct lpuart_soc_data { 283 enum lpuart_type devtype; 284 char iotype; 285 u8 reg_off; 286 }; 287 288 static const struct lpuart_soc_data vf_data = { 289 .devtype = VF610_LPUART, 290 .iotype = UPIO_MEM, 291 }; 292 293 static const struct lpuart_soc_data ls1021a_data = { 294 .devtype = LS1021A_LPUART, 295 .iotype = UPIO_MEM32BE, 296 }; 297 298 static const struct lpuart_soc_data ls1028a_data = { 299 .devtype = LS1028A_LPUART, 300 .iotype = UPIO_MEM32, 301 }; 302 303 static struct lpuart_soc_data imx7ulp_data = { 304 .devtype = IMX7ULP_LPUART, 305 .iotype = UPIO_MEM32, 306 .reg_off = IMX_REG_OFF, 307 }; 308 309 static struct lpuart_soc_data imx8qxp_data = { 310 .devtype = IMX8QXP_LPUART, 311 .iotype = UPIO_MEM32, 312 .reg_off = IMX_REG_OFF, 313 }; 314 static struct lpuart_soc_data imxrt1050_data = { 315 .devtype = IMXRT1050_LPUART, 316 .iotype = UPIO_MEM32, 317 .reg_off = IMX_REG_OFF, 318 }; 319 320 static const struct of_device_id lpuart_dt_ids[] = { 321 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 322 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, }, 323 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, }, 324 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, 325 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, 326 { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data}, 327 { /* sentinel */ } 328 }; 329 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 330 331 /* Forward declare this for the dma callbacks*/ 332 static void lpuart_dma_tx_complete(void *arg); 333 334 static inline bool is_layerscape_lpuart(struct lpuart_port *sport) 335 { 336 return (sport->devtype == LS1021A_LPUART || 337 sport->devtype == LS1028A_LPUART); 338 } 339 340 static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport) 341 { 342 return sport->devtype == IMX7ULP_LPUART; 343 } 344 345 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) 346 { 347 return sport->devtype == IMX8QXP_LPUART; 348 } 349 350 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 351 { 352 switch (port->iotype) { 353 case UPIO_MEM32: 354 return readl(port->membase + off); 355 case UPIO_MEM32BE: 356 return ioread32be(port->membase + off); 357 default: 358 return 0; 359 } 360 } 361 362 static inline void lpuart32_write(struct uart_port *port, u32 val, 363 u32 off) 364 { 365 switch (port->iotype) { 366 case UPIO_MEM32: 367 writel(val, port->membase + off); 368 break; 369 case UPIO_MEM32BE: 370 iowrite32be(val, port->membase + off); 371 break; 372 } 373 } 374 375 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) 376 { 377 int ret = 0; 378 379 if (is_en) { 380 ret = clk_prepare_enable(sport->ipg_clk); 381 if (ret) 382 return ret; 383 384 ret = clk_prepare_enable(sport->baud_clk); 385 if (ret) { 386 clk_disable_unprepare(sport->ipg_clk); 387 return ret; 388 } 389 } else { 390 clk_disable_unprepare(sport->baud_clk); 391 clk_disable_unprepare(sport->ipg_clk); 392 } 393 394 return 0; 395 } 396 397 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) 398 { 399 if (is_imx8qxp_lpuart(sport)) 400 return clk_get_rate(sport->baud_clk); 401 402 return clk_get_rate(sport->ipg_clk); 403 } 404 405 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true) 406 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false) 407 408 static int lpuart_global_reset(struct lpuart_port *sport) 409 { 410 struct uart_port *port = &sport->port; 411 void __iomem *global_addr; 412 int ret; 413 414 if (uart_console(port)) 415 return 0; 416 417 ret = clk_prepare_enable(sport->ipg_clk); 418 if (ret) { 419 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret); 420 return ret; 421 } 422 423 if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) { 424 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF; 425 writel(UART_GLOBAL_RST, global_addr); 426 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); 427 writel(0, global_addr); 428 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); 429 } 430 431 clk_disable_unprepare(sport->ipg_clk); 432 return 0; 433 } 434 435 static void lpuart_stop_tx(struct uart_port *port) 436 { 437 unsigned char temp; 438 439 temp = readb(port->membase + UARTCR2); 440 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 441 writeb(temp, port->membase + UARTCR2); 442 } 443 444 static void lpuart32_stop_tx(struct uart_port *port) 445 { 446 unsigned long temp; 447 448 temp = lpuart32_read(port, UARTCTRL); 449 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 450 lpuart32_write(port, temp, UARTCTRL); 451 } 452 453 static void lpuart_stop_rx(struct uart_port *port) 454 { 455 unsigned char temp; 456 457 temp = readb(port->membase + UARTCR2); 458 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 459 } 460 461 static void lpuart32_stop_rx(struct uart_port *port) 462 { 463 unsigned long temp; 464 465 temp = lpuart32_read(port, UARTCTRL); 466 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); 467 } 468 469 static void lpuart_dma_tx(struct lpuart_port *sport) 470 { 471 struct circ_buf *xmit = &sport->port.state->xmit; 472 struct scatterlist *sgl = sport->tx_sgl; 473 struct device *dev = sport->port.dev; 474 struct dma_chan *chan = sport->dma_tx_chan; 475 int ret; 476 477 if (sport->dma_tx_in_progress) 478 return; 479 480 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 481 482 if (xmit->tail < xmit->head || xmit->head == 0) { 483 sport->dma_tx_nents = 1; 484 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 485 } else { 486 sport->dma_tx_nents = 2; 487 sg_init_table(sgl, 2); 488 sg_set_buf(sgl, xmit->buf + xmit->tail, 489 UART_XMIT_SIZE - xmit->tail); 490 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 491 } 492 493 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, 494 DMA_TO_DEVICE); 495 if (!ret) { 496 dev_err(dev, "DMA mapping error for TX.\n"); 497 return; 498 } 499 500 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, 501 ret, DMA_MEM_TO_DEV, 502 DMA_PREP_INTERRUPT); 503 if (!sport->dma_tx_desc) { 504 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 505 DMA_TO_DEVICE); 506 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 507 return; 508 } 509 510 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 511 sport->dma_tx_desc->callback_param = sport; 512 sport->dma_tx_in_progress = true; 513 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 514 dma_async_issue_pending(chan); 515 } 516 517 static bool lpuart_stopped_or_empty(struct uart_port *port) 518 { 519 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); 520 } 521 522 static void lpuart_dma_tx_complete(void *arg) 523 { 524 struct lpuart_port *sport = arg; 525 struct scatterlist *sgl = &sport->tx_sgl[0]; 526 struct circ_buf *xmit = &sport->port.state->xmit; 527 struct dma_chan *chan = sport->dma_tx_chan; 528 unsigned long flags; 529 530 spin_lock_irqsave(&sport->port.lock, flags); 531 if (!sport->dma_tx_in_progress) { 532 spin_unlock_irqrestore(&sport->port.lock, flags); 533 return; 534 } 535 536 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 537 DMA_TO_DEVICE); 538 539 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 540 541 sport->port.icount.tx += sport->dma_tx_bytes; 542 sport->dma_tx_in_progress = false; 543 spin_unlock_irqrestore(&sport->port.lock, flags); 544 545 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 546 uart_write_wakeup(&sport->port); 547 548 if (waitqueue_active(&sport->dma_wait)) { 549 wake_up(&sport->dma_wait); 550 return; 551 } 552 553 spin_lock_irqsave(&sport->port.lock, flags); 554 555 if (!lpuart_stopped_or_empty(&sport->port)) 556 lpuart_dma_tx(sport); 557 558 spin_unlock_irqrestore(&sport->port.lock, flags); 559 } 560 561 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) 562 { 563 switch (sport->port.iotype) { 564 case UPIO_MEM32: 565 return sport->port.mapbase + UARTDATA; 566 case UPIO_MEM32BE: 567 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; 568 } 569 return sport->port.mapbase + UARTDR; 570 } 571 572 static int lpuart_dma_tx_request(struct uart_port *port) 573 { 574 struct lpuart_port *sport = container_of(port, 575 struct lpuart_port, port); 576 struct dma_slave_config dma_tx_sconfig = {}; 577 int ret; 578 579 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); 580 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 581 dma_tx_sconfig.dst_maxburst = 1; 582 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 583 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 584 585 if (ret) { 586 dev_err(sport->port.dev, 587 "DMA slave config failed, err = %d\n", ret); 588 return ret; 589 } 590 591 return 0; 592 } 593 594 static bool lpuart_is_32(struct lpuart_port *sport) 595 { 596 return sport->port.iotype == UPIO_MEM32 || 597 sport->port.iotype == UPIO_MEM32BE; 598 } 599 600 static void lpuart_flush_buffer(struct uart_port *port) 601 { 602 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 603 struct dma_chan *chan = sport->dma_tx_chan; 604 u32 val; 605 606 if (sport->lpuart_dma_tx_use) { 607 if (sport->dma_tx_in_progress) { 608 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], 609 sport->dma_tx_nents, DMA_TO_DEVICE); 610 sport->dma_tx_in_progress = false; 611 } 612 dmaengine_terminate_all(chan); 613 } 614 615 if (lpuart_is_32(sport)) { 616 val = lpuart32_read(&sport->port, UARTFIFO); 617 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 618 lpuart32_write(&sport->port, val, UARTFIFO); 619 } else { 620 val = readb(sport->port.membase + UARTCFIFO); 621 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; 622 writeb(val, sport->port.membase + UARTCFIFO); 623 } 624 } 625 626 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset, 627 u8 bit) 628 { 629 while (!(readb(port->membase + offset) & bit)) 630 cpu_relax(); 631 } 632 633 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset, 634 u32 bit) 635 { 636 while (!(lpuart32_read(port, offset) & bit)) 637 cpu_relax(); 638 } 639 640 #if defined(CONFIG_CONSOLE_POLL) 641 642 static int lpuart_poll_init(struct uart_port *port) 643 { 644 struct lpuart_port *sport = container_of(port, 645 struct lpuart_port, port); 646 unsigned long flags; 647 unsigned char temp; 648 649 sport->port.fifosize = 0; 650 651 spin_lock_irqsave(&sport->port.lock, flags); 652 /* Disable Rx & Tx */ 653 writeb(0, sport->port.membase + UARTCR2); 654 655 temp = readb(sport->port.membase + UARTPFIFO); 656 /* Enable Rx and Tx FIFO */ 657 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 658 sport->port.membase + UARTPFIFO); 659 660 /* flush Tx and Rx FIFO */ 661 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 662 sport->port.membase + UARTCFIFO); 663 664 /* explicitly clear RDRF */ 665 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 666 readb(sport->port.membase + UARTDR); 667 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 668 } 669 670 writeb(0, sport->port.membase + UARTTWFIFO); 671 writeb(1, sport->port.membase + UARTRWFIFO); 672 673 /* Enable Rx and Tx */ 674 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 675 spin_unlock_irqrestore(&sport->port.lock, flags); 676 677 return 0; 678 } 679 680 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 681 { 682 /* drain */ 683 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 684 writeb(c, port->membase + UARTDR); 685 } 686 687 static int lpuart_poll_get_char(struct uart_port *port) 688 { 689 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 690 return NO_POLL_CHAR; 691 692 return readb(port->membase + UARTDR); 693 } 694 695 static int lpuart32_poll_init(struct uart_port *port) 696 { 697 unsigned long flags; 698 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 699 u32 temp; 700 701 sport->port.fifosize = 0; 702 703 spin_lock_irqsave(&sport->port.lock, flags); 704 705 /* Disable Rx & Tx */ 706 lpuart32_write(&sport->port, 0, UARTCTRL); 707 708 temp = lpuart32_read(&sport->port, UARTFIFO); 709 710 /* Enable Rx and Tx FIFO */ 711 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); 712 713 /* flush Tx and Rx FIFO */ 714 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); 715 716 /* explicitly clear RDRF */ 717 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { 718 lpuart32_read(&sport->port, UARTDATA); 719 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); 720 } 721 722 /* Enable Rx and Tx */ 723 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); 724 spin_unlock_irqrestore(&sport->port.lock, flags); 725 726 return 0; 727 } 728 729 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 730 { 731 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 732 lpuart32_write(port, c, UARTDATA); 733 } 734 735 static int lpuart32_poll_get_char(struct uart_port *port) 736 { 737 if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF)) 738 return NO_POLL_CHAR; 739 740 return lpuart32_read(port, UARTDATA); 741 } 742 #endif 743 744 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 745 { 746 struct circ_buf *xmit = &sport->port.state->xmit; 747 748 if (sport->port.x_char) { 749 writeb(sport->port.x_char, sport->port.membase + UARTDR); 750 sport->port.icount.tx++; 751 sport->port.x_char = 0; 752 return; 753 } 754 755 if (lpuart_stopped_or_empty(&sport->port)) { 756 lpuart_stop_tx(&sport->port); 757 return; 758 } 759 760 while (!uart_circ_empty(xmit) && 761 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 762 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 763 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 764 sport->port.icount.tx++; 765 } 766 767 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 768 uart_write_wakeup(&sport->port); 769 770 if (uart_circ_empty(xmit)) 771 lpuart_stop_tx(&sport->port); 772 } 773 774 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 775 { 776 struct circ_buf *xmit = &sport->port.state->xmit; 777 unsigned long txcnt; 778 779 if (sport->port.x_char) { 780 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 781 sport->port.icount.tx++; 782 sport->port.x_char = 0; 783 return; 784 } 785 786 if (lpuart_stopped_or_empty(&sport->port)) { 787 lpuart32_stop_tx(&sport->port); 788 return; 789 } 790 791 txcnt = lpuart32_read(&sport->port, UARTWATER); 792 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 793 txcnt &= UARTWATER_COUNT_MASK; 794 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 795 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); 796 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 797 sport->port.icount.tx++; 798 txcnt = lpuart32_read(&sport->port, UARTWATER); 799 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 800 txcnt &= UARTWATER_COUNT_MASK; 801 } 802 803 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 804 uart_write_wakeup(&sport->port); 805 806 if (uart_circ_empty(xmit)) 807 lpuart32_stop_tx(&sport->port); 808 } 809 810 static void lpuart_start_tx(struct uart_port *port) 811 { 812 struct lpuart_port *sport = container_of(port, 813 struct lpuart_port, port); 814 unsigned char temp; 815 816 temp = readb(port->membase + UARTCR2); 817 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 818 819 if (sport->lpuart_dma_tx_use) { 820 if (!lpuart_stopped_or_empty(port)) 821 lpuart_dma_tx(sport); 822 } else { 823 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 824 lpuart_transmit_buffer(sport); 825 } 826 } 827 828 static void lpuart32_start_tx(struct uart_port *port) 829 { 830 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 831 unsigned long temp; 832 833 if (sport->lpuart_dma_tx_use) { 834 if (!lpuart_stopped_or_empty(port)) 835 lpuart_dma_tx(sport); 836 } else { 837 temp = lpuart32_read(port, UARTCTRL); 838 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); 839 840 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 841 lpuart32_transmit_buffer(sport); 842 } 843 } 844 845 /* return TIOCSER_TEMT when transmitter is not busy */ 846 static unsigned int lpuart_tx_empty(struct uart_port *port) 847 { 848 struct lpuart_port *sport = container_of(port, 849 struct lpuart_port, port); 850 unsigned char sr1 = readb(port->membase + UARTSR1); 851 unsigned char sfifo = readb(port->membase + UARTSFIFO); 852 853 if (sport->dma_tx_in_progress) 854 return 0; 855 856 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 857 return TIOCSER_TEMT; 858 859 return 0; 860 } 861 862 static unsigned int lpuart32_tx_empty(struct uart_port *port) 863 { 864 struct lpuart_port *sport = container_of(port, 865 struct lpuart_port, port); 866 unsigned long stat = lpuart32_read(port, UARTSTAT); 867 unsigned long sfifo = lpuart32_read(port, UARTFIFO); 868 869 if (sport->dma_tx_in_progress) 870 return 0; 871 872 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) 873 return TIOCSER_TEMT; 874 875 return 0; 876 } 877 878 static void lpuart_txint(struct lpuart_port *sport) 879 { 880 spin_lock(&sport->port.lock); 881 lpuart_transmit_buffer(sport); 882 spin_unlock(&sport->port.lock); 883 } 884 885 static void lpuart_rxint(struct lpuart_port *sport) 886 { 887 unsigned int flg, ignored = 0, overrun = 0; 888 struct tty_port *port = &sport->port.state->port; 889 unsigned char rx, sr; 890 891 spin_lock(&sport->port.lock); 892 893 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 894 flg = TTY_NORMAL; 895 sport->port.icount.rx++; 896 /* 897 * to clear the FE, OR, NF, FE, PE flags, 898 * read SR1 then read DR 899 */ 900 sr = readb(sport->port.membase + UARTSR1); 901 rx = readb(sport->port.membase + UARTDR); 902 903 if (uart_prepare_sysrq_char(&sport->port, rx)) 904 continue; 905 906 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 907 if (sr & UARTSR1_PE) 908 sport->port.icount.parity++; 909 else if (sr & UARTSR1_FE) 910 sport->port.icount.frame++; 911 912 if (sr & UARTSR1_OR) 913 overrun++; 914 915 if (sr & sport->port.ignore_status_mask) { 916 if (++ignored > 100) 917 goto out; 918 continue; 919 } 920 921 sr &= sport->port.read_status_mask; 922 923 if (sr & UARTSR1_PE) 924 flg = TTY_PARITY; 925 else if (sr & UARTSR1_FE) 926 flg = TTY_FRAME; 927 928 if (sr & UARTSR1_OR) 929 flg = TTY_OVERRUN; 930 931 sport->port.sysrq = 0; 932 } 933 934 if (tty_insert_flip_char(port, rx, flg) == 0) 935 sport->port.icount.buf_overrun++; 936 } 937 938 out: 939 if (overrun) { 940 sport->port.icount.overrun += overrun; 941 942 /* 943 * Overruns cause FIFO pointers to become missaligned. 944 * Flushing the receive FIFO reinitializes the pointers. 945 */ 946 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 947 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); 948 } 949 950 uart_unlock_and_check_sysrq(&sport->port); 951 952 tty_flip_buffer_push(port); 953 } 954 955 static void lpuart32_txint(struct lpuart_port *sport) 956 { 957 spin_lock(&sport->port.lock); 958 lpuart32_transmit_buffer(sport); 959 spin_unlock(&sport->port.lock); 960 } 961 962 static void lpuart32_rxint(struct lpuart_port *sport) 963 { 964 unsigned int flg, ignored = 0; 965 struct tty_port *port = &sport->port.state->port; 966 unsigned long rx, sr; 967 bool is_break; 968 969 spin_lock(&sport->port.lock); 970 971 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 972 flg = TTY_NORMAL; 973 sport->port.icount.rx++; 974 /* 975 * to clear the FE, OR, NF, FE, PE flags, 976 * read STAT then read DATA reg 977 */ 978 sr = lpuart32_read(&sport->port, UARTSTAT); 979 rx = lpuart32_read(&sport->port, UARTDATA); 980 rx &= UARTDATA_MASK; 981 982 /* 983 * The LPUART can't distinguish between a break and a framing error, 984 * thus we assume it is a break if the received data is zero. 985 */ 986 is_break = (sr & UARTSTAT_FE) && !rx; 987 988 if (is_break && uart_handle_break(&sport->port)) 989 continue; 990 991 if (uart_prepare_sysrq_char(&sport->port, rx)) 992 continue; 993 994 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 995 if (sr & UARTSTAT_PE) { 996 if (is_break) 997 sport->port.icount.brk++; 998 else 999 sport->port.icount.parity++; 1000 } else if (sr & UARTSTAT_FE) { 1001 sport->port.icount.frame++; 1002 } 1003 1004 if (sr & UARTSTAT_OR) 1005 sport->port.icount.overrun++; 1006 1007 if (sr & sport->port.ignore_status_mask) { 1008 if (++ignored > 100) 1009 goto out; 1010 continue; 1011 } 1012 1013 sr &= sport->port.read_status_mask; 1014 1015 if (sr & UARTSTAT_PE) { 1016 if (is_break) 1017 flg = TTY_BREAK; 1018 else 1019 flg = TTY_PARITY; 1020 } else if (sr & UARTSTAT_FE) { 1021 flg = TTY_FRAME; 1022 } 1023 1024 if (sr & UARTSTAT_OR) 1025 flg = TTY_OVERRUN; 1026 } 1027 1028 if (tty_insert_flip_char(port, rx, flg) == 0) 1029 sport->port.icount.buf_overrun++; 1030 } 1031 1032 out: 1033 uart_unlock_and_check_sysrq(&sport->port); 1034 1035 tty_flip_buffer_push(port); 1036 } 1037 1038 static irqreturn_t lpuart_int(int irq, void *dev_id) 1039 { 1040 struct lpuart_port *sport = dev_id; 1041 unsigned char sts; 1042 1043 sts = readb(sport->port.membase + UARTSR1); 1044 1045 /* SysRq, using dma, check for linebreak by framing err. */ 1046 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { 1047 readb(sport->port.membase + UARTDR); 1048 uart_handle_break(&sport->port); 1049 /* linebreak produces some garbage, removing it */ 1050 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 1051 return IRQ_HANDLED; 1052 } 1053 1054 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) 1055 lpuart_rxint(sport); 1056 1057 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) 1058 lpuart_txint(sport); 1059 1060 return IRQ_HANDLED; 1061 } 1062 1063 static irqreturn_t lpuart32_int(int irq, void *dev_id) 1064 { 1065 struct lpuart_port *sport = dev_id; 1066 unsigned long sts, rxcount; 1067 1068 sts = lpuart32_read(&sport->port, UARTSTAT); 1069 rxcount = lpuart32_read(&sport->port, UARTWATER); 1070 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 1071 1072 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) 1073 lpuart32_rxint(sport); 1074 1075 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) 1076 lpuart32_txint(sport); 1077 1078 lpuart32_write(&sport->port, sts, UARTSTAT); 1079 return IRQ_HANDLED; 1080 } 1081 1082 1083 static inline void lpuart_handle_sysrq_chars(struct uart_port *port, 1084 unsigned char *p, int count) 1085 { 1086 while (count--) { 1087 if (*p && uart_handle_sysrq_char(port, *p)) 1088 return; 1089 p++; 1090 } 1091 } 1092 1093 static void lpuart_handle_sysrq(struct lpuart_port *sport) 1094 { 1095 struct circ_buf *ring = &sport->rx_ring; 1096 int count; 1097 1098 if (ring->head < ring->tail) { 1099 count = sport->rx_sgl.length - ring->tail; 1100 lpuart_handle_sysrq_chars(&sport->port, 1101 ring->buf + ring->tail, count); 1102 ring->tail = 0; 1103 } 1104 1105 if (ring->head > ring->tail) { 1106 count = ring->head - ring->tail; 1107 lpuart_handle_sysrq_chars(&sport->port, 1108 ring->buf + ring->tail, count); 1109 ring->tail = ring->head; 1110 } 1111 } 1112 1113 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 1114 { 1115 struct tty_port *port = &sport->port.state->port; 1116 struct dma_tx_state state; 1117 enum dma_status dmastat; 1118 struct dma_chan *chan = sport->dma_rx_chan; 1119 struct circ_buf *ring = &sport->rx_ring; 1120 unsigned long flags; 1121 int count = 0, copied; 1122 1123 if (lpuart_is_32(sport)) { 1124 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); 1125 1126 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { 1127 /* Read DR to clear the error flags */ 1128 lpuart32_read(&sport->port, UARTDATA); 1129 1130 if (sr & UARTSTAT_PE) 1131 sport->port.icount.parity++; 1132 else if (sr & UARTSTAT_FE) 1133 sport->port.icount.frame++; 1134 } 1135 } else { 1136 unsigned char sr = readb(sport->port.membase + UARTSR1); 1137 1138 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 1139 unsigned char cr2; 1140 1141 /* Disable receiver during this operation... */ 1142 cr2 = readb(sport->port.membase + UARTCR2); 1143 cr2 &= ~UARTCR2_RE; 1144 writeb(cr2, sport->port.membase + UARTCR2); 1145 1146 /* Read DR to clear the error flags */ 1147 readb(sport->port.membase + UARTDR); 1148 1149 if (sr & UARTSR1_PE) 1150 sport->port.icount.parity++; 1151 else if (sr & UARTSR1_FE) 1152 sport->port.icount.frame++; 1153 /* 1154 * At this point parity/framing error is 1155 * cleared However, since the DMA already read 1156 * the data register and we had to read it 1157 * again after reading the status register to 1158 * properly clear the flags, the FIFO actually 1159 * underflowed... This requires a clearing of 1160 * the FIFO... 1161 */ 1162 if (readb(sport->port.membase + UARTSFIFO) & 1163 UARTSFIFO_RXUF) { 1164 writeb(UARTSFIFO_RXUF, 1165 sport->port.membase + UARTSFIFO); 1166 writeb(UARTCFIFO_RXFLUSH, 1167 sport->port.membase + UARTCFIFO); 1168 } 1169 1170 cr2 |= UARTCR2_RE; 1171 writeb(cr2, sport->port.membase + UARTCR2); 1172 } 1173 } 1174 1175 async_tx_ack(sport->dma_rx_desc); 1176 1177 spin_lock_irqsave(&sport->port.lock, flags); 1178 1179 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1180 if (dmastat == DMA_ERROR) { 1181 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1182 spin_unlock_irqrestore(&sport->port.lock, flags); 1183 return; 1184 } 1185 1186 /* CPU claims ownership of RX DMA buffer */ 1187 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, 1188 DMA_FROM_DEVICE); 1189 1190 /* 1191 * ring->head points to the end of data already written by the DMA. 1192 * ring->tail points to the beginning of data to be read by the 1193 * framework. 1194 * The current transfer size should not be larger than the dma buffer 1195 * length. 1196 */ 1197 ring->head = sport->rx_sgl.length - state.residue; 1198 BUG_ON(ring->head > sport->rx_sgl.length); 1199 1200 /* 1201 * Silent handling of keys pressed in the sysrq timeframe 1202 */ 1203 if (sport->port.sysrq) { 1204 lpuart_handle_sysrq(sport); 1205 goto exit; 1206 } 1207 1208 /* 1209 * At this point ring->head may point to the first byte right after the 1210 * last byte of the dma buffer: 1211 * 0 <= ring->head <= sport->rx_sgl.length 1212 * 1213 * However ring->tail must always points inside the dma buffer: 1214 * 0 <= ring->tail <= sport->rx_sgl.length - 1 1215 * 1216 * Since we use a ring buffer, we have to handle the case 1217 * where head is lower than tail. In such a case, we first read from 1218 * tail to the end of the buffer then reset tail. 1219 */ 1220 if (ring->head < ring->tail) { 1221 count = sport->rx_sgl.length - ring->tail; 1222 1223 copied = tty_insert_flip_string(port, ring->buf + ring->tail, count); 1224 if (copied != count) 1225 sport->port.icount.buf_overrun++; 1226 ring->tail = 0; 1227 sport->port.icount.rx += copied; 1228 } 1229 1230 /* Finally we read data from tail to head */ 1231 if (ring->tail < ring->head) { 1232 count = ring->head - ring->tail; 1233 copied = tty_insert_flip_string(port, ring->buf + ring->tail, count); 1234 if (copied != count) 1235 sport->port.icount.buf_overrun++; 1236 /* Wrap ring->head if needed */ 1237 if (ring->head >= sport->rx_sgl.length) 1238 ring->head = 0; 1239 ring->tail = ring->head; 1240 sport->port.icount.rx += copied; 1241 } 1242 1243 exit: 1244 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, 1245 DMA_FROM_DEVICE); 1246 1247 spin_unlock_irqrestore(&sport->port.lock, flags); 1248 1249 tty_flip_buffer_push(port); 1250 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 1251 } 1252 1253 static void lpuart_dma_rx_complete(void *arg) 1254 { 1255 struct lpuart_port *sport = arg; 1256 1257 lpuart_copy_rx_to_tty(sport); 1258 } 1259 1260 static void lpuart_timer_func(struct timer_list *t) 1261 { 1262 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); 1263 1264 lpuart_copy_rx_to_tty(sport); 1265 } 1266 1267 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 1268 { 1269 struct dma_slave_config dma_rx_sconfig = {}; 1270 struct circ_buf *ring = &sport->rx_ring; 1271 int ret, nent; 1272 int bits, baud; 1273 struct tty_port *port = &sport->port.state->port; 1274 struct tty_struct *tty = port->tty; 1275 struct ktermios *termios = &tty->termios; 1276 struct dma_chan *chan = sport->dma_rx_chan; 1277 1278 baud = tty_get_baud_rate(tty); 1279 1280 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; 1281 if (termios->c_cflag & PARENB) 1282 bits++; 1283 1284 /* 1285 * Calculate length of one DMA buffer size to keep latency below 1286 * 10ms at any baud rate. 1287 */ 1288 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 1289 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 1290 if (sport->rx_dma_rng_buf_len < 16) 1291 sport->rx_dma_rng_buf_len = 16; 1292 1293 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1294 if (!ring->buf) 1295 return -ENOMEM; 1296 1297 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1298 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, 1299 DMA_FROM_DEVICE); 1300 1301 if (!nent) { 1302 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1303 return -EINVAL; 1304 } 1305 1306 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); 1307 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1308 dma_rx_sconfig.src_maxburst = 1; 1309 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1310 ret = dmaengine_slave_config(chan, &dma_rx_sconfig); 1311 1312 if (ret < 0) { 1313 dev_err(sport->port.dev, 1314 "DMA Rx slave config failed, err = %d\n", ret); 1315 return ret; 1316 } 1317 1318 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, 1319 sg_dma_address(&sport->rx_sgl), 1320 sport->rx_sgl.length, 1321 sport->rx_sgl.length / 2, 1322 DMA_DEV_TO_MEM, 1323 DMA_PREP_INTERRUPT); 1324 if (!sport->dma_rx_desc) { 1325 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1326 return -EFAULT; 1327 } 1328 1329 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1330 sport->dma_rx_desc->callback_param = sport; 1331 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1332 dma_async_issue_pending(chan); 1333 1334 if (lpuart_is_32(sport)) { 1335 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); 1336 1337 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); 1338 } else { 1339 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1340 sport->port.membase + UARTCR5); 1341 } 1342 1343 return 0; 1344 } 1345 1346 static void lpuart_dma_rx_free(struct uart_port *port) 1347 { 1348 struct lpuart_port *sport = container_of(port, 1349 struct lpuart_port, port); 1350 struct dma_chan *chan = sport->dma_rx_chan; 1351 1352 dmaengine_terminate_all(chan); 1353 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1354 kfree(sport->rx_ring.buf); 1355 sport->rx_ring.tail = 0; 1356 sport->rx_ring.head = 0; 1357 sport->dma_rx_desc = NULL; 1358 sport->dma_rx_cookie = -EINVAL; 1359 } 1360 1361 static int lpuart_config_rs485(struct uart_port *port, 1362 struct serial_rs485 *rs485) 1363 { 1364 struct lpuart_port *sport = container_of(port, 1365 struct lpuart_port, port); 1366 1367 u8 modem = readb(sport->port.membase + UARTMODEM) & 1368 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1369 writeb(modem, sport->port.membase + UARTMODEM); 1370 1371 /* clear unsupported configurations */ 1372 rs485->delay_rts_before_send = 0; 1373 rs485->delay_rts_after_send = 0; 1374 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1375 1376 if (rs485->flags & SER_RS485_ENABLED) { 1377 /* Enable auto RS-485 RTS mode */ 1378 modem |= UARTMODEM_TXRTSE; 1379 1380 /* 1381 * RTS needs to be logic HIGH either during transfer _or_ after 1382 * transfer, other variants are not supported by the hardware. 1383 */ 1384 1385 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1386 SER_RS485_RTS_AFTER_SEND))) 1387 rs485->flags |= SER_RS485_RTS_ON_SEND; 1388 1389 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1390 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1391 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1392 1393 /* 1394 * The hardware defaults to RTS logic HIGH while transfer. 1395 * Switch polarity in case RTS shall be logic HIGH 1396 * after transfer. 1397 * Note: UART is assumed to be active high. 1398 */ 1399 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1400 modem &= ~UARTMODEM_TXRTSPOL; 1401 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1402 modem |= UARTMODEM_TXRTSPOL; 1403 } 1404 1405 /* Store the new configuration */ 1406 sport->port.rs485 = *rs485; 1407 1408 writeb(modem, sport->port.membase + UARTMODEM); 1409 return 0; 1410 } 1411 1412 static int lpuart32_config_rs485(struct uart_port *port, 1413 struct serial_rs485 *rs485) 1414 { 1415 struct lpuart_port *sport = container_of(port, 1416 struct lpuart_port, port); 1417 1418 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) 1419 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1420 lpuart32_write(&sport->port, modem, UARTMODIR); 1421 1422 /* clear unsupported configurations */ 1423 rs485->delay_rts_before_send = 0; 1424 rs485->delay_rts_after_send = 0; 1425 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1426 1427 if (rs485->flags & SER_RS485_ENABLED) { 1428 /* Enable auto RS-485 RTS mode */ 1429 modem |= UARTMODEM_TXRTSE; 1430 1431 /* 1432 * RTS needs to be logic HIGH either during transfer _or_ after 1433 * transfer, other variants are not supported by the hardware. 1434 */ 1435 1436 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1437 SER_RS485_RTS_AFTER_SEND))) 1438 rs485->flags |= SER_RS485_RTS_ON_SEND; 1439 1440 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1441 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1442 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1443 1444 /* 1445 * The hardware defaults to RTS logic HIGH while transfer. 1446 * Switch polarity in case RTS shall be logic HIGH 1447 * after transfer. 1448 * Note: UART is assumed to be active high. 1449 */ 1450 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1451 modem &= ~UARTMODEM_TXRTSPOL; 1452 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1453 modem |= UARTMODEM_TXRTSPOL; 1454 } 1455 1456 /* Store the new configuration */ 1457 sport->port.rs485 = *rs485; 1458 1459 lpuart32_write(&sport->port, modem, UARTMODIR); 1460 return 0; 1461 } 1462 1463 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1464 { 1465 unsigned int mctrl = 0; 1466 u8 reg; 1467 1468 reg = readb(port->membase + UARTCR1); 1469 if (reg & UARTCR1_LOOPS) 1470 mctrl |= TIOCM_LOOP; 1471 1472 return mctrl; 1473 } 1474 1475 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1476 { 1477 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 1478 u32 reg; 1479 1480 reg = lpuart32_read(port, UARTCTRL); 1481 if (reg & UARTCTRL_LOOPS) 1482 mctrl |= TIOCM_LOOP; 1483 1484 return mctrl; 1485 } 1486 1487 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1488 { 1489 u8 reg; 1490 1491 reg = readb(port->membase + UARTCR1); 1492 1493 /* for internal loopback we need LOOPS=1 and RSRC=0 */ 1494 reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC); 1495 if (mctrl & TIOCM_LOOP) 1496 reg |= UARTCR1_LOOPS; 1497 1498 writeb(reg, port->membase + UARTCR1); 1499 } 1500 1501 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1502 { 1503 u32 reg; 1504 1505 reg = lpuart32_read(port, UARTCTRL); 1506 1507 /* for internal loopback we need LOOPS=1 and RSRC=0 */ 1508 reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC); 1509 if (mctrl & TIOCM_LOOP) 1510 reg |= UARTCTRL_LOOPS; 1511 1512 lpuart32_write(port, reg, UARTCTRL); 1513 } 1514 1515 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1516 { 1517 unsigned char temp; 1518 1519 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1520 1521 if (break_state != 0) 1522 temp |= UARTCR2_SBK; 1523 1524 writeb(temp, port->membase + UARTCR2); 1525 } 1526 1527 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1528 { 1529 unsigned long temp; 1530 1531 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; 1532 1533 if (break_state != 0) 1534 temp |= UARTCTRL_SBK; 1535 1536 lpuart32_write(port, temp, UARTCTRL); 1537 } 1538 1539 static void lpuart_setup_watermark(struct lpuart_port *sport) 1540 { 1541 unsigned char val, cr2; 1542 unsigned char cr2_saved; 1543 1544 cr2 = readb(sport->port.membase + UARTCR2); 1545 cr2_saved = cr2; 1546 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1547 UARTCR2_RIE | UARTCR2_RE); 1548 writeb(cr2, sport->port.membase + UARTCR2); 1549 1550 val = readb(sport->port.membase + UARTPFIFO); 1551 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1552 sport->port.membase + UARTPFIFO); 1553 1554 /* flush Tx and Rx FIFO */ 1555 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1556 sport->port.membase + UARTCFIFO); 1557 1558 /* explicitly clear RDRF */ 1559 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1560 readb(sport->port.membase + UARTDR); 1561 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1562 } 1563 1564 writeb(0, sport->port.membase + UARTTWFIFO); 1565 writeb(1, sport->port.membase + UARTRWFIFO); 1566 1567 /* Restore cr2 */ 1568 writeb(cr2_saved, sport->port.membase + UARTCR2); 1569 } 1570 1571 static void lpuart_setup_watermark_enable(struct lpuart_port *sport) 1572 { 1573 unsigned char cr2; 1574 1575 lpuart_setup_watermark(sport); 1576 1577 cr2 = readb(sport->port.membase + UARTCR2); 1578 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE; 1579 writeb(cr2, sport->port.membase + UARTCR2); 1580 } 1581 1582 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1583 { 1584 unsigned long val, ctrl; 1585 unsigned long ctrl_saved; 1586 1587 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1588 ctrl_saved = ctrl; 1589 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1590 UARTCTRL_RIE | UARTCTRL_RE); 1591 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1592 1593 /* enable FIFO mode */ 1594 val = lpuart32_read(&sport->port, UARTFIFO); 1595 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1596 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1597 lpuart32_write(&sport->port, val, UARTFIFO); 1598 1599 /* set the watermark */ 1600 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1601 lpuart32_write(&sport->port, val, UARTWATER); 1602 1603 /* Restore cr2 */ 1604 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1605 } 1606 1607 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) 1608 { 1609 u32 temp; 1610 1611 lpuart32_setup_watermark(sport); 1612 1613 temp = lpuart32_read(&sport->port, UARTCTRL); 1614 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE; 1615 lpuart32_write(&sport->port, temp, UARTCTRL); 1616 } 1617 1618 static void rx_dma_timer_init(struct lpuart_port *sport) 1619 { 1620 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); 1621 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1622 add_timer(&sport->lpuart_timer); 1623 } 1624 1625 static void lpuart_request_dma(struct lpuart_port *sport) 1626 { 1627 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); 1628 if (IS_ERR(sport->dma_tx_chan)) { 1629 dev_dbg_once(sport->port.dev, 1630 "DMA tx channel request failed, operating without tx DMA (%ld)\n", 1631 PTR_ERR(sport->dma_tx_chan)); 1632 sport->dma_tx_chan = NULL; 1633 } 1634 1635 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); 1636 if (IS_ERR(sport->dma_rx_chan)) { 1637 dev_dbg_once(sport->port.dev, 1638 "DMA rx channel request failed, operating without rx DMA (%ld)\n", 1639 PTR_ERR(sport->dma_rx_chan)); 1640 sport->dma_rx_chan = NULL; 1641 } 1642 } 1643 1644 static void lpuart_tx_dma_startup(struct lpuart_port *sport) 1645 { 1646 u32 uartbaud; 1647 int ret; 1648 1649 if (uart_console(&sport->port)) 1650 goto err; 1651 1652 if (!sport->dma_tx_chan) 1653 goto err; 1654 1655 ret = lpuart_dma_tx_request(&sport->port); 1656 if (ret) 1657 goto err; 1658 1659 init_waitqueue_head(&sport->dma_wait); 1660 sport->lpuart_dma_tx_use = true; 1661 if (lpuart_is_32(sport)) { 1662 uartbaud = lpuart32_read(&sport->port, UARTBAUD); 1663 lpuart32_write(&sport->port, 1664 uartbaud | UARTBAUD_TDMAE, UARTBAUD); 1665 } else { 1666 writeb(readb(sport->port.membase + UARTCR5) | 1667 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 1668 } 1669 1670 return; 1671 1672 err: 1673 sport->lpuart_dma_tx_use = false; 1674 } 1675 1676 static void lpuart_rx_dma_startup(struct lpuart_port *sport) 1677 { 1678 int ret; 1679 unsigned char cr3; 1680 1681 if (uart_console(&sport->port)) 1682 goto err; 1683 1684 if (!sport->dma_rx_chan) 1685 goto err; 1686 1687 ret = lpuart_start_rx_dma(sport); 1688 if (ret) 1689 goto err; 1690 1691 /* set Rx DMA timeout */ 1692 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1693 if (!sport->dma_rx_timeout) 1694 sport->dma_rx_timeout = 1; 1695 1696 sport->lpuart_dma_rx_use = true; 1697 rx_dma_timer_init(sport); 1698 1699 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { 1700 cr3 = readb(sport->port.membase + UARTCR3); 1701 cr3 |= UARTCR3_FEIE; 1702 writeb(cr3, sport->port.membase + UARTCR3); 1703 } 1704 1705 return; 1706 1707 err: 1708 sport->lpuart_dma_rx_use = false; 1709 } 1710 1711 static int lpuart_startup(struct uart_port *port) 1712 { 1713 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1714 unsigned long flags; 1715 unsigned char temp; 1716 1717 /* determine FIFO size and enable FIFO mode */ 1718 temp = readb(sport->port.membase + UARTPFIFO); 1719 1720 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & 1721 UARTPFIFO_FIFOSIZE_MASK); 1722 sport->port.fifosize = sport->txfifo_size; 1723 1724 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & 1725 UARTPFIFO_FIFOSIZE_MASK); 1726 1727 lpuart_request_dma(sport); 1728 1729 spin_lock_irqsave(&sport->port.lock, flags); 1730 1731 lpuart_setup_watermark_enable(sport); 1732 1733 lpuart_rx_dma_startup(sport); 1734 lpuart_tx_dma_startup(sport); 1735 1736 spin_unlock_irqrestore(&sport->port.lock, flags); 1737 1738 return 0; 1739 } 1740 1741 static void lpuart32_configure(struct lpuart_port *sport) 1742 { 1743 unsigned long temp; 1744 1745 if (sport->lpuart_dma_rx_use) { 1746 /* RXWATER must be 0 */ 1747 temp = lpuart32_read(&sport->port, UARTWATER); 1748 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF); 1749 lpuart32_write(&sport->port, temp, UARTWATER); 1750 } 1751 temp = lpuart32_read(&sport->port, UARTCTRL); 1752 if (!sport->lpuart_dma_rx_use) 1753 temp |= UARTCTRL_RIE; 1754 if (!sport->lpuart_dma_tx_use) 1755 temp |= UARTCTRL_TIE; 1756 lpuart32_write(&sport->port, temp, UARTCTRL); 1757 } 1758 1759 static int lpuart32_startup(struct uart_port *port) 1760 { 1761 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1762 unsigned long flags; 1763 unsigned long temp; 1764 1765 /* determine FIFO size */ 1766 temp = lpuart32_read(&sport->port, UARTFIFO); 1767 1768 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & 1769 UARTFIFO_FIFOSIZE_MASK); 1770 sport->port.fifosize = sport->txfifo_size; 1771 1772 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & 1773 UARTFIFO_FIFOSIZE_MASK); 1774 1775 /* 1776 * The LS1021A and LS1028A have a fixed FIFO depth of 16 words. 1777 * Although they support the RX/TXSIZE fields, their encoding is 1778 * different. Eg the reference manual states 0b101 is 16 words. 1779 */ 1780 if (is_layerscape_lpuart(sport)) { 1781 sport->rxfifo_size = 16; 1782 sport->txfifo_size = 16; 1783 sport->port.fifosize = sport->txfifo_size; 1784 } 1785 1786 lpuart_request_dma(sport); 1787 1788 spin_lock_irqsave(&sport->port.lock, flags); 1789 1790 lpuart32_setup_watermark_enable(sport); 1791 1792 lpuart_rx_dma_startup(sport); 1793 lpuart_tx_dma_startup(sport); 1794 1795 lpuart32_configure(sport); 1796 1797 spin_unlock_irqrestore(&sport->port.lock, flags); 1798 return 0; 1799 } 1800 1801 static void lpuart_dma_shutdown(struct lpuart_port *sport) 1802 { 1803 if (sport->lpuart_dma_rx_use) { 1804 del_timer_sync(&sport->lpuart_timer); 1805 lpuart_dma_rx_free(&sport->port); 1806 } 1807 1808 if (sport->lpuart_dma_tx_use) { 1809 if (wait_event_interruptible_timeout(sport->dma_wait, 1810 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { 1811 sport->dma_tx_in_progress = false; 1812 dmaengine_terminate_all(sport->dma_tx_chan); 1813 } 1814 } 1815 1816 if (sport->dma_tx_chan) 1817 dma_release_channel(sport->dma_tx_chan); 1818 if (sport->dma_rx_chan) 1819 dma_release_channel(sport->dma_rx_chan); 1820 } 1821 1822 static void lpuart_shutdown(struct uart_port *port) 1823 { 1824 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1825 unsigned char temp; 1826 unsigned long flags; 1827 1828 spin_lock_irqsave(&port->lock, flags); 1829 1830 /* disable Rx/Tx and interrupts */ 1831 temp = readb(port->membase + UARTCR2); 1832 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1833 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1834 writeb(temp, port->membase + UARTCR2); 1835 1836 spin_unlock_irqrestore(&port->lock, flags); 1837 1838 lpuart_dma_shutdown(sport); 1839 } 1840 1841 static void lpuart32_shutdown(struct uart_port *port) 1842 { 1843 struct lpuart_port *sport = 1844 container_of(port, struct lpuart_port, port); 1845 unsigned long temp; 1846 unsigned long flags; 1847 1848 spin_lock_irqsave(&port->lock, flags); 1849 1850 /* disable Rx/Tx and interrupts */ 1851 temp = lpuart32_read(port, UARTCTRL); 1852 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1853 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1854 lpuart32_write(port, temp, UARTCTRL); 1855 1856 spin_unlock_irqrestore(&port->lock, flags); 1857 1858 lpuart_dma_shutdown(sport); 1859 } 1860 1861 static void 1862 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1863 struct ktermios *old) 1864 { 1865 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1866 unsigned long flags; 1867 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1868 unsigned int baud; 1869 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1870 unsigned int sbr, brfa; 1871 1872 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1873 old_cr2 = readb(sport->port.membase + UARTCR2); 1874 cr3 = readb(sport->port.membase + UARTCR3); 1875 cr4 = readb(sport->port.membase + UARTCR4); 1876 bdh = readb(sport->port.membase + UARTBDH); 1877 modem = readb(sport->port.membase + UARTMODEM); 1878 /* 1879 * only support CS8 and CS7, and for CS7 must enable PE. 1880 * supported mode: 1881 * - (7,e/o,1) 1882 * - (8,n,1) 1883 * - (8,m/s,1) 1884 * - (8,e/o,1) 1885 */ 1886 while ((termios->c_cflag & CSIZE) != CS8 && 1887 (termios->c_cflag & CSIZE) != CS7) { 1888 termios->c_cflag &= ~CSIZE; 1889 termios->c_cflag |= old_csize; 1890 old_csize = CS8; 1891 } 1892 1893 if ((termios->c_cflag & CSIZE) == CS8 || 1894 (termios->c_cflag & CSIZE) == CS7) 1895 cr1 = old_cr1 & ~UARTCR1_M; 1896 1897 if (termios->c_cflag & CMSPAR) { 1898 if ((termios->c_cflag & CSIZE) != CS8) { 1899 termios->c_cflag &= ~CSIZE; 1900 termios->c_cflag |= CS8; 1901 } 1902 cr1 |= UARTCR1_M; 1903 } 1904 1905 /* 1906 * When auto RS-485 RTS mode is enabled, 1907 * hardware flow control need to be disabled. 1908 */ 1909 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1910 termios->c_cflag &= ~CRTSCTS; 1911 1912 if (termios->c_cflag & CRTSCTS) 1913 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE; 1914 else 1915 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1916 1917 termios->c_cflag &= ~CSTOPB; 1918 1919 /* parity must be enabled when CS7 to match 8-bits format */ 1920 if ((termios->c_cflag & CSIZE) == CS7) 1921 termios->c_cflag |= PARENB; 1922 1923 if (termios->c_cflag & PARENB) { 1924 if (termios->c_cflag & CMSPAR) { 1925 cr1 &= ~UARTCR1_PE; 1926 if (termios->c_cflag & PARODD) 1927 cr3 |= UARTCR3_T8; 1928 else 1929 cr3 &= ~UARTCR3_T8; 1930 } else { 1931 cr1 |= UARTCR1_PE; 1932 if ((termios->c_cflag & CSIZE) == CS8) 1933 cr1 |= UARTCR1_M; 1934 if (termios->c_cflag & PARODD) 1935 cr1 |= UARTCR1_PT; 1936 else 1937 cr1 &= ~UARTCR1_PT; 1938 } 1939 } else { 1940 cr1 &= ~UARTCR1_PE; 1941 } 1942 1943 /* ask the core to calculate the divisor */ 1944 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1945 1946 /* 1947 * Need to update the Ring buffer length according to the selected 1948 * baud rate and restart Rx DMA path. 1949 * 1950 * Since timer function acqures sport->port.lock, need to stop before 1951 * acquring same lock because otherwise del_timer_sync() can deadlock. 1952 */ 1953 if (old && sport->lpuart_dma_rx_use) { 1954 del_timer_sync(&sport->lpuart_timer); 1955 lpuart_dma_rx_free(&sport->port); 1956 } 1957 1958 spin_lock_irqsave(&sport->port.lock, flags); 1959 1960 sport->port.read_status_mask = 0; 1961 if (termios->c_iflag & INPCK) 1962 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; 1963 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1964 sport->port.read_status_mask |= UARTSR1_FE; 1965 1966 /* characters to ignore */ 1967 sport->port.ignore_status_mask = 0; 1968 if (termios->c_iflag & IGNPAR) 1969 sport->port.ignore_status_mask |= UARTSR1_PE; 1970 if (termios->c_iflag & IGNBRK) { 1971 sport->port.ignore_status_mask |= UARTSR1_FE; 1972 /* 1973 * if we're ignoring parity and break indicators, 1974 * ignore overruns too (for real raw support). 1975 */ 1976 if (termios->c_iflag & IGNPAR) 1977 sport->port.ignore_status_mask |= UARTSR1_OR; 1978 } 1979 1980 /* update the per-port timeout */ 1981 uart_update_timeout(port, termios->c_cflag, baud); 1982 1983 /* wait transmit engin complete */ 1984 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 1985 1986 /* disable transmit and receive */ 1987 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1988 sport->port.membase + UARTCR2); 1989 1990 sbr = sport->port.uartclk / (16 * baud); 1991 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1992 bdh &= ~UARTBDH_SBR_MASK; 1993 bdh |= (sbr >> 8) & 0x1F; 1994 cr4 &= ~UARTCR4_BRFA_MASK; 1995 brfa &= UARTCR4_BRFA_MASK; 1996 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1997 writeb(bdh, sport->port.membase + UARTBDH); 1998 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1999 writeb(cr3, sport->port.membase + UARTCR3); 2000 writeb(cr1, sport->port.membase + UARTCR1); 2001 writeb(modem, sport->port.membase + UARTMODEM); 2002 2003 /* restore control register */ 2004 writeb(old_cr2, sport->port.membase + UARTCR2); 2005 2006 if (old && sport->lpuart_dma_rx_use) { 2007 if (!lpuart_start_rx_dma(sport)) 2008 rx_dma_timer_init(sport); 2009 else 2010 sport->lpuart_dma_rx_use = false; 2011 } 2012 2013 spin_unlock_irqrestore(&sport->port.lock, flags); 2014 } 2015 2016 static void __lpuart32_serial_setbrg(struct uart_port *port, 2017 unsigned int baudrate, bool use_rx_dma, 2018 bool use_tx_dma) 2019 { 2020 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; 2021 u32 clk = port->uartclk; 2022 2023 /* 2024 * The idea is to use the best OSR (over-sampling rate) possible. 2025 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 2026 * Loop to find the best OSR value possible, one that generates minimum 2027 * baud_diff iterate through the rest of the supported values of OSR. 2028 * 2029 * Calculation Formula: 2030 * Baud Rate = baud clock / ((OSR+1) × SBR) 2031 */ 2032 baud_diff = baudrate; 2033 osr = 0; 2034 sbr = 0; 2035 2036 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 2037 /* calculate the temporary sbr value */ 2038 tmp_sbr = (clk / (baudrate * tmp_osr)); 2039 if (tmp_sbr == 0) 2040 tmp_sbr = 1; 2041 2042 /* 2043 * calculate the baud rate difference based on the temporary 2044 * osr and sbr values 2045 */ 2046 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 2047 2048 /* select best values between sbr and sbr+1 */ 2049 tmp = clk / (tmp_osr * (tmp_sbr + 1)); 2050 if (tmp_diff > (baudrate - tmp)) { 2051 tmp_diff = baudrate - tmp; 2052 tmp_sbr++; 2053 } 2054 2055 if (tmp_sbr > UARTBAUD_SBR_MASK) 2056 continue; 2057 2058 if (tmp_diff <= baud_diff) { 2059 baud_diff = tmp_diff; 2060 osr = tmp_osr; 2061 sbr = tmp_sbr; 2062 2063 if (!baud_diff) 2064 break; 2065 } 2066 } 2067 2068 /* handle buadrate outside acceptable rate */ 2069 if (baud_diff > ((baudrate / 100) * 3)) 2070 dev_warn(port->dev, 2071 "unacceptable baud rate difference of more than 3%%\n"); 2072 2073 tmp = lpuart32_read(port, UARTBAUD); 2074 2075 if ((osr > 3) && (osr < 8)) 2076 tmp |= UARTBAUD_BOTHEDGE; 2077 2078 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 2079 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; 2080 2081 tmp &= ~UARTBAUD_SBR_MASK; 2082 tmp |= sbr & UARTBAUD_SBR_MASK; 2083 2084 if (!use_rx_dma) 2085 tmp &= ~UARTBAUD_RDMAE; 2086 if (!use_tx_dma) 2087 tmp &= ~UARTBAUD_TDMAE; 2088 2089 lpuart32_write(port, tmp, UARTBAUD); 2090 } 2091 2092 static void lpuart32_serial_setbrg(struct lpuart_port *sport, 2093 unsigned int baudrate) 2094 { 2095 __lpuart32_serial_setbrg(&sport->port, baudrate, 2096 sport->lpuart_dma_rx_use, 2097 sport->lpuart_dma_tx_use); 2098 } 2099 2100 2101 static void 2102 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 2103 struct ktermios *old) 2104 { 2105 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 2106 unsigned long flags; 2107 unsigned long ctrl, old_ctrl, bd, modem; 2108 unsigned int baud; 2109 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 2110 2111 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); 2112 bd = lpuart32_read(&sport->port, UARTBAUD); 2113 modem = lpuart32_read(&sport->port, UARTMODIR); 2114 /* 2115 * only support CS8 and CS7, and for CS7 must enable PE. 2116 * supported mode: 2117 * - (7,e/o,1) 2118 * - (8,n,1) 2119 * - (8,m/s,1) 2120 * - (8,e/o,1) 2121 */ 2122 while ((termios->c_cflag & CSIZE) != CS8 && 2123 (termios->c_cflag & CSIZE) != CS7) { 2124 termios->c_cflag &= ~CSIZE; 2125 termios->c_cflag |= old_csize; 2126 old_csize = CS8; 2127 } 2128 2129 if ((termios->c_cflag & CSIZE) == CS8 || 2130 (termios->c_cflag & CSIZE) == CS7) 2131 ctrl = old_ctrl & ~UARTCTRL_M; 2132 2133 if (termios->c_cflag & CMSPAR) { 2134 if ((termios->c_cflag & CSIZE) != CS8) { 2135 termios->c_cflag &= ~CSIZE; 2136 termios->c_cflag |= CS8; 2137 } 2138 ctrl |= UARTCTRL_M; 2139 } 2140 2141 /* 2142 * When auto RS-485 RTS mode is enabled, 2143 * hardware flow control need to be disabled. 2144 */ 2145 if (sport->port.rs485.flags & SER_RS485_ENABLED) 2146 termios->c_cflag &= ~CRTSCTS; 2147 2148 if (termios->c_cflag & CRTSCTS) { 2149 modem |= (UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 2150 } else { 2151 termios->c_cflag &= ~CRTSCTS; 2152 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 2153 } 2154 2155 if (termios->c_cflag & CSTOPB) 2156 bd |= UARTBAUD_SBNS; 2157 else 2158 bd &= ~UARTBAUD_SBNS; 2159 2160 /* parity must be enabled when CS7 to match 8-bits format */ 2161 if ((termios->c_cflag & CSIZE) == CS7) 2162 termios->c_cflag |= PARENB; 2163 2164 if ((termios->c_cflag & PARENB)) { 2165 if (termios->c_cflag & CMSPAR) { 2166 ctrl &= ~UARTCTRL_PE; 2167 ctrl |= UARTCTRL_M; 2168 } else { 2169 ctrl |= UARTCTRL_PE; 2170 if ((termios->c_cflag & CSIZE) == CS8) 2171 ctrl |= UARTCTRL_M; 2172 if (termios->c_cflag & PARODD) 2173 ctrl |= UARTCTRL_PT; 2174 else 2175 ctrl &= ~UARTCTRL_PT; 2176 } 2177 } else { 2178 ctrl &= ~UARTCTRL_PE; 2179 } 2180 2181 /* ask the core to calculate the divisor */ 2182 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); 2183 2184 /* 2185 * Need to update the Ring buffer length according to the selected 2186 * baud rate and restart Rx DMA path. 2187 * 2188 * Since timer function acqures sport->port.lock, need to stop before 2189 * acquring same lock because otherwise del_timer_sync() can deadlock. 2190 */ 2191 if (old && sport->lpuart_dma_rx_use) { 2192 del_timer_sync(&sport->lpuart_timer); 2193 lpuart_dma_rx_free(&sport->port); 2194 } 2195 2196 spin_lock_irqsave(&sport->port.lock, flags); 2197 2198 sport->port.read_status_mask = 0; 2199 if (termios->c_iflag & INPCK) 2200 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; 2201 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2202 sport->port.read_status_mask |= UARTSTAT_FE; 2203 2204 /* characters to ignore */ 2205 sport->port.ignore_status_mask = 0; 2206 if (termios->c_iflag & IGNPAR) 2207 sport->port.ignore_status_mask |= UARTSTAT_PE; 2208 if (termios->c_iflag & IGNBRK) { 2209 sport->port.ignore_status_mask |= UARTSTAT_FE; 2210 /* 2211 * if we're ignoring parity and break indicators, 2212 * ignore overruns too (for real raw support). 2213 */ 2214 if (termios->c_iflag & IGNPAR) 2215 sport->port.ignore_status_mask |= UARTSTAT_OR; 2216 } 2217 2218 /* update the per-port timeout */ 2219 uart_update_timeout(port, termios->c_cflag, baud); 2220 2221 /* wait transmit engin complete */ 2222 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2223 2224 /* disable transmit and receive */ 2225 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 2226 UARTCTRL); 2227 2228 lpuart32_write(&sport->port, bd, UARTBAUD); 2229 lpuart32_serial_setbrg(sport, baud); 2230 lpuart32_write(&sport->port, modem, UARTMODIR); 2231 lpuart32_write(&sport->port, ctrl, UARTCTRL); 2232 /* restore control register */ 2233 2234 if (old && sport->lpuart_dma_rx_use) { 2235 if (!lpuart_start_rx_dma(sport)) 2236 rx_dma_timer_init(sport); 2237 else 2238 sport->lpuart_dma_rx_use = false; 2239 } 2240 2241 spin_unlock_irqrestore(&sport->port.lock, flags); 2242 } 2243 2244 static const char *lpuart_type(struct uart_port *port) 2245 { 2246 return "FSL_LPUART"; 2247 } 2248 2249 static void lpuart_release_port(struct uart_port *port) 2250 { 2251 /* nothing to do */ 2252 } 2253 2254 static int lpuart_request_port(struct uart_port *port) 2255 { 2256 return 0; 2257 } 2258 2259 /* configure/autoconfigure the port */ 2260 static void lpuart_config_port(struct uart_port *port, int flags) 2261 { 2262 if (flags & UART_CONFIG_TYPE) 2263 port->type = PORT_LPUART; 2264 } 2265 2266 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 2267 { 2268 int ret = 0; 2269 2270 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 2271 ret = -EINVAL; 2272 if (port->irq != ser->irq) 2273 ret = -EINVAL; 2274 if (ser->io_type != UPIO_MEM) 2275 ret = -EINVAL; 2276 if (port->uartclk / 16 != ser->baud_base) 2277 ret = -EINVAL; 2278 if (port->iobase != ser->port) 2279 ret = -EINVAL; 2280 if (ser->hub6 != 0) 2281 ret = -EINVAL; 2282 return ret; 2283 } 2284 2285 static const struct uart_ops lpuart_pops = { 2286 .tx_empty = lpuart_tx_empty, 2287 .set_mctrl = lpuart_set_mctrl, 2288 .get_mctrl = lpuart_get_mctrl, 2289 .stop_tx = lpuart_stop_tx, 2290 .start_tx = lpuart_start_tx, 2291 .stop_rx = lpuart_stop_rx, 2292 .break_ctl = lpuart_break_ctl, 2293 .startup = lpuart_startup, 2294 .shutdown = lpuart_shutdown, 2295 .set_termios = lpuart_set_termios, 2296 .type = lpuart_type, 2297 .request_port = lpuart_request_port, 2298 .release_port = lpuart_release_port, 2299 .config_port = lpuart_config_port, 2300 .verify_port = lpuart_verify_port, 2301 .flush_buffer = lpuart_flush_buffer, 2302 #if defined(CONFIG_CONSOLE_POLL) 2303 .poll_init = lpuart_poll_init, 2304 .poll_get_char = lpuart_poll_get_char, 2305 .poll_put_char = lpuart_poll_put_char, 2306 #endif 2307 }; 2308 2309 static const struct uart_ops lpuart32_pops = { 2310 .tx_empty = lpuart32_tx_empty, 2311 .set_mctrl = lpuart32_set_mctrl, 2312 .get_mctrl = lpuart32_get_mctrl, 2313 .stop_tx = lpuart32_stop_tx, 2314 .start_tx = lpuart32_start_tx, 2315 .stop_rx = lpuart32_stop_rx, 2316 .break_ctl = lpuart32_break_ctl, 2317 .startup = lpuart32_startup, 2318 .shutdown = lpuart32_shutdown, 2319 .set_termios = lpuart32_set_termios, 2320 .type = lpuart_type, 2321 .request_port = lpuart_request_port, 2322 .release_port = lpuart_release_port, 2323 .config_port = lpuart_config_port, 2324 .verify_port = lpuart_verify_port, 2325 .flush_buffer = lpuart_flush_buffer, 2326 #if defined(CONFIG_CONSOLE_POLL) 2327 .poll_init = lpuart32_poll_init, 2328 .poll_get_char = lpuart32_poll_get_char, 2329 .poll_put_char = lpuart32_poll_put_char, 2330 #endif 2331 }; 2332 2333 static struct lpuart_port *lpuart_ports[UART_NR]; 2334 2335 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 2336 static void lpuart_console_putchar(struct uart_port *port, unsigned char ch) 2337 { 2338 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 2339 writeb(ch, port->membase + UARTDR); 2340 } 2341 2342 static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch) 2343 { 2344 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 2345 lpuart32_write(port, ch, UARTDATA); 2346 } 2347 2348 static void 2349 lpuart_console_write(struct console *co, const char *s, unsigned int count) 2350 { 2351 struct lpuart_port *sport = lpuart_ports[co->index]; 2352 unsigned char old_cr2, cr2; 2353 unsigned long flags; 2354 int locked = 1; 2355 2356 if (oops_in_progress) 2357 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2358 else 2359 spin_lock_irqsave(&sport->port.lock, flags); 2360 2361 /* first save CR2 and then disable interrupts */ 2362 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 2363 cr2 |= UARTCR2_TE | UARTCR2_RE; 2364 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 2365 writeb(cr2, sport->port.membase + UARTCR2); 2366 2367 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 2368 2369 /* wait for transmitter finish complete and restore CR2 */ 2370 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 2371 2372 writeb(old_cr2, sport->port.membase + UARTCR2); 2373 2374 if (locked) 2375 spin_unlock_irqrestore(&sport->port.lock, flags); 2376 } 2377 2378 static void 2379 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 2380 { 2381 struct lpuart_port *sport = lpuart_ports[co->index]; 2382 unsigned long old_cr, cr; 2383 unsigned long flags; 2384 int locked = 1; 2385 2386 if (oops_in_progress) 2387 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2388 else 2389 spin_lock_irqsave(&sport->port.lock, flags); 2390 2391 /* first save CR2 and then disable interrupts */ 2392 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 2393 cr |= UARTCTRL_TE | UARTCTRL_RE; 2394 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 2395 lpuart32_write(&sport->port, cr, UARTCTRL); 2396 2397 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 2398 2399 /* wait for transmitter finish complete and restore CR2 */ 2400 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2401 2402 lpuart32_write(&sport->port, old_cr, UARTCTRL); 2403 2404 if (locked) 2405 spin_unlock_irqrestore(&sport->port.lock, flags); 2406 } 2407 2408 /* 2409 * if the port was already initialised (eg, by a boot loader), 2410 * try to determine the current setup. 2411 */ 2412 static void __init 2413 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 2414 int *parity, int *bits) 2415 { 2416 unsigned char cr, bdh, bdl, brfa; 2417 unsigned int sbr, uartclk, baud_raw; 2418 2419 cr = readb(sport->port.membase + UARTCR2); 2420 cr &= UARTCR2_TE | UARTCR2_RE; 2421 if (!cr) 2422 return; 2423 2424 /* ok, the port was enabled */ 2425 2426 cr = readb(sport->port.membase + UARTCR1); 2427 2428 *parity = 'n'; 2429 if (cr & UARTCR1_PE) { 2430 if (cr & UARTCR1_PT) 2431 *parity = 'o'; 2432 else 2433 *parity = 'e'; 2434 } 2435 2436 if (cr & UARTCR1_M) 2437 *bits = 9; 2438 else 2439 *bits = 8; 2440 2441 bdh = readb(sport->port.membase + UARTBDH); 2442 bdh &= UARTBDH_SBR_MASK; 2443 bdl = readb(sport->port.membase + UARTBDL); 2444 sbr = bdh; 2445 sbr <<= 8; 2446 sbr |= bdl; 2447 brfa = readb(sport->port.membase + UARTCR4); 2448 brfa &= UARTCR4_BRFA_MASK; 2449 2450 uartclk = lpuart_get_baud_clk_rate(sport); 2451 /* 2452 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2453 */ 2454 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 2455 2456 if (*baud != baud_raw) 2457 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2458 "from %d to %d\n", baud_raw, *baud); 2459 } 2460 2461 static void __init 2462 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 2463 int *parity, int *bits) 2464 { 2465 unsigned long cr, bd; 2466 unsigned int sbr, uartclk, baud_raw; 2467 2468 cr = lpuart32_read(&sport->port, UARTCTRL); 2469 cr &= UARTCTRL_TE | UARTCTRL_RE; 2470 if (!cr) 2471 return; 2472 2473 /* ok, the port was enabled */ 2474 2475 cr = lpuart32_read(&sport->port, UARTCTRL); 2476 2477 *parity = 'n'; 2478 if (cr & UARTCTRL_PE) { 2479 if (cr & UARTCTRL_PT) 2480 *parity = 'o'; 2481 else 2482 *parity = 'e'; 2483 } 2484 2485 if (cr & UARTCTRL_M) 2486 *bits = 9; 2487 else 2488 *bits = 8; 2489 2490 bd = lpuart32_read(&sport->port, UARTBAUD); 2491 bd &= UARTBAUD_SBR_MASK; 2492 if (!bd) 2493 return; 2494 2495 sbr = bd; 2496 uartclk = lpuart_get_baud_clk_rate(sport); 2497 /* 2498 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2499 */ 2500 baud_raw = uartclk / (16 * sbr); 2501 2502 if (*baud != baud_raw) 2503 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2504 "from %d to %d\n", baud_raw, *baud); 2505 } 2506 2507 static int __init lpuart_console_setup(struct console *co, char *options) 2508 { 2509 struct lpuart_port *sport; 2510 int baud = 115200; 2511 int bits = 8; 2512 int parity = 'n'; 2513 int flow = 'n'; 2514 2515 /* 2516 * check whether an invalid uart number has been specified, and 2517 * if so, search for the first available port that does have 2518 * console support. 2519 */ 2520 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2521 co->index = 0; 2522 2523 sport = lpuart_ports[co->index]; 2524 if (sport == NULL) 2525 return -ENODEV; 2526 2527 if (options) 2528 uart_parse_options(options, &baud, &parity, &bits, &flow); 2529 else 2530 if (lpuart_is_32(sport)) 2531 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2532 else 2533 lpuart_console_get_options(sport, &baud, &parity, &bits); 2534 2535 if (lpuart_is_32(sport)) 2536 lpuart32_setup_watermark(sport); 2537 else 2538 lpuart_setup_watermark(sport); 2539 2540 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2541 } 2542 2543 static struct uart_driver lpuart_reg; 2544 static struct console lpuart_console = { 2545 .name = DEV_NAME, 2546 .write = lpuart_console_write, 2547 .device = uart_console_device, 2548 .setup = lpuart_console_setup, 2549 .flags = CON_PRINTBUFFER, 2550 .index = -1, 2551 .data = &lpuart_reg, 2552 }; 2553 2554 static struct console lpuart32_console = { 2555 .name = DEV_NAME, 2556 .write = lpuart32_console_write, 2557 .device = uart_console_device, 2558 .setup = lpuart_console_setup, 2559 .flags = CON_PRINTBUFFER, 2560 .index = -1, 2561 .data = &lpuart_reg, 2562 }; 2563 2564 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2565 { 2566 struct earlycon_device *dev = con->data; 2567 2568 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2569 } 2570 2571 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2572 { 2573 struct earlycon_device *dev = con->data; 2574 2575 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2576 } 2577 2578 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2579 const char *opt) 2580 { 2581 if (!device->port.membase) 2582 return -ENODEV; 2583 2584 device->con->write = lpuart_early_write; 2585 return 0; 2586 } 2587 2588 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2589 const char *opt) 2590 { 2591 if (!device->port.membase) 2592 return -ENODEV; 2593 2594 if (device->port.iotype != UPIO_MEM32) 2595 device->port.iotype = UPIO_MEM32BE; 2596 2597 device->con->write = lpuart32_early_write; 2598 return 0; 2599 } 2600 2601 static int __init ls1028a_early_console_setup(struct earlycon_device *device, 2602 const char *opt) 2603 { 2604 u32 cr; 2605 2606 if (!device->port.membase) 2607 return -ENODEV; 2608 2609 device->port.iotype = UPIO_MEM32; 2610 device->con->write = lpuart32_early_write; 2611 2612 /* set the baudrate */ 2613 if (device->port.uartclk && device->baud) 2614 __lpuart32_serial_setbrg(&device->port, device->baud, 2615 false, false); 2616 2617 /* enable transmitter */ 2618 cr = lpuart32_read(&device->port, UARTCTRL); 2619 cr |= UARTCTRL_TE; 2620 lpuart32_write(&device->port, cr, UARTCTRL); 2621 2622 return 0; 2623 } 2624 2625 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2626 const char *opt) 2627 { 2628 if (!device->port.membase) 2629 return -ENODEV; 2630 2631 device->port.iotype = UPIO_MEM32; 2632 device->port.membase += IMX_REG_OFF; 2633 device->con->write = lpuart32_early_write; 2634 2635 return 0; 2636 } 2637 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2638 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2639 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup); 2640 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2641 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup); 2642 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup); 2643 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2644 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2645 2646 #define LPUART_CONSOLE (&lpuart_console) 2647 #define LPUART32_CONSOLE (&lpuart32_console) 2648 #else 2649 #define LPUART_CONSOLE NULL 2650 #define LPUART32_CONSOLE NULL 2651 #endif 2652 2653 static struct uart_driver lpuart_reg = { 2654 .owner = THIS_MODULE, 2655 .driver_name = DRIVER_NAME, 2656 .dev_name = DEV_NAME, 2657 .nr = ARRAY_SIZE(lpuart_ports), 2658 .cons = LPUART_CONSOLE, 2659 }; 2660 2661 static int lpuart_probe(struct platform_device *pdev) 2662 { 2663 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev); 2664 struct device_node *np = pdev->dev.of_node; 2665 struct lpuart_port *sport; 2666 struct resource *res; 2667 int ret; 2668 2669 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2670 if (!sport) 2671 return -ENOMEM; 2672 2673 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2674 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 2675 if (IS_ERR(sport->port.membase)) 2676 return PTR_ERR(sport->port.membase); 2677 2678 sport->port.membase += sdata->reg_off; 2679 sport->port.mapbase = res->start + sdata->reg_off; 2680 sport->port.dev = &pdev->dev; 2681 sport->port.type = PORT_LPUART; 2682 sport->devtype = sdata->devtype; 2683 ret = platform_get_irq(pdev, 0); 2684 if (ret < 0) 2685 return ret; 2686 sport->port.irq = ret; 2687 sport->port.iotype = sdata->iotype; 2688 if (lpuart_is_32(sport)) 2689 sport->port.ops = &lpuart32_pops; 2690 else 2691 sport->port.ops = &lpuart_pops; 2692 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); 2693 sport->port.flags = UPF_BOOT_AUTOCONF; 2694 2695 if (lpuart_is_32(sport)) 2696 sport->port.rs485_config = lpuart32_config_rs485; 2697 else 2698 sport->port.rs485_config = lpuart_config_rs485; 2699 2700 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 2701 if (IS_ERR(sport->ipg_clk)) { 2702 ret = PTR_ERR(sport->ipg_clk); 2703 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); 2704 return ret; 2705 } 2706 2707 sport->baud_clk = NULL; 2708 if (is_imx8qxp_lpuart(sport)) { 2709 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); 2710 if (IS_ERR(sport->baud_clk)) { 2711 ret = PTR_ERR(sport->baud_clk); 2712 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); 2713 return ret; 2714 } 2715 } 2716 2717 ret = of_alias_get_id(np, "serial"); 2718 if (ret < 0) { 2719 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL); 2720 if (ret < 0) { 2721 dev_err(&pdev->dev, "port line is full, add device failed\n"); 2722 return ret; 2723 } 2724 sport->id_allocated = true; 2725 } 2726 if (ret >= ARRAY_SIZE(lpuart_ports)) { 2727 dev_err(&pdev->dev, "serial%d out of range\n", ret); 2728 ret = -EINVAL; 2729 goto failed_out_of_range; 2730 } 2731 sport->port.line = ret; 2732 2733 ret = lpuart_enable_clks(sport); 2734 if (ret) 2735 goto failed_clock_enable; 2736 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); 2737 2738 lpuart_ports[sport->port.line] = sport; 2739 2740 platform_set_drvdata(pdev, &sport->port); 2741 2742 if (lpuart_is_32(sport)) { 2743 lpuart_reg.cons = LPUART32_CONSOLE; 2744 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0, 2745 DRIVER_NAME, sport); 2746 } else { 2747 lpuart_reg.cons = LPUART_CONSOLE; 2748 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0, 2749 DRIVER_NAME, sport); 2750 } 2751 2752 if (ret) 2753 goto failed_irq_request; 2754 2755 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2756 if (ret) 2757 goto failed_attach_port; 2758 2759 ret = lpuart_global_reset(sport); 2760 if (ret) 2761 goto failed_reset; 2762 2763 ret = uart_get_rs485_mode(&sport->port); 2764 if (ret) 2765 goto failed_get_rs485; 2766 2767 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX) 2768 dev_err(&pdev->dev, "driver doesn't support RX during TX\n"); 2769 2770 if (sport->port.rs485.delay_rts_before_send || 2771 sport->port.rs485.delay_rts_after_send) 2772 dev_err(&pdev->dev, "driver doesn't support RTS delays\n"); 2773 2774 sport->port.rs485_config(&sport->port, &sport->port.rs485); 2775 2776 return 0; 2777 2778 failed_get_rs485: 2779 failed_reset: 2780 uart_remove_one_port(&lpuart_reg, &sport->port); 2781 failed_attach_port: 2782 failed_irq_request: 2783 lpuart_disable_clks(sport); 2784 failed_clock_enable: 2785 failed_out_of_range: 2786 if (sport->id_allocated) 2787 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); 2788 return ret; 2789 } 2790 2791 static int lpuart_remove(struct platform_device *pdev) 2792 { 2793 struct lpuart_port *sport = platform_get_drvdata(pdev); 2794 2795 uart_remove_one_port(&lpuart_reg, &sport->port); 2796 2797 if (sport->id_allocated) 2798 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); 2799 2800 lpuart_disable_clks(sport); 2801 2802 if (sport->dma_tx_chan) 2803 dma_release_channel(sport->dma_tx_chan); 2804 2805 if (sport->dma_rx_chan) 2806 dma_release_channel(sport->dma_rx_chan); 2807 2808 return 0; 2809 } 2810 2811 static int __maybe_unused lpuart_suspend(struct device *dev) 2812 { 2813 struct lpuart_port *sport = dev_get_drvdata(dev); 2814 unsigned long temp; 2815 bool irq_wake; 2816 2817 if (lpuart_is_32(sport)) { 2818 /* disable Rx/Tx and interrupts */ 2819 temp = lpuart32_read(&sport->port, UARTCTRL); 2820 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2821 lpuart32_write(&sport->port, temp, UARTCTRL); 2822 } else { 2823 /* disable Rx/Tx and interrupts */ 2824 temp = readb(sport->port.membase + UARTCR2); 2825 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2826 writeb(temp, sport->port.membase + UARTCR2); 2827 } 2828 2829 uart_suspend_port(&lpuart_reg, &sport->port); 2830 2831 /* uart_suspend_port() might set wakeup flag */ 2832 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2833 2834 if (sport->lpuart_dma_rx_use) { 2835 /* 2836 * EDMA driver during suspend will forcefully release any 2837 * non-idle DMA channels. If port wakeup is enabled or if port 2838 * is console port or 'no_console_suspend' is set the Rx DMA 2839 * cannot resume as as expected, hence gracefully release the 2840 * Rx DMA path before suspend and start Rx DMA path on resume. 2841 */ 2842 if (irq_wake) { 2843 del_timer_sync(&sport->lpuart_timer); 2844 lpuart_dma_rx_free(&sport->port); 2845 } 2846 2847 /* Disable Rx DMA to use UART port as wakeup source */ 2848 if (lpuart_is_32(sport)) { 2849 temp = lpuart32_read(&sport->port, UARTBAUD); 2850 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, 2851 UARTBAUD); 2852 } else { 2853 writeb(readb(sport->port.membase + UARTCR5) & 2854 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 2855 } 2856 } 2857 2858 if (sport->lpuart_dma_tx_use) { 2859 sport->dma_tx_in_progress = false; 2860 dmaengine_terminate_all(sport->dma_tx_chan); 2861 } 2862 2863 if (sport->port.suspended && !irq_wake) 2864 lpuart_disable_clks(sport); 2865 2866 return 0; 2867 } 2868 2869 static int __maybe_unused lpuart_resume(struct device *dev) 2870 { 2871 struct lpuart_port *sport = dev_get_drvdata(dev); 2872 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2873 2874 if (sport->port.suspended && !irq_wake) 2875 lpuart_enable_clks(sport); 2876 2877 if (lpuart_is_32(sport)) 2878 lpuart32_setup_watermark_enable(sport); 2879 else 2880 lpuart_setup_watermark_enable(sport); 2881 2882 if (sport->lpuart_dma_rx_use) { 2883 if (irq_wake) { 2884 if (!lpuart_start_rx_dma(sport)) 2885 rx_dma_timer_init(sport); 2886 else 2887 sport->lpuart_dma_rx_use = false; 2888 } 2889 } 2890 2891 lpuart_tx_dma_startup(sport); 2892 2893 if (lpuart_is_32(sport)) 2894 lpuart32_configure(sport); 2895 2896 uart_resume_port(&lpuart_reg, &sport->port); 2897 2898 return 0; 2899 } 2900 2901 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2902 2903 static struct platform_driver lpuart_driver = { 2904 .probe = lpuart_probe, 2905 .remove = lpuart_remove, 2906 .driver = { 2907 .name = "fsl-lpuart", 2908 .of_match_table = lpuart_dt_ids, 2909 .pm = &lpuart_pm_ops, 2910 }, 2911 }; 2912 2913 static int __init lpuart_serial_init(void) 2914 { 2915 int ret = uart_register_driver(&lpuart_reg); 2916 2917 if (ret) 2918 return ret; 2919 2920 ret = platform_driver_register(&lpuart_driver); 2921 if (ret) 2922 uart_unregister_driver(&lpuart_reg); 2923 2924 return ret; 2925 } 2926 2927 static void __exit lpuart_serial_exit(void) 2928 { 2929 ida_destroy(&fsl_lpuart_ida); 2930 platform_driver_unregister(&lpuart_driver); 2931 uart_unregister_driver(&lpuart_reg); 2932 } 2933 2934 module_init(lpuart_serial_init); 2935 module_exit(lpuart_serial_exit); 2936 2937 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2938 MODULE_LICENSE("GPL v2"); 2939