1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale lpuart serial port driver 4 * 5 * Copyright 2012-2014 Freescale Semiconductor, Inc. 6 */ 7 8 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 9 #define SUPPORT_SYSRQ 10 #endif 11 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dmapool.h> 17 #include <linux/io.h> 18 #include <linux/irq.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/of_dma.h> 23 #include <linux/serial_core.h> 24 #include <linux/slab.h> 25 #include <linux/tty_flip.h> 26 27 /* All registers are 8-bit width */ 28 #define UARTBDH 0x00 29 #define UARTBDL 0x01 30 #define UARTCR1 0x02 31 #define UARTCR2 0x03 32 #define UARTSR1 0x04 33 #define UARTCR3 0x06 34 #define UARTDR 0x07 35 #define UARTCR4 0x0a 36 #define UARTCR5 0x0b 37 #define UARTMODEM 0x0d 38 #define UARTPFIFO 0x10 39 #define UARTCFIFO 0x11 40 #define UARTSFIFO 0x12 41 #define UARTTWFIFO 0x13 42 #define UARTTCFIFO 0x14 43 #define UARTRWFIFO 0x15 44 45 #define UARTBDH_LBKDIE 0x80 46 #define UARTBDH_RXEDGIE 0x40 47 #define UARTBDH_SBR_MASK 0x1f 48 49 #define UARTCR1_LOOPS 0x80 50 #define UARTCR1_RSRC 0x20 51 #define UARTCR1_M 0x10 52 #define UARTCR1_WAKE 0x08 53 #define UARTCR1_ILT 0x04 54 #define UARTCR1_PE 0x02 55 #define UARTCR1_PT 0x01 56 57 #define UARTCR2_TIE 0x80 58 #define UARTCR2_TCIE 0x40 59 #define UARTCR2_RIE 0x20 60 #define UARTCR2_ILIE 0x10 61 #define UARTCR2_TE 0x08 62 #define UARTCR2_RE 0x04 63 #define UARTCR2_RWU 0x02 64 #define UARTCR2_SBK 0x01 65 66 #define UARTSR1_TDRE 0x80 67 #define UARTSR1_TC 0x40 68 #define UARTSR1_RDRF 0x20 69 #define UARTSR1_IDLE 0x10 70 #define UARTSR1_OR 0x08 71 #define UARTSR1_NF 0x04 72 #define UARTSR1_FE 0x02 73 #define UARTSR1_PE 0x01 74 75 #define UARTCR3_R8 0x80 76 #define UARTCR3_T8 0x40 77 #define UARTCR3_TXDIR 0x20 78 #define UARTCR3_TXINV 0x10 79 #define UARTCR3_ORIE 0x08 80 #define UARTCR3_NEIE 0x04 81 #define UARTCR3_FEIE 0x02 82 #define UARTCR3_PEIE 0x01 83 84 #define UARTCR4_MAEN1 0x80 85 #define UARTCR4_MAEN2 0x40 86 #define UARTCR4_M10 0x20 87 #define UARTCR4_BRFA_MASK 0x1f 88 #define UARTCR4_BRFA_OFF 0 89 90 #define UARTCR5_TDMAS 0x80 91 #define UARTCR5_RDMAS 0x20 92 93 #define UARTMODEM_RXRTSE 0x08 94 #define UARTMODEM_TXRTSPOL 0x04 95 #define UARTMODEM_TXRTSE 0x02 96 #define UARTMODEM_TXCTSE 0x01 97 98 #define UARTPFIFO_TXFE 0x80 99 #define UARTPFIFO_FIFOSIZE_MASK 0x7 100 #define UARTPFIFO_TXSIZE_OFF 4 101 #define UARTPFIFO_RXFE 0x08 102 #define UARTPFIFO_RXSIZE_OFF 0 103 104 #define UARTCFIFO_TXFLUSH 0x80 105 #define UARTCFIFO_RXFLUSH 0x40 106 #define UARTCFIFO_RXOFE 0x04 107 #define UARTCFIFO_TXOFE 0x02 108 #define UARTCFIFO_RXUFE 0x01 109 110 #define UARTSFIFO_TXEMPT 0x80 111 #define UARTSFIFO_RXEMPT 0x40 112 #define UARTSFIFO_RXOF 0x04 113 #define UARTSFIFO_TXOF 0x02 114 #define UARTSFIFO_RXUF 0x01 115 116 /* 32-bit register definition */ 117 #define UARTBAUD 0x00 118 #define UARTSTAT 0x04 119 #define UARTCTRL 0x08 120 #define UARTDATA 0x0C 121 #define UARTMATCH 0x10 122 #define UARTMODIR 0x14 123 #define UARTFIFO 0x18 124 #define UARTWATER 0x1c 125 126 #define UARTBAUD_MAEN1 0x80000000 127 #define UARTBAUD_MAEN2 0x40000000 128 #define UARTBAUD_M10 0x20000000 129 #define UARTBAUD_TDMAE 0x00800000 130 #define UARTBAUD_RDMAE 0x00200000 131 #define UARTBAUD_MATCFG 0x00400000 132 #define UARTBAUD_BOTHEDGE 0x00020000 133 #define UARTBAUD_RESYNCDIS 0x00010000 134 #define UARTBAUD_LBKDIE 0x00008000 135 #define UARTBAUD_RXEDGIE 0x00004000 136 #define UARTBAUD_SBNS 0x00002000 137 #define UARTBAUD_SBR 0x00000000 138 #define UARTBAUD_SBR_MASK 0x1fff 139 #define UARTBAUD_OSR_MASK 0x1f 140 #define UARTBAUD_OSR_SHIFT 24 141 142 #define UARTSTAT_LBKDIF 0x80000000 143 #define UARTSTAT_RXEDGIF 0x40000000 144 #define UARTSTAT_MSBF 0x20000000 145 #define UARTSTAT_RXINV 0x10000000 146 #define UARTSTAT_RWUID 0x08000000 147 #define UARTSTAT_BRK13 0x04000000 148 #define UARTSTAT_LBKDE 0x02000000 149 #define UARTSTAT_RAF 0x01000000 150 #define UARTSTAT_TDRE 0x00800000 151 #define UARTSTAT_TC 0x00400000 152 #define UARTSTAT_RDRF 0x00200000 153 #define UARTSTAT_IDLE 0x00100000 154 #define UARTSTAT_OR 0x00080000 155 #define UARTSTAT_NF 0x00040000 156 #define UARTSTAT_FE 0x00020000 157 #define UARTSTAT_PE 0x00010000 158 #define UARTSTAT_MA1F 0x00008000 159 #define UARTSTAT_M21F 0x00004000 160 161 #define UARTCTRL_R8T9 0x80000000 162 #define UARTCTRL_R9T8 0x40000000 163 #define UARTCTRL_TXDIR 0x20000000 164 #define UARTCTRL_TXINV 0x10000000 165 #define UARTCTRL_ORIE 0x08000000 166 #define UARTCTRL_NEIE 0x04000000 167 #define UARTCTRL_FEIE 0x02000000 168 #define UARTCTRL_PEIE 0x01000000 169 #define UARTCTRL_TIE 0x00800000 170 #define UARTCTRL_TCIE 0x00400000 171 #define UARTCTRL_RIE 0x00200000 172 #define UARTCTRL_ILIE 0x00100000 173 #define UARTCTRL_TE 0x00080000 174 #define UARTCTRL_RE 0x00040000 175 #define UARTCTRL_RWU 0x00020000 176 #define UARTCTRL_SBK 0x00010000 177 #define UARTCTRL_MA1IE 0x00008000 178 #define UARTCTRL_MA2IE 0x00004000 179 #define UARTCTRL_IDLECFG 0x00000100 180 #define UARTCTRL_LOOPS 0x00000080 181 #define UARTCTRL_DOZEEN 0x00000040 182 #define UARTCTRL_RSRC 0x00000020 183 #define UARTCTRL_M 0x00000010 184 #define UARTCTRL_WAKE 0x00000008 185 #define UARTCTRL_ILT 0x00000004 186 #define UARTCTRL_PE 0x00000002 187 #define UARTCTRL_PT 0x00000001 188 189 #define UARTDATA_NOISY 0x00008000 190 #define UARTDATA_PARITYE 0x00004000 191 #define UARTDATA_FRETSC 0x00002000 192 #define UARTDATA_RXEMPT 0x00001000 193 #define UARTDATA_IDLINE 0x00000800 194 #define UARTDATA_MASK 0x3ff 195 196 #define UARTMODIR_IREN 0x00020000 197 #define UARTMODIR_TXCTSSRC 0x00000020 198 #define UARTMODIR_TXCTSC 0x00000010 199 #define UARTMODIR_RXRTSE 0x00000008 200 #define UARTMODIR_TXRTSPOL 0x00000004 201 #define UARTMODIR_TXRTSE 0x00000002 202 #define UARTMODIR_TXCTSE 0x00000001 203 204 #define UARTFIFO_TXEMPT 0x00800000 205 #define UARTFIFO_RXEMPT 0x00400000 206 #define UARTFIFO_TXOF 0x00020000 207 #define UARTFIFO_RXUF 0x00010000 208 #define UARTFIFO_TXFLUSH 0x00008000 209 #define UARTFIFO_RXFLUSH 0x00004000 210 #define UARTFIFO_TXOFE 0x00000200 211 #define UARTFIFO_RXUFE 0x00000100 212 #define UARTFIFO_TXFE 0x00000080 213 #define UARTFIFO_FIFOSIZE_MASK 0x7 214 #define UARTFIFO_TXSIZE_OFF 4 215 #define UARTFIFO_RXFE 0x00000008 216 #define UARTFIFO_RXSIZE_OFF 0 217 218 #define UARTWATER_COUNT_MASK 0xff 219 #define UARTWATER_TXCNT_OFF 8 220 #define UARTWATER_RXCNT_OFF 24 221 #define UARTWATER_WATER_MASK 0xff 222 #define UARTWATER_TXWATER_OFF 0 223 #define UARTWATER_RXWATER_OFF 16 224 225 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 226 #define DMA_RX_TIMEOUT (10) 227 228 #define DRIVER_NAME "fsl-lpuart" 229 #define DEV_NAME "ttyLP" 230 #define UART_NR 6 231 232 /* IMX lpuart has four extra unused regs located at the beginning */ 233 #define IMX_REG_OFF 0x10 234 235 static DEFINE_IDA(fsl_lpuart_ida); 236 237 enum lpuart_type { 238 VF610_LPUART, 239 LS1021A_LPUART, 240 IMX7ULP_LPUART, 241 IMX8QXP_LPUART, 242 }; 243 244 struct lpuart_port { 245 struct uart_port port; 246 enum lpuart_type devtype; 247 struct clk *ipg_clk; 248 struct clk *baud_clk; 249 unsigned int txfifo_size; 250 unsigned int rxfifo_size; 251 252 bool lpuart_dma_tx_use; 253 bool lpuart_dma_rx_use; 254 struct dma_chan *dma_tx_chan; 255 struct dma_chan *dma_rx_chan; 256 struct dma_async_tx_descriptor *dma_tx_desc; 257 struct dma_async_tx_descriptor *dma_rx_desc; 258 dma_cookie_t dma_tx_cookie; 259 dma_cookie_t dma_rx_cookie; 260 unsigned int dma_tx_bytes; 261 unsigned int dma_rx_bytes; 262 bool dma_tx_in_progress; 263 unsigned int dma_rx_timeout; 264 struct timer_list lpuart_timer; 265 struct scatterlist rx_sgl, tx_sgl[2]; 266 struct circ_buf rx_ring; 267 int rx_dma_rng_buf_len; 268 unsigned int dma_tx_nents; 269 wait_queue_head_t dma_wait; 270 }; 271 272 struct lpuart_soc_data { 273 enum lpuart_type devtype; 274 char iotype; 275 u8 reg_off; 276 }; 277 278 static const struct lpuart_soc_data vf_data = { 279 .devtype = VF610_LPUART, 280 .iotype = UPIO_MEM, 281 }; 282 283 static const struct lpuart_soc_data ls_data = { 284 .devtype = LS1021A_LPUART, 285 .iotype = UPIO_MEM32BE, 286 }; 287 288 static struct lpuart_soc_data imx7ulp_data = { 289 .devtype = IMX7ULP_LPUART, 290 .iotype = UPIO_MEM32, 291 .reg_off = IMX_REG_OFF, 292 }; 293 294 static struct lpuart_soc_data imx8qxp_data = { 295 .devtype = IMX8QXP_LPUART, 296 .iotype = UPIO_MEM32, 297 .reg_off = IMX_REG_OFF, 298 }; 299 300 static const struct of_device_id lpuart_dt_ids[] = { 301 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 302 { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, }, 303 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, 304 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, 305 { /* sentinel */ } 306 }; 307 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 308 309 /* Forward declare this for the dma callbacks*/ 310 static void lpuart_dma_tx_complete(void *arg); 311 312 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) 313 { 314 return sport->devtype == IMX8QXP_LPUART; 315 } 316 317 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 318 { 319 switch (port->iotype) { 320 case UPIO_MEM32: 321 return readl(port->membase + off); 322 case UPIO_MEM32BE: 323 return ioread32be(port->membase + off); 324 default: 325 return 0; 326 } 327 } 328 329 static inline void lpuart32_write(struct uart_port *port, u32 val, 330 u32 off) 331 { 332 switch (port->iotype) { 333 case UPIO_MEM32: 334 writel(val, port->membase + off); 335 break; 336 case UPIO_MEM32BE: 337 iowrite32be(val, port->membase + off); 338 break; 339 } 340 } 341 342 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) 343 { 344 int ret = 0; 345 346 if (is_en) { 347 ret = clk_prepare_enable(sport->ipg_clk); 348 if (ret) 349 return ret; 350 351 ret = clk_prepare_enable(sport->baud_clk); 352 if (ret) { 353 clk_disable_unprepare(sport->ipg_clk); 354 return ret; 355 } 356 } else { 357 clk_disable_unprepare(sport->baud_clk); 358 clk_disable_unprepare(sport->ipg_clk); 359 } 360 361 return 0; 362 } 363 364 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) 365 { 366 if (is_imx8qxp_lpuart(sport)) 367 return clk_get_rate(sport->baud_clk); 368 369 return clk_get_rate(sport->ipg_clk); 370 } 371 372 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true) 373 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false) 374 375 static void lpuart_stop_tx(struct uart_port *port) 376 { 377 unsigned char temp; 378 379 temp = readb(port->membase + UARTCR2); 380 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 381 writeb(temp, port->membase + UARTCR2); 382 } 383 384 static void lpuart32_stop_tx(struct uart_port *port) 385 { 386 unsigned long temp; 387 388 temp = lpuart32_read(port, UARTCTRL); 389 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 390 lpuart32_write(port, temp, UARTCTRL); 391 } 392 393 static void lpuart_stop_rx(struct uart_port *port) 394 { 395 unsigned char temp; 396 397 temp = readb(port->membase + UARTCR2); 398 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 399 } 400 401 static void lpuart32_stop_rx(struct uart_port *port) 402 { 403 unsigned long temp; 404 405 temp = lpuart32_read(port, UARTCTRL); 406 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); 407 } 408 409 static void lpuart_dma_tx(struct lpuart_port *sport) 410 { 411 struct circ_buf *xmit = &sport->port.state->xmit; 412 struct scatterlist *sgl = sport->tx_sgl; 413 struct device *dev = sport->port.dev; 414 int ret; 415 416 if (sport->dma_tx_in_progress) 417 return; 418 419 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 420 421 if (xmit->tail < xmit->head || xmit->head == 0) { 422 sport->dma_tx_nents = 1; 423 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 424 } else { 425 sport->dma_tx_nents = 2; 426 sg_init_table(sgl, 2); 427 sg_set_buf(sgl, xmit->buf + xmit->tail, 428 UART_XMIT_SIZE - xmit->tail); 429 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 430 } 431 432 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 433 if (!ret) { 434 dev_err(dev, "DMA mapping error for TX.\n"); 435 return; 436 } 437 438 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl, 439 sport->dma_tx_nents, 440 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 441 if (!sport->dma_tx_desc) { 442 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 443 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 444 return; 445 } 446 447 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 448 sport->dma_tx_desc->callback_param = sport; 449 sport->dma_tx_in_progress = true; 450 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 451 dma_async_issue_pending(sport->dma_tx_chan); 452 } 453 454 static void lpuart_dma_tx_complete(void *arg) 455 { 456 struct lpuart_port *sport = arg; 457 struct scatterlist *sgl = &sport->tx_sgl[0]; 458 struct circ_buf *xmit = &sport->port.state->xmit; 459 unsigned long flags; 460 461 spin_lock_irqsave(&sport->port.lock, flags); 462 463 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 464 465 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 466 467 sport->port.icount.tx += sport->dma_tx_bytes; 468 sport->dma_tx_in_progress = false; 469 spin_unlock_irqrestore(&sport->port.lock, flags); 470 471 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 472 uart_write_wakeup(&sport->port); 473 474 if (waitqueue_active(&sport->dma_wait)) { 475 wake_up(&sport->dma_wait); 476 return; 477 } 478 479 spin_lock_irqsave(&sport->port.lock, flags); 480 481 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 482 lpuart_dma_tx(sport); 483 484 spin_unlock_irqrestore(&sport->port.lock, flags); 485 } 486 487 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) 488 { 489 switch (sport->port.iotype) { 490 case UPIO_MEM32: 491 return sport->port.mapbase + UARTDATA; 492 case UPIO_MEM32BE: 493 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; 494 } 495 return sport->port.mapbase + UARTDR; 496 } 497 498 static int lpuart_dma_tx_request(struct uart_port *port) 499 { 500 struct lpuart_port *sport = container_of(port, 501 struct lpuart_port, port); 502 struct dma_slave_config dma_tx_sconfig = {}; 503 int ret; 504 505 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); 506 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 507 dma_tx_sconfig.dst_maxburst = 1; 508 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 509 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 510 511 if (ret) { 512 dev_err(sport->port.dev, 513 "DMA slave config failed, err = %d\n", ret); 514 return ret; 515 } 516 517 return 0; 518 } 519 520 static void lpuart_flush_buffer(struct uart_port *port) 521 { 522 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 523 524 if (sport->lpuart_dma_tx_use) { 525 if (sport->dma_tx_in_progress) { 526 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 527 sport->dma_tx_nents, DMA_TO_DEVICE); 528 sport->dma_tx_in_progress = false; 529 } 530 dmaengine_terminate_all(sport->dma_tx_chan); 531 } 532 } 533 534 #if defined(CONFIG_CONSOLE_POLL) 535 536 static int lpuart_poll_init(struct uart_port *port) 537 { 538 struct lpuart_port *sport = container_of(port, 539 struct lpuart_port, port); 540 unsigned long flags; 541 unsigned char temp; 542 543 sport->port.fifosize = 0; 544 545 spin_lock_irqsave(&sport->port.lock, flags); 546 /* Disable Rx & Tx */ 547 writeb(0, sport->port.membase + UARTCR2); 548 549 temp = readb(sport->port.membase + UARTPFIFO); 550 /* Enable Rx and Tx FIFO */ 551 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 552 sport->port.membase + UARTPFIFO); 553 554 /* flush Tx and Rx FIFO */ 555 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 556 sport->port.membase + UARTCFIFO); 557 558 /* explicitly clear RDRF */ 559 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 560 readb(sport->port.membase + UARTDR); 561 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 562 } 563 564 writeb(0, sport->port.membase + UARTTWFIFO); 565 writeb(1, sport->port.membase + UARTRWFIFO); 566 567 /* Enable Rx and Tx */ 568 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 569 spin_unlock_irqrestore(&sport->port.lock, flags); 570 571 return 0; 572 } 573 574 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 575 { 576 /* drain */ 577 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) 578 barrier(); 579 580 writeb(c, port->membase + UARTDR); 581 } 582 583 static int lpuart_poll_get_char(struct uart_port *port) 584 { 585 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 586 return NO_POLL_CHAR; 587 588 return readb(port->membase + UARTDR); 589 } 590 591 static int lpuart32_poll_init(struct uart_port *port) 592 { 593 unsigned long flags; 594 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 595 u32 temp; 596 597 sport->port.fifosize = 0; 598 599 spin_lock_irqsave(&sport->port.lock, flags); 600 601 /* Disable Rx & Tx */ 602 writel(0, sport->port.membase + UARTCTRL); 603 604 temp = readl(sport->port.membase + UARTFIFO); 605 606 /* Enable Rx and Tx FIFO */ 607 writel(temp | UARTFIFO_RXFE | UARTFIFO_TXFE, 608 sport->port.membase + UARTFIFO); 609 610 /* flush Tx and Rx FIFO */ 611 writel(UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, 612 sport->port.membase + UARTFIFO); 613 614 /* explicitly clear RDRF */ 615 if (readl(sport->port.membase + UARTSTAT) & UARTSTAT_RDRF) { 616 readl(sport->port.membase + UARTDATA); 617 writel(UARTFIFO_RXUF, sport->port.membase + UARTFIFO); 618 } 619 620 /* Enable Rx and Tx */ 621 writel(UARTCTRL_RE | UARTCTRL_TE, sport->port.membase + UARTCTRL); 622 spin_unlock_irqrestore(&sport->port.lock, flags); 623 624 return 0; 625 } 626 627 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 628 { 629 while (!(readl(port->membase + UARTSTAT) & UARTSTAT_TDRE)) 630 barrier(); 631 632 writel(c, port->membase + UARTDATA); 633 } 634 635 static int lpuart32_poll_get_char(struct uart_port *port) 636 { 637 if (!(readl(port->membase + UARTSTAT) & UARTSTAT_RDRF)) 638 return NO_POLL_CHAR; 639 640 return readl(port->membase + UARTDATA); 641 } 642 #endif 643 644 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 645 { 646 struct circ_buf *xmit = &sport->port.state->xmit; 647 648 while (!uart_circ_empty(xmit) && 649 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 650 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 651 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 652 sport->port.icount.tx++; 653 } 654 655 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 656 uart_write_wakeup(&sport->port); 657 658 if (uart_circ_empty(xmit)) 659 lpuart_stop_tx(&sport->port); 660 } 661 662 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 663 { 664 struct circ_buf *xmit = &sport->port.state->xmit; 665 unsigned long txcnt; 666 667 txcnt = lpuart32_read(&sport->port, UARTWATER); 668 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 669 txcnt &= UARTWATER_COUNT_MASK; 670 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 671 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); 672 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 673 sport->port.icount.tx++; 674 txcnt = lpuart32_read(&sport->port, UARTWATER); 675 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 676 txcnt &= UARTWATER_COUNT_MASK; 677 } 678 679 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 680 uart_write_wakeup(&sport->port); 681 682 if (uart_circ_empty(xmit)) 683 lpuart32_stop_tx(&sport->port); 684 } 685 686 static void lpuart_start_tx(struct uart_port *port) 687 { 688 struct lpuart_port *sport = container_of(port, 689 struct lpuart_port, port); 690 struct circ_buf *xmit = &sport->port.state->xmit; 691 unsigned char temp; 692 693 temp = readb(port->membase + UARTCR2); 694 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 695 696 if (sport->lpuart_dma_tx_use) { 697 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) 698 lpuart_dma_tx(sport); 699 } else { 700 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 701 lpuart_transmit_buffer(sport); 702 } 703 } 704 705 static void lpuart32_start_tx(struct uart_port *port) 706 { 707 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 708 struct circ_buf *xmit = &sport->port.state->xmit; 709 unsigned long temp; 710 711 if (sport->lpuart_dma_tx_use) { 712 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) 713 lpuart_dma_tx(sport); 714 } else { 715 temp = lpuart32_read(port, UARTCTRL); 716 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); 717 718 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 719 lpuart32_transmit_buffer(sport); 720 } 721 } 722 723 /* return TIOCSER_TEMT when transmitter is not busy */ 724 static unsigned int lpuart_tx_empty(struct uart_port *port) 725 { 726 struct lpuart_port *sport = container_of(port, 727 struct lpuart_port, port); 728 unsigned char sr1 = readb(port->membase + UARTSR1); 729 unsigned char sfifo = readb(port->membase + UARTSFIFO); 730 731 if (sport->dma_tx_in_progress) 732 return 0; 733 734 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 735 return TIOCSER_TEMT; 736 737 return 0; 738 } 739 740 static unsigned int lpuart32_tx_empty(struct uart_port *port) 741 { 742 struct lpuart_port *sport = container_of(port, 743 struct lpuart_port, port); 744 unsigned long stat = lpuart32_read(port, UARTSTAT); 745 unsigned long sfifo = lpuart32_read(port, UARTFIFO); 746 747 if (sport->dma_tx_in_progress) 748 return 0; 749 750 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) 751 return TIOCSER_TEMT; 752 753 return 0; 754 } 755 756 static bool lpuart_is_32(struct lpuart_port *sport) 757 { 758 return sport->port.iotype == UPIO_MEM32 || 759 sport->port.iotype == UPIO_MEM32BE; 760 } 761 762 static irqreturn_t lpuart_txint(int irq, void *dev_id) 763 { 764 struct lpuart_port *sport = dev_id; 765 struct circ_buf *xmit = &sport->port.state->xmit; 766 unsigned long flags; 767 768 spin_lock_irqsave(&sport->port.lock, flags); 769 if (sport->port.x_char) { 770 if (lpuart_is_32(sport)) 771 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 772 else 773 writeb(sport->port.x_char, sport->port.membase + UARTDR); 774 goto out; 775 } 776 777 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 778 if (lpuart_is_32(sport)) 779 lpuart32_stop_tx(&sport->port); 780 else 781 lpuart_stop_tx(&sport->port); 782 goto out; 783 } 784 785 if (lpuart_is_32(sport)) 786 lpuart32_transmit_buffer(sport); 787 else 788 lpuart_transmit_buffer(sport); 789 790 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 791 uart_write_wakeup(&sport->port); 792 793 out: 794 spin_unlock_irqrestore(&sport->port.lock, flags); 795 return IRQ_HANDLED; 796 } 797 798 static irqreturn_t lpuart_rxint(int irq, void *dev_id) 799 { 800 struct lpuart_port *sport = dev_id; 801 unsigned int flg, ignored = 0; 802 struct tty_port *port = &sport->port.state->port; 803 unsigned long flags; 804 unsigned char rx, sr; 805 806 spin_lock_irqsave(&sport->port.lock, flags); 807 808 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 809 flg = TTY_NORMAL; 810 sport->port.icount.rx++; 811 /* 812 * to clear the FE, OR, NF, FE, PE flags, 813 * read SR1 then read DR 814 */ 815 sr = readb(sport->port.membase + UARTSR1); 816 rx = readb(sport->port.membase + UARTDR); 817 818 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 819 continue; 820 821 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 822 if (sr & UARTSR1_PE) 823 sport->port.icount.parity++; 824 else if (sr & UARTSR1_FE) 825 sport->port.icount.frame++; 826 827 if (sr & UARTSR1_OR) 828 sport->port.icount.overrun++; 829 830 if (sr & sport->port.ignore_status_mask) { 831 if (++ignored > 100) 832 goto out; 833 continue; 834 } 835 836 sr &= sport->port.read_status_mask; 837 838 if (sr & UARTSR1_PE) 839 flg = TTY_PARITY; 840 else if (sr & UARTSR1_FE) 841 flg = TTY_FRAME; 842 843 if (sr & UARTSR1_OR) 844 flg = TTY_OVERRUN; 845 846 #ifdef SUPPORT_SYSRQ 847 sport->port.sysrq = 0; 848 #endif 849 } 850 851 tty_insert_flip_char(port, rx, flg); 852 } 853 854 out: 855 spin_unlock_irqrestore(&sport->port.lock, flags); 856 857 tty_flip_buffer_push(port); 858 return IRQ_HANDLED; 859 } 860 861 static irqreturn_t lpuart32_rxint(int irq, void *dev_id) 862 { 863 struct lpuart_port *sport = dev_id; 864 unsigned int flg, ignored = 0; 865 struct tty_port *port = &sport->port.state->port; 866 unsigned long flags; 867 unsigned long rx, sr; 868 869 spin_lock_irqsave(&sport->port.lock, flags); 870 871 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 872 flg = TTY_NORMAL; 873 sport->port.icount.rx++; 874 /* 875 * to clear the FE, OR, NF, FE, PE flags, 876 * read STAT then read DATA reg 877 */ 878 sr = lpuart32_read(&sport->port, UARTSTAT); 879 rx = lpuart32_read(&sport->port, UARTDATA); 880 rx &= 0x3ff; 881 882 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 883 continue; 884 885 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 886 if (sr & UARTSTAT_PE) 887 sport->port.icount.parity++; 888 else if (sr & UARTSTAT_FE) 889 sport->port.icount.frame++; 890 891 if (sr & UARTSTAT_OR) 892 sport->port.icount.overrun++; 893 894 if (sr & sport->port.ignore_status_mask) { 895 if (++ignored > 100) 896 goto out; 897 continue; 898 } 899 900 sr &= sport->port.read_status_mask; 901 902 if (sr & UARTSTAT_PE) 903 flg = TTY_PARITY; 904 else if (sr & UARTSTAT_FE) 905 flg = TTY_FRAME; 906 907 if (sr & UARTSTAT_OR) 908 flg = TTY_OVERRUN; 909 910 #ifdef SUPPORT_SYSRQ 911 sport->port.sysrq = 0; 912 #endif 913 } 914 915 tty_insert_flip_char(port, rx, flg); 916 } 917 918 out: 919 spin_unlock_irqrestore(&sport->port.lock, flags); 920 921 tty_flip_buffer_push(port); 922 return IRQ_HANDLED; 923 } 924 925 static irqreturn_t lpuart_int(int irq, void *dev_id) 926 { 927 struct lpuart_port *sport = dev_id; 928 unsigned char sts; 929 930 sts = readb(sport->port.membase + UARTSR1); 931 932 if (sts & UARTSR1_RDRF) 933 lpuart_rxint(irq, dev_id); 934 935 if (sts & UARTSR1_TDRE) 936 lpuart_txint(irq, dev_id); 937 938 return IRQ_HANDLED; 939 } 940 941 static irqreturn_t lpuart32_int(int irq, void *dev_id) 942 { 943 struct lpuart_port *sport = dev_id; 944 unsigned long sts, rxcount; 945 946 sts = lpuart32_read(&sport->port, UARTSTAT); 947 rxcount = lpuart32_read(&sport->port, UARTWATER); 948 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 949 950 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) 951 lpuart32_rxint(irq, dev_id); 952 953 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) 954 lpuart_txint(irq, dev_id); 955 956 lpuart32_write(&sport->port, sts, UARTSTAT); 957 return IRQ_HANDLED; 958 } 959 960 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 961 { 962 struct tty_port *port = &sport->port.state->port; 963 struct dma_tx_state state; 964 enum dma_status dmastat; 965 struct circ_buf *ring = &sport->rx_ring; 966 unsigned long flags; 967 int count = 0; 968 969 if (lpuart_is_32(sport)) { 970 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); 971 972 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { 973 /* Read DR to clear the error flags */ 974 lpuart32_read(&sport->port, UARTDATA); 975 976 if (sr & UARTSTAT_PE) 977 sport->port.icount.parity++; 978 else if (sr & UARTSTAT_FE) 979 sport->port.icount.frame++; 980 } 981 } else { 982 unsigned char sr = readb(sport->port.membase + UARTSR1); 983 984 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 985 /* Read DR to clear the error flags */ 986 readb(sport->port.membase + UARTDR); 987 988 if (sr & UARTSR1_PE) 989 sport->port.icount.parity++; 990 else if (sr & UARTSR1_FE) 991 sport->port.icount.frame++; 992 } 993 } 994 995 async_tx_ack(sport->dma_rx_desc); 996 997 spin_lock_irqsave(&sport->port.lock, flags); 998 999 dmastat = dmaengine_tx_status(sport->dma_rx_chan, 1000 sport->dma_rx_cookie, 1001 &state); 1002 1003 if (dmastat == DMA_ERROR) { 1004 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1005 spin_unlock_irqrestore(&sport->port.lock, flags); 1006 return; 1007 } 1008 1009 /* CPU claims ownership of RX DMA buffer */ 1010 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1011 1012 /* 1013 * ring->head points to the end of data already written by the DMA. 1014 * ring->tail points to the beginning of data to be read by the 1015 * framework. 1016 * The current transfer size should not be larger than the dma buffer 1017 * length. 1018 */ 1019 ring->head = sport->rx_sgl.length - state.residue; 1020 BUG_ON(ring->head > sport->rx_sgl.length); 1021 /* 1022 * At this point ring->head may point to the first byte right after the 1023 * last byte of the dma buffer: 1024 * 0 <= ring->head <= sport->rx_sgl.length 1025 * 1026 * However ring->tail must always points inside the dma buffer: 1027 * 0 <= ring->tail <= sport->rx_sgl.length - 1 1028 * 1029 * Since we use a ring buffer, we have to handle the case 1030 * where head is lower than tail. In such a case, we first read from 1031 * tail to the end of the buffer then reset tail. 1032 */ 1033 if (ring->head < ring->tail) { 1034 count = sport->rx_sgl.length - ring->tail; 1035 1036 tty_insert_flip_string(port, ring->buf + ring->tail, count); 1037 ring->tail = 0; 1038 sport->port.icount.rx += count; 1039 } 1040 1041 /* Finally we read data from tail to head */ 1042 if (ring->tail < ring->head) { 1043 count = ring->head - ring->tail; 1044 tty_insert_flip_string(port, ring->buf + ring->tail, count); 1045 /* Wrap ring->head if needed */ 1046 if (ring->head >= sport->rx_sgl.length) 1047 ring->head = 0; 1048 ring->tail = ring->head; 1049 sport->port.icount.rx += count; 1050 } 1051 1052 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1, 1053 DMA_FROM_DEVICE); 1054 1055 spin_unlock_irqrestore(&sport->port.lock, flags); 1056 1057 tty_flip_buffer_push(port); 1058 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 1059 } 1060 1061 static void lpuart_dma_rx_complete(void *arg) 1062 { 1063 struct lpuart_port *sport = arg; 1064 1065 lpuart_copy_rx_to_tty(sport); 1066 } 1067 1068 static void lpuart_timer_func(struct timer_list *t) 1069 { 1070 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); 1071 1072 lpuart_copy_rx_to_tty(sport); 1073 } 1074 1075 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 1076 { 1077 struct dma_slave_config dma_rx_sconfig = {}; 1078 struct circ_buf *ring = &sport->rx_ring; 1079 int ret, nent; 1080 int bits, baud; 1081 struct tty_port *port = &sport->port.state->port; 1082 struct tty_struct *tty = port->tty; 1083 struct ktermios *termios = &tty->termios; 1084 1085 baud = tty_get_baud_rate(tty); 1086 1087 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; 1088 if (termios->c_cflag & PARENB) 1089 bits++; 1090 1091 /* 1092 * Calculate length of one DMA buffer size to keep latency below 1093 * 10ms at any baud rate. 1094 */ 1095 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 1096 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 1097 if (sport->rx_dma_rng_buf_len < 16) 1098 sport->rx_dma_rng_buf_len = 16; 1099 1100 ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1101 if (!ring->buf) 1102 return -ENOMEM; 1103 1104 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1105 sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1106 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1107 1108 if (!nent) { 1109 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1110 return -EINVAL; 1111 } 1112 1113 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); 1114 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1115 dma_rx_sconfig.src_maxburst = 1; 1116 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1117 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig); 1118 1119 if (ret < 0) { 1120 dev_err(sport->port.dev, 1121 "DMA Rx slave config failed, err = %d\n", ret); 1122 return ret; 1123 } 1124 1125 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan, 1126 sg_dma_address(&sport->rx_sgl), 1127 sport->rx_sgl.length, 1128 sport->rx_sgl.length / 2, 1129 DMA_DEV_TO_MEM, 1130 DMA_PREP_INTERRUPT); 1131 if (!sport->dma_rx_desc) { 1132 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1133 return -EFAULT; 1134 } 1135 1136 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1137 sport->dma_rx_desc->callback_param = sport; 1138 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1139 dma_async_issue_pending(sport->dma_rx_chan); 1140 1141 if (lpuart_is_32(sport)) { 1142 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); 1143 1144 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); 1145 } else { 1146 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1147 sport->port.membase + UARTCR5); 1148 } 1149 1150 return 0; 1151 } 1152 1153 static void lpuart_dma_rx_free(struct uart_port *port) 1154 { 1155 struct lpuart_port *sport = container_of(port, 1156 struct lpuart_port, port); 1157 1158 if (sport->dma_rx_chan) 1159 dmaengine_terminate_all(sport->dma_rx_chan); 1160 1161 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1162 kfree(sport->rx_ring.buf); 1163 sport->rx_ring.tail = 0; 1164 sport->rx_ring.head = 0; 1165 sport->dma_rx_desc = NULL; 1166 sport->dma_rx_cookie = -EINVAL; 1167 } 1168 1169 static int lpuart_config_rs485(struct uart_port *port, 1170 struct serial_rs485 *rs485) 1171 { 1172 struct lpuart_port *sport = container_of(port, 1173 struct lpuart_port, port); 1174 1175 u8 modem = readb(sport->port.membase + UARTMODEM) & 1176 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1177 writeb(modem, sport->port.membase + UARTMODEM); 1178 1179 /* clear unsupported configurations */ 1180 rs485->delay_rts_before_send = 0; 1181 rs485->delay_rts_after_send = 0; 1182 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1183 1184 if (rs485->flags & SER_RS485_ENABLED) { 1185 /* Enable auto RS-485 RTS mode */ 1186 modem |= UARTMODEM_TXRTSE; 1187 1188 /* 1189 * RTS needs to be logic HIGH either during transer _or_ after 1190 * transfer, other variants are not supported by the hardware. 1191 */ 1192 1193 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1194 SER_RS485_RTS_AFTER_SEND))) 1195 rs485->flags |= SER_RS485_RTS_ON_SEND; 1196 1197 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1198 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1199 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1200 1201 /* 1202 * The hardware defaults to RTS logic HIGH while transfer. 1203 * Switch polarity in case RTS shall be logic HIGH 1204 * after transfer. 1205 * Note: UART is assumed to be active high. 1206 */ 1207 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1208 modem &= ~UARTMODEM_TXRTSPOL; 1209 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1210 modem |= UARTMODEM_TXRTSPOL; 1211 } 1212 1213 /* Store the new configuration */ 1214 sport->port.rs485 = *rs485; 1215 1216 writeb(modem, sport->port.membase + UARTMODEM); 1217 return 0; 1218 } 1219 1220 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1221 { 1222 unsigned int temp = 0; 1223 unsigned char reg; 1224 1225 reg = readb(port->membase + UARTMODEM); 1226 if (reg & UARTMODEM_TXCTSE) 1227 temp |= TIOCM_CTS; 1228 1229 if (reg & UARTMODEM_RXRTSE) 1230 temp |= TIOCM_RTS; 1231 1232 return temp; 1233 } 1234 1235 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1236 { 1237 unsigned int temp = 0; 1238 unsigned long reg; 1239 1240 reg = lpuart32_read(port, UARTMODIR); 1241 if (reg & UARTMODIR_TXCTSE) 1242 temp |= TIOCM_CTS; 1243 1244 if (reg & UARTMODIR_RXRTSE) 1245 temp |= TIOCM_RTS; 1246 1247 return temp; 1248 } 1249 1250 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1251 { 1252 unsigned char temp; 1253 struct lpuart_port *sport = container_of(port, 1254 struct lpuart_port, port); 1255 1256 /* Make sure RXRTSE bit is not set when RS485 is enabled */ 1257 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { 1258 temp = readb(sport->port.membase + UARTMODEM) & 1259 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1260 1261 if (mctrl & TIOCM_RTS) 1262 temp |= UARTMODEM_RXRTSE; 1263 1264 if (mctrl & TIOCM_CTS) 1265 temp |= UARTMODEM_TXCTSE; 1266 1267 writeb(temp, port->membase + UARTMODEM); 1268 } 1269 } 1270 1271 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1272 { 1273 unsigned long temp; 1274 1275 temp = lpuart32_read(port, UARTMODIR) & 1276 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 1277 1278 if (mctrl & TIOCM_RTS) 1279 temp |= UARTMODIR_RXRTSE; 1280 1281 if (mctrl & TIOCM_CTS) 1282 temp |= UARTMODIR_TXCTSE; 1283 1284 lpuart32_write(port, temp, UARTMODIR); 1285 } 1286 1287 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1288 { 1289 unsigned char temp; 1290 1291 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1292 1293 if (break_state != 0) 1294 temp |= UARTCR2_SBK; 1295 1296 writeb(temp, port->membase + UARTCR2); 1297 } 1298 1299 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1300 { 1301 unsigned long temp; 1302 1303 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; 1304 1305 if (break_state != 0) 1306 temp |= UARTCTRL_SBK; 1307 1308 lpuart32_write(port, temp, UARTCTRL); 1309 } 1310 1311 static void lpuart_setup_watermark(struct lpuart_port *sport) 1312 { 1313 unsigned char val, cr2; 1314 unsigned char cr2_saved; 1315 1316 cr2 = readb(sport->port.membase + UARTCR2); 1317 cr2_saved = cr2; 1318 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1319 UARTCR2_RIE | UARTCR2_RE); 1320 writeb(cr2, sport->port.membase + UARTCR2); 1321 1322 val = readb(sport->port.membase + UARTPFIFO); 1323 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1324 sport->port.membase + UARTPFIFO); 1325 1326 /* flush Tx and Rx FIFO */ 1327 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1328 sport->port.membase + UARTCFIFO); 1329 1330 /* explicitly clear RDRF */ 1331 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1332 readb(sport->port.membase + UARTDR); 1333 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1334 } 1335 1336 writeb(0, sport->port.membase + UARTTWFIFO); 1337 writeb(1, sport->port.membase + UARTRWFIFO); 1338 1339 /* Restore cr2 */ 1340 writeb(cr2_saved, sport->port.membase + UARTCR2); 1341 } 1342 1343 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1344 { 1345 unsigned long val, ctrl; 1346 unsigned long ctrl_saved; 1347 1348 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1349 ctrl_saved = ctrl; 1350 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1351 UARTCTRL_RIE | UARTCTRL_RE); 1352 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1353 1354 /* enable FIFO mode */ 1355 val = lpuart32_read(&sport->port, UARTFIFO); 1356 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1357 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1358 lpuart32_write(&sport->port, val, UARTFIFO); 1359 1360 /* set the watermark */ 1361 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1362 lpuart32_write(&sport->port, val, UARTWATER); 1363 1364 /* Restore cr2 */ 1365 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1366 } 1367 1368 static void rx_dma_timer_init(struct lpuart_port *sport) 1369 { 1370 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); 1371 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1372 add_timer(&sport->lpuart_timer); 1373 } 1374 1375 static int lpuart_startup(struct uart_port *port) 1376 { 1377 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1378 unsigned long flags; 1379 unsigned char temp; 1380 1381 /* determine FIFO size and enable FIFO mode */ 1382 temp = readb(sport->port.membase + UARTPFIFO); 1383 1384 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) & 1385 UARTPFIFO_FIFOSIZE_MASK) + 1); 1386 1387 sport->port.fifosize = sport->txfifo_size; 1388 1389 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) & 1390 UARTPFIFO_FIFOSIZE_MASK) + 1); 1391 1392 spin_lock_irqsave(&sport->port.lock, flags); 1393 1394 lpuart_setup_watermark(sport); 1395 1396 temp = readb(sport->port.membase + UARTCR2); 1397 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 1398 writeb(temp, sport->port.membase + UARTCR2); 1399 1400 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) { 1401 /* set Rx DMA timeout */ 1402 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1403 if (!sport->dma_rx_timeout) 1404 sport->dma_rx_timeout = 1; 1405 1406 sport->lpuart_dma_rx_use = true; 1407 rx_dma_timer_init(sport); 1408 } else { 1409 sport->lpuart_dma_rx_use = false; 1410 } 1411 1412 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) { 1413 init_waitqueue_head(&sport->dma_wait); 1414 sport->lpuart_dma_tx_use = true; 1415 temp = readb(port->membase + UARTCR5); 1416 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5); 1417 } else { 1418 sport->lpuart_dma_tx_use = false; 1419 } 1420 1421 spin_unlock_irqrestore(&sport->port.lock, flags); 1422 1423 return 0; 1424 } 1425 1426 static int lpuart32_startup(struct uart_port *port) 1427 { 1428 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1429 unsigned long flags; 1430 unsigned long temp; 1431 1432 /* determine FIFO size */ 1433 temp = lpuart32_read(&sport->port, UARTFIFO); 1434 1435 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) & 1436 UARTFIFO_FIFOSIZE_MASK) - 1); 1437 1438 sport->port.fifosize = sport->txfifo_size; 1439 1440 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) & 1441 UARTFIFO_FIFOSIZE_MASK) - 1); 1442 1443 spin_lock_irqsave(&sport->port.lock, flags); 1444 1445 lpuart32_setup_watermark(sport); 1446 1447 temp = lpuart32_read(&sport->port, UARTCTRL); 1448 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE; 1449 lpuart32_write(&sport->port, temp, UARTCTRL); 1450 1451 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) { 1452 /* set Rx DMA timeout */ 1453 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1454 if (!sport->dma_rx_timeout) 1455 sport->dma_rx_timeout = 1; 1456 1457 sport->lpuart_dma_rx_use = true; 1458 rx_dma_timer_init(sport); 1459 } else { 1460 sport->lpuart_dma_rx_use = false; 1461 } 1462 1463 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) { 1464 init_waitqueue_head(&sport->dma_wait); 1465 sport->lpuart_dma_tx_use = true; 1466 temp = lpuart32_read(&sport->port, UARTBAUD); 1467 lpuart32_write(&sport->port, temp | UARTBAUD_TDMAE, UARTBAUD); 1468 } else { 1469 sport->lpuart_dma_tx_use = false; 1470 } 1471 1472 if (sport->lpuart_dma_rx_use) { 1473 /* RXWATER must be 0 */ 1474 temp = lpuart32_read(&sport->port, UARTWATER); 1475 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF); 1476 lpuart32_write(&sport->port, temp, UARTWATER); 1477 } 1478 temp = lpuart32_read(&sport->port, UARTCTRL); 1479 if (!sport->lpuart_dma_rx_use) 1480 temp |= UARTCTRL_RIE; 1481 if (!sport->lpuart_dma_tx_use) 1482 temp |= UARTCTRL_TIE; 1483 lpuart32_write(&sport->port, temp, UARTCTRL); 1484 1485 spin_unlock_irqrestore(&sport->port.lock, flags); 1486 return 0; 1487 } 1488 1489 static void lpuart_shutdown(struct uart_port *port) 1490 { 1491 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1492 unsigned char temp; 1493 unsigned long flags; 1494 1495 spin_lock_irqsave(&port->lock, flags); 1496 1497 /* disable Rx/Tx and interrupts */ 1498 temp = readb(port->membase + UARTCR2); 1499 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1500 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1501 writeb(temp, port->membase + UARTCR2); 1502 1503 spin_unlock_irqrestore(&port->lock, flags); 1504 1505 if (sport->lpuart_dma_rx_use) { 1506 del_timer_sync(&sport->lpuart_timer); 1507 lpuart_dma_rx_free(&sport->port); 1508 } 1509 1510 if (sport->lpuart_dma_tx_use) { 1511 if (wait_event_interruptible(sport->dma_wait, 1512 !sport->dma_tx_in_progress) != false) { 1513 sport->dma_tx_in_progress = false; 1514 dmaengine_terminate_all(sport->dma_tx_chan); 1515 } 1516 1517 lpuart_stop_tx(port); 1518 } 1519 } 1520 1521 static void lpuart32_shutdown(struct uart_port *port) 1522 { 1523 struct lpuart_port *sport = 1524 container_of(port, struct lpuart_port, port); 1525 unsigned long temp; 1526 unsigned long flags; 1527 1528 spin_lock_irqsave(&port->lock, flags); 1529 1530 /* disable Rx/Tx and interrupts */ 1531 temp = lpuart32_read(port, UARTCTRL); 1532 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1533 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1534 lpuart32_write(port, temp, UARTCTRL); 1535 1536 spin_unlock_irqrestore(&port->lock, flags); 1537 1538 if (sport->lpuart_dma_rx_use) { 1539 del_timer_sync(&sport->lpuart_timer); 1540 lpuart_dma_rx_free(&sport->port); 1541 } 1542 1543 if (sport->lpuart_dma_tx_use) { 1544 if (wait_event_interruptible(sport->dma_wait, 1545 !sport->dma_tx_in_progress)) { 1546 sport->dma_tx_in_progress = false; 1547 dmaengine_terminate_all(sport->dma_tx_chan); 1548 } 1549 1550 lpuart32_stop_tx(port); 1551 } 1552 } 1553 1554 static void 1555 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1556 struct ktermios *old) 1557 { 1558 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1559 unsigned long flags; 1560 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1561 unsigned int baud; 1562 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1563 unsigned int sbr, brfa; 1564 1565 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1566 old_cr2 = readb(sport->port.membase + UARTCR2); 1567 cr3 = readb(sport->port.membase + UARTCR3); 1568 cr4 = readb(sport->port.membase + UARTCR4); 1569 bdh = readb(sport->port.membase + UARTBDH); 1570 modem = readb(sport->port.membase + UARTMODEM); 1571 /* 1572 * only support CS8 and CS7, and for CS7 must enable PE. 1573 * supported mode: 1574 * - (7,e/o,1) 1575 * - (8,n,1) 1576 * - (8,m/s,1) 1577 * - (8,e/o,1) 1578 */ 1579 while ((termios->c_cflag & CSIZE) != CS8 && 1580 (termios->c_cflag & CSIZE) != CS7) { 1581 termios->c_cflag &= ~CSIZE; 1582 termios->c_cflag |= old_csize; 1583 old_csize = CS8; 1584 } 1585 1586 if ((termios->c_cflag & CSIZE) == CS8 || 1587 (termios->c_cflag & CSIZE) == CS7) 1588 cr1 = old_cr1 & ~UARTCR1_M; 1589 1590 if (termios->c_cflag & CMSPAR) { 1591 if ((termios->c_cflag & CSIZE) != CS8) { 1592 termios->c_cflag &= ~CSIZE; 1593 termios->c_cflag |= CS8; 1594 } 1595 cr1 |= UARTCR1_M; 1596 } 1597 1598 /* 1599 * When auto RS-485 RTS mode is enabled, 1600 * hardware flow control need to be disabled. 1601 */ 1602 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1603 termios->c_cflag &= ~CRTSCTS; 1604 1605 if (termios->c_cflag & CRTSCTS) { 1606 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1607 } else { 1608 termios->c_cflag &= ~CRTSCTS; 1609 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1610 } 1611 1612 if (termios->c_cflag & CSTOPB) 1613 termios->c_cflag &= ~CSTOPB; 1614 1615 /* parity must be enabled when CS7 to match 8-bits format */ 1616 if ((termios->c_cflag & CSIZE) == CS7) 1617 termios->c_cflag |= PARENB; 1618 1619 if ((termios->c_cflag & PARENB)) { 1620 if (termios->c_cflag & CMSPAR) { 1621 cr1 &= ~UARTCR1_PE; 1622 if (termios->c_cflag & PARODD) 1623 cr3 |= UARTCR3_T8; 1624 else 1625 cr3 &= ~UARTCR3_T8; 1626 } else { 1627 cr1 |= UARTCR1_PE; 1628 if ((termios->c_cflag & CSIZE) == CS8) 1629 cr1 |= UARTCR1_M; 1630 if (termios->c_cflag & PARODD) 1631 cr1 |= UARTCR1_PT; 1632 else 1633 cr1 &= ~UARTCR1_PT; 1634 } 1635 } else { 1636 cr1 &= ~UARTCR1_PE; 1637 } 1638 1639 /* ask the core to calculate the divisor */ 1640 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1641 1642 /* 1643 * Need to update the Ring buffer length according to the selected 1644 * baud rate and restart Rx DMA path. 1645 * 1646 * Since timer function acqures sport->port.lock, need to stop before 1647 * acquring same lock because otherwise del_timer_sync() can deadlock. 1648 */ 1649 if (old && sport->lpuart_dma_rx_use) { 1650 del_timer_sync(&sport->lpuart_timer); 1651 lpuart_dma_rx_free(&sport->port); 1652 } 1653 1654 spin_lock_irqsave(&sport->port.lock, flags); 1655 1656 sport->port.read_status_mask = 0; 1657 if (termios->c_iflag & INPCK) 1658 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE); 1659 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1660 sport->port.read_status_mask |= UARTSR1_FE; 1661 1662 /* characters to ignore */ 1663 sport->port.ignore_status_mask = 0; 1664 if (termios->c_iflag & IGNPAR) 1665 sport->port.ignore_status_mask |= UARTSR1_PE; 1666 if (termios->c_iflag & IGNBRK) { 1667 sport->port.ignore_status_mask |= UARTSR1_FE; 1668 /* 1669 * if we're ignoring parity and break indicators, 1670 * ignore overruns too (for real raw support). 1671 */ 1672 if (termios->c_iflag & IGNPAR) 1673 sport->port.ignore_status_mask |= UARTSR1_OR; 1674 } 1675 1676 /* update the per-port timeout */ 1677 uart_update_timeout(port, termios->c_cflag, baud); 1678 1679 /* wait transmit engin complete */ 1680 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1681 barrier(); 1682 1683 /* disable transmit and receive */ 1684 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1685 sport->port.membase + UARTCR2); 1686 1687 sbr = sport->port.uartclk / (16 * baud); 1688 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1689 bdh &= ~UARTBDH_SBR_MASK; 1690 bdh |= (sbr >> 8) & 0x1F; 1691 cr4 &= ~UARTCR4_BRFA_MASK; 1692 brfa &= UARTCR4_BRFA_MASK; 1693 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1694 writeb(bdh, sport->port.membase + UARTBDH); 1695 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1696 writeb(cr3, sport->port.membase + UARTCR3); 1697 writeb(cr1, sport->port.membase + UARTCR1); 1698 writeb(modem, sport->port.membase + UARTMODEM); 1699 1700 /* restore control register */ 1701 writeb(old_cr2, sport->port.membase + UARTCR2); 1702 1703 if (old && sport->lpuart_dma_rx_use) { 1704 if (!lpuart_start_rx_dma(sport)) 1705 rx_dma_timer_init(sport); 1706 else 1707 sport->lpuart_dma_rx_use = false; 1708 } 1709 1710 spin_unlock_irqrestore(&sport->port.lock, flags); 1711 } 1712 1713 static void 1714 lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate) 1715 { 1716 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; 1717 u32 clk = sport->port.uartclk; 1718 1719 /* 1720 * The idea is to use the best OSR (over-sampling rate) possible. 1721 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 1722 * Loop to find the best OSR value possible, one that generates minimum 1723 * baud_diff iterate through the rest of the supported values of OSR. 1724 * 1725 * Calculation Formula: 1726 * Baud Rate = baud clock / ((OSR+1) × SBR) 1727 */ 1728 baud_diff = baudrate; 1729 osr = 0; 1730 sbr = 0; 1731 1732 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 1733 /* calculate the temporary sbr value */ 1734 tmp_sbr = (clk / (baudrate * tmp_osr)); 1735 if (tmp_sbr == 0) 1736 tmp_sbr = 1; 1737 1738 /* 1739 * calculate the baud rate difference based on the temporary 1740 * osr and sbr values 1741 */ 1742 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 1743 1744 /* select best values between sbr and sbr+1 */ 1745 tmp = clk / (tmp_osr * (tmp_sbr + 1)); 1746 if (tmp_diff > (baudrate - tmp)) { 1747 tmp_diff = baudrate - tmp; 1748 tmp_sbr++; 1749 } 1750 1751 if (tmp_diff <= baud_diff) { 1752 baud_diff = tmp_diff; 1753 osr = tmp_osr; 1754 sbr = tmp_sbr; 1755 1756 if (!baud_diff) 1757 break; 1758 } 1759 } 1760 1761 /* handle buadrate outside acceptable rate */ 1762 if (baud_diff > ((baudrate / 100) * 3)) 1763 dev_warn(sport->port.dev, 1764 "unacceptable baud rate difference of more than 3%%\n"); 1765 1766 tmp = lpuart32_read(&sport->port, UARTBAUD); 1767 1768 if ((osr > 3) && (osr < 8)) 1769 tmp |= UARTBAUD_BOTHEDGE; 1770 1771 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 1772 tmp |= (((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT); 1773 1774 tmp &= ~UARTBAUD_SBR_MASK; 1775 tmp |= sbr & UARTBAUD_SBR_MASK; 1776 1777 if (!sport->lpuart_dma_rx_use) 1778 tmp &= ~UARTBAUD_RDMAE; 1779 if (!sport->lpuart_dma_tx_use) 1780 tmp &= ~UARTBAUD_TDMAE; 1781 1782 lpuart32_write(&sport->port, tmp, UARTBAUD); 1783 } 1784 1785 static void 1786 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 1787 struct ktermios *old) 1788 { 1789 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1790 unsigned long flags; 1791 unsigned long ctrl, old_ctrl, modem; 1792 unsigned int baud; 1793 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1794 1795 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); 1796 modem = lpuart32_read(&sport->port, UARTMODIR); 1797 /* 1798 * only support CS8 and CS7, and for CS7 must enable PE. 1799 * supported mode: 1800 * - (7,e/o,1) 1801 * - (8,n,1) 1802 * - (8,m/s,1) 1803 * - (8,e/o,1) 1804 */ 1805 while ((termios->c_cflag & CSIZE) != CS8 && 1806 (termios->c_cflag & CSIZE) != CS7) { 1807 termios->c_cflag &= ~CSIZE; 1808 termios->c_cflag |= old_csize; 1809 old_csize = CS8; 1810 } 1811 1812 if ((termios->c_cflag & CSIZE) == CS8 || 1813 (termios->c_cflag & CSIZE) == CS7) 1814 ctrl = old_ctrl & ~UARTCTRL_M; 1815 1816 if (termios->c_cflag & CMSPAR) { 1817 if ((termios->c_cflag & CSIZE) != CS8) { 1818 termios->c_cflag &= ~CSIZE; 1819 termios->c_cflag |= CS8; 1820 } 1821 ctrl |= UARTCTRL_M; 1822 } 1823 1824 if (termios->c_cflag & CRTSCTS) { 1825 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1826 } else { 1827 termios->c_cflag &= ~CRTSCTS; 1828 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1829 } 1830 1831 if (termios->c_cflag & CSTOPB) 1832 termios->c_cflag &= ~CSTOPB; 1833 1834 /* parity must be enabled when CS7 to match 8-bits format */ 1835 if ((termios->c_cflag & CSIZE) == CS7) 1836 termios->c_cflag |= PARENB; 1837 1838 if ((termios->c_cflag & PARENB)) { 1839 if (termios->c_cflag & CMSPAR) { 1840 ctrl &= ~UARTCTRL_PE; 1841 ctrl |= UARTCTRL_M; 1842 } else { 1843 ctrl |= UARTCTRL_PE; 1844 if ((termios->c_cflag & CSIZE) == CS8) 1845 ctrl |= UARTCTRL_M; 1846 if (termios->c_cflag & PARODD) 1847 ctrl |= UARTCTRL_PT; 1848 else 1849 ctrl &= ~UARTCTRL_PT; 1850 } 1851 } else { 1852 ctrl &= ~UARTCTRL_PE; 1853 } 1854 1855 /* ask the core to calculate the divisor */ 1856 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); 1857 1858 /* 1859 * Need to update the Ring buffer length according to the selected 1860 * baud rate and restart Rx DMA path. 1861 * 1862 * Since timer function acqures sport->port.lock, need to stop before 1863 * acquring same lock because otherwise del_timer_sync() can deadlock. 1864 */ 1865 if (old && sport->lpuart_dma_rx_use) { 1866 del_timer_sync(&sport->lpuart_timer); 1867 lpuart_dma_rx_free(&sport->port); 1868 } 1869 1870 spin_lock_irqsave(&sport->port.lock, flags); 1871 1872 sport->port.read_status_mask = 0; 1873 if (termios->c_iflag & INPCK) 1874 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE); 1875 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1876 sport->port.read_status_mask |= UARTSTAT_FE; 1877 1878 /* characters to ignore */ 1879 sport->port.ignore_status_mask = 0; 1880 if (termios->c_iflag & IGNPAR) 1881 sport->port.ignore_status_mask |= UARTSTAT_PE; 1882 if (termios->c_iflag & IGNBRK) { 1883 sport->port.ignore_status_mask |= UARTSTAT_FE; 1884 /* 1885 * if we're ignoring parity and break indicators, 1886 * ignore overruns too (for real raw support). 1887 */ 1888 if (termios->c_iflag & IGNPAR) 1889 sport->port.ignore_status_mask |= UARTSTAT_OR; 1890 } 1891 1892 /* update the per-port timeout */ 1893 uart_update_timeout(port, termios->c_cflag, baud); 1894 1895 /* wait transmit engin complete */ 1896 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC)) 1897 barrier(); 1898 1899 /* disable transmit and receive */ 1900 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 1901 UARTCTRL); 1902 1903 lpuart32_serial_setbrg(sport, baud); 1904 lpuart32_write(&sport->port, modem, UARTMODIR); 1905 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1906 /* restore control register */ 1907 1908 if (old && sport->lpuart_dma_rx_use) { 1909 if (!lpuart_start_rx_dma(sport)) 1910 rx_dma_timer_init(sport); 1911 else 1912 sport->lpuart_dma_rx_use = false; 1913 } 1914 1915 spin_unlock_irqrestore(&sport->port.lock, flags); 1916 } 1917 1918 static const char *lpuart_type(struct uart_port *port) 1919 { 1920 return "FSL_LPUART"; 1921 } 1922 1923 static void lpuart_release_port(struct uart_port *port) 1924 { 1925 /* nothing to do */ 1926 } 1927 1928 static int lpuart_request_port(struct uart_port *port) 1929 { 1930 return 0; 1931 } 1932 1933 /* configure/autoconfigure the port */ 1934 static void lpuart_config_port(struct uart_port *port, int flags) 1935 { 1936 if (flags & UART_CONFIG_TYPE) 1937 port->type = PORT_LPUART; 1938 } 1939 1940 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 1941 { 1942 int ret = 0; 1943 1944 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 1945 ret = -EINVAL; 1946 if (port->irq != ser->irq) 1947 ret = -EINVAL; 1948 if (ser->io_type != UPIO_MEM) 1949 ret = -EINVAL; 1950 if (port->uartclk / 16 != ser->baud_base) 1951 ret = -EINVAL; 1952 if (port->iobase != ser->port) 1953 ret = -EINVAL; 1954 if (ser->hub6 != 0) 1955 ret = -EINVAL; 1956 return ret; 1957 } 1958 1959 static const struct uart_ops lpuart_pops = { 1960 .tx_empty = lpuart_tx_empty, 1961 .set_mctrl = lpuart_set_mctrl, 1962 .get_mctrl = lpuart_get_mctrl, 1963 .stop_tx = lpuart_stop_tx, 1964 .start_tx = lpuart_start_tx, 1965 .stop_rx = lpuart_stop_rx, 1966 .break_ctl = lpuart_break_ctl, 1967 .startup = lpuart_startup, 1968 .shutdown = lpuart_shutdown, 1969 .set_termios = lpuart_set_termios, 1970 .type = lpuart_type, 1971 .request_port = lpuart_request_port, 1972 .release_port = lpuart_release_port, 1973 .config_port = lpuart_config_port, 1974 .verify_port = lpuart_verify_port, 1975 .flush_buffer = lpuart_flush_buffer, 1976 #if defined(CONFIG_CONSOLE_POLL) 1977 .poll_init = lpuart_poll_init, 1978 .poll_get_char = lpuart_poll_get_char, 1979 .poll_put_char = lpuart_poll_put_char, 1980 #endif 1981 }; 1982 1983 static const struct uart_ops lpuart32_pops = { 1984 .tx_empty = lpuart32_tx_empty, 1985 .set_mctrl = lpuart32_set_mctrl, 1986 .get_mctrl = lpuart32_get_mctrl, 1987 .stop_tx = lpuart32_stop_tx, 1988 .start_tx = lpuart32_start_tx, 1989 .stop_rx = lpuart32_stop_rx, 1990 .break_ctl = lpuart32_break_ctl, 1991 .startup = lpuart32_startup, 1992 .shutdown = lpuart32_shutdown, 1993 .set_termios = lpuart32_set_termios, 1994 .type = lpuart_type, 1995 .request_port = lpuart_request_port, 1996 .release_port = lpuart_release_port, 1997 .config_port = lpuart_config_port, 1998 .verify_port = lpuart_verify_port, 1999 .flush_buffer = lpuart_flush_buffer, 2000 #if defined(CONFIG_CONSOLE_POLL) 2001 .poll_init = lpuart32_poll_init, 2002 .poll_get_char = lpuart32_poll_get_char, 2003 .poll_put_char = lpuart32_poll_put_char, 2004 #endif 2005 }; 2006 2007 static struct lpuart_port *lpuart_ports[UART_NR]; 2008 2009 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 2010 static void lpuart_console_putchar(struct uart_port *port, int ch) 2011 { 2012 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) 2013 barrier(); 2014 2015 writeb(ch, port->membase + UARTDR); 2016 } 2017 2018 static void lpuart32_console_putchar(struct uart_port *port, int ch) 2019 { 2020 while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)) 2021 barrier(); 2022 2023 lpuart32_write(port, ch, UARTDATA); 2024 } 2025 2026 static void 2027 lpuart_console_write(struct console *co, const char *s, unsigned int count) 2028 { 2029 struct lpuart_port *sport = lpuart_ports[co->index]; 2030 unsigned char old_cr2, cr2; 2031 unsigned long flags; 2032 int locked = 1; 2033 2034 if (sport->port.sysrq || oops_in_progress) 2035 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2036 else 2037 spin_lock_irqsave(&sport->port.lock, flags); 2038 2039 /* first save CR2 and then disable interrupts */ 2040 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 2041 cr2 |= (UARTCR2_TE | UARTCR2_RE); 2042 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 2043 writeb(cr2, sport->port.membase + UARTCR2); 2044 2045 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 2046 2047 /* wait for transmitter finish complete and restore CR2 */ 2048 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 2049 barrier(); 2050 2051 writeb(old_cr2, sport->port.membase + UARTCR2); 2052 2053 if (locked) 2054 spin_unlock_irqrestore(&sport->port.lock, flags); 2055 } 2056 2057 static void 2058 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 2059 { 2060 struct lpuart_port *sport = lpuart_ports[co->index]; 2061 unsigned long old_cr, cr; 2062 unsigned long flags; 2063 int locked = 1; 2064 2065 if (sport->port.sysrq || oops_in_progress) 2066 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2067 else 2068 spin_lock_irqsave(&sport->port.lock, flags); 2069 2070 /* first save CR2 and then disable interrupts */ 2071 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 2072 cr |= (UARTCTRL_TE | UARTCTRL_RE); 2073 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 2074 lpuart32_write(&sport->port, cr, UARTCTRL); 2075 2076 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 2077 2078 /* wait for transmitter finish complete and restore CR2 */ 2079 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC)) 2080 barrier(); 2081 2082 lpuart32_write(&sport->port, old_cr, UARTCTRL); 2083 2084 if (locked) 2085 spin_unlock_irqrestore(&sport->port.lock, flags); 2086 } 2087 2088 /* 2089 * if the port was already initialised (eg, by a boot loader), 2090 * try to determine the current setup. 2091 */ 2092 static void __init 2093 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 2094 int *parity, int *bits) 2095 { 2096 unsigned char cr, bdh, bdl, brfa; 2097 unsigned int sbr, uartclk, baud_raw; 2098 2099 cr = readb(sport->port.membase + UARTCR2); 2100 cr &= UARTCR2_TE | UARTCR2_RE; 2101 if (!cr) 2102 return; 2103 2104 /* ok, the port was enabled */ 2105 2106 cr = readb(sport->port.membase + UARTCR1); 2107 2108 *parity = 'n'; 2109 if (cr & UARTCR1_PE) { 2110 if (cr & UARTCR1_PT) 2111 *parity = 'o'; 2112 else 2113 *parity = 'e'; 2114 } 2115 2116 if (cr & UARTCR1_M) 2117 *bits = 9; 2118 else 2119 *bits = 8; 2120 2121 bdh = readb(sport->port.membase + UARTBDH); 2122 bdh &= UARTBDH_SBR_MASK; 2123 bdl = readb(sport->port.membase + UARTBDL); 2124 sbr = bdh; 2125 sbr <<= 8; 2126 sbr |= bdl; 2127 brfa = readb(sport->port.membase + UARTCR4); 2128 brfa &= UARTCR4_BRFA_MASK; 2129 2130 uartclk = lpuart_get_baud_clk_rate(sport); 2131 /* 2132 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2133 */ 2134 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 2135 2136 if (*baud != baud_raw) 2137 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2138 "from %d to %d\n", baud_raw, *baud); 2139 } 2140 2141 static void __init 2142 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 2143 int *parity, int *bits) 2144 { 2145 unsigned long cr, bd; 2146 unsigned int sbr, uartclk, baud_raw; 2147 2148 cr = lpuart32_read(&sport->port, UARTCTRL); 2149 cr &= UARTCTRL_TE | UARTCTRL_RE; 2150 if (!cr) 2151 return; 2152 2153 /* ok, the port was enabled */ 2154 2155 cr = lpuart32_read(&sport->port, UARTCTRL); 2156 2157 *parity = 'n'; 2158 if (cr & UARTCTRL_PE) { 2159 if (cr & UARTCTRL_PT) 2160 *parity = 'o'; 2161 else 2162 *parity = 'e'; 2163 } 2164 2165 if (cr & UARTCTRL_M) 2166 *bits = 9; 2167 else 2168 *bits = 8; 2169 2170 bd = lpuart32_read(&sport->port, UARTBAUD); 2171 bd &= UARTBAUD_SBR_MASK; 2172 sbr = bd; 2173 uartclk = lpuart_get_baud_clk_rate(sport); 2174 /* 2175 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2176 */ 2177 baud_raw = uartclk / (16 * sbr); 2178 2179 if (*baud != baud_raw) 2180 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2181 "from %d to %d\n", baud_raw, *baud); 2182 } 2183 2184 static int __init lpuart_console_setup(struct console *co, char *options) 2185 { 2186 struct lpuart_port *sport; 2187 int baud = 115200; 2188 int bits = 8; 2189 int parity = 'n'; 2190 int flow = 'n'; 2191 2192 /* 2193 * check whether an invalid uart number has been specified, and 2194 * if so, search for the first available port that does have 2195 * console support. 2196 */ 2197 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2198 co->index = 0; 2199 2200 sport = lpuart_ports[co->index]; 2201 if (sport == NULL) 2202 return -ENODEV; 2203 2204 if (options) 2205 uart_parse_options(options, &baud, &parity, &bits, &flow); 2206 else 2207 if (lpuart_is_32(sport)) 2208 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2209 else 2210 lpuart_console_get_options(sport, &baud, &parity, &bits); 2211 2212 if (lpuart_is_32(sport)) 2213 lpuart32_setup_watermark(sport); 2214 else 2215 lpuart_setup_watermark(sport); 2216 2217 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2218 } 2219 2220 static struct uart_driver lpuart_reg; 2221 static struct console lpuart_console = { 2222 .name = DEV_NAME, 2223 .write = lpuart_console_write, 2224 .device = uart_console_device, 2225 .setup = lpuart_console_setup, 2226 .flags = CON_PRINTBUFFER, 2227 .index = -1, 2228 .data = &lpuart_reg, 2229 }; 2230 2231 static struct console lpuart32_console = { 2232 .name = DEV_NAME, 2233 .write = lpuart32_console_write, 2234 .device = uart_console_device, 2235 .setup = lpuart_console_setup, 2236 .flags = CON_PRINTBUFFER, 2237 .index = -1, 2238 .data = &lpuart_reg, 2239 }; 2240 2241 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2242 { 2243 struct earlycon_device *dev = con->data; 2244 2245 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2246 } 2247 2248 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2249 { 2250 struct earlycon_device *dev = con->data; 2251 2252 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2253 } 2254 2255 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2256 const char *opt) 2257 { 2258 if (!device->port.membase) 2259 return -ENODEV; 2260 2261 device->con->write = lpuart_early_write; 2262 return 0; 2263 } 2264 2265 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2266 const char *opt) 2267 { 2268 if (!device->port.membase) 2269 return -ENODEV; 2270 2271 device->port.iotype = UPIO_MEM32BE; 2272 device->con->write = lpuart32_early_write; 2273 return 0; 2274 } 2275 2276 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2277 const char *opt) 2278 { 2279 if (!device->port.membase) 2280 return -ENODEV; 2281 2282 device->port.iotype = UPIO_MEM32; 2283 device->port.membase += IMX_REG_OFF; 2284 device->con->write = lpuart32_early_write; 2285 2286 return 0; 2287 } 2288 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2289 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2290 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2291 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2292 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2293 2294 #define LPUART_CONSOLE (&lpuart_console) 2295 #define LPUART32_CONSOLE (&lpuart32_console) 2296 #else 2297 #define LPUART_CONSOLE NULL 2298 #define LPUART32_CONSOLE NULL 2299 #endif 2300 2301 static struct uart_driver lpuart_reg = { 2302 .owner = THIS_MODULE, 2303 .driver_name = DRIVER_NAME, 2304 .dev_name = DEV_NAME, 2305 .nr = ARRAY_SIZE(lpuart_ports), 2306 .cons = LPUART_CONSOLE, 2307 }; 2308 2309 static int lpuart_probe(struct platform_device *pdev) 2310 { 2311 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids, 2312 &pdev->dev); 2313 const struct lpuart_soc_data *sdata = of_id->data; 2314 struct device_node *np = pdev->dev.of_node; 2315 struct lpuart_port *sport; 2316 struct resource *res; 2317 int ret; 2318 2319 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2320 if (!sport) 2321 return -ENOMEM; 2322 2323 pdev->dev.coherent_dma_mask = 0; 2324 2325 ret = of_alias_get_id(np, "serial"); 2326 if (ret < 0) { 2327 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL); 2328 if (ret < 0) { 2329 dev_err(&pdev->dev, "port line is full, add device failed\n"); 2330 return ret; 2331 } 2332 } 2333 if (ret >= ARRAY_SIZE(lpuart_ports)) { 2334 dev_err(&pdev->dev, "serial%d out of range\n", ret); 2335 return -EINVAL; 2336 } 2337 sport->port.line = ret; 2338 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2339 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 2340 if (IS_ERR(sport->port.membase)) 2341 return PTR_ERR(sport->port.membase); 2342 2343 sport->port.membase += sdata->reg_off; 2344 sport->port.mapbase = res->start; 2345 sport->port.dev = &pdev->dev; 2346 sport->port.type = PORT_LPUART; 2347 sport->devtype = sdata->devtype; 2348 ret = platform_get_irq(pdev, 0); 2349 if (ret < 0) { 2350 dev_err(&pdev->dev, "cannot obtain irq\n"); 2351 return ret; 2352 } 2353 sport->port.irq = ret; 2354 sport->port.iotype = sdata->iotype; 2355 if (lpuart_is_32(sport)) 2356 sport->port.ops = &lpuart32_pops; 2357 else 2358 sport->port.ops = &lpuart_pops; 2359 sport->port.flags = UPF_BOOT_AUTOCONF; 2360 2361 sport->port.rs485_config = lpuart_config_rs485; 2362 2363 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 2364 if (IS_ERR(sport->ipg_clk)) { 2365 ret = PTR_ERR(sport->ipg_clk); 2366 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); 2367 return ret; 2368 } 2369 2370 sport->baud_clk = NULL; 2371 if (is_imx8qxp_lpuart(sport)) { 2372 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); 2373 if (IS_ERR(sport->baud_clk)) { 2374 ret = PTR_ERR(sport->baud_clk); 2375 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); 2376 return ret; 2377 } 2378 } 2379 2380 ret = lpuart_enable_clks(sport); 2381 if (ret) 2382 return ret; 2383 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); 2384 2385 lpuart_ports[sport->port.line] = sport; 2386 2387 platform_set_drvdata(pdev, &sport->port); 2388 2389 if (lpuart_is_32(sport)) { 2390 lpuart_reg.cons = LPUART32_CONSOLE; 2391 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0, 2392 DRIVER_NAME, sport); 2393 } else { 2394 lpuart_reg.cons = LPUART_CONSOLE; 2395 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0, 2396 DRIVER_NAME, sport); 2397 } 2398 2399 if (ret) 2400 goto failed_irq_request; 2401 2402 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2403 if (ret) 2404 goto failed_attach_port; 2405 2406 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2407 2408 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX) 2409 dev_err(&pdev->dev, "driver doesn't support RX during TX\n"); 2410 2411 if (sport->port.rs485.delay_rts_before_send || 2412 sport->port.rs485.delay_rts_after_send) 2413 dev_err(&pdev->dev, "driver doesn't support RTS delays\n"); 2414 2415 lpuart_config_rs485(&sport->port, &sport->port.rs485); 2416 2417 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx"); 2418 if (!sport->dma_tx_chan) 2419 dev_info(sport->port.dev, "DMA tx channel request failed, " 2420 "operating without tx DMA\n"); 2421 2422 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx"); 2423 if (!sport->dma_rx_chan) 2424 dev_info(sport->port.dev, "DMA rx channel request failed, " 2425 "operating without rx DMA\n"); 2426 2427 return 0; 2428 2429 failed_attach_port: 2430 failed_irq_request: 2431 lpuart_disable_clks(sport); 2432 return ret; 2433 } 2434 2435 static int lpuart_remove(struct platform_device *pdev) 2436 { 2437 struct lpuart_port *sport = platform_get_drvdata(pdev); 2438 2439 uart_remove_one_port(&lpuart_reg, &sport->port); 2440 2441 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); 2442 2443 lpuart_disable_clks(sport); 2444 2445 if (sport->dma_tx_chan) 2446 dma_release_channel(sport->dma_tx_chan); 2447 2448 if (sport->dma_rx_chan) 2449 dma_release_channel(sport->dma_rx_chan); 2450 2451 return 0; 2452 } 2453 2454 #ifdef CONFIG_PM_SLEEP 2455 static int lpuart_suspend(struct device *dev) 2456 { 2457 struct lpuart_port *sport = dev_get_drvdata(dev); 2458 unsigned long temp; 2459 bool irq_wake; 2460 2461 if (lpuart_is_32(sport)) { 2462 /* disable Rx/Tx and interrupts */ 2463 temp = lpuart32_read(&sport->port, UARTCTRL); 2464 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2465 lpuart32_write(&sport->port, temp, UARTCTRL); 2466 } else { 2467 /* disable Rx/Tx and interrupts */ 2468 temp = readb(sport->port.membase + UARTCR2); 2469 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2470 writeb(temp, sport->port.membase + UARTCR2); 2471 } 2472 2473 uart_suspend_port(&lpuart_reg, &sport->port); 2474 2475 /* uart_suspend_port() might set wakeup flag */ 2476 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2477 2478 if (sport->lpuart_dma_rx_use) { 2479 /* 2480 * EDMA driver during suspend will forcefully release any 2481 * non-idle DMA channels. If port wakeup is enabled or if port 2482 * is console port or 'no_console_suspend' is set the Rx DMA 2483 * cannot resume as as expected, hence gracefully release the 2484 * Rx DMA path before suspend and start Rx DMA path on resume. 2485 */ 2486 if (irq_wake) { 2487 del_timer_sync(&sport->lpuart_timer); 2488 lpuart_dma_rx_free(&sport->port); 2489 } 2490 2491 /* Disable Rx DMA to use UART port as wakeup source */ 2492 if (lpuart_is_32(sport)) { 2493 temp = lpuart32_read(&sport->port, UARTBAUD); 2494 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, 2495 UARTBAUD); 2496 } else { 2497 writeb(readb(sport->port.membase + UARTCR5) & 2498 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 2499 } 2500 } 2501 2502 if (sport->lpuart_dma_tx_use) { 2503 sport->dma_tx_in_progress = false; 2504 dmaengine_terminate_all(sport->dma_tx_chan); 2505 } 2506 2507 if (sport->port.suspended && !irq_wake) 2508 lpuart_disable_clks(sport); 2509 2510 return 0; 2511 } 2512 2513 static int lpuart_resume(struct device *dev) 2514 { 2515 struct lpuart_port *sport = dev_get_drvdata(dev); 2516 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2517 unsigned long temp; 2518 2519 if (sport->port.suspended && !irq_wake) 2520 lpuart_enable_clks(sport); 2521 2522 if (lpuart_is_32(sport)) { 2523 lpuart32_setup_watermark(sport); 2524 temp = lpuart32_read(&sport->port, UARTCTRL); 2525 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE; 2526 lpuart32_write(&sport->port, temp, UARTCTRL); 2527 } else { 2528 lpuart_setup_watermark(sport); 2529 temp = readb(sport->port.membase + UARTCR2); 2530 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 2531 writeb(temp, sport->port.membase + UARTCR2); 2532 } 2533 2534 if (sport->lpuart_dma_rx_use) { 2535 if (irq_wake) { 2536 if (!lpuart_start_rx_dma(sport)) 2537 rx_dma_timer_init(sport); 2538 else 2539 sport->lpuart_dma_rx_use = false; 2540 } 2541 } 2542 2543 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) { 2544 init_waitqueue_head(&sport->dma_wait); 2545 sport->lpuart_dma_tx_use = true; 2546 if (lpuart_is_32(sport)) { 2547 temp = lpuart32_read(&sport->port, UARTBAUD); 2548 lpuart32_write(&sport->port, 2549 temp | UARTBAUD_TDMAE, UARTBAUD); 2550 } else { 2551 writeb(readb(sport->port.membase + UARTCR5) | 2552 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 2553 } 2554 } else { 2555 sport->lpuart_dma_tx_use = false; 2556 } 2557 2558 if (lpuart_is_32(sport)) { 2559 if (sport->lpuart_dma_rx_use) { 2560 /* RXWATER must be 0 */ 2561 temp = lpuart32_read(&sport->port, UARTWATER); 2562 temp &= ~(UARTWATER_WATER_MASK << 2563 UARTWATER_RXWATER_OFF); 2564 lpuart32_write(&sport->port, temp, UARTWATER); 2565 } 2566 temp = lpuart32_read(&sport->port, UARTCTRL); 2567 if (!sport->lpuart_dma_rx_use) 2568 temp |= UARTCTRL_RIE; 2569 if (!sport->lpuart_dma_tx_use) 2570 temp |= UARTCTRL_TIE; 2571 lpuart32_write(&sport->port, temp, UARTCTRL); 2572 } 2573 2574 uart_resume_port(&lpuart_reg, &sport->port); 2575 2576 return 0; 2577 } 2578 #endif 2579 2580 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2581 2582 static struct platform_driver lpuart_driver = { 2583 .probe = lpuart_probe, 2584 .remove = lpuart_remove, 2585 .driver = { 2586 .name = "fsl-lpuart", 2587 .of_match_table = lpuart_dt_ids, 2588 .pm = &lpuart_pm_ops, 2589 }, 2590 }; 2591 2592 static int __init lpuart_serial_init(void) 2593 { 2594 int ret = uart_register_driver(&lpuart_reg); 2595 2596 if (ret) 2597 return ret; 2598 2599 ret = platform_driver_register(&lpuart_driver); 2600 if (ret) 2601 uart_unregister_driver(&lpuart_reg); 2602 2603 return ret; 2604 } 2605 2606 static void __exit lpuart_serial_exit(void) 2607 { 2608 ida_destroy(&fsl_lpuart_ida); 2609 platform_driver_unregister(&lpuart_driver); 2610 uart_unregister_driver(&lpuart_reg); 2611 } 2612 2613 module_init(lpuart_serial_init); 2614 module_exit(lpuart_serial_exit); 2615 2616 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2617 MODULE_LICENSE("GPL v2"); 2618