1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale lpuart serial port driver 4 * 5 * Copyright 2012-2014 Freescale Semiconductor, Inc. 6 */ 7 8 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 9 #define SUPPORT_SYSRQ 10 #endif 11 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dmapool.h> 17 #include <linux/io.h> 18 #include <linux/irq.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/of_dma.h> 23 #include <linux/serial_core.h> 24 #include <linux/slab.h> 25 #include <linux/tty_flip.h> 26 27 /* All registers are 8-bit width */ 28 #define UARTBDH 0x00 29 #define UARTBDL 0x01 30 #define UARTCR1 0x02 31 #define UARTCR2 0x03 32 #define UARTSR1 0x04 33 #define UARTCR3 0x06 34 #define UARTDR 0x07 35 #define UARTCR4 0x0a 36 #define UARTCR5 0x0b 37 #define UARTMODEM 0x0d 38 #define UARTPFIFO 0x10 39 #define UARTCFIFO 0x11 40 #define UARTSFIFO 0x12 41 #define UARTTWFIFO 0x13 42 #define UARTTCFIFO 0x14 43 #define UARTRWFIFO 0x15 44 45 #define UARTBDH_LBKDIE 0x80 46 #define UARTBDH_RXEDGIE 0x40 47 #define UARTBDH_SBR_MASK 0x1f 48 49 #define UARTCR1_LOOPS 0x80 50 #define UARTCR1_RSRC 0x20 51 #define UARTCR1_M 0x10 52 #define UARTCR1_WAKE 0x08 53 #define UARTCR1_ILT 0x04 54 #define UARTCR1_PE 0x02 55 #define UARTCR1_PT 0x01 56 57 #define UARTCR2_TIE 0x80 58 #define UARTCR2_TCIE 0x40 59 #define UARTCR2_RIE 0x20 60 #define UARTCR2_ILIE 0x10 61 #define UARTCR2_TE 0x08 62 #define UARTCR2_RE 0x04 63 #define UARTCR2_RWU 0x02 64 #define UARTCR2_SBK 0x01 65 66 #define UARTSR1_TDRE 0x80 67 #define UARTSR1_TC 0x40 68 #define UARTSR1_RDRF 0x20 69 #define UARTSR1_IDLE 0x10 70 #define UARTSR1_OR 0x08 71 #define UARTSR1_NF 0x04 72 #define UARTSR1_FE 0x02 73 #define UARTSR1_PE 0x01 74 75 #define UARTCR3_R8 0x80 76 #define UARTCR3_T8 0x40 77 #define UARTCR3_TXDIR 0x20 78 #define UARTCR3_TXINV 0x10 79 #define UARTCR3_ORIE 0x08 80 #define UARTCR3_NEIE 0x04 81 #define UARTCR3_FEIE 0x02 82 #define UARTCR3_PEIE 0x01 83 84 #define UARTCR4_MAEN1 0x80 85 #define UARTCR4_MAEN2 0x40 86 #define UARTCR4_M10 0x20 87 #define UARTCR4_BRFA_MASK 0x1f 88 #define UARTCR4_BRFA_OFF 0 89 90 #define UARTCR5_TDMAS 0x80 91 #define UARTCR5_RDMAS 0x20 92 93 #define UARTMODEM_RXRTSE 0x08 94 #define UARTMODEM_TXRTSPOL 0x04 95 #define UARTMODEM_TXRTSE 0x02 96 #define UARTMODEM_TXCTSE 0x01 97 98 #define UARTPFIFO_TXFE 0x80 99 #define UARTPFIFO_FIFOSIZE_MASK 0x7 100 #define UARTPFIFO_TXSIZE_OFF 4 101 #define UARTPFIFO_RXFE 0x08 102 #define UARTPFIFO_RXSIZE_OFF 0 103 104 #define UARTCFIFO_TXFLUSH 0x80 105 #define UARTCFIFO_RXFLUSH 0x40 106 #define UARTCFIFO_RXOFE 0x04 107 #define UARTCFIFO_TXOFE 0x02 108 #define UARTCFIFO_RXUFE 0x01 109 110 #define UARTSFIFO_TXEMPT 0x80 111 #define UARTSFIFO_RXEMPT 0x40 112 #define UARTSFIFO_RXOF 0x04 113 #define UARTSFIFO_TXOF 0x02 114 #define UARTSFIFO_RXUF 0x01 115 116 /* 32-bit register definition */ 117 #define UARTBAUD 0x00 118 #define UARTSTAT 0x04 119 #define UARTCTRL 0x08 120 #define UARTDATA 0x0C 121 #define UARTMATCH 0x10 122 #define UARTMODIR 0x14 123 #define UARTFIFO 0x18 124 #define UARTWATER 0x1c 125 126 #define UARTBAUD_MAEN1 0x80000000 127 #define UARTBAUD_MAEN2 0x40000000 128 #define UARTBAUD_M10 0x20000000 129 #define UARTBAUD_TDMAE 0x00800000 130 #define UARTBAUD_RDMAE 0x00200000 131 #define UARTBAUD_MATCFG 0x00400000 132 #define UARTBAUD_BOTHEDGE 0x00020000 133 #define UARTBAUD_RESYNCDIS 0x00010000 134 #define UARTBAUD_LBKDIE 0x00008000 135 #define UARTBAUD_RXEDGIE 0x00004000 136 #define UARTBAUD_SBNS 0x00002000 137 #define UARTBAUD_SBR 0x00000000 138 #define UARTBAUD_SBR_MASK 0x1fff 139 #define UARTBAUD_OSR_MASK 0x1f 140 #define UARTBAUD_OSR_SHIFT 24 141 142 #define UARTSTAT_LBKDIF 0x80000000 143 #define UARTSTAT_RXEDGIF 0x40000000 144 #define UARTSTAT_MSBF 0x20000000 145 #define UARTSTAT_RXINV 0x10000000 146 #define UARTSTAT_RWUID 0x08000000 147 #define UARTSTAT_BRK13 0x04000000 148 #define UARTSTAT_LBKDE 0x02000000 149 #define UARTSTAT_RAF 0x01000000 150 #define UARTSTAT_TDRE 0x00800000 151 #define UARTSTAT_TC 0x00400000 152 #define UARTSTAT_RDRF 0x00200000 153 #define UARTSTAT_IDLE 0x00100000 154 #define UARTSTAT_OR 0x00080000 155 #define UARTSTAT_NF 0x00040000 156 #define UARTSTAT_FE 0x00020000 157 #define UARTSTAT_PE 0x00010000 158 #define UARTSTAT_MA1F 0x00008000 159 #define UARTSTAT_M21F 0x00004000 160 161 #define UARTCTRL_R8T9 0x80000000 162 #define UARTCTRL_R9T8 0x40000000 163 #define UARTCTRL_TXDIR 0x20000000 164 #define UARTCTRL_TXINV 0x10000000 165 #define UARTCTRL_ORIE 0x08000000 166 #define UARTCTRL_NEIE 0x04000000 167 #define UARTCTRL_FEIE 0x02000000 168 #define UARTCTRL_PEIE 0x01000000 169 #define UARTCTRL_TIE 0x00800000 170 #define UARTCTRL_TCIE 0x00400000 171 #define UARTCTRL_RIE 0x00200000 172 #define UARTCTRL_ILIE 0x00100000 173 #define UARTCTRL_TE 0x00080000 174 #define UARTCTRL_RE 0x00040000 175 #define UARTCTRL_RWU 0x00020000 176 #define UARTCTRL_SBK 0x00010000 177 #define UARTCTRL_MA1IE 0x00008000 178 #define UARTCTRL_MA2IE 0x00004000 179 #define UARTCTRL_IDLECFG 0x00000100 180 #define UARTCTRL_LOOPS 0x00000080 181 #define UARTCTRL_DOZEEN 0x00000040 182 #define UARTCTRL_RSRC 0x00000020 183 #define UARTCTRL_M 0x00000010 184 #define UARTCTRL_WAKE 0x00000008 185 #define UARTCTRL_ILT 0x00000004 186 #define UARTCTRL_PE 0x00000002 187 #define UARTCTRL_PT 0x00000001 188 189 #define UARTDATA_NOISY 0x00008000 190 #define UARTDATA_PARITYE 0x00004000 191 #define UARTDATA_FRETSC 0x00002000 192 #define UARTDATA_RXEMPT 0x00001000 193 #define UARTDATA_IDLINE 0x00000800 194 #define UARTDATA_MASK 0x3ff 195 196 #define UARTMODIR_IREN 0x00020000 197 #define UARTMODIR_TXCTSSRC 0x00000020 198 #define UARTMODIR_TXCTSC 0x00000010 199 #define UARTMODIR_RXRTSE 0x00000008 200 #define UARTMODIR_TXRTSPOL 0x00000004 201 #define UARTMODIR_TXRTSE 0x00000002 202 #define UARTMODIR_TXCTSE 0x00000001 203 204 #define UARTFIFO_TXEMPT 0x00800000 205 #define UARTFIFO_RXEMPT 0x00400000 206 #define UARTFIFO_TXOF 0x00020000 207 #define UARTFIFO_RXUF 0x00010000 208 #define UARTFIFO_TXFLUSH 0x00008000 209 #define UARTFIFO_RXFLUSH 0x00004000 210 #define UARTFIFO_TXOFE 0x00000200 211 #define UARTFIFO_RXUFE 0x00000100 212 #define UARTFIFO_TXFE 0x00000080 213 #define UARTFIFO_FIFOSIZE_MASK 0x7 214 #define UARTFIFO_TXSIZE_OFF 4 215 #define UARTFIFO_RXFE 0x00000008 216 #define UARTFIFO_RXSIZE_OFF 0 217 218 #define UARTWATER_COUNT_MASK 0xff 219 #define UARTWATER_TXCNT_OFF 8 220 #define UARTWATER_RXCNT_OFF 24 221 #define UARTWATER_WATER_MASK 0xff 222 #define UARTWATER_TXWATER_OFF 0 223 #define UARTWATER_RXWATER_OFF 16 224 225 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 226 #define DMA_RX_TIMEOUT (10) 227 228 #define DRIVER_NAME "fsl-lpuart" 229 #define DEV_NAME "ttyLP" 230 #define UART_NR 6 231 232 /* IMX lpuart has four extra unused regs located at the beginning */ 233 #define IMX_REG_OFF 0x10 234 235 struct lpuart_port { 236 struct uart_port port; 237 struct clk *clk; 238 unsigned int txfifo_size; 239 unsigned int rxfifo_size; 240 241 bool lpuart_dma_tx_use; 242 bool lpuart_dma_rx_use; 243 struct dma_chan *dma_tx_chan; 244 struct dma_chan *dma_rx_chan; 245 struct dma_async_tx_descriptor *dma_tx_desc; 246 struct dma_async_tx_descriptor *dma_rx_desc; 247 dma_cookie_t dma_tx_cookie; 248 dma_cookie_t dma_rx_cookie; 249 unsigned int dma_tx_bytes; 250 unsigned int dma_rx_bytes; 251 bool dma_tx_in_progress; 252 unsigned int dma_rx_timeout; 253 struct timer_list lpuart_timer; 254 struct scatterlist rx_sgl, tx_sgl[2]; 255 struct circ_buf rx_ring; 256 int rx_dma_rng_buf_len; 257 unsigned int dma_tx_nents; 258 wait_queue_head_t dma_wait; 259 }; 260 261 struct lpuart_soc_data { 262 char iotype; 263 u8 reg_off; 264 }; 265 266 static const struct lpuart_soc_data vf_data = { 267 .iotype = UPIO_MEM, 268 }; 269 270 static const struct lpuart_soc_data ls_data = { 271 .iotype = UPIO_MEM32BE, 272 }; 273 274 static struct lpuart_soc_data imx_data = { 275 .iotype = UPIO_MEM32, 276 .reg_off = IMX_REG_OFF, 277 }; 278 279 static const struct of_device_id lpuart_dt_ids[] = { 280 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 281 { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, }, 282 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx_data, }, 283 { /* sentinel */ } 284 }; 285 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 286 287 /* Forward declare this for the dma callbacks*/ 288 static void lpuart_dma_tx_complete(void *arg); 289 290 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 291 { 292 switch (port->iotype) { 293 case UPIO_MEM32: 294 return readl(port->membase + off); 295 case UPIO_MEM32BE: 296 return ioread32be(port->membase + off); 297 default: 298 return 0; 299 } 300 } 301 302 static inline void lpuart32_write(struct uart_port *port, u32 val, 303 u32 off) 304 { 305 switch (port->iotype) { 306 case UPIO_MEM32: 307 writel(val, port->membase + off); 308 break; 309 case UPIO_MEM32BE: 310 iowrite32be(val, port->membase + off); 311 break; 312 } 313 } 314 315 static void lpuart_stop_tx(struct uart_port *port) 316 { 317 unsigned char temp; 318 319 temp = readb(port->membase + UARTCR2); 320 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 321 writeb(temp, port->membase + UARTCR2); 322 } 323 324 static void lpuart32_stop_tx(struct uart_port *port) 325 { 326 unsigned long temp; 327 328 temp = lpuart32_read(port, UARTCTRL); 329 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 330 lpuart32_write(port, temp, UARTCTRL); 331 } 332 333 static void lpuart_stop_rx(struct uart_port *port) 334 { 335 unsigned char temp; 336 337 temp = readb(port->membase + UARTCR2); 338 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 339 } 340 341 static void lpuart32_stop_rx(struct uart_port *port) 342 { 343 unsigned long temp; 344 345 temp = lpuart32_read(port, UARTCTRL); 346 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); 347 } 348 349 static void lpuart_dma_tx(struct lpuart_port *sport) 350 { 351 struct circ_buf *xmit = &sport->port.state->xmit; 352 struct scatterlist *sgl = sport->tx_sgl; 353 struct device *dev = sport->port.dev; 354 int ret; 355 356 if (sport->dma_tx_in_progress) 357 return; 358 359 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 360 361 if (xmit->tail < xmit->head || xmit->head == 0) { 362 sport->dma_tx_nents = 1; 363 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 364 } else { 365 sport->dma_tx_nents = 2; 366 sg_init_table(sgl, 2); 367 sg_set_buf(sgl, xmit->buf + xmit->tail, 368 UART_XMIT_SIZE - xmit->tail); 369 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 370 } 371 372 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 373 if (!ret) { 374 dev_err(dev, "DMA mapping error for TX.\n"); 375 return; 376 } 377 378 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl, 379 sport->dma_tx_nents, 380 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 381 if (!sport->dma_tx_desc) { 382 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 383 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 384 return; 385 } 386 387 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 388 sport->dma_tx_desc->callback_param = sport; 389 sport->dma_tx_in_progress = true; 390 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 391 dma_async_issue_pending(sport->dma_tx_chan); 392 } 393 394 static void lpuart_dma_tx_complete(void *arg) 395 { 396 struct lpuart_port *sport = arg; 397 struct scatterlist *sgl = &sport->tx_sgl[0]; 398 struct circ_buf *xmit = &sport->port.state->xmit; 399 unsigned long flags; 400 401 spin_lock_irqsave(&sport->port.lock, flags); 402 403 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 404 405 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 406 407 sport->port.icount.tx += sport->dma_tx_bytes; 408 sport->dma_tx_in_progress = false; 409 spin_unlock_irqrestore(&sport->port.lock, flags); 410 411 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 412 uart_write_wakeup(&sport->port); 413 414 if (waitqueue_active(&sport->dma_wait)) { 415 wake_up(&sport->dma_wait); 416 return; 417 } 418 419 spin_lock_irqsave(&sport->port.lock, flags); 420 421 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 422 lpuart_dma_tx(sport); 423 424 spin_unlock_irqrestore(&sport->port.lock, flags); 425 } 426 427 static int lpuart_dma_tx_request(struct uart_port *port) 428 { 429 struct lpuart_port *sport = container_of(port, 430 struct lpuart_port, port); 431 struct dma_slave_config dma_tx_sconfig = {}; 432 int ret; 433 434 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR; 435 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 436 dma_tx_sconfig.dst_maxburst = 1; 437 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 438 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 439 440 if (ret) { 441 dev_err(sport->port.dev, 442 "DMA slave config failed, err = %d\n", ret); 443 return ret; 444 } 445 446 return 0; 447 } 448 449 static void lpuart_flush_buffer(struct uart_port *port) 450 { 451 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 452 453 if (sport->lpuart_dma_tx_use) { 454 if (sport->dma_tx_in_progress) { 455 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 456 sport->dma_tx_nents, DMA_TO_DEVICE); 457 sport->dma_tx_in_progress = false; 458 } 459 dmaengine_terminate_all(sport->dma_tx_chan); 460 } 461 } 462 463 #if defined(CONFIG_CONSOLE_POLL) 464 465 static int lpuart_poll_init(struct uart_port *port) 466 { 467 struct lpuart_port *sport = container_of(port, 468 struct lpuart_port, port); 469 unsigned long flags; 470 unsigned char temp; 471 472 sport->port.fifosize = 0; 473 474 spin_lock_irqsave(&sport->port.lock, flags); 475 /* Disable Rx & Tx */ 476 writeb(0, sport->port.membase + UARTCR2); 477 478 temp = readb(sport->port.membase + UARTPFIFO); 479 /* Enable Rx and Tx FIFO */ 480 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 481 sport->port.membase + UARTPFIFO); 482 483 /* flush Tx and Rx FIFO */ 484 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 485 sport->port.membase + UARTCFIFO); 486 487 /* explicitly clear RDRF */ 488 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 489 readb(sport->port.membase + UARTDR); 490 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 491 } 492 493 writeb(0, sport->port.membase + UARTTWFIFO); 494 writeb(1, sport->port.membase + UARTRWFIFO); 495 496 /* Enable Rx and Tx */ 497 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 498 spin_unlock_irqrestore(&sport->port.lock, flags); 499 500 return 0; 501 } 502 503 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 504 { 505 /* drain */ 506 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) 507 barrier(); 508 509 writeb(c, port->membase + UARTDR); 510 } 511 512 static int lpuart_poll_get_char(struct uart_port *port) 513 { 514 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 515 return NO_POLL_CHAR; 516 517 return readb(port->membase + UARTDR); 518 } 519 520 static int lpuart32_poll_init(struct uart_port *port) 521 { 522 unsigned long flags; 523 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 524 u32 temp; 525 526 sport->port.fifosize = 0; 527 528 spin_lock_irqsave(&sport->port.lock, flags); 529 530 /* Disable Rx & Tx */ 531 writel(0, sport->port.membase + UARTCTRL); 532 533 temp = readl(sport->port.membase + UARTFIFO); 534 535 /* Enable Rx and Tx FIFO */ 536 writel(temp | UARTFIFO_RXFE | UARTFIFO_TXFE, 537 sport->port.membase + UARTFIFO); 538 539 /* flush Tx and Rx FIFO */ 540 writel(UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, 541 sport->port.membase + UARTFIFO); 542 543 /* explicitly clear RDRF */ 544 if (readl(sport->port.membase + UARTSTAT) & UARTSTAT_RDRF) { 545 readl(sport->port.membase + UARTDATA); 546 writel(UARTFIFO_RXUF, sport->port.membase + UARTFIFO); 547 } 548 549 /* Enable Rx and Tx */ 550 writel(UARTCTRL_RE | UARTCTRL_TE, sport->port.membase + UARTCTRL); 551 spin_unlock_irqrestore(&sport->port.lock, flags); 552 553 return 0; 554 } 555 556 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 557 { 558 while (!(readl(port->membase + UARTSTAT) & UARTSTAT_TDRE)) 559 barrier(); 560 561 writel(c, port->membase + UARTDATA); 562 } 563 564 static int lpuart32_poll_get_char(struct uart_port *port) 565 { 566 if (!(readl(port->membase + UARTSTAT) & UARTSTAT_RDRF)) 567 return NO_POLL_CHAR; 568 569 return readl(port->membase + UARTDATA); 570 } 571 #endif 572 573 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 574 { 575 struct circ_buf *xmit = &sport->port.state->xmit; 576 577 while (!uart_circ_empty(xmit) && 578 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 579 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 580 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 581 sport->port.icount.tx++; 582 } 583 584 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 585 uart_write_wakeup(&sport->port); 586 587 if (uart_circ_empty(xmit)) 588 lpuart_stop_tx(&sport->port); 589 } 590 591 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 592 { 593 struct circ_buf *xmit = &sport->port.state->xmit; 594 unsigned long txcnt; 595 596 txcnt = lpuart32_read(&sport->port, UARTWATER); 597 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 598 txcnt &= UARTWATER_COUNT_MASK; 599 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 600 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); 601 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 602 sport->port.icount.tx++; 603 txcnt = lpuart32_read(&sport->port, UARTWATER); 604 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 605 txcnt &= UARTWATER_COUNT_MASK; 606 } 607 608 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 609 uart_write_wakeup(&sport->port); 610 611 if (uart_circ_empty(xmit)) 612 lpuart32_stop_tx(&sport->port); 613 } 614 615 static void lpuart_start_tx(struct uart_port *port) 616 { 617 struct lpuart_port *sport = container_of(port, 618 struct lpuart_port, port); 619 struct circ_buf *xmit = &sport->port.state->xmit; 620 unsigned char temp; 621 622 temp = readb(port->membase + UARTCR2); 623 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 624 625 if (sport->lpuart_dma_tx_use) { 626 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) 627 lpuart_dma_tx(sport); 628 } else { 629 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 630 lpuart_transmit_buffer(sport); 631 } 632 } 633 634 static void lpuart32_start_tx(struct uart_port *port) 635 { 636 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 637 unsigned long temp; 638 639 temp = lpuart32_read(port, UARTCTRL); 640 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); 641 642 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 643 lpuart32_transmit_buffer(sport); 644 } 645 646 /* return TIOCSER_TEMT when transmitter is not busy */ 647 static unsigned int lpuart_tx_empty(struct uart_port *port) 648 { 649 struct lpuart_port *sport = container_of(port, 650 struct lpuart_port, port); 651 unsigned char sr1 = readb(port->membase + UARTSR1); 652 unsigned char sfifo = readb(port->membase + UARTSFIFO); 653 654 if (sport->dma_tx_in_progress) 655 return 0; 656 657 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 658 return TIOCSER_TEMT; 659 660 return 0; 661 } 662 663 static unsigned int lpuart32_tx_empty(struct uart_port *port) 664 { 665 return (lpuart32_read(port, UARTSTAT) & UARTSTAT_TC) ? 666 TIOCSER_TEMT : 0; 667 } 668 669 static bool lpuart_is_32(struct lpuart_port *sport) 670 { 671 return sport->port.iotype == UPIO_MEM32 || 672 sport->port.iotype == UPIO_MEM32BE; 673 } 674 675 static irqreturn_t lpuart_txint(int irq, void *dev_id) 676 { 677 struct lpuart_port *sport = dev_id; 678 struct circ_buf *xmit = &sport->port.state->xmit; 679 unsigned long flags; 680 681 spin_lock_irqsave(&sport->port.lock, flags); 682 if (sport->port.x_char) { 683 if (lpuart_is_32(sport)) 684 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 685 else 686 writeb(sport->port.x_char, sport->port.membase + UARTDR); 687 goto out; 688 } 689 690 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 691 if (lpuart_is_32(sport)) 692 lpuart32_stop_tx(&sport->port); 693 else 694 lpuart_stop_tx(&sport->port); 695 goto out; 696 } 697 698 if (lpuart_is_32(sport)) 699 lpuart32_transmit_buffer(sport); 700 else 701 lpuart_transmit_buffer(sport); 702 703 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 704 uart_write_wakeup(&sport->port); 705 706 out: 707 spin_unlock_irqrestore(&sport->port.lock, flags); 708 return IRQ_HANDLED; 709 } 710 711 static irqreturn_t lpuart_rxint(int irq, void *dev_id) 712 { 713 struct lpuart_port *sport = dev_id; 714 unsigned int flg, ignored = 0; 715 struct tty_port *port = &sport->port.state->port; 716 unsigned long flags; 717 unsigned char rx, sr; 718 719 spin_lock_irqsave(&sport->port.lock, flags); 720 721 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 722 flg = TTY_NORMAL; 723 sport->port.icount.rx++; 724 /* 725 * to clear the FE, OR, NF, FE, PE flags, 726 * read SR1 then read DR 727 */ 728 sr = readb(sport->port.membase + UARTSR1); 729 rx = readb(sport->port.membase + UARTDR); 730 731 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 732 continue; 733 734 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 735 if (sr & UARTSR1_PE) 736 sport->port.icount.parity++; 737 else if (sr & UARTSR1_FE) 738 sport->port.icount.frame++; 739 740 if (sr & UARTSR1_OR) 741 sport->port.icount.overrun++; 742 743 if (sr & sport->port.ignore_status_mask) { 744 if (++ignored > 100) 745 goto out; 746 continue; 747 } 748 749 sr &= sport->port.read_status_mask; 750 751 if (sr & UARTSR1_PE) 752 flg = TTY_PARITY; 753 else if (sr & UARTSR1_FE) 754 flg = TTY_FRAME; 755 756 if (sr & UARTSR1_OR) 757 flg = TTY_OVERRUN; 758 759 #ifdef SUPPORT_SYSRQ 760 sport->port.sysrq = 0; 761 #endif 762 } 763 764 tty_insert_flip_char(port, rx, flg); 765 } 766 767 out: 768 spin_unlock_irqrestore(&sport->port.lock, flags); 769 770 tty_flip_buffer_push(port); 771 return IRQ_HANDLED; 772 } 773 774 static irqreturn_t lpuart32_rxint(int irq, void *dev_id) 775 { 776 struct lpuart_port *sport = dev_id; 777 unsigned int flg, ignored = 0; 778 struct tty_port *port = &sport->port.state->port; 779 unsigned long flags; 780 unsigned long rx, sr; 781 782 spin_lock_irqsave(&sport->port.lock, flags); 783 784 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 785 flg = TTY_NORMAL; 786 sport->port.icount.rx++; 787 /* 788 * to clear the FE, OR, NF, FE, PE flags, 789 * read STAT then read DATA reg 790 */ 791 sr = lpuart32_read(&sport->port, UARTSTAT); 792 rx = lpuart32_read(&sport->port, UARTDATA); 793 rx &= 0x3ff; 794 795 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 796 continue; 797 798 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 799 if (sr & UARTSTAT_PE) 800 sport->port.icount.parity++; 801 else if (sr & UARTSTAT_FE) 802 sport->port.icount.frame++; 803 804 if (sr & UARTSTAT_OR) 805 sport->port.icount.overrun++; 806 807 if (sr & sport->port.ignore_status_mask) { 808 if (++ignored > 100) 809 goto out; 810 continue; 811 } 812 813 sr &= sport->port.read_status_mask; 814 815 if (sr & UARTSTAT_PE) 816 flg = TTY_PARITY; 817 else if (sr & UARTSTAT_FE) 818 flg = TTY_FRAME; 819 820 if (sr & UARTSTAT_OR) 821 flg = TTY_OVERRUN; 822 823 #ifdef SUPPORT_SYSRQ 824 sport->port.sysrq = 0; 825 #endif 826 } 827 828 tty_insert_flip_char(port, rx, flg); 829 } 830 831 out: 832 spin_unlock_irqrestore(&sport->port.lock, flags); 833 834 tty_flip_buffer_push(port); 835 return IRQ_HANDLED; 836 } 837 838 static irqreturn_t lpuart_int(int irq, void *dev_id) 839 { 840 struct lpuart_port *sport = dev_id; 841 unsigned char sts; 842 843 sts = readb(sport->port.membase + UARTSR1); 844 845 if (sts & UARTSR1_RDRF) 846 lpuart_rxint(irq, dev_id); 847 848 if (sts & UARTSR1_TDRE) 849 lpuart_txint(irq, dev_id); 850 851 return IRQ_HANDLED; 852 } 853 854 static irqreturn_t lpuart32_int(int irq, void *dev_id) 855 { 856 struct lpuart_port *sport = dev_id; 857 unsigned long sts, rxcount; 858 859 sts = lpuart32_read(&sport->port, UARTSTAT); 860 rxcount = lpuart32_read(&sport->port, UARTWATER); 861 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 862 863 if (sts & UARTSTAT_RDRF || rxcount > 0) 864 lpuart32_rxint(irq, dev_id); 865 866 if ((sts & UARTSTAT_TDRE) && 867 !(lpuart32_read(&sport->port, UARTBAUD) & UARTBAUD_TDMAE)) 868 lpuart_txint(irq, dev_id); 869 870 lpuart32_write(&sport->port, sts, UARTSTAT); 871 return IRQ_HANDLED; 872 } 873 874 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 875 { 876 struct tty_port *port = &sport->port.state->port; 877 struct dma_tx_state state; 878 enum dma_status dmastat; 879 struct circ_buf *ring = &sport->rx_ring; 880 unsigned long flags; 881 int count = 0; 882 unsigned char sr; 883 884 sr = readb(sport->port.membase + UARTSR1); 885 886 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 887 /* Read DR to clear the error flags */ 888 readb(sport->port.membase + UARTDR); 889 890 if (sr & UARTSR1_PE) 891 sport->port.icount.parity++; 892 else if (sr & UARTSR1_FE) 893 sport->port.icount.frame++; 894 } 895 896 async_tx_ack(sport->dma_rx_desc); 897 898 spin_lock_irqsave(&sport->port.lock, flags); 899 900 dmastat = dmaengine_tx_status(sport->dma_rx_chan, 901 sport->dma_rx_cookie, 902 &state); 903 904 if (dmastat == DMA_ERROR) { 905 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 906 spin_unlock_irqrestore(&sport->port.lock, flags); 907 return; 908 } 909 910 /* CPU claims ownership of RX DMA buffer */ 911 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 912 913 /* 914 * ring->head points to the end of data already written by the DMA. 915 * ring->tail points to the beginning of data to be read by the 916 * framework. 917 * The current transfer size should not be larger than the dma buffer 918 * length. 919 */ 920 ring->head = sport->rx_sgl.length - state.residue; 921 BUG_ON(ring->head > sport->rx_sgl.length); 922 /* 923 * At this point ring->head may point to the first byte right after the 924 * last byte of the dma buffer: 925 * 0 <= ring->head <= sport->rx_sgl.length 926 * 927 * However ring->tail must always points inside the dma buffer: 928 * 0 <= ring->tail <= sport->rx_sgl.length - 1 929 * 930 * Since we use a ring buffer, we have to handle the case 931 * where head is lower than tail. In such a case, we first read from 932 * tail to the end of the buffer then reset tail. 933 */ 934 if (ring->head < ring->tail) { 935 count = sport->rx_sgl.length - ring->tail; 936 937 tty_insert_flip_string(port, ring->buf + ring->tail, count); 938 ring->tail = 0; 939 sport->port.icount.rx += count; 940 } 941 942 /* Finally we read data from tail to head */ 943 if (ring->tail < ring->head) { 944 count = ring->head - ring->tail; 945 tty_insert_flip_string(port, ring->buf + ring->tail, count); 946 /* Wrap ring->head if needed */ 947 if (ring->head >= sport->rx_sgl.length) 948 ring->head = 0; 949 ring->tail = ring->head; 950 sport->port.icount.rx += count; 951 } 952 953 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1, 954 DMA_FROM_DEVICE); 955 956 spin_unlock_irqrestore(&sport->port.lock, flags); 957 958 tty_flip_buffer_push(port); 959 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 960 } 961 962 static void lpuart_dma_rx_complete(void *arg) 963 { 964 struct lpuart_port *sport = arg; 965 966 lpuart_copy_rx_to_tty(sport); 967 } 968 969 static void lpuart_timer_func(unsigned long data) 970 { 971 struct lpuart_port *sport = (struct lpuart_port *)data; 972 973 lpuart_copy_rx_to_tty(sport); 974 } 975 976 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 977 { 978 struct dma_slave_config dma_rx_sconfig = {}; 979 struct circ_buf *ring = &sport->rx_ring; 980 int ret, nent; 981 int bits, baud; 982 struct tty_struct *tty = tty_port_tty_get(&sport->port.state->port); 983 struct ktermios *termios = &tty->termios; 984 985 baud = tty_get_baud_rate(tty); 986 987 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; 988 if (termios->c_cflag & PARENB) 989 bits++; 990 991 /* 992 * Calculate length of one DMA buffer size to keep latency below 993 * 10ms at any baud rate. 994 */ 995 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 996 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 997 if (sport->rx_dma_rng_buf_len < 16) 998 sport->rx_dma_rng_buf_len = 16; 999 1000 ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1001 if (!ring->buf) { 1002 dev_err(sport->port.dev, "Ring buf alloc failed\n"); 1003 return -ENOMEM; 1004 } 1005 1006 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1007 sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1008 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1009 1010 if (!nent) { 1011 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1012 return -EINVAL; 1013 } 1014 1015 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR; 1016 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1017 dma_rx_sconfig.src_maxburst = 1; 1018 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1019 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig); 1020 1021 if (ret < 0) { 1022 dev_err(sport->port.dev, 1023 "DMA Rx slave config failed, err = %d\n", ret); 1024 return ret; 1025 } 1026 1027 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan, 1028 sg_dma_address(&sport->rx_sgl), 1029 sport->rx_sgl.length, 1030 sport->rx_sgl.length / 2, 1031 DMA_DEV_TO_MEM, 1032 DMA_PREP_INTERRUPT); 1033 if (!sport->dma_rx_desc) { 1034 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1035 return -EFAULT; 1036 } 1037 1038 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1039 sport->dma_rx_desc->callback_param = sport; 1040 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1041 dma_async_issue_pending(sport->dma_rx_chan); 1042 1043 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1044 sport->port.membase + UARTCR5); 1045 1046 return 0; 1047 } 1048 1049 static void lpuart_dma_rx_free(struct uart_port *port) 1050 { 1051 struct lpuart_port *sport = container_of(port, 1052 struct lpuart_port, port); 1053 1054 if (sport->dma_rx_chan) 1055 dmaengine_terminate_all(sport->dma_rx_chan); 1056 1057 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1058 kfree(sport->rx_ring.buf); 1059 sport->rx_ring.tail = 0; 1060 sport->rx_ring.head = 0; 1061 sport->dma_rx_desc = NULL; 1062 sport->dma_rx_cookie = -EINVAL; 1063 } 1064 1065 static int lpuart_config_rs485(struct uart_port *port, 1066 struct serial_rs485 *rs485) 1067 { 1068 struct lpuart_port *sport = container_of(port, 1069 struct lpuart_port, port); 1070 1071 u8 modem = readb(sport->port.membase + UARTMODEM) & 1072 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1073 writeb(modem, sport->port.membase + UARTMODEM); 1074 1075 /* clear unsupported configurations */ 1076 rs485->delay_rts_before_send = 0; 1077 rs485->delay_rts_after_send = 0; 1078 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1079 1080 if (rs485->flags & SER_RS485_ENABLED) { 1081 /* Enable auto RS-485 RTS mode */ 1082 modem |= UARTMODEM_TXRTSE; 1083 1084 /* 1085 * RTS needs to be logic HIGH either during transer _or_ after 1086 * transfer, other variants are not supported by the hardware. 1087 */ 1088 1089 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1090 SER_RS485_RTS_AFTER_SEND))) 1091 rs485->flags |= SER_RS485_RTS_ON_SEND; 1092 1093 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1094 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1095 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1096 1097 /* 1098 * The hardware defaults to RTS logic HIGH while transfer. 1099 * Switch polarity in case RTS shall be logic HIGH 1100 * after transfer. 1101 * Note: UART is assumed to be active high. 1102 */ 1103 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1104 modem &= ~UARTMODEM_TXRTSPOL; 1105 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1106 modem |= UARTMODEM_TXRTSPOL; 1107 } 1108 1109 /* Store the new configuration */ 1110 sport->port.rs485 = *rs485; 1111 1112 writeb(modem, sport->port.membase + UARTMODEM); 1113 return 0; 1114 } 1115 1116 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1117 { 1118 unsigned int temp = 0; 1119 unsigned char reg; 1120 1121 reg = readb(port->membase + UARTMODEM); 1122 if (reg & UARTMODEM_TXCTSE) 1123 temp |= TIOCM_CTS; 1124 1125 if (reg & UARTMODEM_RXRTSE) 1126 temp |= TIOCM_RTS; 1127 1128 return temp; 1129 } 1130 1131 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1132 { 1133 unsigned int temp = 0; 1134 unsigned long reg; 1135 1136 reg = lpuart32_read(port, UARTMODIR); 1137 if (reg & UARTMODIR_TXCTSE) 1138 temp |= TIOCM_CTS; 1139 1140 if (reg & UARTMODIR_RXRTSE) 1141 temp |= TIOCM_RTS; 1142 1143 return temp; 1144 } 1145 1146 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1147 { 1148 unsigned char temp; 1149 struct lpuart_port *sport = container_of(port, 1150 struct lpuart_port, port); 1151 1152 /* Make sure RXRTSE bit is not set when RS485 is enabled */ 1153 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { 1154 temp = readb(sport->port.membase + UARTMODEM) & 1155 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1156 1157 if (mctrl & TIOCM_RTS) 1158 temp |= UARTMODEM_RXRTSE; 1159 1160 if (mctrl & TIOCM_CTS) 1161 temp |= UARTMODEM_TXCTSE; 1162 1163 writeb(temp, port->membase + UARTMODEM); 1164 } 1165 } 1166 1167 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1168 { 1169 unsigned long temp; 1170 1171 temp = lpuart32_read(port, UARTMODIR) & 1172 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 1173 1174 if (mctrl & TIOCM_RTS) 1175 temp |= UARTMODIR_RXRTSE; 1176 1177 if (mctrl & TIOCM_CTS) 1178 temp |= UARTMODIR_TXCTSE; 1179 1180 lpuart32_write(port, temp, UARTMODIR); 1181 } 1182 1183 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1184 { 1185 unsigned char temp; 1186 1187 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1188 1189 if (break_state != 0) 1190 temp |= UARTCR2_SBK; 1191 1192 writeb(temp, port->membase + UARTCR2); 1193 } 1194 1195 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1196 { 1197 unsigned long temp; 1198 1199 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; 1200 1201 if (break_state != 0) 1202 temp |= UARTCTRL_SBK; 1203 1204 lpuart32_write(port, temp, UARTCTRL); 1205 } 1206 1207 static void lpuart_setup_watermark(struct lpuart_port *sport) 1208 { 1209 unsigned char val, cr2; 1210 unsigned char cr2_saved; 1211 1212 cr2 = readb(sport->port.membase + UARTCR2); 1213 cr2_saved = cr2; 1214 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1215 UARTCR2_RIE | UARTCR2_RE); 1216 writeb(cr2, sport->port.membase + UARTCR2); 1217 1218 val = readb(sport->port.membase + UARTPFIFO); 1219 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1220 sport->port.membase + UARTPFIFO); 1221 1222 /* flush Tx and Rx FIFO */ 1223 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1224 sport->port.membase + UARTCFIFO); 1225 1226 /* explicitly clear RDRF */ 1227 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1228 readb(sport->port.membase + UARTDR); 1229 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1230 } 1231 1232 writeb(0, sport->port.membase + UARTTWFIFO); 1233 writeb(1, sport->port.membase + UARTRWFIFO); 1234 1235 /* Restore cr2 */ 1236 writeb(cr2_saved, sport->port.membase + UARTCR2); 1237 } 1238 1239 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1240 { 1241 unsigned long val, ctrl; 1242 unsigned long ctrl_saved; 1243 1244 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1245 ctrl_saved = ctrl; 1246 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1247 UARTCTRL_RIE | UARTCTRL_RE); 1248 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1249 1250 /* enable FIFO mode */ 1251 val = lpuart32_read(&sport->port, UARTFIFO); 1252 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1253 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1254 lpuart32_write(&sport->port, val, UARTFIFO); 1255 1256 /* set the watermark */ 1257 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1258 lpuart32_write(&sport->port, val, UARTWATER); 1259 1260 /* Restore cr2 */ 1261 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1262 } 1263 1264 static void rx_dma_timer_init(struct lpuart_port *sport) 1265 { 1266 setup_timer(&sport->lpuart_timer, lpuart_timer_func, 1267 (unsigned long)sport); 1268 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1269 add_timer(&sport->lpuart_timer); 1270 } 1271 1272 static int lpuart_startup(struct uart_port *port) 1273 { 1274 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1275 unsigned long flags; 1276 unsigned char temp; 1277 1278 /* determine FIFO size and enable FIFO mode */ 1279 temp = readb(sport->port.membase + UARTPFIFO); 1280 1281 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) & 1282 UARTPFIFO_FIFOSIZE_MASK) + 1); 1283 1284 sport->port.fifosize = sport->txfifo_size; 1285 1286 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) & 1287 UARTPFIFO_FIFOSIZE_MASK) + 1); 1288 1289 spin_lock_irqsave(&sport->port.lock, flags); 1290 1291 lpuart_setup_watermark(sport); 1292 1293 temp = readb(sport->port.membase + UARTCR2); 1294 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 1295 writeb(temp, sport->port.membase + UARTCR2); 1296 1297 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) { 1298 /* set Rx DMA timeout */ 1299 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1300 if (!sport->dma_rx_timeout) 1301 sport->dma_rx_timeout = 1; 1302 1303 sport->lpuart_dma_rx_use = true; 1304 rx_dma_timer_init(sport); 1305 } else { 1306 sport->lpuart_dma_rx_use = false; 1307 } 1308 1309 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) { 1310 init_waitqueue_head(&sport->dma_wait); 1311 sport->lpuart_dma_tx_use = true; 1312 temp = readb(port->membase + UARTCR5); 1313 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5); 1314 } else { 1315 sport->lpuart_dma_tx_use = false; 1316 } 1317 1318 spin_unlock_irqrestore(&sport->port.lock, flags); 1319 1320 return 0; 1321 } 1322 1323 static int lpuart32_startup(struct uart_port *port) 1324 { 1325 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1326 unsigned long flags; 1327 unsigned long temp; 1328 1329 /* determine FIFO size */ 1330 temp = lpuart32_read(&sport->port, UARTFIFO); 1331 1332 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) & 1333 UARTFIFO_FIFOSIZE_MASK) - 1); 1334 1335 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) & 1336 UARTFIFO_FIFOSIZE_MASK) - 1); 1337 1338 spin_lock_irqsave(&sport->port.lock, flags); 1339 1340 lpuart32_setup_watermark(sport); 1341 1342 temp = lpuart32_read(&sport->port, UARTCTRL); 1343 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE); 1344 temp |= UARTCTRL_ILIE; 1345 lpuart32_write(&sport->port, temp, UARTCTRL); 1346 1347 spin_unlock_irqrestore(&sport->port.lock, flags); 1348 return 0; 1349 } 1350 1351 static void lpuart_shutdown(struct uart_port *port) 1352 { 1353 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1354 unsigned char temp; 1355 unsigned long flags; 1356 1357 spin_lock_irqsave(&port->lock, flags); 1358 1359 /* disable Rx/Tx and interrupts */ 1360 temp = readb(port->membase + UARTCR2); 1361 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1362 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1363 writeb(temp, port->membase + UARTCR2); 1364 1365 spin_unlock_irqrestore(&port->lock, flags); 1366 1367 if (sport->lpuart_dma_rx_use) { 1368 del_timer_sync(&sport->lpuart_timer); 1369 lpuart_dma_rx_free(&sport->port); 1370 } 1371 1372 if (sport->lpuart_dma_tx_use) { 1373 if (wait_event_interruptible(sport->dma_wait, 1374 !sport->dma_tx_in_progress) != false) { 1375 sport->dma_tx_in_progress = false; 1376 dmaengine_terminate_all(sport->dma_tx_chan); 1377 } 1378 1379 lpuart_stop_tx(port); 1380 } 1381 } 1382 1383 static void lpuart32_shutdown(struct uart_port *port) 1384 { 1385 unsigned long temp; 1386 unsigned long flags; 1387 1388 spin_lock_irqsave(&port->lock, flags); 1389 1390 /* disable Rx/Tx and interrupts */ 1391 temp = lpuart32_read(port, UARTCTRL); 1392 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1393 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1394 lpuart32_write(port, temp, UARTCTRL); 1395 1396 spin_unlock_irqrestore(&port->lock, flags); 1397 } 1398 1399 static void 1400 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1401 struct ktermios *old) 1402 { 1403 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1404 unsigned long flags; 1405 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1406 unsigned int baud; 1407 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1408 unsigned int sbr, brfa; 1409 1410 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1411 old_cr2 = readb(sport->port.membase + UARTCR2); 1412 cr3 = readb(sport->port.membase + UARTCR3); 1413 cr4 = readb(sport->port.membase + UARTCR4); 1414 bdh = readb(sport->port.membase + UARTBDH); 1415 modem = readb(sport->port.membase + UARTMODEM); 1416 /* 1417 * only support CS8 and CS7, and for CS7 must enable PE. 1418 * supported mode: 1419 * - (7,e/o,1) 1420 * - (8,n,1) 1421 * - (8,m/s,1) 1422 * - (8,e/o,1) 1423 */ 1424 while ((termios->c_cflag & CSIZE) != CS8 && 1425 (termios->c_cflag & CSIZE) != CS7) { 1426 termios->c_cflag &= ~CSIZE; 1427 termios->c_cflag |= old_csize; 1428 old_csize = CS8; 1429 } 1430 1431 if ((termios->c_cflag & CSIZE) == CS8 || 1432 (termios->c_cflag & CSIZE) == CS7) 1433 cr1 = old_cr1 & ~UARTCR1_M; 1434 1435 if (termios->c_cflag & CMSPAR) { 1436 if ((termios->c_cflag & CSIZE) != CS8) { 1437 termios->c_cflag &= ~CSIZE; 1438 termios->c_cflag |= CS8; 1439 } 1440 cr1 |= UARTCR1_M; 1441 } 1442 1443 /* 1444 * When auto RS-485 RTS mode is enabled, 1445 * hardware flow control need to be disabled. 1446 */ 1447 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1448 termios->c_cflag &= ~CRTSCTS; 1449 1450 if (termios->c_cflag & CRTSCTS) { 1451 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1452 } else { 1453 termios->c_cflag &= ~CRTSCTS; 1454 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1455 } 1456 1457 if (termios->c_cflag & CSTOPB) 1458 termios->c_cflag &= ~CSTOPB; 1459 1460 /* parity must be enabled when CS7 to match 8-bits format */ 1461 if ((termios->c_cflag & CSIZE) == CS7) 1462 termios->c_cflag |= PARENB; 1463 1464 if ((termios->c_cflag & PARENB)) { 1465 if (termios->c_cflag & CMSPAR) { 1466 cr1 &= ~UARTCR1_PE; 1467 if (termios->c_cflag & PARODD) 1468 cr3 |= UARTCR3_T8; 1469 else 1470 cr3 &= ~UARTCR3_T8; 1471 } else { 1472 cr1 |= UARTCR1_PE; 1473 if ((termios->c_cflag & CSIZE) == CS8) 1474 cr1 |= UARTCR1_M; 1475 if (termios->c_cflag & PARODD) 1476 cr1 |= UARTCR1_PT; 1477 else 1478 cr1 &= ~UARTCR1_PT; 1479 } 1480 } 1481 1482 /* ask the core to calculate the divisor */ 1483 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1484 1485 /* 1486 * Need to update the Ring buffer length according to the selected 1487 * baud rate and restart Rx DMA path. 1488 * 1489 * Since timer function acqures sport->port.lock, need to stop before 1490 * acquring same lock because otherwise del_timer_sync() can deadlock. 1491 */ 1492 if (old && sport->lpuart_dma_rx_use) { 1493 del_timer_sync(&sport->lpuart_timer); 1494 lpuart_dma_rx_free(&sport->port); 1495 } 1496 1497 spin_lock_irqsave(&sport->port.lock, flags); 1498 1499 sport->port.read_status_mask = 0; 1500 if (termios->c_iflag & INPCK) 1501 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE); 1502 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1503 sport->port.read_status_mask |= UARTSR1_FE; 1504 1505 /* characters to ignore */ 1506 sport->port.ignore_status_mask = 0; 1507 if (termios->c_iflag & IGNPAR) 1508 sport->port.ignore_status_mask |= UARTSR1_PE; 1509 if (termios->c_iflag & IGNBRK) { 1510 sport->port.ignore_status_mask |= UARTSR1_FE; 1511 /* 1512 * if we're ignoring parity and break indicators, 1513 * ignore overruns too (for real raw support). 1514 */ 1515 if (termios->c_iflag & IGNPAR) 1516 sport->port.ignore_status_mask |= UARTSR1_OR; 1517 } 1518 1519 /* update the per-port timeout */ 1520 uart_update_timeout(port, termios->c_cflag, baud); 1521 1522 /* wait transmit engin complete */ 1523 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1524 barrier(); 1525 1526 /* disable transmit and receive */ 1527 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1528 sport->port.membase + UARTCR2); 1529 1530 sbr = sport->port.uartclk / (16 * baud); 1531 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1532 bdh &= ~UARTBDH_SBR_MASK; 1533 bdh |= (sbr >> 8) & 0x1F; 1534 cr4 &= ~UARTCR4_BRFA_MASK; 1535 brfa &= UARTCR4_BRFA_MASK; 1536 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1537 writeb(bdh, sport->port.membase + UARTBDH); 1538 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1539 writeb(cr3, sport->port.membase + UARTCR3); 1540 writeb(cr1, sport->port.membase + UARTCR1); 1541 writeb(modem, sport->port.membase + UARTMODEM); 1542 1543 /* restore control register */ 1544 writeb(old_cr2, sport->port.membase + UARTCR2); 1545 1546 if (old && sport->lpuart_dma_rx_use) { 1547 if (!lpuart_start_rx_dma(sport)) 1548 rx_dma_timer_init(sport); 1549 else 1550 sport->lpuart_dma_rx_use = false; 1551 } 1552 1553 spin_unlock_irqrestore(&sport->port.lock, flags); 1554 } 1555 1556 static void 1557 lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate) 1558 { 1559 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; 1560 u32 clk = sport->port.uartclk; 1561 1562 /* 1563 * The idea is to use the best OSR (over-sampling rate) possible. 1564 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 1565 * Loop to find the best OSR value possible, one that generates minimum 1566 * baud_diff iterate through the rest of the supported values of OSR. 1567 * 1568 * Calculation Formula: 1569 * Baud Rate = baud clock / ((OSR+1) × SBR) 1570 */ 1571 baud_diff = baudrate; 1572 osr = 0; 1573 sbr = 0; 1574 1575 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 1576 /* calculate the temporary sbr value */ 1577 tmp_sbr = (clk / (baudrate * tmp_osr)); 1578 if (tmp_sbr == 0) 1579 tmp_sbr = 1; 1580 1581 /* 1582 * calculate the baud rate difference based on the temporary 1583 * osr and sbr values 1584 */ 1585 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 1586 1587 /* select best values between sbr and sbr+1 */ 1588 tmp = clk / (tmp_osr * (tmp_sbr + 1)); 1589 if (tmp_diff > (baudrate - tmp)) { 1590 tmp_diff = baudrate - tmp; 1591 tmp_sbr++; 1592 } 1593 1594 if (tmp_diff <= baud_diff) { 1595 baud_diff = tmp_diff; 1596 osr = tmp_osr; 1597 sbr = tmp_sbr; 1598 1599 if (!baud_diff) 1600 break; 1601 } 1602 } 1603 1604 /* handle buadrate outside acceptable rate */ 1605 if (baud_diff > ((baudrate / 100) * 3)) 1606 dev_warn(sport->port.dev, 1607 "unacceptable baud rate difference of more than 3%%\n"); 1608 1609 tmp = lpuart32_read(&sport->port, UARTBAUD); 1610 1611 if ((osr > 3) && (osr < 8)) 1612 tmp |= UARTBAUD_BOTHEDGE; 1613 1614 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 1615 tmp |= (((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT); 1616 1617 tmp &= ~UARTBAUD_SBR_MASK; 1618 tmp |= sbr & UARTBAUD_SBR_MASK; 1619 1620 tmp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); 1621 1622 lpuart32_write(&sport->port, tmp, UARTBAUD); 1623 } 1624 1625 static void 1626 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 1627 struct ktermios *old) 1628 { 1629 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1630 unsigned long flags; 1631 unsigned long ctrl, old_ctrl, modem; 1632 unsigned int baud; 1633 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1634 1635 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); 1636 modem = lpuart32_read(&sport->port, UARTMODIR); 1637 /* 1638 * only support CS8 and CS7, and for CS7 must enable PE. 1639 * supported mode: 1640 * - (7,e/o,1) 1641 * - (8,n,1) 1642 * - (8,m/s,1) 1643 * - (8,e/o,1) 1644 */ 1645 while ((termios->c_cflag & CSIZE) != CS8 && 1646 (termios->c_cflag & CSIZE) != CS7) { 1647 termios->c_cflag &= ~CSIZE; 1648 termios->c_cflag |= old_csize; 1649 old_csize = CS8; 1650 } 1651 1652 if ((termios->c_cflag & CSIZE) == CS8 || 1653 (termios->c_cflag & CSIZE) == CS7) 1654 ctrl = old_ctrl & ~UARTCTRL_M; 1655 1656 if (termios->c_cflag & CMSPAR) { 1657 if ((termios->c_cflag & CSIZE) != CS8) { 1658 termios->c_cflag &= ~CSIZE; 1659 termios->c_cflag |= CS8; 1660 } 1661 ctrl |= UARTCTRL_M; 1662 } 1663 1664 if (termios->c_cflag & CRTSCTS) { 1665 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1666 } else { 1667 termios->c_cflag &= ~CRTSCTS; 1668 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1669 } 1670 1671 if (termios->c_cflag & CSTOPB) 1672 termios->c_cflag &= ~CSTOPB; 1673 1674 /* parity must be enabled when CS7 to match 8-bits format */ 1675 if ((termios->c_cflag & CSIZE) == CS7) 1676 termios->c_cflag |= PARENB; 1677 1678 if ((termios->c_cflag & PARENB)) { 1679 if (termios->c_cflag & CMSPAR) { 1680 ctrl &= ~UARTCTRL_PE; 1681 ctrl |= UARTCTRL_M; 1682 } else { 1683 ctrl |= UARTCR1_PE; 1684 if ((termios->c_cflag & CSIZE) == CS8) 1685 ctrl |= UARTCTRL_M; 1686 if (termios->c_cflag & PARODD) 1687 ctrl |= UARTCTRL_PT; 1688 else 1689 ctrl &= ~UARTCTRL_PT; 1690 } 1691 } 1692 1693 /* ask the core to calculate the divisor */ 1694 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1695 1696 spin_lock_irqsave(&sport->port.lock, flags); 1697 1698 sport->port.read_status_mask = 0; 1699 if (termios->c_iflag & INPCK) 1700 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE); 1701 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1702 sport->port.read_status_mask |= UARTSTAT_FE; 1703 1704 /* characters to ignore */ 1705 sport->port.ignore_status_mask = 0; 1706 if (termios->c_iflag & IGNPAR) 1707 sport->port.ignore_status_mask |= UARTSTAT_PE; 1708 if (termios->c_iflag & IGNBRK) { 1709 sport->port.ignore_status_mask |= UARTSTAT_FE; 1710 /* 1711 * if we're ignoring parity and break indicators, 1712 * ignore overruns too (for real raw support). 1713 */ 1714 if (termios->c_iflag & IGNPAR) 1715 sport->port.ignore_status_mask |= UARTSTAT_OR; 1716 } 1717 1718 /* update the per-port timeout */ 1719 uart_update_timeout(port, termios->c_cflag, baud); 1720 1721 /* wait transmit engin complete */ 1722 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC)) 1723 barrier(); 1724 1725 /* disable transmit and receive */ 1726 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 1727 UARTCTRL); 1728 1729 lpuart32_serial_setbrg(sport, baud); 1730 lpuart32_write(&sport->port, modem, UARTMODIR); 1731 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1732 /* restore control register */ 1733 1734 spin_unlock_irqrestore(&sport->port.lock, flags); 1735 } 1736 1737 static const char *lpuart_type(struct uart_port *port) 1738 { 1739 return "FSL_LPUART"; 1740 } 1741 1742 static void lpuart_release_port(struct uart_port *port) 1743 { 1744 /* nothing to do */ 1745 } 1746 1747 static int lpuart_request_port(struct uart_port *port) 1748 { 1749 return 0; 1750 } 1751 1752 /* configure/autoconfigure the port */ 1753 static void lpuart_config_port(struct uart_port *port, int flags) 1754 { 1755 if (flags & UART_CONFIG_TYPE) 1756 port->type = PORT_LPUART; 1757 } 1758 1759 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 1760 { 1761 int ret = 0; 1762 1763 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 1764 ret = -EINVAL; 1765 if (port->irq != ser->irq) 1766 ret = -EINVAL; 1767 if (ser->io_type != UPIO_MEM) 1768 ret = -EINVAL; 1769 if (port->uartclk / 16 != ser->baud_base) 1770 ret = -EINVAL; 1771 if (port->iobase != ser->port) 1772 ret = -EINVAL; 1773 if (ser->hub6 != 0) 1774 ret = -EINVAL; 1775 return ret; 1776 } 1777 1778 static const struct uart_ops lpuart_pops = { 1779 .tx_empty = lpuart_tx_empty, 1780 .set_mctrl = lpuart_set_mctrl, 1781 .get_mctrl = lpuart_get_mctrl, 1782 .stop_tx = lpuart_stop_tx, 1783 .start_tx = lpuart_start_tx, 1784 .stop_rx = lpuart_stop_rx, 1785 .break_ctl = lpuart_break_ctl, 1786 .startup = lpuart_startup, 1787 .shutdown = lpuart_shutdown, 1788 .set_termios = lpuart_set_termios, 1789 .type = lpuart_type, 1790 .request_port = lpuart_request_port, 1791 .release_port = lpuart_release_port, 1792 .config_port = lpuart_config_port, 1793 .verify_port = lpuart_verify_port, 1794 .flush_buffer = lpuart_flush_buffer, 1795 #if defined(CONFIG_CONSOLE_POLL) 1796 .poll_init = lpuart_poll_init, 1797 .poll_get_char = lpuart_poll_get_char, 1798 .poll_put_char = lpuart_poll_put_char, 1799 #endif 1800 }; 1801 1802 static const struct uart_ops lpuart32_pops = { 1803 .tx_empty = lpuart32_tx_empty, 1804 .set_mctrl = lpuart32_set_mctrl, 1805 .get_mctrl = lpuart32_get_mctrl, 1806 .stop_tx = lpuart32_stop_tx, 1807 .start_tx = lpuart32_start_tx, 1808 .stop_rx = lpuart32_stop_rx, 1809 .break_ctl = lpuart32_break_ctl, 1810 .startup = lpuart32_startup, 1811 .shutdown = lpuart32_shutdown, 1812 .set_termios = lpuart32_set_termios, 1813 .type = lpuart_type, 1814 .request_port = lpuart_request_port, 1815 .release_port = lpuart_release_port, 1816 .config_port = lpuart_config_port, 1817 .verify_port = lpuart_verify_port, 1818 .flush_buffer = lpuart_flush_buffer, 1819 #if defined(CONFIG_CONSOLE_POLL) 1820 .poll_init = lpuart32_poll_init, 1821 .poll_get_char = lpuart32_poll_get_char, 1822 .poll_put_char = lpuart32_poll_put_char, 1823 #endif 1824 }; 1825 1826 static struct lpuart_port *lpuart_ports[UART_NR]; 1827 1828 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 1829 static void lpuart_console_putchar(struct uart_port *port, int ch) 1830 { 1831 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) 1832 barrier(); 1833 1834 writeb(ch, port->membase + UARTDR); 1835 } 1836 1837 static void lpuart32_console_putchar(struct uart_port *port, int ch) 1838 { 1839 while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)) 1840 barrier(); 1841 1842 lpuart32_write(port, ch, UARTDATA); 1843 } 1844 1845 static void 1846 lpuart_console_write(struct console *co, const char *s, unsigned int count) 1847 { 1848 struct lpuart_port *sport = lpuart_ports[co->index]; 1849 unsigned char old_cr2, cr2; 1850 unsigned long flags; 1851 int locked = 1; 1852 1853 if (sport->port.sysrq || oops_in_progress) 1854 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1855 else 1856 spin_lock_irqsave(&sport->port.lock, flags); 1857 1858 /* first save CR2 and then disable interrupts */ 1859 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 1860 cr2 |= (UARTCR2_TE | UARTCR2_RE); 1861 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1862 writeb(cr2, sport->port.membase + UARTCR2); 1863 1864 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 1865 1866 /* wait for transmitter finish complete and restore CR2 */ 1867 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1868 barrier(); 1869 1870 writeb(old_cr2, sport->port.membase + UARTCR2); 1871 1872 if (locked) 1873 spin_unlock_irqrestore(&sport->port.lock, flags); 1874 } 1875 1876 static void 1877 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 1878 { 1879 struct lpuart_port *sport = lpuart_ports[co->index]; 1880 unsigned long old_cr, cr; 1881 unsigned long flags; 1882 int locked = 1; 1883 1884 if (sport->port.sysrq || oops_in_progress) 1885 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1886 else 1887 spin_lock_irqsave(&sport->port.lock, flags); 1888 1889 /* first save CR2 and then disable interrupts */ 1890 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 1891 cr |= (UARTCTRL_TE | UARTCTRL_RE); 1892 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1893 lpuart32_write(&sport->port, cr, UARTCTRL); 1894 1895 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 1896 1897 /* wait for transmitter finish complete and restore CR2 */ 1898 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC)) 1899 barrier(); 1900 1901 lpuart32_write(&sport->port, old_cr, UARTCTRL); 1902 1903 if (locked) 1904 spin_unlock_irqrestore(&sport->port.lock, flags); 1905 } 1906 1907 /* 1908 * if the port was already initialised (eg, by a boot loader), 1909 * try to determine the current setup. 1910 */ 1911 static void __init 1912 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 1913 int *parity, int *bits) 1914 { 1915 unsigned char cr, bdh, bdl, brfa; 1916 unsigned int sbr, uartclk, baud_raw; 1917 1918 cr = readb(sport->port.membase + UARTCR2); 1919 cr &= UARTCR2_TE | UARTCR2_RE; 1920 if (!cr) 1921 return; 1922 1923 /* ok, the port was enabled */ 1924 1925 cr = readb(sport->port.membase + UARTCR1); 1926 1927 *parity = 'n'; 1928 if (cr & UARTCR1_PE) { 1929 if (cr & UARTCR1_PT) 1930 *parity = 'o'; 1931 else 1932 *parity = 'e'; 1933 } 1934 1935 if (cr & UARTCR1_M) 1936 *bits = 9; 1937 else 1938 *bits = 8; 1939 1940 bdh = readb(sport->port.membase + UARTBDH); 1941 bdh &= UARTBDH_SBR_MASK; 1942 bdl = readb(sport->port.membase + UARTBDL); 1943 sbr = bdh; 1944 sbr <<= 8; 1945 sbr |= bdl; 1946 brfa = readb(sport->port.membase + UARTCR4); 1947 brfa &= UARTCR4_BRFA_MASK; 1948 1949 uartclk = clk_get_rate(sport->clk); 1950 /* 1951 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 1952 */ 1953 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 1954 1955 if (*baud != baud_raw) 1956 printk(KERN_INFO "Serial: Console lpuart rounded baud rate" 1957 "from %d to %d\n", baud_raw, *baud); 1958 } 1959 1960 static void __init 1961 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 1962 int *parity, int *bits) 1963 { 1964 unsigned long cr, bd; 1965 unsigned int sbr, uartclk, baud_raw; 1966 1967 cr = lpuart32_read(&sport->port, UARTCTRL); 1968 cr &= UARTCTRL_TE | UARTCTRL_RE; 1969 if (!cr) 1970 return; 1971 1972 /* ok, the port was enabled */ 1973 1974 cr = lpuart32_read(&sport->port, UARTCTRL); 1975 1976 *parity = 'n'; 1977 if (cr & UARTCTRL_PE) { 1978 if (cr & UARTCTRL_PT) 1979 *parity = 'o'; 1980 else 1981 *parity = 'e'; 1982 } 1983 1984 if (cr & UARTCTRL_M) 1985 *bits = 9; 1986 else 1987 *bits = 8; 1988 1989 bd = lpuart32_read(&sport->port, UARTBAUD); 1990 bd &= UARTBAUD_SBR_MASK; 1991 sbr = bd; 1992 uartclk = clk_get_rate(sport->clk); 1993 /* 1994 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 1995 */ 1996 baud_raw = uartclk / (16 * sbr); 1997 1998 if (*baud != baud_raw) 1999 printk(KERN_INFO "Serial: Console lpuart rounded baud rate" 2000 "from %d to %d\n", baud_raw, *baud); 2001 } 2002 2003 static int __init lpuart_console_setup(struct console *co, char *options) 2004 { 2005 struct lpuart_port *sport; 2006 int baud = 115200; 2007 int bits = 8; 2008 int parity = 'n'; 2009 int flow = 'n'; 2010 2011 /* 2012 * check whether an invalid uart number has been specified, and 2013 * if so, search for the first available port that does have 2014 * console support. 2015 */ 2016 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2017 co->index = 0; 2018 2019 sport = lpuart_ports[co->index]; 2020 if (sport == NULL) 2021 return -ENODEV; 2022 2023 if (options) 2024 uart_parse_options(options, &baud, &parity, &bits, &flow); 2025 else 2026 if (lpuart_is_32(sport)) 2027 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2028 else 2029 lpuart_console_get_options(sport, &baud, &parity, &bits); 2030 2031 if (lpuart_is_32(sport)) 2032 lpuart32_setup_watermark(sport); 2033 else 2034 lpuart_setup_watermark(sport); 2035 2036 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2037 } 2038 2039 static struct uart_driver lpuart_reg; 2040 static struct console lpuart_console = { 2041 .name = DEV_NAME, 2042 .write = lpuart_console_write, 2043 .device = uart_console_device, 2044 .setup = lpuart_console_setup, 2045 .flags = CON_PRINTBUFFER, 2046 .index = -1, 2047 .data = &lpuart_reg, 2048 }; 2049 2050 static struct console lpuart32_console = { 2051 .name = DEV_NAME, 2052 .write = lpuart32_console_write, 2053 .device = uart_console_device, 2054 .setup = lpuart_console_setup, 2055 .flags = CON_PRINTBUFFER, 2056 .index = -1, 2057 .data = &lpuart_reg, 2058 }; 2059 2060 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2061 { 2062 struct earlycon_device *dev = con->data; 2063 2064 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2065 } 2066 2067 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2068 { 2069 struct earlycon_device *dev = con->data; 2070 2071 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2072 } 2073 2074 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2075 const char *opt) 2076 { 2077 if (!device->port.membase) 2078 return -ENODEV; 2079 2080 device->con->write = lpuart_early_write; 2081 return 0; 2082 } 2083 2084 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2085 const char *opt) 2086 { 2087 if (!device->port.membase) 2088 return -ENODEV; 2089 2090 device->port.iotype = UPIO_MEM32BE; 2091 device->con->write = lpuart32_early_write; 2092 return 0; 2093 } 2094 2095 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2096 const char *opt) 2097 { 2098 if (!device->port.membase) 2099 return -ENODEV; 2100 2101 device->port.iotype = UPIO_MEM32; 2102 device->port.membase += IMX_REG_OFF; 2103 device->con->write = lpuart32_early_write; 2104 2105 return 0; 2106 } 2107 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2108 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2109 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2110 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2111 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2112 2113 #define LPUART_CONSOLE (&lpuart_console) 2114 #define LPUART32_CONSOLE (&lpuart32_console) 2115 #else 2116 #define LPUART_CONSOLE NULL 2117 #define LPUART32_CONSOLE NULL 2118 #endif 2119 2120 static struct uart_driver lpuart_reg = { 2121 .owner = THIS_MODULE, 2122 .driver_name = DRIVER_NAME, 2123 .dev_name = DEV_NAME, 2124 .nr = ARRAY_SIZE(lpuart_ports), 2125 .cons = LPUART_CONSOLE, 2126 }; 2127 2128 static int lpuart_probe(struct platform_device *pdev) 2129 { 2130 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids, 2131 &pdev->dev); 2132 const struct lpuart_soc_data *sdata = of_id->data; 2133 struct device_node *np = pdev->dev.of_node; 2134 struct lpuart_port *sport; 2135 struct resource *res; 2136 int ret; 2137 2138 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2139 if (!sport) 2140 return -ENOMEM; 2141 2142 pdev->dev.coherent_dma_mask = 0; 2143 2144 ret = of_alias_get_id(np, "serial"); 2145 if (ret < 0) { 2146 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2147 return ret; 2148 } 2149 sport->port.line = ret; 2150 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2151 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 2152 if (IS_ERR(sport->port.membase)) 2153 return PTR_ERR(sport->port.membase); 2154 2155 sport->port.membase += sdata->reg_off; 2156 sport->port.mapbase = res->start; 2157 sport->port.dev = &pdev->dev; 2158 sport->port.type = PORT_LPUART; 2159 ret = platform_get_irq(pdev, 0); 2160 if (ret < 0) { 2161 dev_err(&pdev->dev, "cannot obtain irq\n"); 2162 return ret; 2163 } 2164 sport->port.irq = ret; 2165 sport->port.iotype = sdata->iotype; 2166 if (lpuart_is_32(sport)) 2167 sport->port.ops = &lpuart32_pops; 2168 else 2169 sport->port.ops = &lpuart_pops; 2170 sport->port.flags = UPF_BOOT_AUTOCONF; 2171 2172 sport->port.rs485_config = lpuart_config_rs485; 2173 2174 sport->clk = devm_clk_get(&pdev->dev, "ipg"); 2175 if (IS_ERR(sport->clk)) { 2176 ret = PTR_ERR(sport->clk); 2177 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret); 2178 return ret; 2179 } 2180 2181 ret = clk_prepare_enable(sport->clk); 2182 if (ret) { 2183 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret); 2184 return ret; 2185 } 2186 2187 sport->port.uartclk = clk_get_rate(sport->clk); 2188 2189 lpuart_ports[sport->port.line] = sport; 2190 2191 platform_set_drvdata(pdev, &sport->port); 2192 2193 if (lpuart_is_32(sport)) { 2194 lpuart_reg.cons = LPUART32_CONSOLE; 2195 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0, 2196 DRIVER_NAME, sport); 2197 } else { 2198 lpuart_reg.cons = LPUART_CONSOLE; 2199 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0, 2200 DRIVER_NAME, sport); 2201 } 2202 2203 if (ret) 2204 goto failed_irq_request; 2205 2206 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2207 if (ret) 2208 goto failed_attach_port; 2209 2210 of_get_rs485_mode(np, &sport->port.rs485); 2211 2212 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX) { 2213 dev_err(&pdev->dev, "driver doesn't support RX during TX\n"); 2214 return -ENOSYS; 2215 } 2216 2217 if (sport->port.rs485.delay_rts_before_send || 2218 sport->port.rs485.delay_rts_after_send) { 2219 dev_err(&pdev->dev, "driver doesn't support RTS delays\n"); 2220 return -ENOSYS; 2221 } 2222 2223 if (sport->port.rs485.flags & SER_RS485_ENABLED) { 2224 sport->port.rs485.flags |= SER_RS485_RTS_ON_SEND; 2225 writeb(UARTMODEM_TXRTSE, sport->port.membase + UARTMODEM); 2226 } 2227 2228 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx"); 2229 if (!sport->dma_tx_chan) 2230 dev_info(sport->port.dev, "DMA tx channel request failed, " 2231 "operating without tx DMA\n"); 2232 2233 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx"); 2234 if (!sport->dma_rx_chan) 2235 dev_info(sport->port.dev, "DMA rx channel request failed, " 2236 "operating without rx DMA\n"); 2237 2238 return 0; 2239 2240 failed_attach_port: 2241 failed_irq_request: 2242 clk_disable_unprepare(sport->clk); 2243 return ret; 2244 } 2245 2246 static int lpuart_remove(struct platform_device *pdev) 2247 { 2248 struct lpuart_port *sport = platform_get_drvdata(pdev); 2249 2250 uart_remove_one_port(&lpuart_reg, &sport->port); 2251 2252 clk_disable_unprepare(sport->clk); 2253 2254 if (sport->dma_tx_chan) 2255 dma_release_channel(sport->dma_tx_chan); 2256 2257 if (sport->dma_rx_chan) 2258 dma_release_channel(sport->dma_rx_chan); 2259 2260 return 0; 2261 } 2262 2263 #ifdef CONFIG_PM_SLEEP 2264 static int lpuart_suspend(struct device *dev) 2265 { 2266 struct lpuart_port *sport = dev_get_drvdata(dev); 2267 unsigned long temp; 2268 bool irq_wake; 2269 2270 if (lpuart_is_32(sport)) { 2271 /* disable Rx/Tx and interrupts */ 2272 temp = lpuart32_read(&sport->port, UARTCTRL); 2273 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2274 lpuart32_write(&sport->port, temp, UARTCTRL); 2275 } else { 2276 /* disable Rx/Tx and interrupts */ 2277 temp = readb(sport->port.membase + UARTCR2); 2278 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2279 writeb(temp, sport->port.membase + UARTCR2); 2280 } 2281 2282 uart_suspend_port(&lpuart_reg, &sport->port); 2283 2284 /* uart_suspend_port() might set wakeup flag */ 2285 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2286 2287 if (sport->lpuart_dma_rx_use) { 2288 /* 2289 * EDMA driver during suspend will forcefully release any 2290 * non-idle DMA channels. If port wakeup is enabled or if port 2291 * is console port or 'no_console_suspend' is set the Rx DMA 2292 * cannot resume as as expected, hence gracefully release the 2293 * Rx DMA path before suspend and start Rx DMA path on resume. 2294 */ 2295 if (irq_wake) { 2296 del_timer_sync(&sport->lpuart_timer); 2297 lpuart_dma_rx_free(&sport->port); 2298 } 2299 2300 /* Disable Rx DMA to use UART port as wakeup source */ 2301 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS, 2302 sport->port.membase + UARTCR5); 2303 } 2304 2305 if (sport->lpuart_dma_tx_use) { 2306 sport->dma_tx_in_progress = false; 2307 dmaengine_terminate_all(sport->dma_tx_chan); 2308 } 2309 2310 if (sport->port.suspended && !irq_wake) 2311 clk_disable_unprepare(sport->clk); 2312 2313 return 0; 2314 } 2315 2316 static int lpuart_resume(struct device *dev) 2317 { 2318 struct lpuart_port *sport = dev_get_drvdata(dev); 2319 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2320 unsigned long temp; 2321 2322 if (sport->port.suspended && !irq_wake) 2323 clk_prepare_enable(sport->clk); 2324 2325 if (lpuart_is_32(sport)) { 2326 lpuart32_setup_watermark(sport); 2327 temp = lpuart32_read(&sport->port, UARTCTRL); 2328 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | 2329 UARTCTRL_TE | UARTCTRL_ILIE); 2330 lpuart32_write(&sport->port, temp, UARTCTRL); 2331 } else { 2332 lpuart_setup_watermark(sport); 2333 temp = readb(sport->port.membase + UARTCR2); 2334 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 2335 writeb(temp, sport->port.membase + UARTCR2); 2336 } 2337 2338 if (sport->lpuart_dma_rx_use) { 2339 if (irq_wake) { 2340 if (!lpuart_start_rx_dma(sport)) 2341 rx_dma_timer_init(sport); 2342 else 2343 sport->lpuart_dma_rx_use = false; 2344 } 2345 } 2346 2347 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) { 2348 init_waitqueue_head(&sport->dma_wait); 2349 sport->lpuart_dma_tx_use = true; 2350 writeb(readb(sport->port.membase + UARTCR5) | 2351 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 2352 } else { 2353 sport->lpuart_dma_tx_use = false; 2354 } 2355 2356 uart_resume_port(&lpuart_reg, &sport->port); 2357 2358 return 0; 2359 } 2360 #endif 2361 2362 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2363 2364 static struct platform_driver lpuart_driver = { 2365 .probe = lpuart_probe, 2366 .remove = lpuart_remove, 2367 .driver = { 2368 .name = "fsl-lpuart", 2369 .of_match_table = lpuart_dt_ids, 2370 .pm = &lpuart_pm_ops, 2371 }, 2372 }; 2373 2374 static int __init lpuart_serial_init(void) 2375 { 2376 int ret = uart_register_driver(&lpuart_reg); 2377 2378 if (ret) 2379 return ret; 2380 2381 ret = platform_driver_register(&lpuart_driver); 2382 if (ret) 2383 uart_unregister_driver(&lpuart_reg); 2384 2385 return ret; 2386 } 2387 2388 static void __exit lpuart_serial_exit(void) 2389 { 2390 platform_driver_unregister(&lpuart_driver); 2391 uart_unregister_driver(&lpuart_reg); 2392 } 2393 2394 module_init(lpuart_serial_init); 2395 module_exit(lpuart_serial_exit); 2396 2397 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2398 MODULE_LICENSE("GPL v2"); 2399