1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale lpuart serial port driver 4 * 5 * Copyright 2012-2014 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/console.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/dmapool.h> 14 #include <linux/io.h> 15 #include <linux/iopoll.h> 16 #include <linux/irq.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/of_dma.h> 21 #include <linux/serial_core.h> 22 #include <linux/slab.h> 23 #include <linux/tty_flip.h> 24 25 /* All registers are 8-bit width */ 26 #define UARTBDH 0x00 27 #define UARTBDL 0x01 28 #define UARTCR1 0x02 29 #define UARTCR2 0x03 30 #define UARTSR1 0x04 31 #define UARTCR3 0x06 32 #define UARTDR 0x07 33 #define UARTCR4 0x0a 34 #define UARTCR5 0x0b 35 #define UARTMODEM 0x0d 36 #define UARTPFIFO 0x10 37 #define UARTCFIFO 0x11 38 #define UARTSFIFO 0x12 39 #define UARTTWFIFO 0x13 40 #define UARTTCFIFO 0x14 41 #define UARTRWFIFO 0x15 42 43 #define UARTBDH_LBKDIE 0x80 44 #define UARTBDH_RXEDGIE 0x40 45 #define UARTBDH_SBR_MASK 0x1f 46 47 #define UARTCR1_LOOPS 0x80 48 #define UARTCR1_RSRC 0x20 49 #define UARTCR1_M 0x10 50 #define UARTCR1_WAKE 0x08 51 #define UARTCR1_ILT 0x04 52 #define UARTCR1_PE 0x02 53 #define UARTCR1_PT 0x01 54 55 #define UARTCR2_TIE 0x80 56 #define UARTCR2_TCIE 0x40 57 #define UARTCR2_RIE 0x20 58 #define UARTCR2_ILIE 0x10 59 #define UARTCR2_TE 0x08 60 #define UARTCR2_RE 0x04 61 #define UARTCR2_RWU 0x02 62 #define UARTCR2_SBK 0x01 63 64 #define UARTSR1_TDRE 0x80 65 #define UARTSR1_TC 0x40 66 #define UARTSR1_RDRF 0x20 67 #define UARTSR1_IDLE 0x10 68 #define UARTSR1_OR 0x08 69 #define UARTSR1_NF 0x04 70 #define UARTSR1_FE 0x02 71 #define UARTSR1_PE 0x01 72 73 #define UARTCR3_R8 0x80 74 #define UARTCR3_T8 0x40 75 #define UARTCR3_TXDIR 0x20 76 #define UARTCR3_TXINV 0x10 77 #define UARTCR3_ORIE 0x08 78 #define UARTCR3_NEIE 0x04 79 #define UARTCR3_FEIE 0x02 80 #define UARTCR3_PEIE 0x01 81 82 #define UARTCR4_MAEN1 0x80 83 #define UARTCR4_MAEN2 0x40 84 #define UARTCR4_M10 0x20 85 #define UARTCR4_BRFA_MASK 0x1f 86 #define UARTCR4_BRFA_OFF 0 87 88 #define UARTCR5_TDMAS 0x80 89 #define UARTCR5_RDMAS 0x20 90 91 #define UARTMODEM_RXRTSE 0x08 92 #define UARTMODEM_TXRTSPOL 0x04 93 #define UARTMODEM_TXRTSE 0x02 94 #define UARTMODEM_TXCTSE 0x01 95 96 #define UARTPFIFO_TXFE 0x80 97 #define UARTPFIFO_FIFOSIZE_MASK 0x7 98 #define UARTPFIFO_TXSIZE_OFF 4 99 #define UARTPFIFO_RXFE 0x08 100 #define UARTPFIFO_RXSIZE_OFF 0 101 102 #define UARTCFIFO_TXFLUSH 0x80 103 #define UARTCFIFO_RXFLUSH 0x40 104 #define UARTCFIFO_RXOFE 0x04 105 #define UARTCFIFO_TXOFE 0x02 106 #define UARTCFIFO_RXUFE 0x01 107 108 #define UARTSFIFO_TXEMPT 0x80 109 #define UARTSFIFO_RXEMPT 0x40 110 #define UARTSFIFO_RXOF 0x04 111 #define UARTSFIFO_TXOF 0x02 112 #define UARTSFIFO_RXUF 0x01 113 114 /* 32-bit global registers only for i.MX7ULP/i.MX8x 115 * Used to reset all internal logic and registers, except the Global Register. 116 */ 117 #define UART_GLOBAL 0x8 118 119 /* 32-bit register definition */ 120 #define UARTBAUD 0x00 121 #define UARTSTAT 0x04 122 #define UARTCTRL 0x08 123 #define UARTDATA 0x0C 124 #define UARTMATCH 0x10 125 #define UARTMODIR 0x14 126 #define UARTFIFO 0x18 127 #define UARTWATER 0x1c 128 129 #define UARTBAUD_MAEN1 0x80000000 130 #define UARTBAUD_MAEN2 0x40000000 131 #define UARTBAUD_M10 0x20000000 132 #define UARTBAUD_TDMAE 0x00800000 133 #define UARTBAUD_RDMAE 0x00200000 134 #define UARTBAUD_MATCFG 0x00400000 135 #define UARTBAUD_BOTHEDGE 0x00020000 136 #define UARTBAUD_RESYNCDIS 0x00010000 137 #define UARTBAUD_LBKDIE 0x00008000 138 #define UARTBAUD_RXEDGIE 0x00004000 139 #define UARTBAUD_SBNS 0x00002000 140 #define UARTBAUD_SBR 0x00000000 141 #define UARTBAUD_SBR_MASK 0x1fff 142 #define UARTBAUD_OSR_MASK 0x1f 143 #define UARTBAUD_OSR_SHIFT 24 144 145 #define UARTSTAT_LBKDIF 0x80000000 146 #define UARTSTAT_RXEDGIF 0x40000000 147 #define UARTSTAT_MSBF 0x20000000 148 #define UARTSTAT_RXINV 0x10000000 149 #define UARTSTAT_RWUID 0x08000000 150 #define UARTSTAT_BRK13 0x04000000 151 #define UARTSTAT_LBKDE 0x02000000 152 #define UARTSTAT_RAF 0x01000000 153 #define UARTSTAT_TDRE 0x00800000 154 #define UARTSTAT_TC 0x00400000 155 #define UARTSTAT_RDRF 0x00200000 156 #define UARTSTAT_IDLE 0x00100000 157 #define UARTSTAT_OR 0x00080000 158 #define UARTSTAT_NF 0x00040000 159 #define UARTSTAT_FE 0x00020000 160 #define UARTSTAT_PE 0x00010000 161 #define UARTSTAT_MA1F 0x00008000 162 #define UARTSTAT_M21F 0x00004000 163 164 #define UARTCTRL_R8T9 0x80000000 165 #define UARTCTRL_R9T8 0x40000000 166 #define UARTCTRL_TXDIR 0x20000000 167 #define UARTCTRL_TXINV 0x10000000 168 #define UARTCTRL_ORIE 0x08000000 169 #define UARTCTRL_NEIE 0x04000000 170 #define UARTCTRL_FEIE 0x02000000 171 #define UARTCTRL_PEIE 0x01000000 172 #define UARTCTRL_TIE 0x00800000 173 #define UARTCTRL_TCIE 0x00400000 174 #define UARTCTRL_RIE 0x00200000 175 #define UARTCTRL_ILIE 0x00100000 176 #define UARTCTRL_TE 0x00080000 177 #define UARTCTRL_RE 0x00040000 178 #define UARTCTRL_RWU 0x00020000 179 #define UARTCTRL_SBK 0x00010000 180 #define UARTCTRL_MA1IE 0x00008000 181 #define UARTCTRL_MA2IE 0x00004000 182 #define UARTCTRL_IDLECFG 0x00000100 183 #define UARTCTRL_LOOPS 0x00000080 184 #define UARTCTRL_DOZEEN 0x00000040 185 #define UARTCTRL_RSRC 0x00000020 186 #define UARTCTRL_M 0x00000010 187 #define UARTCTRL_WAKE 0x00000008 188 #define UARTCTRL_ILT 0x00000004 189 #define UARTCTRL_PE 0x00000002 190 #define UARTCTRL_PT 0x00000001 191 192 #define UARTDATA_NOISY 0x00008000 193 #define UARTDATA_PARITYE 0x00004000 194 #define UARTDATA_FRETSC 0x00002000 195 #define UARTDATA_RXEMPT 0x00001000 196 #define UARTDATA_IDLINE 0x00000800 197 #define UARTDATA_MASK 0x3ff 198 199 #define UARTMODIR_IREN 0x00020000 200 #define UARTMODIR_TXCTSSRC 0x00000020 201 #define UARTMODIR_TXCTSC 0x00000010 202 #define UARTMODIR_RXRTSE 0x00000008 203 #define UARTMODIR_TXRTSPOL 0x00000004 204 #define UARTMODIR_TXRTSE 0x00000002 205 #define UARTMODIR_TXCTSE 0x00000001 206 207 #define UARTFIFO_TXEMPT 0x00800000 208 #define UARTFIFO_RXEMPT 0x00400000 209 #define UARTFIFO_TXOF 0x00020000 210 #define UARTFIFO_RXUF 0x00010000 211 #define UARTFIFO_TXFLUSH 0x00008000 212 #define UARTFIFO_RXFLUSH 0x00004000 213 #define UARTFIFO_TXOFE 0x00000200 214 #define UARTFIFO_RXUFE 0x00000100 215 #define UARTFIFO_TXFE 0x00000080 216 #define UARTFIFO_FIFOSIZE_MASK 0x7 217 #define UARTFIFO_TXSIZE_OFF 4 218 #define UARTFIFO_RXFE 0x00000008 219 #define UARTFIFO_RXSIZE_OFF 0 220 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0)) 221 222 #define UARTWATER_COUNT_MASK 0xff 223 #define UARTWATER_TXCNT_OFF 8 224 #define UARTWATER_RXCNT_OFF 24 225 #define UARTWATER_WATER_MASK 0xff 226 #define UARTWATER_TXWATER_OFF 0 227 #define UARTWATER_RXWATER_OFF 16 228 229 #define UART_GLOBAL_RST 0x2 230 #define GLOBAL_RST_MIN_US 20 231 #define GLOBAL_RST_MAX_US 40 232 233 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 234 #define DMA_RX_TIMEOUT (10) 235 236 #define DRIVER_NAME "fsl-lpuart" 237 #define DEV_NAME "ttyLP" 238 #define UART_NR 6 239 240 /* IMX lpuart has four extra unused regs located at the beginning */ 241 #define IMX_REG_OFF 0x10 242 243 enum lpuart_type { 244 VF610_LPUART, 245 LS1021A_LPUART, 246 LS1028A_LPUART, 247 IMX7ULP_LPUART, 248 IMX8QXP_LPUART, 249 IMXRT1050_LPUART, 250 }; 251 252 struct lpuart_port { 253 struct uart_port port; 254 enum lpuart_type devtype; 255 struct clk *ipg_clk; 256 struct clk *baud_clk; 257 unsigned int txfifo_size; 258 unsigned int rxfifo_size; 259 260 bool lpuart_dma_tx_use; 261 bool lpuart_dma_rx_use; 262 struct dma_chan *dma_tx_chan; 263 struct dma_chan *dma_rx_chan; 264 struct dma_async_tx_descriptor *dma_tx_desc; 265 struct dma_async_tx_descriptor *dma_rx_desc; 266 dma_cookie_t dma_tx_cookie; 267 dma_cookie_t dma_rx_cookie; 268 unsigned int dma_tx_bytes; 269 unsigned int dma_rx_bytes; 270 bool dma_tx_in_progress; 271 unsigned int dma_rx_timeout; 272 struct timer_list lpuart_timer; 273 struct scatterlist rx_sgl, tx_sgl[2]; 274 struct circ_buf rx_ring; 275 int rx_dma_rng_buf_len; 276 unsigned int dma_tx_nents; 277 wait_queue_head_t dma_wait; 278 bool is_cs7; /* Set to true when character size is 7 */ 279 /* and the parity is enabled */ 280 }; 281 282 struct lpuart_soc_data { 283 enum lpuart_type devtype; 284 char iotype; 285 u8 reg_off; 286 }; 287 288 static const struct lpuart_soc_data vf_data = { 289 .devtype = VF610_LPUART, 290 .iotype = UPIO_MEM, 291 }; 292 293 static const struct lpuart_soc_data ls1021a_data = { 294 .devtype = LS1021A_LPUART, 295 .iotype = UPIO_MEM32BE, 296 }; 297 298 static const struct lpuart_soc_data ls1028a_data = { 299 .devtype = LS1028A_LPUART, 300 .iotype = UPIO_MEM32, 301 }; 302 303 static struct lpuart_soc_data imx7ulp_data = { 304 .devtype = IMX7ULP_LPUART, 305 .iotype = UPIO_MEM32, 306 .reg_off = IMX_REG_OFF, 307 }; 308 309 static struct lpuart_soc_data imx8qxp_data = { 310 .devtype = IMX8QXP_LPUART, 311 .iotype = UPIO_MEM32, 312 .reg_off = IMX_REG_OFF, 313 }; 314 static struct lpuart_soc_data imxrt1050_data = { 315 .devtype = IMXRT1050_LPUART, 316 .iotype = UPIO_MEM32, 317 .reg_off = IMX_REG_OFF, 318 }; 319 320 static const struct of_device_id lpuart_dt_ids[] = { 321 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 322 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, }, 323 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, }, 324 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, 325 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, 326 { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data}, 327 { /* sentinel */ } 328 }; 329 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 330 331 /* Forward declare this for the dma callbacks*/ 332 static void lpuart_dma_tx_complete(void *arg); 333 334 static inline bool is_layerscape_lpuart(struct lpuart_port *sport) 335 { 336 return (sport->devtype == LS1021A_LPUART || 337 sport->devtype == LS1028A_LPUART); 338 } 339 340 static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport) 341 { 342 return sport->devtype == IMX7ULP_LPUART; 343 } 344 345 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) 346 { 347 return sport->devtype == IMX8QXP_LPUART; 348 } 349 350 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 351 { 352 switch (port->iotype) { 353 case UPIO_MEM32: 354 return readl(port->membase + off); 355 case UPIO_MEM32BE: 356 return ioread32be(port->membase + off); 357 default: 358 return 0; 359 } 360 } 361 362 static inline void lpuart32_write(struct uart_port *port, u32 val, 363 u32 off) 364 { 365 switch (port->iotype) { 366 case UPIO_MEM32: 367 writel(val, port->membase + off); 368 break; 369 case UPIO_MEM32BE: 370 iowrite32be(val, port->membase + off); 371 break; 372 } 373 } 374 375 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) 376 { 377 int ret = 0; 378 379 if (is_en) { 380 ret = clk_prepare_enable(sport->ipg_clk); 381 if (ret) 382 return ret; 383 384 ret = clk_prepare_enable(sport->baud_clk); 385 if (ret) { 386 clk_disable_unprepare(sport->ipg_clk); 387 return ret; 388 } 389 } else { 390 clk_disable_unprepare(sport->baud_clk); 391 clk_disable_unprepare(sport->ipg_clk); 392 } 393 394 return 0; 395 } 396 397 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) 398 { 399 if (is_imx8qxp_lpuart(sport)) 400 return clk_get_rate(sport->baud_clk); 401 402 return clk_get_rate(sport->ipg_clk); 403 } 404 405 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true) 406 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false) 407 408 static void lpuart_stop_tx(struct uart_port *port) 409 { 410 unsigned char temp; 411 412 temp = readb(port->membase + UARTCR2); 413 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 414 writeb(temp, port->membase + UARTCR2); 415 } 416 417 static void lpuart32_stop_tx(struct uart_port *port) 418 { 419 unsigned long temp; 420 421 temp = lpuart32_read(port, UARTCTRL); 422 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 423 lpuart32_write(port, temp, UARTCTRL); 424 } 425 426 static void lpuart_stop_rx(struct uart_port *port) 427 { 428 unsigned char temp; 429 430 temp = readb(port->membase + UARTCR2); 431 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 432 } 433 434 static void lpuart32_stop_rx(struct uart_port *port) 435 { 436 unsigned long temp; 437 438 temp = lpuart32_read(port, UARTCTRL); 439 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); 440 } 441 442 static void lpuart_dma_tx(struct lpuart_port *sport) 443 { 444 struct circ_buf *xmit = &sport->port.state->xmit; 445 struct scatterlist *sgl = sport->tx_sgl; 446 struct device *dev = sport->port.dev; 447 struct dma_chan *chan = sport->dma_tx_chan; 448 int ret; 449 450 if (sport->dma_tx_in_progress) 451 return; 452 453 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 454 455 if (xmit->tail < xmit->head || xmit->head == 0) { 456 sport->dma_tx_nents = 1; 457 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 458 } else { 459 sport->dma_tx_nents = 2; 460 sg_init_table(sgl, 2); 461 sg_set_buf(sgl, xmit->buf + xmit->tail, 462 UART_XMIT_SIZE - xmit->tail); 463 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 464 } 465 466 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, 467 DMA_TO_DEVICE); 468 if (!ret) { 469 dev_err(dev, "DMA mapping error for TX.\n"); 470 return; 471 } 472 473 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, 474 ret, DMA_MEM_TO_DEV, 475 DMA_PREP_INTERRUPT); 476 if (!sport->dma_tx_desc) { 477 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 478 DMA_TO_DEVICE); 479 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 480 return; 481 } 482 483 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 484 sport->dma_tx_desc->callback_param = sport; 485 sport->dma_tx_in_progress = true; 486 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 487 dma_async_issue_pending(chan); 488 } 489 490 static bool lpuart_stopped_or_empty(struct uart_port *port) 491 { 492 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); 493 } 494 495 static void lpuart_dma_tx_complete(void *arg) 496 { 497 struct lpuart_port *sport = arg; 498 struct scatterlist *sgl = &sport->tx_sgl[0]; 499 struct circ_buf *xmit = &sport->port.state->xmit; 500 struct dma_chan *chan = sport->dma_tx_chan; 501 unsigned long flags; 502 503 spin_lock_irqsave(&sport->port.lock, flags); 504 if (!sport->dma_tx_in_progress) { 505 spin_unlock_irqrestore(&sport->port.lock, flags); 506 return; 507 } 508 509 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 510 DMA_TO_DEVICE); 511 512 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 513 514 sport->port.icount.tx += sport->dma_tx_bytes; 515 sport->dma_tx_in_progress = false; 516 spin_unlock_irqrestore(&sport->port.lock, flags); 517 518 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 519 uart_write_wakeup(&sport->port); 520 521 if (waitqueue_active(&sport->dma_wait)) { 522 wake_up(&sport->dma_wait); 523 return; 524 } 525 526 spin_lock_irqsave(&sport->port.lock, flags); 527 528 if (!lpuart_stopped_or_empty(&sport->port)) 529 lpuart_dma_tx(sport); 530 531 spin_unlock_irqrestore(&sport->port.lock, flags); 532 } 533 534 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) 535 { 536 switch (sport->port.iotype) { 537 case UPIO_MEM32: 538 return sport->port.mapbase + UARTDATA; 539 case UPIO_MEM32BE: 540 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; 541 } 542 return sport->port.mapbase + UARTDR; 543 } 544 545 static int lpuart_dma_tx_request(struct uart_port *port) 546 { 547 struct lpuart_port *sport = container_of(port, 548 struct lpuart_port, port); 549 struct dma_slave_config dma_tx_sconfig = {}; 550 int ret; 551 552 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); 553 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 554 dma_tx_sconfig.dst_maxburst = 1; 555 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 556 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 557 558 if (ret) { 559 dev_err(sport->port.dev, 560 "DMA slave config failed, err = %d\n", ret); 561 return ret; 562 } 563 564 return 0; 565 } 566 567 static bool lpuart_is_32(struct lpuart_port *sport) 568 { 569 return sport->port.iotype == UPIO_MEM32 || 570 sport->port.iotype == UPIO_MEM32BE; 571 } 572 573 static void lpuart_flush_buffer(struct uart_port *port) 574 { 575 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 576 struct dma_chan *chan = sport->dma_tx_chan; 577 u32 val; 578 579 if (sport->lpuart_dma_tx_use) { 580 if (sport->dma_tx_in_progress) { 581 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], 582 sport->dma_tx_nents, DMA_TO_DEVICE); 583 sport->dma_tx_in_progress = false; 584 } 585 dmaengine_terminate_all(chan); 586 } 587 588 if (lpuart_is_32(sport)) { 589 val = lpuart32_read(&sport->port, UARTFIFO); 590 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 591 lpuart32_write(&sport->port, val, UARTFIFO); 592 } else { 593 val = readb(sport->port.membase + UARTCFIFO); 594 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; 595 writeb(val, sport->port.membase + UARTCFIFO); 596 } 597 } 598 599 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset, 600 u8 bit) 601 { 602 while (!(readb(port->membase + offset) & bit)) 603 cpu_relax(); 604 } 605 606 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset, 607 u32 bit) 608 { 609 while (!(lpuart32_read(port, offset) & bit)) 610 cpu_relax(); 611 } 612 613 #if defined(CONFIG_CONSOLE_POLL) 614 615 static int lpuart_poll_init(struct uart_port *port) 616 { 617 struct lpuart_port *sport = container_of(port, 618 struct lpuart_port, port); 619 unsigned long flags; 620 unsigned char temp; 621 622 sport->port.fifosize = 0; 623 624 spin_lock_irqsave(&sport->port.lock, flags); 625 /* Disable Rx & Tx */ 626 writeb(0, sport->port.membase + UARTCR2); 627 628 temp = readb(sport->port.membase + UARTPFIFO); 629 /* Enable Rx and Tx FIFO */ 630 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 631 sport->port.membase + UARTPFIFO); 632 633 /* flush Tx and Rx FIFO */ 634 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 635 sport->port.membase + UARTCFIFO); 636 637 /* explicitly clear RDRF */ 638 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 639 readb(sport->port.membase + UARTDR); 640 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 641 } 642 643 writeb(0, sport->port.membase + UARTTWFIFO); 644 writeb(1, sport->port.membase + UARTRWFIFO); 645 646 /* Enable Rx and Tx */ 647 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 648 spin_unlock_irqrestore(&sport->port.lock, flags); 649 650 return 0; 651 } 652 653 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 654 { 655 /* drain */ 656 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 657 writeb(c, port->membase + UARTDR); 658 } 659 660 static int lpuart_poll_get_char(struct uart_port *port) 661 { 662 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 663 return NO_POLL_CHAR; 664 665 return readb(port->membase + UARTDR); 666 } 667 668 static int lpuart32_poll_init(struct uart_port *port) 669 { 670 unsigned long flags; 671 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 672 u32 temp; 673 674 sport->port.fifosize = 0; 675 676 spin_lock_irqsave(&sport->port.lock, flags); 677 678 /* Disable Rx & Tx */ 679 lpuart32_write(&sport->port, 0, UARTCTRL); 680 681 temp = lpuart32_read(&sport->port, UARTFIFO); 682 683 /* Enable Rx and Tx FIFO */ 684 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); 685 686 /* flush Tx and Rx FIFO */ 687 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); 688 689 /* explicitly clear RDRF */ 690 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { 691 lpuart32_read(&sport->port, UARTDATA); 692 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); 693 } 694 695 /* Enable Rx and Tx */ 696 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); 697 spin_unlock_irqrestore(&sport->port.lock, flags); 698 699 return 0; 700 } 701 702 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 703 { 704 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 705 lpuart32_write(port, c, UARTDATA); 706 } 707 708 static int lpuart32_poll_get_char(struct uart_port *port) 709 { 710 if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF)) 711 return NO_POLL_CHAR; 712 713 return lpuart32_read(port, UARTDATA); 714 } 715 #endif 716 717 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 718 { 719 struct circ_buf *xmit = &sport->port.state->xmit; 720 721 if (sport->port.x_char) { 722 writeb(sport->port.x_char, sport->port.membase + UARTDR); 723 sport->port.icount.tx++; 724 sport->port.x_char = 0; 725 return; 726 } 727 728 if (lpuart_stopped_or_empty(&sport->port)) { 729 lpuart_stop_tx(&sport->port); 730 return; 731 } 732 733 while (!uart_circ_empty(xmit) && 734 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 735 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 736 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 737 sport->port.icount.tx++; 738 } 739 740 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 741 uart_write_wakeup(&sport->port); 742 743 if (uart_circ_empty(xmit)) 744 lpuart_stop_tx(&sport->port); 745 } 746 747 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 748 { 749 struct circ_buf *xmit = &sport->port.state->xmit; 750 unsigned long txcnt; 751 752 if (sport->port.x_char) { 753 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 754 sport->port.icount.tx++; 755 sport->port.x_char = 0; 756 return; 757 } 758 759 if (lpuart_stopped_or_empty(&sport->port)) { 760 lpuart32_stop_tx(&sport->port); 761 return; 762 } 763 764 txcnt = lpuart32_read(&sport->port, UARTWATER); 765 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 766 txcnt &= UARTWATER_COUNT_MASK; 767 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 768 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); 769 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 770 sport->port.icount.tx++; 771 txcnt = lpuart32_read(&sport->port, UARTWATER); 772 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 773 txcnt &= UARTWATER_COUNT_MASK; 774 } 775 776 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 777 uart_write_wakeup(&sport->port); 778 779 if (uart_circ_empty(xmit)) 780 lpuart32_stop_tx(&sport->port); 781 } 782 783 static void lpuart_start_tx(struct uart_port *port) 784 { 785 struct lpuart_port *sport = container_of(port, 786 struct lpuart_port, port); 787 unsigned char temp; 788 789 temp = readb(port->membase + UARTCR2); 790 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 791 792 if (sport->lpuart_dma_tx_use) { 793 if (!lpuart_stopped_or_empty(port)) 794 lpuart_dma_tx(sport); 795 } else { 796 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 797 lpuart_transmit_buffer(sport); 798 } 799 } 800 801 static void lpuart32_start_tx(struct uart_port *port) 802 { 803 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 804 unsigned long temp; 805 806 if (sport->lpuart_dma_tx_use) { 807 if (!lpuart_stopped_or_empty(port)) 808 lpuart_dma_tx(sport); 809 } else { 810 temp = lpuart32_read(port, UARTCTRL); 811 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); 812 813 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 814 lpuart32_transmit_buffer(sport); 815 } 816 } 817 818 /* return TIOCSER_TEMT when transmitter is not busy */ 819 static unsigned int lpuart_tx_empty(struct uart_port *port) 820 { 821 struct lpuart_port *sport = container_of(port, 822 struct lpuart_port, port); 823 unsigned char sr1 = readb(port->membase + UARTSR1); 824 unsigned char sfifo = readb(port->membase + UARTSFIFO); 825 826 if (sport->dma_tx_in_progress) 827 return 0; 828 829 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 830 return TIOCSER_TEMT; 831 832 return 0; 833 } 834 835 static unsigned int lpuart32_tx_empty(struct uart_port *port) 836 { 837 struct lpuart_port *sport = container_of(port, 838 struct lpuart_port, port); 839 unsigned long stat = lpuart32_read(port, UARTSTAT); 840 unsigned long sfifo = lpuart32_read(port, UARTFIFO); 841 842 if (sport->dma_tx_in_progress) 843 return 0; 844 845 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) 846 return TIOCSER_TEMT; 847 848 return 0; 849 } 850 851 static void lpuart_txint(struct lpuart_port *sport) 852 { 853 spin_lock(&sport->port.lock); 854 lpuart_transmit_buffer(sport); 855 spin_unlock(&sport->port.lock); 856 } 857 858 static void lpuart_rxint(struct lpuart_port *sport) 859 { 860 unsigned int flg, ignored = 0, overrun = 0; 861 struct tty_port *port = &sport->port.state->port; 862 unsigned char rx, sr; 863 864 spin_lock(&sport->port.lock); 865 866 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 867 flg = TTY_NORMAL; 868 sport->port.icount.rx++; 869 /* 870 * to clear the FE, OR, NF, FE, PE flags, 871 * read SR1 then read DR 872 */ 873 sr = readb(sport->port.membase + UARTSR1); 874 rx = readb(sport->port.membase + UARTDR); 875 876 if (uart_prepare_sysrq_char(&sport->port, rx)) 877 continue; 878 879 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 880 if (sr & UARTSR1_PE) 881 sport->port.icount.parity++; 882 else if (sr & UARTSR1_FE) 883 sport->port.icount.frame++; 884 885 if (sr & UARTSR1_OR) 886 overrun++; 887 888 if (sr & sport->port.ignore_status_mask) { 889 if (++ignored > 100) 890 goto out; 891 continue; 892 } 893 894 sr &= sport->port.read_status_mask; 895 896 if (sr & UARTSR1_PE) 897 flg = TTY_PARITY; 898 else if (sr & UARTSR1_FE) 899 flg = TTY_FRAME; 900 901 if (sr & UARTSR1_OR) 902 flg = TTY_OVERRUN; 903 904 sport->port.sysrq = 0; 905 } 906 907 if (tty_insert_flip_char(port, rx, flg) == 0) 908 sport->port.icount.buf_overrun++; 909 } 910 911 out: 912 if (overrun) { 913 sport->port.icount.overrun += overrun; 914 915 /* 916 * Overruns cause FIFO pointers to become missaligned. 917 * Flushing the receive FIFO reinitializes the pointers. 918 */ 919 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 920 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); 921 } 922 923 uart_unlock_and_check_sysrq(&sport->port); 924 925 tty_flip_buffer_push(port); 926 } 927 928 static void lpuart32_txint(struct lpuart_port *sport) 929 { 930 spin_lock(&sport->port.lock); 931 lpuart32_transmit_buffer(sport); 932 spin_unlock(&sport->port.lock); 933 } 934 935 static void lpuart32_rxint(struct lpuart_port *sport) 936 { 937 unsigned int flg, ignored = 0; 938 struct tty_port *port = &sport->port.state->port; 939 unsigned long rx, sr; 940 bool is_break; 941 942 spin_lock(&sport->port.lock); 943 944 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 945 flg = TTY_NORMAL; 946 sport->port.icount.rx++; 947 /* 948 * to clear the FE, OR, NF, FE, PE flags, 949 * read STAT then read DATA reg 950 */ 951 sr = lpuart32_read(&sport->port, UARTSTAT); 952 rx = lpuart32_read(&sport->port, UARTDATA); 953 rx &= UARTDATA_MASK; 954 955 /* 956 * The LPUART can't distinguish between a break and a framing error, 957 * thus we assume it is a break if the received data is zero. 958 */ 959 is_break = (sr & UARTSTAT_FE) && !rx; 960 961 if (is_break && uart_handle_break(&sport->port)) 962 continue; 963 964 if (uart_prepare_sysrq_char(&sport->port, rx)) 965 continue; 966 967 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 968 if (sr & UARTSTAT_PE) { 969 sport->port.icount.parity++; 970 } else if (sr & UARTSTAT_FE) { 971 if (is_break) 972 sport->port.icount.brk++; 973 else 974 sport->port.icount.frame++; 975 } 976 977 if (sr & UARTSTAT_OR) 978 sport->port.icount.overrun++; 979 980 if (sr & sport->port.ignore_status_mask) { 981 if (++ignored > 100) 982 goto out; 983 continue; 984 } 985 986 sr &= sport->port.read_status_mask; 987 988 if (sr & UARTSTAT_PE) { 989 flg = TTY_PARITY; 990 } else if (sr & UARTSTAT_FE) { 991 if (is_break) 992 flg = TTY_BREAK; 993 else 994 flg = TTY_FRAME; 995 } 996 997 if (sr & UARTSTAT_OR) 998 flg = TTY_OVERRUN; 999 } 1000 1001 if (sport->is_cs7) 1002 rx &= 0x7F; 1003 1004 if (tty_insert_flip_char(port, rx, flg) == 0) 1005 sport->port.icount.buf_overrun++; 1006 } 1007 1008 out: 1009 uart_unlock_and_check_sysrq(&sport->port); 1010 1011 tty_flip_buffer_push(port); 1012 } 1013 1014 static irqreturn_t lpuart_int(int irq, void *dev_id) 1015 { 1016 struct lpuart_port *sport = dev_id; 1017 unsigned char sts; 1018 1019 sts = readb(sport->port.membase + UARTSR1); 1020 1021 /* SysRq, using dma, check for linebreak by framing err. */ 1022 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { 1023 readb(sport->port.membase + UARTDR); 1024 uart_handle_break(&sport->port); 1025 /* linebreak produces some garbage, removing it */ 1026 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 1027 return IRQ_HANDLED; 1028 } 1029 1030 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) 1031 lpuart_rxint(sport); 1032 1033 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) 1034 lpuart_txint(sport); 1035 1036 return IRQ_HANDLED; 1037 } 1038 1039 static irqreturn_t lpuart32_int(int irq, void *dev_id) 1040 { 1041 struct lpuart_port *sport = dev_id; 1042 unsigned long sts, rxcount; 1043 1044 sts = lpuart32_read(&sport->port, UARTSTAT); 1045 rxcount = lpuart32_read(&sport->port, UARTWATER); 1046 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 1047 1048 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) 1049 lpuart32_rxint(sport); 1050 1051 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) 1052 lpuart32_txint(sport); 1053 1054 lpuart32_write(&sport->port, sts, UARTSTAT); 1055 return IRQ_HANDLED; 1056 } 1057 1058 1059 static inline void lpuart_handle_sysrq_chars(struct uart_port *port, 1060 unsigned char *p, int count) 1061 { 1062 while (count--) { 1063 if (*p && uart_handle_sysrq_char(port, *p)) 1064 return; 1065 p++; 1066 } 1067 } 1068 1069 static void lpuart_handle_sysrq(struct lpuart_port *sport) 1070 { 1071 struct circ_buf *ring = &sport->rx_ring; 1072 int count; 1073 1074 if (ring->head < ring->tail) { 1075 count = sport->rx_sgl.length - ring->tail; 1076 lpuart_handle_sysrq_chars(&sport->port, 1077 ring->buf + ring->tail, count); 1078 ring->tail = 0; 1079 } 1080 1081 if (ring->head > ring->tail) { 1082 count = ring->head - ring->tail; 1083 lpuart_handle_sysrq_chars(&sport->port, 1084 ring->buf + ring->tail, count); 1085 ring->tail = ring->head; 1086 } 1087 } 1088 1089 static int lpuart_tty_insert_flip_string(struct tty_port *port, 1090 unsigned char *chars, size_t size, bool is_cs7) 1091 { 1092 int i; 1093 1094 if (is_cs7) 1095 for (i = 0; i < size; i++) 1096 chars[i] &= 0x7F; 1097 return tty_insert_flip_string(port, chars, size); 1098 } 1099 1100 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 1101 { 1102 struct tty_port *port = &sport->port.state->port; 1103 struct dma_tx_state state; 1104 enum dma_status dmastat; 1105 struct dma_chan *chan = sport->dma_rx_chan; 1106 struct circ_buf *ring = &sport->rx_ring; 1107 unsigned long flags; 1108 int count, copied; 1109 1110 if (lpuart_is_32(sport)) { 1111 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); 1112 1113 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { 1114 /* Read DR to clear the error flags */ 1115 lpuart32_read(&sport->port, UARTDATA); 1116 1117 if (sr & UARTSTAT_PE) 1118 sport->port.icount.parity++; 1119 else if (sr & UARTSTAT_FE) 1120 sport->port.icount.frame++; 1121 } 1122 } else { 1123 unsigned char sr = readb(sport->port.membase + UARTSR1); 1124 1125 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 1126 unsigned char cr2; 1127 1128 /* Disable receiver during this operation... */ 1129 cr2 = readb(sport->port.membase + UARTCR2); 1130 cr2 &= ~UARTCR2_RE; 1131 writeb(cr2, sport->port.membase + UARTCR2); 1132 1133 /* Read DR to clear the error flags */ 1134 readb(sport->port.membase + UARTDR); 1135 1136 if (sr & UARTSR1_PE) 1137 sport->port.icount.parity++; 1138 else if (sr & UARTSR1_FE) 1139 sport->port.icount.frame++; 1140 /* 1141 * At this point parity/framing error is 1142 * cleared However, since the DMA already read 1143 * the data register and we had to read it 1144 * again after reading the status register to 1145 * properly clear the flags, the FIFO actually 1146 * underflowed... This requires a clearing of 1147 * the FIFO... 1148 */ 1149 if (readb(sport->port.membase + UARTSFIFO) & 1150 UARTSFIFO_RXUF) { 1151 writeb(UARTSFIFO_RXUF, 1152 sport->port.membase + UARTSFIFO); 1153 writeb(UARTCFIFO_RXFLUSH, 1154 sport->port.membase + UARTCFIFO); 1155 } 1156 1157 cr2 |= UARTCR2_RE; 1158 writeb(cr2, sport->port.membase + UARTCR2); 1159 } 1160 } 1161 1162 async_tx_ack(sport->dma_rx_desc); 1163 1164 spin_lock_irqsave(&sport->port.lock, flags); 1165 1166 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1167 if (dmastat == DMA_ERROR) { 1168 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1169 spin_unlock_irqrestore(&sport->port.lock, flags); 1170 return; 1171 } 1172 1173 /* CPU claims ownership of RX DMA buffer */ 1174 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, 1175 DMA_FROM_DEVICE); 1176 1177 /* 1178 * ring->head points to the end of data already written by the DMA. 1179 * ring->tail points to the beginning of data to be read by the 1180 * framework. 1181 * The current transfer size should not be larger than the dma buffer 1182 * length. 1183 */ 1184 ring->head = sport->rx_sgl.length - state.residue; 1185 BUG_ON(ring->head > sport->rx_sgl.length); 1186 1187 /* 1188 * Silent handling of keys pressed in the sysrq timeframe 1189 */ 1190 if (sport->port.sysrq) { 1191 lpuart_handle_sysrq(sport); 1192 goto exit; 1193 } 1194 1195 /* 1196 * At this point ring->head may point to the first byte right after the 1197 * last byte of the dma buffer: 1198 * 0 <= ring->head <= sport->rx_sgl.length 1199 * 1200 * However ring->tail must always points inside the dma buffer: 1201 * 0 <= ring->tail <= sport->rx_sgl.length - 1 1202 * 1203 * Since we use a ring buffer, we have to handle the case 1204 * where head is lower than tail. In such a case, we first read from 1205 * tail to the end of the buffer then reset tail. 1206 */ 1207 if (ring->head < ring->tail) { 1208 count = sport->rx_sgl.length - ring->tail; 1209 1210 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, 1211 count, sport->is_cs7); 1212 if (copied != count) 1213 sport->port.icount.buf_overrun++; 1214 ring->tail = 0; 1215 sport->port.icount.rx += copied; 1216 } 1217 1218 /* Finally we read data from tail to head */ 1219 if (ring->tail < ring->head) { 1220 count = ring->head - ring->tail; 1221 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, 1222 count, sport->is_cs7); 1223 if (copied != count) 1224 sport->port.icount.buf_overrun++; 1225 /* Wrap ring->head if needed */ 1226 if (ring->head >= sport->rx_sgl.length) 1227 ring->head = 0; 1228 ring->tail = ring->head; 1229 sport->port.icount.rx += copied; 1230 } 1231 1232 exit: 1233 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, 1234 DMA_FROM_DEVICE); 1235 1236 spin_unlock_irqrestore(&sport->port.lock, flags); 1237 1238 tty_flip_buffer_push(port); 1239 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 1240 } 1241 1242 static void lpuart_dma_rx_complete(void *arg) 1243 { 1244 struct lpuart_port *sport = arg; 1245 1246 lpuart_copy_rx_to_tty(sport); 1247 } 1248 1249 static void lpuart_timer_func(struct timer_list *t) 1250 { 1251 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); 1252 1253 lpuart_copy_rx_to_tty(sport); 1254 } 1255 1256 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 1257 { 1258 struct dma_slave_config dma_rx_sconfig = {}; 1259 struct circ_buf *ring = &sport->rx_ring; 1260 int ret, nent; 1261 struct tty_port *port = &sport->port.state->port; 1262 struct tty_struct *tty = port->tty; 1263 struct ktermios *termios = &tty->termios; 1264 struct dma_chan *chan = sport->dma_rx_chan; 1265 unsigned int bits = tty_get_frame_size(termios->c_cflag); 1266 unsigned int baud = tty_get_baud_rate(tty); 1267 1268 /* 1269 * Calculate length of one DMA buffer size to keep latency below 1270 * 10ms at any baud rate. 1271 */ 1272 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 1273 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 1274 if (sport->rx_dma_rng_buf_len < 16) 1275 sport->rx_dma_rng_buf_len = 16; 1276 1277 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1278 if (!ring->buf) 1279 return -ENOMEM; 1280 1281 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1282 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, 1283 DMA_FROM_DEVICE); 1284 1285 if (!nent) { 1286 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1287 return -EINVAL; 1288 } 1289 1290 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); 1291 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1292 dma_rx_sconfig.src_maxburst = 1; 1293 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1294 ret = dmaengine_slave_config(chan, &dma_rx_sconfig); 1295 1296 if (ret < 0) { 1297 dev_err(sport->port.dev, 1298 "DMA Rx slave config failed, err = %d\n", ret); 1299 return ret; 1300 } 1301 1302 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, 1303 sg_dma_address(&sport->rx_sgl), 1304 sport->rx_sgl.length, 1305 sport->rx_sgl.length / 2, 1306 DMA_DEV_TO_MEM, 1307 DMA_PREP_INTERRUPT); 1308 if (!sport->dma_rx_desc) { 1309 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1310 return -EFAULT; 1311 } 1312 1313 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1314 sport->dma_rx_desc->callback_param = sport; 1315 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1316 dma_async_issue_pending(chan); 1317 1318 if (lpuart_is_32(sport)) { 1319 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); 1320 1321 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); 1322 } else { 1323 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1324 sport->port.membase + UARTCR5); 1325 } 1326 1327 return 0; 1328 } 1329 1330 static void lpuart_dma_rx_free(struct uart_port *port) 1331 { 1332 struct lpuart_port *sport = container_of(port, 1333 struct lpuart_port, port); 1334 struct dma_chan *chan = sport->dma_rx_chan; 1335 1336 dmaengine_terminate_all(chan); 1337 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1338 kfree(sport->rx_ring.buf); 1339 sport->rx_ring.tail = 0; 1340 sport->rx_ring.head = 0; 1341 sport->dma_rx_desc = NULL; 1342 sport->dma_rx_cookie = -EINVAL; 1343 } 1344 1345 static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios, 1346 struct serial_rs485 *rs485) 1347 { 1348 struct lpuart_port *sport = container_of(port, 1349 struct lpuart_port, port); 1350 1351 u8 modem = readb(sport->port.membase + UARTMODEM) & 1352 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1353 writeb(modem, sport->port.membase + UARTMODEM); 1354 1355 if (rs485->flags & SER_RS485_ENABLED) { 1356 /* Enable auto RS-485 RTS mode */ 1357 modem |= UARTMODEM_TXRTSE; 1358 1359 /* 1360 * The hardware defaults to RTS logic HIGH while transfer. 1361 * Switch polarity in case RTS shall be logic HIGH 1362 * after transfer. 1363 * Note: UART is assumed to be active high. 1364 */ 1365 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1366 modem |= UARTMODEM_TXRTSPOL; 1367 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1368 modem &= ~UARTMODEM_TXRTSPOL; 1369 } 1370 1371 writeb(modem, sport->port.membase + UARTMODEM); 1372 return 0; 1373 } 1374 1375 static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios, 1376 struct serial_rs485 *rs485) 1377 { 1378 struct lpuart_port *sport = container_of(port, 1379 struct lpuart_port, port); 1380 1381 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) 1382 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1383 lpuart32_write(&sport->port, modem, UARTMODIR); 1384 1385 if (rs485->flags & SER_RS485_ENABLED) { 1386 /* Enable auto RS-485 RTS mode */ 1387 modem |= UARTMODEM_TXRTSE; 1388 1389 /* 1390 * The hardware defaults to RTS logic HIGH while transfer. 1391 * Switch polarity in case RTS shall be logic HIGH 1392 * after transfer. 1393 * Note: UART is assumed to be active high. 1394 */ 1395 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1396 modem &= ~UARTMODEM_TXRTSPOL; 1397 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1398 modem |= UARTMODEM_TXRTSPOL; 1399 } 1400 1401 lpuart32_write(&sport->port, modem, UARTMODIR); 1402 return 0; 1403 } 1404 1405 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1406 { 1407 unsigned int mctrl = 0; 1408 u8 reg; 1409 1410 reg = readb(port->membase + UARTCR1); 1411 if (reg & UARTCR1_LOOPS) 1412 mctrl |= TIOCM_LOOP; 1413 1414 return mctrl; 1415 } 1416 1417 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1418 { 1419 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 1420 u32 reg; 1421 1422 reg = lpuart32_read(port, UARTCTRL); 1423 if (reg & UARTCTRL_LOOPS) 1424 mctrl |= TIOCM_LOOP; 1425 1426 return mctrl; 1427 } 1428 1429 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1430 { 1431 u8 reg; 1432 1433 reg = readb(port->membase + UARTCR1); 1434 1435 /* for internal loopback we need LOOPS=1 and RSRC=0 */ 1436 reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC); 1437 if (mctrl & TIOCM_LOOP) 1438 reg |= UARTCR1_LOOPS; 1439 1440 writeb(reg, port->membase + UARTCR1); 1441 } 1442 1443 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1444 { 1445 u32 reg; 1446 1447 reg = lpuart32_read(port, UARTCTRL); 1448 1449 /* for internal loopback we need LOOPS=1 and RSRC=0 */ 1450 reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC); 1451 if (mctrl & TIOCM_LOOP) 1452 reg |= UARTCTRL_LOOPS; 1453 1454 lpuart32_write(port, reg, UARTCTRL); 1455 } 1456 1457 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1458 { 1459 unsigned char temp; 1460 1461 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1462 1463 if (break_state != 0) 1464 temp |= UARTCR2_SBK; 1465 1466 writeb(temp, port->membase + UARTCR2); 1467 } 1468 1469 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1470 { 1471 unsigned long temp; 1472 1473 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; 1474 1475 if (break_state != 0) 1476 temp |= UARTCTRL_SBK; 1477 1478 lpuart32_write(port, temp, UARTCTRL); 1479 } 1480 1481 static void lpuart_setup_watermark(struct lpuart_port *sport) 1482 { 1483 unsigned char val, cr2; 1484 unsigned char cr2_saved; 1485 1486 cr2 = readb(sport->port.membase + UARTCR2); 1487 cr2_saved = cr2; 1488 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1489 UARTCR2_RIE | UARTCR2_RE); 1490 writeb(cr2, sport->port.membase + UARTCR2); 1491 1492 val = readb(sport->port.membase + UARTPFIFO); 1493 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1494 sport->port.membase + UARTPFIFO); 1495 1496 /* flush Tx and Rx FIFO */ 1497 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1498 sport->port.membase + UARTCFIFO); 1499 1500 /* explicitly clear RDRF */ 1501 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1502 readb(sport->port.membase + UARTDR); 1503 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1504 } 1505 1506 writeb(0, sport->port.membase + UARTTWFIFO); 1507 writeb(1, sport->port.membase + UARTRWFIFO); 1508 1509 /* Restore cr2 */ 1510 writeb(cr2_saved, sport->port.membase + UARTCR2); 1511 } 1512 1513 static void lpuart_setup_watermark_enable(struct lpuart_port *sport) 1514 { 1515 unsigned char cr2; 1516 1517 lpuart_setup_watermark(sport); 1518 1519 cr2 = readb(sport->port.membase + UARTCR2); 1520 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE; 1521 writeb(cr2, sport->port.membase + UARTCR2); 1522 } 1523 1524 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1525 { 1526 unsigned long val, ctrl; 1527 unsigned long ctrl_saved; 1528 1529 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1530 ctrl_saved = ctrl; 1531 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1532 UARTCTRL_RIE | UARTCTRL_RE); 1533 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1534 1535 /* enable FIFO mode */ 1536 val = lpuart32_read(&sport->port, UARTFIFO); 1537 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1538 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1539 lpuart32_write(&sport->port, val, UARTFIFO); 1540 1541 /* set the watermark */ 1542 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1543 lpuart32_write(&sport->port, val, UARTWATER); 1544 1545 /* Restore cr2 */ 1546 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1547 } 1548 1549 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) 1550 { 1551 u32 temp; 1552 1553 lpuart32_setup_watermark(sport); 1554 1555 temp = lpuart32_read(&sport->port, UARTCTRL); 1556 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE; 1557 lpuart32_write(&sport->port, temp, UARTCTRL); 1558 } 1559 1560 static void rx_dma_timer_init(struct lpuart_port *sport) 1561 { 1562 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); 1563 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1564 add_timer(&sport->lpuart_timer); 1565 } 1566 1567 static void lpuart_request_dma(struct lpuart_port *sport) 1568 { 1569 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); 1570 if (IS_ERR(sport->dma_tx_chan)) { 1571 dev_dbg_once(sport->port.dev, 1572 "DMA tx channel request failed, operating without tx DMA (%ld)\n", 1573 PTR_ERR(sport->dma_tx_chan)); 1574 sport->dma_tx_chan = NULL; 1575 } 1576 1577 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); 1578 if (IS_ERR(sport->dma_rx_chan)) { 1579 dev_dbg_once(sport->port.dev, 1580 "DMA rx channel request failed, operating without rx DMA (%ld)\n", 1581 PTR_ERR(sport->dma_rx_chan)); 1582 sport->dma_rx_chan = NULL; 1583 } 1584 } 1585 1586 static void lpuart_tx_dma_startup(struct lpuart_port *sport) 1587 { 1588 u32 uartbaud; 1589 int ret; 1590 1591 if (uart_console(&sport->port)) 1592 goto err; 1593 1594 if (!sport->dma_tx_chan) 1595 goto err; 1596 1597 ret = lpuart_dma_tx_request(&sport->port); 1598 if (ret) 1599 goto err; 1600 1601 init_waitqueue_head(&sport->dma_wait); 1602 sport->lpuart_dma_tx_use = true; 1603 if (lpuart_is_32(sport)) { 1604 uartbaud = lpuart32_read(&sport->port, UARTBAUD); 1605 lpuart32_write(&sport->port, 1606 uartbaud | UARTBAUD_TDMAE, UARTBAUD); 1607 } else { 1608 writeb(readb(sport->port.membase + UARTCR5) | 1609 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 1610 } 1611 1612 return; 1613 1614 err: 1615 sport->lpuart_dma_tx_use = false; 1616 } 1617 1618 static void lpuart_rx_dma_startup(struct lpuart_port *sport) 1619 { 1620 int ret; 1621 unsigned char cr3; 1622 1623 if (uart_console(&sport->port)) 1624 goto err; 1625 1626 if (!sport->dma_rx_chan) 1627 goto err; 1628 1629 ret = lpuart_start_rx_dma(sport); 1630 if (ret) 1631 goto err; 1632 1633 /* set Rx DMA timeout */ 1634 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1635 if (!sport->dma_rx_timeout) 1636 sport->dma_rx_timeout = 1; 1637 1638 sport->lpuart_dma_rx_use = true; 1639 rx_dma_timer_init(sport); 1640 1641 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { 1642 cr3 = readb(sport->port.membase + UARTCR3); 1643 cr3 |= UARTCR3_FEIE; 1644 writeb(cr3, sport->port.membase + UARTCR3); 1645 } 1646 1647 return; 1648 1649 err: 1650 sport->lpuart_dma_rx_use = false; 1651 } 1652 1653 static int lpuart_startup(struct uart_port *port) 1654 { 1655 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1656 unsigned long flags; 1657 unsigned char temp; 1658 1659 /* determine FIFO size and enable FIFO mode */ 1660 temp = readb(sport->port.membase + UARTPFIFO); 1661 1662 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & 1663 UARTPFIFO_FIFOSIZE_MASK); 1664 sport->port.fifosize = sport->txfifo_size; 1665 1666 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & 1667 UARTPFIFO_FIFOSIZE_MASK); 1668 1669 lpuart_request_dma(sport); 1670 1671 spin_lock_irqsave(&sport->port.lock, flags); 1672 1673 lpuart_setup_watermark_enable(sport); 1674 1675 lpuart_rx_dma_startup(sport); 1676 lpuart_tx_dma_startup(sport); 1677 1678 spin_unlock_irqrestore(&sport->port.lock, flags); 1679 1680 return 0; 1681 } 1682 1683 static void lpuart32_configure(struct lpuart_port *sport) 1684 { 1685 unsigned long temp; 1686 1687 if (sport->lpuart_dma_rx_use) { 1688 /* RXWATER must be 0 */ 1689 temp = lpuart32_read(&sport->port, UARTWATER); 1690 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF); 1691 lpuart32_write(&sport->port, temp, UARTWATER); 1692 } 1693 temp = lpuart32_read(&sport->port, UARTCTRL); 1694 if (!sport->lpuart_dma_rx_use) 1695 temp |= UARTCTRL_RIE; 1696 if (!sport->lpuart_dma_tx_use) 1697 temp |= UARTCTRL_TIE; 1698 lpuart32_write(&sport->port, temp, UARTCTRL); 1699 } 1700 1701 static int lpuart32_startup(struct uart_port *port) 1702 { 1703 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1704 unsigned long flags; 1705 unsigned long temp; 1706 1707 /* determine FIFO size */ 1708 temp = lpuart32_read(&sport->port, UARTFIFO); 1709 1710 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & 1711 UARTFIFO_FIFOSIZE_MASK); 1712 sport->port.fifosize = sport->txfifo_size; 1713 1714 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & 1715 UARTFIFO_FIFOSIZE_MASK); 1716 1717 /* 1718 * The LS1021A and LS1028A have a fixed FIFO depth of 16 words. 1719 * Although they support the RX/TXSIZE fields, their encoding is 1720 * different. Eg the reference manual states 0b101 is 16 words. 1721 */ 1722 if (is_layerscape_lpuart(sport)) { 1723 sport->rxfifo_size = 16; 1724 sport->txfifo_size = 16; 1725 sport->port.fifosize = sport->txfifo_size; 1726 } 1727 1728 lpuart_request_dma(sport); 1729 1730 spin_lock_irqsave(&sport->port.lock, flags); 1731 1732 lpuart32_setup_watermark_enable(sport); 1733 1734 lpuart_rx_dma_startup(sport); 1735 lpuart_tx_dma_startup(sport); 1736 1737 lpuart32_configure(sport); 1738 1739 spin_unlock_irqrestore(&sport->port.lock, flags); 1740 return 0; 1741 } 1742 1743 static void lpuart_dma_shutdown(struct lpuart_port *sport) 1744 { 1745 if (sport->lpuart_dma_rx_use) { 1746 del_timer_sync(&sport->lpuart_timer); 1747 lpuart_dma_rx_free(&sport->port); 1748 sport->lpuart_dma_rx_use = false; 1749 } 1750 1751 if (sport->lpuart_dma_tx_use) { 1752 if (wait_event_interruptible_timeout(sport->dma_wait, 1753 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { 1754 sport->dma_tx_in_progress = false; 1755 dmaengine_terminate_all(sport->dma_tx_chan); 1756 } 1757 sport->lpuart_dma_tx_use = false; 1758 } 1759 1760 if (sport->dma_tx_chan) 1761 dma_release_channel(sport->dma_tx_chan); 1762 if (sport->dma_rx_chan) 1763 dma_release_channel(sport->dma_rx_chan); 1764 } 1765 1766 static void lpuart_shutdown(struct uart_port *port) 1767 { 1768 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1769 unsigned char temp; 1770 unsigned long flags; 1771 1772 spin_lock_irqsave(&port->lock, flags); 1773 1774 /* disable Rx/Tx and interrupts */ 1775 temp = readb(port->membase + UARTCR2); 1776 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1777 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1778 writeb(temp, port->membase + UARTCR2); 1779 1780 spin_unlock_irqrestore(&port->lock, flags); 1781 1782 lpuart_dma_shutdown(sport); 1783 } 1784 1785 static void lpuart32_shutdown(struct uart_port *port) 1786 { 1787 struct lpuart_port *sport = 1788 container_of(port, struct lpuart_port, port); 1789 unsigned long temp; 1790 unsigned long flags; 1791 1792 spin_lock_irqsave(&port->lock, flags); 1793 1794 /* disable Rx/Tx and interrupts */ 1795 temp = lpuart32_read(port, UARTCTRL); 1796 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1797 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1798 lpuart32_write(port, temp, UARTCTRL); 1799 1800 spin_unlock_irqrestore(&port->lock, flags); 1801 1802 lpuart_dma_shutdown(sport); 1803 } 1804 1805 static void 1806 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1807 const struct ktermios *old) 1808 { 1809 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1810 unsigned long flags; 1811 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1812 unsigned int baud; 1813 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1814 unsigned int sbr, brfa; 1815 1816 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1817 old_cr2 = readb(sport->port.membase + UARTCR2); 1818 cr3 = readb(sport->port.membase + UARTCR3); 1819 cr4 = readb(sport->port.membase + UARTCR4); 1820 bdh = readb(sport->port.membase + UARTBDH); 1821 modem = readb(sport->port.membase + UARTMODEM); 1822 /* 1823 * only support CS8 and CS7, and for CS7 must enable PE. 1824 * supported mode: 1825 * - (7,e/o,1) 1826 * - (8,n,1) 1827 * - (8,m/s,1) 1828 * - (8,e/o,1) 1829 */ 1830 while ((termios->c_cflag & CSIZE) != CS8 && 1831 (termios->c_cflag & CSIZE) != CS7) { 1832 termios->c_cflag &= ~CSIZE; 1833 termios->c_cflag |= old_csize; 1834 old_csize = CS8; 1835 } 1836 1837 if ((termios->c_cflag & CSIZE) == CS8 || 1838 (termios->c_cflag & CSIZE) == CS7) 1839 cr1 = old_cr1 & ~UARTCR1_M; 1840 1841 if (termios->c_cflag & CMSPAR) { 1842 if ((termios->c_cflag & CSIZE) != CS8) { 1843 termios->c_cflag &= ~CSIZE; 1844 termios->c_cflag |= CS8; 1845 } 1846 cr1 |= UARTCR1_M; 1847 } 1848 1849 /* 1850 * When auto RS-485 RTS mode is enabled, 1851 * hardware flow control need to be disabled. 1852 */ 1853 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1854 termios->c_cflag &= ~CRTSCTS; 1855 1856 if (termios->c_cflag & CRTSCTS) 1857 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE; 1858 else 1859 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1860 1861 termios->c_cflag &= ~CSTOPB; 1862 1863 /* parity must be enabled when CS7 to match 8-bits format */ 1864 if ((termios->c_cflag & CSIZE) == CS7) 1865 termios->c_cflag |= PARENB; 1866 1867 if (termios->c_cflag & PARENB) { 1868 if (termios->c_cflag & CMSPAR) { 1869 cr1 &= ~UARTCR1_PE; 1870 if (termios->c_cflag & PARODD) 1871 cr3 |= UARTCR3_T8; 1872 else 1873 cr3 &= ~UARTCR3_T8; 1874 } else { 1875 cr1 |= UARTCR1_PE; 1876 if ((termios->c_cflag & CSIZE) == CS8) 1877 cr1 |= UARTCR1_M; 1878 if (termios->c_cflag & PARODD) 1879 cr1 |= UARTCR1_PT; 1880 else 1881 cr1 &= ~UARTCR1_PT; 1882 } 1883 } else { 1884 cr1 &= ~UARTCR1_PE; 1885 } 1886 1887 /* ask the core to calculate the divisor */ 1888 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1889 1890 /* 1891 * Need to update the Ring buffer length according to the selected 1892 * baud rate and restart Rx DMA path. 1893 * 1894 * Since timer function acqures sport->port.lock, need to stop before 1895 * acquring same lock because otherwise del_timer_sync() can deadlock. 1896 */ 1897 if (old && sport->lpuart_dma_rx_use) { 1898 del_timer_sync(&sport->lpuart_timer); 1899 lpuart_dma_rx_free(&sport->port); 1900 } 1901 1902 spin_lock_irqsave(&sport->port.lock, flags); 1903 1904 sport->port.read_status_mask = 0; 1905 if (termios->c_iflag & INPCK) 1906 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; 1907 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1908 sport->port.read_status_mask |= UARTSR1_FE; 1909 1910 /* characters to ignore */ 1911 sport->port.ignore_status_mask = 0; 1912 if (termios->c_iflag & IGNPAR) 1913 sport->port.ignore_status_mask |= UARTSR1_PE; 1914 if (termios->c_iflag & IGNBRK) { 1915 sport->port.ignore_status_mask |= UARTSR1_FE; 1916 /* 1917 * if we're ignoring parity and break indicators, 1918 * ignore overruns too (for real raw support). 1919 */ 1920 if (termios->c_iflag & IGNPAR) 1921 sport->port.ignore_status_mask |= UARTSR1_OR; 1922 } 1923 1924 /* update the per-port timeout */ 1925 uart_update_timeout(port, termios->c_cflag, baud); 1926 1927 /* wait transmit engin complete */ 1928 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 1929 1930 /* disable transmit and receive */ 1931 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1932 sport->port.membase + UARTCR2); 1933 1934 sbr = sport->port.uartclk / (16 * baud); 1935 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1936 bdh &= ~UARTBDH_SBR_MASK; 1937 bdh |= (sbr >> 8) & 0x1F; 1938 cr4 &= ~UARTCR4_BRFA_MASK; 1939 brfa &= UARTCR4_BRFA_MASK; 1940 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1941 writeb(bdh, sport->port.membase + UARTBDH); 1942 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1943 writeb(cr3, sport->port.membase + UARTCR3); 1944 writeb(cr1, sport->port.membase + UARTCR1); 1945 writeb(modem, sport->port.membase + UARTMODEM); 1946 1947 /* restore control register */ 1948 writeb(old_cr2, sport->port.membase + UARTCR2); 1949 1950 if (old && sport->lpuart_dma_rx_use) { 1951 if (!lpuart_start_rx_dma(sport)) 1952 rx_dma_timer_init(sport); 1953 else 1954 sport->lpuart_dma_rx_use = false; 1955 } 1956 1957 spin_unlock_irqrestore(&sport->port.lock, flags); 1958 } 1959 1960 static void __lpuart32_serial_setbrg(struct uart_port *port, 1961 unsigned int baudrate, bool use_rx_dma, 1962 bool use_tx_dma) 1963 { 1964 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; 1965 u32 clk = port->uartclk; 1966 1967 /* 1968 * The idea is to use the best OSR (over-sampling rate) possible. 1969 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 1970 * Loop to find the best OSR value possible, one that generates minimum 1971 * baud_diff iterate through the rest of the supported values of OSR. 1972 * 1973 * Calculation Formula: 1974 * Baud Rate = baud clock / ((OSR+1) × SBR) 1975 */ 1976 baud_diff = baudrate; 1977 osr = 0; 1978 sbr = 0; 1979 1980 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 1981 /* calculate the temporary sbr value */ 1982 tmp_sbr = (clk / (baudrate * tmp_osr)); 1983 if (tmp_sbr == 0) 1984 tmp_sbr = 1; 1985 1986 /* 1987 * calculate the baud rate difference based on the temporary 1988 * osr and sbr values 1989 */ 1990 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 1991 1992 /* select best values between sbr and sbr+1 */ 1993 tmp = clk / (tmp_osr * (tmp_sbr + 1)); 1994 if (tmp_diff > (baudrate - tmp)) { 1995 tmp_diff = baudrate - tmp; 1996 tmp_sbr++; 1997 } 1998 1999 if (tmp_sbr > UARTBAUD_SBR_MASK) 2000 continue; 2001 2002 if (tmp_diff <= baud_diff) { 2003 baud_diff = tmp_diff; 2004 osr = tmp_osr; 2005 sbr = tmp_sbr; 2006 2007 if (!baud_diff) 2008 break; 2009 } 2010 } 2011 2012 /* handle buadrate outside acceptable rate */ 2013 if (baud_diff > ((baudrate / 100) * 3)) 2014 dev_warn(port->dev, 2015 "unacceptable baud rate difference of more than 3%%\n"); 2016 2017 tmp = lpuart32_read(port, UARTBAUD); 2018 2019 if ((osr > 3) && (osr < 8)) 2020 tmp |= UARTBAUD_BOTHEDGE; 2021 2022 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 2023 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; 2024 2025 tmp &= ~UARTBAUD_SBR_MASK; 2026 tmp |= sbr & UARTBAUD_SBR_MASK; 2027 2028 if (!use_rx_dma) 2029 tmp &= ~UARTBAUD_RDMAE; 2030 if (!use_tx_dma) 2031 tmp &= ~UARTBAUD_TDMAE; 2032 2033 lpuart32_write(port, tmp, UARTBAUD); 2034 } 2035 2036 static void lpuart32_serial_setbrg(struct lpuart_port *sport, 2037 unsigned int baudrate) 2038 { 2039 __lpuart32_serial_setbrg(&sport->port, baudrate, 2040 sport->lpuart_dma_rx_use, 2041 sport->lpuart_dma_tx_use); 2042 } 2043 2044 2045 static void 2046 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 2047 const struct ktermios *old) 2048 { 2049 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 2050 unsigned long flags; 2051 unsigned long ctrl, old_ctrl, bd, modem; 2052 unsigned int baud; 2053 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 2054 2055 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); 2056 bd = lpuart32_read(&sport->port, UARTBAUD); 2057 modem = lpuart32_read(&sport->port, UARTMODIR); 2058 sport->is_cs7 = false; 2059 /* 2060 * only support CS8 and CS7, and for CS7 must enable PE. 2061 * supported mode: 2062 * - (7,e/o,1) 2063 * - (8,n,1) 2064 * - (8,m/s,1) 2065 * - (8,e/o,1) 2066 */ 2067 while ((termios->c_cflag & CSIZE) != CS8 && 2068 (termios->c_cflag & CSIZE) != CS7) { 2069 termios->c_cflag &= ~CSIZE; 2070 termios->c_cflag |= old_csize; 2071 old_csize = CS8; 2072 } 2073 2074 if ((termios->c_cflag & CSIZE) == CS8 || 2075 (termios->c_cflag & CSIZE) == CS7) 2076 ctrl = old_ctrl & ~UARTCTRL_M; 2077 2078 if (termios->c_cflag & CMSPAR) { 2079 if ((termios->c_cflag & CSIZE) != CS8) { 2080 termios->c_cflag &= ~CSIZE; 2081 termios->c_cflag |= CS8; 2082 } 2083 ctrl |= UARTCTRL_M; 2084 } 2085 2086 /* 2087 * When auto RS-485 RTS mode is enabled, 2088 * hardware flow control need to be disabled. 2089 */ 2090 if (sport->port.rs485.flags & SER_RS485_ENABLED) 2091 termios->c_cflag &= ~CRTSCTS; 2092 2093 if (termios->c_cflag & CRTSCTS) 2094 modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE; 2095 else 2096 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 2097 2098 if (termios->c_cflag & CSTOPB) 2099 bd |= UARTBAUD_SBNS; 2100 else 2101 bd &= ~UARTBAUD_SBNS; 2102 2103 /* parity must be enabled when CS7 to match 8-bits format */ 2104 if ((termios->c_cflag & CSIZE) == CS7) 2105 termios->c_cflag |= PARENB; 2106 2107 if ((termios->c_cflag & PARENB)) { 2108 if (termios->c_cflag & CMSPAR) { 2109 ctrl &= ~UARTCTRL_PE; 2110 ctrl |= UARTCTRL_M; 2111 } else { 2112 ctrl |= UARTCTRL_PE; 2113 if ((termios->c_cflag & CSIZE) == CS8) 2114 ctrl |= UARTCTRL_M; 2115 if (termios->c_cflag & PARODD) 2116 ctrl |= UARTCTRL_PT; 2117 else 2118 ctrl &= ~UARTCTRL_PT; 2119 } 2120 } else { 2121 ctrl &= ~UARTCTRL_PE; 2122 } 2123 2124 /* ask the core to calculate the divisor */ 2125 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); 2126 2127 /* 2128 * Need to update the Ring buffer length according to the selected 2129 * baud rate and restart Rx DMA path. 2130 * 2131 * Since timer function acqures sport->port.lock, need to stop before 2132 * acquring same lock because otherwise del_timer_sync() can deadlock. 2133 */ 2134 if (old && sport->lpuart_dma_rx_use) { 2135 del_timer_sync(&sport->lpuart_timer); 2136 lpuart_dma_rx_free(&sport->port); 2137 } 2138 2139 spin_lock_irqsave(&sport->port.lock, flags); 2140 2141 sport->port.read_status_mask = 0; 2142 if (termios->c_iflag & INPCK) 2143 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; 2144 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2145 sport->port.read_status_mask |= UARTSTAT_FE; 2146 2147 /* characters to ignore */ 2148 sport->port.ignore_status_mask = 0; 2149 if (termios->c_iflag & IGNPAR) 2150 sport->port.ignore_status_mask |= UARTSTAT_PE; 2151 if (termios->c_iflag & IGNBRK) { 2152 sport->port.ignore_status_mask |= UARTSTAT_FE; 2153 /* 2154 * if we're ignoring parity and break indicators, 2155 * ignore overruns too (for real raw support). 2156 */ 2157 if (termios->c_iflag & IGNPAR) 2158 sport->port.ignore_status_mask |= UARTSTAT_OR; 2159 } 2160 2161 /* update the per-port timeout */ 2162 uart_update_timeout(port, termios->c_cflag, baud); 2163 2164 /* wait transmit engin complete */ 2165 lpuart32_write(&sport->port, 0, UARTMODIR); 2166 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2167 2168 /* disable transmit and receive */ 2169 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 2170 UARTCTRL); 2171 2172 lpuart32_write(&sport->port, bd, UARTBAUD); 2173 lpuart32_serial_setbrg(sport, baud); 2174 lpuart32_write(&sport->port, modem, UARTMODIR); 2175 lpuart32_write(&sport->port, ctrl, UARTCTRL); 2176 /* restore control register */ 2177 2178 if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE) 2179 sport->is_cs7 = true; 2180 2181 if (old && sport->lpuart_dma_rx_use) { 2182 if (!lpuart_start_rx_dma(sport)) 2183 rx_dma_timer_init(sport); 2184 else 2185 sport->lpuart_dma_rx_use = false; 2186 } 2187 2188 spin_unlock_irqrestore(&sport->port.lock, flags); 2189 } 2190 2191 static const char *lpuart_type(struct uart_port *port) 2192 { 2193 return "FSL_LPUART"; 2194 } 2195 2196 static void lpuart_release_port(struct uart_port *port) 2197 { 2198 /* nothing to do */ 2199 } 2200 2201 static int lpuart_request_port(struct uart_port *port) 2202 { 2203 return 0; 2204 } 2205 2206 /* configure/autoconfigure the port */ 2207 static void lpuart_config_port(struct uart_port *port, int flags) 2208 { 2209 if (flags & UART_CONFIG_TYPE) 2210 port->type = PORT_LPUART; 2211 } 2212 2213 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 2214 { 2215 int ret = 0; 2216 2217 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 2218 ret = -EINVAL; 2219 if (port->irq != ser->irq) 2220 ret = -EINVAL; 2221 if (ser->io_type != UPIO_MEM) 2222 ret = -EINVAL; 2223 if (port->uartclk / 16 != ser->baud_base) 2224 ret = -EINVAL; 2225 if (port->iobase != ser->port) 2226 ret = -EINVAL; 2227 if (ser->hub6 != 0) 2228 ret = -EINVAL; 2229 return ret; 2230 } 2231 2232 static const struct uart_ops lpuart_pops = { 2233 .tx_empty = lpuart_tx_empty, 2234 .set_mctrl = lpuart_set_mctrl, 2235 .get_mctrl = lpuart_get_mctrl, 2236 .stop_tx = lpuart_stop_tx, 2237 .start_tx = lpuart_start_tx, 2238 .stop_rx = lpuart_stop_rx, 2239 .break_ctl = lpuart_break_ctl, 2240 .startup = lpuart_startup, 2241 .shutdown = lpuart_shutdown, 2242 .set_termios = lpuart_set_termios, 2243 .type = lpuart_type, 2244 .request_port = lpuart_request_port, 2245 .release_port = lpuart_release_port, 2246 .config_port = lpuart_config_port, 2247 .verify_port = lpuart_verify_port, 2248 .flush_buffer = lpuart_flush_buffer, 2249 #if defined(CONFIG_CONSOLE_POLL) 2250 .poll_init = lpuart_poll_init, 2251 .poll_get_char = lpuart_poll_get_char, 2252 .poll_put_char = lpuart_poll_put_char, 2253 #endif 2254 }; 2255 2256 static const struct uart_ops lpuart32_pops = { 2257 .tx_empty = lpuart32_tx_empty, 2258 .set_mctrl = lpuart32_set_mctrl, 2259 .get_mctrl = lpuart32_get_mctrl, 2260 .stop_tx = lpuart32_stop_tx, 2261 .start_tx = lpuart32_start_tx, 2262 .stop_rx = lpuart32_stop_rx, 2263 .break_ctl = lpuart32_break_ctl, 2264 .startup = lpuart32_startup, 2265 .shutdown = lpuart32_shutdown, 2266 .set_termios = lpuart32_set_termios, 2267 .type = lpuart_type, 2268 .request_port = lpuart_request_port, 2269 .release_port = lpuart_release_port, 2270 .config_port = lpuart_config_port, 2271 .verify_port = lpuart_verify_port, 2272 .flush_buffer = lpuart_flush_buffer, 2273 #if defined(CONFIG_CONSOLE_POLL) 2274 .poll_init = lpuart32_poll_init, 2275 .poll_get_char = lpuart32_poll_get_char, 2276 .poll_put_char = lpuart32_poll_put_char, 2277 #endif 2278 }; 2279 2280 static struct lpuart_port *lpuart_ports[UART_NR]; 2281 2282 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 2283 static void lpuart_console_putchar(struct uart_port *port, unsigned char ch) 2284 { 2285 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 2286 writeb(ch, port->membase + UARTDR); 2287 } 2288 2289 static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch) 2290 { 2291 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 2292 lpuart32_write(port, ch, UARTDATA); 2293 } 2294 2295 static void 2296 lpuart_console_write(struct console *co, const char *s, unsigned int count) 2297 { 2298 struct lpuart_port *sport = lpuart_ports[co->index]; 2299 unsigned char old_cr2, cr2; 2300 unsigned long flags; 2301 int locked = 1; 2302 2303 if (oops_in_progress) 2304 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2305 else 2306 spin_lock_irqsave(&sport->port.lock, flags); 2307 2308 /* first save CR2 and then disable interrupts */ 2309 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 2310 cr2 |= UARTCR2_TE | UARTCR2_RE; 2311 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 2312 writeb(cr2, sport->port.membase + UARTCR2); 2313 2314 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 2315 2316 /* wait for transmitter finish complete and restore CR2 */ 2317 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 2318 2319 writeb(old_cr2, sport->port.membase + UARTCR2); 2320 2321 if (locked) 2322 spin_unlock_irqrestore(&sport->port.lock, flags); 2323 } 2324 2325 static void 2326 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 2327 { 2328 struct lpuart_port *sport = lpuart_ports[co->index]; 2329 unsigned long old_cr, cr; 2330 unsigned long flags; 2331 int locked = 1; 2332 2333 if (oops_in_progress) 2334 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2335 else 2336 spin_lock_irqsave(&sport->port.lock, flags); 2337 2338 /* first save CR2 and then disable interrupts */ 2339 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 2340 cr |= UARTCTRL_TE | UARTCTRL_RE; 2341 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 2342 lpuart32_write(&sport->port, cr, UARTCTRL); 2343 2344 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 2345 2346 /* wait for transmitter finish complete and restore CR2 */ 2347 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2348 2349 lpuart32_write(&sport->port, old_cr, UARTCTRL); 2350 2351 if (locked) 2352 spin_unlock_irqrestore(&sport->port.lock, flags); 2353 } 2354 2355 /* 2356 * if the port was already initialised (eg, by a boot loader), 2357 * try to determine the current setup. 2358 */ 2359 static void __init 2360 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 2361 int *parity, int *bits) 2362 { 2363 unsigned char cr, bdh, bdl, brfa; 2364 unsigned int sbr, uartclk, baud_raw; 2365 2366 cr = readb(sport->port.membase + UARTCR2); 2367 cr &= UARTCR2_TE | UARTCR2_RE; 2368 if (!cr) 2369 return; 2370 2371 /* ok, the port was enabled */ 2372 2373 cr = readb(sport->port.membase + UARTCR1); 2374 2375 *parity = 'n'; 2376 if (cr & UARTCR1_PE) { 2377 if (cr & UARTCR1_PT) 2378 *parity = 'o'; 2379 else 2380 *parity = 'e'; 2381 } 2382 2383 if (cr & UARTCR1_M) 2384 *bits = 9; 2385 else 2386 *bits = 8; 2387 2388 bdh = readb(sport->port.membase + UARTBDH); 2389 bdh &= UARTBDH_SBR_MASK; 2390 bdl = readb(sport->port.membase + UARTBDL); 2391 sbr = bdh; 2392 sbr <<= 8; 2393 sbr |= bdl; 2394 brfa = readb(sport->port.membase + UARTCR4); 2395 brfa &= UARTCR4_BRFA_MASK; 2396 2397 uartclk = lpuart_get_baud_clk_rate(sport); 2398 /* 2399 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2400 */ 2401 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 2402 2403 if (*baud != baud_raw) 2404 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2405 "from %d to %d\n", baud_raw, *baud); 2406 } 2407 2408 static void __init 2409 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 2410 int *parity, int *bits) 2411 { 2412 unsigned long cr, bd; 2413 unsigned int sbr, uartclk, baud_raw; 2414 2415 cr = lpuart32_read(&sport->port, UARTCTRL); 2416 cr &= UARTCTRL_TE | UARTCTRL_RE; 2417 if (!cr) 2418 return; 2419 2420 /* ok, the port was enabled */ 2421 2422 cr = lpuart32_read(&sport->port, UARTCTRL); 2423 2424 *parity = 'n'; 2425 if (cr & UARTCTRL_PE) { 2426 if (cr & UARTCTRL_PT) 2427 *parity = 'o'; 2428 else 2429 *parity = 'e'; 2430 } 2431 2432 if (cr & UARTCTRL_M) 2433 *bits = 9; 2434 else 2435 *bits = 8; 2436 2437 bd = lpuart32_read(&sport->port, UARTBAUD); 2438 bd &= UARTBAUD_SBR_MASK; 2439 if (!bd) 2440 return; 2441 2442 sbr = bd; 2443 uartclk = lpuart_get_baud_clk_rate(sport); 2444 /* 2445 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2446 */ 2447 baud_raw = uartclk / (16 * sbr); 2448 2449 if (*baud != baud_raw) 2450 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2451 "from %d to %d\n", baud_raw, *baud); 2452 } 2453 2454 static int __init lpuart_console_setup(struct console *co, char *options) 2455 { 2456 struct lpuart_port *sport; 2457 int baud = 115200; 2458 int bits = 8; 2459 int parity = 'n'; 2460 int flow = 'n'; 2461 2462 /* 2463 * check whether an invalid uart number has been specified, and 2464 * if so, search for the first available port that does have 2465 * console support. 2466 */ 2467 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2468 co->index = 0; 2469 2470 sport = lpuart_ports[co->index]; 2471 if (sport == NULL) 2472 return -ENODEV; 2473 2474 if (options) 2475 uart_parse_options(options, &baud, &parity, &bits, &flow); 2476 else 2477 if (lpuart_is_32(sport)) 2478 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2479 else 2480 lpuart_console_get_options(sport, &baud, &parity, &bits); 2481 2482 if (lpuart_is_32(sport)) 2483 lpuart32_setup_watermark(sport); 2484 else 2485 lpuart_setup_watermark(sport); 2486 2487 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2488 } 2489 2490 static struct uart_driver lpuart_reg; 2491 static struct console lpuart_console = { 2492 .name = DEV_NAME, 2493 .write = lpuart_console_write, 2494 .device = uart_console_device, 2495 .setup = lpuart_console_setup, 2496 .flags = CON_PRINTBUFFER, 2497 .index = -1, 2498 .data = &lpuart_reg, 2499 }; 2500 2501 static struct console lpuart32_console = { 2502 .name = DEV_NAME, 2503 .write = lpuart32_console_write, 2504 .device = uart_console_device, 2505 .setup = lpuart_console_setup, 2506 .flags = CON_PRINTBUFFER, 2507 .index = -1, 2508 .data = &lpuart_reg, 2509 }; 2510 2511 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2512 { 2513 struct earlycon_device *dev = con->data; 2514 2515 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2516 } 2517 2518 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2519 { 2520 struct earlycon_device *dev = con->data; 2521 2522 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2523 } 2524 2525 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2526 const char *opt) 2527 { 2528 if (!device->port.membase) 2529 return -ENODEV; 2530 2531 device->con->write = lpuart_early_write; 2532 return 0; 2533 } 2534 2535 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2536 const char *opt) 2537 { 2538 if (!device->port.membase) 2539 return -ENODEV; 2540 2541 if (device->port.iotype != UPIO_MEM32) 2542 device->port.iotype = UPIO_MEM32BE; 2543 2544 device->con->write = lpuart32_early_write; 2545 return 0; 2546 } 2547 2548 static int __init ls1028a_early_console_setup(struct earlycon_device *device, 2549 const char *opt) 2550 { 2551 u32 cr; 2552 2553 if (!device->port.membase) 2554 return -ENODEV; 2555 2556 device->port.iotype = UPIO_MEM32; 2557 device->con->write = lpuart32_early_write; 2558 2559 /* set the baudrate */ 2560 if (device->port.uartclk && device->baud) 2561 __lpuart32_serial_setbrg(&device->port, device->baud, 2562 false, false); 2563 2564 /* enable transmitter */ 2565 cr = lpuart32_read(&device->port, UARTCTRL); 2566 cr |= UARTCTRL_TE; 2567 lpuart32_write(&device->port, cr, UARTCTRL); 2568 2569 return 0; 2570 } 2571 2572 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2573 const char *opt) 2574 { 2575 if (!device->port.membase) 2576 return -ENODEV; 2577 2578 device->port.iotype = UPIO_MEM32; 2579 device->port.membase += IMX_REG_OFF; 2580 device->con->write = lpuart32_early_write; 2581 2582 return 0; 2583 } 2584 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2585 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2586 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup); 2587 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2588 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup); 2589 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup); 2590 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2591 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2592 2593 #define LPUART_CONSOLE (&lpuart_console) 2594 #define LPUART32_CONSOLE (&lpuart32_console) 2595 #else 2596 #define LPUART_CONSOLE NULL 2597 #define LPUART32_CONSOLE NULL 2598 #endif 2599 2600 static struct uart_driver lpuart_reg = { 2601 .owner = THIS_MODULE, 2602 .driver_name = DRIVER_NAME, 2603 .dev_name = DEV_NAME, 2604 .nr = ARRAY_SIZE(lpuart_ports), 2605 .cons = LPUART_CONSOLE, 2606 }; 2607 2608 static const struct serial_rs485 lpuart_rs485_supported = { 2609 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND, 2610 /* delay_rts_* and RX_DURING_TX are not supported */ 2611 }; 2612 2613 static int lpuart_global_reset(struct lpuart_port *sport) 2614 { 2615 struct uart_port *port = &sport->port; 2616 void __iomem *global_addr; 2617 unsigned long ctrl, bd; 2618 unsigned int val = 0; 2619 int ret; 2620 2621 ret = clk_prepare_enable(sport->ipg_clk); 2622 if (ret) { 2623 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret); 2624 return ret; 2625 } 2626 2627 if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) { 2628 /* 2629 * If the transmitter is used by earlycon, wait for transmit engine to 2630 * complete and then reset. 2631 */ 2632 ctrl = lpuart32_read(port, UARTCTRL); 2633 if (ctrl & UARTCTRL_TE) { 2634 bd = lpuart32_read(&sport->port, UARTBAUD); 2635 if (read_poll_timeout(lpuart32_tx_empty, val, val, 1, 100000, false, 2636 port)) { 2637 dev_warn(sport->port.dev, 2638 "timeout waiting for transmit engine to complete\n"); 2639 clk_disable_unprepare(sport->ipg_clk); 2640 return 0; 2641 } 2642 } 2643 2644 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF; 2645 writel(UART_GLOBAL_RST, global_addr); 2646 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); 2647 writel(0, global_addr); 2648 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); 2649 2650 /* Recover the transmitter for earlycon. */ 2651 if (ctrl & UARTCTRL_TE) { 2652 lpuart32_write(port, bd, UARTBAUD); 2653 lpuart32_write(port, ctrl, UARTCTRL); 2654 } 2655 } 2656 2657 clk_disable_unprepare(sport->ipg_clk); 2658 return 0; 2659 } 2660 2661 static int lpuart_probe(struct platform_device *pdev) 2662 { 2663 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev); 2664 struct device_node *np = pdev->dev.of_node; 2665 struct lpuart_port *sport; 2666 struct resource *res; 2667 irq_handler_t handler; 2668 int ret; 2669 2670 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2671 if (!sport) 2672 return -ENOMEM; 2673 2674 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2675 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 2676 if (IS_ERR(sport->port.membase)) 2677 return PTR_ERR(sport->port.membase); 2678 2679 sport->port.membase += sdata->reg_off; 2680 sport->port.mapbase = res->start + sdata->reg_off; 2681 sport->port.dev = &pdev->dev; 2682 sport->port.type = PORT_LPUART; 2683 sport->devtype = sdata->devtype; 2684 ret = platform_get_irq(pdev, 0); 2685 if (ret < 0) 2686 return ret; 2687 sport->port.irq = ret; 2688 sport->port.iotype = sdata->iotype; 2689 if (lpuart_is_32(sport)) 2690 sport->port.ops = &lpuart32_pops; 2691 else 2692 sport->port.ops = &lpuart_pops; 2693 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); 2694 sport->port.flags = UPF_BOOT_AUTOCONF; 2695 2696 if (lpuart_is_32(sport)) 2697 sport->port.rs485_config = lpuart32_config_rs485; 2698 else 2699 sport->port.rs485_config = lpuart_config_rs485; 2700 sport->port.rs485_supported = lpuart_rs485_supported; 2701 2702 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 2703 if (IS_ERR(sport->ipg_clk)) { 2704 ret = PTR_ERR(sport->ipg_clk); 2705 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); 2706 return ret; 2707 } 2708 2709 sport->baud_clk = NULL; 2710 if (is_imx8qxp_lpuart(sport)) { 2711 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); 2712 if (IS_ERR(sport->baud_clk)) { 2713 ret = PTR_ERR(sport->baud_clk); 2714 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); 2715 return ret; 2716 } 2717 } 2718 2719 ret = of_alias_get_id(np, "serial"); 2720 if (ret < 0) { 2721 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2722 return ret; 2723 } 2724 if (ret >= ARRAY_SIZE(lpuart_ports)) { 2725 dev_err(&pdev->dev, "serial%d out of range\n", ret); 2726 return -EINVAL; 2727 } 2728 sport->port.line = ret; 2729 2730 ret = lpuart_enable_clks(sport); 2731 if (ret) 2732 return ret; 2733 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); 2734 2735 lpuart_ports[sport->port.line] = sport; 2736 2737 platform_set_drvdata(pdev, &sport->port); 2738 2739 if (lpuart_is_32(sport)) { 2740 lpuart_reg.cons = LPUART32_CONSOLE; 2741 handler = lpuart32_int; 2742 } else { 2743 lpuart_reg.cons = LPUART_CONSOLE; 2744 handler = lpuart_int; 2745 } 2746 2747 ret = lpuart_global_reset(sport); 2748 if (ret) 2749 goto failed_reset; 2750 2751 ret = uart_get_rs485_mode(&sport->port); 2752 if (ret) 2753 goto failed_get_rs485; 2754 2755 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2756 if (ret) 2757 goto failed_attach_port; 2758 2759 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0, 2760 DRIVER_NAME, sport); 2761 if (ret) 2762 goto failed_irq_request; 2763 2764 return 0; 2765 2766 failed_irq_request: 2767 uart_remove_one_port(&lpuart_reg, &sport->port); 2768 failed_attach_port: 2769 failed_get_rs485: 2770 failed_reset: 2771 lpuart_disable_clks(sport); 2772 return ret; 2773 } 2774 2775 static int lpuart_remove(struct platform_device *pdev) 2776 { 2777 struct lpuart_port *sport = platform_get_drvdata(pdev); 2778 2779 uart_remove_one_port(&lpuart_reg, &sport->port); 2780 2781 lpuart_disable_clks(sport); 2782 2783 if (sport->dma_tx_chan) 2784 dma_release_channel(sport->dma_tx_chan); 2785 2786 if (sport->dma_rx_chan) 2787 dma_release_channel(sport->dma_rx_chan); 2788 2789 return 0; 2790 } 2791 2792 static int __maybe_unused lpuart_suspend(struct device *dev) 2793 { 2794 struct lpuart_port *sport = dev_get_drvdata(dev); 2795 unsigned long temp; 2796 bool irq_wake; 2797 2798 if (lpuart_is_32(sport)) { 2799 /* disable Rx/Tx and interrupts */ 2800 temp = lpuart32_read(&sport->port, UARTCTRL); 2801 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2802 lpuart32_write(&sport->port, temp, UARTCTRL); 2803 } else { 2804 /* disable Rx/Tx and interrupts */ 2805 temp = readb(sport->port.membase + UARTCR2); 2806 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2807 writeb(temp, sport->port.membase + UARTCR2); 2808 } 2809 2810 uart_suspend_port(&lpuart_reg, &sport->port); 2811 2812 /* uart_suspend_port() might set wakeup flag */ 2813 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2814 2815 if (sport->lpuart_dma_rx_use) { 2816 /* 2817 * EDMA driver during suspend will forcefully release any 2818 * non-idle DMA channels. If port wakeup is enabled or if port 2819 * is console port or 'no_console_suspend' is set the Rx DMA 2820 * cannot resume as expected, hence gracefully release the 2821 * Rx DMA path before suspend and start Rx DMA path on resume. 2822 */ 2823 if (irq_wake) { 2824 del_timer_sync(&sport->lpuart_timer); 2825 lpuart_dma_rx_free(&sport->port); 2826 } 2827 2828 /* Disable Rx DMA to use UART port as wakeup source */ 2829 if (lpuart_is_32(sport)) { 2830 temp = lpuart32_read(&sport->port, UARTBAUD); 2831 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, 2832 UARTBAUD); 2833 } else { 2834 writeb(readb(sport->port.membase + UARTCR5) & 2835 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 2836 } 2837 } 2838 2839 if (sport->lpuart_dma_tx_use) { 2840 sport->dma_tx_in_progress = false; 2841 dmaengine_terminate_all(sport->dma_tx_chan); 2842 } 2843 2844 if (sport->port.suspended && !irq_wake) 2845 lpuart_disable_clks(sport); 2846 2847 return 0; 2848 } 2849 2850 static int __maybe_unused lpuart_resume(struct device *dev) 2851 { 2852 struct lpuart_port *sport = dev_get_drvdata(dev); 2853 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2854 2855 if (sport->port.suspended && !irq_wake) 2856 lpuart_enable_clks(sport); 2857 2858 if (lpuart_is_32(sport)) 2859 lpuart32_setup_watermark_enable(sport); 2860 else 2861 lpuart_setup_watermark_enable(sport); 2862 2863 if (sport->lpuart_dma_rx_use) { 2864 if (irq_wake) { 2865 if (!lpuart_start_rx_dma(sport)) 2866 rx_dma_timer_init(sport); 2867 else 2868 sport->lpuart_dma_rx_use = false; 2869 } 2870 } 2871 2872 lpuart_tx_dma_startup(sport); 2873 2874 if (lpuart_is_32(sport)) 2875 lpuart32_configure(sport); 2876 2877 uart_resume_port(&lpuart_reg, &sport->port); 2878 2879 return 0; 2880 } 2881 2882 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2883 2884 static struct platform_driver lpuart_driver = { 2885 .probe = lpuart_probe, 2886 .remove = lpuart_remove, 2887 .driver = { 2888 .name = "fsl-lpuart", 2889 .of_match_table = lpuart_dt_ids, 2890 .pm = &lpuart_pm_ops, 2891 }, 2892 }; 2893 2894 static int __init lpuart_serial_init(void) 2895 { 2896 int ret = uart_register_driver(&lpuart_reg); 2897 2898 if (ret) 2899 return ret; 2900 2901 ret = platform_driver_register(&lpuart_driver); 2902 if (ret) 2903 uart_unregister_driver(&lpuart_reg); 2904 2905 return ret; 2906 } 2907 2908 static void __exit lpuart_serial_exit(void) 2909 { 2910 platform_driver_unregister(&lpuart_driver); 2911 uart_unregister_driver(&lpuart_reg); 2912 } 2913 2914 module_init(lpuart_serial_init); 2915 module_exit(lpuart_serial_exit); 2916 2917 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2918 MODULE_LICENSE("GPL v2"); 2919