1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale lpuart serial port driver 4 * 5 * Copyright 2012-2014 Freescale Semiconductor, Inc. 6 */ 7 8 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 9 #define SUPPORT_SYSRQ 10 #endif 11 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dmapool.h> 17 #include <linux/io.h> 18 #include <linux/irq.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/of_dma.h> 23 #include <linux/serial_core.h> 24 #include <linux/slab.h> 25 #include <linux/tty_flip.h> 26 27 /* All registers are 8-bit width */ 28 #define UARTBDH 0x00 29 #define UARTBDL 0x01 30 #define UARTCR1 0x02 31 #define UARTCR2 0x03 32 #define UARTSR1 0x04 33 #define UARTCR3 0x06 34 #define UARTDR 0x07 35 #define UARTCR4 0x0a 36 #define UARTCR5 0x0b 37 #define UARTMODEM 0x0d 38 #define UARTPFIFO 0x10 39 #define UARTCFIFO 0x11 40 #define UARTSFIFO 0x12 41 #define UARTTWFIFO 0x13 42 #define UARTTCFIFO 0x14 43 #define UARTRWFIFO 0x15 44 45 #define UARTBDH_LBKDIE 0x80 46 #define UARTBDH_RXEDGIE 0x40 47 #define UARTBDH_SBR_MASK 0x1f 48 49 #define UARTCR1_LOOPS 0x80 50 #define UARTCR1_RSRC 0x20 51 #define UARTCR1_M 0x10 52 #define UARTCR1_WAKE 0x08 53 #define UARTCR1_ILT 0x04 54 #define UARTCR1_PE 0x02 55 #define UARTCR1_PT 0x01 56 57 #define UARTCR2_TIE 0x80 58 #define UARTCR2_TCIE 0x40 59 #define UARTCR2_RIE 0x20 60 #define UARTCR2_ILIE 0x10 61 #define UARTCR2_TE 0x08 62 #define UARTCR2_RE 0x04 63 #define UARTCR2_RWU 0x02 64 #define UARTCR2_SBK 0x01 65 66 #define UARTSR1_TDRE 0x80 67 #define UARTSR1_TC 0x40 68 #define UARTSR1_RDRF 0x20 69 #define UARTSR1_IDLE 0x10 70 #define UARTSR1_OR 0x08 71 #define UARTSR1_NF 0x04 72 #define UARTSR1_FE 0x02 73 #define UARTSR1_PE 0x01 74 75 #define UARTCR3_R8 0x80 76 #define UARTCR3_T8 0x40 77 #define UARTCR3_TXDIR 0x20 78 #define UARTCR3_TXINV 0x10 79 #define UARTCR3_ORIE 0x08 80 #define UARTCR3_NEIE 0x04 81 #define UARTCR3_FEIE 0x02 82 #define UARTCR3_PEIE 0x01 83 84 #define UARTCR4_MAEN1 0x80 85 #define UARTCR4_MAEN2 0x40 86 #define UARTCR4_M10 0x20 87 #define UARTCR4_BRFA_MASK 0x1f 88 #define UARTCR4_BRFA_OFF 0 89 90 #define UARTCR5_TDMAS 0x80 91 #define UARTCR5_RDMAS 0x20 92 93 #define UARTMODEM_RXRTSE 0x08 94 #define UARTMODEM_TXRTSPOL 0x04 95 #define UARTMODEM_TXRTSE 0x02 96 #define UARTMODEM_TXCTSE 0x01 97 98 #define UARTPFIFO_TXFE 0x80 99 #define UARTPFIFO_FIFOSIZE_MASK 0x7 100 #define UARTPFIFO_TXSIZE_OFF 4 101 #define UARTPFIFO_RXFE 0x08 102 #define UARTPFIFO_RXSIZE_OFF 0 103 104 #define UARTCFIFO_TXFLUSH 0x80 105 #define UARTCFIFO_RXFLUSH 0x40 106 #define UARTCFIFO_RXOFE 0x04 107 #define UARTCFIFO_TXOFE 0x02 108 #define UARTCFIFO_RXUFE 0x01 109 110 #define UARTSFIFO_TXEMPT 0x80 111 #define UARTSFIFO_RXEMPT 0x40 112 #define UARTSFIFO_RXOF 0x04 113 #define UARTSFIFO_TXOF 0x02 114 #define UARTSFIFO_RXUF 0x01 115 116 /* 32-bit register definition */ 117 #define UARTBAUD 0x00 118 #define UARTSTAT 0x04 119 #define UARTCTRL 0x08 120 #define UARTDATA 0x0C 121 #define UARTMATCH 0x10 122 #define UARTMODIR 0x14 123 #define UARTFIFO 0x18 124 #define UARTWATER 0x1c 125 126 #define UARTBAUD_MAEN1 0x80000000 127 #define UARTBAUD_MAEN2 0x40000000 128 #define UARTBAUD_M10 0x20000000 129 #define UARTBAUD_TDMAE 0x00800000 130 #define UARTBAUD_RDMAE 0x00200000 131 #define UARTBAUD_MATCFG 0x00400000 132 #define UARTBAUD_BOTHEDGE 0x00020000 133 #define UARTBAUD_RESYNCDIS 0x00010000 134 #define UARTBAUD_LBKDIE 0x00008000 135 #define UARTBAUD_RXEDGIE 0x00004000 136 #define UARTBAUD_SBNS 0x00002000 137 #define UARTBAUD_SBR 0x00000000 138 #define UARTBAUD_SBR_MASK 0x1fff 139 #define UARTBAUD_OSR_MASK 0x1f 140 #define UARTBAUD_OSR_SHIFT 24 141 142 #define UARTSTAT_LBKDIF 0x80000000 143 #define UARTSTAT_RXEDGIF 0x40000000 144 #define UARTSTAT_MSBF 0x20000000 145 #define UARTSTAT_RXINV 0x10000000 146 #define UARTSTAT_RWUID 0x08000000 147 #define UARTSTAT_BRK13 0x04000000 148 #define UARTSTAT_LBKDE 0x02000000 149 #define UARTSTAT_RAF 0x01000000 150 #define UARTSTAT_TDRE 0x00800000 151 #define UARTSTAT_TC 0x00400000 152 #define UARTSTAT_RDRF 0x00200000 153 #define UARTSTAT_IDLE 0x00100000 154 #define UARTSTAT_OR 0x00080000 155 #define UARTSTAT_NF 0x00040000 156 #define UARTSTAT_FE 0x00020000 157 #define UARTSTAT_PE 0x00010000 158 #define UARTSTAT_MA1F 0x00008000 159 #define UARTSTAT_M21F 0x00004000 160 161 #define UARTCTRL_R8T9 0x80000000 162 #define UARTCTRL_R9T8 0x40000000 163 #define UARTCTRL_TXDIR 0x20000000 164 #define UARTCTRL_TXINV 0x10000000 165 #define UARTCTRL_ORIE 0x08000000 166 #define UARTCTRL_NEIE 0x04000000 167 #define UARTCTRL_FEIE 0x02000000 168 #define UARTCTRL_PEIE 0x01000000 169 #define UARTCTRL_TIE 0x00800000 170 #define UARTCTRL_TCIE 0x00400000 171 #define UARTCTRL_RIE 0x00200000 172 #define UARTCTRL_ILIE 0x00100000 173 #define UARTCTRL_TE 0x00080000 174 #define UARTCTRL_RE 0x00040000 175 #define UARTCTRL_RWU 0x00020000 176 #define UARTCTRL_SBK 0x00010000 177 #define UARTCTRL_MA1IE 0x00008000 178 #define UARTCTRL_MA2IE 0x00004000 179 #define UARTCTRL_IDLECFG 0x00000100 180 #define UARTCTRL_LOOPS 0x00000080 181 #define UARTCTRL_DOZEEN 0x00000040 182 #define UARTCTRL_RSRC 0x00000020 183 #define UARTCTRL_M 0x00000010 184 #define UARTCTRL_WAKE 0x00000008 185 #define UARTCTRL_ILT 0x00000004 186 #define UARTCTRL_PE 0x00000002 187 #define UARTCTRL_PT 0x00000001 188 189 #define UARTDATA_NOISY 0x00008000 190 #define UARTDATA_PARITYE 0x00004000 191 #define UARTDATA_FRETSC 0x00002000 192 #define UARTDATA_RXEMPT 0x00001000 193 #define UARTDATA_IDLINE 0x00000800 194 #define UARTDATA_MASK 0x3ff 195 196 #define UARTMODIR_IREN 0x00020000 197 #define UARTMODIR_TXCTSSRC 0x00000020 198 #define UARTMODIR_TXCTSC 0x00000010 199 #define UARTMODIR_RXRTSE 0x00000008 200 #define UARTMODIR_TXRTSPOL 0x00000004 201 #define UARTMODIR_TXRTSE 0x00000002 202 #define UARTMODIR_TXCTSE 0x00000001 203 204 #define UARTFIFO_TXEMPT 0x00800000 205 #define UARTFIFO_RXEMPT 0x00400000 206 #define UARTFIFO_TXOF 0x00020000 207 #define UARTFIFO_RXUF 0x00010000 208 #define UARTFIFO_TXFLUSH 0x00008000 209 #define UARTFIFO_RXFLUSH 0x00004000 210 #define UARTFIFO_TXOFE 0x00000200 211 #define UARTFIFO_RXUFE 0x00000100 212 #define UARTFIFO_TXFE 0x00000080 213 #define UARTFIFO_FIFOSIZE_MASK 0x7 214 #define UARTFIFO_TXSIZE_OFF 4 215 #define UARTFIFO_RXFE 0x00000008 216 #define UARTFIFO_RXSIZE_OFF 0 217 218 #define UARTWATER_COUNT_MASK 0xff 219 #define UARTWATER_TXCNT_OFF 8 220 #define UARTWATER_RXCNT_OFF 24 221 #define UARTWATER_WATER_MASK 0xff 222 #define UARTWATER_TXWATER_OFF 0 223 #define UARTWATER_RXWATER_OFF 16 224 225 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 226 #define DMA_RX_TIMEOUT (10) 227 228 #define DRIVER_NAME "fsl-lpuart" 229 #define DEV_NAME "ttyLP" 230 #define UART_NR 6 231 232 /* IMX lpuart has four extra unused regs located at the beginning */ 233 #define IMX_REG_OFF 0x10 234 235 static DEFINE_IDA(fsl_lpuart_ida); 236 237 struct lpuart_port { 238 struct uart_port port; 239 struct clk *clk; 240 unsigned int txfifo_size; 241 unsigned int rxfifo_size; 242 243 bool lpuart_dma_tx_use; 244 bool lpuart_dma_rx_use; 245 struct dma_chan *dma_tx_chan; 246 struct dma_chan *dma_rx_chan; 247 struct dma_async_tx_descriptor *dma_tx_desc; 248 struct dma_async_tx_descriptor *dma_rx_desc; 249 dma_cookie_t dma_tx_cookie; 250 dma_cookie_t dma_rx_cookie; 251 unsigned int dma_tx_bytes; 252 unsigned int dma_rx_bytes; 253 bool dma_tx_in_progress; 254 unsigned int dma_rx_timeout; 255 struct timer_list lpuart_timer; 256 struct scatterlist rx_sgl, tx_sgl[2]; 257 struct circ_buf rx_ring; 258 int rx_dma_rng_buf_len; 259 unsigned int dma_tx_nents; 260 wait_queue_head_t dma_wait; 261 }; 262 263 struct lpuart_soc_data { 264 char iotype; 265 u8 reg_off; 266 }; 267 268 static const struct lpuart_soc_data vf_data = { 269 .iotype = UPIO_MEM, 270 }; 271 272 static const struct lpuart_soc_data ls_data = { 273 .iotype = UPIO_MEM32BE, 274 }; 275 276 static struct lpuart_soc_data imx_data = { 277 .iotype = UPIO_MEM32, 278 .reg_off = IMX_REG_OFF, 279 }; 280 281 static const struct of_device_id lpuart_dt_ids[] = { 282 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 283 { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, }, 284 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx_data, }, 285 { /* sentinel */ } 286 }; 287 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 288 289 /* Forward declare this for the dma callbacks*/ 290 static void lpuart_dma_tx_complete(void *arg); 291 292 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 293 { 294 switch (port->iotype) { 295 case UPIO_MEM32: 296 return readl(port->membase + off); 297 case UPIO_MEM32BE: 298 return ioread32be(port->membase + off); 299 default: 300 return 0; 301 } 302 } 303 304 static inline void lpuart32_write(struct uart_port *port, u32 val, 305 u32 off) 306 { 307 switch (port->iotype) { 308 case UPIO_MEM32: 309 writel(val, port->membase + off); 310 break; 311 case UPIO_MEM32BE: 312 iowrite32be(val, port->membase + off); 313 break; 314 } 315 } 316 317 static void lpuart_stop_tx(struct uart_port *port) 318 { 319 unsigned char temp; 320 321 temp = readb(port->membase + UARTCR2); 322 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 323 writeb(temp, port->membase + UARTCR2); 324 } 325 326 static void lpuart32_stop_tx(struct uart_port *port) 327 { 328 unsigned long temp; 329 330 temp = lpuart32_read(port, UARTCTRL); 331 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 332 lpuart32_write(port, temp, UARTCTRL); 333 } 334 335 static void lpuart_stop_rx(struct uart_port *port) 336 { 337 unsigned char temp; 338 339 temp = readb(port->membase + UARTCR2); 340 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 341 } 342 343 static void lpuart32_stop_rx(struct uart_port *port) 344 { 345 unsigned long temp; 346 347 temp = lpuart32_read(port, UARTCTRL); 348 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); 349 } 350 351 static void lpuart_dma_tx(struct lpuart_port *sport) 352 { 353 struct circ_buf *xmit = &sport->port.state->xmit; 354 struct scatterlist *sgl = sport->tx_sgl; 355 struct device *dev = sport->port.dev; 356 int ret; 357 358 if (sport->dma_tx_in_progress) 359 return; 360 361 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 362 363 if (xmit->tail < xmit->head || xmit->head == 0) { 364 sport->dma_tx_nents = 1; 365 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 366 } else { 367 sport->dma_tx_nents = 2; 368 sg_init_table(sgl, 2); 369 sg_set_buf(sgl, xmit->buf + xmit->tail, 370 UART_XMIT_SIZE - xmit->tail); 371 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 372 } 373 374 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 375 if (!ret) { 376 dev_err(dev, "DMA mapping error for TX.\n"); 377 return; 378 } 379 380 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl, 381 sport->dma_tx_nents, 382 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 383 if (!sport->dma_tx_desc) { 384 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 385 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 386 return; 387 } 388 389 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 390 sport->dma_tx_desc->callback_param = sport; 391 sport->dma_tx_in_progress = true; 392 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 393 dma_async_issue_pending(sport->dma_tx_chan); 394 } 395 396 static void lpuart_dma_tx_complete(void *arg) 397 { 398 struct lpuart_port *sport = arg; 399 struct scatterlist *sgl = &sport->tx_sgl[0]; 400 struct circ_buf *xmit = &sport->port.state->xmit; 401 unsigned long flags; 402 403 spin_lock_irqsave(&sport->port.lock, flags); 404 405 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 406 407 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 408 409 sport->port.icount.tx += sport->dma_tx_bytes; 410 sport->dma_tx_in_progress = false; 411 spin_unlock_irqrestore(&sport->port.lock, flags); 412 413 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 414 uart_write_wakeup(&sport->port); 415 416 if (waitqueue_active(&sport->dma_wait)) { 417 wake_up(&sport->dma_wait); 418 return; 419 } 420 421 spin_lock_irqsave(&sport->port.lock, flags); 422 423 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 424 lpuart_dma_tx(sport); 425 426 spin_unlock_irqrestore(&sport->port.lock, flags); 427 } 428 429 static int lpuart_dma_tx_request(struct uart_port *port) 430 { 431 struct lpuart_port *sport = container_of(port, 432 struct lpuart_port, port); 433 struct dma_slave_config dma_tx_sconfig = {}; 434 int ret; 435 436 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR; 437 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 438 dma_tx_sconfig.dst_maxburst = 1; 439 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 440 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 441 442 if (ret) { 443 dev_err(sport->port.dev, 444 "DMA slave config failed, err = %d\n", ret); 445 return ret; 446 } 447 448 return 0; 449 } 450 451 static void lpuart_flush_buffer(struct uart_port *port) 452 { 453 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 454 455 if (sport->lpuart_dma_tx_use) { 456 if (sport->dma_tx_in_progress) { 457 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 458 sport->dma_tx_nents, DMA_TO_DEVICE); 459 sport->dma_tx_in_progress = false; 460 } 461 dmaengine_terminate_all(sport->dma_tx_chan); 462 } 463 } 464 465 #if defined(CONFIG_CONSOLE_POLL) 466 467 static int lpuart_poll_init(struct uart_port *port) 468 { 469 struct lpuart_port *sport = container_of(port, 470 struct lpuart_port, port); 471 unsigned long flags; 472 unsigned char temp; 473 474 sport->port.fifosize = 0; 475 476 spin_lock_irqsave(&sport->port.lock, flags); 477 /* Disable Rx & Tx */ 478 writeb(0, sport->port.membase + UARTCR2); 479 480 temp = readb(sport->port.membase + UARTPFIFO); 481 /* Enable Rx and Tx FIFO */ 482 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 483 sport->port.membase + UARTPFIFO); 484 485 /* flush Tx and Rx FIFO */ 486 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 487 sport->port.membase + UARTCFIFO); 488 489 /* explicitly clear RDRF */ 490 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 491 readb(sport->port.membase + UARTDR); 492 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 493 } 494 495 writeb(0, sport->port.membase + UARTTWFIFO); 496 writeb(1, sport->port.membase + UARTRWFIFO); 497 498 /* Enable Rx and Tx */ 499 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 500 spin_unlock_irqrestore(&sport->port.lock, flags); 501 502 return 0; 503 } 504 505 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 506 { 507 /* drain */ 508 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) 509 barrier(); 510 511 writeb(c, port->membase + UARTDR); 512 } 513 514 static int lpuart_poll_get_char(struct uart_port *port) 515 { 516 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 517 return NO_POLL_CHAR; 518 519 return readb(port->membase + UARTDR); 520 } 521 522 static int lpuart32_poll_init(struct uart_port *port) 523 { 524 unsigned long flags; 525 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 526 u32 temp; 527 528 sport->port.fifosize = 0; 529 530 spin_lock_irqsave(&sport->port.lock, flags); 531 532 /* Disable Rx & Tx */ 533 writel(0, sport->port.membase + UARTCTRL); 534 535 temp = readl(sport->port.membase + UARTFIFO); 536 537 /* Enable Rx and Tx FIFO */ 538 writel(temp | UARTFIFO_RXFE | UARTFIFO_TXFE, 539 sport->port.membase + UARTFIFO); 540 541 /* flush Tx and Rx FIFO */ 542 writel(UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, 543 sport->port.membase + UARTFIFO); 544 545 /* explicitly clear RDRF */ 546 if (readl(sport->port.membase + UARTSTAT) & UARTSTAT_RDRF) { 547 readl(sport->port.membase + UARTDATA); 548 writel(UARTFIFO_RXUF, sport->port.membase + UARTFIFO); 549 } 550 551 /* Enable Rx and Tx */ 552 writel(UARTCTRL_RE | UARTCTRL_TE, sport->port.membase + UARTCTRL); 553 spin_unlock_irqrestore(&sport->port.lock, flags); 554 555 return 0; 556 } 557 558 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 559 { 560 while (!(readl(port->membase + UARTSTAT) & UARTSTAT_TDRE)) 561 barrier(); 562 563 writel(c, port->membase + UARTDATA); 564 } 565 566 static int lpuart32_poll_get_char(struct uart_port *port) 567 { 568 if (!(readl(port->membase + UARTSTAT) & UARTSTAT_RDRF)) 569 return NO_POLL_CHAR; 570 571 return readl(port->membase + UARTDATA); 572 } 573 #endif 574 575 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 576 { 577 struct circ_buf *xmit = &sport->port.state->xmit; 578 579 while (!uart_circ_empty(xmit) && 580 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 581 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 582 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 583 sport->port.icount.tx++; 584 } 585 586 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 587 uart_write_wakeup(&sport->port); 588 589 if (uart_circ_empty(xmit)) 590 lpuart_stop_tx(&sport->port); 591 } 592 593 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 594 { 595 struct circ_buf *xmit = &sport->port.state->xmit; 596 unsigned long txcnt; 597 598 txcnt = lpuart32_read(&sport->port, UARTWATER); 599 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 600 txcnt &= UARTWATER_COUNT_MASK; 601 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 602 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); 603 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 604 sport->port.icount.tx++; 605 txcnt = lpuart32_read(&sport->port, UARTWATER); 606 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 607 txcnt &= UARTWATER_COUNT_MASK; 608 } 609 610 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 611 uart_write_wakeup(&sport->port); 612 613 if (uart_circ_empty(xmit)) 614 lpuart32_stop_tx(&sport->port); 615 } 616 617 static void lpuart_start_tx(struct uart_port *port) 618 { 619 struct lpuart_port *sport = container_of(port, 620 struct lpuart_port, port); 621 struct circ_buf *xmit = &sport->port.state->xmit; 622 unsigned char temp; 623 624 temp = readb(port->membase + UARTCR2); 625 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 626 627 if (sport->lpuart_dma_tx_use) { 628 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) 629 lpuart_dma_tx(sport); 630 } else { 631 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 632 lpuart_transmit_buffer(sport); 633 } 634 } 635 636 static void lpuart32_start_tx(struct uart_port *port) 637 { 638 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 639 unsigned long temp; 640 641 temp = lpuart32_read(port, UARTCTRL); 642 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); 643 644 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 645 lpuart32_transmit_buffer(sport); 646 } 647 648 /* return TIOCSER_TEMT when transmitter is not busy */ 649 static unsigned int lpuart_tx_empty(struct uart_port *port) 650 { 651 struct lpuart_port *sport = container_of(port, 652 struct lpuart_port, port); 653 unsigned char sr1 = readb(port->membase + UARTSR1); 654 unsigned char sfifo = readb(port->membase + UARTSFIFO); 655 656 if (sport->dma_tx_in_progress) 657 return 0; 658 659 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 660 return TIOCSER_TEMT; 661 662 return 0; 663 } 664 665 static unsigned int lpuart32_tx_empty(struct uart_port *port) 666 { 667 return (lpuart32_read(port, UARTSTAT) & UARTSTAT_TC) ? 668 TIOCSER_TEMT : 0; 669 } 670 671 static bool lpuart_is_32(struct lpuart_port *sport) 672 { 673 return sport->port.iotype == UPIO_MEM32 || 674 sport->port.iotype == UPIO_MEM32BE; 675 } 676 677 static irqreturn_t lpuart_txint(int irq, void *dev_id) 678 { 679 struct lpuart_port *sport = dev_id; 680 struct circ_buf *xmit = &sport->port.state->xmit; 681 unsigned long flags; 682 683 spin_lock_irqsave(&sport->port.lock, flags); 684 if (sport->port.x_char) { 685 if (lpuart_is_32(sport)) 686 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 687 else 688 writeb(sport->port.x_char, sport->port.membase + UARTDR); 689 goto out; 690 } 691 692 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 693 if (lpuart_is_32(sport)) 694 lpuart32_stop_tx(&sport->port); 695 else 696 lpuart_stop_tx(&sport->port); 697 goto out; 698 } 699 700 if (lpuart_is_32(sport)) 701 lpuart32_transmit_buffer(sport); 702 else 703 lpuart_transmit_buffer(sport); 704 705 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 706 uart_write_wakeup(&sport->port); 707 708 out: 709 spin_unlock_irqrestore(&sport->port.lock, flags); 710 return IRQ_HANDLED; 711 } 712 713 static irqreturn_t lpuart_rxint(int irq, void *dev_id) 714 { 715 struct lpuart_port *sport = dev_id; 716 unsigned int flg, ignored = 0; 717 struct tty_port *port = &sport->port.state->port; 718 unsigned long flags; 719 unsigned char rx, sr; 720 721 spin_lock_irqsave(&sport->port.lock, flags); 722 723 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 724 flg = TTY_NORMAL; 725 sport->port.icount.rx++; 726 /* 727 * to clear the FE, OR, NF, FE, PE flags, 728 * read SR1 then read DR 729 */ 730 sr = readb(sport->port.membase + UARTSR1); 731 rx = readb(sport->port.membase + UARTDR); 732 733 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 734 continue; 735 736 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 737 if (sr & UARTSR1_PE) 738 sport->port.icount.parity++; 739 else if (sr & UARTSR1_FE) 740 sport->port.icount.frame++; 741 742 if (sr & UARTSR1_OR) 743 sport->port.icount.overrun++; 744 745 if (sr & sport->port.ignore_status_mask) { 746 if (++ignored > 100) 747 goto out; 748 continue; 749 } 750 751 sr &= sport->port.read_status_mask; 752 753 if (sr & UARTSR1_PE) 754 flg = TTY_PARITY; 755 else if (sr & UARTSR1_FE) 756 flg = TTY_FRAME; 757 758 if (sr & UARTSR1_OR) 759 flg = TTY_OVERRUN; 760 761 #ifdef SUPPORT_SYSRQ 762 sport->port.sysrq = 0; 763 #endif 764 } 765 766 tty_insert_flip_char(port, rx, flg); 767 } 768 769 out: 770 spin_unlock_irqrestore(&sport->port.lock, flags); 771 772 tty_flip_buffer_push(port); 773 return IRQ_HANDLED; 774 } 775 776 static irqreturn_t lpuart32_rxint(int irq, void *dev_id) 777 { 778 struct lpuart_port *sport = dev_id; 779 unsigned int flg, ignored = 0; 780 struct tty_port *port = &sport->port.state->port; 781 unsigned long flags; 782 unsigned long rx, sr; 783 784 spin_lock_irqsave(&sport->port.lock, flags); 785 786 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 787 flg = TTY_NORMAL; 788 sport->port.icount.rx++; 789 /* 790 * to clear the FE, OR, NF, FE, PE flags, 791 * read STAT then read DATA reg 792 */ 793 sr = lpuart32_read(&sport->port, UARTSTAT); 794 rx = lpuart32_read(&sport->port, UARTDATA); 795 rx &= 0x3ff; 796 797 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 798 continue; 799 800 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 801 if (sr & UARTSTAT_PE) 802 sport->port.icount.parity++; 803 else if (sr & UARTSTAT_FE) 804 sport->port.icount.frame++; 805 806 if (sr & UARTSTAT_OR) 807 sport->port.icount.overrun++; 808 809 if (sr & sport->port.ignore_status_mask) { 810 if (++ignored > 100) 811 goto out; 812 continue; 813 } 814 815 sr &= sport->port.read_status_mask; 816 817 if (sr & UARTSTAT_PE) 818 flg = TTY_PARITY; 819 else if (sr & UARTSTAT_FE) 820 flg = TTY_FRAME; 821 822 if (sr & UARTSTAT_OR) 823 flg = TTY_OVERRUN; 824 825 #ifdef SUPPORT_SYSRQ 826 sport->port.sysrq = 0; 827 #endif 828 } 829 830 tty_insert_flip_char(port, rx, flg); 831 } 832 833 out: 834 spin_unlock_irqrestore(&sport->port.lock, flags); 835 836 tty_flip_buffer_push(port); 837 return IRQ_HANDLED; 838 } 839 840 static irqreturn_t lpuart_int(int irq, void *dev_id) 841 { 842 struct lpuart_port *sport = dev_id; 843 unsigned char sts; 844 845 sts = readb(sport->port.membase + UARTSR1); 846 847 if (sts & UARTSR1_RDRF) 848 lpuart_rxint(irq, dev_id); 849 850 if (sts & UARTSR1_TDRE) 851 lpuart_txint(irq, dev_id); 852 853 return IRQ_HANDLED; 854 } 855 856 static irqreturn_t lpuart32_int(int irq, void *dev_id) 857 { 858 struct lpuart_port *sport = dev_id; 859 unsigned long sts, rxcount; 860 861 sts = lpuart32_read(&sport->port, UARTSTAT); 862 rxcount = lpuart32_read(&sport->port, UARTWATER); 863 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 864 865 if (sts & UARTSTAT_RDRF || rxcount > 0) 866 lpuart32_rxint(irq, dev_id); 867 868 if ((sts & UARTSTAT_TDRE) && 869 !(lpuart32_read(&sport->port, UARTBAUD) & UARTBAUD_TDMAE)) 870 lpuart_txint(irq, dev_id); 871 872 lpuart32_write(&sport->port, sts, UARTSTAT); 873 return IRQ_HANDLED; 874 } 875 876 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 877 { 878 struct tty_port *port = &sport->port.state->port; 879 struct dma_tx_state state; 880 enum dma_status dmastat; 881 struct circ_buf *ring = &sport->rx_ring; 882 unsigned long flags; 883 int count = 0; 884 unsigned char sr; 885 886 sr = readb(sport->port.membase + UARTSR1); 887 888 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 889 /* Read DR to clear the error flags */ 890 readb(sport->port.membase + UARTDR); 891 892 if (sr & UARTSR1_PE) 893 sport->port.icount.parity++; 894 else if (sr & UARTSR1_FE) 895 sport->port.icount.frame++; 896 } 897 898 async_tx_ack(sport->dma_rx_desc); 899 900 spin_lock_irqsave(&sport->port.lock, flags); 901 902 dmastat = dmaengine_tx_status(sport->dma_rx_chan, 903 sport->dma_rx_cookie, 904 &state); 905 906 if (dmastat == DMA_ERROR) { 907 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 908 spin_unlock_irqrestore(&sport->port.lock, flags); 909 return; 910 } 911 912 /* CPU claims ownership of RX DMA buffer */ 913 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 914 915 /* 916 * ring->head points to the end of data already written by the DMA. 917 * ring->tail points to the beginning of data to be read by the 918 * framework. 919 * The current transfer size should not be larger than the dma buffer 920 * length. 921 */ 922 ring->head = sport->rx_sgl.length - state.residue; 923 BUG_ON(ring->head > sport->rx_sgl.length); 924 /* 925 * At this point ring->head may point to the first byte right after the 926 * last byte of the dma buffer: 927 * 0 <= ring->head <= sport->rx_sgl.length 928 * 929 * However ring->tail must always points inside the dma buffer: 930 * 0 <= ring->tail <= sport->rx_sgl.length - 1 931 * 932 * Since we use a ring buffer, we have to handle the case 933 * where head is lower than tail. In such a case, we first read from 934 * tail to the end of the buffer then reset tail. 935 */ 936 if (ring->head < ring->tail) { 937 count = sport->rx_sgl.length - ring->tail; 938 939 tty_insert_flip_string(port, ring->buf + ring->tail, count); 940 ring->tail = 0; 941 sport->port.icount.rx += count; 942 } 943 944 /* Finally we read data from tail to head */ 945 if (ring->tail < ring->head) { 946 count = ring->head - ring->tail; 947 tty_insert_flip_string(port, ring->buf + ring->tail, count); 948 /* Wrap ring->head if needed */ 949 if (ring->head >= sport->rx_sgl.length) 950 ring->head = 0; 951 ring->tail = ring->head; 952 sport->port.icount.rx += count; 953 } 954 955 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1, 956 DMA_FROM_DEVICE); 957 958 spin_unlock_irqrestore(&sport->port.lock, flags); 959 960 tty_flip_buffer_push(port); 961 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 962 } 963 964 static void lpuart_dma_rx_complete(void *arg) 965 { 966 struct lpuart_port *sport = arg; 967 968 lpuart_copy_rx_to_tty(sport); 969 } 970 971 static void lpuart_timer_func(struct timer_list *t) 972 { 973 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); 974 975 lpuart_copy_rx_to_tty(sport); 976 } 977 978 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 979 { 980 struct dma_slave_config dma_rx_sconfig = {}; 981 struct circ_buf *ring = &sport->rx_ring; 982 int ret, nent; 983 int bits, baud; 984 struct tty_port *port = &sport->port.state->port; 985 struct tty_struct *tty = port->tty; 986 struct ktermios *termios = &tty->termios; 987 988 baud = tty_get_baud_rate(tty); 989 990 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; 991 if (termios->c_cflag & PARENB) 992 bits++; 993 994 /* 995 * Calculate length of one DMA buffer size to keep latency below 996 * 10ms at any baud rate. 997 */ 998 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 999 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 1000 if (sport->rx_dma_rng_buf_len < 16) 1001 sport->rx_dma_rng_buf_len = 16; 1002 1003 ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1004 if (!ring->buf) { 1005 dev_err(sport->port.dev, "Ring buf alloc failed\n"); 1006 return -ENOMEM; 1007 } 1008 1009 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1010 sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1011 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1012 1013 if (!nent) { 1014 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1015 return -EINVAL; 1016 } 1017 1018 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR; 1019 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1020 dma_rx_sconfig.src_maxburst = 1; 1021 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1022 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig); 1023 1024 if (ret < 0) { 1025 dev_err(sport->port.dev, 1026 "DMA Rx slave config failed, err = %d\n", ret); 1027 return ret; 1028 } 1029 1030 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan, 1031 sg_dma_address(&sport->rx_sgl), 1032 sport->rx_sgl.length, 1033 sport->rx_sgl.length / 2, 1034 DMA_DEV_TO_MEM, 1035 DMA_PREP_INTERRUPT); 1036 if (!sport->dma_rx_desc) { 1037 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1038 return -EFAULT; 1039 } 1040 1041 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1042 sport->dma_rx_desc->callback_param = sport; 1043 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1044 dma_async_issue_pending(sport->dma_rx_chan); 1045 1046 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1047 sport->port.membase + UARTCR5); 1048 1049 return 0; 1050 } 1051 1052 static void lpuart_dma_rx_free(struct uart_port *port) 1053 { 1054 struct lpuart_port *sport = container_of(port, 1055 struct lpuart_port, port); 1056 1057 if (sport->dma_rx_chan) 1058 dmaengine_terminate_all(sport->dma_rx_chan); 1059 1060 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1061 kfree(sport->rx_ring.buf); 1062 sport->rx_ring.tail = 0; 1063 sport->rx_ring.head = 0; 1064 sport->dma_rx_desc = NULL; 1065 sport->dma_rx_cookie = -EINVAL; 1066 } 1067 1068 static int lpuart_config_rs485(struct uart_port *port, 1069 struct serial_rs485 *rs485) 1070 { 1071 struct lpuart_port *sport = container_of(port, 1072 struct lpuart_port, port); 1073 1074 u8 modem = readb(sport->port.membase + UARTMODEM) & 1075 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1076 writeb(modem, sport->port.membase + UARTMODEM); 1077 1078 /* clear unsupported configurations */ 1079 rs485->delay_rts_before_send = 0; 1080 rs485->delay_rts_after_send = 0; 1081 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1082 1083 if (rs485->flags & SER_RS485_ENABLED) { 1084 /* Enable auto RS-485 RTS mode */ 1085 modem |= UARTMODEM_TXRTSE; 1086 1087 /* 1088 * RTS needs to be logic HIGH either during transer _or_ after 1089 * transfer, other variants are not supported by the hardware. 1090 */ 1091 1092 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1093 SER_RS485_RTS_AFTER_SEND))) 1094 rs485->flags |= SER_RS485_RTS_ON_SEND; 1095 1096 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1097 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1098 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1099 1100 /* 1101 * The hardware defaults to RTS logic HIGH while transfer. 1102 * Switch polarity in case RTS shall be logic HIGH 1103 * after transfer. 1104 * Note: UART is assumed to be active high. 1105 */ 1106 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1107 modem &= ~UARTMODEM_TXRTSPOL; 1108 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1109 modem |= UARTMODEM_TXRTSPOL; 1110 } 1111 1112 /* Store the new configuration */ 1113 sport->port.rs485 = *rs485; 1114 1115 writeb(modem, sport->port.membase + UARTMODEM); 1116 return 0; 1117 } 1118 1119 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1120 { 1121 unsigned int temp = 0; 1122 unsigned char reg; 1123 1124 reg = readb(port->membase + UARTMODEM); 1125 if (reg & UARTMODEM_TXCTSE) 1126 temp |= TIOCM_CTS; 1127 1128 if (reg & UARTMODEM_RXRTSE) 1129 temp |= TIOCM_RTS; 1130 1131 return temp; 1132 } 1133 1134 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1135 { 1136 unsigned int temp = 0; 1137 unsigned long reg; 1138 1139 reg = lpuart32_read(port, UARTMODIR); 1140 if (reg & UARTMODIR_TXCTSE) 1141 temp |= TIOCM_CTS; 1142 1143 if (reg & UARTMODIR_RXRTSE) 1144 temp |= TIOCM_RTS; 1145 1146 return temp; 1147 } 1148 1149 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1150 { 1151 unsigned char temp; 1152 struct lpuart_port *sport = container_of(port, 1153 struct lpuart_port, port); 1154 1155 /* Make sure RXRTSE bit is not set when RS485 is enabled */ 1156 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { 1157 temp = readb(sport->port.membase + UARTMODEM) & 1158 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1159 1160 if (mctrl & TIOCM_RTS) 1161 temp |= UARTMODEM_RXRTSE; 1162 1163 if (mctrl & TIOCM_CTS) 1164 temp |= UARTMODEM_TXCTSE; 1165 1166 writeb(temp, port->membase + UARTMODEM); 1167 } 1168 } 1169 1170 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1171 { 1172 unsigned long temp; 1173 1174 temp = lpuart32_read(port, UARTMODIR) & 1175 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 1176 1177 if (mctrl & TIOCM_RTS) 1178 temp |= UARTMODIR_RXRTSE; 1179 1180 if (mctrl & TIOCM_CTS) 1181 temp |= UARTMODIR_TXCTSE; 1182 1183 lpuart32_write(port, temp, UARTMODIR); 1184 } 1185 1186 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1187 { 1188 unsigned char temp; 1189 1190 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1191 1192 if (break_state != 0) 1193 temp |= UARTCR2_SBK; 1194 1195 writeb(temp, port->membase + UARTCR2); 1196 } 1197 1198 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1199 { 1200 unsigned long temp; 1201 1202 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; 1203 1204 if (break_state != 0) 1205 temp |= UARTCTRL_SBK; 1206 1207 lpuart32_write(port, temp, UARTCTRL); 1208 } 1209 1210 static void lpuart_setup_watermark(struct lpuart_port *sport) 1211 { 1212 unsigned char val, cr2; 1213 unsigned char cr2_saved; 1214 1215 cr2 = readb(sport->port.membase + UARTCR2); 1216 cr2_saved = cr2; 1217 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1218 UARTCR2_RIE | UARTCR2_RE); 1219 writeb(cr2, sport->port.membase + UARTCR2); 1220 1221 val = readb(sport->port.membase + UARTPFIFO); 1222 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1223 sport->port.membase + UARTPFIFO); 1224 1225 /* flush Tx and Rx FIFO */ 1226 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1227 sport->port.membase + UARTCFIFO); 1228 1229 /* explicitly clear RDRF */ 1230 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1231 readb(sport->port.membase + UARTDR); 1232 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1233 } 1234 1235 writeb(0, sport->port.membase + UARTTWFIFO); 1236 writeb(1, sport->port.membase + UARTRWFIFO); 1237 1238 /* Restore cr2 */ 1239 writeb(cr2_saved, sport->port.membase + UARTCR2); 1240 } 1241 1242 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1243 { 1244 unsigned long val, ctrl; 1245 unsigned long ctrl_saved; 1246 1247 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1248 ctrl_saved = ctrl; 1249 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1250 UARTCTRL_RIE | UARTCTRL_RE); 1251 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1252 1253 /* enable FIFO mode */ 1254 val = lpuart32_read(&sport->port, UARTFIFO); 1255 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1256 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1257 lpuart32_write(&sport->port, val, UARTFIFO); 1258 1259 /* set the watermark */ 1260 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1261 lpuart32_write(&sport->port, val, UARTWATER); 1262 1263 /* Restore cr2 */ 1264 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1265 } 1266 1267 static void rx_dma_timer_init(struct lpuart_port *sport) 1268 { 1269 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); 1270 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1271 add_timer(&sport->lpuart_timer); 1272 } 1273 1274 static int lpuart_startup(struct uart_port *port) 1275 { 1276 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1277 unsigned long flags; 1278 unsigned char temp; 1279 1280 /* determine FIFO size and enable FIFO mode */ 1281 temp = readb(sport->port.membase + UARTPFIFO); 1282 1283 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) & 1284 UARTPFIFO_FIFOSIZE_MASK) + 1); 1285 1286 sport->port.fifosize = sport->txfifo_size; 1287 1288 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) & 1289 UARTPFIFO_FIFOSIZE_MASK) + 1); 1290 1291 spin_lock_irqsave(&sport->port.lock, flags); 1292 1293 lpuart_setup_watermark(sport); 1294 1295 temp = readb(sport->port.membase + UARTCR2); 1296 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 1297 writeb(temp, sport->port.membase + UARTCR2); 1298 1299 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) { 1300 /* set Rx DMA timeout */ 1301 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1302 if (!sport->dma_rx_timeout) 1303 sport->dma_rx_timeout = 1; 1304 1305 sport->lpuart_dma_rx_use = true; 1306 rx_dma_timer_init(sport); 1307 } else { 1308 sport->lpuart_dma_rx_use = false; 1309 } 1310 1311 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) { 1312 init_waitqueue_head(&sport->dma_wait); 1313 sport->lpuart_dma_tx_use = true; 1314 temp = readb(port->membase + UARTCR5); 1315 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5); 1316 } else { 1317 sport->lpuart_dma_tx_use = false; 1318 } 1319 1320 spin_unlock_irqrestore(&sport->port.lock, flags); 1321 1322 return 0; 1323 } 1324 1325 static int lpuart32_startup(struct uart_port *port) 1326 { 1327 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1328 unsigned long flags; 1329 unsigned long temp; 1330 1331 /* determine FIFO size */ 1332 temp = lpuart32_read(&sport->port, UARTFIFO); 1333 1334 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) & 1335 UARTFIFO_FIFOSIZE_MASK) - 1); 1336 1337 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) & 1338 UARTFIFO_FIFOSIZE_MASK) - 1); 1339 1340 spin_lock_irqsave(&sport->port.lock, flags); 1341 1342 lpuart32_setup_watermark(sport); 1343 1344 temp = lpuart32_read(&sport->port, UARTCTRL); 1345 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE); 1346 temp |= UARTCTRL_ILIE; 1347 lpuart32_write(&sport->port, temp, UARTCTRL); 1348 1349 spin_unlock_irqrestore(&sport->port.lock, flags); 1350 return 0; 1351 } 1352 1353 static void lpuart_shutdown(struct uart_port *port) 1354 { 1355 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1356 unsigned char temp; 1357 unsigned long flags; 1358 1359 spin_lock_irqsave(&port->lock, flags); 1360 1361 /* disable Rx/Tx and interrupts */ 1362 temp = readb(port->membase + UARTCR2); 1363 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1364 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1365 writeb(temp, port->membase + UARTCR2); 1366 1367 spin_unlock_irqrestore(&port->lock, flags); 1368 1369 if (sport->lpuart_dma_rx_use) { 1370 del_timer_sync(&sport->lpuart_timer); 1371 lpuart_dma_rx_free(&sport->port); 1372 } 1373 1374 if (sport->lpuart_dma_tx_use) { 1375 if (wait_event_interruptible(sport->dma_wait, 1376 !sport->dma_tx_in_progress) != false) { 1377 sport->dma_tx_in_progress = false; 1378 dmaengine_terminate_all(sport->dma_tx_chan); 1379 } 1380 1381 lpuart_stop_tx(port); 1382 } 1383 } 1384 1385 static void lpuart32_shutdown(struct uart_port *port) 1386 { 1387 unsigned long temp; 1388 unsigned long flags; 1389 1390 spin_lock_irqsave(&port->lock, flags); 1391 1392 /* disable Rx/Tx and interrupts */ 1393 temp = lpuart32_read(port, UARTCTRL); 1394 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1395 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1396 lpuart32_write(port, temp, UARTCTRL); 1397 1398 spin_unlock_irqrestore(&port->lock, flags); 1399 } 1400 1401 static void 1402 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1403 struct ktermios *old) 1404 { 1405 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1406 unsigned long flags; 1407 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1408 unsigned int baud; 1409 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1410 unsigned int sbr, brfa; 1411 1412 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1413 old_cr2 = readb(sport->port.membase + UARTCR2); 1414 cr3 = readb(sport->port.membase + UARTCR3); 1415 cr4 = readb(sport->port.membase + UARTCR4); 1416 bdh = readb(sport->port.membase + UARTBDH); 1417 modem = readb(sport->port.membase + UARTMODEM); 1418 /* 1419 * only support CS8 and CS7, and for CS7 must enable PE. 1420 * supported mode: 1421 * - (7,e/o,1) 1422 * - (8,n,1) 1423 * - (8,m/s,1) 1424 * - (8,e/o,1) 1425 */ 1426 while ((termios->c_cflag & CSIZE) != CS8 && 1427 (termios->c_cflag & CSIZE) != CS7) { 1428 termios->c_cflag &= ~CSIZE; 1429 termios->c_cflag |= old_csize; 1430 old_csize = CS8; 1431 } 1432 1433 if ((termios->c_cflag & CSIZE) == CS8 || 1434 (termios->c_cflag & CSIZE) == CS7) 1435 cr1 = old_cr1 & ~UARTCR1_M; 1436 1437 if (termios->c_cflag & CMSPAR) { 1438 if ((termios->c_cflag & CSIZE) != CS8) { 1439 termios->c_cflag &= ~CSIZE; 1440 termios->c_cflag |= CS8; 1441 } 1442 cr1 |= UARTCR1_M; 1443 } 1444 1445 /* 1446 * When auto RS-485 RTS mode is enabled, 1447 * hardware flow control need to be disabled. 1448 */ 1449 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1450 termios->c_cflag &= ~CRTSCTS; 1451 1452 if (termios->c_cflag & CRTSCTS) { 1453 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1454 } else { 1455 termios->c_cflag &= ~CRTSCTS; 1456 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1457 } 1458 1459 if (termios->c_cflag & CSTOPB) 1460 termios->c_cflag &= ~CSTOPB; 1461 1462 /* parity must be enabled when CS7 to match 8-bits format */ 1463 if ((termios->c_cflag & CSIZE) == CS7) 1464 termios->c_cflag |= PARENB; 1465 1466 if ((termios->c_cflag & PARENB)) { 1467 if (termios->c_cflag & CMSPAR) { 1468 cr1 &= ~UARTCR1_PE; 1469 if (termios->c_cflag & PARODD) 1470 cr3 |= UARTCR3_T8; 1471 else 1472 cr3 &= ~UARTCR3_T8; 1473 } else { 1474 cr1 |= UARTCR1_PE; 1475 if ((termios->c_cflag & CSIZE) == CS8) 1476 cr1 |= UARTCR1_M; 1477 if (termios->c_cflag & PARODD) 1478 cr1 |= UARTCR1_PT; 1479 else 1480 cr1 &= ~UARTCR1_PT; 1481 } 1482 } else { 1483 cr1 &= ~UARTCR1_PE; 1484 } 1485 1486 /* ask the core to calculate the divisor */ 1487 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1488 1489 /* 1490 * Need to update the Ring buffer length according to the selected 1491 * baud rate and restart Rx DMA path. 1492 * 1493 * Since timer function acqures sport->port.lock, need to stop before 1494 * acquring same lock because otherwise del_timer_sync() can deadlock. 1495 */ 1496 if (old && sport->lpuart_dma_rx_use) { 1497 del_timer_sync(&sport->lpuart_timer); 1498 lpuart_dma_rx_free(&sport->port); 1499 } 1500 1501 spin_lock_irqsave(&sport->port.lock, flags); 1502 1503 sport->port.read_status_mask = 0; 1504 if (termios->c_iflag & INPCK) 1505 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE); 1506 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1507 sport->port.read_status_mask |= UARTSR1_FE; 1508 1509 /* characters to ignore */ 1510 sport->port.ignore_status_mask = 0; 1511 if (termios->c_iflag & IGNPAR) 1512 sport->port.ignore_status_mask |= UARTSR1_PE; 1513 if (termios->c_iflag & IGNBRK) { 1514 sport->port.ignore_status_mask |= UARTSR1_FE; 1515 /* 1516 * if we're ignoring parity and break indicators, 1517 * ignore overruns too (for real raw support). 1518 */ 1519 if (termios->c_iflag & IGNPAR) 1520 sport->port.ignore_status_mask |= UARTSR1_OR; 1521 } 1522 1523 /* update the per-port timeout */ 1524 uart_update_timeout(port, termios->c_cflag, baud); 1525 1526 /* wait transmit engin complete */ 1527 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1528 barrier(); 1529 1530 /* disable transmit and receive */ 1531 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1532 sport->port.membase + UARTCR2); 1533 1534 sbr = sport->port.uartclk / (16 * baud); 1535 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1536 bdh &= ~UARTBDH_SBR_MASK; 1537 bdh |= (sbr >> 8) & 0x1F; 1538 cr4 &= ~UARTCR4_BRFA_MASK; 1539 brfa &= UARTCR4_BRFA_MASK; 1540 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1541 writeb(bdh, sport->port.membase + UARTBDH); 1542 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1543 writeb(cr3, sport->port.membase + UARTCR3); 1544 writeb(cr1, sport->port.membase + UARTCR1); 1545 writeb(modem, sport->port.membase + UARTMODEM); 1546 1547 /* restore control register */ 1548 writeb(old_cr2, sport->port.membase + UARTCR2); 1549 1550 if (old && sport->lpuart_dma_rx_use) { 1551 if (!lpuart_start_rx_dma(sport)) 1552 rx_dma_timer_init(sport); 1553 else 1554 sport->lpuart_dma_rx_use = false; 1555 } 1556 1557 spin_unlock_irqrestore(&sport->port.lock, flags); 1558 } 1559 1560 static void 1561 lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate) 1562 { 1563 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; 1564 u32 clk = sport->port.uartclk; 1565 1566 /* 1567 * The idea is to use the best OSR (over-sampling rate) possible. 1568 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 1569 * Loop to find the best OSR value possible, one that generates minimum 1570 * baud_diff iterate through the rest of the supported values of OSR. 1571 * 1572 * Calculation Formula: 1573 * Baud Rate = baud clock / ((OSR+1) × SBR) 1574 */ 1575 baud_diff = baudrate; 1576 osr = 0; 1577 sbr = 0; 1578 1579 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 1580 /* calculate the temporary sbr value */ 1581 tmp_sbr = (clk / (baudrate * tmp_osr)); 1582 if (tmp_sbr == 0) 1583 tmp_sbr = 1; 1584 1585 /* 1586 * calculate the baud rate difference based on the temporary 1587 * osr and sbr values 1588 */ 1589 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 1590 1591 /* select best values between sbr and sbr+1 */ 1592 tmp = clk / (tmp_osr * (tmp_sbr + 1)); 1593 if (tmp_diff > (baudrate - tmp)) { 1594 tmp_diff = baudrate - tmp; 1595 tmp_sbr++; 1596 } 1597 1598 if (tmp_diff <= baud_diff) { 1599 baud_diff = tmp_diff; 1600 osr = tmp_osr; 1601 sbr = tmp_sbr; 1602 1603 if (!baud_diff) 1604 break; 1605 } 1606 } 1607 1608 /* handle buadrate outside acceptable rate */ 1609 if (baud_diff > ((baudrate / 100) * 3)) 1610 dev_warn(sport->port.dev, 1611 "unacceptable baud rate difference of more than 3%%\n"); 1612 1613 tmp = lpuart32_read(&sport->port, UARTBAUD); 1614 1615 if ((osr > 3) && (osr < 8)) 1616 tmp |= UARTBAUD_BOTHEDGE; 1617 1618 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 1619 tmp |= (((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT); 1620 1621 tmp &= ~UARTBAUD_SBR_MASK; 1622 tmp |= sbr & UARTBAUD_SBR_MASK; 1623 1624 tmp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); 1625 1626 lpuart32_write(&sport->port, tmp, UARTBAUD); 1627 } 1628 1629 static void 1630 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 1631 struct ktermios *old) 1632 { 1633 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1634 unsigned long flags; 1635 unsigned long ctrl, old_ctrl, modem; 1636 unsigned int baud; 1637 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1638 1639 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); 1640 modem = lpuart32_read(&sport->port, UARTMODIR); 1641 /* 1642 * only support CS8 and CS7, and for CS7 must enable PE. 1643 * supported mode: 1644 * - (7,e/o,1) 1645 * - (8,n,1) 1646 * - (8,m/s,1) 1647 * - (8,e/o,1) 1648 */ 1649 while ((termios->c_cflag & CSIZE) != CS8 && 1650 (termios->c_cflag & CSIZE) != CS7) { 1651 termios->c_cflag &= ~CSIZE; 1652 termios->c_cflag |= old_csize; 1653 old_csize = CS8; 1654 } 1655 1656 if ((termios->c_cflag & CSIZE) == CS8 || 1657 (termios->c_cflag & CSIZE) == CS7) 1658 ctrl = old_ctrl & ~UARTCTRL_M; 1659 1660 if (termios->c_cflag & CMSPAR) { 1661 if ((termios->c_cflag & CSIZE) != CS8) { 1662 termios->c_cflag &= ~CSIZE; 1663 termios->c_cflag |= CS8; 1664 } 1665 ctrl |= UARTCTRL_M; 1666 } 1667 1668 if (termios->c_cflag & CRTSCTS) { 1669 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1670 } else { 1671 termios->c_cflag &= ~CRTSCTS; 1672 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1673 } 1674 1675 if (termios->c_cflag & CSTOPB) 1676 termios->c_cflag &= ~CSTOPB; 1677 1678 /* parity must be enabled when CS7 to match 8-bits format */ 1679 if ((termios->c_cflag & CSIZE) == CS7) 1680 termios->c_cflag |= PARENB; 1681 1682 if ((termios->c_cflag & PARENB)) { 1683 if (termios->c_cflag & CMSPAR) { 1684 ctrl &= ~UARTCTRL_PE; 1685 ctrl |= UARTCTRL_M; 1686 } else { 1687 ctrl |= UARTCTRL_PE; 1688 if ((termios->c_cflag & CSIZE) == CS8) 1689 ctrl |= UARTCTRL_M; 1690 if (termios->c_cflag & PARODD) 1691 ctrl |= UARTCTRL_PT; 1692 else 1693 ctrl &= ~UARTCTRL_PT; 1694 } 1695 } else { 1696 ctrl &= ~UARTCTRL_PE; 1697 } 1698 1699 /* ask the core to calculate the divisor */ 1700 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1701 1702 spin_lock_irqsave(&sport->port.lock, flags); 1703 1704 sport->port.read_status_mask = 0; 1705 if (termios->c_iflag & INPCK) 1706 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE); 1707 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1708 sport->port.read_status_mask |= UARTSTAT_FE; 1709 1710 /* characters to ignore */ 1711 sport->port.ignore_status_mask = 0; 1712 if (termios->c_iflag & IGNPAR) 1713 sport->port.ignore_status_mask |= UARTSTAT_PE; 1714 if (termios->c_iflag & IGNBRK) { 1715 sport->port.ignore_status_mask |= UARTSTAT_FE; 1716 /* 1717 * if we're ignoring parity and break indicators, 1718 * ignore overruns too (for real raw support). 1719 */ 1720 if (termios->c_iflag & IGNPAR) 1721 sport->port.ignore_status_mask |= UARTSTAT_OR; 1722 } 1723 1724 /* update the per-port timeout */ 1725 uart_update_timeout(port, termios->c_cflag, baud); 1726 1727 /* wait transmit engin complete */ 1728 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC)) 1729 barrier(); 1730 1731 /* disable transmit and receive */ 1732 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 1733 UARTCTRL); 1734 1735 lpuart32_serial_setbrg(sport, baud); 1736 lpuart32_write(&sport->port, modem, UARTMODIR); 1737 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1738 /* restore control register */ 1739 1740 spin_unlock_irqrestore(&sport->port.lock, flags); 1741 } 1742 1743 static const char *lpuart_type(struct uart_port *port) 1744 { 1745 return "FSL_LPUART"; 1746 } 1747 1748 static void lpuart_release_port(struct uart_port *port) 1749 { 1750 /* nothing to do */ 1751 } 1752 1753 static int lpuart_request_port(struct uart_port *port) 1754 { 1755 return 0; 1756 } 1757 1758 /* configure/autoconfigure the port */ 1759 static void lpuart_config_port(struct uart_port *port, int flags) 1760 { 1761 if (flags & UART_CONFIG_TYPE) 1762 port->type = PORT_LPUART; 1763 } 1764 1765 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 1766 { 1767 int ret = 0; 1768 1769 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 1770 ret = -EINVAL; 1771 if (port->irq != ser->irq) 1772 ret = -EINVAL; 1773 if (ser->io_type != UPIO_MEM) 1774 ret = -EINVAL; 1775 if (port->uartclk / 16 != ser->baud_base) 1776 ret = -EINVAL; 1777 if (port->iobase != ser->port) 1778 ret = -EINVAL; 1779 if (ser->hub6 != 0) 1780 ret = -EINVAL; 1781 return ret; 1782 } 1783 1784 static const struct uart_ops lpuart_pops = { 1785 .tx_empty = lpuart_tx_empty, 1786 .set_mctrl = lpuart_set_mctrl, 1787 .get_mctrl = lpuart_get_mctrl, 1788 .stop_tx = lpuart_stop_tx, 1789 .start_tx = lpuart_start_tx, 1790 .stop_rx = lpuart_stop_rx, 1791 .break_ctl = lpuart_break_ctl, 1792 .startup = lpuart_startup, 1793 .shutdown = lpuart_shutdown, 1794 .set_termios = lpuart_set_termios, 1795 .type = lpuart_type, 1796 .request_port = lpuart_request_port, 1797 .release_port = lpuart_release_port, 1798 .config_port = lpuart_config_port, 1799 .verify_port = lpuart_verify_port, 1800 .flush_buffer = lpuart_flush_buffer, 1801 #if defined(CONFIG_CONSOLE_POLL) 1802 .poll_init = lpuart_poll_init, 1803 .poll_get_char = lpuart_poll_get_char, 1804 .poll_put_char = lpuart_poll_put_char, 1805 #endif 1806 }; 1807 1808 static const struct uart_ops lpuart32_pops = { 1809 .tx_empty = lpuart32_tx_empty, 1810 .set_mctrl = lpuart32_set_mctrl, 1811 .get_mctrl = lpuart32_get_mctrl, 1812 .stop_tx = lpuart32_stop_tx, 1813 .start_tx = lpuart32_start_tx, 1814 .stop_rx = lpuart32_stop_rx, 1815 .break_ctl = lpuart32_break_ctl, 1816 .startup = lpuart32_startup, 1817 .shutdown = lpuart32_shutdown, 1818 .set_termios = lpuart32_set_termios, 1819 .type = lpuart_type, 1820 .request_port = lpuart_request_port, 1821 .release_port = lpuart_release_port, 1822 .config_port = lpuart_config_port, 1823 .verify_port = lpuart_verify_port, 1824 .flush_buffer = lpuart_flush_buffer, 1825 #if defined(CONFIG_CONSOLE_POLL) 1826 .poll_init = lpuart32_poll_init, 1827 .poll_get_char = lpuart32_poll_get_char, 1828 .poll_put_char = lpuart32_poll_put_char, 1829 #endif 1830 }; 1831 1832 static struct lpuart_port *lpuart_ports[UART_NR]; 1833 1834 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 1835 static void lpuart_console_putchar(struct uart_port *port, int ch) 1836 { 1837 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) 1838 barrier(); 1839 1840 writeb(ch, port->membase + UARTDR); 1841 } 1842 1843 static void lpuart32_console_putchar(struct uart_port *port, int ch) 1844 { 1845 while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)) 1846 barrier(); 1847 1848 lpuart32_write(port, ch, UARTDATA); 1849 } 1850 1851 static void 1852 lpuart_console_write(struct console *co, const char *s, unsigned int count) 1853 { 1854 struct lpuart_port *sport = lpuart_ports[co->index]; 1855 unsigned char old_cr2, cr2; 1856 unsigned long flags; 1857 int locked = 1; 1858 1859 if (sport->port.sysrq || oops_in_progress) 1860 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1861 else 1862 spin_lock_irqsave(&sport->port.lock, flags); 1863 1864 /* first save CR2 and then disable interrupts */ 1865 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 1866 cr2 |= (UARTCR2_TE | UARTCR2_RE); 1867 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1868 writeb(cr2, sport->port.membase + UARTCR2); 1869 1870 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 1871 1872 /* wait for transmitter finish complete and restore CR2 */ 1873 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1874 barrier(); 1875 1876 writeb(old_cr2, sport->port.membase + UARTCR2); 1877 1878 if (locked) 1879 spin_unlock_irqrestore(&sport->port.lock, flags); 1880 } 1881 1882 static void 1883 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 1884 { 1885 struct lpuart_port *sport = lpuart_ports[co->index]; 1886 unsigned long old_cr, cr; 1887 unsigned long flags; 1888 int locked = 1; 1889 1890 if (sport->port.sysrq || oops_in_progress) 1891 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1892 else 1893 spin_lock_irqsave(&sport->port.lock, flags); 1894 1895 /* first save CR2 and then disable interrupts */ 1896 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 1897 cr |= (UARTCTRL_TE | UARTCTRL_RE); 1898 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1899 lpuart32_write(&sport->port, cr, UARTCTRL); 1900 1901 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 1902 1903 /* wait for transmitter finish complete and restore CR2 */ 1904 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC)) 1905 barrier(); 1906 1907 lpuart32_write(&sport->port, old_cr, UARTCTRL); 1908 1909 if (locked) 1910 spin_unlock_irqrestore(&sport->port.lock, flags); 1911 } 1912 1913 /* 1914 * if the port was already initialised (eg, by a boot loader), 1915 * try to determine the current setup. 1916 */ 1917 static void __init 1918 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 1919 int *parity, int *bits) 1920 { 1921 unsigned char cr, bdh, bdl, brfa; 1922 unsigned int sbr, uartclk, baud_raw; 1923 1924 cr = readb(sport->port.membase + UARTCR2); 1925 cr &= UARTCR2_TE | UARTCR2_RE; 1926 if (!cr) 1927 return; 1928 1929 /* ok, the port was enabled */ 1930 1931 cr = readb(sport->port.membase + UARTCR1); 1932 1933 *parity = 'n'; 1934 if (cr & UARTCR1_PE) { 1935 if (cr & UARTCR1_PT) 1936 *parity = 'o'; 1937 else 1938 *parity = 'e'; 1939 } 1940 1941 if (cr & UARTCR1_M) 1942 *bits = 9; 1943 else 1944 *bits = 8; 1945 1946 bdh = readb(sport->port.membase + UARTBDH); 1947 bdh &= UARTBDH_SBR_MASK; 1948 bdl = readb(sport->port.membase + UARTBDL); 1949 sbr = bdh; 1950 sbr <<= 8; 1951 sbr |= bdl; 1952 brfa = readb(sport->port.membase + UARTCR4); 1953 brfa &= UARTCR4_BRFA_MASK; 1954 1955 uartclk = clk_get_rate(sport->clk); 1956 /* 1957 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 1958 */ 1959 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 1960 1961 if (*baud != baud_raw) 1962 printk(KERN_INFO "Serial: Console lpuart rounded baud rate" 1963 "from %d to %d\n", baud_raw, *baud); 1964 } 1965 1966 static void __init 1967 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 1968 int *parity, int *bits) 1969 { 1970 unsigned long cr, bd; 1971 unsigned int sbr, uartclk, baud_raw; 1972 1973 cr = lpuart32_read(&sport->port, UARTCTRL); 1974 cr &= UARTCTRL_TE | UARTCTRL_RE; 1975 if (!cr) 1976 return; 1977 1978 /* ok, the port was enabled */ 1979 1980 cr = lpuart32_read(&sport->port, UARTCTRL); 1981 1982 *parity = 'n'; 1983 if (cr & UARTCTRL_PE) { 1984 if (cr & UARTCTRL_PT) 1985 *parity = 'o'; 1986 else 1987 *parity = 'e'; 1988 } 1989 1990 if (cr & UARTCTRL_M) 1991 *bits = 9; 1992 else 1993 *bits = 8; 1994 1995 bd = lpuart32_read(&sport->port, UARTBAUD); 1996 bd &= UARTBAUD_SBR_MASK; 1997 sbr = bd; 1998 uartclk = clk_get_rate(sport->clk); 1999 /* 2000 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2001 */ 2002 baud_raw = uartclk / (16 * sbr); 2003 2004 if (*baud != baud_raw) 2005 printk(KERN_INFO "Serial: Console lpuart rounded baud rate" 2006 "from %d to %d\n", baud_raw, *baud); 2007 } 2008 2009 static int __init lpuart_console_setup(struct console *co, char *options) 2010 { 2011 struct lpuart_port *sport; 2012 int baud = 115200; 2013 int bits = 8; 2014 int parity = 'n'; 2015 int flow = 'n'; 2016 2017 /* 2018 * check whether an invalid uart number has been specified, and 2019 * if so, search for the first available port that does have 2020 * console support. 2021 */ 2022 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2023 co->index = 0; 2024 2025 sport = lpuart_ports[co->index]; 2026 if (sport == NULL) 2027 return -ENODEV; 2028 2029 if (options) 2030 uart_parse_options(options, &baud, &parity, &bits, &flow); 2031 else 2032 if (lpuart_is_32(sport)) 2033 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2034 else 2035 lpuart_console_get_options(sport, &baud, &parity, &bits); 2036 2037 if (lpuart_is_32(sport)) 2038 lpuart32_setup_watermark(sport); 2039 else 2040 lpuart_setup_watermark(sport); 2041 2042 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2043 } 2044 2045 static struct uart_driver lpuart_reg; 2046 static struct console lpuart_console = { 2047 .name = DEV_NAME, 2048 .write = lpuart_console_write, 2049 .device = uart_console_device, 2050 .setup = lpuart_console_setup, 2051 .flags = CON_PRINTBUFFER, 2052 .index = -1, 2053 .data = &lpuart_reg, 2054 }; 2055 2056 static struct console lpuart32_console = { 2057 .name = DEV_NAME, 2058 .write = lpuart32_console_write, 2059 .device = uart_console_device, 2060 .setup = lpuart_console_setup, 2061 .flags = CON_PRINTBUFFER, 2062 .index = -1, 2063 .data = &lpuart_reg, 2064 }; 2065 2066 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2067 { 2068 struct earlycon_device *dev = con->data; 2069 2070 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2071 } 2072 2073 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2074 { 2075 struct earlycon_device *dev = con->data; 2076 2077 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2078 } 2079 2080 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2081 const char *opt) 2082 { 2083 if (!device->port.membase) 2084 return -ENODEV; 2085 2086 device->con->write = lpuart_early_write; 2087 return 0; 2088 } 2089 2090 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2091 const char *opt) 2092 { 2093 if (!device->port.membase) 2094 return -ENODEV; 2095 2096 device->port.iotype = UPIO_MEM32BE; 2097 device->con->write = lpuart32_early_write; 2098 return 0; 2099 } 2100 2101 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2102 const char *opt) 2103 { 2104 if (!device->port.membase) 2105 return -ENODEV; 2106 2107 device->port.iotype = UPIO_MEM32; 2108 device->port.membase += IMX_REG_OFF; 2109 device->con->write = lpuart32_early_write; 2110 2111 return 0; 2112 } 2113 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2114 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2115 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2116 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2117 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2118 2119 #define LPUART_CONSOLE (&lpuart_console) 2120 #define LPUART32_CONSOLE (&lpuart32_console) 2121 #else 2122 #define LPUART_CONSOLE NULL 2123 #define LPUART32_CONSOLE NULL 2124 #endif 2125 2126 static struct uart_driver lpuart_reg = { 2127 .owner = THIS_MODULE, 2128 .driver_name = DRIVER_NAME, 2129 .dev_name = DEV_NAME, 2130 .nr = ARRAY_SIZE(lpuart_ports), 2131 .cons = LPUART_CONSOLE, 2132 }; 2133 2134 static int lpuart_probe(struct platform_device *pdev) 2135 { 2136 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids, 2137 &pdev->dev); 2138 const struct lpuart_soc_data *sdata = of_id->data; 2139 struct device_node *np = pdev->dev.of_node; 2140 struct lpuart_port *sport; 2141 struct resource *res; 2142 int ret; 2143 2144 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2145 if (!sport) 2146 return -ENOMEM; 2147 2148 pdev->dev.coherent_dma_mask = 0; 2149 2150 ret = of_alias_get_id(np, "serial"); 2151 if (ret < 0) { 2152 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL); 2153 if (ret < 0) { 2154 dev_err(&pdev->dev, "port line is full, add device failed\n"); 2155 return ret; 2156 } 2157 } 2158 if (ret >= ARRAY_SIZE(lpuart_ports)) { 2159 dev_err(&pdev->dev, "serial%d out of range\n", ret); 2160 return -EINVAL; 2161 } 2162 sport->port.line = ret; 2163 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2164 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 2165 if (IS_ERR(sport->port.membase)) 2166 return PTR_ERR(sport->port.membase); 2167 2168 sport->port.membase += sdata->reg_off; 2169 sport->port.mapbase = res->start; 2170 sport->port.dev = &pdev->dev; 2171 sport->port.type = PORT_LPUART; 2172 ret = platform_get_irq(pdev, 0); 2173 if (ret < 0) { 2174 dev_err(&pdev->dev, "cannot obtain irq\n"); 2175 return ret; 2176 } 2177 sport->port.irq = ret; 2178 sport->port.iotype = sdata->iotype; 2179 if (lpuart_is_32(sport)) 2180 sport->port.ops = &lpuart32_pops; 2181 else 2182 sport->port.ops = &lpuart_pops; 2183 sport->port.flags = UPF_BOOT_AUTOCONF; 2184 2185 sport->port.rs485_config = lpuart_config_rs485; 2186 2187 sport->clk = devm_clk_get(&pdev->dev, "ipg"); 2188 if (IS_ERR(sport->clk)) { 2189 ret = PTR_ERR(sport->clk); 2190 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret); 2191 return ret; 2192 } 2193 2194 ret = clk_prepare_enable(sport->clk); 2195 if (ret) { 2196 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret); 2197 return ret; 2198 } 2199 2200 sport->port.uartclk = clk_get_rate(sport->clk); 2201 2202 lpuart_ports[sport->port.line] = sport; 2203 2204 platform_set_drvdata(pdev, &sport->port); 2205 2206 if (lpuart_is_32(sport)) { 2207 lpuart_reg.cons = LPUART32_CONSOLE; 2208 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0, 2209 DRIVER_NAME, sport); 2210 } else { 2211 lpuart_reg.cons = LPUART_CONSOLE; 2212 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0, 2213 DRIVER_NAME, sport); 2214 } 2215 2216 if (ret) 2217 goto failed_irq_request; 2218 2219 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2220 if (ret) 2221 goto failed_attach_port; 2222 2223 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2224 2225 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX) 2226 dev_err(&pdev->dev, "driver doesn't support RX during TX\n"); 2227 2228 if (sport->port.rs485.delay_rts_before_send || 2229 sport->port.rs485.delay_rts_after_send) 2230 dev_err(&pdev->dev, "driver doesn't support RTS delays\n"); 2231 2232 lpuart_config_rs485(&sport->port, &sport->port.rs485); 2233 2234 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx"); 2235 if (!sport->dma_tx_chan) 2236 dev_info(sport->port.dev, "DMA tx channel request failed, " 2237 "operating without tx DMA\n"); 2238 2239 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx"); 2240 if (!sport->dma_rx_chan) 2241 dev_info(sport->port.dev, "DMA rx channel request failed, " 2242 "operating without rx DMA\n"); 2243 2244 return 0; 2245 2246 failed_attach_port: 2247 failed_irq_request: 2248 clk_disable_unprepare(sport->clk); 2249 return ret; 2250 } 2251 2252 static int lpuart_remove(struct platform_device *pdev) 2253 { 2254 struct lpuart_port *sport = platform_get_drvdata(pdev); 2255 2256 uart_remove_one_port(&lpuart_reg, &sport->port); 2257 2258 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); 2259 2260 clk_disable_unprepare(sport->clk); 2261 2262 if (sport->dma_tx_chan) 2263 dma_release_channel(sport->dma_tx_chan); 2264 2265 if (sport->dma_rx_chan) 2266 dma_release_channel(sport->dma_rx_chan); 2267 2268 return 0; 2269 } 2270 2271 #ifdef CONFIG_PM_SLEEP 2272 static int lpuart_suspend(struct device *dev) 2273 { 2274 struct lpuart_port *sport = dev_get_drvdata(dev); 2275 unsigned long temp; 2276 bool irq_wake; 2277 2278 if (lpuart_is_32(sport)) { 2279 /* disable Rx/Tx and interrupts */ 2280 temp = lpuart32_read(&sport->port, UARTCTRL); 2281 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2282 lpuart32_write(&sport->port, temp, UARTCTRL); 2283 } else { 2284 /* disable Rx/Tx and interrupts */ 2285 temp = readb(sport->port.membase + UARTCR2); 2286 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2287 writeb(temp, sport->port.membase + UARTCR2); 2288 } 2289 2290 uart_suspend_port(&lpuart_reg, &sport->port); 2291 2292 /* uart_suspend_port() might set wakeup flag */ 2293 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2294 2295 if (sport->lpuart_dma_rx_use) { 2296 /* 2297 * EDMA driver during suspend will forcefully release any 2298 * non-idle DMA channels. If port wakeup is enabled or if port 2299 * is console port or 'no_console_suspend' is set the Rx DMA 2300 * cannot resume as as expected, hence gracefully release the 2301 * Rx DMA path before suspend and start Rx DMA path on resume. 2302 */ 2303 if (irq_wake) { 2304 del_timer_sync(&sport->lpuart_timer); 2305 lpuart_dma_rx_free(&sport->port); 2306 } 2307 2308 /* Disable Rx DMA to use UART port as wakeup source */ 2309 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS, 2310 sport->port.membase + UARTCR5); 2311 } 2312 2313 if (sport->lpuart_dma_tx_use) { 2314 sport->dma_tx_in_progress = false; 2315 dmaengine_terminate_all(sport->dma_tx_chan); 2316 } 2317 2318 if (sport->port.suspended && !irq_wake) 2319 clk_disable_unprepare(sport->clk); 2320 2321 return 0; 2322 } 2323 2324 static int lpuart_resume(struct device *dev) 2325 { 2326 struct lpuart_port *sport = dev_get_drvdata(dev); 2327 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2328 unsigned long temp; 2329 2330 if (sport->port.suspended && !irq_wake) 2331 clk_prepare_enable(sport->clk); 2332 2333 if (lpuart_is_32(sport)) { 2334 lpuart32_setup_watermark(sport); 2335 temp = lpuart32_read(&sport->port, UARTCTRL); 2336 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | 2337 UARTCTRL_TE | UARTCTRL_ILIE); 2338 lpuart32_write(&sport->port, temp, UARTCTRL); 2339 } else { 2340 lpuart_setup_watermark(sport); 2341 temp = readb(sport->port.membase + UARTCR2); 2342 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 2343 writeb(temp, sport->port.membase + UARTCR2); 2344 } 2345 2346 if (sport->lpuart_dma_rx_use) { 2347 if (irq_wake) { 2348 if (!lpuart_start_rx_dma(sport)) 2349 rx_dma_timer_init(sport); 2350 else 2351 sport->lpuart_dma_rx_use = false; 2352 } 2353 } 2354 2355 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) { 2356 init_waitqueue_head(&sport->dma_wait); 2357 sport->lpuart_dma_tx_use = true; 2358 writeb(readb(sport->port.membase + UARTCR5) | 2359 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 2360 } else { 2361 sport->lpuart_dma_tx_use = false; 2362 } 2363 2364 uart_resume_port(&lpuart_reg, &sport->port); 2365 2366 return 0; 2367 } 2368 #endif 2369 2370 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2371 2372 static struct platform_driver lpuart_driver = { 2373 .probe = lpuart_probe, 2374 .remove = lpuart_remove, 2375 .driver = { 2376 .name = "fsl-lpuart", 2377 .of_match_table = lpuart_dt_ids, 2378 .pm = &lpuart_pm_ops, 2379 }, 2380 }; 2381 2382 static int __init lpuart_serial_init(void) 2383 { 2384 int ret = uart_register_driver(&lpuart_reg); 2385 2386 if (ret) 2387 return ret; 2388 2389 ret = platform_driver_register(&lpuart_driver); 2390 if (ret) 2391 uart_unregister_driver(&lpuart_reg); 2392 2393 return ret; 2394 } 2395 2396 static void __exit lpuart_serial_exit(void) 2397 { 2398 ida_destroy(&fsl_lpuart_ida); 2399 platform_driver_unregister(&lpuart_driver); 2400 uart_unregister_driver(&lpuart_reg); 2401 } 2402 2403 module_init(lpuart_serial_init); 2404 module_exit(lpuart_serial_exit); 2405 2406 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2407 MODULE_LICENSE("GPL v2"); 2408