1 /* 2 * Freescale lpuart serial port driver 3 * 4 * Copyright 2012-2014 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 13 #define SUPPORT_SYSRQ 14 #endif 15 16 #include <linux/clk.h> 17 #include <linux/console.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/dmaengine.h> 20 #include <linux/dmapool.h> 21 #include <linux/io.h> 22 #include <linux/irq.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/of_dma.h> 27 #include <linux/serial_core.h> 28 #include <linux/slab.h> 29 #include <linux/tty_flip.h> 30 31 /* All registers are 8-bit width */ 32 #define UARTBDH 0x00 33 #define UARTBDL 0x01 34 #define UARTCR1 0x02 35 #define UARTCR2 0x03 36 #define UARTSR1 0x04 37 #define UARTCR3 0x06 38 #define UARTDR 0x07 39 #define UARTCR4 0x0a 40 #define UARTCR5 0x0b 41 #define UARTMODEM 0x0d 42 #define UARTPFIFO 0x10 43 #define UARTCFIFO 0x11 44 #define UARTSFIFO 0x12 45 #define UARTTWFIFO 0x13 46 #define UARTTCFIFO 0x14 47 #define UARTRWFIFO 0x15 48 49 #define UARTBDH_LBKDIE 0x80 50 #define UARTBDH_RXEDGIE 0x40 51 #define UARTBDH_SBR_MASK 0x1f 52 53 #define UARTCR1_LOOPS 0x80 54 #define UARTCR1_RSRC 0x20 55 #define UARTCR1_M 0x10 56 #define UARTCR1_WAKE 0x08 57 #define UARTCR1_ILT 0x04 58 #define UARTCR1_PE 0x02 59 #define UARTCR1_PT 0x01 60 61 #define UARTCR2_TIE 0x80 62 #define UARTCR2_TCIE 0x40 63 #define UARTCR2_RIE 0x20 64 #define UARTCR2_ILIE 0x10 65 #define UARTCR2_TE 0x08 66 #define UARTCR2_RE 0x04 67 #define UARTCR2_RWU 0x02 68 #define UARTCR2_SBK 0x01 69 70 #define UARTSR1_TDRE 0x80 71 #define UARTSR1_TC 0x40 72 #define UARTSR1_RDRF 0x20 73 #define UARTSR1_IDLE 0x10 74 #define UARTSR1_OR 0x08 75 #define UARTSR1_NF 0x04 76 #define UARTSR1_FE 0x02 77 #define UARTSR1_PE 0x01 78 79 #define UARTCR3_R8 0x80 80 #define UARTCR3_T8 0x40 81 #define UARTCR3_TXDIR 0x20 82 #define UARTCR3_TXINV 0x10 83 #define UARTCR3_ORIE 0x08 84 #define UARTCR3_NEIE 0x04 85 #define UARTCR3_FEIE 0x02 86 #define UARTCR3_PEIE 0x01 87 88 #define UARTCR4_MAEN1 0x80 89 #define UARTCR4_MAEN2 0x40 90 #define UARTCR4_M10 0x20 91 #define UARTCR4_BRFA_MASK 0x1f 92 #define UARTCR4_BRFA_OFF 0 93 94 #define UARTCR5_TDMAS 0x80 95 #define UARTCR5_RDMAS 0x20 96 97 #define UARTMODEM_RXRTSE 0x08 98 #define UARTMODEM_TXRTSPOL 0x04 99 #define UARTMODEM_TXRTSE 0x02 100 #define UARTMODEM_TXCTSE 0x01 101 102 #define UARTPFIFO_TXFE 0x80 103 #define UARTPFIFO_FIFOSIZE_MASK 0x7 104 #define UARTPFIFO_TXSIZE_OFF 4 105 #define UARTPFIFO_RXFE 0x08 106 #define UARTPFIFO_RXSIZE_OFF 0 107 108 #define UARTCFIFO_TXFLUSH 0x80 109 #define UARTCFIFO_RXFLUSH 0x40 110 #define UARTCFIFO_RXOFE 0x04 111 #define UARTCFIFO_TXOFE 0x02 112 #define UARTCFIFO_RXUFE 0x01 113 114 #define UARTSFIFO_TXEMPT 0x80 115 #define UARTSFIFO_RXEMPT 0x40 116 #define UARTSFIFO_RXOF 0x04 117 #define UARTSFIFO_TXOF 0x02 118 #define UARTSFIFO_RXUF 0x01 119 120 /* 32-bit register defination */ 121 #define UARTBAUD 0x00 122 #define UARTSTAT 0x04 123 #define UARTCTRL 0x08 124 #define UARTDATA 0x0C 125 #define UARTMATCH 0x10 126 #define UARTMODIR 0x14 127 #define UARTFIFO 0x18 128 #define UARTWATER 0x1c 129 130 #define UARTBAUD_MAEN1 0x80000000 131 #define UARTBAUD_MAEN2 0x40000000 132 #define UARTBAUD_M10 0x20000000 133 #define UARTBAUD_TDMAE 0x00800000 134 #define UARTBAUD_RDMAE 0x00200000 135 #define UARTBAUD_MATCFG 0x00400000 136 #define UARTBAUD_BOTHEDGE 0x00020000 137 #define UARTBAUD_RESYNCDIS 0x00010000 138 #define UARTBAUD_LBKDIE 0x00008000 139 #define UARTBAUD_RXEDGIE 0x00004000 140 #define UARTBAUD_SBNS 0x00002000 141 #define UARTBAUD_SBR 0x00000000 142 #define UARTBAUD_SBR_MASK 0x1fff 143 144 #define UARTSTAT_LBKDIF 0x80000000 145 #define UARTSTAT_RXEDGIF 0x40000000 146 #define UARTSTAT_MSBF 0x20000000 147 #define UARTSTAT_RXINV 0x10000000 148 #define UARTSTAT_RWUID 0x08000000 149 #define UARTSTAT_BRK13 0x04000000 150 #define UARTSTAT_LBKDE 0x02000000 151 #define UARTSTAT_RAF 0x01000000 152 #define UARTSTAT_TDRE 0x00800000 153 #define UARTSTAT_TC 0x00400000 154 #define UARTSTAT_RDRF 0x00200000 155 #define UARTSTAT_IDLE 0x00100000 156 #define UARTSTAT_OR 0x00080000 157 #define UARTSTAT_NF 0x00040000 158 #define UARTSTAT_FE 0x00020000 159 #define UARTSTAT_PE 0x00010000 160 #define UARTSTAT_MA1F 0x00008000 161 #define UARTSTAT_M21F 0x00004000 162 163 #define UARTCTRL_R8T9 0x80000000 164 #define UARTCTRL_R9T8 0x40000000 165 #define UARTCTRL_TXDIR 0x20000000 166 #define UARTCTRL_TXINV 0x10000000 167 #define UARTCTRL_ORIE 0x08000000 168 #define UARTCTRL_NEIE 0x04000000 169 #define UARTCTRL_FEIE 0x02000000 170 #define UARTCTRL_PEIE 0x01000000 171 #define UARTCTRL_TIE 0x00800000 172 #define UARTCTRL_TCIE 0x00400000 173 #define UARTCTRL_RIE 0x00200000 174 #define UARTCTRL_ILIE 0x00100000 175 #define UARTCTRL_TE 0x00080000 176 #define UARTCTRL_RE 0x00040000 177 #define UARTCTRL_RWU 0x00020000 178 #define UARTCTRL_SBK 0x00010000 179 #define UARTCTRL_MA1IE 0x00008000 180 #define UARTCTRL_MA2IE 0x00004000 181 #define UARTCTRL_IDLECFG 0x00000100 182 #define UARTCTRL_LOOPS 0x00000080 183 #define UARTCTRL_DOZEEN 0x00000040 184 #define UARTCTRL_RSRC 0x00000020 185 #define UARTCTRL_M 0x00000010 186 #define UARTCTRL_WAKE 0x00000008 187 #define UARTCTRL_ILT 0x00000004 188 #define UARTCTRL_PE 0x00000002 189 #define UARTCTRL_PT 0x00000001 190 191 #define UARTDATA_NOISY 0x00008000 192 #define UARTDATA_PARITYE 0x00004000 193 #define UARTDATA_FRETSC 0x00002000 194 #define UARTDATA_RXEMPT 0x00001000 195 #define UARTDATA_IDLINE 0x00000800 196 #define UARTDATA_MASK 0x3ff 197 198 #define UARTMODIR_IREN 0x00020000 199 #define UARTMODIR_TXCTSSRC 0x00000020 200 #define UARTMODIR_TXCTSC 0x00000010 201 #define UARTMODIR_RXRTSE 0x00000008 202 #define UARTMODIR_TXRTSPOL 0x00000004 203 #define UARTMODIR_TXRTSE 0x00000002 204 #define UARTMODIR_TXCTSE 0x00000001 205 206 #define UARTFIFO_TXEMPT 0x00800000 207 #define UARTFIFO_RXEMPT 0x00400000 208 #define UARTFIFO_TXOF 0x00020000 209 #define UARTFIFO_RXUF 0x00010000 210 #define UARTFIFO_TXFLUSH 0x00008000 211 #define UARTFIFO_RXFLUSH 0x00004000 212 #define UARTFIFO_TXOFE 0x00000200 213 #define UARTFIFO_RXUFE 0x00000100 214 #define UARTFIFO_TXFE 0x00000080 215 #define UARTFIFO_FIFOSIZE_MASK 0x7 216 #define UARTFIFO_TXSIZE_OFF 4 217 #define UARTFIFO_RXFE 0x00000008 218 #define UARTFIFO_RXSIZE_OFF 0 219 220 #define UARTWATER_COUNT_MASK 0xff 221 #define UARTWATER_TXCNT_OFF 8 222 #define UARTWATER_RXCNT_OFF 24 223 #define UARTWATER_WATER_MASK 0xff 224 #define UARTWATER_TXWATER_OFF 0 225 #define UARTWATER_RXWATER_OFF 16 226 227 #define FSL_UART_RX_DMA_BUFFER_SIZE 64 228 229 #define DRIVER_NAME "fsl-lpuart" 230 #define DEV_NAME "ttyLP" 231 #define UART_NR 6 232 233 struct lpuart_port { 234 struct uart_port port; 235 struct clk *clk; 236 unsigned int txfifo_size; 237 unsigned int rxfifo_size; 238 bool lpuart32; 239 240 bool lpuart_dma_tx_use; 241 bool lpuart_dma_rx_use; 242 struct dma_chan *dma_tx_chan; 243 struct dma_chan *dma_rx_chan; 244 struct dma_async_tx_descriptor *dma_tx_desc; 245 struct dma_async_tx_descriptor *dma_rx_desc; 246 dma_addr_t dma_tx_buf_bus; 247 dma_addr_t dma_rx_buf_bus; 248 dma_cookie_t dma_tx_cookie; 249 dma_cookie_t dma_rx_cookie; 250 unsigned char *dma_tx_buf_virt; 251 unsigned char *dma_rx_buf_virt; 252 unsigned int dma_tx_bytes; 253 unsigned int dma_rx_bytes; 254 int dma_tx_in_progress; 255 int dma_rx_in_progress; 256 unsigned int dma_rx_timeout; 257 struct timer_list lpuart_timer; 258 }; 259 260 static struct of_device_id lpuart_dt_ids[] = { 261 { 262 .compatible = "fsl,vf610-lpuart", 263 }, 264 { 265 .compatible = "fsl,ls1021a-lpuart", 266 }, 267 { /* sentinel */ } 268 }; 269 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 270 271 /* Forward declare this for the dma callbacks*/ 272 static void lpuart_dma_tx_complete(void *arg); 273 static void lpuart_dma_rx_complete(void *arg); 274 275 static u32 lpuart32_read(void __iomem *addr) 276 { 277 return ioread32be(addr); 278 } 279 280 static void lpuart32_write(u32 val, void __iomem *addr) 281 { 282 iowrite32be(val, addr); 283 } 284 285 static void lpuart_stop_tx(struct uart_port *port) 286 { 287 unsigned char temp; 288 289 temp = readb(port->membase + UARTCR2); 290 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 291 writeb(temp, port->membase + UARTCR2); 292 } 293 294 static void lpuart32_stop_tx(struct uart_port *port) 295 { 296 unsigned long temp; 297 298 temp = lpuart32_read(port->membase + UARTCTRL); 299 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 300 lpuart32_write(temp, port->membase + UARTCTRL); 301 } 302 303 static void lpuart_stop_rx(struct uart_port *port) 304 { 305 unsigned char temp; 306 307 temp = readb(port->membase + UARTCR2); 308 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 309 } 310 311 static void lpuart32_stop_rx(struct uart_port *port) 312 { 313 unsigned long temp; 314 315 temp = lpuart32_read(port->membase + UARTCTRL); 316 lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL); 317 } 318 319 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport, 320 struct tty_port *tty, int count) 321 { 322 int copied; 323 324 sport->port.icount.rx += count; 325 326 if (!tty) { 327 dev_err(sport->port.dev, "No tty port\n"); 328 return; 329 } 330 331 dma_sync_single_for_cpu(sport->port.dev, sport->dma_rx_buf_bus, 332 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE); 333 copied = tty_insert_flip_string(tty, 334 ((unsigned char *)(sport->dma_rx_buf_virt)), count); 335 336 if (copied != count) { 337 WARN_ON(1); 338 dev_err(sport->port.dev, "RxData copy to tty layer failed\n"); 339 } 340 341 dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus, 342 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE); 343 } 344 345 static void lpuart_pio_tx(struct lpuart_port *sport) 346 { 347 struct circ_buf *xmit = &sport->port.state->xmit; 348 unsigned long flags; 349 350 spin_lock_irqsave(&sport->port.lock, flags); 351 352 while (!uart_circ_empty(xmit) && 353 readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) { 354 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 355 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 356 sport->port.icount.tx++; 357 } 358 359 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 360 uart_write_wakeup(&sport->port); 361 362 if (uart_circ_empty(xmit)) 363 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS, 364 sport->port.membase + UARTCR5); 365 366 spin_unlock_irqrestore(&sport->port.lock, flags); 367 } 368 369 static int lpuart_dma_tx(struct lpuart_port *sport, unsigned long count) 370 { 371 struct circ_buf *xmit = &sport->port.state->xmit; 372 dma_addr_t tx_bus_addr; 373 374 dma_sync_single_for_device(sport->port.dev, sport->dma_tx_buf_bus, 375 UART_XMIT_SIZE, DMA_TO_DEVICE); 376 sport->dma_tx_bytes = count & ~(sport->txfifo_size - 1); 377 tx_bus_addr = sport->dma_tx_buf_bus + xmit->tail; 378 sport->dma_tx_desc = dmaengine_prep_slave_single(sport->dma_tx_chan, 379 tx_bus_addr, sport->dma_tx_bytes, 380 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 381 382 if (!sport->dma_tx_desc) { 383 dev_err(sport->port.dev, "Not able to get desc for tx\n"); 384 return -EIO; 385 } 386 387 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 388 sport->dma_tx_desc->callback_param = sport; 389 sport->dma_tx_in_progress = 1; 390 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 391 dma_async_issue_pending(sport->dma_tx_chan); 392 393 return 0; 394 } 395 396 static void lpuart_prepare_tx(struct lpuart_port *sport) 397 { 398 struct circ_buf *xmit = &sport->port.state->xmit; 399 unsigned long count = CIRC_CNT_TO_END(xmit->head, 400 xmit->tail, UART_XMIT_SIZE); 401 402 if (!count) 403 return; 404 405 if (count < sport->txfifo_size) 406 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS, 407 sport->port.membase + UARTCR5); 408 else { 409 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS, 410 sport->port.membase + UARTCR5); 411 lpuart_dma_tx(sport, count); 412 } 413 } 414 415 static void lpuart_dma_tx_complete(void *arg) 416 { 417 struct lpuart_port *sport = arg; 418 struct circ_buf *xmit = &sport->port.state->xmit; 419 unsigned long flags; 420 421 async_tx_ack(sport->dma_tx_desc); 422 423 spin_lock_irqsave(&sport->port.lock, flags); 424 425 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 426 sport->dma_tx_in_progress = 0; 427 428 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 429 uart_write_wakeup(&sport->port); 430 431 lpuart_prepare_tx(sport); 432 433 spin_unlock_irqrestore(&sport->port.lock, flags); 434 } 435 436 static int lpuart_dma_rx(struct lpuart_port *sport) 437 { 438 dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus, 439 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE); 440 sport->dma_rx_desc = dmaengine_prep_slave_single(sport->dma_rx_chan, 441 sport->dma_rx_buf_bus, FSL_UART_RX_DMA_BUFFER_SIZE, 442 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 443 444 if (!sport->dma_rx_desc) { 445 dev_err(sport->port.dev, "Not able to get desc for rx\n"); 446 return -EIO; 447 } 448 449 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 450 sport->dma_rx_desc->callback_param = sport; 451 sport->dma_rx_in_progress = 1; 452 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 453 dma_async_issue_pending(sport->dma_rx_chan); 454 455 return 0; 456 } 457 458 static void lpuart_flush_buffer(struct uart_port *port) 459 { 460 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 461 if (sport->lpuart_dma_tx_use) { 462 dmaengine_terminate_all(sport->dma_tx_chan); 463 sport->dma_tx_in_progress = 0; 464 } 465 } 466 467 static void lpuart_dma_rx_complete(void *arg) 468 { 469 struct lpuart_port *sport = arg; 470 struct tty_port *port = &sport->port.state->port; 471 unsigned long flags; 472 473 async_tx_ack(sport->dma_rx_desc); 474 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 475 476 spin_lock_irqsave(&sport->port.lock, flags); 477 478 sport->dma_rx_in_progress = 0; 479 lpuart_copy_rx_to_tty(sport, port, FSL_UART_RX_DMA_BUFFER_SIZE); 480 tty_flip_buffer_push(port); 481 lpuart_dma_rx(sport); 482 483 spin_unlock_irqrestore(&sport->port.lock, flags); 484 } 485 486 static void lpuart_timer_func(unsigned long data) 487 { 488 struct lpuart_port *sport = (struct lpuart_port *)data; 489 struct tty_port *port = &sport->port.state->port; 490 struct dma_tx_state state; 491 unsigned long flags; 492 unsigned char temp; 493 int count; 494 495 del_timer(&sport->lpuart_timer); 496 dmaengine_pause(sport->dma_rx_chan); 497 dmaengine_tx_status(sport->dma_rx_chan, sport->dma_rx_cookie, &state); 498 dmaengine_terminate_all(sport->dma_rx_chan); 499 count = FSL_UART_RX_DMA_BUFFER_SIZE - state.residue; 500 async_tx_ack(sport->dma_rx_desc); 501 502 spin_lock_irqsave(&sport->port.lock, flags); 503 504 sport->dma_rx_in_progress = 0; 505 lpuart_copy_rx_to_tty(sport, port, count); 506 tty_flip_buffer_push(port); 507 temp = readb(sport->port.membase + UARTCR5); 508 writeb(temp & ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 509 510 spin_unlock_irqrestore(&sport->port.lock, flags); 511 } 512 513 static inline void lpuart_prepare_rx(struct lpuart_port *sport) 514 { 515 unsigned long flags; 516 unsigned char temp; 517 518 spin_lock_irqsave(&sport->port.lock, flags); 519 520 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 521 add_timer(&sport->lpuart_timer); 522 523 lpuart_dma_rx(sport); 524 temp = readb(sport->port.membase + UARTCR5); 525 writeb(temp | UARTCR5_RDMAS, sport->port.membase + UARTCR5); 526 527 spin_unlock_irqrestore(&sport->port.lock, flags); 528 } 529 530 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 531 { 532 struct circ_buf *xmit = &sport->port.state->xmit; 533 534 while (!uart_circ_empty(xmit) && 535 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 536 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 537 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 538 sport->port.icount.tx++; 539 } 540 541 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 542 uart_write_wakeup(&sport->port); 543 544 if (uart_circ_empty(xmit)) 545 lpuart_stop_tx(&sport->port); 546 } 547 548 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 549 { 550 struct circ_buf *xmit = &sport->port.state->xmit; 551 unsigned long txcnt; 552 553 txcnt = lpuart32_read(sport->port.membase + UARTWATER); 554 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 555 txcnt &= UARTWATER_COUNT_MASK; 556 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 557 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA); 558 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 559 sport->port.icount.tx++; 560 txcnt = lpuart32_read(sport->port.membase + UARTWATER); 561 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 562 txcnt &= UARTWATER_COUNT_MASK; 563 } 564 565 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 566 uart_write_wakeup(&sport->port); 567 568 if (uart_circ_empty(xmit)) 569 lpuart32_stop_tx(&sport->port); 570 } 571 572 static void lpuart_start_tx(struct uart_port *port) 573 { 574 struct lpuart_port *sport = container_of(port, 575 struct lpuart_port, port); 576 struct circ_buf *xmit = &sport->port.state->xmit; 577 unsigned char temp; 578 579 temp = readb(port->membase + UARTCR2); 580 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 581 582 if (sport->lpuart_dma_tx_use) { 583 if (!uart_circ_empty(xmit) && !sport->dma_tx_in_progress) 584 lpuart_prepare_tx(sport); 585 } else { 586 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 587 lpuart_transmit_buffer(sport); 588 } 589 } 590 591 static void lpuart32_start_tx(struct uart_port *port) 592 { 593 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 594 unsigned long temp; 595 596 temp = lpuart32_read(port->membase + UARTCTRL); 597 lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL); 598 599 if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE) 600 lpuart32_transmit_buffer(sport); 601 } 602 603 static irqreturn_t lpuart_txint(int irq, void *dev_id) 604 { 605 struct lpuart_port *sport = dev_id; 606 struct circ_buf *xmit = &sport->port.state->xmit; 607 unsigned long flags; 608 609 spin_lock_irqsave(&sport->port.lock, flags); 610 if (sport->port.x_char) { 611 if (sport->lpuart32) 612 lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA); 613 else 614 writeb(sport->port.x_char, sport->port.membase + UARTDR); 615 goto out; 616 } 617 618 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 619 if (sport->lpuart32) 620 lpuart32_stop_tx(&sport->port); 621 else 622 lpuart_stop_tx(&sport->port); 623 goto out; 624 } 625 626 if (sport->lpuart32) 627 lpuart32_transmit_buffer(sport); 628 else 629 lpuart_transmit_buffer(sport); 630 631 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 632 uart_write_wakeup(&sport->port); 633 634 out: 635 spin_unlock_irqrestore(&sport->port.lock, flags); 636 return IRQ_HANDLED; 637 } 638 639 static irqreturn_t lpuart_rxint(int irq, void *dev_id) 640 { 641 struct lpuart_port *sport = dev_id; 642 unsigned int flg, ignored = 0; 643 struct tty_port *port = &sport->port.state->port; 644 unsigned long flags; 645 unsigned char rx, sr; 646 647 spin_lock_irqsave(&sport->port.lock, flags); 648 649 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 650 flg = TTY_NORMAL; 651 sport->port.icount.rx++; 652 /* 653 * to clear the FE, OR, NF, FE, PE flags, 654 * read SR1 then read DR 655 */ 656 sr = readb(sport->port.membase + UARTSR1); 657 rx = readb(sport->port.membase + UARTDR); 658 659 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 660 continue; 661 662 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 663 if (sr & UARTSR1_PE) 664 sport->port.icount.parity++; 665 else if (sr & UARTSR1_FE) 666 sport->port.icount.frame++; 667 668 if (sr & UARTSR1_OR) 669 sport->port.icount.overrun++; 670 671 if (sr & sport->port.ignore_status_mask) { 672 if (++ignored > 100) 673 goto out; 674 continue; 675 } 676 677 sr &= sport->port.read_status_mask; 678 679 if (sr & UARTSR1_PE) 680 flg = TTY_PARITY; 681 else if (sr & UARTSR1_FE) 682 flg = TTY_FRAME; 683 684 if (sr & UARTSR1_OR) 685 flg = TTY_OVERRUN; 686 687 #ifdef SUPPORT_SYSRQ 688 sport->port.sysrq = 0; 689 #endif 690 } 691 692 tty_insert_flip_char(port, rx, flg); 693 } 694 695 out: 696 spin_unlock_irqrestore(&sport->port.lock, flags); 697 698 tty_flip_buffer_push(port); 699 return IRQ_HANDLED; 700 } 701 702 static irqreturn_t lpuart32_rxint(int irq, void *dev_id) 703 { 704 struct lpuart_port *sport = dev_id; 705 unsigned int flg, ignored = 0; 706 struct tty_port *port = &sport->port.state->port; 707 unsigned long flags; 708 unsigned long rx, sr; 709 710 spin_lock_irqsave(&sport->port.lock, flags); 711 712 while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) { 713 flg = TTY_NORMAL; 714 sport->port.icount.rx++; 715 /* 716 * to clear the FE, OR, NF, FE, PE flags, 717 * read STAT then read DATA reg 718 */ 719 sr = lpuart32_read(sport->port.membase + UARTSTAT); 720 rx = lpuart32_read(sport->port.membase + UARTDATA); 721 rx &= 0x3ff; 722 723 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 724 continue; 725 726 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 727 if (sr & UARTSTAT_PE) 728 sport->port.icount.parity++; 729 else if (sr & UARTSTAT_FE) 730 sport->port.icount.frame++; 731 732 if (sr & UARTSTAT_OR) 733 sport->port.icount.overrun++; 734 735 if (sr & sport->port.ignore_status_mask) { 736 if (++ignored > 100) 737 goto out; 738 continue; 739 } 740 741 sr &= sport->port.read_status_mask; 742 743 if (sr & UARTSTAT_PE) 744 flg = TTY_PARITY; 745 else if (sr & UARTSTAT_FE) 746 flg = TTY_FRAME; 747 748 if (sr & UARTSTAT_OR) 749 flg = TTY_OVERRUN; 750 751 #ifdef SUPPORT_SYSRQ 752 sport->port.sysrq = 0; 753 #endif 754 } 755 756 tty_insert_flip_char(port, rx, flg); 757 } 758 759 out: 760 spin_unlock_irqrestore(&sport->port.lock, flags); 761 762 tty_flip_buffer_push(port); 763 return IRQ_HANDLED; 764 } 765 766 static irqreturn_t lpuart_int(int irq, void *dev_id) 767 { 768 struct lpuart_port *sport = dev_id; 769 unsigned char sts, crdma; 770 771 sts = readb(sport->port.membase + UARTSR1); 772 crdma = readb(sport->port.membase + UARTCR5); 773 774 if (sts & UARTSR1_RDRF && !(crdma & UARTCR5_RDMAS)) { 775 if (sport->lpuart_dma_rx_use) 776 lpuart_prepare_rx(sport); 777 else 778 lpuart_rxint(irq, dev_id); 779 } 780 if (sts & UARTSR1_TDRE && !(crdma & UARTCR5_TDMAS)) { 781 if (sport->lpuart_dma_tx_use) 782 lpuart_pio_tx(sport); 783 else 784 lpuart_txint(irq, dev_id); 785 } 786 787 return IRQ_HANDLED; 788 } 789 790 static irqreturn_t lpuart32_int(int irq, void *dev_id) 791 { 792 struct lpuart_port *sport = dev_id; 793 unsigned long sts, rxcount; 794 795 sts = lpuart32_read(sport->port.membase + UARTSTAT); 796 rxcount = lpuart32_read(sport->port.membase + UARTWATER); 797 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 798 799 if (sts & UARTSTAT_RDRF || rxcount > 0) 800 lpuart32_rxint(irq, dev_id); 801 802 if ((sts & UARTSTAT_TDRE) && 803 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE)) 804 lpuart_txint(irq, dev_id); 805 806 lpuart32_write(sts, sport->port.membase + UARTSTAT); 807 return IRQ_HANDLED; 808 } 809 810 /* return TIOCSER_TEMT when transmitter is not busy */ 811 static unsigned int lpuart_tx_empty(struct uart_port *port) 812 { 813 return (readb(port->membase + UARTSR1) & UARTSR1_TC) ? 814 TIOCSER_TEMT : 0; 815 } 816 817 static unsigned int lpuart32_tx_empty(struct uart_port *port) 818 { 819 return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ? 820 TIOCSER_TEMT : 0; 821 } 822 823 static unsigned int lpuart_get_mctrl(struct uart_port *port) 824 { 825 unsigned int temp = 0; 826 unsigned char reg; 827 828 reg = readb(port->membase + UARTMODEM); 829 if (reg & UARTMODEM_TXCTSE) 830 temp |= TIOCM_CTS; 831 832 if (reg & UARTMODEM_RXRTSE) 833 temp |= TIOCM_RTS; 834 835 return temp; 836 } 837 838 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 839 { 840 unsigned int temp = 0; 841 unsigned long reg; 842 843 reg = lpuart32_read(port->membase + UARTMODIR); 844 if (reg & UARTMODIR_TXCTSE) 845 temp |= TIOCM_CTS; 846 847 if (reg & UARTMODIR_RXRTSE) 848 temp |= TIOCM_RTS; 849 850 return temp; 851 } 852 853 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 854 { 855 unsigned char temp; 856 857 temp = readb(port->membase + UARTMODEM) & 858 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 859 860 if (mctrl & TIOCM_RTS) 861 temp |= UARTMODEM_RXRTSE; 862 863 if (mctrl & TIOCM_CTS) 864 temp |= UARTMODEM_TXCTSE; 865 866 writeb(temp, port->membase + UARTMODEM); 867 } 868 869 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 870 { 871 unsigned long temp; 872 873 temp = lpuart32_read(port->membase + UARTMODIR) & 874 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 875 876 if (mctrl & TIOCM_RTS) 877 temp |= UARTMODIR_RXRTSE; 878 879 if (mctrl & TIOCM_CTS) 880 temp |= UARTMODIR_TXCTSE; 881 882 lpuart32_write(temp, port->membase + UARTMODIR); 883 } 884 885 static void lpuart_break_ctl(struct uart_port *port, int break_state) 886 { 887 unsigned char temp; 888 889 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 890 891 if (break_state != 0) 892 temp |= UARTCR2_SBK; 893 894 writeb(temp, port->membase + UARTCR2); 895 } 896 897 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 898 { 899 unsigned long temp; 900 901 temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK; 902 903 if (break_state != 0) 904 temp |= UARTCTRL_SBK; 905 906 lpuart32_write(temp, port->membase + UARTCTRL); 907 } 908 909 static void lpuart_setup_watermark(struct lpuart_port *sport) 910 { 911 unsigned char val, cr2; 912 unsigned char cr2_saved; 913 914 cr2 = readb(sport->port.membase + UARTCR2); 915 cr2_saved = cr2; 916 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 917 UARTCR2_RIE | UARTCR2_RE); 918 writeb(cr2, sport->port.membase + UARTCR2); 919 920 val = readb(sport->port.membase + UARTPFIFO); 921 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 922 sport->port.membase + UARTPFIFO); 923 924 /* flush Tx and Rx FIFO */ 925 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 926 sport->port.membase + UARTCFIFO); 927 928 writeb(0, sport->port.membase + UARTTWFIFO); 929 writeb(1, sport->port.membase + UARTRWFIFO); 930 931 /* Restore cr2 */ 932 writeb(cr2_saved, sport->port.membase + UARTCR2); 933 } 934 935 static void lpuart32_setup_watermark(struct lpuart_port *sport) 936 { 937 unsigned long val, ctrl; 938 unsigned long ctrl_saved; 939 940 ctrl = lpuart32_read(sport->port.membase + UARTCTRL); 941 ctrl_saved = ctrl; 942 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 943 UARTCTRL_RIE | UARTCTRL_RE); 944 lpuart32_write(ctrl, sport->port.membase + UARTCTRL); 945 946 /* enable FIFO mode */ 947 val = lpuart32_read(sport->port.membase + UARTFIFO); 948 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 949 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 950 lpuart32_write(val, sport->port.membase + UARTFIFO); 951 952 /* set the watermark */ 953 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 954 lpuart32_write(val, sport->port.membase + UARTWATER); 955 956 /* Restore cr2 */ 957 lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL); 958 } 959 960 static int lpuart_dma_tx_request(struct uart_port *port) 961 { 962 struct lpuart_port *sport = container_of(port, 963 struct lpuart_port, port); 964 struct dma_slave_config dma_tx_sconfig; 965 dma_addr_t dma_bus; 966 unsigned char *dma_buf; 967 int ret; 968 969 dma_bus = dma_map_single(sport->dma_tx_chan->device->dev, 970 sport->port.state->xmit.buf, 971 UART_XMIT_SIZE, DMA_TO_DEVICE); 972 973 if (dma_mapping_error(sport->dma_tx_chan->device->dev, dma_bus)) { 974 dev_err(sport->port.dev, "dma_map_single tx failed\n"); 975 return -ENOMEM; 976 } 977 978 dma_buf = sport->port.state->xmit.buf; 979 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR; 980 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 981 dma_tx_sconfig.dst_maxburst = sport->txfifo_size; 982 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 983 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 984 985 if (ret < 0) { 986 dev_err(sport->port.dev, 987 "Dma slave config failed, err = %d\n", ret); 988 return ret; 989 } 990 991 sport->dma_tx_buf_virt = dma_buf; 992 sport->dma_tx_buf_bus = dma_bus; 993 sport->dma_tx_in_progress = 0; 994 995 return 0; 996 } 997 998 static int lpuart_dma_rx_request(struct uart_port *port) 999 { 1000 struct lpuart_port *sport = container_of(port, 1001 struct lpuart_port, port); 1002 struct dma_slave_config dma_rx_sconfig; 1003 dma_addr_t dma_bus; 1004 unsigned char *dma_buf; 1005 int ret; 1006 1007 dma_buf = devm_kzalloc(sport->port.dev, 1008 FSL_UART_RX_DMA_BUFFER_SIZE, GFP_KERNEL); 1009 1010 if (!dma_buf) { 1011 dev_err(sport->port.dev, "Dma rx alloc failed\n"); 1012 return -ENOMEM; 1013 } 1014 1015 dma_bus = dma_map_single(sport->dma_rx_chan->device->dev, dma_buf, 1016 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE); 1017 1018 if (dma_mapping_error(sport->dma_rx_chan->device->dev, dma_bus)) { 1019 dev_err(sport->port.dev, "dma_map_single rx failed\n"); 1020 return -ENOMEM; 1021 } 1022 1023 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR; 1024 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1025 dma_rx_sconfig.src_maxburst = 1; 1026 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1027 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig); 1028 1029 if (ret < 0) { 1030 dev_err(sport->port.dev, 1031 "Dma slave config failed, err = %d\n", ret); 1032 return ret; 1033 } 1034 1035 sport->dma_rx_buf_virt = dma_buf; 1036 sport->dma_rx_buf_bus = dma_bus; 1037 sport->dma_rx_in_progress = 0; 1038 1039 return 0; 1040 } 1041 1042 static void lpuart_dma_tx_free(struct uart_port *port) 1043 { 1044 struct lpuart_port *sport = container_of(port, 1045 struct lpuart_port, port); 1046 1047 dma_unmap_single(sport->port.dev, sport->dma_tx_buf_bus, 1048 UART_XMIT_SIZE, DMA_TO_DEVICE); 1049 1050 sport->dma_tx_buf_bus = 0; 1051 sport->dma_tx_buf_virt = NULL; 1052 } 1053 1054 static void lpuart_dma_rx_free(struct uart_port *port) 1055 { 1056 struct lpuart_port *sport = container_of(port, 1057 struct lpuart_port, port); 1058 1059 dma_unmap_single(sport->port.dev, sport->dma_rx_buf_bus, 1060 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE); 1061 1062 sport->dma_rx_buf_bus = 0; 1063 sport->dma_rx_buf_virt = NULL; 1064 } 1065 1066 static int lpuart_startup(struct uart_port *port) 1067 { 1068 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1069 int ret; 1070 unsigned long flags; 1071 unsigned char temp; 1072 1073 /* determine FIFO size and enable FIFO mode */ 1074 temp = readb(sport->port.membase + UARTPFIFO); 1075 1076 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) & 1077 UARTPFIFO_FIFOSIZE_MASK) + 1); 1078 1079 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) & 1080 UARTPFIFO_FIFOSIZE_MASK) + 1); 1081 1082 if (sport->dma_rx_chan && !lpuart_dma_rx_request(port)) { 1083 sport->lpuart_dma_rx_use = true; 1084 setup_timer(&sport->lpuart_timer, lpuart_timer_func, 1085 (unsigned long)sport); 1086 } else 1087 sport->lpuart_dma_rx_use = false; 1088 1089 1090 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) { 1091 sport->lpuart_dma_tx_use = true; 1092 temp = readb(port->membase + UARTCR5); 1093 temp &= ~UARTCR5_RDMAS; 1094 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5); 1095 } else 1096 sport->lpuart_dma_tx_use = false; 1097 1098 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0, 1099 DRIVER_NAME, sport); 1100 if (ret) 1101 return ret; 1102 1103 spin_lock_irqsave(&sport->port.lock, flags); 1104 1105 lpuart_setup_watermark(sport); 1106 1107 temp = readb(sport->port.membase + UARTCR2); 1108 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 1109 writeb(temp, sport->port.membase + UARTCR2); 1110 1111 spin_unlock_irqrestore(&sport->port.lock, flags); 1112 return 0; 1113 } 1114 1115 static int lpuart32_startup(struct uart_port *port) 1116 { 1117 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1118 int ret; 1119 unsigned long flags; 1120 unsigned long temp; 1121 1122 /* determine FIFO size */ 1123 temp = lpuart32_read(sport->port.membase + UARTFIFO); 1124 1125 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) & 1126 UARTFIFO_FIFOSIZE_MASK) - 1); 1127 1128 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) & 1129 UARTFIFO_FIFOSIZE_MASK) - 1); 1130 1131 ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0, 1132 DRIVER_NAME, sport); 1133 if (ret) 1134 return ret; 1135 1136 spin_lock_irqsave(&sport->port.lock, flags); 1137 1138 lpuart32_setup_watermark(sport); 1139 1140 temp = lpuart32_read(sport->port.membase + UARTCTRL); 1141 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE); 1142 temp |= UARTCTRL_ILIE; 1143 lpuart32_write(temp, sport->port.membase + UARTCTRL); 1144 1145 spin_unlock_irqrestore(&sport->port.lock, flags); 1146 return 0; 1147 } 1148 1149 static void lpuart_shutdown(struct uart_port *port) 1150 { 1151 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1152 unsigned char temp; 1153 unsigned long flags; 1154 1155 spin_lock_irqsave(&port->lock, flags); 1156 1157 /* disable Rx/Tx and interrupts */ 1158 temp = readb(port->membase + UARTCR2); 1159 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1160 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1161 writeb(temp, port->membase + UARTCR2); 1162 1163 spin_unlock_irqrestore(&port->lock, flags); 1164 1165 devm_free_irq(port->dev, port->irq, sport); 1166 1167 if (sport->lpuart_dma_rx_use) { 1168 lpuart_dma_rx_free(&sport->port); 1169 del_timer_sync(&sport->lpuart_timer); 1170 } 1171 1172 if (sport->lpuart_dma_tx_use) 1173 lpuart_dma_tx_free(&sport->port); 1174 } 1175 1176 static void lpuart32_shutdown(struct uart_port *port) 1177 { 1178 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1179 unsigned long temp; 1180 unsigned long flags; 1181 1182 spin_lock_irqsave(&port->lock, flags); 1183 1184 /* disable Rx/Tx and interrupts */ 1185 temp = lpuart32_read(port->membase + UARTCTRL); 1186 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1187 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1188 lpuart32_write(temp, port->membase + UARTCTRL); 1189 1190 spin_unlock_irqrestore(&port->lock, flags); 1191 1192 devm_free_irq(port->dev, port->irq, sport); 1193 } 1194 1195 static void 1196 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1197 struct ktermios *old) 1198 { 1199 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1200 unsigned long flags; 1201 unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem; 1202 unsigned int baud; 1203 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1204 unsigned int sbr, brfa; 1205 1206 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1207 old_cr2 = readb(sport->port.membase + UARTCR2); 1208 cr4 = readb(sport->port.membase + UARTCR4); 1209 bdh = readb(sport->port.membase + UARTBDH); 1210 modem = readb(sport->port.membase + UARTMODEM); 1211 /* 1212 * only support CS8 and CS7, and for CS7 must enable PE. 1213 * supported mode: 1214 * - (7,e/o,1) 1215 * - (8,n,1) 1216 * - (8,m/s,1) 1217 * - (8,e/o,1) 1218 */ 1219 while ((termios->c_cflag & CSIZE) != CS8 && 1220 (termios->c_cflag & CSIZE) != CS7) { 1221 termios->c_cflag &= ~CSIZE; 1222 termios->c_cflag |= old_csize; 1223 old_csize = CS8; 1224 } 1225 1226 if ((termios->c_cflag & CSIZE) == CS8 || 1227 (termios->c_cflag & CSIZE) == CS7) 1228 cr1 = old_cr1 & ~UARTCR1_M; 1229 1230 if (termios->c_cflag & CMSPAR) { 1231 if ((termios->c_cflag & CSIZE) != CS8) { 1232 termios->c_cflag &= ~CSIZE; 1233 termios->c_cflag |= CS8; 1234 } 1235 cr1 |= UARTCR1_M; 1236 } 1237 1238 if (termios->c_cflag & CRTSCTS) { 1239 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1240 } else { 1241 termios->c_cflag &= ~CRTSCTS; 1242 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1243 } 1244 1245 if (termios->c_cflag & CSTOPB) 1246 termios->c_cflag &= ~CSTOPB; 1247 1248 /* parity must be enabled when CS7 to match 8-bits format */ 1249 if ((termios->c_cflag & CSIZE) == CS7) 1250 termios->c_cflag |= PARENB; 1251 1252 if ((termios->c_cflag & PARENB)) { 1253 if (termios->c_cflag & CMSPAR) { 1254 cr1 &= ~UARTCR1_PE; 1255 cr1 |= UARTCR1_M; 1256 } else { 1257 cr1 |= UARTCR1_PE; 1258 if ((termios->c_cflag & CSIZE) == CS8) 1259 cr1 |= UARTCR1_M; 1260 if (termios->c_cflag & PARODD) 1261 cr1 |= UARTCR1_PT; 1262 else 1263 cr1 &= ~UARTCR1_PT; 1264 } 1265 } 1266 1267 /* ask the core to calculate the divisor */ 1268 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1269 1270 spin_lock_irqsave(&sport->port.lock, flags); 1271 1272 sport->port.read_status_mask = 0; 1273 if (termios->c_iflag & INPCK) 1274 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE); 1275 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1276 sport->port.read_status_mask |= UARTSR1_FE; 1277 1278 /* characters to ignore */ 1279 sport->port.ignore_status_mask = 0; 1280 if (termios->c_iflag & IGNPAR) 1281 sport->port.ignore_status_mask |= UARTSR1_PE; 1282 if (termios->c_iflag & IGNBRK) { 1283 sport->port.ignore_status_mask |= UARTSR1_FE; 1284 /* 1285 * if we're ignoring parity and break indicators, 1286 * ignore overruns too (for real raw support). 1287 */ 1288 if (termios->c_iflag & IGNPAR) 1289 sport->port.ignore_status_mask |= UARTSR1_OR; 1290 } 1291 1292 /* update the per-port timeout */ 1293 uart_update_timeout(port, termios->c_cflag, baud); 1294 1295 if (sport->lpuart_dma_rx_use) { 1296 /* Calculate delay for 1.5 DMA buffers */ 1297 sport->dma_rx_timeout = (sport->port.timeout - HZ / 50) * 1298 FSL_UART_RX_DMA_BUFFER_SIZE * 3 / 1299 sport->rxfifo_size / 2; 1300 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n", 1301 sport->dma_rx_timeout * 1000 / HZ, sport->port.timeout); 1302 if (sport->dma_rx_timeout < msecs_to_jiffies(20)) 1303 sport->dma_rx_timeout = msecs_to_jiffies(20); 1304 } 1305 1306 /* wait transmit engin complete */ 1307 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1308 barrier(); 1309 1310 /* disable transmit and receive */ 1311 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1312 sport->port.membase + UARTCR2); 1313 1314 sbr = sport->port.uartclk / (16 * baud); 1315 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1316 bdh &= ~UARTBDH_SBR_MASK; 1317 bdh |= (sbr >> 8) & 0x1F; 1318 cr4 &= ~UARTCR4_BRFA_MASK; 1319 brfa &= UARTCR4_BRFA_MASK; 1320 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1321 writeb(bdh, sport->port.membase + UARTBDH); 1322 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1323 writeb(cr1, sport->port.membase + UARTCR1); 1324 writeb(modem, sport->port.membase + UARTMODEM); 1325 1326 /* restore control register */ 1327 writeb(old_cr2, sport->port.membase + UARTCR2); 1328 1329 spin_unlock_irqrestore(&sport->port.lock, flags); 1330 } 1331 1332 static void 1333 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 1334 struct ktermios *old) 1335 { 1336 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1337 unsigned long flags; 1338 unsigned long ctrl, old_ctrl, bd, modem; 1339 unsigned int baud; 1340 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1341 unsigned int sbr; 1342 1343 ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL); 1344 bd = lpuart32_read(sport->port.membase + UARTBAUD); 1345 modem = lpuart32_read(sport->port.membase + UARTMODIR); 1346 /* 1347 * only support CS8 and CS7, and for CS7 must enable PE. 1348 * supported mode: 1349 * - (7,e/o,1) 1350 * - (8,n,1) 1351 * - (8,m/s,1) 1352 * - (8,e/o,1) 1353 */ 1354 while ((termios->c_cflag & CSIZE) != CS8 && 1355 (termios->c_cflag & CSIZE) != CS7) { 1356 termios->c_cflag &= ~CSIZE; 1357 termios->c_cflag |= old_csize; 1358 old_csize = CS8; 1359 } 1360 1361 if ((termios->c_cflag & CSIZE) == CS8 || 1362 (termios->c_cflag & CSIZE) == CS7) 1363 ctrl = old_ctrl & ~UARTCTRL_M; 1364 1365 if (termios->c_cflag & CMSPAR) { 1366 if ((termios->c_cflag & CSIZE) != CS8) { 1367 termios->c_cflag &= ~CSIZE; 1368 termios->c_cflag |= CS8; 1369 } 1370 ctrl |= UARTCTRL_M; 1371 } 1372 1373 if (termios->c_cflag & CRTSCTS) { 1374 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1375 } else { 1376 termios->c_cflag &= ~CRTSCTS; 1377 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1378 } 1379 1380 if (termios->c_cflag & CSTOPB) 1381 termios->c_cflag &= ~CSTOPB; 1382 1383 /* parity must be enabled when CS7 to match 8-bits format */ 1384 if ((termios->c_cflag & CSIZE) == CS7) 1385 termios->c_cflag |= PARENB; 1386 1387 if ((termios->c_cflag & PARENB)) { 1388 if (termios->c_cflag & CMSPAR) { 1389 ctrl &= ~UARTCTRL_PE; 1390 ctrl |= UARTCTRL_M; 1391 } else { 1392 ctrl |= UARTCR1_PE; 1393 if ((termios->c_cflag & CSIZE) == CS8) 1394 ctrl |= UARTCTRL_M; 1395 if (termios->c_cflag & PARODD) 1396 ctrl |= UARTCTRL_PT; 1397 else 1398 ctrl &= ~UARTCTRL_PT; 1399 } 1400 } 1401 1402 /* ask the core to calculate the divisor */ 1403 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1404 1405 spin_lock_irqsave(&sport->port.lock, flags); 1406 1407 sport->port.read_status_mask = 0; 1408 if (termios->c_iflag & INPCK) 1409 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE); 1410 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1411 sport->port.read_status_mask |= UARTSTAT_FE; 1412 1413 /* characters to ignore */ 1414 sport->port.ignore_status_mask = 0; 1415 if (termios->c_iflag & IGNPAR) 1416 sport->port.ignore_status_mask |= UARTSTAT_PE; 1417 if (termios->c_iflag & IGNBRK) { 1418 sport->port.ignore_status_mask |= UARTSTAT_FE; 1419 /* 1420 * if we're ignoring parity and break indicators, 1421 * ignore overruns too (for real raw support). 1422 */ 1423 if (termios->c_iflag & IGNPAR) 1424 sport->port.ignore_status_mask |= UARTSTAT_OR; 1425 } 1426 1427 /* update the per-port timeout */ 1428 uart_update_timeout(port, termios->c_cflag, baud); 1429 1430 /* wait transmit engin complete */ 1431 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC)) 1432 barrier(); 1433 1434 /* disable transmit and receive */ 1435 lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 1436 sport->port.membase + UARTCTRL); 1437 1438 sbr = sport->port.uartclk / (16 * baud); 1439 bd &= ~UARTBAUD_SBR_MASK; 1440 bd |= sbr & UARTBAUD_SBR_MASK; 1441 bd |= UARTBAUD_BOTHEDGE; 1442 bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); 1443 lpuart32_write(bd, sport->port.membase + UARTBAUD); 1444 lpuart32_write(modem, sport->port.membase + UARTMODIR); 1445 lpuart32_write(ctrl, sport->port.membase + UARTCTRL); 1446 /* restore control register */ 1447 1448 spin_unlock_irqrestore(&sport->port.lock, flags); 1449 } 1450 1451 static const char *lpuart_type(struct uart_port *port) 1452 { 1453 return "FSL_LPUART"; 1454 } 1455 1456 static void lpuart_release_port(struct uart_port *port) 1457 { 1458 /* nothing to do */ 1459 } 1460 1461 static int lpuart_request_port(struct uart_port *port) 1462 { 1463 return 0; 1464 } 1465 1466 /* configure/autoconfigure the port */ 1467 static void lpuart_config_port(struct uart_port *port, int flags) 1468 { 1469 if (flags & UART_CONFIG_TYPE) 1470 port->type = PORT_LPUART; 1471 } 1472 1473 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 1474 { 1475 int ret = 0; 1476 1477 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 1478 ret = -EINVAL; 1479 if (port->irq != ser->irq) 1480 ret = -EINVAL; 1481 if (ser->io_type != UPIO_MEM) 1482 ret = -EINVAL; 1483 if (port->uartclk / 16 != ser->baud_base) 1484 ret = -EINVAL; 1485 if (port->iobase != ser->port) 1486 ret = -EINVAL; 1487 if (ser->hub6 != 0) 1488 ret = -EINVAL; 1489 return ret; 1490 } 1491 1492 static struct uart_ops lpuart_pops = { 1493 .tx_empty = lpuart_tx_empty, 1494 .set_mctrl = lpuart_set_mctrl, 1495 .get_mctrl = lpuart_get_mctrl, 1496 .stop_tx = lpuart_stop_tx, 1497 .start_tx = lpuart_start_tx, 1498 .stop_rx = lpuart_stop_rx, 1499 .break_ctl = lpuart_break_ctl, 1500 .startup = lpuart_startup, 1501 .shutdown = lpuart_shutdown, 1502 .set_termios = lpuart_set_termios, 1503 .type = lpuart_type, 1504 .request_port = lpuart_request_port, 1505 .release_port = lpuart_release_port, 1506 .config_port = lpuart_config_port, 1507 .verify_port = lpuart_verify_port, 1508 .flush_buffer = lpuart_flush_buffer, 1509 }; 1510 1511 static struct uart_ops lpuart32_pops = { 1512 .tx_empty = lpuart32_tx_empty, 1513 .set_mctrl = lpuart32_set_mctrl, 1514 .get_mctrl = lpuart32_get_mctrl, 1515 .stop_tx = lpuart32_stop_tx, 1516 .start_tx = lpuart32_start_tx, 1517 .stop_rx = lpuart32_stop_rx, 1518 .break_ctl = lpuart32_break_ctl, 1519 .startup = lpuart32_startup, 1520 .shutdown = lpuart32_shutdown, 1521 .set_termios = lpuart32_set_termios, 1522 .type = lpuart_type, 1523 .request_port = lpuart_request_port, 1524 .release_port = lpuart_release_port, 1525 .config_port = lpuart_config_port, 1526 .verify_port = lpuart_verify_port, 1527 .flush_buffer = lpuart_flush_buffer, 1528 }; 1529 1530 static struct lpuart_port *lpuart_ports[UART_NR]; 1531 1532 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 1533 static void lpuart_console_putchar(struct uart_port *port, int ch) 1534 { 1535 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) 1536 barrier(); 1537 1538 writeb(ch, port->membase + UARTDR); 1539 } 1540 1541 static void lpuart32_console_putchar(struct uart_port *port, int ch) 1542 { 1543 while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)) 1544 barrier(); 1545 1546 lpuart32_write(ch, port->membase + UARTDATA); 1547 } 1548 1549 static void 1550 lpuart_console_write(struct console *co, const char *s, unsigned int count) 1551 { 1552 struct lpuart_port *sport = lpuart_ports[co->index]; 1553 unsigned char old_cr2, cr2; 1554 1555 /* first save CR2 and then disable interrupts */ 1556 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 1557 cr2 |= (UARTCR2_TE | UARTCR2_RE); 1558 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1559 writeb(cr2, sport->port.membase + UARTCR2); 1560 1561 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 1562 1563 /* wait for transmitter finish complete and restore CR2 */ 1564 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1565 barrier(); 1566 1567 writeb(old_cr2, sport->port.membase + UARTCR2); 1568 } 1569 1570 static void 1571 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 1572 { 1573 struct lpuart_port *sport = lpuart_ports[co->index]; 1574 unsigned long old_cr, cr; 1575 1576 /* first save CR2 and then disable interrupts */ 1577 cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL); 1578 cr |= (UARTCTRL_TE | UARTCTRL_RE); 1579 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1580 lpuart32_write(cr, sport->port.membase + UARTCTRL); 1581 1582 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 1583 1584 /* wait for transmitter finish complete and restore CR2 */ 1585 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC)) 1586 barrier(); 1587 1588 lpuart32_write(old_cr, sport->port.membase + UARTCTRL); 1589 } 1590 1591 /* 1592 * if the port was already initialised (eg, by a boot loader), 1593 * try to determine the current setup. 1594 */ 1595 static void __init 1596 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 1597 int *parity, int *bits) 1598 { 1599 unsigned char cr, bdh, bdl, brfa; 1600 unsigned int sbr, uartclk, baud_raw; 1601 1602 cr = readb(sport->port.membase + UARTCR2); 1603 cr &= UARTCR2_TE | UARTCR2_RE; 1604 if (!cr) 1605 return; 1606 1607 /* ok, the port was enabled */ 1608 1609 cr = readb(sport->port.membase + UARTCR1); 1610 1611 *parity = 'n'; 1612 if (cr & UARTCR1_PE) { 1613 if (cr & UARTCR1_PT) 1614 *parity = 'o'; 1615 else 1616 *parity = 'e'; 1617 } 1618 1619 if (cr & UARTCR1_M) 1620 *bits = 9; 1621 else 1622 *bits = 8; 1623 1624 bdh = readb(sport->port.membase + UARTBDH); 1625 bdh &= UARTBDH_SBR_MASK; 1626 bdl = readb(sport->port.membase + UARTBDL); 1627 sbr = bdh; 1628 sbr <<= 8; 1629 sbr |= bdl; 1630 brfa = readb(sport->port.membase + UARTCR4); 1631 brfa &= UARTCR4_BRFA_MASK; 1632 1633 uartclk = clk_get_rate(sport->clk); 1634 /* 1635 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 1636 */ 1637 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 1638 1639 if (*baud != baud_raw) 1640 printk(KERN_INFO "Serial: Console lpuart rounded baud rate" 1641 "from %d to %d\n", baud_raw, *baud); 1642 } 1643 1644 static void __init 1645 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 1646 int *parity, int *bits) 1647 { 1648 unsigned long cr, bd; 1649 unsigned int sbr, uartclk, baud_raw; 1650 1651 cr = lpuart32_read(sport->port.membase + UARTCTRL); 1652 cr &= UARTCTRL_TE | UARTCTRL_RE; 1653 if (!cr) 1654 return; 1655 1656 /* ok, the port was enabled */ 1657 1658 cr = lpuart32_read(sport->port.membase + UARTCTRL); 1659 1660 *parity = 'n'; 1661 if (cr & UARTCTRL_PE) { 1662 if (cr & UARTCTRL_PT) 1663 *parity = 'o'; 1664 else 1665 *parity = 'e'; 1666 } 1667 1668 if (cr & UARTCTRL_M) 1669 *bits = 9; 1670 else 1671 *bits = 8; 1672 1673 bd = lpuart32_read(sport->port.membase + UARTBAUD); 1674 bd &= UARTBAUD_SBR_MASK; 1675 sbr = bd; 1676 uartclk = clk_get_rate(sport->clk); 1677 /* 1678 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 1679 */ 1680 baud_raw = uartclk / (16 * sbr); 1681 1682 if (*baud != baud_raw) 1683 printk(KERN_INFO "Serial: Console lpuart rounded baud rate" 1684 "from %d to %d\n", baud_raw, *baud); 1685 } 1686 1687 static int __init lpuart_console_setup(struct console *co, char *options) 1688 { 1689 struct lpuart_port *sport; 1690 int baud = 115200; 1691 int bits = 8; 1692 int parity = 'n'; 1693 int flow = 'n'; 1694 1695 /* 1696 * check whether an invalid uart number has been specified, and 1697 * if so, search for the first available port that does have 1698 * console support. 1699 */ 1700 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 1701 co->index = 0; 1702 1703 sport = lpuart_ports[co->index]; 1704 if (sport == NULL) 1705 return -ENODEV; 1706 1707 if (options) 1708 uart_parse_options(options, &baud, &parity, &bits, &flow); 1709 else 1710 if (sport->lpuart32) 1711 lpuart32_console_get_options(sport, &baud, &parity, &bits); 1712 else 1713 lpuart_console_get_options(sport, &baud, &parity, &bits); 1714 1715 if (sport->lpuart32) 1716 lpuart32_setup_watermark(sport); 1717 else 1718 lpuart_setup_watermark(sport); 1719 1720 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 1721 } 1722 1723 static struct uart_driver lpuart_reg; 1724 static struct console lpuart_console = { 1725 .name = DEV_NAME, 1726 .write = lpuart_console_write, 1727 .device = uart_console_device, 1728 .setup = lpuart_console_setup, 1729 .flags = CON_PRINTBUFFER, 1730 .index = -1, 1731 .data = &lpuart_reg, 1732 }; 1733 1734 static struct console lpuart32_console = { 1735 .name = DEV_NAME, 1736 .write = lpuart32_console_write, 1737 .device = uart_console_device, 1738 .setup = lpuart_console_setup, 1739 .flags = CON_PRINTBUFFER, 1740 .index = -1, 1741 .data = &lpuart_reg, 1742 }; 1743 1744 #define LPUART_CONSOLE (&lpuart_console) 1745 #define LPUART32_CONSOLE (&lpuart32_console) 1746 #else 1747 #define LPUART_CONSOLE NULL 1748 #define LPUART32_CONSOLE NULL 1749 #endif 1750 1751 static struct uart_driver lpuart_reg = { 1752 .owner = THIS_MODULE, 1753 .driver_name = DRIVER_NAME, 1754 .dev_name = DEV_NAME, 1755 .nr = ARRAY_SIZE(lpuart_ports), 1756 .cons = LPUART_CONSOLE, 1757 }; 1758 1759 static int lpuart_probe(struct platform_device *pdev) 1760 { 1761 struct device_node *np = pdev->dev.of_node; 1762 struct lpuart_port *sport; 1763 struct resource *res; 1764 int ret; 1765 1766 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1767 if (!sport) 1768 return -ENOMEM; 1769 1770 pdev->dev.coherent_dma_mask = 0; 1771 1772 ret = of_alias_get_id(np, "serial"); 1773 if (ret < 0) { 1774 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1775 return ret; 1776 } 1777 sport->port.line = ret; 1778 sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart"); 1779 1780 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1781 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 1782 if (IS_ERR(sport->port.membase)) 1783 return PTR_ERR(sport->port.membase); 1784 1785 sport->port.mapbase = res->start; 1786 sport->port.dev = &pdev->dev; 1787 sport->port.type = PORT_LPUART; 1788 sport->port.iotype = UPIO_MEM; 1789 sport->port.irq = platform_get_irq(pdev, 0); 1790 if (sport->lpuart32) 1791 sport->port.ops = &lpuart32_pops; 1792 else 1793 sport->port.ops = &lpuart_pops; 1794 sport->port.flags = UPF_BOOT_AUTOCONF; 1795 1796 sport->clk = devm_clk_get(&pdev->dev, "ipg"); 1797 if (IS_ERR(sport->clk)) { 1798 ret = PTR_ERR(sport->clk); 1799 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret); 1800 return ret; 1801 } 1802 1803 ret = clk_prepare_enable(sport->clk); 1804 if (ret) { 1805 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret); 1806 return ret; 1807 } 1808 1809 sport->port.uartclk = clk_get_rate(sport->clk); 1810 1811 lpuart_ports[sport->port.line] = sport; 1812 1813 platform_set_drvdata(pdev, &sport->port); 1814 1815 if (sport->lpuart32) 1816 lpuart_reg.cons = LPUART32_CONSOLE; 1817 else 1818 lpuart_reg.cons = LPUART_CONSOLE; 1819 1820 ret = uart_add_one_port(&lpuart_reg, &sport->port); 1821 if (ret) { 1822 clk_disable_unprepare(sport->clk); 1823 return ret; 1824 } 1825 1826 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx"); 1827 if (!sport->dma_tx_chan) 1828 dev_info(sport->port.dev, "DMA tx channel request failed, " 1829 "operating without tx DMA\n"); 1830 1831 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx"); 1832 if (!sport->dma_rx_chan) 1833 dev_info(sport->port.dev, "DMA rx channel request failed, " 1834 "operating without rx DMA\n"); 1835 1836 return 0; 1837 } 1838 1839 static int lpuart_remove(struct platform_device *pdev) 1840 { 1841 struct lpuart_port *sport = platform_get_drvdata(pdev); 1842 1843 uart_remove_one_port(&lpuart_reg, &sport->port); 1844 1845 clk_disable_unprepare(sport->clk); 1846 1847 if (sport->dma_tx_chan) 1848 dma_release_channel(sport->dma_tx_chan); 1849 1850 if (sport->dma_rx_chan) 1851 dma_release_channel(sport->dma_rx_chan); 1852 1853 return 0; 1854 } 1855 1856 #ifdef CONFIG_PM_SLEEP 1857 static int lpuart_suspend(struct device *dev) 1858 { 1859 struct lpuart_port *sport = dev_get_drvdata(dev); 1860 unsigned long temp; 1861 1862 if (sport->lpuart32) { 1863 /* disable Rx/Tx and interrupts */ 1864 temp = lpuart32_read(sport->port.membase + UARTCTRL); 1865 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 1866 lpuart32_write(temp, sport->port.membase + UARTCTRL); 1867 } else { 1868 /* disable Rx/Tx and interrupts */ 1869 temp = readb(sport->port.membase + UARTCR2); 1870 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 1871 writeb(temp, sport->port.membase + UARTCR2); 1872 } 1873 1874 uart_suspend_port(&lpuart_reg, &sport->port); 1875 1876 return 0; 1877 } 1878 1879 static int lpuart_resume(struct device *dev) 1880 { 1881 struct lpuart_port *sport = dev_get_drvdata(dev); 1882 unsigned long temp; 1883 1884 if (sport->lpuart32) { 1885 lpuart32_setup_watermark(sport); 1886 temp = lpuart32_read(sport->port.membase + UARTCTRL); 1887 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | 1888 UARTCTRL_TE | UARTCTRL_ILIE); 1889 lpuart32_write(temp, sport->port.membase + UARTCTRL); 1890 } else { 1891 lpuart_setup_watermark(sport); 1892 temp = readb(sport->port.membase + UARTCR2); 1893 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 1894 writeb(temp, sport->port.membase + UARTCR2); 1895 } 1896 1897 uart_resume_port(&lpuart_reg, &sport->port); 1898 1899 return 0; 1900 } 1901 #endif 1902 1903 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 1904 1905 static struct platform_driver lpuart_driver = { 1906 .probe = lpuart_probe, 1907 .remove = lpuart_remove, 1908 .driver = { 1909 .name = "fsl-lpuart", 1910 .of_match_table = lpuart_dt_ids, 1911 .pm = &lpuart_pm_ops, 1912 }, 1913 }; 1914 1915 static int __init lpuart_serial_init(void) 1916 { 1917 int ret = uart_register_driver(&lpuart_reg); 1918 1919 if (ret) 1920 return ret; 1921 1922 ret = platform_driver_register(&lpuart_driver); 1923 if (ret) 1924 uart_unregister_driver(&lpuart_reg); 1925 1926 return ret; 1927 } 1928 1929 static void __exit lpuart_serial_exit(void) 1930 { 1931 platform_driver_unregister(&lpuart_driver); 1932 uart_unregister_driver(&lpuart_reg); 1933 } 1934 1935 module_init(lpuart_serial_init); 1936 module_exit(lpuart_serial_exit); 1937 1938 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 1939 MODULE_LICENSE("GPL v2"); 1940