1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale lpuart serial port driver 4 * 5 * Copyright 2012-2014 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/console.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dmapool.h> 13 #include <linux/io.h> 14 #include <linux/irq.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/of_dma.h> 19 #include <linux/serial_core.h> 20 #include <linux/slab.h> 21 #include <linux/tty_flip.h> 22 23 /* All registers are 8-bit width */ 24 #define UARTBDH 0x00 25 #define UARTBDL 0x01 26 #define UARTCR1 0x02 27 #define UARTCR2 0x03 28 #define UARTSR1 0x04 29 #define UARTCR3 0x06 30 #define UARTDR 0x07 31 #define UARTCR4 0x0a 32 #define UARTCR5 0x0b 33 #define UARTMODEM 0x0d 34 #define UARTPFIFO 0x10 35 #define UARTCFIFO 0x11 36 #define UARTSFIFO 0x12 37 #define UARTTWFIFO 0x13 38 #define UARTTCFIFO 0x14 39 #define UARTRWFIFO 0x15 40 41 #define UARTBDH_LBKDIE 0x80 42 #define UARTBDH_RXEDGIE 0x40 43 #define UARTBDH_SBR_MASK 0x1f 44 45 #define UARTCR1_LOOPS 0x80 46 #define UARTCR1_RSRC 0x20 47 #define UARTCR1_M 0x10 48 #define UARTCR1_WAKE 0x08 49 #define UARTCR1_ILT 0x04 50 #define UARTCR1_PE 0x02 51 #define UARTCR1_PT 0x01 52 53 #define UARTCR2_TIE 0x80 54 #define UARTCR2_TCIE 0x40 55 #define UARTCR2_RIE 0x20 56 #define UARTCR2_ILIE 0x10 57 #define UARTCR2_TE 0x08 58 #define UARTCR2_RE 0x04 59 #define UARTCR2_RWU 0x02 60 #define UARTCR2_SBK 0x01 61 62 #define UARTSR1_TDRE 0x80 63 #define UARTSR1_TC 0x40 64 #define UARTSR1_RDRF 0x20 65 #define UARTSR1_IDLE 0x10 66 #define UARTSR1_OR 0x08 67 #define UARTSR1_NF 0x04 68 #define UARTSR1_FE 0x02 69 #define UARTSR1_PE 0x01 70 71 #define UARTCR3_R8 0x80 72 #define UARTCR3_T8 0x40 73 #define UARTCR3_TXDIR 0x20 74 #define UARTCR3_TXINV 0x10 75 #define UARTCR3_ORIE 0x08 76 #define UARTCR3_NEIE 0x04 77 #define UARTCR3_FEIE 0x02 78 #define UARTCR3_PEIE 0x01 79 80 #define UARTCR4_MAEN1 0x80 81 #define UARTCR4_MAEN2 0x40 82 #define UARTCR4_M10 0x20 83 #define UARTCR4_BRFA_MASK 0x1f 84 #define UARTCR4_BRFA_OFF 0 85 86 #define UARTCR5_TDMAS 0x80 87 #define UARTCR5_RDMAS 0x20 88 89 #define UARTMODEM_RXRTSE 0x08 90 #define UARTMODEM_TXRTSPOL 0x04 91 #define UARTMODEM_TXRTSE 0x02 92 #define UARTMODEM_TXCTSE 0x01 93 94 #define UARTPFIFO_TXFE 0x80 95 #define UARTPFIFO_FIFOSIZE_MASK 0x7 96 #define UARTPFIFO_TXSIZE_OFF 4 97 #define UARTPFIFO_RXFE 0x08 98 #define UARTPFIFO_RXSIZE_OFF 0 99 100 #define UARTCFIFO_TXFLUSH 0x80 101 #define UARTCFIFO_RXFLUSH 0x40 102 #define UARTCFIFO_RXOFE 0x04 103 #define UARTCFIFO_TXOFE 0x02 104 #define UARTCFIFO_RXUFE 0x01 105 106 #define UARTSFIFO_TXEMPT 0x80 107 #define UARTSFIFO_RXEMPT 0x40 108 #define UARTSFIFO_RXOF 0x04 109 #define UARTSFIFO_TXOF 0x02 110 #define UARTSFIFO_RXUF 0x01 111 112 /* 32-bit register definition */ 113 #define UARTBAUD 0x00 114 #define UARTSTAT 0x04 115 #define UARTCTRL 0x08 116 #define UARTDATA 0x0C 117 #define UARTMATCH 0x10 118 #define UARTMODIR 0x14 119 #define UARTFIFO 0x18 120 #define UARTWATER 0x1c 121 122 #define UARTBAUD_MAEN1 0x80000000 123 #define UARTBAUD_MAEN2 0x40000000 124 #define UARTBAUD_M10 0x20000000 125 #define UARTBAUD_TDMAE 0x00800000 126 #define UARTBAUD_RDMAE 0x00200000 127 #define UARTBAUD_MATCFG 0x00400000 128 #define UARTBAUD_BOTHEDGE 0x00020000 129 #define UARTBAUD_RESYNCDIS 0x00010000 130 #define UARTBAUD_LBKDIE 0x00008000 131 #define UARTBAUD_RXEDGIE 0x00004000 132 #define UARTBAUD_SBNS 0x00002000 133 #define UARTBAUD_SBR 0x00000000 134 #define UARTBAUD_SBR_MASK 0x1fff 135 #define UARTBAUD_OSR_MASK 0x1f 136 #define UARTBAUD_OSR_SHIFT 24 137 138 #define UARTSTAT_LBKDIF 0x80000000 139 #define UARTSTAT_RXEDGIF 0x40000000 140 #define UARTSTAT_MSBF 0x20000000 141 #define UARTSTAT_RXINV 0x10000000 142 #define UARTSTAT_RWUID 0x08000000 143 #define UARTSTAT_BRK13 0x04000000 144 #define UARTSTAT_LBKDE 0x02000000 145 #define UARTSTAT_RAF 0x01000000 146 #define UARTSTAT_TDRE 0x00800000 147 #define UARTSTAT_TC 0x00400000 148 #define UARTSTAT_RDRF 0x00200000 149 #define UARTSTAT_IDLE 0x00100000 150 #define UARTSTAT_OR 0x00080000 151 #define UARTSTAT_NF 0x00040000 152 #define UARTSTAT_FE 0x00020000 153 #define UARTSTAT_PE 0x00010000 154 #define UARTSTAT_MA1F 0x00008000 155 #define UARTSTAT_M21F 0x00004000 156 157 #define UARTCTRL_R8T9 0x80000000 158 #define UARTCTRL_R9T8 0x40000000 159 #define UARTCTRL_TXDIR 0x20000000 160 #define UARTCTRL_TXINV 0x10000000 161 #define UARTCTRL_ORIE 0x08000000 162 #define UARTCTRL_NEIE 0x04000000 163 #define UARTCTRL_FEIE 0x02000000 164 #define UARTCTRL_PEIE 0x01000000 165 #define UARTCTRL_TIE 0x00800000 166 #define UARTCTRL_TCIE 0x00400000 167 #define UARTCTRL_RIE 0x00200000 168 #define UARTCTRL_ILIE 0x00100000 169 #define UARTCTRL_TE 0x00080000 170 #define UARTCTRL_RE 0x00040000 171 #define UARTCTRL_RWU 0x00020000 172 #define UARTCTRL_SBK 0x00010000 173 #define UARTCTRL_MA1IE 0x00008000 174 #define UARTCTRL_MA2IE 0x00004000 175 #define UARTCTRL_IDLECFG 0x00000100 176 #define UARTCTRL_LOOPS 0x00000080 177 #define UARTCTRL_DOZEEN 0x00000040 178 #define UARTCTRL_RSRC 0x00000020 179 #define UARTCTRL_M 0x00000010 180 #define UARTCTRL_WAKE 0x00000008 181 #define UARTCTRL_ILT 0x00000004 182 #define UARTCTRL_PE 0x00000002 183 #define UARTCTRL_PT 0x00000001 184 185 #define UARTDATA_NOISY 0x00008000 186 #define UARTDATA_PARITYE 0x00004000 187 #define UARTDATA_FRETSC 0x00002000 188 #define UARTDATA_RXEMPT 0x00001000 189 #define UARTDATA_IDLINE 0x00000800 190 #define UARTDATA_MASK 0x3ff 191 192 #define UARTMODIR_IREN 0x00020000 193 #define UARTMODIR_TXCTSSRC 0x00000020 194 #define UARTMODIR_TXCTSC 0x00000010 195 #define UARTMODIR_RXRTSE 0x00000008 196 #define UARTMODIR_TXRTSPOL 0x00000004 197 #define UARTMODIR_TXRTSE 0x00000002 198 #define UARTMODIR_TXCTSE 0x00000001 199 200 #define UARTFIFO_TXEMPT 0x00800000 201 #define UARTFIFO_RXEMPT 0x00400000 202 #define UARTFIFO_TXOF 0x00020000 203 #define UARTFIFO_RXUF 0x00010000 204 #define UARTFIFO_TXFLUSH 0x00008000 205 #define UARTFIFO_RXFLUSH 0x00004000 206 #define UARTFIFO_TXOFE 0x00000200 207 #define UARTFIFO_RXUFE 0x00000100 208 #define UARTFIFO_TXFE 0x00000080 209 #define UARTFIFO_FIFOSIZE_MASK 0x7 210 #define UARTFIFO_TXSIZE_OFF 4 211 #define UARTFIFO_RXFE 0x00000008 212 #define UARTFIFO_RXSIZE_OFF 0 213 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0)) 214 215 #define UARTWATER_COUNT_MASK 0xff 216 #define UARTWATER_TXCNT_OFF 8 217 #define UARTWATER_RXCNT_OFF 24 218 #define UARTWATER_WATER_MASK 0xff 219 #define UARTWATER_TXWATER_OFF 0 220 #define UARTWATER_RXWATER_OFF 16 221 222 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 223 #define DMA_RX_TIMEOUT (10) 224 225 #define DRIVER_NAME "fsl-lpuart" 226 #define DEV_NAME "ttyLP" 227 #define UART_NR 6 228 229 /* IMX lpuart has four extra unused regs located at the beginning */ 230 #define IMX_REG_OFF 0x10 231 232 static DEFINE_IDA(fsl_lpuart_ida); 233 234 enum lpuart_type { 235 VF610_LPUART, 236 LS1021A_LPUART, 237 LS1028A_LPUART, 238 IMX7ULP_LPUART, 239 IMX8QXP_LPUART, 240 }; 241 242 struct lpuart_port { 243 struct uart_port port; 244 enum lpuart_type devtype; 245 struct clk *ipg_clk; 246 struct clk *baud_clk; 247 unsigned int txfifo_size; 248 unsigned int rxfifo_size; 249 250 bool lpuart_dma_tx_use; 251 bool lpuart_dma_rx_use; 252 struct dma_chan *dma_tx_chan; 253 struct dma_chan *dma_rx_chan; 254 struct dma_async_tx_descriptor *dma_tx_desc; 255 struct dma_async_tx_descriptor *dma_rx_desc; 256 dma_cookie_t dma_tx_cookie; 257 dma_cookie_t dma_rx_cookie; 258 unsigned int dma_tx_bytes; 259 unsigned int dma_rx_bytes; 260 bool dma_tx_in_progress; 261 unsigned int dma_rx_timeout; 262 struct timer_list lpuart_timer; 263 struct scatterlist rx_sgl, tx_sgl[2]; 264 struct circ_buf rx_ring; 265 int rx_dma_rng_buf_len; 266 unsigned int dma_tx_nents; 267 wait_queue_head_t dma_wait; 268 bool id_allocated; 269 }; 270 271 struct lpuart_soc_data { 272 enum lpuart_type devtype; 273 char iotype; 274 u8 reg_off; 275 }; 276 277 static const struct lpuart_soc_data vf_data = { 278 .devtype = VF610_LPUART, 279 .iotype = UPIO_MEM, 280 }; 281 282 static const struct lpuart_soc_data ls1021a_data = { 283 .devtype = LS1021A_LPUART, 284 .iotype = UPIO_MEM32BE, 285 }; 286 287 static const struct lpuart_soc_data ls1028a_data = { 288 .devtype = LS1028A_LPUART, 289 .iotype = UPIO_MEM32, 290 }; 291 292 static struct lpuart_soc_data imx7ulp_data = { 293 .devtype = IMX7ULP_LPUART, 294 .iotype = UPIO_MEM32, 295 .reg_off = IMX_REG_OFF, 296 }; 297 298 static struct lpuart_soc_data imx8qxp_data = { 299 .devtype = IMX8QXP_LPUART, 300 .iotype = UPIO_MEM32, 301 .reg_off = IMX_REG_OFF, 302 }; 303 304 static const struct of_device_id lpuart_dt_ids[] = { 305 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 306 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, }, 307 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, }, 308 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, 309 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, 310 { /* sentinel */ } 311 }; 312 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 313 314 /* Forward declare this for the dma callbacks*/ 315 static void lpuart_dma_tx_complete(void *arg); 316 317 static inline bool is_ls1028a_lpuart(struct lpuart_port *sport) 318 { 319 return sport->devtype == LS1028A_LPUART; 320 } 321 322 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) 323 { 324 return sport->devtype == IMX8QXP_LPUART; 325 } 326 327 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 328 { 329 switch (port->iotype) { 330 case UPIO_MEM32: 331 return readl(port->membase + off); 332 case UPIO_MEM32BE: 333 return ioread32be(port->membase + off); 334 default: 335 return 0; 336 } 337 } 338 339 static inline void lpuart32_write(struct uart_port *port, u32 val, 340 u32 off) 341 { 342 switch (port->iotype) { 343 case UPIO_MEM32: 344 writel(val, port->membase + off); 345 break; 346 case UPIO_MEM32BE: 347 iowrite32be(val, port->membase + off); 348 break; 349 } 350 } 351 352 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) 353 { 354 int ret = 0; 355 356 if (is_en) { 357 ret = clk_prepare_enable(sport->ipg_clk); 358 if (ret) 359 return ret; 360 361 ret = clk_prepare_enable(sport->baud_clk); 362 if (ret) { 363 clk_disable_unprepare(sport->ipg_clk); 364 return ret; 365 } 366 } else { 367 clk_disable_unprepare(sport->baud_clk); 368 clk_disable_unprepare(sport->ipg_clk); 369 } 370 371 return 0; 372 } 373 374 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) 375 { 376 if (is_imx8qxp_lpuart(sport)) 377 return clk_get_rate(sport->baud_clk); 378 379 return clk_get_rate(sport->ipg_clk); 380 } 381 382 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true) 383 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false) 384 385 static void lpuart_stop_tx(struct uart_port *port) 386 { 387 unsigned char temp; 388 389 temp = readb(port->membase + UARTCR2); 390 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 391 writeb(temp, port->membase + UARTCR2); 392 } 393 394 static void lpuart32_stop_tx(struct uart_port *port) 395 { 396 unsigned long temp; 397 398 temp = lpuart32_read(port, UARTCTRL); 399 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 400 lpuart32_write(port, temp, UARTCTRL); 401 } 402 403 static void lpuart_stop_rx(struct uart_port *port) 404 { 405 unsigned char temp; 406 407 temp = readb(port->membase + UARTCR2); 408 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 409 } 410 411 static void lpuart32_stop_rx(struct uart_port *port) 412 { 413 unsigned long temp; 414 415 temp = lpuart32_read(port, UARTCTRL); 416 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); 417 } 418 419 static void lpuart_dma_tx(struct lpuart_port *sport) 420 { 421 struct circ_buf *xmit = &sport->port.state->xmit; 422 struct scatterlist *sgl = sport->tx_sgl; 423 struct device *dev = sport->port.dev; 424 struct dma_chan *chan = sport->dma_tx_chan; 425 int ret; 426 427 if (sport->dma_tx_in_progress) 428 return; 429 430 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 431 432 if (xmit->tail < xmit->head || xmit->head == 0) { 433 sport->dma_tx_nents = 1; 434 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 435 } else { 436 sport->dma_tx_nents = 2; 437 sg_init_table(sgl, 2); 438 sg_set_buf(sgl, xmit->buf + xmit->tail, 439 UART_XMIT_SIZE - xmit->tail); 440 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 441 } 442 443 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, 444 DMA_TO_DEVICE); 445 if (!ret) { 446 dev_err(dev, "DMA mapping error for TX.\n"); 447 return; 448 } 449 450 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, 451 ret, DMA_MEM_TO_DEV, 452 DMA_PREP_INTERRUPT); 453 if (!sport->dma_tx_desc) { 454 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 455 DMA_TO_DEVICE); 456 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 457 return; 458 } 459 460 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 461 sport->dma_tx_desc->callback_param = sport; 462 sport->dma_tx_in_progress = true; 463 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 464 dma_async_issue_pending(chan); 465 } 466 467 static bool lpuart_stopped_or_empty(struct uart_port *port) 468 { 469 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); 470 } 471 472 static void lpuart_dma_tx_complete(void *arg) 473 { 474 struct lpuart_port *sport = arg; 475 struct scatterlist *sgl = &sport->tx_sgl[0]; 476 struct circ_buf *xmit = &sport->port.state->xmit; 477 struct dma_chan *chan = sport->dma_tx_chan; 478 unsigned long flags; 479 480 spin_lock_irqsave(&sport->port.lock, flags); 481 482 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 483 DMA_TO_DEVICE); 484 485 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 486 487 sport->port.icount.tx += sport->dma_tx_bytes; 488 sport->dma_tx_in_progress = false; 489 spin_unlock_irqrestore(&sport->port.lock, flags); 490 491 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 492 uart_write_wakeup(&sport->port); 493 494 if (waitqueue_active(&sport->dma_wait)) { 495 wake_up(&sport->dma_wait); 496 return; 497 } 498 499 spin_lock_irqsave(&sport->port.lock, flags); 500 501 if (!lpuart_stopped_or_empty(&sport->port)) 502 lpuart_dma_tx(sport); 503 504 spin_unlock_irqrestore(&sport->port.lock, flags); 505 } 506 507 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) 508 { 509 switch (sport->port.iotype) { 510 case UPIO_MEM32: 511 return sport->port.mapbase + UARTDATA; 512 case UPIO_MEM32BE: 513 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; 514 } 515 return sport->port.mapbase + UARTDR; 516 } 517 518 static int lpuart_dma_tx_request(struct uart_port *port) 519 { 520 struct lpuart_port *sport = container_of(port, 521 struct lpuart_port, port); 522 struct dma_slave_config dma_tx_sconfig = {}; 523 int ret; 524 525 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); 526 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 527 dma_tx_sconfig.dst_maxburst = 1; 528 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 529 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 530 531 if (ret) { 532 dev_err(sport->port.dev, 533 "DMA slave config failed, err = %d\n", ret); 534 return ret; 535 } 536 537 return 0; 538 } 539 540 static bool lpuart_is_32(struct lpuart_port *sport) 541 { 542 return sport->port.iotype == UPIO_MEM32 || 543 sport->port.iotype == UPIO_MEM32BE; 544 } 545 546 static void lpuart_flush_buffer(struct uart_port *port) 547 { 548 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 549 struct dma_chan *chan = sport->dma_tx_chan; 550 u32 val; 551 552 if (sport->lpuart_dma_tx_use) { 553 if (sport->dma_tx_in_progress) { 554 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], 555 sport->dma_tx_nents, DMA_TO_DEVICE); 556 sport->dma_tx_in_progress = false; 557 } 558 dmaengine_terminate_all(chan); 559 } 560 561 if (lpuart_is_32(sport)) { 562 val = lpuart32_read(&sport->port, UARTFIFO); 563 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 564 lpuart32_write(&sport->port, val, UARTFIFO); 565 } else { 566 val = readb(sport->port.membase + UARTCFIFO); 567 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; 568 writeb(val, sport->port.membase + UARTCFIFO); 569 } 570 } 571 572 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset, 573 u8 bit) 574 { 575 while (!(readb(port->membase + offset) & bit)) 576 cpu_relax(); 577 } 578 579 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset, 580 u32 bit) 581 { 582 while (!(lpuart32_read(port, offset) & bit)) 583 cpu_relax(); 584 } 585 586 #if defined(CONFIG_CONSOLE_POLL) 587 588 static int lpuart_poll_init(struct uart_port *port) 589 { 590 struct lpuart_port *sport = container_of(port, 591 struct lpuart_port, port); 592 unsigned long flags; 593 unsigned char temp; 594 595 sport->port.fifosize = 0; 596 597 spin_lock_irqsave(&sport->port.lock, flags); 598 /* Disable Rx & Tx */ 599 writeb(0, sport->port.membase + UARTCR2); 600 601 temp = readb(sport->port.membase + UARTPFIFO); 602 /* Enable Rx and Tx FIFO */ 603 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 604 sport->port.membase + UARTPFIFO); 605 606 /* flush Tx and Rx FIFO */ 607 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 608 sport->port.membase + UARTCFIFO); 609 610 /* explicitly clear RDRF */ 611 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 612 readb(sport->port.membase + UARTDR); 613 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 614 } 615 616 writeb(0, sport->port.membase + UARTTWFIFO); 617 writeb(1, sport->port.membase + UARTRWFIFO); 618 619 /* Enable Rx and Tx */ 620 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 621 spin_unlock_irqrestore(&sport->port.lock, flags); 622 623 return 0; 624 } 625 626 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 627 { 628 /* drain */ 629 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 630 writeb(c, port->membase + UARTDR); 631 } 632 633 static int lpuart_poll_get_char(struct uart_port *port) 634 { 635 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 636 return NO_POLL_CHAR; 637 638 return readb(port->membase + UARTDR); 639 } 640 641 static int lpuart32_poll_init(struct uart_port *port) 642 { 643 unsigned long flags; 644 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 645 u32 temp; 646 647 sport->port.fifosize = 0; 648 649 spin_lock_irqsave(&sport->port.lock, flags); 650 651 /* Disable Rx & Tx */ 652 lpuart32_write(&sport->port, 0, UARTCTRL); 653 654 temp = lpuart32_read(&sport->port, UARTFIFO); 655 656 /* Enable Rx and Tx FIFO */ 657 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); 658 659 /* flush Tx and Rx FIFO */ 660 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); 661 662 /* explicitly clear RDRF */ 663 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { 664 lpuart32_read(&sport->port, UARTDATA); 665 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); 666 } 667 668 /* Enable Rx and Tx */ 669 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); 670 spin_unlock_irqrestore(&sport->port.lock, flags); 671 672 return 0; 673 } 674 675 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 676 { 677 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 678 lpuart32_write(port, c, UARTDATA); 679 } 680 681 static int lpuart32_poll_get_char(struct uart_port *port) 682 { 683 if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF)) 684 return NO_POLL_CHAR; 685 686 return lpuart32_read(port, UARTDATA); 687 } 688 #endif 689 690 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 691 { 692 struct circ_buf *xmit = &sport->port.state->xmit; 693 694 if (sport->port.x_char) { 695 writeb(sport->port.x_char, sport->port.membase + UARTDR); 696 sport->port.icount.tx++; 697 sport->port.x_char = 0; 698 return; 699 } 700 701 if (lpuart_stopped_or_empty(&sport->port)) { 702 lpuart_stop_tx(&sport->port); 703 return; 704 } 705 706 while (!uart_circ_empty(xmit) && 707 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 708 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 709 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 710 sport->port.icount.tx++; 711 } 712 713 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 714 uart_write_wakeup(&sport->port); 715 716 if (uart_circ_empty(xmit)) 717 lpuart_stop_tx(&sport->port); 718 } 719 720 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 721 { 722 struct circ_buf *xmit = &sport->port.state->xmit; 723 unsigned long txcnt; 724 725 if (sport->port.x_char) { 726 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 727 sport->port.icount.tx++; 728 sport->port.x_char = 0; 729 return; 730 } 731 732 if (lpuart_stopped_or_empty(&sport->port)) { 733 lpuart32_stop_tx(&sport->port); 734 return; 735 } 736 737 txcnt = lpuart32_read(&sport->port, UARTWATER); 738 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 739 txcnt &= UARTWATER_COUNT_MASK; 740 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 741 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); 742 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 743 sport->port.icount.tx++; 744 txcnt = lpuart32_read(&sport->port, UARTWATER); 745 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 746 txcnt &= UARTWATER_COUNT_MASK; 747 } 748 749 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 750 uart_write_wakeup(&sport->port); 751 752 if (uart_circ_empty(xmit)) 753 lpuart32_stop_tx(&sport->port); 754 } 755 756 static void lpuart_start_tx(struct uart_port *port) 757 { 758 struct lpuart_port *sport = container_of(port, 759 struct lpuart_port, port); 760 unsigned char temp; 761 762 temp = readb(port->membase + UARTCR2); 763 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 764 765 if (sport->lpuart_dma_tx_use) { 766 if (!lpuart_stopped_or_empty(port)) 767 lpuart_dma_tx(sport); 768 } else { 769 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 770 lpuart_transmit_buffer(sport); 771 } 772 } 773 774 static void lpuart32_start_tx(struct uart_port *port) 775 { 776 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 777 unsigned long temp; 778 779 if (sport->lpuart_dma_tx_use) { 780 if (!lpuart_stopped_or_empty(port)) 781 lpuart_dma_tx(sport); 782 } else { 783 temp = lpuart32_read(port, UARTCTRL); 784 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); 785 786 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 787 lpuart32_transmit_buffer(sport); 788 } 789 } 790 791 /* return TIOCSER_TEMT when transmitter is not busy */ 792 static unsigned int lpuart_tx_empty(struct uart_port *port) 793 { 794 struct lpuart_port *sport = container_of(port, 795 struct lpuart_port, port); 796 unsigned char sr1 = readb(port->membase + UARTSR1); 797 unsigned char sfifo = readb(port->membase + UARTSFIFO); 798 799 if (sport->dma_tx_in_progress) 800 return 0; 801 802 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 803 return TIOCSER_TEMT; 804 805 return 0; 806 } 807 808 static unsigned int lpuart32_tx_empty(struct uart_port *port) 809 { 810 struct lpuart_port *sport = container_of(port, 811 struct lpuart_port, port); 812 unsigned long stat = lpuart32_read(port, UARTSTAT); 813 unsigned long sfifo = lpuart32_read(port, UARTFIFO); 814 815 if (sport->dma_tx_in_progress) 816 return 0; 817 818 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) 819 return TIOCSER_TEMT; 820 821 return 0; 822 } 823 824 static void lpuart_txint(struct lpuart_port *sport) 825 { 826 unsigned long flags; 827 828 spin_lock_irqsave(&sport->port.lock, flags); 829 lpuart_transmit_buffer(sport); 830 spin_unlock_irqrestore(&sport->port.lock, flags); 831 } 832 833 static void lpuart_rxint(struct lpuart_port *sport) 834 { 835 unsigned int flg, ignored = 0, overrun = 0; 836 struct tty_port *port = &sport->port.state->port; 837 unsigned long flags; 838 unsigned char rx, sr; 839 840 spin_lock_irqsave(&sport->port.lock, flags); 841 842 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 843 flg = TTY_NORMAL; 844 sport->port.icount.rx++; 845 /* 846 * to clear the FE, OR, NF, FE, PE flags, 847 * read SR1 then read DR 848 */ 849 sr = readb(sport->port.membase + UARTSR1); 850 rx = readb(sport->port.membase + UARTDR); 851 852 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 853 continue; 854 855 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 856 if (sr & UARTSR1_PE) 857 sport->port.icount.parity++; 858 else if (sr & UARTSR1_FE) 859 sport->port.icount.frame++; 860 861 if (sr & UARTSR1_OR) 862 overrun++; 863 864 if (sr & sport->port.ignore_status_mask) { 865 if (++ignored > 100) 866 goto out; 867 continue; 868 } 869 870 sr &= sport->port.read_status_mask; 871 872 if (sr & UARTSR1_PE) 873 flg = TTY_PARITY; 874 else if (sr & UARTSR1_FE) 875 flg = TTY_FRAME; 876 877 if (sr & UARTSR1_OR) 878 flg = TTY_OVERRUN; 879 880 sport->port.sysrq = 0; 881 } 882 883 tty_insert_flip_char(port, rx, flg); 884 } 885 886 out: 887 if (overrun) { 888 sport->port.icount.overrun += overrun; 889 890 /* 891 * Overruns cause FIFO pointers to become missaligned. 892 * Flushing the receive FIFO reinitializes the pointers. 893 */ 894 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 895 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); 896 } 897 898 spin_unlock_irqrestore(&sport->port.lock, flags); 899 900 tty_flip_buffer_push(port); 901 } 902 903 static void lpuart32_txint(struct lpuart_port *sport) 904 { 905 unsigned long flags; 906 907 spin_lock_irqsave(&sport->port.lock, flags); 908 lpuart32_transmit_buffer(sport); 909 spin_unlock_irqrestore(&sport->port.lock, flags); 910 } 911 912 static void lpuart32_rxint(struct lpuart_port *sport) 913 { 914 unsigned int flg, ignored = 0; 915 struct tty_port *port = &sport->port.state->port; 916 unsigned long flags; 917 unsigned long rx, sr; 918 919 spin_lock_irqsave(&sport->port.lock, flags); 920 921 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 922 flg = TTY_NORMAL; 923 sport->port.icount.rx++; 924 /* 925 * to clear the FE, OR, NF, FE, PE flags, 926 * read STAT then read DATA reg 927 */ 928 sr = lpuart32_read(&sport->port, UARTSTAT); 929 rx = lpuart32_read(&sport->port, UARTDATA); 930 rx &= 0x3ff; 931 932 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 933 continue; 934 935 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 936 if (sr & UARTSTAT_PE) 937 sport->port.icount.parity++; 938 else if (sr & UARTSTAT_FE) 939 sport->port.icount.frame++; 940 941 if (sr & UARTSTAT_OR) 942 sport->port.icount.overrun++; 943 944 if (sr & sport->port.ignore_status_mask) { 945 if (++ignored > 100) 946 goto out; 947 continue; 948 } 949 950 sr &= sport->port.read_status_mask; 951 952 if (sr & UARTSTAT_PE) 953 flg = TTY_PARITY; 954 else if (sr & UARTSTAT_FE) 955 flg = TTY_FRAME; 956 957 if (sr & UARTSTAT_OR) 958 flg = TTY_OVERRUN; 959 960 sport->port.sysrq = 0; 961 } 962 963 tty_insert_flip_char(port, rx, flg); 964 } 965 966 out: 967 spin_unlock_irqrestore(&sport->port.lock, flags); 968 969 tty_flip_buffer_push(port); 970 } 971 972 static irqreturn_t lpuart_int(int irq, void *dev_id) 973 { 974 struct lpuart_port *sport = dev_id; 975 unsigned char sts; 976 977 sts = readb(sport->port.membase + UARTSR1); 978 979 /* SysRq, using dma, check for linebreak by framing err. */ 980 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { 981 readb(sport->port.membase + UARTDR); 982 uart_handle_break(&sport->port); 983 /* linebreak produces some garbage, removing it */ 984 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 985 return IRQ_HANDLED; 986 } 987 988 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) 989 lpuart_rxint(sport); 990 991 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) 992 lpuart_txint(sport); 993 994 return IRQ_HANDLED; 995 } 996 997 static irqreturn_t lpuart32_int(int irq, void *dev_id) 998 { 999 struct lpuart_port *sport = dev_id; 1000 unsigned long sts, rxcount; 1001 1002 sts = lpuart32_read(&sport->port, UARTSTAT); 1003 rxcount = lpuart32_read(&sport->port, UARTWATER); 1004 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 1005 1006 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) 1007 lpuart32_rxint(sport); 1008 1009 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) 1010 lpuart32_txint(sport); 1011 1012 lpuart32_write(&sport->port, sts, UARTSTAT); 1013 return IRQ_HANDLED; 1014 } 1015 1016 1017 static inline void lpuart_handle_sysrq_chars(struct uart_port *port, 1018 unsigned char *p, int count) 1019 { 1020 while (count--) { 1021 if (*p && uart_handle_sysrq_char(port, *p)) 1022 return; 1023 p++; 1024 } 1025 } 1026 1027 static void lpuart_handle_sysrq(struct lpuart_port *sport) 1028 { 1029 struct circ_buf *ring = &sport->rx_ring; 1030 int count; 1031 1032 if (ring->head < ring->tail) { 1033 count = sport->rx_sgl.length - ring->tail; 1034 lpuart_handle_sysrq_chars(&sport->port, 1035 ring->buf + ring->tail, count); 1036 ring->tail = 0; 1037 } 1038 1039 if (ring->head > ring->tail) { 1040 count = ring->head - ring->tail; 1041 lpuart_handle_sysrq_chars(&sport->port, 1042 ring->buf + ring->tail, count); 1043 ring->tail = ring->head; 1044 } 1045 } 1046 1047 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 1048 { 1049 struct tty_port *port = &sport->port.state->port; 1050 struct dma_tx_state state; 1051 enum dma_status dmastat; 1052 struct dma_chan *chan = sport->dma_rx_chan; 1053 struct circ_buf *ring = &sport->rx_ring; 1054 unsigned long flags; 1055 int count = 0; 1056 1057 if (lpuart_is_32(sport)) { 1058 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); 1059 1060 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { 1061 /* Read DR to clear the error flags */ 1062 lpuart32_read(&sport->port, UARTDATA); 1063 1064 if (sr & UARTSTAT_PE) 1065 sport->port.icount.parity++; 1066 else if (sr & UARTSTAT_FE) 1067 sport->port.icount.frame++; 1068 } 1069 } else { 1070 unsigned char sr = readb(sport->port.membase + UARTSR1); 1071 1072 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 1073 unsigned char cr2; 1074 1075 /* Disable receiver during this operation... */ 1076 cr2 = readb(sport->port.membase + UARTCR2); 1077 cr2 &= ~UARTCR2_RE; 1078 writeb(cr2, sport->port.membase + UARTCR2); 1079 1080 /* Read DR to clear the error flags */ 1081 readb(sport->port.membase + UARTDR); 1082 1083 if (sr & UARTSR1_PE) 1084 sport->port.icount.parity++; 1085 else if (sr & UARTSR1_FE) 1086 sport->port.icount.frame++; 1087 /* 1088 * At this point parity/framing error is 1089 * cleared However, since the DMA already read 1090 * the data register and we had to read it 1091 * again after reading the status register to 1092 * properly clear the flags, the FIFO actually 1093 * underflowed... This requires a clearing of 1094 * the FIFO... 1095 */ 1096 if (readb(sport->port.membase + UARTSFIFO) & 1097 UARTSFIFO_RXUF) { 1098 writeb(UARTSFIFO_RXUF, 1099 sport->port.membase + UARTSFIFO); 1100 writeb(UARTCFIFO_RXFLUSH, 1101 sport->port.membase + UARTCFIFO); 1102 } 1103 1104 cr2 |= UARTCR2_RE; 1105 writeb(cr2, sport->port.membase + UARTCR2); 1106 } 1107 } 1108 1109 async_tx_ack(sport->dma_rx_desc); 1110 1111 spin_lock_irqsave(&sport->port.lock, flags); 1112 1113 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1114 if (dmastat == DMA_ERROR) { 1115 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1116 spin_unlock_irqrestore(&sport->port.lock, flags); 1117 return; 1118 } 1119 1120 /* CPU claims ownership of RX DMA buffer */ 1121 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, 1122 DMA_FROM_DEVICE); 1123 1124 /* 1125 * ring->head points to the end of data already written by the DMA. 1126 * ring->tail points to the beginning of data to be read by the 1127 * framework. 1128 * The current transfer size should not be larger than the dma buffer 1129 * length. 1130 */ 1131 ring->head = sport->rx_sgl.length - state.residue; 1132 BUG_ON(ring->head > sport->rx_sgl.length); 1133 1134 /* 1135 * Silent handling of keys pressed in the sysrq timeframe 1136 */ 1137 if (sport->port.sysrq) { 1138 lpuart_handle_sysrq(sport); 1139 goto exit; 1140 } 1141 1142 /* 1143 * At this point ring->head may point to the first byte right after the 1144 * last byte of the dma buffer: 1145 * 0 <= ring->head <= sport->rx_sgl.length 1146 * 1147 * However ring->tail must always points inside the dma buffer: 1148 * 0 <= ring->tail <= sport->rx_sgl.length - 1 1149 * 1150 * Since we use a ring buffer, we have to handle the case 1151 * where head is lower than tail. In such a case, we first read from 1152 * tail to the end of the buffer then reset tail. 1153 */ 1154 if (ring->head < ring->tail) { 1155 count = sport->rx_sgl.length - ring->tail; 1156 1157 tty_insert_flip_string(port, ring->buf + ring->tail, count); 1158 ring->tail = 0; 1159 sport->port.icount.rx += count; 1160 } 1161 1162 /* Finally we read data from tail to head */ 1163 if (ring->tail < ring->head) { 1164 count = ring->head - ring->tail; 1165 tty_insert_flip_string(port, ring->buf + ring->tail, count); 1166 /* Wrap ring->head if needed */ 1167 if (ring->head >= sport->rx_sgl.length) 1168 ring->head = 0; 1169 ring->tail = ring->head; 1170 sport->port.icount.rx += count; 1171 } 1172 1173 exit: 1174 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, 1175 DMA_FROM_DEVICE); 1176 1177 spin_unlock_irqrestore(&sport->port.lock, flags); 1178 1179 tty_flip_buffer_push(port); 1180 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 1181 } 1182 1183 static void lpuart_dma_rx_complete(void *arg) 1184 { 1185 struct lpuart_port *sport = arg; 1186 1187 lpuart_copy_rx_to_tty(sport); 1188 } 1189 1190 static void lpuart_timer_func(struct timer_list *t) 1191 { 1192 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); 1193 1194 lpuart_copy_rx_to_tty(sport); 1195 } 1196 1197 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 1198 { 1199 struct dma_slave_config dma_rx_sconfig = {}; 1200 struct circ_buf *ring = &sport->rx_ring; 1201 int ret, nent; 1202 int bits, baud; 1203 struct tty_port *port = &sport->port.state->port; 1204 struct tty_struct *tty = port->tty; 1205 struct ktermios *termios = &tty->termios; 1206 struct dma_chan *chan = sport->dma_rx_chan; 1207 1208 baud = tty_get_baud_rate(tty); 1209 1210 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; 1211 if (termios->c_cflag & PARENB) 1212 bits++; 1213 1214 /* 1215 * Calculate length of one DMA buffer size to keep latency below 1216 * 10ms at any baud rate. 1217 */ 1218 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 1219 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 1220 if (sport->rx_dma_rng_buf_len < 16) 1221 sport->rx_dma_rng_buf_len = 16; 1222 1223 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1224 if (!ring->buf) 1225 return -ENOMEM; 1226 1227 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1228 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, 1229 DMA_FROM_DEVICE); 1230 1231 if (!nent) { 1232 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1233 return -EINVAL; 1234 } 1235 1236 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); 1237 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1238 dma_rx_sconfig.src_maxburst = 1; 1239 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1240 ret = dmaengine_slave_config(chan, &dma_rx_sconfig); 1241 1242 if (ret < 0) { 1243 dev_err(sport->port.dev, 1244 "DMA Rx slave config failed, err = %d\n", ret); 1245 return ret; 1246 } 1247 1248 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, 1249 sg_dma_address(&sport->rx_sgl), 1250 sport->rx_sgl.length, 1251 sport->rx_sgl.length / 2, 1252 DMA_DEV_TO_MEM, 1253 DMA_PREP_INTERRUPT); 1254 if (!sport->dma_rx_desc) { 1255 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1256 return -EFAULT; 1257 } 1258 1259 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1260 sport->dma_rx_desc->callback_param = sport; 1261 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1262 dma_async_issue_pending(chan); 1263 1264 if (lpuart_is_32(sport)) { 1265 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); 1266 1267 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); 1268 } else { 1269 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1270 sport->port.membase + UARTCR5); 1271 } 1272 1273 return 0; 1274 } 1275 1276 static void lpuart_dma_rx_free(struct uart_port *port) 1277 { 1278 struct lpuart_port *sport = container_of(port, 1279 struct lpuart_port, port); 1280 struct dma_chan *chan = sport->dma_rx_chan; 1281 1282 dmaengine_terminate_all(chan); 1283 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1284 kfree(sport->rx_ring.buf); 1285 sport->rx_ring.tail = 0; 1286 sport->rx_ring.head = 0; 1287 sport->dma_rx_desc = NULL; 1288 sport->dma_rx_cookie = -EINVAL; 1289 } 1290 1291 static int lpuart_config_rs485(struct uart_port *port, 1292 struct serial_rs485 *rs485) 1293 { 1294 struct lpuart_port *sport = container_of(port, 1295 struct lpuart_port, port); 1296 1297 u8 modem = readb(sport->port.membase + UARTMODEM) & 1298 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1299 writeb(modem, sport->port.membase + UARTMODEM); 1300 1301 /* clear unsupported configurations */ 1302 rs485->delay_rts_before_send = 0; 1303 rs485->delay_rts_after_send = 0; 1304 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1305 1306 if (rs485->flags & SER_RS485_ENABLED) { 1307 /* Enable auto RS-485 RTS mode */ 1308 modem |= UARTMODEM_TXRTSE; 1309 1310 /* 1311 * RTS needs to be logic HIGH either during transfer _or_ after 1312 * transfer, other variants are not supported by the hardware. 1313 */ 1314 1315 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1316 SER_RS485_RTS_AFTER_SEND))) 1317 rs485->flags |= SER_RS485_RTS_ON_SEND; 1318 1319 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1320 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1321 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1322 1323 /* 1324 * The hardware defaults to RTS logic HIGH while transfer. 1325 * Switch polarity in case RTS shall be logic HIGH 1326 * after transfer. 1327 * Note: UART is assumed to be active high. 1328 */ 1329 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1330 modem &= ~UARTMODEM_TXRTSPOL; 1331 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1332 modem |= UARTMODEM_TXRTSPOL; 1333 } 1334 1335 /* Store the new configuration */ 1336 sport->port.rs485 = *rs485; 1337 1338 writeb(modem, sport->port.membase + UARTMODEM); 1339 return 0; 1340 } 1341 1342 static int lpuart32_config_rs485(struct uart_port *port, 1343 struct serial_rs485 *rs485) 1344 { 1345 struct lpuart_port *sport = container_of(port, 1346 struct lpuart_port, port); 1347 1348 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) 1349 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1350 lpuart32_write(&sport->port, modem, UARTMODIR); 1351 1352 /* clear unsupported configurations */ 1353 rs485->delay_rts_before_send = 0; 1354 rs485->delay_rts_after_send = 0; 1355 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1356 1357 if (rs485->flags & SER_RS485_ENABLED) { 1358 /* Enable auto RS-485 RTS mode */ 1359 modem |= UARTMODEM_TXRTSE; 1360 1361 /* 1362 * RTS needs to be logic HIGH either during transfer _or_ after 1363 * transfer, other variants are not supported by the hardware. 1364 */ 1365 1366 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1367 SER_RS485_RTS_AFTER_SEND))) 1368 rs485->flags |= SER_RS485_RTS_ON_SEND; 1369 1370 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1371 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1372 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1373 1374 /* 1375 * The hardware defaults to RTS logic HIGH while transfer. 1376 * Switch polarity in case RTS shall be logic HIGH 1377 * after transfer. 1378 * Note: UART is assumed to be active high. 1379 */ 1380 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1381 modem &= ~UARTMODEM_TXRTSPOL; 1382 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1383 modem |= UARTMODEM_TXRTSPOL; 1384 } 1385 1386 /* Store the new configuration */ 1387 sport->port.rs485 = *rs485; 1388 1389 lpuart32_write(&sport->port, modem, UARTMODIR); 1390 return 0; 1391 } 1392 1393 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1394 { 1395 unsigned int temp = 0; 1396 unsigned char reg; 1397 1398 reg = readb(port->membase + UARTMODEM); 1399 if (reg & UARTMODEM_TXCTSE) 1400 temp |= TIOCM_CTS; 1401 1402 if (reg & UARTMODEM_RXRTSE) 1403 temp |= TIOCM_RTS; 1404 1405 return temp; 1406 } 1407 1408 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1409 { 1410 unsigned int temp = 0; 1411 unsigned long reg; 1412 1413 reg = lpuart32_read(port, UARTMODIR); 1414 if (reg & UARTMODIR_TXCTSE) 1415 temp |= TIOCM_CTS; 1416 1417 if (reg & UARTMODIR_RXRTSE) 1418 temp |= TIOCM_RTS; 1419 1420 return temp; 1421 } 1422 1423 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1424 { 1425 unsigned char temp; 1426 struct lpuart_port *sport = container_of(port, 1427 struct lpuart_port, port); 1428 1429 /* Make sure RXRTSE bit is not set when RS485 is enabled */ 1430 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { 1431 temp = readb(sport->port.membase + UARTMODEM) & 1432 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1433 1434 if (mctrl & TIOCM_RTS) 1435 temp |= UARTMODEM_RXRTSE; 1436 1437 if (mctrl & TIOCM_CTS) 1438 temp |= UARTMODEM_TXCTSE; 1439 1440 writeb(temp, port->membase + UARTMODEM); 1441 } 1442 } 1443 1444 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1445 { 1446 1447 } 1448 1449 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1450 { 1451 unsigned char temp; 1452 1453 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1454 1455 if (break_state != 0) 1456 temp |= UARTCR2_SBK; 1457 1458 writeb(temp, port->membase + UARTCR2); 1459 } 1460 1461 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1462 { 1463 unsigned long temp; 1464 1465 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; 1466 1467 if (break_state != 0) 1468 temp |= UARTCTRL_SBK; 1469 1470 lpuart32_write(port, temp, UARTCTRL); 1471 } 1472 1473 static void lpuart_setup_watermark(struct lpuart_port *sport) 1474 { 1475 unsigned char val, cr2; 1476 unsigned char cr2_saved; 1477 1478 cr2 = readb(sport->port.membase + UARTCR2); 1479 cr2_saved = cr2; 1480 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1481 UARTCR2_RIE | UARTCR2_RE); 1482 writeb(cr2, sport->port.membase + UARTCR2); 1483 1484 val = readb(sport->port.membase + UARTPFIFO); 1485 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1486 sport->port.membase + UARTPFIFO); 1487 1488 /* flush Tx and Rx FIFO */ 1489 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1490 sport->port.membase + UARTCFIFO); 1491 1492 /* explicitly clear RDRF */ 1493 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1494 readb(sport->port.membase + UARTDR); 1495 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1496 } 1497 1498 writeb(0, sport->port.membase + UARTTWFIFO); 1499 writeb(1, sport->port.membase + UARTRWFIFO); 1500 1501 /* Restore cr2 */ 1502 writeb(cr2_saved, sport->port.membase + UARTCR2); 1503 } 1504 1505 static void lpuart_setup_watermark_enable(struct lpuart_port *sport) 1506 { 1507 unsigned char cr2; 1508 1509 lpuart_setup_watermark(sport); 1510 1511 cr2 = readb(sport->port.membase + UARTCR2); 1512 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE; 1513 writeb(cr2, sport->port.membase + UARTCR2); 1514 } 1515 1516 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1517 { 1518 unsigned long val, ctrl; 1519 unsigned long ctrl_saved; 1520 1521 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1522 ctrl_saved = ctrl; 1523 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1524 UARTCTRL_RIE | UARTCTRL_RE); 1525 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1526 1527 /* enable FIFO mode */ 1528 val = lpuart32_read(&sport->port, UARTFIFO); 1529 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1530 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1531 lpuart32_write(&sport->port, val, UARTFIFO); 1532 1533 /* set the watermark */ 1534 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1535 lpuart32_write(&sport->port, val, UARTWATER); 1536 1537 /* Restore cr2 */ 1538 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1539 } 1540 1541 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) 1542 { 1543 u32 temp; 1544 1545 lpuart32_setup_watermark(sport); 1546 1547 temp = lpuart32_read(&sport->port, UARTCTRL); 1548 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE; 1549 lpuart32_write(&sport->port, temp, UARTCTRL); 1550 } 1551 1552 static void rx_dma_timer_init(struct lpuart_port *sport) 1553 { 1554 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); 1555 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1556 add_timer(&sport->lpuart_timer); 1557 } 1558 1559 static void lpuart_request_dma(struct lpuart_port *sport) 1560 { 1561 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); 1562 if (IS_ERR(sport->dma_tx_chan)) { 1563 dev_dbg_once(sport->port.dev, 1564 "DMA tx channel request failed, operating without tx DMA (%ld)\n", 1565 PTR_ERR(sport->dma_tx_chan)); 1566 sport->dma_tx_chan = NULL; 1567 } 1568 1569 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); 1570 if (IS_ERR(sport->dma_rx_chan)) { 1571 dev_dbg_once(sport->port.dev, 1572 "DMA rx channel request failed, operating without rx DMA (%ld)\n", 1573 PTR_ERR(sport->dma_rx_chan)); 1574 sport->dma_rx_chan = NULL; 1575 } 1576 } 1577 1578 static void lpuart_tx_dma_startup(struct lpuart_port *sport) 1579 { 1580 u32 uartbaud; 1581 int ret; 1582 1583 if (!sport->dma_tx_chan) 1584 goto err; 1585 1586 ret = lpuart_dma_tx_request(&sport->port); 1587 if (ret) 1588 goto err; 1589 1590 init_waitqueue_head(&sport->dma_wait); 1591 sport->lpuart_dma_tx_use = true; 1592 if (lpuart_is_32(sport)) { 1593 uartbaud = lpuart32_read(&sport->port, UARTBAUD); 1594 lpuart32_write(&sport->port, 1595 uartbaud | UARTBAUD_TDMAE, UARTBAUD); 1596 } else { 1597 writeb(readb(sport->port.membase + UARTCR5) | 1598 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 1599 } 1600 1601 return; 1602 1603 err: 1604 sport->lpuart_dma_tx_use = false; 1605 } 1606 1607 static void lpuart_rx_dma_startup(struct lpuart_port *sport) 1608 { 1609 int ret; 1610 unsigned char cr3; 1611 1612 if (!sport->dma_rx_chan) 1613 goto err; 1614 1615 ret = lpuart_start_rx_dma(sport); 1616 if (ret) 1617 goto err; 1618 1619 /* set Rx DMA timeout */ 1620 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1621 if (!sport->dma_rx_timeout) 1622 sport->dma_rx_timeout = 1; 1623 1624 sport->lpuart_dma_rx_use = true; 1625 rx_dma_timer_init(sport); 1626 1627 if (sport->port.has_sysrq) { 1628 cr3 = readb(sport->port.membase + UARTCR3); 1629 cr3 |= UARTCR3_FEIE; 1630 writeb(cr3, sport->port.membase + UARTCR3); 1631 } 1632 1633 return; 1634 1635 err: 1636 sport->lpuart_dma_rx_use = false; 1637 } 1638 1639 static int lpuart_startup(struct uart_port *port) 1640 { 1641 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1642 unsigned long flags; 1643 unsigned char temp; 1644 1645 /* determine FIFO size and enable FIFO mode */ 1646 temp = readb(sport->port.membase + UARTPFIFO); 1647 1648 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & 1649 UARTPFIFO_FIFOSIZE_MASK); 1650 sport->port.fifosize = sport->txfifo_size; 1651 1652 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & 1653 UARTPFIFO_FIFOSIZE_MASK); 1654 1655 lpuart_request_dma(sport); 1656 1657 spin_lock_irqsave(&sport->port.lock, flags); 1658 1659 lpuart_setup_watermark_enable(sport); 1660 1661 lpuart_rx_dma_startup(sport); 1662 lpuart_tx_dma_startup(sport); 1663 1664 spin_unlock_irqrestore(&sport->port.lock, flags); 1665 1666 return 0; 1667 } 1668 1669 static void lpuart32_configure(struct lpuart_port *sport) 1670 { 1671 unsigned long temp; 1672 1673 if (sport->lpuart_dma_rx_use) { 1674 /* RXWATER must be 0 */ 1675 temp = lpuart32_read(&sport->port, UARTWATER); 1676 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF); 1677 lpuart32_write(&sport->port, temp, UARTWATER); 1678 } 1679 temp = lpuart32_read(&sport->port, UARTCTRL); 1680 if (!sport->lpuart_dma_rx_use) 1681 temp |= UARTCTRL_RIE; 1682 if (!sport->lpuart_dma_tx_use) 1683 temp |= UARTCTRL_TIE; 1684 lpuart32_write(&sport->port, temp, UARTCTRL); 1685 } 1686 1687 static int lpuart32_startup(struct uart_port *port) 1688 { 1689 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1690 unsigned long flags; 1691 unsigned long temp; 1692 1693 /* determine FIFO size */ 1694 temp = lpuart32_read(&sport->port, UARTFIFO); 1695 1696 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & 1697 UARTFIFO_FIFOSIZE_MASK); 1698 sport->port.fifosize = sport->txfifo_size; 1699 1700 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & 1701 UARTFIFO_FIFOSIZE_MASK); 1702 1703 /* 1704 * The LS1028A has a fixed length of 16 words. Although it supports the 1705 * RX/TXSIZE fields their encoding is different. Eg the reference manual 1706 * states 0b101 is 16 words. 1707 */ 1708 if (is_ls1028a_lpuart(sport)) { 1709 sport->rxfifo_size = 16; 1710 sport->txfifo_size = 16; 1711 sport->port.fifosize = sport->txfifo_size; 1712 } 1713 1714 lpuart_request_dma(sport); 1715 1716 spin_lock_irqsave(&sport->port.lock, flags); 1717 1718 lpuart32_setup_watermark_enable(sport); 1719 1720 lpuart_rx_dma_startup(sport); 1721 lpuart_tx_dma_startup(sport); 1722 1723 lpuart32_configure(sport); 1724 1725 spin_unlock_irqrestore(&sport->port.lock, flags); 1726 return 0; 1727 } 1728 1729 static void lpuart_dma_shutdown(struct lpuart_port *sport) 1730 { 1731 if (sport->lpuart_dma_rx_use) { 1732 del_timer_sync(&sport->lpuart_timer); 1733 lpuart_dma_rx_free(&sport->port); 1734 } 1735 1736 if (sport->lpuart_dma_tx_use) { 1737 if (wait_event_interruptible(sport->dma_wait, 1738 !sport->dma_tx_in_progress) != false) { 1739 sport->dma_tx_in_progress = false; 1740 dmaengine_terminate_all(sport->dma_tx_chan); 1741 } 1742 } 1743 1744 if (sport->dma_tx_chan) 1745 dma_release_channel(sport->dma_tx_chan); 1746 if (sport->dma_rx_chan) 1747 dma_release_channel(sport->dma_rx_chan); 1748 } 1749 1750 static void lpuart_shutdown(struct uart_port *port) 1751 { 1752 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1753 unsigned char temp; 1754 unsigned long flags; 1755 1756 spin_lock_irqsave(&port->lock, flags); 1757 1758 /* disable Rx/Tx and interrupts */ 1759 temp = readb(port->membase + UARTCR2); 1760 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1761 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1762 writeb(temp, port->membase + UARTCR2); 1763 1764 spin_unlock_irqrestore(&port->lock, flags); 1765 1766 lpuart_dma_shutdown(sport); 1767 } 1768 1769 static void lpuart32_shutdown(struct uart_port *port) 1770 { 1771 struct lpuart_port *sport = 1772 container_of(port, struct lpuart_port, port); 1773 unsigned long temp; 1774 unsigned long flags; 1775 1776 spin_lock_irqsave(&port->lock, flags); 1777 1778 /* disable Rx/Tx and interrupts */ 1779 temp = lpuart32_read(port, UARTCTRL); 1780 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1781 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1782 lpuart32_write(port, temp, UARTCTRL); 1783 1784 spin_unlock_irqrestore(&port->lock, flags); 1785 1786 lpuart_dma_shutdown(sport); 1787 } 1788 1789 static void 1790 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1791 struct ktermios *old) 1792 { 1793 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1794 unsigned long flags; 1795 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1796 unsigned int baud; 1797 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1798 unsigned int sbr, brfa; 1799 1800 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1801 old_cr2 = readb(sport->port.membase + UARTCR2); 1802 cr3 = readb(sport->port.membase + UARTCR3); 1803 cr4 = readb(sport->port.membase + UARTCR4); 1804 bdh = readb(sport->port.membase + UARTBDH); 1805 modem = readb(sport->port.membase + UARTMODEM); 1806 /* 1807 * only support CS8 and CS7, and for CS7 must enable PE. 1808 * supported mode: 1809 * - (7,e/o,1) 1810 * - (8,n,1) 1811 * - (8,m/s,1) 1812 * - (8,e/o,1) 1813 */ 1814 while ((termios->c_cflag & CSIZE) != CS8 && 1815 (termios->c_cflag & CSIZE) != CS7) { 1816 termios->c_cflag &= ~CSIZE; 1817 termios->c_cflag |= old_csize; 1818 old_csize = CS8; 1819 } 1820 1821 if ((termios->c_cflag & CSIZE) == CS8 || 1822 (termios->c_cflag & CSIZE) == CS7) 1823 cr1 = old_cr1 & ~UARTCR1_M; 1824 1825 if (termios->c_cflag & CMSPAR) { 1826 if ((termios->c_cflag & CSIZE) != CS8) { 1827 termios->c_cflag &= ~CSIZE; 1828 termios->c_cflag |= CS8; 1829 } 1830 cr1 |= UARTCR1_M; 1831 } 1832 1833 /* 1834 * When auto RS-485 RTS mode is enabled, 1835 * hardware flow control need to be disabled. 1836 */ 1837 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1838 termios->c_cflag &= ~CRTSCTS; 1839 1840 if (termios->c_cflag & CRTSCTS) 1841 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE; 1842 else 1843 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1844 1845 termios->c_cflag &= ~CSTOPB; 1846 1847 /* parity must be enabled when CS7 to match 8-bits format */ 1848 if ((termios->c_cflag & CSIZE) == CS7) 1849 termios->c_cflag |= PARENB; 1850 1851 if (termios->c_cflag & PARENB) { 1852 if (termios->c_cflag & CMSPAR) { 1853 cr1 &= ~UARTCR1_PE; 1854 if (termios->c_cflag & PARODD) 1855 cr3 |= UARTCR3_T8; 1856 else 1857 cr3 &= ~UARTCR3_T8; 1858 } else { 1859 cr1 |= UARTCR1_PE; 1860 if ((termios->c_cflag & CSIZE) == CS8) 1861 cr1 |= UARTCR1_M; 1862 if (termios->c_cflag & PARODD) 1863 cr1 |= UARTCR1_PT; 1864 else 1865 cr1 &= ~UARTCR1_PT; 1866 } 1867 } else { 1868 cr1 &= ~UARTCR1_PE; 1869 } 1870 1871 /* ask the core to calculate the divisor */ 1872 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1873 1874 /* 1875 * Need to update the Ring buffer length according to the selected 1876 * baud rate and restart Rx DMA path. 1877 * 1878 * Since timer function acqures sport->port.lock, need to stop before 1879 * acquring same lock because otherwise del_timer_sync() can deadlock. 1880 */ 1881 if (old && sport->lpuart_dma_rx_use) { 1882 del_timer_sync(&sport->lpuart_timer); 1883 lpuart_dma_rx_free(&sport->port); 1884 } 1885 1886 spin_lock_irqsave(&sport->port.lock, flags); 1887 1888 sport->port.read_status_mask = 0; 1889 if (termios->c_iflag & INPCK) 1890 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; 1891 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1892 sport->port.read_status_mask |= UARTSR1_FE; 1893 1894 /* characters to ignore */ 1895 sport->port.ignore_status_mask = 0; 1896 if (termios->c_iflag & IGNPAR) 1897 sport->port.ignore_status_mask |= UARTSR1_PE; 1898 if (termios->c_iflag & IGNBRK) { 1899 sport->port.ignore_status_mask |= UARTSR1_FE; 1900 /* 1901 * if we're ignoring parity and break indicators, 1902 * ignore overruns too (for real raw support). 1903 */ 1904 if (termios->c_iflag & IGNPAR) 1905 sport->port.ignore_status_mask |= UARTSR1_OR; 1906 } 1907 1908 /* update the per-port timeout */ 1909 uart_update_timeout(port, termios->c_cflag, baud); 1910 1911 /* wait transmit engin complete */ 1912 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 1913 1914 /* disable transmit and receive */ 1915 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1916 sport->port.membase + UARTCR2); 1917 1918 sbr = sport->port.uartclk / (16 * baud); 1919 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1920 bdh &= ~UARTBDH_SBR_MASK; 1921 bdh |= (sbr >> 8) & 0x1F; 1922 cr4 &= ~UARTCR4_BRFA_MASK; 1923 brfa &= UARTCR4_BRFA_MASK; 1924 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1925 writeb(bdh, sport->port.membase + UARTBDH); 1926 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1927 writeb(cr3, sport->port.membase + UARTCR3); 1928 writeb(cr1, sport->port.membase + UARTCR1); 1929 writeb(modem, sport->port.membase + UARTMODEM); 1930 1931 /* restore control register */ 1932 writeb(old_cr2, sport->port.membase + UARTCR2); 1933 1934 if (old && sport->lpuart_dma_rx_use) { 1935 if (!lpuart_start_rx_dma(sport)) 1936 rx_dma_timer_init(sport); 1937 else 1938 sport->lpuart_dma_rx_use = false; 1939 } 1940 1941 spin_unlock_irqrestore(&sport->port.lock, flags); 1942 } 1943 1944 static void __lpuart32_serial_setbrg(struct uart_port *port, 1945 unsigned int baudrate, bool use_rx_dma, 1946 bool use_tx_dma) 1947 { 1948 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; 1949 u32 clk = port->uartclk; 1950 1951 /* 1952 * The idea is to use the best OSR (over-sampling rate) possible. 1953 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 1954 * Loop to find the best OSR value possible, one that generates minimum 1955 * baud_diff iterate through the rest of the supported values of OSR. 1956 * 1957 * Calculation Formula: 1958 * Baud Rate = baud clock / ((OSR+1) × SBR) 1959 */ 1960 baud_diff = baudrate; 1961 osr = 0; 1962 sbr = 0; 1963 1964 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 1965 /* calculate the temporary sbr value */ 1966 tmp_sbr = (clk / (baudrate * tmp_osr)); 1967 if (tmp_sbr == 0) 1968 tmp_sbr = 1; 1969 1970 /* 1971 * calculate the baud rate difference based on the temporary 1972 * osr and sbr values 1973 */ 1974 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 1975 1976 /* select best values between sbr and sbr+1 */ 1977 tmp = clk / (tmp_osr * (tmp_sbr + 1)); 1978 if (tmp_diff > (baudrate - tmp)) { 1979 tmp_diff = baudrate - tmp; 1980 tmp_sbr++; 1981 } 1982 1983 if (tmp_sbr > UARTBAUD_SBR_MASK) 1984 continue; 1985 1986 if (tmp_diff <= baud_diff) { 1987 baud_diff = tmp_diff; 1988 osr = tmp_osr; 1989 sbr = tmp_sbr; 1990 1991 if (!baud_diff) 1992 break; 1993 } 1994 } 1995 1996 /* handle buadrate outside acceptable rate */ 1997 if (baud_diff > ((baudrate / 100) * 3)) 1998 dev_warn(port->dev, 1999 "unacceptable baud rate difference of more than 3%%\n"); 2000 2001 tmp = lpuart32_read(port, UARTBAUD); 2002 2003 if ((osr > 3) && (osr < 8)) 2004 tmp |= UARTBAUD_BOTHEDGE; 2005 2006 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 2007 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; 2008 2009 tmp &= ~UARTBAUD_SBR_MASK; 2010 tmp |= sbr & UARTBAUD_SBR_MASK; 2011 2012 if (!use_rx_dma) 2013 tmp &= ~UARTBAUD_RDMAE; 2014 if (!use_tx_dma) 2015 tmp &= ~UARTBAUD_TDMAE; 2016 2017 lpuart32_write(port, tmp, UARTBAUD); 2018 } 2019 2020 static void lpuart32_serial_setbrg(struct lpuart_port *sport, 2021 unsigned int baudrate) 2022 { 2023 __lpuart32_serial_setbrg(&sport->port, baudrate, 2024 sport->lpuart_dma_rx_use, 2025 sport->lpuart_dma_tx_use); 2026 } 2027 2028 2029 static void 2030 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 2031 struct ktermios *old) 2032 { 2033 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 2034 unsigned long flags; 2035 unsigned long ctrl, old_ctrl, modem; 2036 unsigned int baud; 2037 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 2038 2039 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); 2040 modem = lpuart32_read(&sport->port, UARTMODIR); 2041 /* 2042 * only support CS8 and CS7, and for CS7 must enable PE. 2043 * supported mode: 2044 * - (7,e/o,1) 2045 * - (8,n,1) 2046 * - (8,m/s,1) 2047 * - (8,e/o,1) 2048 */ 2049 while ((termios->c_cflag & CSIZE) != CS8 && 2050 (termios->c_cflag & CSIZE) != CS7) { 2051 termios->c_cflag &= ~CSIZE; 2052 termios->c_cflag |= old_csize; 2053 old_csize = CS8; 2054 } 2055 2056 if ((termios->c_cflag & CSIZE) == CS8 || 2057 (termios->c_cflag & CSIZE) == CS7) 2058 ctrl = old_ctrl & ~UARTCTRL_M; 2059 2060 if (termios->c_cflag & CMSPAR) { 2061 if ((termios->c_cflag & CSIZE) != CS8) { 2062 termios->c_cflag &= ~CSIZE; 2063 termios->c_cflag |= CS8; 2064 } 2065 ctrl |= UARTCTRL_M; 2066 } 2067 2068 /* 2069 * When auto RS-485 RTS mode is enabled, 2070 * hardware flow control need to be disabled. 2071 */ 2072 if (sport->port.rs485.flags & SER_RS485_ENABLED) 2073 termios->c_cflag &= ~CRTSCTS; 2074 2075 if (termios->c_cflag & CRTSCTS) { 2076 modem |= (UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 2077 } else { 2078 termios->c_cflag &= ~CRTSCTS; 2079 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 2080 } 2081 2082 if (termios->c_cflag & CSTOPB) 2083 termios->c_cflag &= ~CSTOPB; 2084 2085 /* parity must be enabled when CS7 to match 8-bits format */ 2086 if ((termios->c_cflag & CSIZE) == CS7) 2087 termios->c_cflag |= PARENB; 2088 2089 if ((termios->c_cflag & PARENB)) { 2090 if (termios->c_cflag & CMSPAR) { 2091 ctrl &= ~UARTCTRL_PE; 2092 ctrl |= UARTCTRL_M; 2093 } else { 2094 ctrl |= UARTCTRL_PE; 2095 if ((termios->c_cflag & CSIZE) == CS8) 2096 ctrl |= UARTCTRL_M; 2097 if (termios->c_cflag & PARODD) 2098 ctrl |= UARTCTRL_PT; 2099 else 2100 ctrl &= ~UARTCTRL_PT; 2101 } 2102 } else { 2103 ctrl &= ~UARTCTRL_PE; 2104 } 2105 2106 /* ask the core to calculate the divisor */ 2107 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); 2108 2109 /* 2110 * Need to update the Ring buffer length according to the selected 2111 * baud rate and restart Rx DMA path. 2112 * 2113 * Since timer function acqures sport->port.lock, need to stop before 2114 * acquring same lock because otherwise del_timer_sync() can deadlock. 2115 */ 2116 if (old && sport->lpuart_dma_rx_use) { 2117 del_timer_sync(&sport->lpuart_timer); 2118 lpuart_dma_rx_free(&sport->port); 2119 } 2120 2121 spin_lock_irqsave(&sport->port.lock, flags); 2122 2123 sport->port.read_status_mask = 0; 2124 if (termios->c_iflag & INPCK) 2125 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; 2126 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2127 sport->port.read_status_mask |= UARTSTAT_FE; 2128 2129 /* characters to ignore */ 2130 sport->port.ignore_status_mask = 0; 2131 if (termios->c_iflag & IGNPAR) 2132 sport->port.ignore_status_mask |= UARTSTAT_PE; 2133 if (termios->c_iflag & IGNBRK) { 2134 sport->port.ignore_status_mask |= UARTSTAT_FE; 2135 /* 2136 * if we're ignoring parity and break indicators, 2137 * ignore overruns too (for real raw support). 2138 */ 2139 if (termios->c_iflag & IGNPAR) 2140 sport->port.ignore_status_mask |= UARTSTAT_OR; 2141 } 2142 2143 /* update the per-port timeout */ 2144 uart_update_timeout(port, termios->c_cflag, baud); 2145 2146 /* wait transmit engin complete */ 2147 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2148 2149 /* disable transmit and receive */ 2150 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 2151 UARTCTRL); 2152 2153 lpuart32_serial_setbrg(sport, baud); 2154 lpuart32_write(&sport->port, modem, UARTMODIR); 2155 lpuart32_write(&sport->port, ctrl, UARTCTRL); 2156 /* restore control register */ 2157 2158 if (old && sport->lpuart_dma_rx_use) { 2159 if (!lpuart_start_rx_dma(sport)) 2160 rx_dma_timer_init(sport); 2161 else 2162 sport->lpuart_dma_rx_use = false; 2163 } 2164 2165 spin_unlock_irqrestore(&sport->port.lock, flags); 2166 } 2167 2168 static const char *lpuart_type(struct uart_port *port) 2169 { 2170 return "FSL_LPUART"; 2171 } 2172 2173 static void lpuart_release_port(struct uart_port *port) 2174 { 2175 /* nothing to do */ 2176 } 2177 2178 static int lpuart_request_port(struct uart_port *port) 2179 { 2180 return 0; 2181 } 2182 2183 /* configure/autoconfigure the port */ 2184 static void lpuart_config_port(struct uart_port *port, int flags) 2185 { 2186 if (flags & UART_CONFIG_TYPE) 2187 port->type = PORT_LPUART; 2188 } 2189 2190 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 2191 { 2192 int ret = 0; 2193 2194 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 2195 ret = -EINVAL; 2196 if (port->irq != ser->irq) 2197 ret = -EINVAL; 2198 if (ser->io_type != UPIO_MEM) 2199 ret = -EINVAL; 2200 if (port->uartclk / 16 != ser->baud_base) 2201 ret = -EINVAL; 2202 if (port->iobase != ser->port) 2203 ret = -EINVAL; 2204 if (ser->hub6 != 0) 2205 ret = -EINVAL; 2206 return ret; 2207 } 2208 2209 static const struct uart_ops lpuart_pops = { 2210 .tx_empty = lpuart_tx_empty, 2211 .set_mctrl = lpuart_set_mctrl, 2212 .get_mctrl = lpuart_get_mctrl, 2213 .stop_tx = lpuart_stop_tx, 2214 .start_tx = lpuart_start_tx, 2215 .stop_rx = lpuart_stop_rx, 2216 .break_ctl = lpuart_break_ctl, 2217 .startup = lpuart_startup, 2218 .shutdown = lpuart_shutdown, 2219 .set_termios = lpuart_set_termios, 2220 .type = lpuart_type, 2221 .request_port = lpuart_request_port, 2222 .release_port = lpuart_release_port, 2223 .config_port = lpuart_config_port, 2224 .verify_port = lpuart_verify_port, 2225 .flush_buffer = lpuart_flush_buffer, 2226 #if defined(CONFIG_CONSOLE_POLL) 2227 .poll_init = lpuart_poll_init, 2228 .poll_get_char = lpuart_poll_get_char, 2229 .poll_put_char = lpuart_poll_put_char, 2230 #endif 2231 }; 2232 2233 static const struct uart_ops lpuart32_pops = { 2234 .tx_empty = lpuart32_tx_empty, 2235 .set_mctrl = lpuart32_set_mctrl, 2236 .get_mctrl = lpuart32_get_mctrl, 2237 .stop_tx = lpuart32_stop_tx, 2238 .start_tx = lpuart32_start_tx, 2239 .stop_rx = lpuart32_stop_rx, 2240 .break_ctl = lpuart32_break_ctl, 2241 .startup = lpuart32_startup, 2242 .shutdown = lpuart32_shutdown, 2243 .set_termios = lpuart32_set_termios, 2244 .type = lpuart_type, 2245 .request_port = lpuart_request_port, 2246 .release_port = lpuart_release_port, 2247 .config_port = lpuart_config_port, 2248 .verify_port = lpuart_verify_port, 2249 .flush_buffer = lpuart_flush_buffer, 2250 #if defined(CONFIG_CONSOLE_POLL) 2251 .poll_init = lpuart32_poll_init, 2252 .poll_get_char = lpuart32_poll_get_char, 2253 .poll_put_char = lpuart32_poll_put_char, 2254 #endif 2255 }; 2256 2257 static struct lpuart_port *lpuart_ports[UART_NR]; 2258 2259 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 2260 static void lpuart_console_putchar(struct uart_port *port, int ch) 2261 { 2262 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 2263 writeb(ch, port->membase + UARTDR); 2264 } 2265 2266 static void lpuart32_console_putchar(struct uart_port *port, int ch) 2267 { 2268 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 2269 lpuart32_write(port, ch, UARTDATA); 2270 } 2271 2272 static void 2273 lpuart_console_write(struct console *co, const char *s, unsigned int count) 2274 { 2275 struct lpuart_port *sport = lpuart_ports[co->index]; 2276 unsigned char old_cr2, cr2; 2277 unsigned long flags; 2278 int locked = 1; 2279 2280 if (sport->port.sysrq || oops_in_progress) 2281 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2282 else 2283 spin_lock_irqsave(&sport->port.lock, flags); 2284 2285 /* first save CR2 and then disable interrupts */ 2286 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 2287 cr2 |= UARTCR2_TE | UARTCR2_RE; 2288 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 2289 writeb(cr2, sport->port.membase + UARTCR2); 2290 2291 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 2292 2293 /* wait for transmitter finish complete and restore CR2 */ 2294 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 2295 2296 writeb(old_cr2, sport->port.membase + UARTCR2); 2297 2298 if (locked) 2299 spin_unlock_irqrestore(&sport->port.lock, flags); 2300 } 2301 2302 static void 2303 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 2304 { 2305 struct lpuart_port *sport = lpuart_ports[co->index]; 2306 unsigned long old_cr, cr; 2307 unsigned long flags; 2308 int locked = 1; 2309 2310 if (sport->port.sysrq || oops_in_progress) 2311 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2312 else 2313 spin_lock_irqsave(&sport->port.lock, flags); 2314 2315 /* first save CR2 and then disable interrupts */ 2316 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 2317 cr |= UARTCTRL_TE | UARTCTRL_RE; 2318 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 2319 lpuart32_write(&sport->port, cr, UARTCTRL); 2320 2321 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 2322 2323 /* wait for transmitter finish complete and restore CR2 */ 2324 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2325 2326 lpuart32_write(&sport->port, old_cr, UARTCTRL); 2327 2328 if (locked) 2329 spin_unlock_irqrestore(&sport->port.lock, flags); 2330 } 2331 2332 /* 2333 * if the port was already initialised (eg, by a boot loader), 2334 * try to determine the current setup. 2335 */ 2336 static void __init 2337 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 2338 int *parity, int *bits) 2339 { 2340 unsigned char cr, bdh, bdl, brfa; 2341 unsigned int sbr, uartclk, baud_raw; 2342 2343 cr = readb(sport->port.membase + UARTCR2); 2344 cr &= UARTCR2_TE | UARTCR2_RE; 2345 if (!cr) 2346 return; 2347 2348 /* ok, the port was enabled */ 2349 2350 cr = readb(sport->port.membase + UARTCR1); 2351 2352 *parity = 'n'; 2353 if (cr & UARTCR1_PE) { 2354 if (cr & UARTCR1_PT) 2355 *parity = 'o'; 2356 else 2357 *parity = 'e'; 2358 } 2359 2360 if (cr & UARTCR1_M) 2361 *bits = 9; 2362 else 2363 *bits = 8; 2364 2365 bdh = readb(sport->port.membase + UARTBDH); 2366 bdh &= UARTBDH_SBR_MASK; 2367 bdl = readb(sport->port.membase + UARTBDL); 2368 sbr = bdh; 2369 sbr <<= 8; 2370 sbr |= bdl; 2371 brfa = readb(sport->port.membase + UARTCR4); 2372 brfa &= UARTCR4_BRFA_MASK; 2373 2374 uartclk = lpuart_get_baud_clk_rate(sport); 2375 /* 2376 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2377 */ 2378 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 2379 2380 if (*baud != baud_raw) 2381 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2382 "from %d to %d\n", baud_raw, *baud); 2383 } 2384 2385 static void __init 2386 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 2387 int *parity, int *bits) 2388 { 2389 unsigned long cr, bd; 2390 unsigned int sbr, uartclk, baud_raw; 2391 2392 cr = lpuart32_read(&sport->port, UARTCTRL); 2393 cr &= UARTCTRL_TE | UARTCTRL_RE; 2394 if (!cr) 2395 return; 2396 2397 /* ok, the port was enabled */ 2398 2399 cr = lpuart32_read(&sport->port, UARTCTRL); 2400 2401 *parity = 'n'; 2402 if (cr & UARTCTRL_PE) { 2403 if (cr & UARTCTRL_PT) 2404 *parity = 'o'; 2405 else 2406 *parity = 'e'; 2407 } 2408 2409 if (cr & UARTCTRL_M) 2410 *bits = 9; 2411 else 2412 *bits = 8; 2413 2414 bd = lpuart32_read(&sport->port, UARTBAUD); 2415 bd &= UARTBAUD_SBR_MASK; 2416 sbr = bd; 2417 uartclk = lpuart_get_baud_clk_rate(sport); 2418 /* 2419 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2420 */ 2421 baud_raw = uartclk / (16 * sbr); 2422 2423 if (*baud != baud_raw) 2424 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2425 "from %d to %d\n", baud_raw, *baud); 2426 } 2427 2428 static int __init lpuart_console_setup(struct console *co, char *options) 2429 { 2430 struct lpuart_port *sport; 2431 int baud = 115200; 2432 int bits = 8; 2433 int parity = 'n'; 2434 int flow = 'n'; 2435 2436 /* 2437 * check whether an invalid uart number has been specified, and 2438 * if so, search for the first available port that does have 2439 * console support. 2440 */ 2441 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2442 co->index = 0; 2443 2444 sport = lpuart_ports[co->index]; 2445 if (sport == NULL) 2446 return -ENODEV; 2447 2448 if (options) 2449 uart_parse_options(options, &baud, &parity, &bits, &flow); 2450 else 2451 if (lpuart_is_32(sport)) 2452 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2453 else 2454 lpuart_console_get_options(sport, &baud, &parity, &bits); 2455 2456 if (lpuart_is_32(sport)) 2457 lpuart32_setup_watermark(sport); 2458 else 2459 lpuart_setup_watermark(sport); 2460 2461 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2462 } 2463 2464 static struct uart_driver lpuart_reg; 2465 static struct console lpuart_console = { 2466 .name = DEV_NAME, 2467 .write = lpuart_console_write, 2468 .device = uart_console_device, 2469 .setup = lpuart_console_setup, 2470 .flags = CON_PRINTBUFFER, 2471 .index = -1, 2472 .data = &lpuart_reg, 2473 }; 2474 2475 static struct console lpuart32_console = { 2476 .name = DEV_NAME, 2477 .write = lpuart32_console_write, 2478 .device = uart_console_device, 2479 .setup = lpuart_console_setup, 2480 .flags = CON_PRINTBUFFER, 2481 .index = -1, 2482 .data = &lpuart_reg, 2483 }; 2484 2485 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2486 { 2487 struct earlycon_device *dev = con->data; 2488 2489 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2490 } 2491 2492 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2493 { 2494 struct earlycon_device *dev = con->data; 2495 2496 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2497 } 2498 2499 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2500 const char *opt) 2501 { 2502 if (!device->port.membase) 2503 return -ENODEV; 2504 2505 device->con->write = lpuart_early_write; 2506 return 0; 2507 } 2508 2509 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2510 const char *opt) 2511 { 2512 if (!device->port.membase) 2513 return -ENODEV; 2514 2515 if (device->port.iotype != UPIO_MEM32) 2516 device->port.iotype = UPIO_MEM32BE; 2517 2518 device->con->write = lpuart32_early_write; 2519 return 0; 2520 } 2521 2522 static int __init ls1028a_early_console_setup(struct earlycon_device *device, 2523 const char *opt) 2524 { 2525 u32 cr; 2526 2527 if (!device->port.membase) 2528 return -ENODEV; 2529 2530 device->port.iotype = UPIO_MEM32; 2531 device->con->write = lpuart32_early_write; 2532 2533 /* set the baudrate */ 2534 if (device->port.uartclk && device->baud) 2535 __lpuart32_serial_setbrg(&device->port, device->baud, 2536 false, false); 2537 2538 /* enable transmitter */ 2539 cr = lpuart32_read(&device->port, UARTCTRL); 2540 cr |= UARTCTRL_TE; 2541 lpuart32_write(&device->port, cr, UARTCTRL); 2542 2543 return 0; 2544 } 2545 2546 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2547 const char *opt) 2548 { 2549 if (!device->port.membase) 2550 return -ENODEV; 2551 2552 device->port.iotype = UPIO_MEM32; 2553 device->port.membase += IMX_REG_OFF; 2554 device->con->write = lpuart32_early_write; 2555 2556 return 0; 2557 } 2558 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2559 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2560 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup); 2561 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2562 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2563 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2564 2565 #define LPUART_CONSOLE (&lpuart_console) 2566 #define LPUART32_CONSOLE (&lpuart32_console) 2567 #else 2568 #define LPUART_CONSOLE NULL 2569 #define LPUART32_CONSOLE NULL 2570 #endif 2571 2572 static struct uart_driver lpuart_reg = { 2573 .owner = THIS_MODULE, 2574 .driver_name = DRIVER_NAME, 2575 .dev_name = DEV_NAME, 2576 .nr = ARRAY_SIZE(lpuart_ports), 2577 .cons = LPUART_CONSOLE, 2578 }; 2579 2580 static int lpuart_probe(struct platform_device *pdev) 2581 { 2582 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids, 2583 &pdev->dev); 2584 const struct lpuart_soc_data *sdata = of_id->data; 2585 struct device_node *np = pdev->dev.of_node; 2586 struct lpuart_port *sport; 2587 struct resource *res; 2588 int ret; 2589 2590 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2591 if (!sport) 2592 return -ENOMEM; 2593 2594 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2595 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 2596 if (IS_ERR(sport->port.membase)) 2597 return PTR_ERR(sport->port.membase); 2598 2599 sport->port.membase += sdata->reg_off; 2600 sport->port.mapbase = res->start; 2601 sport->port.dev = &pdev->dev; 2602 sport->port.type = PORT_LPUART; 2603 sport->devtype = sdata->devtype; 2604 ret = platform_get_irq(pdev, 0); 2605 if (ret < 0) 2606 return ret; 2607 sport->port.irq = ret; 2608 sport->port.iotype = sdata->iotype; 2609 if (lpuart_is_32(sport)) 2610 sport->port.ops = &lpuart32_pops; 2611 else 2612 sport->port.ops = &lpuart_pops; 2613 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); 2614 sport->port.flags = UPF_BOOT_AUTOCONF; 2615 2616 if (lpuart_is_32(sport)) 2617 sport->port.rs485_config = lpuart32_config_rs485; 2618 else 2619 sport->port.rs485_config = lpuart_config_rs485; 2620 2621 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 2622 if (IS_ERR(sport->ipg_clk)) { 2623 ret = PTR_ERR(sport->ipg_clk); 2624 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); 2625 return ret; 2626 } 2627 2628 sport->baud_clk = NULL; 2629 if (is_imx8qxp_lpuart(sport)) { 2630 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); 2631 if (IS_ERR(sport->baud_clk)) { 2632 ret = PTR_ERR(sport->baud_clk); 2633 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); 2634 return ret; 2635 } 2636 } 2637 2638 ret = of_alias_get_id(np, "serial"); 2639 if (ret < 0) { 2640 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL); 2641 if (ret < 0) { 2642 dev_err(&pdev->dev, "port line is full, add device failed\n"); 2643 return ret; 2644 } 2645 sport->id_allocated = true; 2646 } 2647 if (ret >= ARRAY_SIZE(lpuart_ports)) { 2648 dev_err(&pdev->dev, "serial%d out of range\n", ret); 2649 ret = -EINVAL; 2650 goto failed_out_of_range; 2651 } 2652 sport->port.line = ret; 2653 2654 ret = lpuart_enable_clks(sport); 2655 if (ret) 2656 goto failed_clock_enable; 2657 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); 2658 2659 lpuart_ports[sport->port.line] = sport; 2660 2661 platform_set_drvdata(pdev, &sport->port); 2662 2663 if (lpuart_is_32(sport)) { 2664 lpuart_reg.cons = LPUART32_CONSOLE; 2665 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0, 2666 DRIVER_NAME, sport); 2667 } else { 2668 lpuart_reg.cons = LPUART_CONSOLE; 2669 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0, 2670 DRIVER_NAME, sport); 2671 } 2672 2673 if (ret) 2674 goto failed_irq_request; 2675 2676 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2677 if (ret) 2678 goto failed_attach_port; 2679 2680 ret = uart_get_rs485_mode(&sport->port); 2681 if (ret) 2682 goto failed_get_rs485; 2683 2684 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX) 2685 dev_err(&pdev->dev, "driver doesn't support RX during TX\n"); 2686 2687 if (sport->port.rs485.delay_rts_before_send || 2688 sport->port.rs485.delay_rts_after_send) 2689 dev_err(&pdev->dev, "driver doesn't support RTS delays\n"); 2690 2691 sport->port.rs485_config(&sport->port, &sport->port.rs485); 2692 2693 return 0; 2694 2695 failed_get_rs485: 2696 failed_attach_port: 2697 failed_irq_request: 2698 lpuart_disable_clks(sport); 2699 failed_clock_enable: 2700 failed_out_of_range: 2701 if (sport->id_allocated) 2702 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); 2703 return ret; 2704 } 2705 2706 static int lpuart_remove(struct platform_device *pdev) 2707 { 2708 struct lpuart_port *sport = platform_get_drvdata(pdev); 2709 2710 uart_remove_one_port(&lpuart_reg, &sport->port); 2711 2712 if (sport->id_allocated) 2713 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); 2714 2715 lpuart_disable_clks(sport); 2716 2717 if (sport->dma_tx_chan) 2718 dma_release_channel(sport->dma_tx_chan); 2719 2720 if (sport->dma_rx_chan) 2721 dma_release_channel(sport->dma_rx_chan); 2722 2723 return 0; 2724 } 2725 2726 static int __maybe_unused lpuart_suspend(struct device *dev) 2727 { 2728 struct lpuart_port *sport = dev_get_drvdata(dev); 2729 unsigned long temp; 2730 bool irq_wake; 2731 2732 if (lpuart_is_32(sport)) { 2733 /* disable Rx/Tx and interrupts */ 2734 temp = lpuart32_read(&sport->port, UARTCTRL); 2735 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2736 lpuart32_write(&sport->port, temp, UARTCTRL); 2737 } else { 2738 /* disable Rx/Tx and interrupts */ 2739 temp = readb(sport->port.membase + UARTCR2); 2740 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2741 writeb(temp, sport->port.membase + UARTCR2); 2742 } 2743 2744 uart_suspend_port(&lpuart_reg, &sport->port); 2745 2746 /* uart_suspend_port() might set wakeup flag */ 2747 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2748 2749 if (sport->lpuart_dma_rx_use) { 2750 /* 2751 * EDMA driver during suspend will forcefully release any 2752 * non-idle DMA channels. If port wakeup is enabled or if port 2753 * is console port or 'no_console_suspend' is set the Rx DMA 2754 * cannot resume as as expected, hence gracefully release the 2755 * Rx DMA path before suspend and start Rx DMA path on resume. 2756 */ 2757 if (irq_wake) { 2758 del_timer_sync(&sport->lpuart_timer); 2759 lpuart_dma_rx_free(&sport->port); 2760 } 2761 2762 /* Disable Rx DMA to use UART port as wakeup source */ 2763 if (lpuart_is_32(sport)) { 2764 temp = lpuart32_read(&sport->port, UARTBAUD); 2765 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, 2766 UARTBAUD); 2767 } else { 2768 writeb(readb(sport->port.membase + UARTCR5) & 2769 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 2770 } 2771 } 2772 2773 if (sport->lpuart_dma_tx_use) { 2774 sport->dma_tx_in_progress = false; 2775 dmaengine_terminate_all(sport->dma_tx_chan); 2776 } 2777 2778 if (sport->port.suspended && !irq_wake) 2779 lpuart_disable_clks(sport); 2780 2781 return 0; 2782 } 2783 2784 static int __maybe_unused lpuart_resume(struct device *dev) 2785 { 2786 struct lpuart_port *sport = dev_get_drvdata(dev); 2787 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2788 2789 if (sport->port.suspended && !irq_wake) 2790 lpuart_enable_clks(sport); 2791 2792 if (lpuart_is_32(sport)) 2793 lpuart32_setup_watermark_enable(sport); 2794 else 2795 lpuart_setup_watermark_enable(sport); 2796 2797 if (sport->lpuart_dma_rx_use) { 2798 if (irq_wake) { 2799 if (!lpuart_start_rx_dma(sport)) 2800 rx_dma_timer_init(sport); 2801 else 2802 sport->lpuart_dma_rx_use = false; 2803 } 2804 } 2805 2806 lpuart_tx_dma_startup(sport); 2807 2808 if (lpuart_is_32(sport)) 2809 lpuart32_configure(sport); 2810 2811 uart_resume_port(&lpuart_reg, &sport->port); 2812 2813 return 0; 2814 } 2815 2816 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2817 2818 static struct platform_driver lpuart_driver = { 2819 .probe = lpuart_probe, 2820 .remove = lpuart_remove, 2821 .driver = { 2822 .name = "fsl-lpuart", 2823 .of_match_table = lpuart_dt_ids, 2824 .pm = &lpuart_pm_ops, 2825 }, 2826 }; 2827 2828 static int __init lpuart_serial_init(void) 2829 { 2830 int ret = uart_register_driver(&lpuart_reg); 2831 2832 if (ret) 2833 return ret; 2834 2835 ret = platform_driver_register(&lpuart_driver); 2836 if (ret) 2837 uart_unregister_driver(&lpuart_reg); 2838 2839 return ret; 2840 } 2841 2842 static void __exit lpuart_serial_exit(void) 2843 { 2844 ida_destroy(&fsl_lpuart_ida); 2845 platform_driver_unregister(&lpuart_driver); 2846 uart_unregister_driver(&lpuart_reg); 2847 } 2848 2849 module_init(lpuart_serial_init); 2850 module_exit(lpuart_serial_exit); 2851 2852 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2853 MODULE_LICENSE("GPL v2"); 2854