1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale lpuart serial port driver 4 * 5 * Copyright 2012-2014 Freescale Semiconductor, Inc. 6 */ 7 8 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 9 #define SUPPORT_SYSRQ 10 #endif 11 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dmapool.h> 17 #include <linux/io.h> 18 #include <linux/irq.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/of_dma.h> 23 #include <linux/serial_core.h> 24 #include <linux/slab.h> 25 #include <linux/tty_flip.h> 26 27 /* All registers are 8-bit width */ 28 #define UARTBDH 0x00 29 #define UARTBDL 0x01 30 #define UARTCR1 0x02 31 #define UARTCR2 0x03 32 #define UARTSR1 0x04 33 #define UARTCR3 0x06 34 #define UARTDR 0x07 35 #define UARTCR4 0x0a 36 #define UARTCR5 0x0b 37 #define UARTMODEM 0x0d 38 #define UARTPFIFO 0x10 39 #define UARTCFIFO 0x11 40 #define UARTSFIFO 0x12 41 #define UARTTWFIFO 0x13 42 #define UARTTCFIFO 0x14 43 #define UARTRWFIFO 0x15 44 45 #define UARTBDH_LBKDIE 0x80 46 #define UARTBDH_RXEDGIE 0x40 47 #define UARTBDH_SBR_MASK 0x1f 48 49 #define UARTCR1_LOOPS 0x80 50 #define UARTCR1_RSRC 0x20 51 #define UARTCR1_M 0x10 52 #define UARTCR1_WAKE 0x08 53 #define UARTCR1_ILT 0x04 54 #define UARTCR1_PE 0x02 55 #define UARTCR1_PT 0x01 56 57 #define UARTCR2_TIE 0x80 58 #define UARTCR2_TCIE 0x40 59 #define UARTCR2_RIE 0x20 60 #define UARTCR2_ILIE 0x10 61 #define UARTCR2_TE 0x08 62 #define UARTCR2_RE 0x04 63 #define UARTCR2_RWU 0x02 64 #define UARTCR2_SBK 0x01 65 66 #define UARTSR1_TDRE 0x80 67 #define UARTSR1_TC 0x40 68 #define UARTSR1_RDRF 0x20 69 #define UARTSR1_IDLE 0x10 70 #define UARTSR1_OR 0x08 71 #define UARTSR1_NF 0x04 72 #define UARTSR1_FE 0x02 73 #define UARTSR1_PE 0x01 74 75 #define UARTCR3_R8 0x80 76 #define UARTCR3_T8 0x40 77 #define UARTCR3_TXDIR 0x20 78 #define UARTCR3_TXINV 0x10 79 #define UARTCR3_ORIE 0x08 80 #define UARTCR3_NEIE 0x04 81 #define UARTCR3_FEIE 0x02 82 #define UARTCR3_PEIE 0x01 83 84 #define UARTCR4_MAEN1 0x80 85 #define UARTCR4_MAEN2 0x40 86 #define UARTCR4_M10 0x20 87 #define UARTCR4_BRFA_MASK 0x1f 88 #define UARTCR4_BRFA_OFF 0 89 90 #define UARTCR5_TDMAS 0x80 91 #define UARTCR5_RDMAS 0x20 92 93 #define UARTMODEM_RXRTSE 0x08 94 #define UARTMODEM_TXRTSPOL 0x04 95 #define UARTMODEM_TXRTSE 0x02 96 #define UARTMODEM_TXCTSE 0x01 97 98 #define UARTPFIFO_TXFE 0x80 99 #define UARTPFIFO_FIFOSIZE_MASK 0x7 100 #define UARTPFIFO_TXSIZE_OFF 4 101 #define UARTPFIFO_RXFE 0x08 102 #define UARTPFIFO_RXSIZE_OFF 0 103 104 #define UARTCFIFO_TXFLUSH 0x80 105 #define UARTCFIFO_RXFLUSH 0x40 106 #define UARTCFIFO_RXOFE 0x04 107 #define UARTCFIFO_TXOFE 0x02 108 #define UARTCFIFO_RXUFE 0x01 109 110 #define UARTSFIFO_TXEMPT 0x80 111 #define UARTSFIFO_RXEMPT 0x40 112 #define UARTSFIFO_RXOF 0x04 113 #define UARTSFIFO_TXOF 0x02 114 #define UARTSFIFO_RXUF 0x01 115 116 /* 32-bit register definition */ 117 #define UARTBAUD 0x00 118 #define UARTSTAT 0x04 119 #define UARTCTRL 0x08 120 #define UARTDATA 0x0C 121 #define UARTMATCH 0x10 122 #define UARTMODIR 0x14 123 #define UARTFIFO 0x18 124 #define UARTWATER 0x1c 125 126 #define UARTBAUD_MAEN1 0x80000000 127 #define UARTBAUD_MAEN2 0x40000000 128 #define UARTBAUD_M10 0x20000000 129 #define UARTBAUD_TDMAE 0x00800000 130 #define UARTBAUD_RDMAE 0x00200000 131 #define UARTBAUD_MATCFG 0x00400000 132 #define UARTBAUD_BOTHEDGE 0x00020000 133 #define UARTBAUD_RESYNCDIS 0x00010000 134 #define UARTBAUD_LBKDIE 0x00008000 135 #define UARTBAUD_RXEDGIE 0x00004000 136 #define UARTBAUD_SBNS 0x00002000 137 #define UARTBAUD_SBR 0x00000000 138 #define UARTBAUD_SBR_MASK 0x1fff 139 #define UARTBAUD_OSR_MASK 0x1f 140 #define UARTBAUD_OSR_SHIFT 24 141 142 #define UARTSTAT_LBKDIF 0x80000000 143 #define UARTSTAT_RXEDGIF 0x40000000 144 #define UARTSTAT_MSBF 0x20000000 145 #define UARTSTAT_RXINV 0x10000000 146 #define UARTSTAT_RWUID 0x08000000 147 #define UARTSTAT_BRK13 0x04000000 148 #define UARTSTAT_LBKDE 0x02000000 149 #define UARTSTAT_RAF 0x01000000 150 #define UARTSTAT_TDRE 0x00800000 151 #define UARTSTAT_TC 0x00400000 152 #define UARTSTAT_RDRF 0x00200000 153 #define UARTSTAT_IDLE 0x00100000 154 #define UARTSTAT_OR 0x00080000 155 #define UARTSTAT_NF 0x00040000 156 #define UARTSTAT_FE 0x00020000 157 #define UARTSTAT_PE 0x00010000 158 #define UARTSTAT_MA1F 0x00008000 159 #define UARTSTAT_M21F 0x00004000 160 161 #define UARTCTRL_R8T9 0x80000000 162 #define UARTCTRL_R9T8 0x40000000 163 #define UARTCTRL_TXDIR 0x20000000 164 #define UARTCTRL_TXINV 0x10000000 165 #define UARTCTRL_ORIE 0x08000000 166 #define UARTCTRL_NEIE 0x04000000 167 #define UARTCTRL_FEIE 0x02000000 168 #define UARTCTRL_PEIE 0x01000000 169 #define UARTCTRL_TIE 0x00800000 170 #define UARTCTRL_TCIE 0x00400000 171 #define UARTCTRL_RIE 0x00200000 172 #define UARTCTRL_ILIE 0x00100000 173 #define UARTCTRL_TE 0x00080000 174 #define UARTCTRL_RE 0x00040000 175 #define UARTCTRL_RWU 0x00020000 176 #define UARTCTRL_SBK 0x00010000 177 #define UARTCTRL_MA1IE 0x00008000 178 #define UARTCTRL_MA2IE 0x00004000 179 #define UARTCTRL_IDLECFG 0x00000100 180 #define UARTCTRL_LOOPS 0x00000080 181 #define UARTCTRL_DOZEEN 0x00000040 182 #define UARTCTRL_RSRC 0x00000020 183 #define UARTCTRL_M 0x00000010 184 #define UARTCTRL_WAKE 0x00000008 185 #define UARTCTRL_ILT 0x00000004 186 #define UARTCTRL_PE 0x00000002 187 #define UARTCTRL_PT 0x00000001 188 189 #define UARTDATA_NOISY 0x00008000 190 #define UARTDATA_PARITYE 0x00004000 191 #define UARTDATA_FRETSC 0x00002000 192 #define UARTDATA_RXEMPT 0x00001000 193 #define UARTDATA_IDLINE 0x00000800 194 #define UARTDATA_MASK 0x3ff 195 196 #define UARTMODIR_IREN 0x00020000 197 #define UARTMODIR_TXCTSSRC 0x00000020 198 #define UARTMODIR_TXCTSC 0x00000010 199 #define UARTMODIR_RXRTSE 0x00000008 200 #define UARTMODIR_TXRTSPOL 0x00000004 201 #define UARTMODIR_TXRTSE 0x00000002 202 #define UARTMODIR_TXCTSE 0x00000001 203 204 #define UARTFIFO_TXEMPT 0x00800000 205 #define UARTFIFO_RXEMPT 0x00400000 206 #define UARTFIFO_TXOF 0x00020000 207 #define UARTFIFO_RXUF 0x00010000 208 #define UARTFIFO_TXFLUSH 0x00008000 209 #define UARTFIFO_RXFLUSH 0x00004000 210 #define UARTFIFO_TXOFE 0x00000200 211 #define UARTFIFO_RXUFE 0x00000100 212 #define UARTFIFO_TXFE 0x00000080 213 #define UARTFIFO_FIFOSIZE_MASK 0x7 214 #define UARTFIFO_TXSIZE_OFF 4 215 #define UARTFIFO_RXFE 0x00000008 216 #define UARTFIFO_RXSIZE_OFF 0 217 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0)) 218 219 #define UARTWATER_COUNT_MASK 0xff 220 #define UARTWATER_TXCNT_OFF 8 221 #define UARTWATER_RXCNT_OFF 24 222 #define UARTWATER_WATER_MASK 0xff 223 #define UARTWATER_TXWATER_OFF 0 224 #define UARTWATER_RXWATER_OFF 16 225 226 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 227 #define DMA_RX_TIMEOUT (10) 228 229 #define DRIVER_NAME "fsl-lpuart" 230 #define DEV_NAME "ttyLP" 231 #define UART_NR 6 232 233 /* IMX lpuart has four extra unused regs located at the beginning */ 234 #define IMX_REG_OFF 0x10 235 236 static DEFINE_IDA(fsl_lpuart_ida); 237 238 enum lpuart_type { 239 VF610_LPUART, 240 LS1021A_LPUART, 241 IMX7ULP_LPUART, 242 IMX8QXP_LPUART, 243 }; 244 245 struct lpuart_port { 246 struct uart_port port; 247 enum lpuart_type devtype; 248 struct clk *ipg_clk; 249 struct clk *baud_clk; 250 unsigned int txfifo_size; 251 unsigned int rxfifo_size; 252 253 bool lpuart_dma_tx_use; 254 bool lpuart_dma_rx_use; 255 struct dma_chan *dma_tx_chan; 256 struct dma_chan *dma_rx_chan; 257 struct dma_async_tx_descriptor *dma_tx_desc; 258 struct dma_async_tx_descriptor *dma_rx_desc; 259 dma_cookie_t dma_tx_cookie; 260 dma_cookie_t dma_rx_cookie; 261 unsigned int dma_tx_bytes; 262 unsigned int dma_rx_bytes; 263 bool dma_tx_in_progress; 264 unsigned int dma_rx_timeout; 265 struct timer_list lpuart_timer; 266 struct scatterlist rx_sgl, tx_sgl[2]; 267 struct circ_buf rx_ring; 268 int rx_dma_rng_buf_len; 269 unsigned int dma_tx_nents; 270 wait_queue_head_t dma_wait; 271 }; 272 273 struct lpuart_soc_data { 274 enum lpuart_type devtype; 275 char iotype; 276 u8 reg_off; 277 }; 278 279 static const struct lpuart_soc_data vf_data = { 280 .devtype = VF610_LPUART, 281 .iotype = UPIO_MEM, 282 }; 283 284 static const struct lpuart_soc_data ls_data = { 285 .devtype = LS1021A_LPUART, 286 .iotype = UPIO_MEM32BE, 287 }; 288 289 static struct lpuart_soc_data imx7ulp_data = { 290 .devtype = IMX7ULP_LPUART, 291 .iotype = UPIO_MEM32, 292 .reg_off = IMX_REG_OFF, 293 }; 294 295 static struct lpuart_soc_data imx8qxp_data = { 296 .devtype = IMX8QXP_LPUART, 297 .iotype = UPIO_MEM32, 298 .reg_off = IMX_REG_OFF, 299 }; 300 301 static const struct of_device_id lpuart_dt_ids[] = { 302 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 303 { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, }, 304 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, 305 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, 306 { /* sentinel */ } 307 }; 308 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 309 310 /* Forward declare this for the dma callbacks*/ 311 static void lpuart_dma_tx_complete(void *arg); 312 313 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) 314 { 315 return sport->devtype == IMX8QXP_LPUART; 316 } 317 318 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 319 { 320 switch (port->iotype) { 321 case UPIO_MEM32: 322 return readl(port->membase + off); 323 case UPIO_MEM32BE: 324 return ioread32be(port->membase + off); 325 default: 326 return 0; 327 } 328 } 329 330 static inline void lpuart32_write(struct uart_port *port, u32 val, 331 u32 off) 332 { 333 switch (port->iotype) { 334 case UPIO_MEM32: 335 writel(val, port->membase + off); 336 break; 337 case UPIO_MEM32BE: 338 iowrite32be(val, port->membase + off); 339 break; 340 } 341 } 342 343 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) 344 { 345 int ret = 0; 346 347 if (is_en) { 348 ret = clk_prepare_enable(sport->ipg_clk); 349 if (ret) 350 return ret; 351 352 ret = clk_prepare_enable(sport->baud_clk); 353 if (ret) { 354 clk_disable_unprepare(sport->ipg_clk); 355 return ret; 356 } 357 } else { 358 clk_disable_unprepare(sport->baud_clk); 359 clk_disable_unprepare(sport->ipg_clk); 360 } 361 362 return 0; 363 } 364 365 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) 366 { 367 if (is_imx8qxp_lpuart(sport)) 368 return clk_get_rate(sport->baud_clk); 369 370 return clk_get_rate(sport->ipg_clk); 371 } 372 373 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true) 374 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false) 375 376 static void lpuart_stop_tx(struct uart_port *port) 377 { 378 unsigned char temp; 379 380 temp = readb(port->membase + UARTCR2); 381 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 382 writeb(temp, port->membase + UARTCR2); 383 } 384 385 static void lpuart32_stop_tx(struct uart_port *port) 386 { 387 unsigned long temp; 388 389 temp = lpuart32_read(port, UARTCTRL); 390 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 391 lpuart32_write(port, temp, UARTCTRL); 392 } 393 394 static void lpuart_stop_rx(struct uart_port *port) 395 { 396 unsigned char temp; 397 398 temp = readb(port->membase + UARTCR2); 399 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 400 } 401 402 static void lpuart32_stop_rx(struct uart_port *port) 403 { 404 unsigned long temp; 405 406 temp = lpuart32_read(port, UARTCTRL); 407 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); 408 } 409 410 static void lpuart_dma_tx(struct lpuart_port *sport) 411 { 412 struct circ_buf *xmit = &sport->port.state->xmit; 413 struct scatterlist *sgl = sport->tx_sgl; 414 struct device *dev = sport->port.dev; 415 int ret; 416 417 if (sport->dma_tx_in_progress) 418 return; 419 420 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 421 422 if (xmit->tail < xmit->head || xmit->head == 0) { 423 sport->dma_tx_nents = 1; 424 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 425 } else { 426 sport->dma_tx_nents = 2; 427 sg_init_table(sgl, 2); 428 sg_set_buf(sgl, xmit->buf + xmit->tail, 429 UART_XMIT_SIZE - xmit->tail); 430 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 431 } 432 433 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 434 if (!ret) { 435 dev_err(dev, "DMA mapping error for TX.\n"); 436 return; 437 } 438 439 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl, 440 ret, DMA_MEM_TO_DEV, 441 DMA_PREP_INTERRUPT); 442 if (!sport->dma_tx_desc) { 443 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 444 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 445 return; 446 } 447 448 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 449 sport->dma_tx_desc->callback_param = sport; 450 sport->dma_tx_in_progress = true; 451 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 452 dma_async_issue_pending(sport->dma_tx_chan); 453 } 454 455 static bool lpuart_stopped_or_empty(struct uart_port *port) 456 { 457 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); 458 } 459 460 static void lpuart_dma_tx_complete(void *arg) 461 { 462 struct lpuart_port *sport = arg; 463 struct scatterlist *sgl = &sport->tx_sgl[0]; 464 struct circ_buf *xmit = &sport->port.state->xmit; 465 unsigned long flags; 466 467 spin_lock_irqsave(&sport->port.lock, flags); 468 469 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 470 471 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 472 473 sport->port.icount.tx += sport->dma_tx_bytes; 474 sport->dma_tx_in_progress = false; 475 spin_unlock_irqrestore(&sport->port.lock, flags); 476 477 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 478 uart_write_wakeup(&sport->port); 479 480 if (waitqueue_active(&sport->dma_wait)) { 481 wake_up(&sport->dma_wait); 482 return; 483 } 484 485 spin_lock_irqsave(&sport->port.lock, flags); 486 487 if (!lpuart_stopped_or_empty(&sport->port)) 488 lpuart_dma_tx(sport); 489 490 spin_unlock_irqrestore(&sport->port.lock, flags); 491 } 492 493 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) 494 { 495 switch (sport->port.iotype) { 496 case UPIO_MEM32: 497 return sport->port.mapbase + UARTDATA; 498 case UPIO_MEM32BE: 499 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; 500 } 501 return sport->port.mapbase + UARTDR; 502 } 503 504 static int lpuart_dma_tx_request(struct uart_port *port) 505 { 506 struct lpuart_port *sport = container_of(port, 507 struct lpuart_port, port); 508 struct dma_slave_config dma_tx_sconfig = {}; 509 int ret; 510 511 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); 512 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 513 dma_tx_sconfig.dst_maxburst = 1; 514 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 515 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 516 517 if (ret) { 518 dev_err(sport->port.dev, 519 "DMA slave config failed, err = %d\n", ret); 520 return ret; 521 } 522 523 return 0; 524 } 525 526 static bool lpuart_is_32(struct lpuart_port *sport) 527 { 528 return sport->port.iotype == UPIO_MEM32 || 529 sport->port.iotype == UPIO_MEM32BE; 530 } 531 532 static void lpuart_flush_buffer(struct uart_port *port) 533 { 534 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 535 u32 val; 536 537 if (sport->lpuart_dma_tx_use) { 538 if (sport->dma_tx_in_progress) { 539 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 540 sport->dma_tx_nents, DMA_TO_DEVICE); 541 sport->dma_tx_in_progress = false; 542 } 543 dmaengine_terminate_all(sport->dma_tx_chan); 544 } 545 546 if (lpuart_is_32(sport)) { 547 val = lpuart32_read(&sport->port, UARTFIFO); 548 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 549 lpuart32_write(&sport->port, val, UARTFIFO); 550 } else { 551 val = readb(sport->port.membase + UARTCFIFO); 552 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; 553 writeb(val, sport->port.membase + UARTCFIFO); 554 } 555 } 556 557 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset, 558 u8 bit) 559 { 560 while (!(readb(port->membase + offset) & bit)) 561 cpu_relax(); 562 } 563 564 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset, 565 u32 bit) 566 { 567 while (!(lpuart32_read(port, offset) & bit)) 568 cpu_relax(); 569 } 570 571 #if defined(CONFIG_CONSOLE_POLL) 572 573 static int lpuart_poll_init(struct uart_port *port) 574 { 575 struct lpuart_port *sport = container_of(port, 576 struct lpuart_port, port); 577 unsigned long flags; 578 unsigned char temp; 579 580 sport->port.fifosize = 0; 581 582 spin_lock_irqsave(&sport->port.lock, flags); 583 /* Disable Rx & Tx */ 584 writeb(0, sport->port.membase + UARTCR2); 585 586 temp = readb(sport->port.membase + UARTPFIFO); 587 /* Enable Rx and Tx FIFO */ 588 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 589 sport->port.membase + UARTPFIFO); 590 591 /* flush Tx and Rx FIFO */ 592 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 593 sport->port.membase + UARTCFIFO); 594 595 /* explicitly clear RDRF */ 596 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 597 readb(sport->port.membase + UARTDR); 598 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 599 } 600 601 writeb(0, sport->port.membase + UARTTWFIFO); 602 writeb(1, sport->port.membase + UARTRWFIFO); 603 604 /* Enable Rx and Tx */ 605 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 606 spin_unlock_irqrestore(&sport->port.lock, flags); 607 608 return 0; 609 } 610 611 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 612 { 613 /* drain */ 614 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 615 writeb(c, port->membase + UARTDR); 616 } 617 618 static int lpuart_poll_get_char(struct uart_port *port) 619 { 620 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 621 return NO_POLL_CHAR; 622 623 return readb(port->membase + UARTDR); 624 } 625 626 static int lpuart32_poll_init(struct uart_port *port) 627 { 628 unsigned long flags; 629 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 630 u32 temp; 631 632 sport->port.fifosize = 0; 633 634 spin_lock_irqsave(&sport->port.lock, flags); 635 636 /* Disable Rx & Tx */ 637 lpuart32_write(&sport->port, UARTCTRL, 0); 638 639 temp = lpuart32_read(&sport->port, UARTFIFO); 640 641 /* Enable Rx and Tx FIFO */ 642 lpuart32_write(&sport->port, UARTFIFO, 643 temp | UARTFIFO_RXFE | UARTFIFO_TXFE); 644 645 /* flush Tx and Rx FIFO */ 646 lpuart32_write(&sport->port, UARTFIFO, 647 UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH); 648 649 /* explicitly clear RDRF */ 650 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { 651 lpuart32_read(&sport->port, UARTDATA); 652 lpuart32_write(&sport->port, UARTFIFO, UARTFIFO_RXUF); 653 } 654 655 /* Enable Rx and Tx */ 656 lpuart32_write(&sport->port, UARTCTRL, UARTCTRL_RE | UARTCTRL_TE); 657 spin_unlock_irqrestore(&sport->port.lock, flags); 658 659 return 0; 660 } 661 662 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 663 { 664 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 665 lpuart32_write(port, UARTDATA, c); 666 } 667 668 static int lpuart32_poll_get_char(struct uart_port *port) 669 { 670 if (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_RDRF)) 671 return NO_POLL_CHAR; 672 673 return lpuart32_read(port, UARTDATA); 674 } 675 #endif 676 677 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 678 { 679 struct circ_buf *xmit = &sport->port.state->xmit; 680 681 if (sport->port.x_char) { 682 writeb(sport->port.x_char, sport->port.membase + UARTDR); 683 sport->port.icount.tx++; 684 sport->port.x_char = 0; 685 return; 686 } 687 688 if (lpuart_stopped_or_empty(&sport->port)) { 689 lpuart_stop_tx(&sport->port); 690 return; 691 } 692 693 while (!uart_circ_empty(xmit) && 694 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 695 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 696 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 697 sport->port.icount.tx++; 698 } 699 700 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 701 uart_write_wakeup(&sport->port); 702 703 if (uart_circ_empty(xmit)) 704 lpuart_stop_tx(&sport->port); 705 } 706 707 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 708 { 709 struct circ_buf *xmit = &sport->port.state->xmit; 710 unsigned long txcnt; 711 712 if (sport->port.x_char) { 713 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 714 sport->port.icount.tx++; 715 sport->port.x_char = 0; 716 return; 717 } 718 719 if (lpuart_stopped_or_empty(&sport->port)) { 720 lpuart32_stop_tx(&sport->port); 721 return; 722 } 723 724 txcnt = lpuart32_read(&sport->port, UARTWATER); 725 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 726 txcnt &= UARTWATER_COUNT_MASK; 727 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 728 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); 729 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 730 sport->port.icount.tx++; 731 txcnt = lpuart32_read(&sport->port, UARTWATER); 732 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 733 txcnt &= UARTWATER_COUNT_MASK; 734 } 735 736 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 737 uart_write_wakeup(&sport->port); 738 739 if (uart_circ_empty(xmit)) 740 lpuart32_stop_tx(&sport->port); 741 } 742 743 static void lpuart_start_tx(struct uart_port *port) 744 { 745 struct lpuart_port *sport = container_of(port, 746 struct lpuart_port, port); 747 unsigned char temp; 748 749 temp = readb(port->membase + UARTCR2); 750 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 751 752 if (sport->lpuart_dma_tx_use) { 753 if (!lpuart_stopped_or_empty(port)) 754 lpuart_dma_tx(sport); 755 } else { 756 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 757 lpuart_transmit_buffer(sport); 758 } 759 } 760 761 static void lpuart32_start_tx(struct uart_port *port) 762 { 763 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 764 unsigned long temp; 765 766 if (sport->lpuart_dma_tx_use) { 767 if (!lpuart_stopped_or_empty(port)) 768 lpuart_dma_tx(sport); 769 } else { 770 temp = lpuart32_read(port, UARTCTRL); 771 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); 772 773 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 774 lpuart32_transmit_buffer(sport); 775 } 776 } 777 778 /* return TIOCSER_TEMT when transmitter is not busy */ 779 static unsigned int lpuart_tx_empty(struct uart_port *port) 780 { 781 struct lpuart_port *sport = container_of(port, 782 struct lpuart_port, port); 783 unsigned char sr1 = readb(port->membase + UARTSR1); 784 unsigned char sfifo = readb(port->membase + UARTSFIFO); 785 786 if (sport->dma_tx_in_progress) 787 return 0; 788 789 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 790 return TIOCSER_TEMT; 791 792 return 0; 793 } 794 795 static unsigned int lpuart32_tx_empty(struct uart_port *port) 796 { 797 struct lpuart_port *sport = container_of(port, 798 struct lpuart_port, port); 799 unsigned long stat = lpuart32_read(port, UARTSTAT); 800 unsigned long sfifo = lpuart32_read(port, UARTFIFO); 801 802 if (sport->dma_tx_in_progress) 803 return 0; 804 805 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) 806 return TIOCSER_TEMT; 807 808 return 0; 809 } 810 811 static void lpuart_txint(struct lpuart_port *sport) 812 { 813 unsigned long flags; 814 815 spin_lock_irqsave(&sport->port.lock, flags); 816 lpuart_transmit_buffer(sport); 817 spin_unlock_irqrestore(&sport->port.lock, flags); 818 } 819 820 static void lpuart_rxint(struct lpuart_port *sport) 821 { 822 unsigned int flg, ignored = 0, overrun = 0; 823 struct tty_port *port = &sport->port.state->port; 824 unsigned long flags; 825 unsigned char rx, sr; 826 827 spin_lock_irqsave(&sport->port.lock, flags); 828 829 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 830 flg = TTY_NORMAL; 831 sport->port.icount.rx++; 832 /* 833 * to clear the FE, OR, NF, FE, PE flags, 834 * read SR1 then read DR 835 */ 836 sr = readb(sport->port.membase + UARTSR1); 837 rx = readb(sport->port.membase + UARTDR); 838 839 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 840 continue; 841 842 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 843 if (sr & UARTSR1_PE) 844 sport->port.icount.parity++; 845 else if (sr & UARTSR1_FE) 846 sport->port.icount.frame++; 847 848 if (sr & UARTSR1_OR) 849 overrun++; 850 851 if (sr & sport->port.ignore_status_mask) { 852 if (++ignored > 100) 853 goto out; 854 continue; 855 } 856 857 sr &= sport->port.read_status_mask; 858 859 if (sr & UARTSR1_PE) 860 flg = TTY_PARITY; 861 else if (sr & UARTSR1_FE) 862 flg = TTY_FRAME; 863 864 if (sr & UARTSR1_OR) 865 flg = TTY_OVERRUN; 866 867 #ifdef SUPPORT_SYSRQ 868 sport->port.sysrq = 0; 869 #endif 870 } 871 872 tty_insert_flip_char(port, rx, flg); 873 } 874 875 out: 876 if (overrun) { 877 sport->port.icount.overrun += overrun; 878 879 /* 880 * Overruns cause FIFO pointers to become missaligned. 881 * Flushing the receive FIFO reinitializes the pointers. 882 */ 883 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 884 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); 885 } 886 887 spin_unlock_irqrestore(&sport->port.lock, flags); 888 889 tty_flip_buffer_push(port); 890 } 891 892 static void lpuart32_txint(struct lpuart_port *sport) 893 { 894 unsigned long flags; 895 896 spin_lock_irqsave(&sport->port.lock, flags); 897 lpuart32_transmit_buffer(sport); 898 spin_unlock_irqrestore(&sport->port.lock, flags); 899 } 900 901 static void lpuart32_rxint(struct lpuart_port *sport) 902 { 903 unsigned int flg, ignored = 0; 904 struct tty_port *port = &sport->port.state->port; 905 unsigned long flags; 906 unsigned long rx, sr; 907 908 spin_lock_irqsave(&sport->port.lock, flags); 909 910 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 911 flg = TTY_NORMAL; 912 sport->port.icount.rx++; 913 /* 914 * to clear the FE, OR, NF, FE, PE flags, 915 * read STAT then read DATA reg 916 */ 917 sr = lpuart32_read(&sport->port, UARTSTAT); 918 rx = lpuart32_read(&sport->port, UARTDATA); 919 rx &= 0x3ff; 920 921 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 922 continue; 923 924 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 925 if (sr & UARTSTAT_PE) 926 sport->port.icount.parity++; 927 else if (sr & UARTSTAT_FE) 928 sport->port.icount.frame++; 929 930 if (sr & UARTSTAT_OR) 931 sport->port.icount.overrun++; 932 933 if (sr & sport->port.ignore_status_mask) { 934 if (++ignored > 100) 935 goto out; 936 continue; 937 } 938 939 sr &= sport->port.read_status_mask; 940 941 if (sr & UARTSTAT_PE) 942 flg = TTY_PARITY; 943 else if (sr & UARTSTAT_FE) 944 flg = TTY_FRAME; 945 946 if (sr & UARTSTAT_OR) 947 flg = TTY_OVERRUN; 948 949 #ifdef SUPPORT_SYSRQ 950 sport->port.sysrq = 0; 951 #endif 952 } 953 954 tty_insert_flip_char(port, rx, flg); 955 } 956 957 out: 958 spin_unlock_irqrestore(&sport->port.lock, flags); 959 960 tty_flip_buffer_push(port); 961 } 962 963 static irqreturn_t lpuart_int(int irq, void *dev_id) 964 { 965 struct lpuart_port *sport = dev_id; 966 unsigned char sts; 967 968 sts = readb(sport->port.membase + UARTSR1); 969 970 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) 971 lpuart_rxint(sport); 972 973 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) 974 lpuart_txint(sport); 975 976 return IRQ_HANDLED; 977 } 978 979 static irqreturn_t lpuart32_int(int irq, void *dev_id) 980 { 981 struct lpuart_port *sport = dev_id; 982 unsigned long sts, rxcount; 983 984 sts = lpuart32_read(&sport->port, UARTSTAT); 985 rxcount = lpuart32_read(&sport->port, UARTWATER); 986 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 987 988 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) 989 lpuart32_rxint(sport); 990 991 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) 992 lpuart32_txint(sport); 993 994 lpuart32_write(&sport->port, sts, UARTSTAT); 995 return IRQ_HANDLED; 996 } 997 998 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 999 { 1000 struct tty_port *port = &sport->port.state->port; 1001 struct dma_tx_state state; 1002 enum dma_status dmastat; 1003 struct circ_buf *ring = &sport->rx_ring; 1004 unsigned long flags; 1005 int count = 0; 1006 1007 if (lpuart_is_32(sport)) { 1008 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); 1009 1010 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { 1011 /* Read DR to clear the error flags */ 1012 lpuart32_read(&sport->port, UARTDATA); 1013 1014 if (sr & UARTSTAT_PE) 1015 sport->port.icount.parity++; 1016 else if (sr & UARTSTAT_FE) 1017 sport->port.icount.frame++; 1018 } 1019 } else { 1020 unsigned char sr = readb(sport->port.membase + UARTSR1); 1021 1022 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 1023 unsigned char cr2; 1024 1025 /* Disable receiver during this operation... */ 1026 cr2 = readb(sport->port.membase + UARTCR2); 1027 cr2 &= ~UARTCR2_RE; 1028 writeb(cr2, sport->port.membase + UARTCR2); 1029 1030 /* Read DR to clear the error flags */ 1031 readb(sport->port.membase + UARTDR); 1032 1033 if (sr & UARTSR1_PE) 1034 sport->port.icount.parity++; 1035 else if (sr & UARTSR1_FE) 1036 sport->port.icount.frame++; 1037 /* 1038 * At this point parity/framing error is 1039 * cleared However, since the DMA already read 1040 * the data register and we had to read it 1041 * again after reading the status register to 1042 * properly clear the flags, the FIFO actually 1043 * underflowed... This requires a clearing of 1044 * the FIFO... 1045 */ 1046 if (readb(sport->port.membase + UARTSFIFO) & 1047 UARTSFIFO_RXUF) { 1048 writeb(UARTSFIFO_RXUF, 1049 sport->port.membase + UARTSFIFO); 1050 writeb(UARTCFIFO_RXFLUSH, 1051 sport->port.membase + UARTCFIFO); 1052 } 1053 1054 cr2 |= UARTCR2_RE; 1055 writeb(cr2, sport->port.membase + UARTCR2); 1056 } 1057 } 1058 1059 async_tx_ack(sport->dma_rx_desc); 1060 1061 spin_lock_irqsave(&sport->port.lock, flags); 1062 1063 dmastat = dmaengine_tx_status(sport->dma_rx_chan, 1064 sport->dma_rx_cookie, 1065 &state); 1066 1067 if (dmastat == DMA_ERROR) { 1068 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1069 spin_unlock_irqrestore(&sport->port.lock, flags); 1070 return; 1071 } 1072 1073 /* CPU claims ownership of RX DMA buffer */ 1074 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1075 1076 /* 1077 * ring->head points to the end of data already written by the DMA. 1078 * ring->tail points to the beginning of data to be read by the 1079 * framework. 1080 * The current transfer size should not be larger than the dma buffer 1081 * length. 1082 */ 1083 ring->head = sport->rx_sgl.length - state.residue; 1084 BUG_ON(ring->head > sport->rx_sgl.length); 1085 /* 1086 * At this point ring->head may point to the first byte right after the 1087 * last byte of the dma buffer: 1088 * 0 <= ring->head <= sport->rx_sgl.length 1089 * 1090 * However ring->tail must always points inside the dma buffer: 1091 * 0 <= ring->tail <= sport->rx_sgl.length - 1 1092 * 1093 * Since we use a ring buffer, we have to handle the case 1094 * where head is lower than tail. In such a case, we first read from 1095 * tail to the end of the buffer then reset tail. 1096 */ 1097 if (ring->head < ring->tail) { 1098 count = sport->rx_sgl.length - ring->tail; 1099 1100 tty_insert_flip_string(port, ring->buf + ring->tail, count); 1101 ring->tail = 0; 1102 sport->port.icount.rx += count; 1103 } 1104 1105 /* Finally we read data from tail to head */ 1106 if (ring->tail < ring->head) { 1107 count = ring->head - ring->tail; 1108 tty_insert_flip_string(port, ring->buf + ring->tail, count); 1109 /* Wrap ring->head if needed */ 1110 if (ring->head >= sport->rx_sgl.length) 1111 ring->head = 0; 1112 ring->tail = ring->head; 1113 sport->port.icount.rx += count; 1114 } 1115 1116 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1, 1117 DMA_FROM_DEVICE); 1118 1119 spin_unlock_irqrestore(&sport->port.lock, flags); 1120 1121 tty_flip_buffer_push(port); 1122 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 1123 } 1124 1125 static void lpuart_dma_rx_complete(void *arg) 1126 { 1127 struct lpuart_port *sport = arg; 1128 1129 lpuart_copy_rx_to_tty(sport); 1130 } 1131 1132 static void lpuart_timer_func(struct timer_list *t) 1133 { 1134 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); 1135 1136 lpuart_copy_rx_to_tty(sport); 1137 } 1138 1139 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 1140 { 1141 struct dma_slave_config dma_rx_sconfig = {}; 1142 struct circ_buf *ring = &sport->rx_ring; 1143 int ret, nent; 1144 int bits, baud; 1145 struct tty_port *port = &sport->port.state->port; 1146 struct tty_struct *tty = port->tty; 1147 struct ktermios *termios = &tty->termios; 1148 1149 baud = tty_get_baud_rate(tty); 1150 1151 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; 1152 if (termios->c_cflag & PARENB) 1153 bits++; 1154 1155 /* 1156 * Calculate length of one DMA buffer size to keep latency below 1157 * 10ms at any baud rate. 1158 */ 1159 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 1160 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 1161 if (sport->rx_dma_rng_buf_len < 16) 1162 sport->rx_dma_rng_buf_len = 16; 1163 1164 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1165 if (!ring->buf) 1166 return -ENOMEM; 1167 1168 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1169 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1170 1171 if (!nent) { 1172 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1173 return -EINVAL; 1174 } 1175 1176 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); 1177 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1178 dma_rx_sconfig.src_maxburst = 1; 1179 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1180 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig); 1181 1182 if (ret < 0) { 1183 dev_err(sport->port.dev, 1184 "DMA Rx slave config failed, err = %d\n", ret); 1185 return ret; 1186 } 1187 1188 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan, 1189 sg_dma_address(&sport->rx_sgl), 1190 sport->rx_sgl.length, 1191 sport->rx_sgl.length / 2, 1192 DMA_DEV_TO_MEM, 1193 DMA_PREP_INTERRUPT); 1194 if (!sport->dma_rx_desc) { 1195 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1196 return -EFAULT; 1197 } 1198 1199 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1200 sport->dma_rx_desc->callback_param = sport; 1201 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1202 dma_async_issue_pending(sport->dma_rx_chan); 1203 1204 if (lpuart_is_32(sport)) { 1205 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); 1206 1207 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); 1208 } else { 1209 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1210 sport->port.membase + UARTCR5); 1211 } 1212 1213 return 0; 1214 } 1215 1216 static void lpuart_dma_rx_free(struct uart_port *port) 1217 { 1218 struct lpuart_port *sport = container_of(port, 1219 struct lpuart_port, port); 1220 1221 if (sport->dma_rx_chan) 1222 dmaengine_terminate_all(sport->dma_rx_chan); 1223 1224 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1225 kfree(sport->rx_ring.buf); 1226 sport->rx_ring.tail = 0; 1227 sport->rx_ring.head = 0; 1228 sport->dma_rx_desc = NULL; 1229 sport->dma_rx_cookie = -EINVAL; 1230 } 1231 1232 static int lpuart_config_rs485(struct uart_port *port, 1233 struct serial_rs485 *rs485) 1234 { 1235 struct lpuart_port *sport = container_of(port, 1236 struct lpuart_port, port); 1237 1238 u8 modem = readb(sport->port.membase + UARTMODEM) & 1239 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1240 writeb(modem, sport->port.membase + UARTMODEM); 1241 1242 /* clear unsupported configurations */ 1243 rs485->delay_rts_before_send = 0; 1244 rs485->delay_rts_after_send = 0; 1245 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1246 1247 if (rs485->flags & SER_RS485_ENABLED) { 1248 /* Enable auto RS-485 RTS mode */ 1249 modem |= UARTMODEM_TXRTSE; 1250 1251 /* 1252 * RTS needs to be logic HIGH either during transer _or_ after 1253 * transfer, other variants are not supported by the hardware. 1254 */ 1255 1256 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1257 SER_RS485_RTS_AFTER_SEND))) 1258 rs485->flags |= SER_RS485_RTS_ON_SEND; 1259 1260 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1261 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1262 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1263 1264 /* 1265 * The hardware defaults to RTS logic HIGH while transfer. 1266 * Switch polarity in case RTS shall be logic HIGH 1267 * after transfer. 1268 * Note: UART is assumed to be active high. 1269 */ 1270 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1271 modem &= ~UARTMODEM_TXRTSPOL; 1272 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1273 modem |= UARTMODEM_TXRTSPOL; 1274 } 1275 1276 /* Store the new configuration */ 1277 sport->port.rs485 = *rs485; 1278 1279 writeb(modem, sport->port.membase + UARTMODEM); 1280 return 0; 1281 } 1282 1283 static int lpuart32_config_rs485(struct uart_port *port, 1284 struct serial_rs485 *rs485) 1285 { 1286 struct lpuart_port *sport = container_of(port, 1287 struct lpuart_port, port); 1288 1289 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) 1290 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1291 lpuart32_write(&sport->port, modem, UARTMODIR); 1292 1293 /* clear unsupported configurations */ 1294 rs485->delay_rts_before_send = 0; 1295 rs485->delay_rts_after_send = 0; 1296 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1297 1298 if (rs485->flags & SER_RS485_ENABLED) { 1299 /* Enable auto RS-485 RTS mode */ 1300 modem |= UARTMODEM_TXRTSE; 1301 1302 /* 1303 * RTS needs to be logic HIGH either during transer _or_ after 1304 * transfer, other variants are not supported by the hardware. 1305 */ 1306 1307 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1308 SER_RS485_RTS_AFTER_SEND))) 1309 rs485->flags |= SER_RS485_RTS_ON_SEND; 1310 1311 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1312 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1313 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1314 1315 /* 1316 * The hardware defaults to RTS logic HIGH while transfer. 1317 * Switch polarity in case RTS shall be logic HIGH 1318 * after transfer. 1319 * Note: UART is assumed to be active high. 1320 */ 1321 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1322 modem &= ~UARTMODEM_TXRTSPOL; 1323 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1324 modem |= UARTMODEM_TXRTSPOL; 1325 } 1326 1327 /* Store the new configuration */ 1328 sport->port.rs485 = *rs485; 1329 1330 lpuart32_write(&sport->port, modem, UARTMODIR); 1331 return 0; 1332 } 1333 1334 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1335 { 1336 unsigned int temp = 0; 1337 unsigned char reg; 1338 1339 reg = readb(port->membase + UARTMODEM); 1340 if (reg & UARTMODEM_TXCTSE) 1341 temp |= TIOCM_CTS; 1342 1343 if (reg & UARTMODEM_RXRTSE) 1344 temp |= TIOCM_RTS; 1345 1346 return temp; 1347 } 1348 1349 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1350 { 1351 unsigned int temp = 0; 1352 unsigned long reg; 1353 1354 reg = lpuart32_read(port, UARTMODIR); 1355 if (reg & UARTMODIR_TXCTSE) 1356 temp |= TIOCM_CTS; 1357 1358 if (reg & UARTMODIR_RXRTSE) 1359 temp |= TIOCM_RTS; 1360 1361 return temp; 1362 } 1363 1364 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1365 { 1366 unsigned char temp; 1367 struct lpuart_port *sport = container_of(port, 1368 struct lpuart_port, port); 1369 1370 /* Make sure RXRTSE bit is not set when RS485 is enabled */ 1371 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { 1372 temp = readb(sport->port.membase + UARTMODEM) & 1373 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1374 1375 if (mctrl & TIOCM_RTS) 1376 temp |= UARTMODEM_RXRTSE; 1377 1378 if (mctrl & TIOCM_CTS) 1379 temp |= UARTMODEM_TXCTSE; 1380 1381 writeb(temp, port->membase + UARTMODEM); 1382 } 1383 } 1384 1385 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1386 { 1387 1388 } 1389 1390 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1391 { 1392 unsigned char temp; 1393 1394 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1395 1396 if (break_state != 0) 1397 temp |= UARTCR2_SBK; 1398 1399 writeb(temp, port->membase + UARTCR2); 1400 } 1401 1402 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1403 { 1404 unsigned long temp; 1405 1406 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; 1407 1408 if (break_state != 0) 1409 temp |= UARTCTRL_SBK; 1410 1411 lpuart32_write(port, temp, UARTCTRL); 1412 } 1413 1414 static void lpuart_setup_watermark(struct lpuart_port *sport) 1415 { 1416 unsigned char val, cr2; 1417 unsigned char cr2_saved; 1418 1419 cr2 = readb(sport->port.membase + UARTCR2); 1420 cr2_saved = cr2; 1421 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1422 UARTCR2_RIE | UARTCR2_RE); 1423 writeb(cr2, sport->port.membase + UARTCR2); 1424 1425 val = readb(sport->port.membase + UARTPFIFO); 1426 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1427 sport->port.membase + UARTPFIFO); 1428 1429 /* flush Tx and Rx FIFO */ 1430 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1431 sport->port.membase + UARTCFIFO); 1432 1433 /* explicitly clear RDRF */ 1434 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1435 readb(sport->port.membase + UARTDR); 1436 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1437 } 1438 1439 writeb(0, sport->port.membase + UARTTWFIFO); 1440 writeb(1, sport->port.membase + UARTRWFIFO); 1441 1442 /* Restore cr2 */ 1443 writeb(cr2_saved, sport->port.membase + UARTCR2); 1444 } 1445 1446 static void lpuart_setup_watermark_enable(struct lpuart_port *sport) 1447 { 1448 unsigned char cr2; 1449 1450 lpuart_setup_watermark(sport); 1451 1452 cr2 = readb(sport->port.membase + UARTCR2); 1453 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE; 1454 writeb(cr2, sport->port.membase + UARTCR2); 1455 } 1456 1457 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1458 { 1459 unsigned long val, ctrl; 1460 unsigned long ctrl_saved; 1461 1462 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1463 ctrl_saved = ctrl; 1464 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1465 UARTCTRL_RIE | UARTCTRL_RE); 1466 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1467 1468 /* enable FIFO mode */ 1469 val = lpuart32_read(&sport->port, UARTFIFO); 1470 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1471 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1472 lpuart32_write(&sport->port, val, UARTFIFO); 1473 1474 /* set the watermark */ 1475 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1476 lpuart32_write(&sport->port, val, UARTWATER); 1477 1478 /* Restore cr2 */ 1479 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1480 } 1481 1482 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) 1483 { 1484 u32 temp; 1485 1486 lpuart32_setup_watermark(sport); 1487 1488 temp = lpuart32_read(&sport->port, UARTCTRL); 1489 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE; 1490 lpuart32_write(&sport->port, temp, UARTCTRL); 1491 } 1492 1493 static void rx_dma_timer_init(struct lpuart_port *sport) 1494 { 1495 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); 1496 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1497 add_timer(&sport->lpuart_timer); 1498 } 1499 1500 static void lpuart_tx_dma_startup(struct lpuart_port *sport) 1501 { 1502 u32 uartbaud; 1503 1504 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) { 1505 init_waitqueue_head(&sport->dma_wait); 1506 sport->lpuart_dma_tx_use = true; 1507 if (lpuart_is_32(sport)) { 1508 uartbaud = lpuart32_read(&sport->port, UARTBAUD); 1509 lpuart32_write(&sport->port, 1510 uartbaud | UARTBAUD_TDMAE, UARTBAUD); 1511 } else { 1512 writeb(readb(sport->port.membase + UARTCR5) | 1513 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 1514 } 1515 } else { 1516 sport->lpuart_dma_tx_use = false; 1517 } 1518 } 1519 1520 static void lpuart_rx_dma_startup(struct lpuart_port *sport) 1521 { 1522 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) { 1523 /* set Rx DMA timeout */ 1524 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1525 if (!sport->dma_rx_timeout) 1526 sport->dma_rx_timeout = 1; 1527 1528 sport->lpuart_dma_rx_use = true; 1529 rx_dma_timer_init(sport); 1530 } else { 1531 sport->lpuart_dma_rx_use = false; 1532 } 1533 } 1534 1535 static int lpuart_startup(struct uart_port *port) 1536 { 1537 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1538 unsigned long flags; 1539 unsigned char temp; 1540 1541 /* determine FIFO size and enable FIFO mode */ 1542 temp = readb(sport->port.membase + UARTPFIFO); 1543 1544 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & 1545 UARTPFIFO_FIFOSIZE_MASK); 1546 sport->port.fifosize = sport->txfifo_size; 1547 1548 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & 1549 UARTPFIFO_FIFOSIZE_MASK); 1550 1551 spin_lock_irqsave(&sport->port.lock, flags); 1552 1553 lpuart_setup_watermark_enable(sport); 1554 1555 lpuart_rx_dma_startup(sport); 1556 lpuart_tx_dma_startup(sport); 1557 1558 spin_unlock_irqrestore(&sport->port.lock, flags); 1559 1560 return 0; 1561 } 1562 1563 static void lpuart32_configure(struct lpuart_port *sport) 1564 { 1565 unsigned long temp; 1566 1567 if (sport->lpuart_dma_rx_use) { 1568 /* RXWATER must be 0 */ 1569 temp = lpuart32_read(&sport->port, UARTWATER); 1570 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF); 1571 lpuart32_write(&sport->port, temp, UARTWATER); 1572 } 1573 temp = lpuart32_read(&sport->port, UARTCTRL); 1574 if (!sport->lpuart_dma_rx_use) 1575 temp |= UARTCTRL_RIE; 1576 if (!sport->lpuart_dma_tx_use) 1577 temp |= UARTCTRL_TIE; 1578 lpuart32_write(&sport->port, temp, UARTCTRL); 1579 } 1580 1581 static int lpuart32_startup(struct uart_port *port) 1582 { 1583 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1584 unsigned long flags; 1585 unsigned long temp; 1586 1587 /* determine FIFO size */ 1588 temp = lpuart32_read(&sport->port, UARTFIFO); 1589 1590 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & 1591 UARTFIFO_FIFOSIZE_MASK); 1592 sport->port.fifosize = sport->txfifo_size; 1593 1594 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & 1595 UARTFIFO_FIFOSIZE_MASK); 1596 1597 spin_lock_irqsave(&sport->port.lock, flags); 1598 1599 lpuart32_setup_watermark_enable(sport); 1600 1601 1602 lpuart_rx_dma_startup(sport); 1603 lpuart_tx_dma_startup(sport); 1604 1605 lpuart32_configure(sport); 1606 1607 spin_unlock_irqrestore(&sport->port.lock, flags); 1608 return 0; 1609 } 1610 1611 static void lpuart_dma_shutdown(struct lpuart_port *sport) 1612 { 1613 if (sport->lpuart_dma_rx_use) { 1614 del_timer_sync(&sport->lpuart_timer); 1615 lpuart_dma_rx_free(&sport->port); 1616 } 1617 1618 if (sport->lpuart_dma_tx_use) { 1619 if (wait_event_interruptible(sport->dma_wait, 1620 !sport->dma_tx_in_progress) != false) { 1621 sport->dma_tx_in_progress = false; 1622 dmaengine_terminate_all(sport->dma_tx_chan); 1623 } 1624 } 1625 } 1626 1627 static void lpuart_shutdown(struct uart_port *port) 1628 { 1629 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1630 unsigned char temp; 1631 unsigned long flags; 1632 1633 spin_lock_irqsave(&port->lock, flags); 1634 1635 /* disable Rx/Tx and interrupts */ 1636 temp = readb(port->membase + UARTCR2); 1637 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1638 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1639 writeb(temp, port->membase + UARTCR2); 1640 1641 spin_unlock_irqrestore(&port->lock, flags); 1642 1643 lpuart_dma_shutdown(sport); 1644 } 1645 1646 static void lpuart32_shutdown(struct uart_port *port) 1647 { 1648 struct lpuart_port *sport = 1649 container_of(port, struct lpuart_port, port); 1650 unsigned long temp; 1651 unsigned long flags; 1652 1653 spin_lock_irqsave(&port->lock, flags); 1654 1655 /* disable Rx/Tx and interrupts */ 1656 temp = lpuart32_read(port, UARTCTRL); 1657 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1658 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1659 lpuart32_write(port, temp, UARTCTRL); 1660 1661 spin_unlock_irqrestore(&port->lock, flags); 1662 1663 lpuart_dma_shutdown(sport); 1664 } 1665 1666 static void 1667 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1668 struct ktermios *old) 1669 { 1670 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1671 unsigned long flags; 1672 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1673 unsigned int baud; 1674 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1675 unsigned int sbr, brfa; 1676 1677 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1678 old_cr2 = readb(sport->port.membase + UARTCR2); 1679 cr3 = readb(sport->port.membase + UARTCR3); 1680 cr4 = readb(sport->port.membase + UARTCR4); 1681 bdh = readb(sport->port.membase + UARTBDH); 1682 modem = readb(sport->port.membase + UARTMODEM); 1683 /* 1684 * only support CS8 and CS7, and for CS7 must enable PE. 1685 * supported mode: 1686 * - (7,e/o,1) 1687 * - (8,n,1) 1688 * - (8,m/s,1) 1689 * - (8,e/o,1) 1690 */ 1691 while ((termios->c_cflag & CSIZE) != CS8 && 1692 (termios->c_cflag & CSIZE) != CS7) { 1693 termios->c_cflag &= ~CSIZE; 1694 termios->c_cflag |= old_csize; 1695 old_csize = CS8; 1696 } 1697 1698 if ((termios->c_cflag & CSIZE) == CS8 || 1699 (termios->c_cflag & CSIZE) == CS7) 1700 cr1 = old_cr1 & ~UARTCR1_M; 1701 1702 if (termios->c_cflag & CMSPAR) { 1703 if ((termios->c_cflag & CSIZE) != CS8) { 1704 termios->c_cflag &= ~CSIZE; 1705 termios->c_cflag |= CS8; 1706 } 1707 cr1 |= UARTCR1_M; 1708 } 1709 1710 /* 1711 * When auto RS-485 RTS mode is enabled, 1712 * hardware flow control need to be disabled. 1713 */ 1714 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1715 termios->c_cflag &= ~CRTSCTS; 1716 1717 if (termios->c_cflag & CRTSCTS) 1718 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE; 1719 else 1720 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1721 1722 termios->c_cflag &= ~CSTOPB; 1723 1724 /* parity must be enabled when CS7 to match 8-bits format */ 1725 if ((termios->c_cflag & CSIZE) == CS7) 1726 termios->c_cflag |= PARENB; 1727 1728 if (termios->c_cflag & PARENB) { 1729 if (termios->c_cflag & CMSPAR) { 1730 cr1 &= ~UARTCR1_PE; 1731 if (termios->c_cflag & PARODD) 1732 cr3 |= UARTCR3_T8; 1733 else 1734 cr3 &= ~UARTCR3_T8; 1735 } else { 1736 cr1 |= UARTCR1_PE; 1737 if ((termios->c_cflag & CSIZE) == CS8) 1738 cr1 |= UARTCR1_M; 1739 if (termios->c_cflag & PARODD) 1740 cr1 |= UARTCR1_PT; 1741 else 1742 cr1 &= ~UARTCR1_PT; 1743 } 1744 } else { 1745 cr1 &= ~UARTCR1_PE; 1746 } 1747 1748 /* ask the core to calculate the divisor */ 1749 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1750 1751 /* 1752 * Need to update the Ring buffer length according to the selected 1753 * baud rate and restart Rx DMA path. 1754 * 1755 * Since timer function acqures sport->port.lock, need to stop before 1756 * acquring same lock because otherwise del_timer_sync() can deadlock. 1757 */ 1758 if (old && sport->lpuart_dma_rx_use) { 1759 del_timer_sync(&sport->lpuart_timer); 1760 lpuart_dma_rx_free(&sport->port); 1761 } 1762 1763 spin_lock_irqsave(&sport->port.lock, flags); 1764 1765 sport->port.read_status_mask = 0; 1766 if (termios->c_iflag & INPCK) 1767 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; 1768 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1769 sport->port.read_status_mask |= UARTSR1_FE; 1770 1771 /* characters to ignore */ 1772 sport->port.ignore_status_mask = 0; 1773 if (termios->c_iflag & IGNPAR) 1774 sport->port.ignore_status_mask |= UARTSR1_PE; 1775 if (termios->c_iflag & IGNBRK) { 1776 sport->port.ignore_status_mask |= UARTSR1_FE; 1777 /* 1778 * if we're ignoring parity and break indicators, 1779 * ignore overruns too (for real raw support). 1780 */ 1781 if (termios->c_iflag & IGNPAR) 1782 sport->port.ignore_status_mask |= UARTSR1_OR; 1783 } 1784 1785 /* update the per-port timeout */ 1786 uart_update_timeout(port, termios->c_cflag, baud); 1787 1788 /* wait transmit engin complete */ 1789 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 1790 1791 /* disable transmit and receive */ 1792 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1793 sport->port.membase + UARTCR2); 1794 1795 sbr = sport->port.uartclk / (16 * baud); 1796 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1797 bdh &= ~UARTBDH_SBR_MASK; 1798 bdh |= (sbr >> 8) & 0x1F; 1799 cr4 &= ~UARTCR4_BRFA_MASK; 1800 brfa &= UARTCR4_BRFA_MASK; 1801 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1802 writeb(bdh, sport->port.membase + UARTBDH); 1803 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1804 writeb(cr3, sport->port.membase + UARTCR3); 1805 writeb(cr1, sport->port.membase + UARTCR1); 1806 writeb(modem, sport->port.membase + UARTMODEM); 1807 1808 /* restore control register */ 1809 writeb(old_cr2, sport->port.membase + UARTCR2); 1810 1811 if (old && sport->lpuart_dma_rx_use) { 1812 if (!lpuart_start_rx_dma(sport)) 1813 rx_dma_timer_init(sport); 1814 else 1815 sport->lpuart_dma_rx_use = false; 1816 } 1817 1818 spin_unlock_irqrestore(&sport->port.lock, flags); 1819 } 1820 1821 static void 1822 lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate) 1823 { 1824 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; 1825 u32 clk = sport->port.uartclk; 1826 1827 /* 1828 * The idea is to use the best OSR (over-sampling rate) possible. 1829 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 1830 * Loop to find the best OSR value possible, one that generates minimum 1831 * baud_diff iterate through the rest of the supported values of OSR. 1832 * 1833 * Calculation Formula: 1834 * Baud Rate = baud clock / ((OSR+1) × SBR) 1835 */ 1836 baud_diff = baudrate; 1837 osr = 0; 1838 sbr = 0; 1839 1840 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 1841 /* calculate the temporary sbr value */ 1842 tmp_sbr = (clk / (baudrate * tmp_osr)); 1843 if (tmp_sbr == 0) 1844 tmp_sbr = 1; 1845 1846 /* 1847 * calculate the baud rate difference based on the temporary 1848 * osr and sbr values 1849 */ 1850 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 1851 1852 /* select best values between sbr and sbr+1 */ 1853 tmp = clk / (tmp_osr * (tmp_sbr + 1)); 1854 if (tmp_diff > (baudrate - tmp)) { 1855 tmp_diff = baudrate - tmp; 1856 tmp_sbr++; 1857 } 1858 1859 if (tmp_diff <= baud_diff) { 1860 baud_diff = tmp_diff; 1861 osr = tmp_osr; 1862 sbr = tmp_sbr; 1863 1864 if (!baud_diff) 1865 break; 1866 } 1867 } 1868 1869 /* handle buadrate outside acceptable rate */ 1870 if (baud_diff > ((baudrate / 100) * 3)) 1871 dev_warn(sport->port.dev, 1872 "unacceptable baud rate difference of more than 3%%\n"); 1873 1874 tmp = lpuart32_read(&sport->port, UARTBAUD); 1875 1876 if ((osr > 3) && (osr < 8)) 1877 tmp |= UARTBAUD_BOTHEDGE; 1878 1879 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 1880 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; 1881 1882 tmp &= ~UARTBAUD_SBR_MASK; 1883 tmp |= sbr & UARTBAUD_SBR_MASK; 1884 1885 if (!sport->lpuart_dma_rx_use) 1886 tmp &= ~UARTBAUD_RDMAE; 1887 if (!sport->lpuart_dma_tx_use) 1888 tmp &= ~UARTBAUD_TDMAE; 1889 1890 lpuart32_write(&sport->port, tmp, UARTBAUD); 1891 } 1892 1893 static void 1894 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 1895 struct ktermios *old) 1896 { 1897 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1898 unsigned long flags; 1899 unsigned long ctrl, old_ctrl, modem; 1900 unsigned int baud; 1901 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1902 1903 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); 1904 modem = lpuart32_read(&sport->port, UARTMODIR); 1905 /* 1906 * only support CS8 and CS7, and for CS7 must enable PE. 1907 * supported mode: 1908 * - (7,e/o,1) 1909 * - (8,n,1) 1910 * - (8,m/s,1) 1911 * - (8,e/o,1) 1912 */ 1913 while ((termios->c_cflag & CSIZE) != CS8 && 1914 (termios->c_cflag & CSIZE) != CS7) { 1915 termios->c_cflag &= ~CSIZE; 1916 termios->c_cflag |= old_csize; 1917 old_csize = CS8; 1918 } 1919 1920 if ((termios->c_cflag & CSIZE) == CS8 || 1921 (termios->c_cflag & CSIZE) == CS7) 1922 ctrl = old_ctrl & ~UARTCTRL_M; 1923 1924 if (termios->c_cflag & CMSPAR) { 1925 if ((termios->c_cflag & CSIZE) != CS8) { 1926 termios->c_cflag &= ~CSIZE; 1927 termios->c_cflag |= CS8; 1928 } 1929 ctrl |= UARTCTRL_M; 1930 } 1931 1932 /* 1933 * When auto RS-485 RTS mode is enabled, 1934 * hardware flow control need to be disabled. 1935 */ 1936 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1937 termios->c_cflag &= ~CRTSCTS; 1938 1939 if (termios->c_cflag & CRTSCTS) { 1940 modem |= (UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 1941 } else { 1942 termios->c_cflag &= ~CRTSCTS; 1943 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 1944 } 1945 1946 if (termios->c_cflag & CSTOPB) 1947 termios->c_cflag &= ~CSTOPB; 1948 1949 /* parity must be enabled when CS7 to match 8-bits format */ 1950 if ((termios->c_cflag & CSIZE) == CS7) 1951 termios->c_cflag |= PARENB; 1952 1953 if ((termios->c_cflag & PARENB)) { 1954 if (termios->c_cflag & CMSPAR) { 1955 ctrl &= ~UARTCTRL_PE; 1956 ctrl |= UARTCTRL_M; 1957 } else { 1958 ctrl |= UARTCTRL_PE; 1959 if ((termios->c_cflag & CSIZE) == CS8) 1960 ctrl |= UARTCTRL_M; 1961 if (termios->c_cflag & PARODD) 1962 ctrl |= UARTCTRL_PT; 1963 else 1964 ctrl &= ~UARTCTRL_PT; 1965 } 1966 } else { 1967 ctrl &= ~UARTCTRL_PE; 1968 } 1969 1970 /* ask the core to calculate the divisor */ 1971 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); 1972 1973 /* 1974 * Need to update the Ring buffer length according to the selected 1975 * baud rate and restart Rx DMA path. 1976 * 1977 * Since timer function acqures sport->port.lock, need to stop before 1978 * acquring same lock because otherwise del_timer_sync() can deadlock. 1979 */ 1980 if (old && sport->lpuart_dma_rx_use) { 1981 del_timer_sync(&sport->lpuart_timer); 1982 lpuart_dma_rx_free(&sport->port); 1983 } 1984 1985 spin_lock_irqsave(&sport->port.lock, flags); 1986 1987 sport->port.read_status_mask = 0; 1988 if (termios->c_iflag & INPCK) 1989 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; 1990 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1991 sport->port.read_status_mask |= UARTSTAT_FE; 1992 1993 /* characters to ignore */ 1994 sport->port.ignore_status_mask = 0; 1995 if (termios->c_iflag & IGNPAR) 1996 sport->port.ignore_status_mask |= UARTSTAT_PE; 1997 if (termios->c_iflag & IGNBRK) { 1998 sport->port.ignore_status_mask |= UARTSTAT_FE; 1999 /* 2000 * if we're ignoring parity and break indicators, 2001 * ignore overruns too (for real raw support). 2002 */ 2003 if (termios->c_iflag & IGNPAR) 2004 sport->port.ignore_status_mask |= UARTSTAT_OR; 2005 } 2006 2007 /* update the per-port timeout */ 2008 uart_update_timeout(port, termios->c_cflag, baud); 2009 2010 /* wait transmit engin complete */ 2011 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2012 2013 /* disable transmit and receive */ 2014 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 2015 UARTCTRL); 2016 2017 lpuart32_serial_setbrg(sport, baud); 2018 lpuart32_write(&sport->port, modem, UARTMODIR); 2019 lpuart32_write(&sport->port, ctrl, UARTCTRL); 2020 /* restore control register */ 2021 2022 if (old && sport->lpuart_dma_rx_use) { 2023 if (!lpuart_start_rx_dma(sport)) 2024 rx_dma_timer_init(sport); 2025 else 2026 sport->lpuart_dma_rx_use = false; 2027 } 2028 2029 spin_unlock_irqrestore(&sport->port.lock, flags); 2030 } 2031 2032 static const char *lpuart_type(struct uart_port *port) 2033 { 2034 return "FSL_LPUART"; 2035 } 2036 2037 static void lpuart_release_port(struct uart_port *port) 2038 { 2039 /* nothing to do */ 2040 } 2041 2042 static int lpuart_request_port(struct uart_port *port) 2043 { 2044 return 0; 2045 } 2046 2047 /* configure/autoconfigure the port */ 2048 static void lpuart_config_port(struct uart_port *port, int flags) 2049 { 2050 if (flags & UART_CONFIG_TYPE) 2051 port->type = PORT_LPUART; 2052 } 2053 2054 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 2055 { 2056 int ret = 0; 2057 2058 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 2059 ret = -EINVAL; 2060 if (port->irq != ser->irq) 2061 ret = -EINVAL; 2062 if (ser->io_type != UPIO_MEM) 2063 ret = -EINVAL; 2064 if (port->uartclk / 16 != ser->baud_base) 2065 ret = -EINVAL; 2066 if (port->iobase != ser->port) 2067 ret = -EINVAL; 2068 if (ser->hub6 != 0) 2069 ret = -EINVAL; 2070 return ret; 2071 } 2072 2073 static const struct uart_ops lpuart_pops = { 2074 .tx_empty = lpuart_tx_empty, 2075 .set_mctrl = lpuart_set_mctrl, 2076 .get_mctrl = lpuart_get_mctrl, 2077 .stop_tx = lpuart_stop_tx, 2078 .start_tx = lpuart_start_tx, 2079 .stop_rx = lpuart_stop_rx, 2080 .break_ctl = lpuart_break_ctl, 2081 .startup = lpuart_startup, 2082 .shutdown = lpuart_shutdown, 2083 .set_termios = lpuart_set_termios, 2084 .type = lpuart_type, 2085 .request_port = lpuart_request_port, 2086 .release_port = lpuart_release_port, 2087 .config_port = lpuart_config_port, 2088 .verify_port = lpuart_verify_port, 2089 .flush_buffer = lpuart_flush_buffer, 2090 #if defined(CONFIG_CONSOLE_POLL) 2091 .poll_init = lpuart_poll_init, 2092 .poll_get_char = lpuart_poll_get_char, 2093 .poll_put_char = lpuart_poll_put_char, 2094 #endif 2095 }; 2096 2097 static const struct uart_ops lpuart32_pops = { 2098 .tx_empty = lpuart32_tx_empty, 2099 .set_mctrl = lpuart32_set_mctrl, 2100 .get_mctrl = lpuart32_get_mctrl, 2101 .stop_tx = lpuart32_stop_tx, 2102 .start_tx = lpuart32_start_tx, 2103 .stop_rx = lpuart32_stop_rx, 2104 .break_ctl = lpuart32_break_ctl, 2105 .startup = lpuart32_startup, 2106 .shutdown = lpuart32_shutdown, 2107 .set_termios = lpuart32_set_termios, 2108 .type = lpuart_type, 2109 .request_port = lpuart_request_port, 2110 .release_port = lpuart_release_port, 2111 .config_port = lpuart_config_port, 2112 .verify_port = lpuart_verify_port, 2113 .flush_buffer = lpuart_flush_buffer, 2114 #if defined(CONFIG_CONSOLE_POLL) 2115 .poll_init = lpuart32_poll_init, 2116 .poll_get_char = lpuart32_poll_get_char, 2117 .poll_put_char = lpuart32_poll_put_char, 2118 #endif 2119 }; 2120 2121 static struct lpuart_port *lpuart_ports[UART_NR]; 2122 2123 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 2124 static void lpuart_console_putchar(struct uart_port *port, int ch) 2125 { 2126 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 2127 writeb(ch, port->membase + UARTDR); 2128 } 2129 2130 static void lpuart32_console_putchar(struct uart_port *port, int ch) 2131 { 2132 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 2133 lpuart32_write(port, ch, UARTDATA); 2134 } 2135 2136 static void 2137 lpuart_console_write(struct console *co, const char *s, unsigned int count) 2138 { 2139 struct lpuart_port *sport = lpuart_ports[co->index]; 2140 unsigned char old_cr2, cr2; 2141 unsigned long flags; 2142 int locked = 1; 2143 2144 if (sport->port.sysrq || oops_in_progress) 2145 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2146 else 2147 spin_lock_irqsave(&sport->port.lock, flags); 2148 2149 /* first save CR2 and then disable interrupts */ 2150 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 2151 cr2 |= UARTCR2_TE | UARTCR2_RE; 2152 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 2153 writeb(cr2, sport->port.membase + UARTCR2); 2154 2155 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 2156 2157 /* wait for transmitter finish complete and restore CR2 */ 2158 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 2159 2160 writeb(old_cr2, sport->port.membase + UARTCR2); 2161 2162 if (locked) 2163 spin_unlock_irqrestore(&sport->port.lock, flags); 2164 } 2165 2166 static void 2167 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 2168 { 2169 struct lpuart_port *sport = lpuart_ports[co->index]; 2170 unsigned long old_cr, cr; 2171 unsigned long flags; 2172 int locked = 1; 2173 2174 if (sport->port.sysrq || oops_in_progress) 2175 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2176 else 2177 spin_lock_irqsave(&sport->port.lock, flags); 2178 2179 /* first save CR2 and then disable interrupts */ 2180 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 2181 cr |= UARTCTRL_TE | UARTCTRL_RE; 2182 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 2183 lpuart32_write(&sport->port, cr, UARTCTRL); 2184 2185 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 2186 2187 /* wait for transmitter finish complete and restore CR2 */ 2188 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2189 2190 lpuart32_write(&sport->port, old_cr, UARTCTRL); 2191 2192 if (locked) 2193 spin_unlock_irqrestore(&sport->port.lock, flags); 2194 } 2195 2196 /* 2197 * if the port was already initialised (eg, by a boot loader), 2198 * try to determine the current setup. 2199 */ 2200 static void __init 2201 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 2202 int *parity, int *bits) 2203 { 2204 unsigned char cr, bdh, bdl, brfa; 2205 unsigned int sbr, uartclk, baud_raw; 2206 2207 cr = readb(sport->port.membase + UARTCR2); 2208 cr &= UARTCR2_TE | UARTCR2_RE; 2209 if (!cr) 2210 return; 2211 2212 /* ok, the port was enabled */ 2213 2214 cr = readb(sport->port.membase + UARTCR1); 2215 2216 *parity = 'n'; 2217 if (cr & UARTCR1_PE) { 2218 if (cr & UARTCR1_PT) 2219 *parity = 'o'; 2220 else 2221 *parity = 'e'; 2222 } 2223 2224 if (cr & UARTCR1_M) 2225 *bits = 9; 2226 else 2227 *bits = 8; 2228 2229 bdh = readb(sport->port.membase + UARTBDH); 2230 bdh &= UARTBDH_SBR_MASK; 2231 bdl = readb(sport->port.membase + UARTBDL); 2232 sbr = bdh; 2233 sbr <<= 8; 2234 sbr |= bdl; 2235 brfa = readb(sport->port.membase + UARTCR4); 2236 brfa &= UARTCR4_BRFA_MASK; 2237 2238 uartclk = lpuart_get_baud_clk_rate(sport); 2239 /* 2240 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2241 */ 2242 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 2243 2244 if (*baud != baud_raw) 2245 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2246 "from %d to %d\n", baud_raw, *baud); 2247 } 2248 2249 static void __init 2250 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 2251 int *parity, int *bits) 2252 { 2253 unsigned long cr, bd; 2254 unsigned int sbr, uartclk, baud_raw; 2255 2256 cr = lpuart32_read(&sport->port, UARTCTRL); 2257 cr &= UARTCTRL_TE | UARTCTRL_RE; 2258 if (!cr) 2259 return; 2260 2261 /* ok, the port was enabled */ 2262 2263 cr = lpuart32_read(&sport->port, UARTCTRL); 2264 2265 *parity = 'n'; 2266 if (cr & UARTCTRL_PE) { 2267 if (cr & UARTCTRL_PT) 2268 *parity = 'o'; 2269 else 2270 *parity = 'e'; 2271 } 2272 2273 if (cr & UARTCTRL_M) 2274 *bits = 9; 2275 else 2276 *bits = 8; 2277 2278 bd = lpuart32_read(&sport->port, UARTBAUD); 2279 bd &= UARTBAUD_SBR_MASK; 2280 sbr = bd; 2281 uartclk = lpuart_get_baud_clk_rate(sport); 2282 /* 2283 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2284 */ 2285 baud_raw = uartclk / (16 * sbr); 2286 2287 if (*baud != baud_raw) 2288 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2289 "from %d to %d\n", baud_raw, *baud); 2290 } 2291 2292 static int __init lpuart_console_setup(struct console *co, char *options) 2293 { 2294 struct lpuart_port *sport; 2295 int baud = 115200; 2296 int bits = 8; 2297 int parity = 'n'; 2298 int flow = 'n'; 2299 2300 /* 2301 * check whether an invalid uart number has been specified, and 2302 * if so, search for the first available port that does have 2303 * console support. 2304 */ 2305 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2306 co->index = 0; 2307 2308 sport = lpuart_ports[co->index]; 2309 if (sport == NULL) 2310 return -ENODEV; 2311 2312 if (options) 2313 uart_parse_options(options, &baud, &parity, &bits, &flow); 2314 else 2315 if (lpuart_is_32(sport)) 2316 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2317 else 2318 lpuart_console_get_options(sport, &baud, &parity, &bits); 2319 2320 if (lpuart_is_32(sport)) 2321 lpuart32_setup_watermark(sport); 2322 else 2323 lpuart_setup_watermark(sport); 2324 2325 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2326 } 2327 2328 static struct uart_driver lpuart_reg; 2329 static struct console lpuart_console = { 2330 .name = DEV_NAME, 2331 .write = lpuart_console_write, 2332 .device = uart_console_device, 2333 .setup = lpuart_console_setup, 2334 .flags = CON_PRINTBUFFER, 2335 .index = -1, 2336 .data = &lpuart_reg, 2337 }; 2338 2339 static struct console lpuart32_console = { 2340 .name = DEV_NAME, 2341 .write = lpuart32_console_write, 2342 .device = uart_console_device, 2343 .setup = lpuart_console_setup, 2344 .flags = CON_PRINTBUFFER, 2345 .index = -1, 2346 .data = &lpuart_reg, 2347 }; 2348 2349 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2350 { 2351 struct earlycon_device *dev = con->data; 2352 2353 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2354 } 2355 2356 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2357 { 2358 struct earlycon_device *dev = con->data; 2359 2360 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2361 } 2362 2363 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2364 const char *opt) 2365 { 2366 if (!device->port.membase) 2367 return -ENODEV; 2368 2369 device->con->write = lpuart_early_write; 2370 return 0; 2371 } 2372 2373 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2374 const char *opt) 2375 { 2376 if (!device->port.membase) 2377 return -ENODEV; 2378 2379 device->port.iotype = UPIO_MEM32BE; 2380 device->con->write = lpuart32_early_write; 2381 return 0; 2382 } 2383 2384 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2385 const char *opt) 2386 { 2387 if (!device->port.membase) 2388 return -ENODEV; 2389 2390 device->port.iotype = UPIO_MEM32; 2391 device->port.membase += IMX_REG_OFF; 2392 device->con->write = lpuart32_early_write; 2393 2394 return 0; 2395 } 2396 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2397 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2398 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2399 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup); 2400 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2401 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2402 2403 #define LPUART_CONSOLE (&lpuart_console) 2404 #define LPUART32_CONSOLE (&lpuart32_console) 2405 #else 2406 #define LPUART_CONSOLE NULL 2407 #define LPUART32_CONSOLE NULL 2408 #endif 2409 2410 static struct uart_driver lpuart_reg = { 2411 .owner = THIS_MODULE, 2412 .driver_name = DRIVER_NAME, 2413 .dev_name = DEV_NAME, 2414 .nr = ARRAY_SIZE(lpuart_ports), 2415 .cons = LPUART_CONSOLE, 2416 }; 2417 2418 static int lpuart_probe(struct platform_device *pdev) 2419 { 2420 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids, 2421 &pdev->dev); 2422 const struct lpuart_soc_data *sdata = of_id->data; 2423 struct device_node *np = pdev->dev.of_node; 2424 struct lpuart_port *sport; 2425 struct resource *res; 2426 int ret; 2427 2428 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2429 if (!sport) 2430 return -ENOMEM; 2431 2432 ret = of_alias_get_id(np, "serial"); 2433 if (ret < 0) { 2434 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL); 2435 if (ret < 0) { 2436 dev_err(&pdev->dev, "port line is full, add device failed\n"); 2437 return ret; 2438 } 2439 } 2440 if (ret >= ARRAY_SIZE(lpuart_ports)) { 2441 dev_err(&pdev->dev, "serial%d out of range\n", ret); 2442 return -EINVAL; 2443 } 2444 sport->port.line = ret; 2445 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2446 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 2447 if (IS_ERR(sport->port.membase)) 2448 return PTR_ERR(sport->port.membase); 2449 2450 sport->port.membase += sdata->reg_off; 2451 sport->port.mapbase = res->start; 2452 sport->port.dev = &pdev->dev; 2453 sport->port.type = PORT_LPUART; 2454 sport->devtype = sdata->devtype; 2455 ret = platform_get_irq(pdev, 0); 2456 if (ret < 0) 2457 return ret; 2458 sport->port.irq = ret; 2459 sport->port.iotype = sdata->iotype; 2460 if (lpuart_is_32(sport)) 2461 sport->port.ops = &lpuart32_pops; 2462 else 2463 sport->port.ops = &lpuart_pops; 2464 sport->port.flags = UPF_BOOT_AUTOCONF; 2465 2466 if (lpuart_is_32(sport)) 2467 sport->port.rs485_config = lpuart32_config_rs485; 2468 else 2469 sport->port.rs485_config = lpuart_config_rs485; 2470 2471 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 2472 if (IS_ERR(sport->ipg_clk)) { 2473 ret = PTR_ERR(sport->ipg_clk); 2474 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); 2475 return ret; 2476 } 2477 2478 sport->baud_clk = NULL; 2479 if (is_imx8qxp_lpuart(sport)) { 2480 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); 2481 if (IS_ERR(sport->baud_clk)) { 2482 ret = PTR_ERR(sport->baud_clk); 2483 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); 2484 return ret; 2485 } 2486 } 2487 2488 ret = lpuart_enable_clks(sport); 2489 if (ret) 2490 return ret; 2491 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); 2492 2493 lpuart_ports[sport->port.line] = sport; 2494 2495 platform_set_drvdata(pdev, &sport->port); 2496 2497 if (lpuart_is_32(sport)) { 2498 lpuart_reg.cons = LPUART32_CONSOLE; 2499 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0, 2500 DRIVER_NAME, sport); 2501 } else { 2502 lpuart_reg.cons = LPUART_CONSOLE; 2503 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0, 2504 DRIVER_NAME, sport); 2505 } 2506 2507 if (ret) 2508 goto failed_irq_request; 2509 2510 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2511 if (ret) 2512 goto failed_attach_port; 2513 2514 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2515 2516 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX) 2517 dev_err(&pdev->dev, "driver doesn't support RX during TX\n"); 2518 2519 if (sport->port.rs485.delay_rts_before_send || 2520 sport->port.rs485.delay_rts_after_send) 2521 dev_err(&pdev->dev, "driver doesn't support RTS delays\n"); 2522 2523 sport->port.rs485_config(&sport->port, &sport->port.rs485); 2524 2525 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx"); 2526 if (!sport->dma_tx_chan) 2527 dev_info(sport->port.dev, "DMA tx channel request failed, " 2528 "operating without tx DMA\n"); 2529 2530 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx"); 2531 if (!sport->dma_rx_chan) 2532 dev_info(sport->port.dev, "DMA rx channel request failed, " 2533 "operating without rx DMA\n"); 2534 2535 return 0; 2536 2537 failed_attach_port: 2538 failed_irq_request: 2539 lpuart_disable_clks(sport); 2540 return ret; 2541 } 2542 2543 static int lpuart_remove(struct platform_device *pdev) 2544 { 2545 struct lpuart_port *sport = platform_get_drvdata(pdev); 2546 2547 uart_remove_one_port(&lpuart_reg, &sport->port); 2548 2549 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); 2550 2551 lpuart_disable_clks(sport); 2552 2553 if (sport->dma_tx_chan) 2554 dma_release_channel(sport->dma_tx_chan); 2555 2556 if (sport->dma_rx_chan) 2557 dma_release_channel(sport->dma_rx_chan); 2558 2559 return 0; 2560 } 2561 2562 #ifdef CONFIG_PM_SLEEP 2563 static int lpuart_suspend(struct device *dev) 2564 { 2565 struct lpuart_port *sport = dev_get_drvdata(dev); 2566 unsigned long temp; 2567 bool irq_wake; 2568 2569 if (lpuart_is_32(sport)) { 2570 /* disable Rx/Tx and interrupts */ 2571 temp = lpuart32_read(&sport->port, UARTCTRL); 2572 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2573 lpuart32_write(&sport->port, temp, UARTCTRL); 2574 } else { 2575 /* disable Rx/Tx and interrupts */ 2576 temp = readb(sport->port.membase + UARTCR2); 2577 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2578 writeb(temp, sport->port.membase + UARTCR2); 2579 } 2580 2581 uart_suspend_port(&lpuart_reg, &sport->port); 2582 2583 /* uart_suspend_port() might set wakeup flag */ 2584 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2585 2586 if (sport->lpuart_dma_rx_use) { 2587 /* 2588 * EDMA driver during suspend will forcefully release any 2589 * non-idle DMA channels. If port wakeup is enabled or if port 2590 * is console port or 'no_console_suspend' is set the Rx DMA 2591 * cannot resume as as expected, hence gracefully release the 2592 * Rx DMA path before suspend and start Rx DMA path on resume. 2593 */ 2594 if (irq_wake) { 2595 del_timer_sync(&sport->lpuart_timer); 2596 lpuart_dma_rx_free(&sport->port); 2597 } 2598 2599 /* Disable Rx DMA to use UART port as wakeup source */ 2600 if (lpuart_is_32(sport)) { 2601 temp = lpuart32_read(&sport->port, UARTBAUD); 2602 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, 2603 UARTBAUD); 2604 } else { 2605 writeb(readb(sport->port.membase + UARTCR5) & 2606 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 2607 } 2608 } 2609 2610 if (sport->lpuart_dma_tx_use) { 2611 sport->dma_tx_in_progress = false; 2612 dmaengine_terminate_all(sport->dma_tx_chan); 2613 } 2614 2615 if (sport->port.suspended && !irq_wake) 2616 lpuart_disable_clks(sport); 2617 2618 return 0; 2619 } 2620 2621 static int lpuart_resume(struct device *dev) 2622 { 2623 struct lpuart_port *sport = dev_get_drvdata(dev); 2624 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2625 2626 if (sport->port.suspended && !irq_wake) 2627 lpuart_enable_clks(sport); 2628 2629 if (lpuart_is_32(sport)) 2630 lpuart32_setup_watermark_enable(sport); 2631 else 2632 lpuart_setup_watermark_enable(sport); 2633 2634 if (sport->lpuart_dma_rx_use) { 2635 if (irq_wake) { 2636 if (!lpuart_start_rx_dma(sport)) 2637 rx_dma_timer_init(sport); 2638 else 2639 sport->lpuart_dma_rx_use = false; 2640 } 2641 } 2642 2643 lpuart_tx_dma_startup(sport); 2644 2645 if (lpuart_is_32(sport)) 2646 lpuart32_configure(sport); 2647 2648 uart_resume_port(&lpuart_reg, &sport->port); 2649 2650 return 0; 2651 } 2652 #endif 2653 2654 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2655 2656 static struct platform_driver lpuart_driver = { 2657 .probe = lpuart_probe, 2658 .remove = lpuart_remove, 2659 .driver = { 2660 .name = "fsl-lpuart", 2661 .of_match_table = lpuart_dt_ids, 2662 .pm = &lpuart_pm_ops, 2663 }, 2664 }; 2665 2666 static int __init lpuart_serial_init(void) 2667 { 2668 int ret = uart_register_driver(&lpuart_reg); 2669 2670 if (ret) 2671 return ret; 2672 2673 ret = platform_driver_register(&lpuart_driver); 2674 if (ret) 2675 uart_unregister_driver(&lpuart_reg); 2676 2677 return ret; 2678 } 2679 2680 static void __exit lpuart_serial_exit(void) 2681 { 2682 ida_destroy(&fsl_lpuart_ida); 2683 platform_driver_unregister(&lpuart_driver); 2684 uart_unregister_driver(&lpuart_reg); 2685 } 2686 2687 module_init(lpuart_serial_init); 2688 module_exit(lpuart_serial_exit); 2689 2690 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2691 MODULE_LICENSE("GPL v2"); 2692