1 /* 2 * Freescale lpuart serial port driver 3 * 4 * Copyright 2012-2014 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 13 #define SUPPORT_SYSRQ 14 #endif 15 16 #include <linux/clk.h> 17 #include <linux/console.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/dmaengine.h> 20 #include <linux/dmapool.h> 21 #include <linux/io.h> 22 #include <linux/irq.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/of_dma.h> 27 #include <linux/serial_core.h> 28 #include <linux/slab.h> 29 #include <linux/tty_flip.h> 30 31 /* All registers are 8-bit width */ 32 #define UARTBDH 0x00 33 #define UARTBDL 0x01 34 #define UARTCR1 0x02 35 #define UARTCR2 0x03 36 #define UARTSR1 0x04 37 #define UARTCR3 0x06 38 #define UARTDR 0x07 39 #define UARTCR4 0x0a 40 #define UARTCR5 0x0b 41 #define UARTMODEM 0x0d 42 #define UARTPFIFO 0x10 43 #define UARTCFIFO 0x11 44 #define UARTSFIFO 0x12 45 #define UARTTWFIFO 0x13 46 #define UARTTCFIFO 0x14 47 #define UARTRWFIFO 0x15 48 49 #define UARTBDH_LBKDIE 0x80 50 #define UARTBDH_RXEDGIE 0x40 51 #define UARTBDH_SBR_MASK 0x1f 52 53 #define UARTCR1_LOOPS 0x80 54 #define UARTCR1_RSRC 0x20 55 #define UARTCR1_M 0x10 56 #define UARTCR1_WAKE 0x08 57 #define UARTCR1_ILT 0x04 58 #define UARTCR1_PE 0x02 59 #define UARTCR1_PT 0x01 60 61 #define UARTCR2_TIE 0x80 62 #define UARTCR2_TCIE 0x40 63 #define UARTCR2_RIE 0x20 64 #define UARTCR2_ILIE 0x10 65 #define UARTCR2_TE 0x08 66 #define UARTCR2_RE 0x04 67 #define UARTCR2_RWU 0x02 68 #define UARTCR2_SBK 0x01 69 70 #define UARTSR1_TDRE 0x80 71 #define UARTSR1_TC 0x40 72 #define UARTSR1_RDRF 0x20 73 #define UARTSR1_IDLE 0x10 74 #define UARTSR1_OR 0x08 75 #define UARTSR1_NF 0x04 76 #define UARTSR1_FE 0x02 77 #define UARTSR1_PE 0x01 78 79 #define UARTCR3_R8 0x80 80 #define UARTCR3_T8 0x40 81 #define UARTCR3_TXDIR 0x20 82 #define UARTCR3_TXINV 0x10 83 #define UARTCR3_ORIE 0x08 84 #define UARTCR3_NEIE 0x04 85 #define UARTCR3_FEIE 0x02 86 #define UARTCR3_PEIE 0x01 87 88 #define UARTCR4_MAEN1 0x80 89 #define UARTCR4_MAEN2 0x40 90 #define UARTCR4_M10 0x20 91 #define UARTCR4_BRFA_MASK 0x1f 92 #define UARTCR4_BRFA_OFF 0 93 94 #define UARTCR5_TDMAS 0x80 95 #define UARTCR5_RDMAS 0x20 96 97 #define UARTMODEM_RXRTSE 0x08 98 #define UARTMODEM_TXRTSPOL 0x04 99 #define UARTMODEM_TXRTSE 0x02 100 #define UARTMODEM_TXCTSE 0x01 101 102 #define UARTPFIFO_TXFE 0x80 103 #define UARTPFIFO_FIFOSIZE_MASK 0x7 104 #define UARTPFIFO_TXSIZE_OFF 4 105 #define UARTPFIFO_RXFE 0x08 106 #define UARTPFIFO_RXSIZE_OFF 0 107 108 #define UARTCFIFO_TXFLUSH 0x80 109 #define UARTCFIFO_RXFLUSH 0x40 110 #define UARTCFIFO_RXOFE 0x04 111 #define UARTCFIFO_TXOFE 0x02 112 #define UARTCFIFO_RXUFE 0x01 113 114 #define UARTSFIFO_TXEMPT 0x80 115 #define UARTSFIFO_RXEMPT 0x40 116 #define UARTSFIFO_RXOF 0x04 117 #define UARTSFIFO_TXOF 0x02 118 #define UARTSFIFO_RXUF 0x01 119 120 /* 32-bit register defination */ 121 #define UARTBAUD 0x00 122 #define UARTSTAT 0x04 123 #define UARTCTRL 0x08 124 #define UARTDATA 0x0C 125 #define UARTMATCH 0x10 126 #define UARTMODIR 0x14 127 #define UARTFIFO 0x18 128 #define UARTWATER 0x1c 129 130 #define UARTBAUD_MAEN1 0x80000000 131 #define UARTBAUD_MAEN2 0x40000000 132 #define UARTBAUD_M10 0x20000000 133 #define UARTBAUD_TDMAE 0x00800000 134 #define UARTBAUD_RDMAE 0x00200000 135 #define UARTBAUD_MATCFG 0x00400000 136 #define UARTBAUD_BOTHEDGE 0x00020000 137 #define UARTBAUD_RESYNCDIS 0x00010000 138 #define UARTBAUD_LBKDIE 0x00008000 139 #define UARTBAUD_RXEDGIE 0x00004000 140 #define UARTBAUD_SBNS 0x00002000 141 #define UARTBAUD_SBR 0x00000000 142 #define UARTBAUD_SBR_MASK 0x1fff 143 144 #define UARTSTAT_LBKDIF 0x80000000 145 #define UARTSTAT_RXEDGIF 0x40000000 146 #define UARTSTAT_MSBF 0x20000000 147 #define UARTSTAT_RXINV 0x10000000 148 #define UARTSTAT_RWUID 0x08000000 149 #define UARTSTAT_BRK13 0x04000000 150 #define UARTSTAT_LBKDE 0x02000000 151 #define UARTSTAT_RAF 0x01000000 152 #define UARTSTAT_TDRE 0x00800000 153 #define UARTSTAT_TC 0x00400000 154 #define UARTSTAT_RDRF 0x00200000 155 #define UARTSTAT_IDLE 0x00100000 156 #define UARTSTAT_OR 0x00080000 157 #define UARTSTAT_NF 0x00040000 158 #define UARTSTAT_FE 0x00020000 159 #define UARTSTAT_PE 0x00010000 160 #define UARTSTAT_MA1F 0x00008000 161 #define UARTSTAT_M21F 0x00004000 162 163 #define UARTCTRL_R8T9 0x80000000 164 #define UARTCTRL_R9T8 0x40000000 165 #define UARTCTRL_TXDIR 0x20000000 166 #define UARTCTRL_TXINV 0x10000000 167 #define UARTCTRL_ORIE 0x08000000 168 #define UARTCTRL_NEIE 0x04000000 169 #define UARTCTRL_FEIE 0x02000000 170 #define UARTCTRL_PEIE 0x01000000 171 #define UARTCTRL_TIE 0x00800000 172 #define UARTCTRL_TCIE 0x00400000 173 #define UARTCTRL_RIE 0x00200000 174 #define UARTCTRL_ILIE 0x00100000 175 #define UARTCTRL_TE 0x00080000 176 #define UARTCTRL_RE 0x00040000 177 #define UARTCTRL_RWU 0x00020000 178 #define UARTCTRL_SBK 0x00010000 179 #define UARTCTRL_MA1IE 0x00008000 180 #define UARTCTRL_MA2IE 0x00004000 181 #define UARTCTRL_IDLECFG 0x00000100 182 #define UARTCTRL_LOOPS 0x00000080 183 #define UARTCTRL_DOZEEN 0x00000040 184 #define UARTCTRL_RSRC 0x00000020 185 #define UARTCTRL_M 0x00000010 186 #define UARTCTRL_WAKE 0x00000008 187 #define UARTCTRL_ILT 0x00000004 188 #define UARTCTRL_PE 0x00000002 189 #define UARTCTRL_PT 0x00000001 190 191 #define UARTDATA_NOISY 0x00008000 192 #define UARTDATA_PARITYE 0x00004000 193 #define UARTDATA_FRETSC 0x00002000 194 #define UARTDATA_RXEMPT 0x00001000 195 #define UARTDATA_IDLINE 0x00000800 196 #define UARTDATA_MASK 0x3ff 197 198 #define UARTMODIR_IREN 0x00020000 199 #define UARTMODIR_TXCTSSRC 0x00000020 200 #define UARTMODIR_TXCTSC 0x00000010 201 #define UARTMODIR_RXRTSE 0x00000008 202 #define UARTMODIR_TXRTSPOL 0x00000004 203 #define UARTMODIR_TXRTSE 0x00000002 204 #define UARTMODIR_TXCTSE 0x00000001 205 206 #define UARTFIFO_TXEMPT 0x00800000 207 #define UARTFIFO_RXEMPT 0x00400000 208 #define UARTFIFO_TXOF 0x00020000 209 #define UARTFIFO_RXUF 0x00010000 210 #define UARTFIFO_TXFLUSH 0x00008000 211 #define UARTFIFO_RXFLUSH 0x00004000 212 #define UARTFIFO_TXOFE 0x00000200 213 #define UARTFIFO_RXUFE 0x00000100 214 #define UARTFIFO_TXFE 0x00000080 215 #define UARTFIFO_FIFOSIZE_MASK 0x7 216 #define UARTFIFO_TXSIZE_OFF 4 217 #define UARTFIFO_RXFE 0x00000008 218 #define UARTFIFO_RXSIZE_OFF 0 219 220 #define UARTWATER_COUNT_MASK 0xff 221 #define UARTWATER_TXCNT_OFF 8 222 #define UARTWATER_RXCNT_OFF 24 223 #define UARTWATER_WATER_MASK 0xff 224 #define UARTWATER_TXWATER_OFF 0 225 #define UARTWATER_RXWATER_OFF 16 226 227 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 228 #define DMA_RX_TIMEOUT (10) 229 230 #define DRIVER_NAME "fsl-lpuart" 231 #define DEV_NAME "ttyLP" 232 #define UART_NR 6 233 234 struct lpuart_port { 235 struct uart_port port; 236 struct clk *clk; 237 unsigned int txfifo_size; 238 unsigned int rxfifo_size; 239 bool lpuart32; 240 241 bool lpuart_dma_tx_use; 242 bool lpuart_dma_rx_use; 243 struct dma_chan *dma_tx_chan; 244 struct dma_chan *dma_rx_chan; 245 struct dma_async_tx_descriptor *dma_tx_desc; 246 struct dma_async_tx_descriptor *dma_rx_desc; 247 dma_cookie_t dma_tx_cookie; 248 dma_cookie_t dma_rx_cookie; 249 unsigned int dma_tx_bytes; 250 unsigned int dma_rx_bytes; 251 bool dma_tx_in_progress; 252 unsigned int dma_rx_timeout; 253 struct timer_list lpuart_timer; 254 struct scatterlist rx_sgl, tx_sgl[2]; 255 struct circ_buf rx_ring; 256 int rx_dma_rng_buf_len; 257 unsigned int dma_tx_nents; 258 wait_queue_head_t dma_wait; 259 }; 260 261 static const struct of_device_id lpuart_dt_ids[] = { 262 { 263 .compatible = "fsl,vf610-lpuart", 264 }, 265 { 266 .compatible = "fsl,ls1021a-lpuart", 267 }, 268 { /* sentinel */ } 269 }; 270 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 271 272 /* Forward declare this for the dma callbacks*/ 273 static void lpuart_dma_tx_complete(void *arg); 274 275 static u32 lpuart32_read(void __iomem *addr) 276 { 277 return ioread32be(addr); 278 } 279 280 static void lpuart32_write(u32 val, void __iomem *addr) 281 { 282 iowrite32be(val, addr); 283 } 284 285 static void lpuart_stop_tx(struct uart_port *port) 286 { 287 unsigned char temp; 288 289 temp = readb(port->membase + UARTCR2); 290 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 291 writeb(temp, port->membase + UARTCR2); 292 } 293 294 static void lpuart32_stop_tx(struct uart_port *port) 295 { 296 unsigned long temp; 297 298 temp = lpuart32_read(port->membase + UARTCTRL); 299 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 300 lpuart32_write(temp, port->membase + UARTCTRL); 301 } 302 303 static void lpuart_stop_rx(struct uart_port *port) 304 { 305 unsigned char temp; 306 307 temp = readb(port->membase + UARTCR2); 308 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 309 } 310 311 static void lpuart32_stop_rx(struct uart_port *port) 312 { 313 unsigned long temp; 314 315 temp = lpuart32_read(port->membase + UARTCTRL); 316 lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL); 317 } 318 319 static void lpuart_dma_tx(struct lpuart_port *sport) 320 { 321 struct circ_buf *xmit = &sport->port.state->xmit; 322 struct scatterlist *sgl = sport->tx_sgl; 323 struct device *dev = sport->port.dev; 324 int ret; 325 326 if (sport->dma_tx_in_progress) 327 return; 328 329 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 330 331 if (xmit->tail < xmit->head) { 332 sport->dma_tx_nents = 1; 333 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 334 } else { 335 sport->dma_tx_nents = 2; 336 sg_init_table(sgl, 2); 337 sg_set_buf(sgl, xmit->buf + xmit->tail, 338 UART_XMIT_SIZE - xmit->tail); 339 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 340 } 341 342 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 343 if (!ret) { 344 dev_err(dev, "DMA mapping error for TX.\n"); 345 return; 346 } 347 348 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl, 349 sport->dma_tx_nents, 350 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 351 if (!sport->dma_tx_desc) { 352 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 353 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 354 return; 355 } 356 357 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 358 sport->dma_tx_desc->callback_param = sport; 359 sport->dma_tx_in_progress = true; 360 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 361 dma_async_issue_pending(sport->dma_tx_chan); 362 363 } 364 365 static void lpuart_dma_tx_complete(void *arg) 366 { 367 struct lpuart_port *sport = arg; 368 struct scatterlist *sgl = &sport->tx_sgl[0]; 369 struct circ_buf *xmit = &sport->port.state->xmit; 370 unsigned long flags; 371 372 spin_lock_irqsave(&sport->port.lock, flags); 373 374 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 375 376 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 377 378 sport->port.icount.tx += sport->dma_tx_bytes; 379 sport->dma_tx_in_progress = false; 380 spin_unlock_irqrestore(&sport->port.lock, flags); 381 382 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 383 uart_write_wakeup(&sport->port); 384 385 if (waitqueue_active(&sport->dma_wait)) { 386 wake_up(&sport->dma_wait); 387 return; 388 } 389 390 spin_lock_irqsave(&sport->port.lock, flags); 391 392 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 393 lpuart_dma_tx(sport); 394 395 spin_unlock_irqrestore(&sport->port.lock, flags); 396 } 397 398 static int lpuart_dma_tx_request(struct uart_port *port) 399 { 400 struct lpuart_port *sport = container_of(port, 401 struct lpuart_port, port); 402 struct dma_slave_config dma_tx_sconfig = {}; 403 int ret; 404 405 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR; 406 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 407 dma_tx_sconfig.dst_maxburst = 1; 408 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 409 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 410 411 if (ret) { 412 dev_err(sport->port.dev, 413 "DMA slave config failed, err = %d\n", ret); 414 return ret; 415 } 416 417 return 0; 418 } 419 420 static void lpuart_flush_buffer(struct uart_port *port) 421 { 422 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 423 424 if (sport->lpuart_dma_tx_use) { 425 if (sport->dma_tx_in_progress) { 426 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 427 sport->dma_tx_nents, DMA_TO_DEVICE); 428 sport->dma_tx_in_progress = false; 429 } 430 dmaengine_terminate_all(sport->dma_tx_chan); 431 } 432 } 433 434 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 435 { 436 struct circ_buf *xmit = &sport->port.state->xmit; 437 438 while (!uart_circ_empty(xmit) && 439 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 440 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 441 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 442 sport->port.icount.tx++; 443 } 444 445 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 446 uart_write_wakeup(&sport->port); 447 448 if (uart_circ_empty(xmit)) 449 lpuart_stop_tx(&sport->port); 450 } 451 452 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 453 { 454 struct circ_buf *xmit = &sport->port.state->xmit; 455 unsigned long txcnt; 456 457 txcnt = lpuart32_read(sport->port.membase + UARTWATER); 458 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 459 txcnt &= UARTWATER_COUNT_MASK; 460 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 461 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA); 462 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 463 sport->port.icount.tx++; 464 txcnt = lpuart32_read(sport->port.membase + UARTWATER); 465 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 466 txcnt &= UARTWATER_COUNT_MASK; 467 } 468 469 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 470 uart_write_wakeup(&sport->port); 471 472 if (uart_circ_empty(xmit)) 473 lpuart32_stop_tx(&sport->port); 474 } 475 476 static void lpuart_start_tx(struct uart_port *port) 477 { 478 struct lpuart_port *sport = container_of(port, 479 struct lpuart_port, port); 480 struct circ_buf *xmit = &sport->port.state->xmit; 481 unsigned char temp; 482 483 temp = readb(port->membase + UARTCR2); 484 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 485 486 if (sport->lpuart_dma_tx_use) { 487 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) 488 lpuart_dma_tx(sport); 489 } else { 490 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 491 lpuart_transmit_buffer(sport); 492 } 493 } 494 495 static void lpuart32_start_tx(struct uart_port *port) 496 { 497 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 498 unsigned long temp; 499 500 temp = lpuart32_read(port->membase + UARTCTRL); 501 lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL); 502 503 if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE) 504 lpuart32_transmit_buffer(sport); 505 } 506 507 /* return TIOCSER_TEMT when transmitter is not busy */ 508 static unsigned int lpuart_tx_empty(struct uart_port *port) 509 { 510 struct lpuart_port *sport = container_of(port, 511 struct lpuart_port, port); 512 unsigned char sr1 = readb(port->membase + UARTSR1); 513 unsigned char sfifo = readb(port->membase + UARTSFIFO); 514 515 if (sport->dma_tx_in_progress) 516 return 0; 517 518 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 519 return TIOCSER_TEMT; 520 521 return 0; 522 } 523 524 static unsigned int lpuart32_tx_empty(struct uart_port *port) 525 { 526 return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ? 527 TIOCSER_TEMT : 0; 528 } 529 530 static irqreturn_t lpuart_txint(int irq, void *dev_id) 531 { 532 struct lpuart_port *sport = dev_id; 533 struct circ_buf *xmit = &sport->port.state->xmit; 534 unsigned long flags; 535 536 spin_lock_irqsave(&sport->port.lock, flags); 537 if (sport->port.x_char) { 538 if (sport->lpuart32) 539 lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA); 540 else 541 writeb(sport->port.x_char, sport->port.membase + UARTDR); 542 goto out; 543 } 544 545 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 546 if (sport->lpuart32) 547 lpuart32_stop_tx(&sport->port); 548 else 549 lpuart_stop_tx(&sport->port); 550 goto out; 551 } 552 553 if (sport->lpuart32) 554 lpuart32_transmit_buffer(sport); 555 else 556 lpuart_transmit_buffer(sport); 557 558 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 559 uart_write_wakeup(&sport->port); 560 561 out: 562 spin_unlock_irqrestore(&sport->port.lock, flags); 563 return IRQ_HANDLED; 564 } 565 566 static irqreturn_t lpuart_rxint(int irq, void *dev_id) 567 { 568 struct lpuart_port *sport = dev_id; 569 unsigned int flg, ignored = 0; 570 struct tty_port *port = &sport->port.state->port; 571 unsigned long flags; 572 unsigned char rx, sr; 573 574 spin_lock_irqsave(&sport->port.lock, flags); 575 576 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 577 flg = TTY_NORMAL; 578 sport->port.icount.rx++; 579 /* 580 * to clear the FE, OR, NF, FE, PE flags, 581 * read SR1 then read DR 582 */ 583 sr = readb(sport->port.membase + UARTSR1); 584 rx = readb(sport->port.membase + UARTDR); 585 586 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 587 continue; 588 589 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 590 if (sr & UARTSR1_PE) 591 sport->port.icount.parity++; 592 else if (sr & UARTSR1_FE) 593 sport->port.icount.frame++; 594 595 if (sr & UARTSR1_OR) 596 sport->port.icount.overrun++; 597 598 if (sr & sport->port.ignore_status_mask) { 599 if (++ignored > 100) 600 goto out; 601 continue; 602 } 603 604 sr &= sport->port.read_status_mask; 605 606 if (sr & UARTSR1_PE) 607 flg = TTY_PARITY; 608 else if (sr & UARTSR1_FE) 609 flg = TTY_FRAME; 610 611 if (sr & UARTSR1_OR) 612 flg = TTY_OVERRUN; 613 614 #ifdef SUPPORT_SYSRQ 615 sport->port.sysrq = 0; 616 #endif 617 } 618 619 tty_insert_flip_char(port, rx, flg); 620 } 621 622 out: 623 spin_unlock_irqrestore(&sport->port.lock, flags); 624 625 tty_flip_buffer_push(port); 626 return IRQ_HANDLED; 627 } 628 629 static irqreturn_t lpuart32_rxint(int irq, void *dev_id) 630 { 631 struct lpuart_port *sport = dev_id; 632 unsigned int flg, ignored = 0; 633 struct tty_port *port = &sport->port.state->port; 634 unsigned long flags; 635 unsigned long rx, sr; 636 637 spin_lock_irqsave(&sport->port.lock, flags); 638 639 while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) { 640 flg = TTY_NORMAL; 641 sport->port.icount.rx++; 642 /* 643 * to clear the FE, OR, NF, FE, PE flags, 644 * read STAT then read DATA reg 645 */ 646 sr = lpuart32_read(sport->port.membase + UARTSTAT); 647 rx = lpuart32_read(sport->port.membase + UARTDATA); 648 rx &= 0x3ff; 649 650 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 651 continue; 652 653 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 654 if (sr & UARTSTAT_PE) 655 sport->port.icount.parity++; 656 else if (sr & UARTSTAT_FE) 657 sport->port.icount.frame++; 658 659 if (sr & UARTSTAT_OR) 660 sport->port.icount.overrun++; 661 662 if (sr & sport->port.ignore_status_mask) { 663 if (++ignored > 100) 664 goto out; 665 continue; 666 } 667 668 sr &= sport->port.read_status_mask; 669 670 if (sr & UARTSTAT_PE) 671 flg = TTY_PARITY; 672 else if (sr & UARTSTAT_FE) 673 flg = TTY_FRAME; 674 675 if (sr & UARTSTAT_OR) 676 flg = TTY_OVERRUN; 677 678 #ifdef SUPPORT_SYSRQ 679 sport->port.sysrq = 0; 680 #endif 681 } 682 683 tty_insert_flip_char(port, rx, flg); 684 } 685 686 out: 687 spin_unlock_irqrestore(&sport->port.lock, flags); 688 689 tty_flip_buffer_push(port); 690 return IRQ_HANDLED; 691 } 692 693 static irqreturn_t lpuart_int(int irq, void *dev_id) 694 { 695 struct lpuart_port *sport = dev_id; 696 unsigned char sts; 697 698 sts = readb(sport->port.membase + UARTSR1); 699 700 if (sts & UARTSR1_RDRF) 701 lpuart_rxint(irq, dev_id); 702 703 if (sts & UARTSR1_TDRE) 704 lpuart_txint(irq, dev_id); 705 706 return IRQ_HANDLED; 707 } 708 709 static irqreturn_t lpuart32_int(int irq, void *dev_id) 710 { 711 struct lpuart_port *sport = dev_id; 712 unsigned long sts, rxcount; 713 714 sts = lpuart32_read(sport->port.membase + UARTSTAT); 715 rxcount = lpuart32_read(sport->port.membase + UARTWATER); 716 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 717 718 if (sts & UARTSTAT_RDRF || rxcount > 0) 719 lpuart32_rxint(irq, dev_id); 720 721 if ((sts & UARTSTAT_TDRE) && 722 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE)) 723 lpuart_txint(irq, dev_id); 724 725 lpuart32_write(sts, sport->port.membase + UARTSTAT); 726 return IRQ_HANDLED; 727 } 728 729 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 730 { 731 struct tty_port *port = &sport->port.state->port; 732 struct dma_tx_state state; 733 enum dma_status dmastat; 734 struct circ_buf *ring = &sport->rx_ring; 735 unsigned long flags; 736 int count = 0; 737 unsigned char sr; 738 739 sr = readb(sport->port.membase + UARTSR1); 740 741 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 742 /* Read DR to clear the error flags */ 743 readb(sport->port.membase + UARTDR); 744 745 if (sr & UARTSR1_PE) 746 sport->port.icount.parity++; 747 else if (sr & UARTSR1_FE) 748 sport->port.icount.frame++; 749 } 750 751 async_tx_ack(sport->dma_rx_desc); 752 753 spin_lock_irqsave(&sport->port.lock, flags); 754 755 dmastat = dmaengine_tx_status(sport->dma_rx_chan, 756 sport->dma_rx_cookie, 757 &state); 758 759 if (dmastat == DMA_ERROR) { 760 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 761 spin_unlock_irqrestore(&sport->port.lock, flags); 762 return; 763 } 764 765 /* CPU claims ownership of RX DMA buffer */ 766 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 767 768 /* 769 * ring->head points to the end of data already written by the DMA. 770 * ring->tail points to the beginning of data to be read by the 771 * framework. 772 * The current transfer size should not be larger than the dma buffer 773 * length. 774 */ 775 ring->head = sport->rx_sgl.length - state.residue; 776 BUG_ON(ring->head > sport->rx_sgl.length); 777 /* 778 * At this point ring->head may point to the first byte right after the 779 * last byte of the dma buffer: 780 * 0 <= ring->head <= sport->rx_sgl.length 781 * 782 * However ring->tail must always points inside the dma buffer: 783 * 0 <= ring->tail <= sport->rx_sgl.length - 1 784 * 785 * Since we use a ring buffer, we have to handle the case 786 * where head is lower than tail. In such a case, we first read from 787 * tail to the end of the buffer then reset tail. 788 */ 789 if (ring->head < ring->tail) { 790 count = sport->rx_sgl.length - ring->tail; 791 792 tty_insert_flip_string(port, ring->buf + ring->tail, count); 793 ring->tail = 0; 794 sport->port.icount.rx += count; 795 } 796 797 /* Finally we read data from tail to head */ 798 if (ring->tail < ring->head) { 799 count = ring->head - ring->tail; 800 tty_insert_flip_string(port, ring->buf + ring->tail, count); 801 /* Wrap ring->head if needed */ 802 if (ring->head >= sport->rx_sgl.length) 803 ring->head = 0; 804 ring->tail = ring->head; 805 sport->port.icount.rx += count; 806 } 807 808 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1, 809 DMA_FROM_DEVICE); 810 811 spin_unlock_irqrestore(&sport->port.lock, flags); 812 813 tty_flip_buffer_push(port); 814 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 815 } 816 817 static void lpuart_dma_rx_complete(void *arg) 818 { 819 struct lpuart_port *sport = arg; 820 821 lpuart_copy_rx_to_tty(sport); 822 } 823 824 static void lpuart_timer_func(unsigned long data) 825 { 826 struct lpuart_port *sport = (struct lpuart_port *)data; 827 828 lpuart_copy_rx_to_tty(sport); 829 } 830 831 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 832 { 833 struct dma_slave_config dma_rx_sconfig = {}; 834 struct circ_buf *ring = &sport->rx_ring; 835 int ret, nent; 836 int bits, baud; 837 struct tty_struct *tty = tty_port_tty_get(&sport->port.state->port); 838 struct ktermios *termios = &tty->termios; 839 840 baud = tty_get_baud_rate(tty); 841 842 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; 843 if (termios->c_cflag & PARENB) 844 bits++; 845 846 /* 847 * Calculate length of one DMA buffer size to keep latency below 848 * 10ms at any baud rate. 849 */ 850 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 851 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 852 if (sport->rx_dma_rng_buf_len < 16) 853 sport->rx_dma_rng_buf_len = 16; 854 855 ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 856 if (!ring->buf) { 857 dev_err(sport->port.dev, "Ring buf alloc failed\n"); 858 return -ENOMEM; 859 } 860 861 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 862 sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 863 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 864 865 if (!nent) { 866 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 867 return -EINVAL; 868 } 869 870 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR; 871 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 872 dma_rx_sconfig.src_maxburst = 1; 873 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 874 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig); 875 876 if (ret < 0) { 877 dev_err(sport->port.dev, 878 "DMA Rx slave config failed, err = %d\n", ret); 879 return ret; 880 } 881 882 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan, 883 sg_dma_address(&sport->rx_sgl), 884 sport->rx_sgl.length, 885 sport->rx_sgl.length / 2, 886 DMA_DEV_TO_MEM, 887 DMA_PREP_INTERRUPT); 888 if (!sport->dma_rx_desc) { 889 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 890 return -EFAULT; 891 } 892 893 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 894 sport->dma_rx_desc->callback_param = sport; 895 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 896 dma_async_issue_pending(sport->dma_rx_chan); 897 898 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 899 sport->port.membase + UARTCR5); 900 901 return 0; 902 } 903 904 static void lpuart_dma_rx_free(struct uart_port *port) 905 { 906 struct lpuart_port *sport = container_of(port, 907 struct lpuart_port, port); 908 909 if (sport->dma_rx_chan) 910 dmaengine_terminate_all(sport->dma_rx_chan); 911 912 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 913 kfree(sport->rx_ring.buf); 914 sport->rx_ring.tail = 0; 915 sport->rx_ring.head = 0; 916 sport->dma_rx_desc = NULL; 917 sport->dma_rx_cookie = -EINVAL; 918 } 919 920 static int lpuart_config_rs485(struct uart_port *port, 921 struct serial_rs485 *rs485) 922 { 923 struct lpuart_port *sport = container_of(port, 924 struct lpuart_port, port); 925 926 u8 modem = readb(sport->port.membase + UARTMODEM) & 927 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 928 writeb(modem, sport->port.membase + UARTMODEM); 929 930 if (rs485->flags & SER_RS485_ENABLED) { 931 /* Enable auto RS-485 RTS mode */ 932 modem |= UARTMODEM_TXRTSE; 933 934 /* 935 * RTS needs to be logic HIGH either during transer _or_ after 936 * transfer, other variants are not supported by the hardware. 937 */ 938 939 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 940 SER_RS485_RTS_AFTER_SEND))) 941 rs485->flags |= SER_RS485_RTS_ON_SEND; 942 943 if (rs485->flags & SER_RS485_RTS_ON_SEND && 944 rs485->flags & SER_RS485_RTS_AFTER_SEND) 945 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 946 947 /* 948 * The hardware defaults to RTS logic HIGH while transfer. 949 * Switch polarity in case RTS shall be logic HIGH 950 * after transfer. 951 * Note: UART is assumed to be active high. 952 */ 953 if (rs485->flags & SER_RS485_RTS_ON_SEND) 954 modem &= ~UARTMODEM_TXRTSPOL; 955 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 956 modem |= UARTMODEM_TXRTSPOL; 957 } 958 959 /* Store the new configuration */ 960 sport->port.rs485 = *rs485; 961 962 writeb(modem, sport->port.membase + UARTMODEM); 963 return 0; 964 } 965 966 static unsigned int lpuart_get_mctrl(struct uart_port *port) 967 { 968 unsigned int temp = 0; 969 unsigned char reg; 970 971 reg = readb(port->membase + UARTMODEM); 972 if (reg & UARTMODEM_TXCTSE) 973 temp |= TIOCM_CTS; 974 975 if (reg & UARTMODEM_RXRTSE) 976 temp |= TIOCM_RTS; 977 978 return temp; 979 } 980 981 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 982 { 983 unsigned int temp = 0; 984 unsigned long reg; 985 986 reg = lpuart32_read(port->membase + UARTMODIR); 987 if (reg & UARTMODIR_TXCTSE) 988 temp |= TIOCM_CTS; 989 990 if (reg & UARTMODIR_RXRTSE) 991 temp |= TIOCM_RTS; 992 993 return temp; 994 } 995 996 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 997 { 998 unsigned char temp; 999 struct lpuart_port *sport = container_of(port, 1000 struct lpuart_port, port); 1001 1002 /* Make sure RXRTSE bit is not set when RS485 is enabled */ 1003 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { 1004 temp = readb(sport->port.membase + UARTMODEM) & 1005 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1006 1007 if (mctrl & TIOCM_RTS) 1008 temp |= UARTMODEM_RXRTSE; 1009 1010 if (mctrl & TIOCM_CTS) 1011 temp |= UARTMODEM_TXCTSE; 1012 1013 writeb(temp, port->membase + UARTMODEM); 1014 } 1015 } 1016 1017 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1018 { 1019 unsigned long temp; 1020 1021 temp = lpuart32_read(port->membase + UARTMODIR) & 1022 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 1023 1024 if (mctrl & TIOCM_RTS) 1025 temp |= UARTMODIR_RXRTSE; 1026 1027 if (mctrl & TIOCM_CTS) 1028 temp |= UARTMODIR_TXCTSE; 1029 1030 lpuart32_write(temp, port->membase + UARTMODIR); 1031 } 1032 1033 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1034 { 1035 unsigned char temp; 1036 1037 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1038 1039 if (break_state != 0) 1040 temp |= UARTCR2_SBK; 1041 1042 writeb(temp, port->membase + UARTCR2); 1043 } 1044 1045 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1046 { 1047 unsigned long temp; 1048 1049 temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK; 1050 1051 if (break_state != 0) 1052 temp |= UARTCTRL_SBK; 1053 1054 lpuart32_write(temp, port->membase + UARTCTRL); 1055 } 1056 1057 static void lpuart_setup_watermark(struct lpuart_port *sport) 1058 { 1059 unsigned char val, cr2; 1060 unsigned char cr2_saved; 1061 1062 cr2 = readb(sport->port.membase + UARTCR2); 1063 cr2_saved = cr2; 1064 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1065 UARTCR2_RIE | UARTCR2_RE); 1066 writeb(cr2, sport->port.membase + UARTCR2); 1067 1068 val = readb(sport->port.membase + UARTPFIFO); 1069 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1070 sport->port.membase + UARTPFIFO); 1071 1072 /* flush Tx and Rx FIFO */ 1073 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1074 sport->port.membase + UARTCFIFO); 1075 1076 /* explicitly clear RDRF */ 1077 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1078 readb(sport->port.membase + UARTDR); 1079 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1080 } 1081 1082 writeb(0, sport->port.membase + UARTTWFIFO); 1083 writeb(1, sport->port.membase + UARTRWFIFO); 1084 1085 /* Restore cr2 */ 1086 writeb(cr2_saved, sport->port.membase + UARTCR2); 1087 } 1088 1089 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1090 { 1091 unsigned long val, ctrl; 1092 unsigned long ctrl_saved; 1093 1094 ctrl = lpuart32_read(sport->port.membase + UARTCTRL); 1095 ctrl_saved = ctrl; 1096 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1097 UARTCTRL_RIE | UARTCTRL_RE); 1098 lpuart32_write(ctrl, sport->port.membase + UARTCTRL); 1099 1100 /* enable FIFO mode */ 1101 val = lpuart32_read(sport->port.membase + UARTFIFO); 1102 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1103 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1104 lpuart32_write(val, sport->port.membase + UARTFIFO); 1105 1106 /* set the watermark */ 1107 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1108 lpuart32_write(val, sport->port.membase + UARTWATER); 1109 1110 /* Restore cr2 */ 1111 lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL); 1112 } 1113 1114 static void rx_dma_timer_init(struct lpuart_port *sport) 1115 { 1116 setup_timer(&sport->lpuart_timer, lpuart_timer_func, 1117 (unsigned long)sport); 1118 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1119 add_timer(&sport->lpuart_timer); 1120 } 1121 1122 static int lpuart_startup(struct uart_port *port) 1123 { 1124 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1125 int ret; 1126 unsigned long flags; 1127 unsigned char temp; 1128 1129 /* determine FIFO size and enable FIFO mode */ 1130 temp = readb(sport->port.membase + UARTPFIFO); 1131 1132 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) & 1133 UARTPFIFO_FIFOSIZE_MASK) + 1); 1134 1135 sport->port.fifosize = sport->txfifo_size; 1136 1137 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) & 1138 UARTPFIFO_FIFOSIZE_MASK) + 1); 1139 1140 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0, 1141 DRIVER_NAME, sport); 1142 if (ret) 1143 return ret; 1144 1145 spin_lock_irqsave(&sport->port.lock, flags); 1146 1147 lpuart_setup_watermark(sport); 1148 1149 temp = readb(sport->port.membase + UARTCR2); 1150 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 1151 writeb(temp, sport->port.membase + UARTCR2); 1152 1153 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) { 1154 /* set Rx DMA timeout */ 1155 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1156 if (!sport->dma_rx_timeout) 1157 sport->dma_rx_timeout = 1; 1158 1159 sport->lpuart_dma_rx_use = true; 1160 rx_dma_timer_init(sport); 1161 } else { 1162 sport->lpuart_dma_rx_use = false; 1163 } 1164 1165 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) { 1166 init_waitqueue_head(&sport->dma_wait); 1167 sport->lpuart_dma_tx_use = true; 1168 temp = readb(port->membase + UARTCR5); 1169 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5); 1170 } else { 1171 sport->lpuart_dma_tx_use = false; 1172 } 1173 1174 spin_unlock_irqrestore(&sport->port.lock, flags); 1175 1176 return 0; 1177 } 1178 1179 static int lpuart32_startup(struct uart_port *port) 1180 { 1181 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1182 int ret; 1183 unsigned long flags; 1184 unsigned long temp; 1185 1186 /* determine FIFO size */ 1187 temp = lpuart32_read(sport->port.membase + UARTFIFO); 1188 1189 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) & 1190 UARTFIFO_FIFOSIZE_MASK) - 1); 1191 1192 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) & 1193 UARTFIFO_FIFOSIZE_MASK) - 1); 1194 1195 ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0, 1196 DRIVER_NAME, sport); 1197 if (ret) 1198 return ret; 1199 1200 spin_lock_irqsave(&sport->port.lock, flags); 1201 1202 lpuart32_setup_watermark(sport); 1203 1204 temp = lpuart32_read(sport->port.membase + UARTCTRL); 1205 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE); 1206 temp |= UARTCTRL_ILIE; 1207 lpuart32_write(temp, sport->port.membase + UARTCTRL); 1208 1209 spin_unlock_irqrestore(&sport->port.lock, flags); 1210 return 0; 1211 } 1212 1213 static void lpuart_shutdown(struct uart_port *port) 1214 { 1215 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1216 unsigned char temp; 1217 unsigned long flags; 1218 1219 spin_lock_irqsave(&port->lock, flags); 1220 1221 /* disable Rx/Tx and interrupts */ 1222 temp = readb(port->membase + UARTCR2); 1223 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1224 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1225 writeb(temp, port->membase + UARTCR2); 1226 1227 spin_unlock_irqrestore(&port->lock, flags); 1228 1229 devm_free_irq(port->dev, port->irq, sport); 1230 1231 if (sport->lpuart_dma_rx_use) { 1232 del_timer_sync(&sport->lpuart_timer); 1233 lpuart_dma_rx_free(&sport->port); 1234 } 1235 1236 if (sport->lpuart_dma_tx_use) { 1237 if (wait_event_interruptible(sport->dma_wait, 1238 !sport->dma_tx_in_progress) != false) { 1239 sport->dma_tx_in_progress = false; 1240 dmaengine_terminate_all(sport->dma_tx_chan); 1241 } 1242 1243 lpuart_stop_tx(port); 1244 } 1245 } 1246 1247 static void lpuart32_shutdown(struct uart_port *port) 1248 { 1249 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1250 unsigned long temp; 1251 unsigned long flags; 1252 1253 spin_lock_irqsave(&port->lock, flags); 1254 1255 /* disable Rx/Tx and interrupts */ 1256 temp = lpuart32_read(port->membase + UARTCTRL); 1257 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1258 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1259 lpuart32_write(temp, port->membase + UARTCTRL); 1260 1261 spin_unlock_irqrestore(&port->lock, flags); 1262 1263 devm_free_irq(port->dev, port->irq, sport); 1264 } 1265 1266 static void 1267 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1268 struct ktermios *old) 1269 { 1270 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1271 unsigned long flags; 1272 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1273 unsigned int baud; 1274 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1275 unsigned int sbr, brfa; 1276 1277 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1278 old_cr2 = readb(sport->port.membase + UARTCR2); 1279 cr3 = readb(sport->port.membase + UARTCR3); 1280 cr4 = readb(sport->port.membase + UARTCR4); 1281 bdh = readb(sport->port.membase + UARTBDH); 1282 modem = readb(sport->port.membase + UARTMODEM); 1283 /* 1284 * only support CS8 and CS7, and for CS7 must enable PE. 1285 * supported mode: 1286 * - (7,e/o,1) 1287 * - (8,n,1) 1288 * - (8,m/s,1) 1289 * - (8,e/o,1) 1290 */ 1291 while ((termios->c_cflag & CSIZE) != CS8 && 1292 (termios->c_cflag & CSIZE) != CS7) { 1293 termios->c_cflag &= ~CSIZE; 1294 termios->c_cflag |= old_csize; 1295 old_csize = CS8; 1296 } 1297 1298 if ((termios->c_cflag & CSIZE) == CS8 || 1299 (termios->c_cflag & CSIZE) == CS7) 1300 cr1 = old_cr1 & ~UARTCR1_M; 1301 1302 if (termios->c_cflag & CMSPAR) { 1303 if ((termios->c_cflag & CSIZE) != CS8) { 1304 termios->c_cflag &= ~CSIZE; 1305 termios->c_cflag |= CS8; 1306 } 1307 cr1 |= UARTCR1_M; 1308 } 1309 1310 /* 1311 * When auto RS-485 RTS mode is enabled, 1312 * hardware flow control need to be disabled. 1313 */ 1314 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1315 termios->c_cflag &= ~CRTSCTS; 1316 1317 if (termios->c_cflag & CRTSCTS) { 1318 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1319 } else { 1320 termios->c_cflag &= ~CRTSCTS; 1321 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1322 } 1323 1324 if (termios->c_cflag & CSTOPB) 1325 termios->c_cflag &= ~CSTOPB; 1326 1327 /* parity must be enabled when CS7 to match 8-bits format */ 1328 if ((termios->c_cflag & CSIZE) == CS7) 1329 termios->c_cflag |= PARENB; 1330 1331 if ((termios->c_cflag & PARENB)) { 1332 if (termios->c_cflag & CMSPAR) { 1333 cr1 &= ~UARTCR1_PE; 1334 if (termios->c_cflag & PARODD) 1335 cr3 |= UARTCR3_T8; 1336 else 1337 cr3 &= ~UARTCR3_T8; 1338 } else { 1339 cr1 |= UARTCR1_PE; 1340 if ((termios->c_cflag & CSIZE) == CS8) 1341 cr1 |= UARTCR1_M; 1342 if (termios->c_cflag & PARODD) 1343 cr1 |= UARTCR1_PT; 1344 else 1345 cr1 &= ~UARTCR1_PT; 1346 } 1347 } 1348 1349 /* ask the core to calculate the divisor */ 1350 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1351 1352 spin_lock_irqsave(&sport->port.lock, flags); 1353 1354 sport->port.read_status_mask = 0; 1355 if (termios->c_iflag & INPCK) 1356 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE); 1357 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1358 sport->port.read_status_mask |= UARTSR1_FE; 1359 1360 /* characters to ignore */ 1361 sport->port.ignore_status_mask = 0; 1362 if (termios->c_iflag & IGNPAR) 1363 sport->port.ignore_status_mask |= UARTSR1_PE; 1364 if (termios->c_iflag & IGNBRK) { 1365 sport->port.ignore_status_mask |= UARTSR1_FE; 1366 /* 1367 * if we're ignoring parity and break indicators, 1368 * ignore overruns too (for real raw support). 1369 */ 1370 if (termios->c_iflag & IGNPAR) 1371 sport->port.ignore_status_mask |= UARTSR1_OR; 1372 } 1373 1374 /* update the per-port timeout */ 1375 uart_update_timeout(port, termios->c_cflag, baud); 1376 1377 /* wait transmit engin complete */ 1378 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1379 barrier(); 1380 1381 /* disable transmit and receive */ 1382 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1383 sport->port.membase + UARTCR2); 1384 1385 sbr = sport->port.uartclk / (16 * baud); 1386 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1387 bdh &= ~UARTBDH_SBR_MASK; 1388 bdh |= (sbr >> 8) & 0x1F; 1389 cr4 &= ~UARTCR4_BRFA_MASK; 1390 brfa &= UARTCR4_BRFA_MASK; 1391 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1392 writeb(bdh, sport->port.membase + UARTBDH); 1393 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1394 writeb(cr3, sport->port.membase + UARTCR3); 1395 writeb(cr1, sport->port.membase + UARTCR1); 1396 writeb(modem, sport->port.membase + UARTMODEM); 1397 1398 /* restore control register */ 1399 writeb(old_cr2, sport->port.membase + UARTCR2); 1400 1401 /* 1402 * If new baud rate is set, we will also need to update the Ring buffer 1403 * length according to the selected baud rate and restart Rx DMA path. 1404 */ 1405 if (old) { 1406 if (sport->lpuart_dma_rx_use) { 1407 del_timer_sync(&sport->lpuart_timer); 1408 lpuart_dma_rx_free(&sport->port); 1409 } 1410 1411 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) { 1412 sport->lpuart_dma_rx_use = true; 1413 rx_dma_timer_init(sport); 1414 } else { 1415 sport->lpuart_dma_rx_use = false; 1416 } 1417 } 1418 1419 spin_unlock_irqrestore(&sport->port.lock, flags); 1420 } 1421 1422 static void 1423 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 1424 struct ktermios *old) 1425 { 1426 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1427 unsigned long flags; 1428 unsigned long ctrl, old_ctrl, bd, modem; 1429 unsigned int baud; 1430 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1431 unsigned int sbr; 1432 1433 ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL); 1434 bd = lpuart32_read(sport->port.membase + UARTBAUD); 1435 modem = lpuart32_read(sport->port.membase + UARTMODIR); 1436 /* 1437 * only support CS8 and CS7, and for CS7 must enable PE. 1438 * supported mode: 1439 * - (7,e/o,1) 1440 * - (8,n,1) 1441 * - (8,m/s,1) 1442 * - (8,e/o,1) 1443 */ 1444 while ((termios->c_cflag & CSIZE) != CS8 && 1445 (termios->c_cflag & CSIZE) != CS7) { 1446 termios->c_cflag &= ~CSIZE; 1447 termios->c_cflag |= old_csize; 1448 old_csize = CS8; 1449 } 1450 1451 if ((termios->c_cflag & CSIZE) == CS8 || 1452 (termios->c_cflag & CSIZE) == CS7) 1453 ctrl = old_ctrl & ~UARTCTRL_M; 1454 1455 if (termios->c_cflag & CMSPAR) { 1456 if ((termios->c_cflag & CSIZE) != CS8) { 1457 termios->c_cflag &= ~CSIZE; 1458 termios->c_cflag |= CS8; 1459 } 1460 ctrl |= UARTCTRL_M; 1461 } 1462 1463 if (termios->c_cflag & CRTSCTS) { 1464 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1465 } else { 1466 termios->c_cflag &= ~CRTSCTS; 1467 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1468 } 1469 1470 if (termios->c_cflag & CSTOPB) 1471 termios->c_cflag &= ~CSTOPB; 1472 1473 /* parity must be enabled when CS7 to match 8-bits format */ 1474 if ((termios->c_cflag & CSIZE) == CS7) 1475 termios->c_cflag |= PARENB; 1476 1477 if ((termios->c_cflag & PARENB)) { 1478 if (termios->c_cflag & CMSPAR) { 1479 ctrl &= ~UARTCTRL_PE; 1480 ctrl |= UARTCTRL_M; 1481 } else { 1482 ctrl |= UARTCR1_PE; 1483 if ((termios->c_cflag & CSIZE) == CS8) 1484 ctrl |= UARTCTRL_M; 1485 if (termios->c_cflag & PARODD) 1486 ctrl |= UARTCTRL_PT; 1487 else 1488 ctrl &= ~UARTCTRL_PT; 1489 } 1490 } 1491 1492 /* ask the core to calculate the divisor */ 1493 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1494 1495 spin_lock_irqsave(&sport->port.lock, flags); 1496 1497 sport->port.read_status_mask = 0; 1498 if (termios->c_iflag & INPCK) 1499 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE); 1500 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1501 sport->port.read_status_mask |= UARTSTAT_FE; 1502 1503 /* characters to ignore */ 1504 sport->port.ignore_status_mask = 0; 1505 if (termios->c_iflag & IGNPAR) 1506 sport->port.ignore_status_mask |= UARTSTAT_PE; 1507 if (termios->c_iflag & IGNBRK) { 1508 sport->port.ignore_status_mask |= UARTSTAT_FE; 1509 /* 1510 * if we're ignoring parity and break indicators, 1511 * ignore overruns too (for real raw support). 1512 */ 1513 if (termios->c_iflag & IGNPAR) 1514 sport->port.ignore_status_mask |= UARTSTAT_OR; 1515 } 1516 1517 /* update the per-port timeout */ 1518 uart_update_timeout(port, termios->c_cflag, baud); 1519 1520 /* wait transmit engin complete */ 1521 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC)) 1522 barrier(); 1523 1524 /* disable transmit and receive */ 1525 lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 1526 sport->port.membase + UARTCTRL); 1527 1528 sbr = sport->port.uartclk / (16 * baud); 1529 bd &= ~UARTBAUD_SBR_MASK; 1530 bd |= sbr & UARTBAUD_SBR_MASK; 1531 bd |= UARTBAUD_BOTHEDGE; 1532 bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); 1533 lpuart32_write(bd, sport->port.membase + UARTBAUD); 1534 lpuart32_write(modem, sport->port.membase + UARTMODIR); 1535 lpuart32_write(ctrl, sport->port.membase + UARTCTRL); 1536 /* restore control register */ 1537 1538 spin_unlock_irqrestore(&sport->port.lock, flags); 1539 } 1540 1541 static const char *lpuart_type(struct uart_port *port) 1542 { 1543 return "FSL_LPUART"; 1544 } 1545 1546 static void lpuart_release_port(struct uart_port *port) 1547 { 1548 /* nothing to do */ 1549 } 1550 1551 static int lpuart_request_port(struct uart_port *port) 1552 { 1553 return 0; 1554 } 1555 1556 /* configure/autoconfigure the port */ 1557 static void lpuart_config_port(struct uart_port *port, int flags) 1558 { 1559 if (flags & UART_CONFIG_TYPE) 1560 port->type = PORT_LPUART; 1561 } 1562 1563 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 1564 { 1565 int ret = 0; 1566 1567 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 1568 ret = -EINVAL; 1569 if (port->irq != ser->irq) 1570 ret = -EINVAL; 1571 if (ser->io_type != UPIO_MEM) 1572 ret = -EINVAL; 1573 if (port->uartclk / 16 != ser->baud_base) 1574 ret = -EINVAL; 1575 if (port->iobase != ser->port) 1576 ret = -EINVAL; 1577 if (ser->hub6 != 0) 1578 ret = -EINVAL; 1579 return ret; 1580 } 1581 1582 static const struct uart_ops lpuart_pops = { 1583 .tx_empty = lpuart_tx_empty, 1584 .set_mctrl = lpuart_set_mctrl, 1585 .get_mctrl = lpuart_get_mctrl, 1586 .stop_tx = lpuart_stop_tx, 1587 .start_tx = lpuart_start_tx, 1588 .stop_rx = lpuart_stop_rx, 1589 .break_ctl = lpuart_break_ctl, 1590 .startup = lpuart_startup, 1591 .shutdown = lpuart_shutdown, 1592 .set_termios = lpuart_set_termios, 1593 .type = lpuart_type, 1594 .request_port = lpuart_request_port, 1595 .release_port = lpuart_release_port, 1596 .config_port = lpuart_config_port, 1597 .verify_port = lpuart_verify_port, 1598 .flush_buffer = lpuart_flush_buffer, 1599 }; 1600 1601 static const struct uart_ops lpuart32_pops = { 1602 .tx_empty = lpuart32_tx_empty, 1603 .set_mctrl = lpuart32_set_mctrl, 1604 .get_mctrl = lpuart32_get_mctrl, 1605 .stop_tx = lpuart32_stop_tx, 1606 .start_tx = lpuart32_start_tx, 1607 .stop_rx = lpuart32_stop_rx, 1608 .break_ctl = lpuart32_break_ctl, 1609 .startup = lpuart32_startup, 1610 .shutdown = lpuart32_shutdown, 1611 .set_termios = lpuart32_set_termios, 1612 .type = lpuart_type, 1613 .request_port = lpuart_request_port, 1614 .release_port = lpuart_release_port, 1615 .config_port = lpuart_config_port, 1616 .verify_port = lpuart_verify_port, 1617 .flush_buffer = lpuart_flush_buffer, 1618 }; 1619 1620 static struct lpuart_port *lpuart_ports[UART_NR]; 1621 1622 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 1623 static void lpuart_console_putchar(struct uart_port *port, int ch) 1624 { 1625 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) 1626 barrier(); 1627 1628 writeb(ch, port->membase + UARTDR); 1629 } 1630 1631 static void lpuart32_console_putchar(struct uart_port *port, int ch) 1632 { 1633 while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)) 1634 barrier(); 1635 1636 lpuart32_write(ch, port->membase + UARTDATA); 1637 } 1638 1639 static void 1640 lpuart_console_write(struct console *co, const char *s, unsigned int count) 1641 { 1642 struct lpuart_port *sport = lpuart_ports[co->index]; 1643 unsigned char old_cr2, cr2; 1644 1645 /* first save CR2 and then disable interrupts */ 1646 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 1647 cr2 |= (UARTCR2_TE | UARTCR2_RE); 1648 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1649 writeb(cr2, sport->port.membase + UARTCR2); 1650 1651 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 1652 1653 /* wait for transmitter finish complete and restore CR2 */ 1654 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1655 barrier(); 1656 1657 writeb(old_cr2, sport->port.membase + UARTCR2); 1658 } 1659 1660 static void 1661 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 1662 { 1663 struct lpuart_port *sport = lpuart_ports[co->index]; 1664 unsigned long old_cr, cr; 1665 1666 /* first save CR2 and then disable interrupts */ 1667 cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL); 1668 cr |= (UARTCTRL_TE | UARTCTRL_RE); 1669 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1670 lpuart32_write(cr, sport->port.membase + UARTCTRL); 1671 1672 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 1673 1674 /* wait for transmitter finish complete and restore CR2 */ 1675 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC)) 1676 barrier(); 1677 1678 lpuart32_write(old_cr, sport->port.membase + UARTCTRL); 1679 } 1680 1681 /* 1682 * if the port was already initialised (eg, by a boot loader), 1683 * try to determine the current setup. 1684 */ 1685 static void __init 1686 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 1687 int *parity, int *bits) 1688 { 1689 unsigned char cr, bdh, bdl, brfa; 1690 unsigned int sbr, uartclk, baud_raw; 1691 1692 cr = readb(sport->port.membase + UARTCR2); 1693 cr &= UARTCR2_TE | UARTCR2_RE; 1694 if (!cr) 1695 return; 1696 1697 /* ok, the port was enabled */ 1698 1699 cr = readb(sport->port.membase + UARTCR1); 1700 1701 *parity = 'n'; 1702 if (cr & UARTCR1_PE) { 1703 if (cr & UARTCR1_PT) 1704 *parity = 'o'; 1705 else 1706 *parity = 'e'; 1707 } 1708 1709 if (cr & UARTCR1_M) 1710 *bits = 9; 1711 else 1712 *bits = 8; 1713 1714 bdh = readb(sport->port.membase + UARTBDH); 1715 bdh &= UARTBDH_SBR_MASK; 1716 bdl = readb(sport->port.membase + UARTBDL); 1717 sbr = bdh; 1718 sbr <<= 8; 1719 sbr |= bdl; 1720 brfa = readb(sport->port.membase + UARTCR4); 1721 brfa &= UARTCR4_BRFA_MASK; 1722 1723 uartclk = clk_get_rate(sport->clk); 1724 /* 1725 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 1726 */ 1727 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 1728 1729 if (*baud != baud_raw) 1730 printk(KERN_INFO "Serial: Console lpuart rounded baud rate" 1731 "from %d to %d\n", baud_raw, *baud); 1732 } 1733 1734 static void __init 1735 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 1736 int *parity, int *bits) 1737 { 1738 unsigned long cr, bd; 1739 unsigned int sbr, uartclk, baud_raw; 1740 1741 cr = lpuart32_read(sport->port.membase + UARTCTRL); 1742 cr &= UARTCTRL_TE | UARTCTRL_RE; 1743 if (!cr) 1744 return; 1745 1746 /* ok, the port was enabled */ 1747 1748 cr = lpuart32_read(sport->port.membase + UARTCTRL); 1749 1750 *parity = 'n'; 1751 if (cr & UARTCTRL_PE) { 1752 if (cr & UARTCTRL_PT) 1753 *parity = 'o'; 1754 else 1755 *parity = 'e'; 1756 } 1757 1758 if (cr & UARTCTRL_M) 1759 *bits = 9; 1760 else 1761 *bits = 8; 1762 1763 bd = lpuart32_read(sport->port.membase + UARTBAUD); 1764 bd &= UARTBAUD_SBR_MASK; 1765 sbr = bd; 1766 uartclk = clk_get_rate(sport->clk); 1767 /* 1768 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 1769 */ 1770 baud_raw = uartclk / (16 * sbr); 1771 1772 if (*baud != baud_raw) 1773 printk(KERN_INFO "Serial: Console lpuart rounded baud rate" 1774 "from %d to %d\n", baud_raw, *baud); 1775 } 1776 1777 static int __init lpuart_console_setup(struct console *co, char *options) 1778 { 1779 struct lpuart_port *sport; 1780 int baud = 115200; 1781 int bits = 8; 1782 int parity = 'n'; 1783 int flow = 'n'; 1784 1785 /* 1786 * check whether an invalid uart number has been specified, and 1787 * if so, search for the first available port that does have 1788 * console support. 1789 */ 1790 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 1791 co->index = 0; 1792 1793 sport = lpuart_ports[co->index]; 1794 if (sport == NULL) 1795 return -ENODEV; 1796 1797 if (options) 1798 uart_parse_options(options, &baud, &parity, &bits, &flow); 1799 else 1800 if (sport->lpuart32) 1801 lpuart32_console_get_options(sport, &baud, &parity, &bits); 1802 else 1803 lpuart_console_get_options(sport, &baud, &parity, &bits); 1804 1805 if (sport->lpuart32) 1806 lpuart32_setup_watermark(sport); 1807 else 1808 lpuart_setup_watermark(sport); 1809 1810 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 1811 } 1812 1813 static struct uart_driver lpuart_reg; 1814 static struct console lpuart_console = { 1815 .name = DEV_NAME, 1816 .write = lpuart_console_write, 1817 .device = uart_console_device, 1818 .setup = lpuart_console_setup, 1819 .flags = CON_PRINTBUFFER, 1820 .index = -1, 1821 .data = &lpuart_reg, 1822 }; 1823 1824 static struct console lpuart32_console = { 1825 .name = DEV_NAME, 1826 .write = lpuart32_console_write, 1827 .device = uart_console_device, 1828 .setup = lpuart_console_setup, 1829 .flags = CON_PRINTBUFFER, 1830 .index = -1, 1831 .data = &lpuart_reg, 1832 }; 1833 1834 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 1835 { 1836 struct earlycon_device *dev = con->data; 1837 1838 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 1839 } 1840 1841 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 1842 { 1843 struct earlycon_device *dev = con->data; 1844 1845 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 1846 } 1847 1848 static int __init lpuart_early_console_setup(struct earlycon_device *device, 1849 const char *opt) 1850 { 1851 if (!device->port.membase) 1852 return -ENODEV; 1853 1854 device->con->write = lpuart_early_write; 1855 return 0; 1856 } 1857 1858 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 1859 const char *opt) 1860 { 1861 if (!device->port.membase) 1862 return -ENODEV; 1863 1864 device->con->write = lpuart32_early_write; 1865 return 0; 1866 } 1867 1868 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 1869 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 1870 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 1871 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 1872 1873 #define LPUART_CONSOLE (&lpuart_console) 1874 #define LPUART32_CONSOLE (&lpuart32_console) 1875 #else 1876 #define LPUART_CONSOLE NULL 1877 #define LPUART32_CONSOLE NULL 1878 #endif 1879 1880 static struct uart_driver lpuart_reg = { 1881 .owner = THIS_MODULE, 1882 .driver_name = DRIVER_NAME, 1883 .dev_name = DEV_NAME, 1884 .nr = ARRAY_SIZE(lpuart_ports), 1885 .cons = LPUART_CONSOLE, 1886 }; 1887 1888 static int lpuart_probe(struct platform_device *pdev) 1889 { 1890 struct device_node *np = pdev->dev.of_node; 1891 struct lpuart_port *sport; 1892 struct resource *res; 1893 int ret; 1894 1895 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1896 if (!sport) 1897 return -ENOMEM; 1898 1899 pdev->dev.coherent_dma_mask = 0; 1900 1901 ret = of_alias_get_id(np, "serial"); 1902 if (ret < 0) { 1903 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1904 return ret; 1905 } 1906 sport->port.line = ret; 1907 sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart"); 1908 1909 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1910 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 1911 if (IS_ERR(sport->port.membase)) 1912 return PTR_ERR(sport->port.membase); 1913 1914 sport->port.mapbase = res->start; 1915 sport->port.dev = &pdev->dev; 1916 sport->port.type = PORT_LPUART; 1917 sport->port.iotype = UPIO_MEM; 1918 ret = platform_get_irq(pdev, 0); 1919 if (ret < 0) { 1920 dev_err(&pdev->dev, "cannot obtain irq\n"); 1921 return ret; 1922 } 1923 sport->port.irq = ret; 1924 1925 if (sport->lpuart32) 1926 sport->port.ops = &lpuart32_pops; 1927 else 1928 sport->port.ops = &lpuart_pops; 1929 sport->port.flags = UPF_BOOT_AUTOCONF; 1930 1931 sport->port.rs485_config = lpuart_config_rs485; 1932 1933 sport->clk = devm_clk_get(&pdev->dev, "ipg"); 1934 if (IS_ERR(sport->clk)) { 1935 ret = PTR_ERR(sport->clk); 1936 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret); 1937 return ret; 1938 } 1939 1940 ret = clk_prepare_enable(sport->clk); 1941 if (ret) { 1942 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret); 1943 return ret; 1944 } 1945 1946 sport->port.uartclk = clk_get_rate(sport->clk); 1947 1948 lpuart_ports[sport->port.line] = sport; 1949 1950 platform_set_drvdata(pdev, &sport->port); 1951 1952 if (sport->lpuart32) 1953 lpuart_reg.cons = LPUART32_CONSOLE; 1954 else 1955 lpuart_reg.cons = LPUART_CONSOLE; 1956 1957 ret = uart_add_one_port(&lpuart_reg, &sport->port); 1958 if (ret) { 1959 clk_disable_unprepare(sport->clk); 1960 return ret; 1961 } 1962 1963 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx"); 1964 if (!sport->dma_tx_chan) 1965 dev_info(sport->port.dev, "DMA tx channel request failed, " 1966 "operating without tx DMA\n"); 1967 1968 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx"); 1969 if (!sport->dma_rx_chan) 1970 dev_info(sport->port.dev, "DMA rx channel request failed, " 1971 "operating without rx DMA\n"); 1972 1973 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) { 1974 sport->port.rs485.flags |= SER_RS485_ENABLED; 1975 sport->port.rs485.flags |= SER_RS485_RTS_ON_SEND; 1976 writeb(UARTMODEM_TXRTSE, sport->port.membase + UARTMODEM); 1977 } 1978 1979 return 0; 1980 } 1981 1982 static int lpuart_remove(struct platform_device *pdev) 1983 { 1984 struct lpuart_port *sport = platform_get_drvdata(pdev); 1985 1986 uart_remove_one_port(&lpuart_reg, &sport->port); 1987 1988 clk_disable_unprepare(sport->clk); 1989 1990 if (sport->dma_tx_chan) 1991 dma_release_channel(sport->dma_tx_chan); 1992 1993 if (sport->dma_rx_chan) 1994 dma_release_channel(sport->dma_rx_chan); 1995 1996 return 0; 1997 } 1998 1999 #ifdef CONFIG_PM_SLEEP 2000 static int lpuart_suspend(struct device *dev) 2001 { 2002 struct lpuart_port *sport = dev_get_drvdata(dev); 2003 unsigned long temp; 2004 2005 if (sport->lpuart32) { 2006 /* disable Rx/Tx and interrupts */ 2007 temp = lpuart32_read(sport->port.membase + UARTCTRL); 2008 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2009 lpuart32_write(temp, sport->port.membase + UARTCTRL); 2010 } else { 2011 /* disable Rx/Tx and interrupts */ 2012 temp = readb(sport->port.membase + UARTCR2); 2013 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2014 writeb(temp, sport->port.membase + UARTCR2); 2015 } 2016 2017 uart_suspend_port(&lpuart_reg, &sport->port); 2018 2019 if (sport->lpuart_dma_rx_use) { 2020 /* 2021 * EDMA driver during suspend will forcefully release any 2022 * non-idle DMA channels. If port wakeup is enabled or if port 2023 * is console port or 'no_console_suspend' is set the Rx DMA 2024 * cannot resume as as expected, hence gracefully release the 2025 * Rx DMA path before suspend and start Rx DMA path on resume. 2026 */ 2027 if (sport->port.irq_wake) { 2028 del_timer_sync(&sport->lpuart_timer); 2029 lpuart_dma_rx_free(&sport->port); 2030 } 2031 2032 /* Disable Rx DMA to use UART port as wakeup source */ 2033 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS, 2034 sport->port.membase + UARTCR5); 2035 } 2036 2037 if (sport->lpuart_dma_tx_use) { 2038 sport->dma_tx_in_progress = false; 2039 dmaengine_terminate_all(sport->dma_tx_chan); 2040 } 2041 2042 if (sport->port.suspended && !sport->port.irq_wake) 2043 clk_disable_unprepare(sport->clk); 2044 2045 return 0; 2046 } 2047 2048 static int lpuart_resume(struct device *dev) 2049 { 2050 struct lpuart_port *sport = dev_get_drvdata(dev); 2051 unsigned long temp; 2052 2053 if (sport->port.suspended && !sport->port.irq_wake) 2054 clk_prepare_enable(sport->clk); 2055 2056 if (sport->lpuart32) { 2057 lpuart32_setup_watermark(sport); 2058 temp = lpuart32_read(sport->port.membase + UARTCTRL); 2059 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | 2060 UARTCTRL_TE | UARTCTRL_ILIE); 2061 lpuart32_write(temp, sport->port.membase + UARTCTRL); 2062 } else { 2063 lpuart_setup_watermark(sport); 2064 temp = readb(sport->port.membase + UARTCR2); 2065 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 2066 writeb(temp, sport->port.membase + UARTCR2); 2067 } 2068 2069 if (sport->lpuart_dma_rx_use) { 2070 if (sport->port.irq_wake) { 2071 if (!lpuart_start_rx_dma(sport)) { 2072 sport->lpuart_dma_rx_use = true; 2073 rx_dma_timer_init(sport); 2074 } else { 2075 sport->lpuart_dma_rx_use = false; 2076 } 2077 } 2078 } 2079 2080 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) { 2081 init_waitqueue_head(&sport->dma_wait); 2082 sport->lpuart_dma_tx_use = true; 2083 writeb(readb(sport->port.membase + UARTCR5) | 2084 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 2085 } else { 2086 sport->lpuart_dma_tx_use = false; 2087 } 2088 2089 uart_resume_port(&lpuart_reg, &sport->port); 2090 2091 return 0; 2092 } 2093 #endif 2094 2095 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2096 2097 static struct platform_driver lpuart_driver = { 2098 .probe = lpuart_probe, 2099 .remove = lpuart_remove, 2100 .driver = { 2101 .name = "fsl-lpuart", 2102 .of_match_table = lpuart_dt_ids, 2103 .pm = &lpuart_pm_ops, 2104 }, 2105 }; 2106 2107 static int __init lpuart_serial_init(void) 2108 { 2109 int ret = uart_register_driver(&lpuart_reg); 2110 2111 if (ret) 2112 return ret; 2113 2114 ret = platform_driver_register(&lpuart_driver); 2115 if (ret) 2116 uart_unregister_driver(&lpuart_reg); 2117 2118 return ret; 2119 } 2120 2121 static void __exit lpuart_serial_exit(void) 2122 { 2123 platform_driver_unregister(&lpuart_driver); 2124 uart_unregister_driver(&lpuart_reg); 2125 } 2126 2127 module_init(lpuart_serial_init); 2128 module_exit(lpuart_serial_exit); 2129 2130 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2131 MODULE_LICENSE("GPL v2"); 2132