1 /* 2 * Freescale lpuart serial port driver 3 * 4 * Copyright 2012-2014 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 13 #define SUPPORT_SYSRQ 14 #endif 15 16 #include <linux/clk.h> 17 #include <linux/console.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/dmaengine.h> 20 #include <linux/dmapool.h> 21 #include <linux/io.h> 22 #include <linux/irq.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/of_dma.h> 27 #include <linux/serial_core.h> 28 #include <linux/slab.h> 29 #include <linux/tty_flip.h> 30 31 /* All registers are 8-bit width */ 32 #define UARTBDH 0x00 33 #define UARTBDL 0x01 34 #define UARTCR1 0x02 35 #define UARTCR2 0x03 36 #define UARTSR1 0x04 37 #define UARTCR3 0x06 38 #define UARTDR 0x07 39 #define UARTCR4 0x0a 40 #define UARTCR5 0x0b 41 #define UARTMODEM 0x0d 42 #define UARTPFIFO 0x10 43 #define UARTCFIFO 0x11 44 #define UARTSFIFO 0x12 45 #define UARTTWFIFO 0x13 46 #define UARTTCFIFO 0x14 47 #define UARTRWFIFO 0x15 48 49 #define UARTBDH_LBKDIE 0x80 50 #define UARTBDH_RXEDGIE 0x40 51 #define UARTBDH_SBR_MASK 0x1f 52 53 #define UARTCR1_LOOPS 0x80 54 #define UARTCR1_RSRC 0x20 55 #define UARTCR1_M 0x10 56 #define UARTCR1_WAKE 0x08 57 #define UARTCR1_ILT 0x04 58 #define UARTCR1_PE 0x02 59 #define UARTCR1_PT 0x01 60 61 #define UARTCR2_TIE 0x80 62 #define UARTCR2_TCIE 0x40 63 #define UARTCR2_RIE 0x20 64 #define UARTCR2_ILIE 0x10 65 #define UARTCR2_TE 0x08 66 #define UARTCR2_RE 0x04 67 #define UARTCR2_RWU 0x02 68 #define UARTCR2_SBK 0x01 69 70 #define UARTSR1_TDRE 0x80 71 #define UARTSR1_TC 0x40 72 #define UARTSR1_RDRF 0x20 73 #define UARTSR1_IDLE 0x10 74 #define UARTSR1_OR 0x08 75 #define UARTSR1_NF 0x04 76 #define UARTSR1_FE 0x02 77 #define UARTSR1_PE 0x01 78 79 #define UARTCR3_R8 0x80 80 #define UARTCR3_T8 0x40 81 #define UARTCR3_TXDIR 0x20 82 #define UARTCR3_TXINV 0x10 83 #define UARTCR3_ORIE 0x08 84 #define UARTCR3_NEIE 0x04 85 #define UARTCR3_FEIE 0x02 86 #define UARTCR3_PEIE 0x01 87 88 #define UARTCR4_MAEN1 0x80 89 #define UARTCR4_MAEN2 0x40 90 #define UARTCR4_M10 0x20 91 #define UARTCR4_BRFA_MASK 0x1f 92 #define UARTCR4_BRFA_OFF 0 93 94 #define UARTCR5_TDMAS 0x80 95 #define UARTCR5_RDMAS 0x20 96 97 #define UARTMODEM_RXRTSE 0x08 98 #define UARTMODEM_TXRTSPOL 0x04 99 #define UARTMODEM_TXRTSE 0x02 100 #define UARTMODEM_TXCTSE 0x01 101 102 #define UARTPFIFO_TXFE 0x80 103 #define UARTPFIFO_FIFOSIZE_MASK 0x7 104 #define UARTPFIFO_TXSIZE_OFF 4 105 #define UARTPFIFO_RXFE 0x08 106 #define UARTPFIFO_RXSIZE_OFF 0 107 108 #define UARTCFIFO_TXFLUSH 0x80 109 #define UARTCFIFO_RXFLUSH 0x40 110 #define UARTCFIFO_RXOFE 0x04 111 #define UARTCFIFO_TXOFE 0x02 112 #define UARTCFIFO_RXUFE 0x01 113 114 #define UARTSFIFO_TXEMPT 0x80 115 #define UARTSFIFO_RXEMPT 0x40 116 #define UARTSFIFO_RXOF 0x04 117 #define UARTSFIFO_TXOF 0x02 118 #define UARTSFIFO_RXUF 0x01 119 120 /* 32-bit register definition */ 121 #define UARTBAUD 0x00 122 #define UARTSTAT 0x04 123 #define UARTCTRL 0x08 124 #define UARTDATA 0x0C 125 #define UARTMATCH 0x10 126 #define UARTMODIR 0x14 127 #define UARTFIFO 0x18 128 #define UARTWATER 0x1c 129 130 #define UARTBAUD_MAEN1 0x80000000 131 #define UARTBAUD_MAEN2 0x40000000 132 #define UARTBAUD_M10 0x20000000 133 #define UARTBAUD_TDMAE 0x00800000 134 #define UARTBAUD_RDMAE 0x00200000 135 #define UARTBAUD_MATCFG 0x00400000 136 #define UARTBAUD_BOTHEDGE 0x00020000 137 #define UARTBAUD_RESYNCDIS 0x00010000 138 #define UARTBAUD_LBKDIE 0x00008000 139 #define UARTBAUD_RXEDGIE 0x00004000 140 #define UARTBAUD_SBNS 0x00002000 141 #define UARTBAUD_SBR 0x00000000 142 #define UARTBAUD_SBR_MASK 0x1fff 143 #define UARTBAUD_OSR_MASK 0x1f 144 #define UARTBAUD_OSR_SHIFT 24 145 146 #define UARTSTAT_LBKDIF 0x80000000 147 #define UARTSTAT_RXEDGIF 0x40000000 148 #define UARTSTAT_MSBF 0x20000000 149 #define UARTSTAT_RXINV 0x10000000 150 #define UARTSTAT_RWUID 0x08000000 151 #define UARTSTAT_BRK13 0x04000000 152 #define UARTSTAT_LBKDE 0x02000000 153 #define UARTSTAT_RAF 0x01000000 154 #define UARTSTAT_TDRE 0x00800000 155 #define UARTSTAT_TC 0x00400000 156 #define UARTSTAT_RDRF 0x00200000 157 #define UARTSTAT_IDLE 0x00100000 158 #define UARTSTAT_OR 0x00080000 159 #define UARTSTAT_NF 0x00040000 160 #define UARTSTAT_FE 0x00020000 161 #define UARTSTAT_PE 0x00010000 162 #define UARTSTAT_MA1F 0x00008000 163 #define UARTSTAT_M21F 0x00004000 164 165 #define UARTCTRL_R8T9 0x80000000 166 #define UARTCTRL_R9T8 0x40000000 167 #define UARTCTRL_TXDIR 0x20000000 168 #define UARTCTRL_TXINV 0x10000000 169 #define UARTCTRL_ORIE 0x08000000 170 #define UARTCTRL_NEIE 0x04000000 171 #define UARTCTRL_FEIE 0x02000000 172 #define UARTCTRL_PEIE 0x01000000 173 #define UARTCTRL_TIE 0x00800000 174 #define UARTCTRL_TCIE 0x00400000 175 #define UARTCTRL_RIE 0x00200000 176 #define UARTCTRL_ILIE 0x00100000 177 #define UARTCTRL_TE 0x00080000 178 #define UARTCTRL_RE 0x00040000 179 #define UARTCTRL_RWU 0x00020000 180 #define UARTCTRL_SBK 0x00010000 181 #define UARTCTRL_MA1IE 0x00008000 182 #define UARTCTRL_MA2IE 0x00004000 183 #define UARTCTRL_IDLECFG 0x00000100 184 #define UARTCTRL_LOOPS 0x00000080 185 #define UARTCTRL_DOZEEN 0x00000040 186 #define UARTCTRL_RSRC 0x00000020 187 #define UARTCTRL_M 0x00000010 188 #define UARTCTRL_WAKE 0x00000008 189 #define UARTCTRL_ILT 0x00000004 190 #define UARTCTRL_PE 0x00000002 191 #define UARTCTRL_PT 0x00000001 192 193 #define UARTDATA_NOISY 0x00008000 194 #define UARTDATA_PARITYE 0x00004000 195 #define UARTDATA_FRETSC 0x00002000 196 #define UARTDATA_RXEMPT 0x00001000 197 #define UARTDATA_IDLINE 0x00000800 198 #define UARTDATA_MASK 0x3ff 199 200 #define UARTMODIR_IREN 0x00020000 201 #define UARTMODIR_TXCTSSRC 0x00000020 202 #define UARTMODIR_TXCTSC 0x00000010 203 #define UARTMODIR_RXRTSE 0x00000008 204 #define UARTMODIR_TXRTSPOL 0x00000004 205 #define UARTMODIR_TXRTSE 0x00000002 206 #define UARTMODIR_TXCTSE 0x00000001 207 208 #define UARTFIFO_TXEMPT 0x00800000 209 #define UARTFIFO_RXEMPT 0x00400000 210 #define UARTFIFO_TXOF 0x00020000 211 #define UARTFIFO_RXUF 0x00010000 212 #define UARTFIFO_TXFLUSH 0x00008000 213 #define UARTFIFO_RXFLUSH 0x00004000 214 #define UARTFIFO_TXOFE 0x00000200 215 #define UARTFIFO_RXUFE 0x00000100 216 #define UARTFIFO_TXFE 0x00000080 217 #define UARTFIFO_FIFOSIZE_MASK 0x7 218 #define UARTFIFO_TXSIZE_OFF 4 219 #define UARTFIFO_RXFE 0x00000008 220 #define UARTFIFO_RXSIZE_OFF 0 221 222 #define UARTWATER_COUNT_MASK 0xff 223 #define UARTWATER_TXCNT_OFF 8 224 #define UARTWATER_RXCNT_OFF 24 225 #define UARTWATER_WATER_MASK 0xff 226 #define UARTWATER_TXWATER_OFF 0 227 #define UARTWATER_RXWATER_OFF 16 228 229 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 230 #define DMA_RX_TIMEOUT (10) 231 232 #define DRIVER_NAME "fsl-lpuart" 233 #define DEV_NAME "ttyLP" 234 #define UART_NR 6 235 236 /* IMX lpuart has four extra unused regs located at the beginning */ 237 #define IMX_REG_OFF 0x10 238 239 struct lpuart_port { 240 struct uart_port port; 241 struct clk *clk; 242 unsigned int txfifo_size; 243 unsigned int rxfifo_size; 244 245 bool lpuart_dma_tx_use; 246 bool lpuart_dma_rx_use; 247 struct dma_chan *dma_tx_chan; 248 struct dma_chan *dma_rx_chan; 249 struct dma_async_tx_descriptor *dma_tx_desc; 250 struct dma_async_tx_descriptor *dma_rx_desc; 251 dma_cookie_t dma_tx_cookie; 252 dma_cookie_t dma_rx_cookie; 253 unsigned int dma_tx_bytes; 254 unsigned int dma_rx_bytes; 255 bool dma_tx_in_progress; 256 unsigned int dma_rx_timeout; 257 struct timer_list lpuart_timer; 258 struct scatterlist rx_sgl, tx_sgl[2]; 259 struct circ_buf rx_ring; 260 int rx_dma_rng_buf_len; 261 unsigned int dma_tx_nents; 262 wait_queue_head_t dma_wait; 263 }; 264 265 struct lpuart_soc_data { 266 char iotype; 267 u8 reg_off; 268 }; 269 270 static const struct lpuart_soc_data vf_data = { 271 .iotype = UPIO_MEM, 272 }; 273 274 static const struct lpuart_soc_data ls_data = { 275 .iotype = UPIO_MEM32BE, 276 }; 277 278 static struct lpuart_soc_data imx_data = { 279 .iotype = UPIO_MEM32, 280 .reg_off = IMX_REG_OFF, 281 }; 282 283 static const struct of_device_id lpuart_dt_ids[] = { 284 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 285 { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, }, 286 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx_data, }, 287 { /* sentinel */ } 288 }; 289 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 290 291 /* Forward declare this for the dma callbacks*/ 292 static void lpuart_dma_tx_complete(void *arg); 293 294 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 295 { 296 switch (port->iotype) { 297 case UPIO_MEM32: 298 return readl(port->membase + off); 299 case UPIO_MEM32BE: 300 return ioread32be(port->membase + off); 301 default: 302 return 0; 303 } 304 } 305 306 static inline void lpuart32_write(struct uart_port *port, u32 val, 307 u32 off) 308 { 309 switch (port->iotype) { 310 case UPIO_MEM32: 311 writel(val, port->membase + off); 312 break; 313 case UPIO_MEM32BE: 314 iowrite32be(val, port->membase + off); 315 break; 316 } 317 } 318 319 static void lpuart_stop_tx(struct uart_port *port) 320 { 321 unsigned char temp; 322 323 temp = readb(port->membase + UARTCR2); 324 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 325 writeb(temp, port->membase + UARTCR2); 326 } 327 328 static void lpuart32_stop_tx(struct uart_port *port) 329 { 330 unsigned long temp; 331 332 temp = lpuart32_read(port, UARTCTRL); 333 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 334 lpuart32_write(port, temp, UARTCTRL); 335 } 336 337 static void lpuart_stop_rx(struct uart_port *port) 338 { 339 unsigned char temp; 340 341 temp = readb(port->membase + UARTCR2); 342 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 343 } 344 345 static void lpuart32_stop_rx(struct uart_port *port) 346 { 347 unsigned long temp; 348 349 temp = lpuart32_read(port, UARTCTRL); 350 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); 351 } 352 353 static void lpuart_dma_tx(struct lpuart_port *sport) 354 { 355 struct circ_buf *xmit = &sport->port.state->xmit; 356 struct scatterlist *sgl = sport->tx_sgl; 357 struct device *dev = sport->port.dev; 358 int ret; 359 360 if (sport->dma_tx_in_progress) 361 return; 362 363 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 364 365 if (xmit->tail < xmit->head || xmit->head == 0) { 366 sport->dma_tx_nents = 1; 367 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 368 } else { 369 sport->dma_tx_nents = 2; 370 sg_init_table(sgl, 2); 371 sg_set_buf(sgl, xmit->buf + xmit->tail, 372 UART_XMIT_SIZE - xmit->tail); 373 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 374 } 375 376 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 377 if (!ret) { 378 dev_err(dev, "DMA mapping error for TX.\n"); 379 return; 380 } 381 382 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl, 383 sport->dma_tx_nents, 384 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 385 if (!sport->dma_tx_desc) { 386 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 387 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 388 return; 389 } 390 391 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 392 sport->dma_tx_desc->callback_param = sport; 393 sport->dma_tx_in_progress = true; 394 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 395 dma_async_issue_pending(sport->dma_tx_chan); 396 } 397 398 static void lpuart_dma_tx_complete(void *arg) 399 { 400 struct lpuart_port *sport = arg; 401 struct scatterlist *sgl = &sport->tx_sgl[0]; 402 struct circ_buf *xmit = &sport->port.state->xmit; 403 unsigned long flags; 404 405 spin_lock_irqsave(&sport->port.lock, flags); 406 407 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 408 409 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 410 411 sport->port.icount.tx += sport->dma_tx_bytes; 412 sport->dma_tx_in_progress = false; 413 spin_unlock_irqrestore(&sport->port.lock, flags); 414 415 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 416 uart_write_wakeup(&sport->port); 417 418 if (waitqueue_active(&sport->dma_wait)) { 419 wake_up(&sport->dma_wait); 420 return; 421 } 422 423 spin_lock_irqsave(&sport->port.lock, flags); 424 425 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 426 lpuart_dma_tx(sport); 427 428 spin_unlock_irqrestore(&sport->port.lock, flags); 429 } 430 431 static int lpuart_dma_tx_request(struct uart_port *port) 432 { 433 struct lpuart_port *sport = container_of(port, 434 struct lpuart_port, port); 435 struct dma_slave_config dma_tx_sconfig = {}; 436 int ret; 437 438 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR; 439 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 440 dma_tx_sconfig.dst_maxburst = 1; 441 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 442 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 443 444 if (ret) { 445 dev_err(sport->port.dev, 446 "DMA slave config failed, err = %d\n", ret); 447 return ret; 448 } 449 450 return 0; 451 } 452 453 static void lpuart_flush_buffer(struct uart_port *port) 454 { 455 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 456 457 if (sport->lpuart_dma_tx_use) { 458 if (sport->dma_tx_in_progress) { 459 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 460 sport->dma_tx_nents, DMA_TO_DEVICE); 461 sport->dma_tx_in_progress = false; 462 } 463 dmaengine_terminate_all(sport->dma_tx_chan); 464 } 465 } 466 467 #if defined(CONFIG_CONSOLE_POLL) 468 469 static int lpuart_poll_init(struct uart_port *port) 470 { 471 struct lpuart_port *sport = container_of(port, 472 struct lpuart_port, port); 473 unsigned long flags; 474 unsigned char temp; 475 476 sport->port.fifosize = 0; 477 478 spin_lock_irqsave(&sport->port.lock, flags); 479 /* Disable Rx & Tx */ 480 writeb(0, sport->port.membase + UARTCR2); 481 482 temp = readb(sport->port.membase + UARTPFIFO); 483 /* Enable Rx and Tx FIFO */ 484 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 485 sport->port.membase + UARTPFIFO); 486 487 /* flush Tx and Rx FIFO */ 488 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 489 sport->port.membase + UARTCFIFO); 490 491 /* explicitly clear RDRF */ 492 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 493 readb(sport->port.membase + UARTDR); 494 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 495 } 496 497 writeb(0, sport->port.membase + UARTTWFIFO); 498 writeb(1, sport->port.membase + UARTRWFIFO); 499 500 /* Enable Rx and Tx */ 501 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 502 spin_unlock_irqrestore(&sport->port.lock, flags); 503 504 return 0; 505 } 506 507 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 508 { 509 /* drain */ 510 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) 511 barrier(); 512 513 writeb(c, port->membase + UARTDR); 514 } 515 516 static int lpuart_poll_get_char(struct uart_port *port) 517 { 518 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 519 return NO_POLL_CHAR; 520 521 return readb(port->membase + UARTDR); 522 } 523 524 static int lpuart32_poll_init(struct uart_port *port) 525 { 526 unsigned long flags; 527 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 528 u32 temp; 529 530 sport->port.fifosize = 0; 531 532 spin_lock_irqsave(&sport->port.lock, flags); 533 534 /* Disable Rx & Tx */ 535 writel(0, sport->port.membase + UARTCTRL); 536 537 temp = readl(sport->port.membase + UARTFIFO); 538 539 /* Enable Rx and Tx FIFO */ 540 writel(temp | UARTFIFO_RXFE | UARTFIFO_TXFE, 541 sport->port.membase + UARTFIFO); 542 543 /* flush Tx and Rx FIFO */ 544 writel(UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, 545 sport->port.membase + UARTFIFO); 546 547 /* explicitly clear RDRF */ 548 if (readl(sport->port.membase + UARTSTAT) & UARTSTAT_RDRF) { 549 readl(sport->port.membase + UARTDATA); 550 writel(UARTFIFO_RXUF, sport->port.membase + UARTFIFO); 551 } 552 553 /* Enable Rx and Tx */ 554 writel(UARTCTRL_RE | UARTCTRL_TE, sport->port.membase + UARTCTRL); 555 spin_unlock_irqrestore(&sport->port.lock, flags); 556 557 return 0; 558 } 559 560 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 561 { 562 while (!(readl(port->membase + UARTSTAT) & UARTSTAT_TDRE)) 563 barrier(); 564 565 writel(c, port->membase + UARTDATA); 566 } 567 568 static int lpuart32_poll_get_char(struct uart_port *port) 569 { 570 if (!(readl(port->membase + UARTSTAT) & UARTSTAT_RDRF)) 571 return NO_POLL_CHAR; 572 573 return readl(port->membase + UARTDATA); 574 } 575 #endif 576 577 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 578 { 579 struct circ_buf *xmit = &sport->port.state->xmit; 580 581 while (!uart_circ_empty(xmit) && 582 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 583 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 584 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 585 sport->port.icount.tx++; 586 } 587 588 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 589 uart_write_wakeup(&sport->port); 590 591 if (uart_circ_empty(xmit)) 592 lpuart_stop_tx(&sport->port); 593 } 594 595 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 596 { 597 struct circ_buf *xmit = &sport->port.state->xmit; 598 unsigned long txcnt; 599 600 txcnt = lpuart32_read(&sport->port, UARTWATER); 601 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 602 txcnt &= UARTWATER_COUNT_MASK; 603 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 604 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); 605 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 606 sport->port.icount.tx++; 607 txcnt = lpuart32_read(&sport->port, UARTWATER); 608 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 609 txcnt &= UARTWATER_COUNT_MASK; 610 } 611 612 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 613 uart_write_wakeup(&sport->port); 614 615 if (uart_circ_empty(xmit)) 616 lpuart32_stop_tx(&sport->port); 617 } 618 619 static void lpuart_start_tx(struct uart_port *port) 620 { 621 struct lpuart_port *sport = container_of(port, 622 struct lpuart_port, port); 623 struct circ_buf *xmit = &sport->port.state->xmit; 624 unsigned char temp; 625 626 temp = readb(port->membase + UARTCR2); 627 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 628 629 if (sport->lpuart_dma_tx_use) { 630 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) 631 lpuart_dma_tx(sport); 632 } else { 633 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 634 lpuart_transmit_buffer(sport); 635 } 636 } 637 638 static void lpuart32_start_tx(struct uart_port *port) 639 { 640 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 641 unsigned long temp; 642 643 temp = lpuart32_read(port, UARTCTRL); 644 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); 645 646 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 647 lpuart32_transmit_buffer(sport); 648 } 649 650 /* return TIOCSER_TEMT when transmitter is not busy */ 651 static unsigned int lpuart_tx_empty(struct uart_port *port) 652 { 653 struct lpuart_port *sport = container_of(port, 654 struct lpuart_port, port); 655 unsigned char sr1 = readb(port->membase + UARTSR1); 656 unsigned char sfifo = readb(port->membase + UARTSFIFO); 657 658 if (sport->dma_tx_in_progress) 659 return 0; 660 661 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 662 return TIOCSER_TEMT; 663 664 return 0; 665 } 666 667 static unsigned int lpuart32_tx_empty(struct uart_port *port) 668 { 669 return (lpuart32_read(port, UARTSTAT) & UARTSTAT_TC) ? 670 TIOCSER_TEMT : 0; 671 } 672 673 static bool lpuart_is_32(struct lpuart_port *sport) 674 { 675 return sport->port.iotype == UPIO_MEM32 || 676 sport->port.iotype == UPIO_MEM32BE; 677 } 678 679 static irqreturn_t lpuart_txint(int irq, void *dev_id) 680 { 681 struct lpuart_port *sport = dev_id; 682 struct circ_buf *xmit = &sport->port.state->xmit; 683 unsigned long flags; 684 685 spin_lock_irqsave(&sport->port.lock, flags); 686 if (sport->port.x_char) { 687 if (lpuart_is_32(sport)) 688 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 689 else 690 writeb(sport->port.x_char, sport->port.membase + UARTDR); 691 goto out; 692 } 693 694 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 695 if (lpuart_is_32(sport)) 696 lpuart32_stop_tx(&sport->port); 697 else 698 lpuart_stop_tx(&sport->port); 699 goto out; 700 } 701 702 if (lpuart_is_32(sport)) 703 lpuart32_transmit_buffer(sport); 704 else 705 lpuart_transmit_buffer(sport); 706 707 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 708 uart_write_wakeup(&sport->port); 709 710 out: 711 spin_unlock_irqrestore(&sport->port.lock, flags); 712 return IRQ_HANDLED; 713 } 714 715 static irqreturn_t lpuart_rxint(int irq, void *dev_id) 716 { 717 struct lpuart_port *sport = dev_id; 718 unsigned int flg, ignored = 0; 719 struct tty_port *port = &sport->port.state->port; 720 unsigned long flags; 721 unsigned char rx, sr; 722 723 spin_lock_irqsave(&sport->port.lock, flags); 724 725 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 726 flg = TTY_NORMAL; 727 sport->port.icount.rx++; 728 /* 729 * to clear the FE, OR, NF, FE, PE flags, 730 * read SR1 then read DR 731 */ 732 sr = readb(sport->port.membase + UARTSR1); 733 rx = readb(sport->port.membase + UARTDR); 734 735 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 736 continue; 737 738 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 739 if (sr & UARTSR1_PE) 740 sport->port.icount.parity++; 741 else if (sr & UARTSR1_FE) 742 sport->port.icount.frame++; 743 744 if (sr & UARTSR1_OR) 745 sport->port.icount.overrun++; 746 747 if (sr & sport->port.ignore_status_mask) { 748 if (++ignored > 100) 749 goto out; 750 continue; 751 } 752 753 sr &= sport->port.read_status_mask; 754 755 if (sr & UARTSR1_PE) 756 flg = TTY_PARITY; 757 else if (sr & UARTSR1_FE) 758 flg = TTY_FRAME; 759 760 if (sr & UARTSR1_OR) 761 flg = TTY_OVERRUN; 762 763 #ifdef SUPPORT_SYSRQ 764 sport->port.sysrq = 0; 765 #endif 766 } 767 768 tty_insert_flip_char(port, rx, flg); 769 } 770 771 out: 772 spin_unlock_irqrestore(&sport->port.lock, flags); 773 774 tty_flip_buffer_push(port); 775 return IRQ_HANDLED; 776 } 777 778 static irqreturn_t lpuart32_rxint(int irq, void *dev_id) 779 { 780 struct lpuart_port *sport = dev_id; 781 unsigned int flg, ignored = 0; 782 struct tty_port *port = &sport->port.state->port; 783 unsigned long flags; 784 unsigned long rx, sr; 785 786 spin_lock_irqsave(&sport->port.lock, flags); 787 788 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 789 flg = TTY_NORMAL; 790 sport->port.icount.rx++; 791 /* 792 * to clear the FE, OR, NF, FE, PE flags, 793 * read STAT then read DATA reg 794 */ 795 sr = lpuart32_read(&sport->port, UARTSTAT); 796 rx = lpuart32_read(&sport->port, UARTDATA); 797 rx &= 0x3ff; 798 799 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 800 continue; 801 802 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 803 if (sr & UARTSTAT_PE) 804 sport->port.icount.parity++; 805 else if (sr & UARTSTAT_FE) 806 sport->port.icount.frame++; 807 808 if (sr & UARTSTAT_OR) 809 sport->port.icount.overrun++; 810 811 if (sr & sport->port.ignore_status_mask) { 812 if (++ignored > 100) 813 goto out; 814 continue; 815 } 816 817 sr &= sport->port.read_status_mask; 818 819 if (sr & UARTSTAT_PE) 820 flg = TTY_PARITY; 821 else if (sr & UARTSTAT_FE) 822 flg = TTY_FRAME; 823 824 if (sr & UARTSTAT_OR) 825 flg = TTY_OVERRUN; 826 827 #ifdef SUPPORT_SYSRQ 828 sport->port.sysrq = 0; 829 #endif 830 } 831 832 tty_insert_flip_char(port, rx, flg); 833 } 834 835 out: 836 spin_unlock_irqrestore(&sport->port.lock, flags); 837 838 tty_flip_buffer_push(port); 839 return IRQ_HANDLED; 840 } 841 842 static irqreturn_t lpuart_int(int irq, void *dev_id) 843 { 844 struct lpuart_port *sport = dev_id; 845 unsigned char sts; 846 847 sts = readb(sport->port.membase + UARTSR1); 848 849 if (sts & UARTSR1_RDRF) 850 lpuart_rxint(irq, dev_id); 851 852 if (sts & UARTSR1_TDRE) 853 lpuart_txint(irq, dev_id); 854 855 return IRQ_HANDLED; 856 } 857 858 static irqreturn_t lpuart32_int(int irq, void *dev_id) 859 { 860 struct lpuart_port *sport = dev_id; 861 unsigned long sts, rxcount; 862 863 sts = lpuart32_read(&sport->port, UARTSTAT); 864 rxcount = lpuart32_read(&sport->port, UARTWATER); 865 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 866 867 if (sts & UARTSTAT_RDRF || rxcount > 0) 868 lpuart32_rxint(irq, dev_id); 869 870 if ((sts & UARTSTAT_TDRE) && 871 !(lpuart32_read(&sport->port, UARTBAUD) & UARTBAUD_TDMAE)) 872 lpuart_txint(irq, dev_id); 873 874 lpuart32_write(&sport->port, sts, UARTSTAT); 875 return IRQ_HANDLED; 876 } 877 878 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 879 { 880 struct tty_port *port = &sport->port.state->port; 881 struct dma_tx_state state; 882 enum dma_status dmastat; 883 struct circ_buf *ring = &sport->rx_ring; 884 unsigned long flags; 885 int count = 0; 886 unsigned char sr; 887 888 sr = readb(sport->port.membase + UARTSR1); 889 890 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 891 /* Read DR to clear the error flags */ 892 readb(sport->port.membase + UARTDR); 893 894 if (sr & UARTSR1_PE) 895 sport->port.icount.parity++; 896 else if (sr & UARTSR1_FE) 897 sport->port.icount.frame++; 898 } 899 900 async_tx_ack(sport->dma_rx_desc); 901 902 spin_lock_irqsave(&sport->port.lock, flags); 903 904 dmastat = dmaengine_tx_status(sport->dma_rx_chan, 905 sport->dma_rx_cookie, 906 &state); 907 908 if (dmastat == DMA_ERROR) { 909 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 910 spin_unlock_irqrestore(&sport->port.lock, flags); 911 return; 912 } 913 914 /* CPU claims ownership of RX DMA buffer */ 915 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 916 917 /* 918 * ring->head points to the end of data already written by the DMA. 919 * ring->tail points to the beginning of data to be read by the 920 * framework. 921 * The current transfer size should not be larger than the dma buffer 922 * length. 923 */ 924 ring->head = sport->rx_sgl.length - state.residue; 925 BUG_ON(ring->head > sport->rx_sgl.length); 926 /* 927 * At this point ring->head may point to the first byte right after the 928 * last byte of the dma buffer: 929 * 0 <= ring->head <= sport->rx_sgl.length 930 * 931 * However ring->tail must always points inside the dma buffer: 932 * 0 <= ring->tail <= sport->rx_sgl.length - 1 933 * 934 * Since we use a ring buffer, we have to handle the case 935 * where head is lower than tail. In such a case, we first read from 936 * tail to the end of the buffer then reset tail. 937 */ 938 if (ring->head < ring->tail) { 939 count = sport->rx_sgl.length - ring->tail; 940 941 tty_insert_flip_string(port, ring->buf + ring->tail, count); 942 ring->tail = 0; 943 sport->port.icount.rx += count; 944 } 945 946 /* Finally we read data from tail to head */ 947 if (ring->tail < ring->head) { 948 count = ring->head - ring->tail; 949 tty_insert_flip_string(port, ring->buf + ring->tail, count); 950 /* Wrap ring->head if needed */ 951 if (ring->head >= sport->rx_sgl.length) 952 ring->head = 0; 953 ring->tail = ring->head; 954 sport->port.icount.rx += count; 955 } 956 957 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1, 958 DMA_FROM_DEVICE); 959 960 spin_unlock_irqrestore(&sport->port.lock, flags); 961 962 tty_flip_buffer_push(port); 963 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 964 } 965 966 static void lpuart_dma_rx_complete(void *arg) 967 { 968 struct lpuart_port *sport = arg; 969 970 lpuart_copy_rx_to_tty(sport); 971 } 972 973 static void lpuart_timer_func(unsigned long data) 974 { 975 struct lpuart_port *sport = (struct lpuart_port *)data; 976 977 lpuart_copy_rx_to_tty(sport); 978 } 979 980 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 981 { 982 struct dma_slave_config dma_rx_sconfig = {}; 983 struct circ_buf *ring = &sport->rx_ring; 984 int ret, nent; 985 int bits, baud; 986 struct tty_struct *tty = tty_port_tty_get(&sport->port.state->port); 987 struct ktermios *termios = &tty->termios; 988 989 baud = tty_get_baud_rate(tty); 990 991 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; 992 if (termios->c_cflag & PARENB) 993 bits++; 994 995 /* 996 * Calculate length of one DMA buffer size to keep latency below 997 * 10ms at any baud rate. 998 */ 999 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 1000 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 1001 if (sport->rx_dma_rng_buf_len < 16) 1002 sport->rx_dma_rng_buf_len = 16; 1003 1004 ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1005 if (!ring->buf) { 1006 dev_err(sport->port.dev, "Ring buf alloc failed\n"); 1007 return -ENOMEM; 1008 } 1009 1010 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1011 sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1012 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1013 1014 if (!nent) { 1015 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1016 return -EINVAL; 1017 } 1018 1019 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR; 1020 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1021 dma_rx_sconfig.src_maxburst = 1; 1022 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1023 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig); 1024 1025 if (ret < 0) { 1026 dev_err(sport->port.dev, 1027 "DMA Rx slave config failed, err = %d\n", ret); 1028 return ret; 1029 } 1030 1031 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan, 1032 sg_dma_address(&sport->rx_sgl), 1033 sport->rx_sgl.length, 1034 sport->rx_sgl.length / 2, 1035 DMA_DEV_TO_MEM, 1036 DMA_PREP_INTERRUPT); 1037 if (!sport->dma_rx_desc) { 1038 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1039 return -EFAULT; 1040 } 1041 1042 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1043 sport->dma_rx_desc->callback_param = sport; 1044 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1045 dma_async_issue_pending(sport->dma_rx_chan); 1046 1047 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1048 sport->port.membase + UARTCR5); 1049 1050 return 0; 1051 } 1052 1053 static void lpuart_dma_rx_free(struct uart_port *port) 1054 { 1055 struct lpuart_port *sport = container_of(port, 1056 struct lpuart_port, port); 1057 1058 if (sport->dma_rx_chan) 1059 dmaengine_terminate_all(sport->dma_rx_chan); 1060 1061 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1062 kfree(sport->rx_ring.buf); 1063 sport->rx_ring.tail = 0; 1064 sport->rx_ring.head = 0; 1065 sport->dma_rx_desc = NULL; 1066 sport->dma_rx_cookie = -EINVAL; 1067 } 1068 1069 static int lpuart_config_rs485(struct uart_port *port, 1070 struct serial_rs485 *rs485) 1071 { 1072 struct lpuart_port *sport = container_of(port, 1073 struct lpuart_port, port); 1074 1075 u8 modem = readb(sport->port.membase + UARTMODEM) & 1076 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1077 writeb(modem, sport->port.membase + UARTMODEM); 1078 1079 /* clear unsupported configurations */ 1080 rs485->delay_rts_before_send = 0; 1081 rs485->delay_rts_after_send = 0; 1082 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1083 1084 if (rs485->flags & SER_RS485_ENABLED) { 1085 /* Enable auto RS-485 RTS mode */ 1086 modem |= UARTMODEM_TXRTSE; 1087 1088 /* 1089 * RTS needs to be logic HIGH either during transer _or_ after 1090 * transfer, other variants are not supported by the hardware. 1091 */ 1092 1093 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1094 SER_RS485_RTS_AFTER_SEND))) 1095 rs485->flags |= SER_RS485_RTS_ON_SEND; 1096 1097 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1098 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1099 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1100 1101 /* 1102 * The hardware defaults to RTS logic HIGH while transfer. 1103 * Switch polarity in case RTS shall be logic HIGH 1104 * after transfer. 1105 * Note: UART is assumed to be active high. 1106 */ 1107 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1108 modem &= ~UARTMODEM_TXRTSPOL; 1109 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1110 modem |= UARTMODEM_TXRTSPOL; 1111 } 1112 1113 /* Store the new configuration */ 1114 sport->port.rs485 = *rs485; 1115 1116 writeb(modem, sport->port.membase + UARTMODEM); 1117 return 0; 1118 } 1119 1120 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1121 { 1122 unsigned int temp = 0; 1123 unsigned char reg; 1124 1125 reg = readb(port->membase + UARTMODEM); 1126 if (reg & UARTMODEM_TXCTSE) 1127 temp |= TIOCM_CTS; 1128 1129 if (reg & UARTMODEM_RXRTSE) 1130 temp |= TIOCM_RTS; 1131 1132 return temp; 1133 } 1134 1135 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1136 { 1137 unsigned int temp = 0; 1138 unsigned long reg; 1139 1140 reg = lpuart32_read(port, UARTMODIR); 1141 if (reg & UARTMODIR_TXCTSE) 1142 temp |= TIOCM_CTS; 1143 1144 if (reg & UARTMODIR_RXRTSE) 1145 temp |= TIOCM_RTS; 1146 1147 return temp; 1148 } 1149 1150 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1151 { 1152 unsigned char temp; 1153 struct lpuart_port *sport = container_of(port, 1154 struct lpuart_port, port); 1155 1156 /* Make sure RXRTSE bit is not set when RS485 is enabled */ 1157 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { 1158 temp = readb(sport->port.membase + UARTMODEM) & 1159 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1160 1161 if (mctrl & TIOCM_RTS) 1162 temp |= UARTMODEM_RXRTSE; 1163 1164 if (mctrl & TIOCM_CTS) 1165 temp |= UARTMODEM_TXCTSE; 1166 1167 writeb(temp, port->membase + UARTMODEM); 1168 } 1169 } 1170 1171 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1172 { 1173 unsigned long temp; 1174 1175 temp = lpuart32_read(port, UARTMODIR) & 1176 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 1177 1178 if (mctrl & TIOCM_RTS) 1179 temp |= UARTMODIR_RXRTSE; 1180 1181 if (mctrl & TIOCM_CTS) 1182 temp |= UARTMODIR_TXCTSE; 1183 1184 lpuart32_write(port, temp, UARTMODIR); 1185 } 1186 1187 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1188 { 1189 unsigned char temp; 1190 1191 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1192 1193 if (break_state != 0) 1194 temp |= UARTCR2_SBK; 1195 1196 writeb(temp, port->membase + UARTCR2); 1197 } 1198 1199 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1200 { 1201 unsigned long temp; 1202 1203 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; 1204 1205 if (break_state != 0) 1206 temp |= UARTCTRL_SBK; 1207 1208 lpuart32_write(port, temp, UARTCTRL); 1209 } 1210 1211 static void lpuart_setup_watermark(struct lpuart_port *sport) 1212 { 1213 unsigned char val, cr2; 1214 unsigned char cr2_saved; 1215 1216 cr2 = readb(sport->port.membase + UARTCR2); 1217 cr2_saved = cr2; 1218 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1219 UARTCR2_RIE | UARTCR2_RE); 1220 writeb(cr2, sport->port.membase + UARTCR2); 1221 1222 val = readb(sport->port.membase + UARTPFIFO); 1223 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1224 sport->port.membase + UARTPFIFO); 1225 1226 /* flush Tx and Rx FIFO */ 1227 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1228 sport->port.membase + UARTCFIFO); 1229 1230 /* explicitly clear RDRF */ 1231 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1232 readb(sport->port.membase + UARTDR); 1233 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1234 } 1235 1236 writeb(0, sport->port.membase + UARTTWFIFO); 1237 writeb(1, sport->port.membase + UARTRWFIFO); 1238 1239 /* Restore cr2 */ 1240 writeb(cr2_saved, sport->port.membase + UARTCR2); 1241 } 1242 1243 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1244 { 1245 unsigned long val, ctrl; 1246 unsigned long ctrl_saved; 1247 1248 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1249 ctrl_saved = ctrl; 1250 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1251 UARTCTRL_RIE | UARTCTRL_RE); 1252 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1253 1254 /* enable FIFO mode */ 1255 val = lpuart32_read(&sport->port, UARTFIFO); 1256 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1257 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1258 lpuart32_write(&sport->port, val, UARTFIFO); 1259 1260 /* set the watermark */ 1261 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1262 lpuart32_write(&sport->port, val, UARTWATER); 1263 1264 /* Restore cr2 */ 1265 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1266 } 1267 1268 static void rx_dma_timer_init(struct lpuart_port *sport) 1269 { 1270 setup_timer(&sport->lpuart_timer, lpuart_timer_func, 1271 (unsigned long)sport); 1272 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1273 add_timer(&sport->lpuart_timer); 1274 } 1275 1276 static int lpuart_startup(struct uart_port *port) 1277 { 1278 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1279 unsigned long flags; 1280 unsigned char temp; 1281 1282 /* determine FIFO size and enable FIFO mode */ 1283 temp = readb(sport->port.membase + UARTPFIFO); 1284 1285 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) & 1286 UARTPFIFO_FIFOSIZE_MASK) + 1); 1287 1288 sport->port.fifosize = sport->txfifo_size; 1289 1290 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) & 1291 UARTPFIFO_FIFOSIZE_MASK) + 1); 1292 1293 spin_lock_irqsave(&sport->port.lock, flags); 1294 1295 lpuart_setup_watermark(sport); 1296 1297 temp = readb(sport->port.membase + UARTCR2); 1298 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 1299 writeb(temp, sport->port.membase + UARTCR2); 1300 1301 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) { 1302 /* set Rx DMA timeout */ 1303 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1304 if (!sport->dma_rx_timeout) 1305 sport->dma_rx_timeout = 1; 1306 1307 sport->lpuart_dma_rx_use = true; 1308 rx_dma_timer_init(sport); 1309 } else { 1310 sport->lpuart_dma_rx_use = false; 1311 } 1312 1313 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) { 1314 init_waitqueue_head(&sport->dma_wait); 1315 sport->lpuart_dma_tx_use = true; 1316 temp = readb(port->membase + UARTCR5); 1317 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5); 1318 } else { 1319 sport->lpuart_dma_tx_use = false; 1320 } 1321 1322 spin_unlock_irqrestore(&sport->port.lock, flags); 1323 1324 return 0; 1325 } 1326 1327 static int lpuart32_startup(struct uart_port *port) 1328 { 1329 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1330 unsigned long flags; 1331 unsigned long temp; 1332 1333 /* determine FIFO size */ 1334 temp = lpuart32_read(&sport->port, UARTFIFO); 1335 1336 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) & 1337 UARTFIFO_FIFOSIZE_MASK) - 1); 1338 1339 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) & 1340 UARTFIFO_FIFOSIZE_MASK) - 1); 1341 1342 spin_lock_irqsave(&sport->port.lock, flags); 1343 1344 lpuart32_setup_watermark(sport); 1345 1346 temp = lpuart32_read(&sport->port, UARTCTRL); 1347 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE); 1348 temp |= UARTCTRL_ILIE; 1349 lpuart32_write(&sport->port, temp, UARTCTRL); 1350 1351 spin_unlock_irqrestore(&sport->port.lock, flags); 1352 return 0; 1353 } 1354 1355 static void lpuart_shutdown(struct uart_port *port) 1356 { 1357 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1358 unsigned char temp; 1359 unsigned long flags; 1360 1361 spin_lock_irqsave(&port->lock, flags); 1362 1363 /* disable Rx/Tx and interrupts */ 1364 temp = readb(port->membase + UARTCR2); 1365 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1366 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1367 writeb(temp, port->membase + UARTCR2); 1368 1369 spin_unlock_irqrestore(&port->lock, flags); 1370 1371 if (sport->lpuart_dma_rx_use) { 1372 del_timer_sync(&sport->lpuart_timer); 1373 lpuart_dma_rx_free(&sport->port); 1374 } 1375 1376 if (sport->lpuart_dma_tx_use) { 1377 if (wait_event_interruptible(sport->dma_wait, 1378 !sport->dma_tx_in_progress) != false) { 1379 sport->dma_tx_in_progress = false; 1380 dmaengine_terminate_all(sport->dma_tx_chan); 1381 } 1382 1383 lpuart_stop_tx(port); 1384 } 1385 } 1386 1387 static void lpuart32_shutdown(struct uart_port *port) 1388 { 1389 unsigned long temp; 1390 unsigned long flags; 1391 1392 spin_lock_irqsave(&port->lock, flags); 1393 1394 /* disable Rx/Tx and interrupts */ 1395 temp = lpuart32_read(port, UARTCTRL); 1396 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1397 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1398 lpuart32_write(port, temp, UARTCTRL); 1399 1400 spin_unlock_irqrestore(&port->lock, flags); 1401 } 1402 1403 static void 1404 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1405 struct ktermios *old) 1406 { 1407 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1408 unsigned long flags; 1409 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1410 unsigned int baud; 1411 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1412 unsigned int sbr, brfa; 1413 1414 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1415 old_cr2 = readb(sport->port.membase + UARTCR2); 1416 cr3 = readb(sport->port.membase + UARTCR3); 1417 cr4 = readb(sport->port.membase + UARTCR4); 1418 bdh = readb(sport->port.membase + UARTBDH); 1419 modem = readb(sport->port.membase + UARTMODEM); 1420 /* 1421 * only support CS8 and CS7, and for CS7 must enable PE. 1422 * supported mode: 1423 * - (7,e/o,1) 1424 * - (8,n,1) 1425 * - (8,m/s,1) 1426 * - (8,e/o,1) 1427 */ 1428 while ((termios->c_cflag & CSIZE) != CS8 && 1429 (termios->c_cflag & CSIZE) != CS7) { 1430 termios->c_cflag &= ~CSIZE; 1431 termios->c_cflag |= old_csize; 1432 old_csize = CS8; 1433 } 1434 1435 if ((termios->c_cflag & CSIZE) == CS8 || 1436 (termios->c_cflag & CSIZE) == CS7) 1437 cr1 = old_cr1 & ~UARTCR1_M; 1438 1439 if (termios->c_cflag & CMSPAR) { 1440 if ((termios->c_cflag & CSIZE) != CS8) { 1441 termios->c_cflag &= ~CSIZE; 1442 termios->c_cflag |= CS8; 1443 } 1444 cr1 |= UARTCR1_M; 1445 } 1446 1447 /* 1448 * When auto RS-485 RTS mode is enabled, 1449 * hardware flow control need to be disabled. 1450 */ 1451 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1452 termios->c_cflag &= ~CRTSCTS; 1453 1454 if (termios->c_cflag & CRTSCTS) { 1455 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1456 } else { 1457 termios->c_cflag &= ~CRTSCTS; 1458 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1459 } 1460 1461 if (termios->c_cflag & CSTOPB) 1462 termios->c_cflag &= ~CSTOPB; 1463 1464 /* parity must be enabled when CS7 to match 8-bits format */ 1465 if ((termios->c_cflag & CSIZE) == CS7) 1466 termios->c_cflag |= PARENB; 1467 1468 if ((termios->c_cflag & PARENB)) { 1469 if (termios->c_cflag & CMSPAR) { 1470 cr1 &= ~UARTCR1_PE; 1471 if (termios->c_cflag & PARODD) 1472 cr3 |= UARTCR3_T8; 1473 else 1474 cr3 &= ~UARTCR3_T8; 1475 } else { 1476 cr1 |= UARTCR1_PE; 1477 if ((termios->c_cflag & CSIZE) == CS8) 1478 cr1 |= UARTCR1_M; 1479 if (termios->c_cflag & PARODD) 1480 cr1 |= UARTCR1_PT; 1481 else 1482 cr1 &= ~UARTCR1_PT; 1483 } 1484 } 1485 1486 /* ask the core to calculate the divisor */ 1487 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1488 1489 /* 1490 * Need to update the Ring buffer length according to the selected 1491 * baud rate and restart Rx DMA path. 1492 * 1493 * Since timer function acqures sport->port.lock, need to stop before 1494 * acquring same lock because otherwise del_timer_sync() can deadlock. 1495 */ 1496 if (old && sport->lpuart_dma_rx_use) { 1497 del_timer_sync(&sport->lpuart_timer); 1498 lpuart_dma_rx_free(&sport->port); 1499 } 1500 1501 spin_lock_irqsave(&sport->port.lock, flags); 1502 1503 sport->port.read_status_mask = 0; 1504 if (termios->c_iflag & INPCK) 1505 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE); 1506 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1507 sport->port.read_status_mask |= UARTSR1_FE; 1508 1509 /* characters to ignore */ 1510 sport->port.ignore_status_mask = 0; 1511 if (termios->c_iflag & IGNPAR) 1512 sport->port.ignore_status_mask |= UARTSR1_PE; 1513 if (termios->c_iflag & IGNBRK) { 1514 sport->port.ignore_status_mask |= UARTSR1_FE; 1515 /* 1516 * if we're ignoring parity and break indicators, 1517 * ignore overruns too (for real raw support). 1518 */ 1519 if (termios->c_iflag & IGNPAR) 1520 sport->port.ignore_status_mask |= UARTSR1_OR; 1521 } 1522 1523 /* update the per-port timeout */ 1524 uart_update_timeout(port, termios->c_cflag, baud); 1525 1526 /* wait transmit engin complete */ 1527 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1528 barrier(); 1529 1530 /* disable transmit and receive */ 1531 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1532 sport->port.membase + UARTCR2); 1533 1534 sbr = sport->port.uartclk / (16 * baud); 1535 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1536 bdh &= ~UARTBDH_SBR_MASK; 1537 bdh |= (sbr >> 8) & 0x1F; 1538 cr4 &= ~UARTCR4_BRFA_MASK; 1539 brfa &= UARTCR4_BRFA_MASK; 1540 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1541 writeb(bdh, sport->port.membase + UARTBDH); 1542 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1543 writeb(cr3, sport->port.membase + UARTCR3); 1544 writeb(cr1, sport->port.membase + UARTCR1); 1545 writeb(modem, sport->port.membase + UARTMODEM); 1546 1547 /* restore control register */ 1548 writeb(old_cr2, sport->port.membase + UARTCR2); 1549 1550 if (old && sport->lpuart_dma_rx_use) { 1551 if (!lpuart_start_rx_dma(sport)) 1552 rx_dma_timer_init(sport); 1553 else 1554 sport->lpuart_dma_rx_use = false; 1555 } 1556 1557 spin_unlock_irqrestore(&sport->port.lock, flags); 1558 } 1559 1560 static void 1561 lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate) 1562 { 1563 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; 1564 u32 clk = sport->port.uartclk; 1565 1566 /* 1567 * The idea is to use the best OSR (over-sampling rate) possible. 1568 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 1569 * Loop to find the best OSR value possible, one that generates minimum 1570 * baud_diff iterate through the rest of the supported values of OSR. 1571 * 1572 * Calculation Formula: 1573 * Baud Rate = baud clock / ((OSR+1) × SBR) 1574 */ 1575 baud_diff = baudrate; 1576 osr = 0; 1577 sbr = 0; 1578 1579 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 1580 /* calculate the temporary sbr value */ 1581 tmp_sbr = (clk / (baudrate * tmp_osr)); 1582 if (tmp_sbr == 0) 1583 tmp_sbr = 1; 1584 1585 /* 1586 * calculate the baud rate difference based on the temporary 1587 * osr and sbr values 1588 */ 1589 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 1590 1591 /* select best values between sbr and sbr+1 */ 1592 tmp = clk / (tmp_osr * (tmp_sbr + 1)); 1593 if (tmp_diff > (baudrate - tmp)) { 1594 tmp_diff = baudrate - tmp; 1595 tmp_sbr++; 1596 } 1597 1598 if (tmp_diff <= baud_diff) { 1599 baud_diff = tmp_diff; 1600 osr = tmp_osr; 1601 sbr = tmp_sbr; 1602 1603 if (!baud_diff) 1604 break; 1605 } 1606 } 1607 1608 /* handle buadrate outside acceptable rate */ 1609 if (baud_diff > ((baudrate / 100) * 3)) 1610 dev_warn(sport->port.dev, 1611 "unacceptable baud rate difference of more than 3%%\n"); 1612 1613 tmp = lpuart32_read(&sport->port, UARTBAUD); 1614 1615 if ((osr > 3) && (osr < 8)) 1616 tmp |= UARTBAUD_BOTHEDGE; 1617 1618 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 1619 tmp |= (((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT); 1620 1621 tmp &= ~UARTBAUD_SBR_MASK; 1622 tmp |= sbr & UARTBAUD_SBR_MASK; 1623 1624 tmp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); 1625 1626 lpuart32_write(&sport->port, tmp, UARTBAUD); 1627 } 1628 1629 static void 1630 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 1631 struct ktermios *old) 1632 { 1633 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1634 unsigned long flags; 1635 unsigned long ctrl, old_ctrl, bd, modem; 1636 unsigned int baud; 1637 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1638 1639 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); 1640 bd = lpuart32_read(&sport->port, UARTBAUD); 1641 modem = lpuart32_read(&sport->port, UARTMODIR); 1642 /* 1643 * only support CS8 and CS7, and for CS7 must enable PE. 1644 * supported mode: 1645 * - (7,e/o,1) 1646 * - (8,n,1) 1647 * - (8,m/s,1) 1648 * - (8,e/o,1) 1649 */ 1650 while ((termios->c_cflag & CSIZE) != CS8 && 1651 (termios->c_cflag & CSIZE) != CS7) { 1652 termios->c_cflag &= ~CSIZE; 1653 termios->c_cflag |= old_csize; 1654 old_csize = CS8; 1655 } 1656 1657 if ((termios->c_cflag & CSIZE) == CS8 || 1658 (termios->c_cflag & CSIZE) == CS7) 1659 ctrl = old_ctrl & ~UARTCTRL_M; 1660 1661 if (termios->c_cflag & CMSPAR) { 1662 if ((termios->c_cflag & CSIZE) != CS8) { 1663 termios->c_cflag &= ~CSIZE; 1664 termios->c_cflag |= CS8; 1665 } 1666 ctrl |= UARTCTRL_M; 1667 } 1668 1669 if (termios->c_cflag & CRTSCTS) { 1670 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1671 } else { 1672 termios->c_cflag &= ~CRTSCTS; 1673 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1674 } 1675 1676 if (termios->c_cflag & CSTOPB) 1677 termios->c_cflag &= ~CSTOPB; 1678 1679 /* parity must be enabled when CS7 to match 8-bits format */ 1680 if ((termios->c_cflag & CSIZE) == CS7) 1681 termios->c_cflag |= PARENB; 1682 1683 if ((termios->c_cflag & PARENB)) { 1684 if (termios->c_cflag & CMSPAR) { 1685 ctrl &= ~UARTCTRL_PE; 1686 ctrl |= UARTCTRL_M; 1687 } else { 1688 ctrl |= UARTCR1_PE; 1689 if ((termios->c_cflag & CSIZE) == CS8) 1690 ctrl |= UARTCTRL_M; 1691 if (termios->c_cflag & PARODD) 1692 ctrl |= UARTCTRL_PT; 1693 else 1694 ctrl &= ~UARTCTRL_PT; 1695 } 1696 } 1697 1698 /* ask the core to calculate the divisor */ 1699 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1700 1701 spin_lock_irqsave(&sport->port.lock, flags); 1702 1703 sport->port.read_status_mask = 0; 1704 if (termios->c_iflag & INPCK) 1705 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE); 1706 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1707 sport->port.read_status_mask |= UARTSTAT_FE; 1708 1709 /* characters to ignore */ 1710 sport->port.ignore_status_mask = 0; 1711 if (termios->c_iflag & IGNPAR) 1712 sport->port.ignore_status_mask |= UARTSTAT_PE; 1713 if (termios->c_iflag & IGNBRK) { 1714 sport->port.ignore_status_mask |= UARTSTAT_FE; 1715 /* 1716 * if we're ignoring parity and break indicators, 1717 * ignore overruns too (for real raw support). 1718 */ 1719 if (termios->c_iflag & IGNPAR) 1720 sport->port.ignore_status_mask |= UARTSTAT_OR; 1721 } 1722 1723 /* update the per-port timeout */ 1724 uart_update_timeout(port, termios->c_cflag, baud); 1725 1726 /* wait transmit engin complete */ 1727 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC)) 1728 barrier(); 1729 1730 /* disable transmit and receive */ 1731 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 1732 UARTCTRL); 1733 1734 lpuart32_serial_setbrg(sport, baud); 1735 lpuart32_write(&sport->port, modem, UARTMODIR); 1736 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1737 /* restore control register */ 1738 1739 spin_unlock_irqrestore(&sport->port.lock, flags); 1740 } 1741 1742 static const char *lpuart_type(struct uart_port *port) 1743 { 1744 return "FSL_LPUART"; 1745 } 1746 1747 static void lpuart_release_port(struct uart_port *port) 1748 { 1749 /* nothing to do */ 1750 } 1751 1752 static int lpuart_request_port(struct uart_port *port) 1753 { 1754 return 0; 1755 } 1756 1757 /* configure/autoconfigure the port */ 1758 static void lpuart_config_port(struct uart_port *port, int flags) 1759 { 1760 if (flags & UART_CONFIG_TYPE) 1761 port->type = PORT_LPUART; 1762 } 1763 1764 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 1765 { 1766 int ret = 0; 1767 1768 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 1769 ret = -EINVAL; 1770 if (port->irq != ser->irq) 1771 ret = -EINVAL; 1772 if (ser->io_type != UPIO_MEM) 1773 ret = -EINVAL; 1774 if (port->uartclk / 16 != ser->baud_base) 1775 ret = -EINVAL; 1776 if (port->iobase != ser->port) 1777 ret = -EINVAL; 1778 if (ser->hub6 != 0) 1779 ret = -EINVAL; 1780 return ret; 1781 } 1782 1783 static const struct uart_ops lpuart_pops = { 1784 .tx_empty = lpuart_tx_empty, 1785 .set_mctrl = lpuart_set_mctrl, 1786 .get_mctrl = lpuart_get_mctrl, 1787 .stop_tx = lpuart_stop_tx, 1788 .start_tx = lpuart_start_tx, 1789 .stop_rx = lpuart_stop_rx, 1790 .break_ctl = lpuart_break_ctl, 1791 .startup = lpuart_startup, 1792 .shutdown = lpuart_shutdown, 1793 .set_termios = lpuart_set_termios, 1794 .type = lpuart_type, 1795 .request_port = lpuart_request_port, 1796 .release_port = lpuart_release_port, 1797 .config_port = lpuart_config_port, 1798 .verify_port = lpuart_verify_port, 1799 .flush_buffer = lpuart_flush_buffer, 1800 #if defined(CONFIG_CONSOLE_POLL) 1801 .poll_init = lpuart_poll_init, 1802 .poll_get_char = lpuart_poll_get_char, 1803 .poll_put_char = lpuart_poll_put_char, 1804 #endif 1805 }; 1806 1807 static const struct uart_ops lpuart32_pops = { 1808 .tx_empty = lpuart32_tx_empty, 1809 .set_mctrl = lpuart32_set_mctrl, 1810 .get_mctrl = lpuart32_get_mctrl, 1811 .stop_tx = lpuart32_stop_tx, 1812 .start_tx = lpuart32_start_tx, 1813 .stop_rx = lpuart32_stop_rx, 1814 .break_ctl = lpuart32_break_ctl, 1815 .startup = lpuart32_startup, 1816 .shutdown = lpuart32_shutdown, 1817 .set_termios = lpuart32_set_termios, 1818 .type = lpuart_type, 1819 .request_port = lpuart_request_port, 1820 .release_port = lpuart_release_port, 1821 .config_port = lpuart_config_port, 1822 .verify_port = lpuart_verify_port, 1823 .flush_buffer = lpuart_flush_buffer, 1824 #if defined(CONFIG_CONSOLE_POLL) 1825 .poll_init = lpuart32_poll_init, 1826 .poll_get_char = lpuart32_poll_get_char, 1827 .poll_put_char = lpuart32_poll_put_char, 1828 #endif 1829 }; 1830 1831 static struct lpuart_port *lpuart_ports[UART_NR]; 1832 1833 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 1834 static void lpuart_console_putchar(struct uart_port *port, int ch) 1835 { 1836 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) 1837 barrier(); 1838 1839 writeb(ch, port->membase + UARTDR); 1840 } 1841 1842 static void lpuart32_console_putchar(struct uart_port *port, int ch) 1843 { 1844 while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)) 1845 barrier(); 1846 1847 lpuart32_write(port, ch, UARTDATA); 1848 } 1849 1850 static void 1851 lpuart_console_write(struct console *co, const char *s, unsigned int count) 1852 { 1853 struct lpuart_port *sport = lpuart_ports[co->index]; 1854 unsigned char old_cr2, cr2; 1855 unsigned long flags; 1856 int locked = 1; 1857 1858 if (sport->port.sysrq || oops_in_progress) 1859 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1860 else 1861 spin_lock_irqsave(&sport->port.lock, flags); 1862 1863 /* first save CR2 and then disable interrupts */ 1864 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 1865 cr2 |= (UARTCR2_TE | UARTCR2_RE); 1866 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1867 writeb(cr2, sport->port.membase + UARTCR2); 1868 1869 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 1870 1871 /* wait for transmitter finish complete and restore CR2 */ 1872 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1873 barrier(); 1874 1875 writeb(old_cr2, sport->port.membase + UARTCR2); 1876 1877 if (locked) 1878 spin_unlock_irqrestore(&sport->port.lock, flags); 1879 } 1880 1881 static void 1882 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 1883 { 1884 struct lpuart_port *sport = lpuart_ports[co->index]; 1885 unsigned long old_cr, cr; 1886 unsigned long flags; 1887 int locked = 1; 1888 1889 if (sport->port.sysrq || oops_in_progress) 1890 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1891 else 1892 spin_lock_irqsave(&sport->port.lock, flags); 1893 1894 /* first save CR2 and then disable interrupts */ 1895 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 1896 cr |= (UARTCTRL_TE | UARTCTRL_RE); 1897 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1898 lpuart32_write(&sport->port, cr, UARTCTRL); 1899 1900 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 1901 1902 /* wait for transmitter finish complete and restore CR2 */ 1903 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC)) 1904 barrier(); 1905 1906 lpuart32_write(&sport->port, old_cr, UARTCTRL); 1907 1908 if (locked) 1909 spin_unlock_irqrestore(&sport->port.lock, flags); 1910 } 1911 1912 /* 1913 * if the port was already initialised (eg, by a boot loader), 1914 * try to determine the current setup. 1915 */ 1916 static void __init 1917 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 1918 int *parity, int *bits) 1919 { 1920 unsigned char cr, bdh, bdl, brfa; 1921 unsigned int sbr, uartclk, baud_raw; 1922 1923 cr = readb(sport->port.membase + UARTCR2); 1924 cr &= UARTCR2_TE | UARTCR2_RE; 1925 if (!cr) 1926 return; 1927 1928 /* ok, the port was enabled */ 1929 1930 cr = readb(sport->port.membase + UARTCR1); 1931 1932 *parity = 'n'; 1933 if (cr & UARTCR1_PE) { 1934 if (cr & UARTCR1_PT) 1935 *parity = 'o'; 1936 else 1937 *parity = 'e'; 1938 } 1939 1940 if (cr & UARTCR1_M) 1941 *bits = 9; 1942 else 1943 *bits = 8; 1944 1945 bdh = readb(sport->port.membase + UARTBDH); 1946 bdh &= UARTBDH_SBR_MASK; 1947 bdl = readb(sport->port.membase + UARTBDL); 1948 sbr = bdh; 1949 sbr <<= 8; 1950 sbr |= bdl; 1951 brfa = readb(sport->port.membase + UARTCR4); 1952 brfa &= UARTCR4_BRFA_MASK; 1953 1954 uartclk = clk_get_rate(sport->clk); 1955 /* 1956 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 1957 */ 1958 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 1959 1960 if (*baud != baud_raw) 1961 printk(KERN_INFO "Serial: Console lpuart rounded baud rate" 1962 "from %d to %d\n", baud_raw, *baud); 1963 } 1964 1965 static void __init 1966 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 1967 int *parity, int *bits) 1968 { 1969 unsigned long cr, bd; 1970 unsigned int sbr, uartclk, baud_raw; 1971 1972 cr = lpuart32_read(&sport->port, UARTCTRL); 1973 cr &= UARTCTRL_TE | UARTCTRL_RE; 1974 if (!cr) 1975 return; 1976 1977 /* ok, the port was enabled */ 1978 1979 cr = lpuart32_read(&sport->port, UARTCTRL); 1980 1981 *parity = 'n'; 1982 if (cr & UARTCTRL_PE) { 1983 if (cr & UARTCTRL_PT) 1984 *parity = 'o'; 1985 else 1986 *parity = 'e'; 1987 } 1988 1989 if (cr & UARTCTRL_M) 1990 *bits = 9; 1991 else 1992 *bits = 8; 1993 1994 bd = lpuart32_read(&sport->port, UARTBAUD); 1995 bd &= UARTBAUD_SBR_MASK; 1996 sbr = bd; 1997 uartclk = clk_get_rate(sport->clk); 1998 /* 1999 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2000 */ 2001 baud_raw = uartclk / (16 * sbr); 2002 2003 if (*baud != baud_raw) 2004 printk(KERN_INFO "Serial: Console lpuart rounded baud rate" 2005 "from %d to %d\n", baud_raw, *baud); 2006 } 2007 2008 static int __init lpuart_console_setup(struct console *co, char *options) 2009 { 2010 struct lpuart_port *sport; 2011 int baud = 115200; 2012 int bits = 8; 2013 int parity = 'n'; 2014 int flow = 'n'; 2015 2016 /* 2017 * check whether an invalid uart number has been specified, and 2018 * if so, search for the first available port that does have 2019 * console support. 2020 */ 2021 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2022 co->index = 0; 2023 2024 sport = lpuart_ports[co->index]; 2025 if (sport == NULL) 2026 return -ENODEV; 2027 2028 if (options) 2029 uart_parse_options(options, &baud, &parity, &bits, &flow); 2030 else 2031 if (lpuart_is_32(sport)) 2032 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2033 else 2034 lpuart_console_get_options(sport, &baud, &parity, &bits); 2035 2036 if (lpuart_is_32(sport)) 2037 lpuart32_setup_watermark(sport); 2038 else 2039 lpuart_setup_watermark(sport); 2040 2041 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2042 } 2043 2044 static struct uart_driver lpuart_reg; 2045 static struct console lpuart_console = { 2046 .name = DEV_NAME, 2047 .write = lpuart_console_write, 2048 .device = uart_console_device, 2049 .setup = lpuart_console_setup, 2050 .flags = CON_PRINTBUFFER, 2051 .index = -1, 2052 .data = &lpuart_reg, 2053 }; 2054 2055 static struct console lpuart32_console = { 2056 .name = DEV_NAME, 2057 .write = lpuart32_console_write, 2058 .device = uart_console_device, 2059 .setup = lpuart_console_setup, 2060 .flags = CON_PRINTBUFFER, 2061 .index = -1, 2062 .data = &lpuart_reg, 2063 }; 2064 2065 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2066 { 2067 struct earlycon_device *dev = con->data; 2068 2069 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2070 } 2071 2072 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2073 { 2074 struct earlycon_device *dev = con->data; 2075 2076 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2077 } 2078 2079 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2080 const char *opt) 2081 { 2082 if (!device->port.membase) 2083 return -ENODEV; 2084 2085 device->con->write = lpuart_early_write; 2086 return 0; 2087 } 2088 2089 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2090 const char *opt) 2091 { 2092 if (!device->port.membase) 2093 return -ENODEV; 2094 2095 device->port.iotype = UPIO_MEM32BE; 2096 device->con->write = lpuart32_early_write; 2097 return 0; 2098 } 2099 2100 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2101 const char *opt) 2102 { 2103 if (!device->port.membase) 2104 return -ENODEV; 2105 2106 device->port.iotype = UPIO_MEM32; 2107 device->port.membase += IMX_REG_OFF; 2108 device->con->write = lpuart32_early_write; 2109 2110 return 0; 2111 } 2112 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2113 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2114 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2115 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2116 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2117 2118 #define LPUART_CONSOLE (&lpuart_console) 2119 #define LPUART32_CONSOLE (&lpuart32_console) 2120 #else 2121 #define LPUART_CONSOLE NULL 2122 #define LPUART32_CONSOLE NULL 2123 #endif 2124 2125 static struct uart_driver lpuart_reg = { 2126 .owner = THIS_MODULE, 2127 .driver_name = DRIVER_NAME, 2128 .dev_name = DEV_NAME, 2129 .nr = ARRAY_SIZE(lpuart_ports), 2130 .cons = LPUART_CONSOLE, 2131 }; 2132 2133 static int lpuart_probe(struct platform_device *pdev) 2134 { 2135 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids, 2136 &pdev->dev); 2137 const struct lpuart_soc_data *sdata = of_id->data; 2138 struct device_node *np = pdev->dev.of_node; 2139 struct lpuart_port *sport; 2140 struct resource *res; 2141 int ret; 2142 2143 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2144 if (!sport) 2145 return -ENOMEM; 2146 2147 pdev->dev.coherent_dma_mask = 0; 2148 2149 ret = of_alias_get_id(np, "serial"); 2150 if (ret < 0) { 2151 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2152 return ret; 2153 } 2154 sport->port.line = ret; 2155 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2156 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 2157 if (IS_ERR(sport->port.membase)) 2158 return PTR_ERR(sport->port.membase); 2159 2160 sport->port.membase += sdata->reg_off; 2161 sport->port.mapbase = res->start; 2162 sport->port.dev = &pdev->dev; 2163 sport->port.type = PORT_LPUART; 2164 ret = platform_get_irq(pdev, 0); 2165 if (ret < 0) { 2166 dev_err(&pdev->dev, "cannot obtain irq\n"); 2167 return ret; 2168 } 2169 sport->port.irq = ret; 2170 sport->port.iotype = sdata->iotype; 2171 if (lpuart_is_32(sport)) 2172 sport->port.ops = &lpuart32_pops; 2173 else 2174 sport->port.ops = &lpuart_pops; 2175 sport->port.flags = UPF_BOOT_AUTOCONF; 2176 2177 sport->port.rs485_config = lpuart_config_rs485; 2178 2179 sport->clk = devm_clk_get(&pdev->dev, "ipg"); 2180 if (IS_ERR(sport->clk)) { 2181 ret = PTR_ERR(sport->clk); 2182 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret); 2183 return ret; 2184 } 2185 2186 ret = clk_prepare_enable(sport->clk); 2187 if (ret) { 2188 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret); 2189 return ret; 2190 } 2191 2192 sport->port.uartclk = clk_get_rate(sport->clk); 2193 2194 lpuart_ports[sport->port.line] = sport; 2195 2196 platform_set_drvdata(pdev, &sport->port); 2197 2198 if (lpuart_is_32(sport)) { 2199 lpuart_reg.cons = LPUART32_CONSOLE; 2200 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0, 2201 DRIVER_NAME, sport); 2202 } else { 2203 lpuart_reg.cons = LPUART_CONSOLE; 2204 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0, 2205 DRIVER_NAME, sport); 2206 } 2207 2208 if (ret) 2209 goto failed_irq_request; 2210 2211 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2212 if (ret) 2213 goto failed_attach_port; 2214 2215 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx"); 2216 if (!sport->dma_tx_chan) 2217 dev_info(sport->port.dev, "DMA tx channel request failed, " 2218 "operating without tx DMA\n"); 2219 2220 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx"); 2221 if (!sport->dma_rx_chan) 2222 dev_info(sport->port.dev, "DMA rx channel request failed, " 2223 "operating without rx DMA\n"); 2224 2225 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) { 2226 sport->port.rs485.flags |= SER_RS485_ENABLED; 2227 sport->port.rs485.flags |= SER_RS485_RTS_ON_SEND; 2228 writeb(UARTMODEM_TXRTSE, sport->port.membase + UARTMODEM); 2229 } 2230 2231 return 0; 2232 2233 failed_attach_port: 2234 failed_irq_request: 2235 clk_disable_unprepare(sport->clk); 2236 return ret; 2237 } 2238 2239 static int lpuart_remove(struct platform_device *pdev) 2240 { 2241 struct lpuart_port *sport = platform_get_drvdata(pdev); 2242 2243 uart_remove_one_port(&lpuart_reg, &sport->port); 2244 2245 clk_disable_unprepare(sport->clk); 2246 2247 if (sport->dma_tx_chan) 2248 dma_release_channel(sport->dma_tx_chan); 2249 2250 if (sport->dma_rx_chan) 2251 dma_release_channel(sport->dma_rx_chan); 2252 2253 return 0; 2254 } 2255 2256 #ifdef CONFIG_PM_SLEEP 2257 static int lpuart_suspend(struct device *dev) 2258 { 2259 struct lpuart_port *sport = dev_get_drvdata(dev); 2260 unsigned long temp; 2261 bool irq_wake; 2262 2263 if (lpuart_is_32(sport)) { 2264 /* disable Rx/Tx and interrupts */ 2265 temp = lpuart32_read(&sport->port, UARTCTRL); 2266 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2267 lpuart32_write(&sport->port, temp, UARTCTRL); 2268 } else { 2269 /* disable Rx/Tx and interrupts */ 2270 temp = readb(sport->port.membase + UARTCR2); 2271 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2272 writeb(temp, sport->port.membase + UARTCR2); 2273 } 2274 2275 uart_suspend_port(&lpuart_reg, &sport->port); 2276 2277 /* uart_suspend_port() might set wakeup flag */ 2278 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2279 2280 if (sport->lpuart_dma_rx_use) { 2281 /* 2282 * EDMA driver during suspend will forcefully release any 2283 * non-idle DMA channels. If port wakeup is enabled or if port 2284 * is console port or 'no_console_suspend' is set the Rx DMA 2285 * cannot resume as as expected, hence gracefully release the 2286 * Rx DMA path before suspend and start Rx DMA path on resume. 2287 */ 2288 if (irq_wake) { 2289 del_timer_sync(&sport->lpuart_timer); 2290 lpuart_dma_rx_free(&sport->port); 2291 } 2292 2293 /* Disable Rx DMA to use UART port as wakeup source */ 2294 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS, 2295 sport->port.membase + UARTCR5); 2296 } 2297 2298 if (sport->lpuart_dma_tx_use) { 2299 sport->dma_tx_in_progress = false; 2300 dmaengine_terminate_all(sport->dma_tx_chan); 2301 } 2302 2303 if (sport->port.suspended && !irq_wake) 2304 clk_disable_unprepare(sport->clk); 2305 2306 return 0; 2307 } 2308 2309 static int lpuart_resume(struct device *dev) 2310 { 2311 struct lpuart_port *sport = dev_get_drvdata(dev); 2312 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2313 unsigned long temp; 2314 2315 if (sport->port.suspended && !irq_wake) 2316 clk_prepare_enable(sport->clk); 2317 2318 if (lpuart_is_32(sport)) { 2319 lpuart32_setup_watermark(sport); 2320 temp = lpuart32_read(&sport->port, UARTCTRL); 2321 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | 2322 UARTCTRL_TE | UARTCTRL_ILIE); 2323 lpuart32_write(&sport->port, temp, UARTCTRL); 2324 } else { 2325 lpuart_setup_watermark(sport); 2326 temp = readb(sport->port.membase + UARTCR2); 2327 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 2328 writeb(temp, sport->port.membase + UARTCR2); 2329 } 2330 2331 if (sport->lpuart_dma_rx_use) { 2332 if (irq_wake) { 2333 if (!lpuart_start_rx_dma(sport)) 2334 rx_dma_timer_init(sport); 2335 else 2336 sport->lpuart_dma_rx_use = false; 2337 } 2338 } 2339 2340 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) { 2341 init_waitqueue_head(&sport->dma_wait); 2342 sport->lpuart_dma_tx_use = true; 2343 writeb(readb(sport->port.membase + UARTCR5) | 2344 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 2345 } else { 2346 sport->lpuart_dma_tx_use = false; 2347 } 2348 2349 uart_resume_port(&lpuart_reg, &sport->port); 2350 2351 return 0; 2352 } 2353 #endif 2354 2355 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2356 2357 static struct platform_driver lpuart_driver = { 2358 .probe = lpuart_probe, 2359 .remove = lpuart_remove, 2360 .driver = { 2361 .name = "fsl-lpuart", 2362 .of_match_table = lpuart_dt_ids, 2363 .pm = &lpuart_pm_ops, 2364 }, 2365 }; 2366 2367 static int __init lpuart_serial_init(void) 2368 { 2369 int ret = uart_register_driver(&lpuart_reg); 2370 2371 if (ret) 2372 return ret; 2373 2374 ret = platform_driver_register(&lpuart_driver); 2375 if (ret) 2376 uart_unregister_driver(&lpuart_reg); 2377 2378 return ret; 2379 } 2380 2381 static void __exit lpuart_serial_exit(void) 2382 { 2383 platform_driver_unregister(&lpuart_driver); 2384 uart_unregister_driver(&lpuart_reg); 2385 } 2386 2387 module_init(lpuart_serial_init); 2388 module_exit(lpuart_serial_exit); 2389 2390 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2391 MODULE_LICENSE("GPL v2"); 2392