1 /* 2 * Freescale lpuart serial port driver 3 * 4 * Copyright 2012-2014 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 13 #define SUPPORT_SYSRQ 14 #endif 15 16 #include <linux/clk.h> 17 #include <linux/console.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/dmaengine.h> 20 #include <linux/dmapool.h> 21 #include <linux/io.h> 22 #include <linux/irq.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/of_dma.h> 27 #include <linux/serial_core.h> 28 #include <linux/slab.h> 29 #include <linux/tty_flip.h> 30 31 /* All registers are 8-bit width */ 32 #define UARTBDH 0x00 33 #define UARTBDL 0x01 34 #define UARTCR1 0x02 35 #define UARTCR2 0x03 36 #define UARTSR1 0x04 37 #define UARTCR3 0x06 38 #define UARTDR 0x07 39 #define UARTCR4 0x0a 40 #define UARTCR5 0x0b 41 #define UARTMODEM 0x0d 42 #define UARTPFIFO 0x10 43 #define UARTCFIFO 0x11 44 #define UARTSFIFO 0x12 45 #define UARTTWFIFO 0x13 46 #define UARTTCFIFO 0x14 47 #define UARTRWFIFO 0x15 48 49 #define UARTBDH_LBKDIE 0x80 50 #define UARTBDH_RXEDGIE 0x40 51 #define UARTBDH_SBR_MASK 0x1f 52 53 #define UARTCR1_LOOPS 0x80 54 #define UARTCR1_RSRC 0x20 55 #define UARTCR1_M 0x10 56 #define UARTCR1_WAKE 0x08 57 #define UARTCR1_ILT 0x04 58 #define UARTCR1_PE 0x02 59 #define UARTCR1_PT 0x01 60 61 #define UARTCR2_TIE 0x80 62 #define UARTCR2_TCIE 0x40 63 #define UARTCR2_RIE 0x20 64 #define UARTCR2_ILIE 0x10 65 #define UARTCR2_TE 0x08 66 #define UARTCR2_RE 0x04 67 #define UARTCR2_RWU 0x02 68 #define UARTCR2_SBK 0x01 69 70 #define UARTSR1_TDRE 0x80 71 #define UARTSR1_TC 0x40 72 #define UARTSR1_RDRF 0x20 73 #define UARTSR1_IDLE 0x10 74 #define UARTSR1_OR 0x08 75 #define UARTSR1_NF 0x04 76 #define UARTSR1_FE 0x02 77 #define UARTSR1_PE 0x01 78 79 #define UARTCR3_R8 0x80 80 #define UARTCR3_T8 0x40 81 #define UARTCR3_TXDIR 0x20 82 #define UARTCR3_TXINV 0x10 83 #define UARTCR3_ORIE 0x08 84 #define UARTCR3_NEIE 0x04 85 #define UARTCR3_FEIE 0x02 86 #define UARTCR3_PEIE 0x01 87 88 #define UARTCR4_MAEN1 0x80 89 #define UARTCR4_MAEN2 0x40 90 #define UARTCR4_M10 0x20 91 #define UARTCR4_BRFA_MASK 0x1f 92 #define UARTCR4_BRFA_OFF 0 93 94 #define UARTCR5_TDMAS 0x80 95 #define UARTCR5_RDMAS 0x20 96 97 #define UARTMODEM_RXRTSE 0x08 98 #define UARTMODEM_TXRTSPOL 0x04 99 #define UARTMODEM_TXRTSE 0x02 100 #define UARTMODEM_TXCTSE 0x01 101 102 #define UARTPFIFO_TXFE 0x80 103 #define UARTPFIFO_FIFOSIZE_MASK 0x7 104 #define UARTPFIFO_TXSIZE_OFF 4 105 #define UARTPFIFO_RXFE 0x08 106 #define UARTPFIFO_RXSIZE_OFF 0 107 108 #define UARTCFIFO_TXFLUSH 0x80 109 #define UARTCFIFO_RXFLUSH 0x40 110 #define UARTCFIFO_RXOFE 0x04 111 #define UARTCFIFO_TXOFE 0x02 112 #define UARTCFIFO_RXUFE 0x01 113 114 #define UARTSFIFO_TXEMPT 0x80 115 #define UARTSFIFO_RXEMPT 0x40 116 #define UARTSFIFO_RXOF 0x04 117 #define UARTSFIFO_TXOF 0x02 118 #define UARTSFIFO_RXUF 0x01 119 120 /* 32-bit register defination */ 121 #define UARTBAUD 0x00 122 #define UARTSTAT 0x04 123 #define UARTCTRL 0x08 124 #define UARTDATA 0x0C 125 #define UARTMATCH 0x10 126 #define UARTMODIR 0x14 127 #define UARTFIFO 0x18 128 #define UARTWATER 0x1c 129 130 #define UARTBAUD_MAEN1 0x80000000 131 #define UARTBAUD_MAEN2 0x40000000 132 #define UARTBAUD_M10 0x20000000 133 #define UARTBAUD_TDMAE 0x00800000 134 #define UARTBAUD_RDMAE 0x00200000 135 #define UARTBAUD_MATCFG 0x00400000 136 #define UARTBAUD_BOTHEDGE 0x00020000 137 #define UARTBAUD_RESYNCDIS 0x00010000 138 #define UARTBAUD_LBKDIE 0x00008000 139 #define UARTBAUD_RXEDGIE 0x00004000 140 #define UARTBAUD_SBNS 0x00002000 141 #define UARTBAUD_SBR 0x00000000 142 #define UARTBAUD_SBR_MASK 0x1fff 143 #define UARTBAUD_OSR_MASK 0x1f 144 #define UARTBAUD_OSR_SHIFT 24 145 146 #define UARTSTAT_LBKDIF 0x80000000 147 #define UARTSTAT_RXEDGIF 0x40000000 148 #define UARTSTAT_MSBF 0x20000000 149 #define UARTSTAT_RXINV 0x10000000 150 #define UARTSTAT_RWUID 0x08000000 151 #define UARTSTAT_BRK13 0x04000000 152 #define UARTSTAT_LBKDE 0x02000000 153 #define UARTSTAT_RAF 0x01000000 154 #define UARTSTAT_TDRE 0x00800000 155 #define UARTSTAT_TC 0x00400000 156 #define UARTSTAT_RDRF 0x00200000 157 #define UARTSTAT_IDLE 0x00100000 158 #define UARTSTAT_OR 0x00080000 159 #define UARTSTAT_NF 0x00040000 160 #define UARTSTAT_FE 0x00020000 161 #define UARTSTAT_PE 0x00010000 162 #define UARTSTAT_MA1F 0x00008000 163 #define UARTSTAT_M21F 0x00004000 164 165 #define UARTCTRL_R8T9 0x80000000 166 #define UARTCTRL_R9T8 0x40000000 167 #define UARTCTRL_TXDIR 0x20000000 168 #define UARTCTRL_TXINV 0x10000000 169 #define UARTCTRL_ORIE 0x08000000 170 #define UARTCTRL_NEIE 0x04000000 171 #define UARTCTRL_FEIE 0x02000000 172 #define UARTCTRL_PEIE 0x01000000 173 #define UARTCTRL_TIE 0x00800000 174 #define UARTCTRL_TCIE 0x00400000 175 #define UARTCTRL_RIE 0x00200000 176 #define UARTCTRL_ILIE 0x00100000 177 #define UARTCTRL_TE 0x00080000 178 #define UARTCTRL_RE 0x00040000 179 #define UARTCTRL_RWU 0x00020000 180 #define UARTCTRL_SBK 0x00010000 181 #define UARTCTRL_MA1IE 0x00008000 182 #define UARTCTRL_MA2IE 0x00004000 183 #define UARTCTRL_IDLECFG 0x00000100 184 #define UARTCTRL_LOOPS 0x00000080 185 #define UARTCTRL_DOZEEN 0x00000040 186 #define UARTCTRL_RSRC 0x00000020 187 #define UARTCTRL_M 0x00000010 188 #define UARTCTRL_WAKE 0x00000008 189 #define UARTCTRL_ILT 0x00000004 190 #define UARTCTRL_PE 0x00000002 191 #define UARTCTRL_PT 0x00000001 192 193 #define UARTDATA_NOISY 0x00008000 194 #define UARTDATA_PARITYE 0x00004000 195 #define UARTDATA_FRETSC 0x00002000 196 #define UARTDATA_RXEMPT 0x00001000 197 #define UARTDATA_IDLINE 0x00000800 198 #define UARTDATA_MASK 0x3ff 199 200 #define UARTMODIR_IREN 0x00020000 201 #define UARTMODIR_TXCTSSRC 0x00000020 202 #define UARTMODIR_TXCTSC 0x00000010 203 #define UARTMODIR_RXRTSE 0x00000008 204 #define UARTMODIR_TXRTSPOL 0x00000004 205 #define UARTMODIR_TXRTSE 0x00000002 206 #define UARTMODIR_TXCTSE 0x00000001 207 208 #define UARTFIFO_TXEMPT 0x00800000 209 #define UARTFIFO_RXEMPT 0x00400000 210 #define UARTFIFO_TXOF 0x00020000 211 #define UARTFIFO_RXUF 0x00010000 212 #define UARTFIFO_TXFLUSH 0x00008000 213 #define UARTFIFO_RXFLUSH 0x00004000 214 #define UARTFIFO_TXOFE 0x00000200 215 #define UARTFIFO_RXUFE 0x00000100 216 #define UARTFIFO_TXFE 0x00000080 217 #define UARTFIFO_FIFOSIZE_MASK 0x7 218 #define UARTFIFO_TXSIZE_OFF 4 219 #define UARTFIFO_RXFE 0x00000008 220 #define UARTFIFO_RXSIZE_OFF 0 221 222 #define UARTWATER_COUNT_MASK 0xff 223 #define UARTWATER_TXCNT_OFF 8 224 #define UARTWATER_RXCNT_OFF 24 225 #define UARTWATER_WATER_MASK 0xff 226 #define UARTWATER_TXWATER_OFF 0 227 #define UARTWATER_RXWATER_OFF 16 228 229 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 230 #define DMA_RX_TIMEOUT (10) 231 232 #define DRIVER_NAME "fsl-lpuart" 233 #define DEV_NAME "ttyLP" 234 #define UART_NR 6 235 236 /* IMX lpuart has four extra unused regs located at the beginning */ 237 #define IMX_REG_OFF 0x10 238 239 struct lpuart_port { 240 struct uart_port port; 241 struct clk *clk; 242 unsigned int txfifo_size; 243 unsigned int rxfifo_size; 244 245 bool lpuart_dma_tx_use; 246 bool lpuart_dma_rx_use; 247 struct dma_chan *dma_tx_chan; 248 struct dma_chan *dma_rx_chan; 249 struct dma_async_tx_descriptor *dma_tx_desc; 250 struct dma_async_tx_descriptor *dma_rx_desc; 251 dma_cookie_t dma_tx_cookie; 252 dma_cookie_t dma_rx_cookie; 253 unsigned int dma_tx_bytes; 254 unsigned int dma_rx_bytes; 255 bool dma_tx_in_progress; 256 unsigned int dma_rx_timeout; 257 struct timer_list lpuart_timer; 258 struct scatterlist rx_sgl, tx_sgl[2]; 259 struct circ_buf rx_ring; 260 int rx_dma_rng_buf_len; 261 unsigned int dma_tx_nents; 262 wait_queue_head_t dma_wait; 263 }; 264 265 struct lpuart_soc_data { 266 char iotype; 267 u8 reg_off; 268 }; 269 270 static const struct lpuart_soc_data vf_data = { 271 .iotype = UPIO_MEM, 272 }; 273 274 static const struct lpuart_soc_data ls_data = { 275 .iotype = UPIO_MEM32BE, 276 }; 277 278 static struct lpuart_soc_data imx_data = { 279 .iotype = UPIO_MEM32, 280 .reg_off = IMX_REG_OFF, 281 }; 282 283 static const struct of_device_id lpuart_dt_ids[] = { 284 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 285 { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, }, 286 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx_data, }, 287 { /* sentinel */ } 288 }; 289 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 290 291 /* Forward declare this for the dma callbacks*/ 292 static void lpuart_dma_tx_complete(void *arg); 293 294 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 295 { 296 switch (port->iotype) { 297 case UPIO_MEM32: 298 return readl(port->membase + off); 299 case UPIO_MEM32BE: 300 return ioread32be(port->membase + off); 301 default: 302 return 0; 303 } 304 } 305 306 static inline void lpuart32_write(struct uart_port *port, u32 val, 307 u32 off) 308 { 309 switch (port->iotype) { 310 case UPIO_MEM32: 311 writel(val, port->membase + off); 312 break; 313 case UPIO_MEM32BE: 314 iowrite32be(val, port->membase + off); 315 break; 316 } 317 } 318 319 static void lpuart_stop_tx(struct uart_port *port) 320 { 321 unsigned char temp; 322 323 temp = readb(port->membase + UARTCR2); 324 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 325 writeb(temp, port->membase + UARTCR2); 326 } 327 328 static void lpuart32_stop_tx(struct uart_port *port) 329 { 330 unsigned long temp; 331 332 temp = lpuart32_read(port, UARTCTRL); 333 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 334 lpuart32_write(port, temp, UARTCTRL); 335 } 336 337 static void lpuart_stop_rx(struct uart_port *port) 338 { 339 unsigned char temp; 340 341 temp = readb(port->membase + UARTCR2); 342 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 343 } 344 345 static void lpuart32_stop_rx(struct uart_port *port) 346 { 347 unsigned long temp; 348 349 temp = lpuart32_read(port, UARTCTRL); 350 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); 351 } 352 353 static void lpuart_dma_tx(struct lpuart_port *sport) 354 { 355 struct circ_buf *xmit = &sport->port.state->xmit; 356 struct scatterlist *sgl = sport->tx_sgl; 357 struct device *dev = sport->port.dev; 358 int ret; 359 360 if (sport->dma_tx_in_progress) 361 return; 362 363 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 364 365 if (xmit->tail < xmit->head || xmit->head == 0) { 366 sport->dma_tx_nents = 1; 367 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 368 } else { 369 sport->dma_tx_nents = 2; 370 sg_init_table(sgl, 2); 371 sg_set_buf(sgl, xmit->buf + xmit->tail, 372 UART_XMIT_SIZE - xmit->tail); 373 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 374 } 375 376 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 377 if (!ret) { 378 dev_err(dev, "DMA mapping error for TX.\n"); 379 return; 380 } 381 382 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl, 383 sport->dma_tx_nents, 384 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 385 if (!sport->dma_tx_desc) { 386 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 387 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 388 return; 389 } 390 391 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 392 sport->dma_tx_desc->callback_param = sport; 393 sport->dma_tx_in_progress = true; 394 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 395 dma_async_issue_pending(sport->dma_tx_chan); 396 } 397 398 static void lpuart_dma_tx_complete(void *arg) 399 { 400 struct lpuart_port *sport = arg; 401 struct scatterlist *sgl = &sport->tx_sgl[0]; 402 struct circ_buf *xmit = &sport->port.state->xmit; 403 unsigned long flags; 404 405 spin_lock_irqsave(&sport->port.lock, flags); 406 407 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 408 409 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 410 411 sport->port.icount.tx += sport->dma_tx_bytes; 412 sport->dma_tx_in_progress = false; 413 spin_unlock_irqrestore(&sport->port.lock, flags); 414 415 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 416 uart_write_wakeup(&sport->port); 417 418 if (waitqueue_active(&sport->dma_wait)) { 419 wake_up(&sport->dma_wait); 420 return; 421 } 422 423 spin_lock_irqsave(&sport->port.lock, flags); 424 425 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 426 lpuart_dma_tx(sport); 427 428 spin_unlock_irqrestore(&sport->port.lock, flags); 429 } 430 431 static int lpuart_dma_tx_request(struct uart_port *port) 432 { 433 struct lpuart_port *sport = container_of(port, 434 struct lpuart_port, port); 435 struct dma_slave_config dma_tx_sconfig = {}; 436 int ret; 437 438 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR; 439 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 440 dma_tx_sconfig.dst_maxburst = 1; 441 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 442 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 443 444 if (ret) { 445 dev_err(sport->port.dev, 446 "DMA slave config failed, err = %d\n", ret); 447 return ret; 448 } 449 450 return 0; 451 } 452 453 static void lpuart_flush_buffer(struct uart_port *port) 454 { 455 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 456 457 if (sport->lpuart_dma_tx_use) { 458 if (sport->dma_tx_in_progress) { 459 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 460 sport->dma_tx_nents, DMA_TO_DEVICE); 461 sport->dma_tx_in_progress = false; 462 } 463 dmaengine_terminate_all(sport->dma_tx_chan); 464 } 465 } 466 467 #if defined(CONFIG_CONSOLE_POLL) 468 469 static int lpuart_poll_init(struct uart_port *port) 470 { 471 struct lpuart_port *sport = container_of(port, 472 struct lpuart_port, port); 473 unsigned long flags; 474 unsigned char temp; 475 476 sport->port.fifosize = 0; 477 478 spin_lock_irqsave(&sport->port.lock, flags); 479 /* Disable Rx & Tx */ 480 writeb(0, sport->port.membase + UARTCR2); 481 482 temp = readb(sport->port.membase + UARTPFIFO); 483 /* Enable Rx and Tx FIFO */ 484 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 485 sport->port.membase + UARTPFIFO); 486 487 /* flush Tx and Rx FIFO */ 488 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 489 sport->port.membase + UARTCFIFO); 490 491 /* explicitly clear RDRF */ 492 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 493 readb(sport->port.membase + UARTDR); 494 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 495 } 496 497 writeb(0, sport->port.membase + UARTTWFIFO); 498 writeb(1, sport->port.membase + UARTRWFIFO); 499 500 /* Enable Rx and Tx */ 501 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 502 spin_unlock_irqrestore(&sport->port.lock, flags); 503 504 return 0; 505 } 506 507 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 508 { 509 /* drain */ 510 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) 511 barrier(); 512 513 writeb(c, port->membase + UARTDR); 514 } 515 516 static int lpuart_poll_get_char(struct uart_port *port) 517 { 518 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 519 return NO_POLL_CHAR; 520 521 return readb(port->membase + UARTDR); 522 } 523 524 #endif 525 526 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 527 { 528 struct circ_buf *xmit = &sport->port.state->xmit; 529 530 while (!uart_circ_empty(xmit) && 531 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 532 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 533 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 534 sport->port.icount.tx++; 535 } 536 537 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 538 uart_write_wakeup(&sport->port); 539 540 if (uart_circ_empty(xmit)) 541 lpuart_stop_tx(&sport->port); 542 } 543 544 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 545 { 546 struct circ_buf *xmit = &sport->port.state->xmit; 547 unsigned long txcnt; 548 549 txcnt = lpuart32_read(&sport->port, UARTWATER); 550 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 551 txcnt &= UARTWATER_COUNT_MASK; 552 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 553 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); 554 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 555 sport->port.icount.tx++; 556 txcnt = lpuart32_read(&sport->port, UARTWATER); 557 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 558 txcnt &= UARTWATER_COUNT_MASK; 559 } 560 561 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 562 uart_write_wakeup(&sport->port); 563 564 if (uart_circ_empty(xmit)) 565 lpuart32_stop_tx(&sport->port); 566 } 567 568 static void lpuart_start_tx(struct uart_port *port) 569 { 570 struct lpuart_port *sport = container_of(port, 571 struct lpuart_port, port); 572 struct circ_buf *xmit = &sport->port.state->xmit; 573 unsigned char temp; 574 575 temp = readb(port->membase + UARTCR2); 576 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 577 578 if (sport->lpuart_dma_tx_use) { 579 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) 580 lpuart_dma_tx(sport); 581 } else { 582 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 583 lpuart_transmit_buffer(sport); 584 } 585 } 586 587 static void lpuart32_start_tx(struct uart_port *port) 588 { 589 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 590 unsigned long temp; 591 592 temp = lpuart32_read(port, UARTCTRL); 593 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); 594 595 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 596 lpuart32_transmit_buffer(sport); 597 } 598 599 /* return TIOCSER_TEMT when transmitter is not busy */ 600 static unsigned int lpuart_tx_empty(struct uart_port *port) 601 { 602 struct lpuart_port *sport = container_of(port, 603 struct lpuart_port, port); 604 unsigned char sr1 = readb(port->membase + UARTSR1); 605 unsigned char sfifo = readb(port->membase + UARTSFIFO); 606 607 if (sport->dma_tx_in_progress) 608 return 0; 609 610 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 611 return TIOCSER_TEMT; 612 613 return 0; 614 } 615 616 static unsigned int lpuart32_tx_empty(struct uart_port *port) 617 { 618 return (lpuart32_read(port, UARTSTAT) & UARTSTAT_TC) ? 619 TIOCSER_TEMT : 0; 620 } 621 622 static irqreturn_t lpuart_txint(int irq, void *dev_id) 623 { 624 struct lpuart_port *sport = dev_id; 625 struct circ_buf *xmit = &sport->port.state->xmit; 626 unsigned long flags; 627 628 spin_lock_irqsave(&sport->port.lock, flags); 629 if (sport->port.x_char) { 630 if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE)) 631 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 632 else 633 writeb(sport->port.x_char, sport->port.membase + UARTDR); 634 goto out; 635 } 636 637 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 638 if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE)) 639 lpuart32_stop_tx(&sport->port); 640 else 641 lpuart_stop_tx(&sport->port); 642 goto out; 643 } 644 645 if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE)) 646 lpuart32_transmit_buffer(sport); 647 else 648 lpuart_transmit_buffer(sport); 649 650 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 651 uart_write_wakeup(&sport->port); 652 653 out: 654 spin_unlock_irqrestore(&sport->port.lock, flags); 655 return IRQ_HANDLED; 656 } 657 658 static irqreturn_t lpuart_rxint(int irq, void *dev_id) 659 { 660 struct lpuart_port *sport = dev_id; 661 unsigned int flg, ignored = 0; 662 struct tty_port *port = &sport->port.state->port; 663 unsigned long flags; 664 unsigned char rx, sr; 665 666 spin_lock_irqsave(&sport->port.lock, flags); 667 668 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 669 flg = TTY_NORMAL; 670 sport->port.icount.rx++; 671 /* 672 * to clear the FE, OR, NF, FE, PE flags, 673 * read SR1 then read DR 674 */ 675 sr = readb(sport->port.membase + UARTSR1); 676 rx = readb(sport->port.membase + UARTDR); 677 678 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 679 continue; 680 681 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 682 if (sr & UARTSR1_PE) 683 sport->port.icount.parity++; 684 else if (sr & UARTSR1_FE) 685 sport->port.icount.frame++; 686 687 if (sr & UARTSR1_OR) 688 sport->port.icount.overrun++; 689 690 if (sr & sport->port.ignore_status_mask) { 691 if (++ignored > 100) 692 goto out; 693 continue; 694 } 695 696 sr &= sport->port.read_status_mask; 697 698 if (sr & UARTSR1_PE) 699 flg = TTY_PARITY; 700 else if (sr & UARTSR1_FE) 701 flg = TTY_FRAME; 702 703 if (sr & UARTSR1_OR) 704 flg = TTY_OVERRUN; 705 706 #ifdef SUPPORT_SYSRQ 707 sport->port.sysrq = 0; 708 #endif 709 } 710 711 tty_insert_flip_char(port, rx, flg); 712 } 713 714 out: 715 spin_unlock_irqrestore(&sport->port.lock, flags); 716 717 tty_flip_buffer_push(port); 718 return IRQ_HANDLED; 719 } 720 721 static irqreturn_t lpuart32_rxint(int irq, void *dev_id) 722 { 723 struct lpuart_port *sport = dev_id; 724 unsigned int flg, ignored = 0; 725 struct tty_port *port = &sport->port.state->port; 726 unsigned long flags; 727 unsigned long rx, sr; 728 729 spin_lock_irqsave(&sport->port.lock, flags); 730 731 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 732 flg = TTY_NORMAL; 733 sport->port.icount.rx++; 734 /* 735 * to clear the FE, OR, NF, FE, PE flags, 736 * read STAT then read DATA reg 737 */ 738 sr = lpuart32_read(&sport->port, UARTSTAT); 739 rx = lpuart32_read(&sport->port, UARTDATA); 740 rx &= 0x3ff; 741 742 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 743 continue; 744 745 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 746 if (sr & UARTSTAT_PE) 747 sport->port.icount.parity++; 748 else if (sr & UARTSTAT_FE) 749 sport->port.icount.frame++; 750 751 if (sr & UARTSTAT_OR) 752 sport->port.icount.overrun++; 753 754 if (sr & sport->port.ignore_status_mask) { 755 if (++ignored > 100) 756 goto out; 757 continue; 758 } 759 760 sr &= sport->port.read_status_mask; 761 762 if (sr & UARTSTAT_PE) 763 flg = TTY_PARITY; 764 else if (sr & UARTSTAT_FE) 765 flg = TTY_FRAME; 766 767 if (sr & UARTSTAT_OR) 768 flg = TTY_OVERRUN; 769 770 #ifdef SUPPORT_SYSRQ 771 sport->port.sysrq = 0; 772 #endif 773 } 774 775 tty_insert_flip_char(port, rx, flg); 776 } 777 778 out: 779 spin_unlock_irqrestore(&sport->port.lock, flags); 780 781 tty_flip_buffer_push(port); 782 return IRQ_HANDLED; 783 } 784 785 static irqreturn_t lpuart_int(int irq, void *dev_id) 786 { 787 struct lpuart_port *sport = dev_id; 788 unsigned char sts; 789 790 sts = readb(sport->port.membase + UARTSR1); 791 792 if (sts & UARTSR1_RDRF) 793 lpuart_rxint(irq, dev_id); 794 795 if (sts & UARTSR1_TDRE) 796 lpuart_txint(irq, dev_id); 797 798 return IRQ_HANDLED; 799 } 800 801 static irqreturn_t lpuart32_int(int irq, void *dev_id) 802 { 803 struct lpuart_port *sport = dev_id; 804 unsigned long sts, rxcount; 805 806 sts = lpuart32_read(&sport->port, UARTSTAT); 807 rxcount = lpuart32_read(&sport->port, UARTWATER); 808 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 809 810 if (sts & UARTSTAT_RDRF || rxcount > 0) 811 lpuart32_rxint(irq, dev_id); 812 813 if ((sts & UARTSTAT_TDRE) && 814 !(lpuart32_read(&sport->port, UARTBAUD) & UARTBAUD_TDMAE)) 815 lpuart_txint(irq, dev_id); 816 817 lpuart32_write(&sport->port, sts, UARTSTAT); 818 return IRQ_HANDLED; 819 } 820 821 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 822 { 823 struct tty_port *port = &sport->port.state->port; 824 struct dma_tx_state state; 825 enum dma_status dmastat; 826 struct circ_buf *ring = &sport->rx_ring; 827 unsigned long flags; 828 int count = 0; 829 unsigned char sr; 830 831 sr = readb(sport->port.membase + UARTSR1); 832 833 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 834 /* Read DR to clear the error flags */ 835 readb(sport->port.membase + UARTDR); 836 837 if (sr & UARTSR1_PE) 838 sport->port.icount.parity++; 839 else if (sr & UARTSR1_FE) 840 sport->port.icount.frame++; 841 } 842 843 async_tx_ack(sport->dma_rx_desc); 844 845 spin_lock_irqsave(&sport->port.lock, flags); 846 847 dmastat = dmaengine_tx_status(sport->dma_rx_chan, 848 sport->dma_rx_cookie, 849 &state); 850 851 if (dmastat == DMA_ERROR) { 852 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 853 spin_unlock_irqrestore(&sport->port.lock, flags); 854 return; 855 } 856 857 /* CPU claims ownership of RX DMA buffer */ 858 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 859 860 /* 861 * ring->head points to the end of data already written by the DMA. 862 * ring->tail points to the beginning of data to be read by the 863 * framework. 864 * The current transfer size should not be larger than the dma buffer 865 * length. 866 */ 867 ring->head = sport->rx_sgl.length - state.residue; 868 BUG_ON(ring->head > sport->rx_sgl.length); 869 /* 870 * At this point ring->head may point to the first byte right after the 871 * last byte of the dma buffer: 872 * 0 <= ring->head <= sport->rx_sgl.length 873 * 874 * However ring->tail must always points inside the dma buffer: 875 * 0 <= ring->tail <= sport->rx_sgl.length - 1 876 * 877 * Since we use a ring buffer, we have to handle the case 878 * where head is lower than tail. In such a case, we first read from 879 * tail to the end of the buffer then reset tail. 880 */ 881 if (ring->head < ring->tail) { 882 count = sport->rx_sgl.length - ring->tail; 883 884 tty_insert_flip_string(port, ring->buf + ring->tail, count); 885 ring->tail = 0; 886 sport->port.icount.rx += count; 887 } 888 889 /* Finally we read data from tail to head */ 890 if (ring->tail < ring->head) { 891 count = ring->head - ring->tail; 892 tty_insert_flip_string(port, ring->buf + ring->tail, count); 893 /* Wrap ring->head if needed */ 894 if (ring->head >= sport->rx_sgl.length) 895 ring->head = 0; 896 ring->tail = ring->head; 897 sport->port.icount.rx += count; 898 } 899 900 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1, 901 DMA_FROM_DEVICE); 902 903 spin_unlock_irqrestore(&sport->port.lock, flags); 904 905 tty_flip_buffer_push(port); 906 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 907 } 908 909 static void lpuart_dma_rx_complete(void *arg) 910 { 911 struct lpuart_port *sport = arg; 912 913 lpuart_copy_rx_to_tty(sport); 914 } 915 916 static void lpuart_timer_func(unsigned long data) 917 { 918 struct lpuart_port *sport = (struct lpuart_port *)data; 919 920 lpuart_copy_rx_to_tty(sport); 921 } 922 923 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 924 { 925 struct dma_slave_config dma_rx_sconfig = {}; 926 struct circ_buf *ring = &sport->rx_ring; 927 int ret, nent; 928 int bits, baud; 929 struct tty_struct *tty = tty_port_tty_get(&sport->port.state->port); 930 struct ktermios *termios = &tty->termios; 931 932 baud = tty_get_baud_rate(tty); 933 934 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; 935 if (termios->c_cflag & PARENB) 936 bits++; 937 938 /* 939 * Calculate length of one DMA buffer size to keep latency below 940 * 10ms at any baud rate. 941 */ 942 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 943 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 944 if (sport->rx_dma_rng_buf_len < 16) 945 sport->rx_dma_rng_buf_len = 16; 946 947 ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 948 if (!ring->buf) { 949 dev_err(sport->port.dev, "Ring buf alloc failed\n"); 950 return -ENOMEM; 951 } 952 953 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 954 sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 955 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 956 957 if (!nent) { 958 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 959 return -EINVAL; 960 } 961 962 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR; 963 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 964 dma_rx_sconfig.src_maxburst = 1; 965 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 966 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig); 967 968 if (ret < 0) { 969 dev_err(sport->port.dev, 970 "DMA Rx slave config failed, err = %d\n", ret); 971 return ret; 972 } 973 974 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan, 975 sg_dma_address(&sport->rx_sgl), 976 sport->rx_sgl.length, 977 sport->rx_sgl.length / 2, 978 DMA_DEV_TO_MEM, 979 DMA_PREP_INTERRUPT); 980 if (!sport->dma_rx_desc) { 981 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 982 return -EFAULT; 983 } 984 985 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 986 sport->dma_rx_desc->callback_param = sport; 987 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 988 dma_async_issue_pending(sport->dma_rx_chan); 989 990 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 991 sport->port.membase + UARTCR5); 992 993 return 0; 994 } 995 996 static void lpuart_dma_rx_free(struct uart_port *port) 997 { 998 struct lpuart_port *sport = container_of(port, 999 struct lpuart_port, port); 1000 1001 if (sport->dma_rx_chan) 1002 dmaengine_terminate_all(sport->dma_rx_chan); 1003 1004 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1005 kfree(sport->rx_ring.buf); 1006 sport->rx_ring.tail = 0; 1007 sport->rx_ring.head = 0; 1008 sport->dma_rx_desc = NULL; 1009 sport->dma_rx_cookie = -EINVAL; 1010 } 1011 1012 static int lpuart_config_rs485(struct uart_port *port, 1013 struct serial_rs485 *rs485) 1014 { 1015 struct lpuart_port *sport = container_of(port, 1016 struct lpuart_port, port); 1017 1018 u8 modem = readb(sport->port.membase + UARTMODEM) & 1019 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1020 writeb(modem, sport->port.membase + UARTMODEM); 1021 1022 if (rs485->flags & SER_RS485_ENABLED) { 1023 /* Enable auto RS-485 RTS mode */ 1024 modem |= UARTMODEM_TXRTSE; 1025 1026 /* 1027 * RTS needs to be logic HIGH either during transer _or_ after 1028 * transfer, other variants are not supported by the hardware. 1029 */ 1030 1031 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1032 SER_RS485_RTS_AFTER_SEND))) 1033 rs485->flags |= SER_RS485_RTS_ON_SEND; 1034 1035 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1036 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1037 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1038 1039 /* 1040 * The hardware defaults to RTS logic HIGH while transfer. 1041 * Switch polarity in case RTS shall be logic HIGH 1042 * after transfer. 1043 * Note: UART is assumed to be active high. 1044 */ 1045 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1046 modem &= ~UARTMODEM_TXRTSPOL; 1047 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1048 modem |= UARTMODEM_TXRTSPOL; 1049 } 1050 1051 /* Store the new configuration */ 1052 sport->port.rs485 = *rs485; 1053 1054 writeb(modem, sport->port.membase + UARTMODEM); 1055 return 0; 1056 } 1057 1058 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1059 { 1060 unsigned int temp = 0; 1061 unsigned char reg; 1062 1063 reg = readb(port->membase + UARTMODEM); 1064 if (reg & UARTMODEM_TXCTSE) 1065 temp |= TIOCM_CTS; 1066 1067 if (reg & UARTMODEM_RXRTSE) 1068 temp |= TIOCM_RTS; 1069 1070 return temp; 1071 } 1072 1073 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1074 { 1075 unsigned int temp = 0; 1076 unsigned long reg; 1077 1078 reg = lpuart32_read(port, UARTMODIR); 1079 if (reg & UARTMODIR_TXCTSE) 1080 temp |= TIOCM_CTS; 1081 1082 if (reg & UARTMODIR_RXRTSE) 1083 temp |= TIOCM_RTS; 1084 1085 return temp; 1086 } 1087 1088 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1089 { 1090 unsigned char temp; 1091 struct lpuart_port *sport = container_of(port, 1092 struct lpuart_port, port); 1093 1094 /* Make sure RXRTSE bit is not set when RS485 is enabled */ 1095 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { 1096 temp = readb(sport->port.membase + UARTMODEM) & 1097 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1098 1099 if (mctrl & TIOCM_RTS) 1100 temp |= UARTMODEM_RXRTSE; 1101 1102 if (mctrl & TIOCM_CTS) 1103 temp |= UARTMODEM_TXCTSE; 1104 1105 writeb(temp, port->membase + UARTMODEM); 1106 } 1107 } 1108 1109 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1110 { 1111 unsigned long temp; 1112 1113 temp = lpuart32_read(port, UARTMODIR) & 1114 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 1115 1116 if (mctrl & TIOCM_RTS) 1117 temp |= UARTMODIR_RXRTSE; 1118 1119 if (mctrl & TIOCM_CTS) 1120 temp |= UARTMODIR_TXCTSE; 1121 1122 lpuart32_write(port, temp, UARTMODIR); 1123 } 1124 1125 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1126 { 1127 unsigned char temp; 1128 1129 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1130 1131 if (break_state != 0) 1132 temp |= UARTCR2_SBK; 1133 1134 writeb(temp, port->membase + UARTCR2); 1135 } 1136 1137 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1138 { 1139 unsigned long temp; 1140 1141 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; 1142 1143 if (break_state != 0) 1144 temp |= UARTCTRL_SBK; 1145 1146 lpuart32_write(port, temp, UARTCTRL); 1147 } 1148 1149 static void lpuart_setup_watermark(struct lpuart_port *sport) 1150 { 1151 unsigned char val, cr2; 1152 unsigned char cr2_saved; 1153 1154 cr2 = readb(sport->port.membase + UARTCR2); 1155 cr2_saved = cr2; 1156 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1157 UARTCR2_RIE | UARTCR2_RE); 1158 writeb(cr2, sport->port.membase + UARTCR2); 1159 1160 val = readb(sport->port.membase + UARTPFIFO); 1161 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1162 sport->port.membase + UARTPFIFO); 1163 1164 /* flush Tx and Rx FIFO */ 1165 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1166 sport->port.membase + UARTCFIFO); 1167 1168 /* explicitly clear RDRF */ 1169 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1170 readb(sport->port.membase + UARTDR); 1171 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1172 } 1173 1174 writeb(0, sport->port.membase + UARTTWFIFO); 1175 writeb(1, sport->port.membase + UARTRWFIFO); 1176 1177 /* Restore cr2 */ 1178 writeb(cr2_saved, sport->port.membase + UARTCR2); 1179 } 1180 1181 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1182 { 1183 unsigned long val, ctrl; 1184 unsigned long ctrl_saved; 1185 1186 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1187 ctrl_saved = ctrl; 1188 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1189 UARTCTRL_RIE | UARTCTRL_RE); 1190 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1191 1192 /* enable FIFO mode */ 1193 val = lpuart32_read(&sport->port, UARTFIFO); 1194 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1195 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1196 lpuart32_write(&sport->port, val, UARTFIFO); 1197 1198 /* set the watermark */ 1199 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1200 lpuart32_write(&sport->port, val, UARTWATER); 1201 1202 /* Restore cr2 */ 1203 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1204 } 1205 1206 static void rx_dma_timer_init(struct lpuart_port *sport) 1207 { 1208 setup_timer(&sport->lpuart_timer, lpuart_timer_func, 1209 (unsigned long)sport); 1210 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1211 add_timer(&sport->lpuart_timer); 1212 } 1213 1214 static int lpuart_startup(struct uart_port *port) 1215 { 1216 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1217 int ret; 1218 unsigned long flags; 1219 unsigned char temp; 1220 1221 /* determine FIFO size and enable FIFO mode */ 1222 temp = readb(sport->port.membase + UARTPFIFO); 1223 1224 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) & 1225 UARTPFIFO_FIFOSIZE_MASK) + 1); 1226 1227 sport->port.fifosize = sport->txfifo_size; 1228 1229 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) & 1230 UARTPFIFO_FIFOSIZE_MASK) + 1); 1231 1232 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0, 1233 DRIVER_NAME, sport); 1234 if (ret) 1235 return ret; 1236 1237 spin_lock_irqsave(&sport->port.lock, flags); 1238 1239 lpuart_setup_watermark(sport); 1240 1241 temp = readb(sport->port.membase + UARTCR2); 1242 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 1243 writeb(temp, sport->port.membase + UARTCR2); 1244 1245 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) { 1246 /* set Rx DMA timeout */ 1247 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1248 if (!sport->dma_rx_timeout) 1249 sport->dma_rx_timeout = 1; 1250 1251 sport->lpuart_dma_rx_use = true; 1252 rx_dma_timer_init(sport); 1253 } else { 1254 sport->lpuart_dma_rx_use = false; 1255 } 1256 1257 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) { 1258 init_waitqueue_head(&sport->dma_wait); 1259 sport->lpuart_dma_tx_use = true; 1260 temp = readb(port->membase + UARTCR5); 1261 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5); 1262 } else { 1263 sport->lpuart_dma_tx_use = false; 1264 } 1265 1266 spin_unlock_irqrestore(&sport->port.lock, flags); 1267 1268 return 0; 1269 } 1270 1271 static int lpuart32_startup(struct uart_port *port) 1272 { 1273 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1274 int ret; 1275 unsigned long flags; 1276 unsigned long temp; 1277 1278 /* determine FIFO size */ 1279 temp = lpuart32_read(&sport->port, UARTFIFO); 1280 1281 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) & 1282 UARTFIFO_FIFOSIZE_MASK) - 1); 1283 1284 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) & 1285 UARTFIFO_FIFOSIZE_MASK) - 1); 1286 1287 ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0, 1288 DRIVER_NAME, sport); 1289 if (ret) 1290 return ret; 1291 1292 spin_lock_irqsave(&sport->port.lock, flags); 1293 1294 lpuart32_setup_watermark(sport); 1295 1296 temp = lpuart32_read(&sport->port, UARTCTRL); 1297 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE); 1298 temp |= UARTCTRL_ILIE; 1299 lpuart32_write(&sport->port, temp, UARTCTRL); 1300 1301 spin_unlock_irqrestore(&sport->port.lock, flags); 1302 return 0; 1303 } 1304 1305 static void lpuart_shutdown(struct uart_port *port) 1306 { 1307 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1308 unsigned char temp; 1309 unsigned long flags; 1310 1311 spin_lock_irqsave(&port->lock, flags); 1312 1313 /* disable Rx/Tx and interrupts */ 1314 temp = readb(port->membase + UARTCR2); 1315 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1316 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1317 writeb(temp, port->membase + UARTCR2); 1318 1319 spin_unlock_irqrestore(&port->lock, flags); 1320 1321 devm_free_irq(port->dev, port->irq, sport); 1322 1323 if (sport->lpuart_dma_rx_use) { 1324 del_timer_sync(&sport->lpuart_timer); 1325 lpuart_dma_rx_free(&sport->port); 1326 } 1327 1328 if (sport->lpuart_dma_tx_use) { 1329 if (wait_event_interruptible(sport->dma_wait, 1330 !sport->dma_tx_in_progress) != false) { 1331 sport->dma_tx_in_progress = false; 1332 dmaengine_terminate_all(sport->dma_tx_chan); 1333 } 1334 1335 lpuart_stop_tx(port); 1336 } 1337 } 1338 1339 static void lpuart32_shutdown(struct uart_port *port) 1340 { 1341 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1342 unsigned long temp; 1343 unsigned long flags; 1344 1345 spin_lock_irqsave(&port->lock, flags); 1346 1347 /* disable Rx/Tx and interrupts */ 1348 temp = lpuart32_read(port, UARTCTRL); 1349 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1350 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1351 lpuart32_write(port, temp, UARTCTRL); 1352 1353 spin_unlock_irqrestore(&port->lock, flags); 1354 1355 devm_free_irq(port->dev, port->irq, sport); 1356 } 1357 1358 static void 1359 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1360 struct ktermios *old) 1361 { 1362 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1363 unsigned long flags; 1364 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1365 unsigned int baud; 1366 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1367 unsigned int sbr, brfa; 1368 1369 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1370 old_cr2 = readb(sport->port.membase + UARTCR2); 1371 cr3 = readb(sport->port.membase + UARTCR3); 1372 cr4 = readb(sport->port.membase + UARTCR4); 1373 bdh = readb(sport->port.membase + UARTBDH); 1374 modem = readb(sport->port.membase + UARTMODEM); 1375 /* 1376 * only support CS8 and CS7, and for CS7 must enable PE. 1377 * supported mode: 1378 * - (7,e/o,1) 1379 * - (8,n,1) 1380 * - (8,m/s,1) 1381 * - (8,e/o,1) 1382 */ 1383 while ((termios->c_cflag & CSIZE) != CS8 && 1384 (termios->c_cflag & CSIZE) != CS7) { 1385 termios->c_cflag &= ~CSIZE; 1386 termios->c_cflag |= old_csize; 1387 old_csize = CS8; 1388 } 1389 1390 if ((termios->c_cflag & CSIZE) == CS8 || 1391 (termios->c_cflag & CSIZE) == CS7) 1392 cr1 = old_cr1 & ~UARTCR1_M; 1393 1394 if (termios->c_cflag & CMSPAR) { 1395 if ((termios->c_cflag & CSIZE) != CS8) { 1396 termios->c_cflag &= ~CSIZE; 1397 termios->c_cflag |= CS8; 1398 } 1399 cr1 |= UARTCR1_M; 1400 } 1401 1402 /* 1403 * When auto RS-485 RTS mode is enabled, 1404 * hardware flow control need to be disabled. 1405 */ 1406 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1407 termios->c_cflag &= ~CRTSCTS; 1408 1409 if (termios->c_cflag & CRTSCTS) { 1410 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1411 } else { 1412 termios->c_cflag &= ~CRTSCTS; 1413 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1414 } 1415 1416 if (termios->c_cflag & CSTOPB) 1417 termios->c_cflag &= ~CSTOPB; 1418 1419 /* parity must be enabled when CS7 to match 8-bits format */ 1420 if ((termios->c_cflag & CSIZE) == CS7) 1421 termios->c_cflag |= PARENB; 1422 1423 if ((termios->c_cflag & PARENB)) { 1424 if (termios->c_cflag & CMSPAR) { 1425 cr1 &= ~UARTCR1_PE; 1426 if (termios->c_cflag & PARODD) 1427 cr3 |= UARTCR3_T8; 1428 else 1429 cr3 &= ~UARTCR3_T8; 1430 } else { 1431 cr1 |= UARTCR1_PE; 1432 if ((termios->c_cflag & CSIZE) == CS8) 1433 cr1 |= UARTCR1_M; 1434 if (termios->c_cflag & PARODD) 1435 cr1 |= UARTCR1_PT; 1436 else 1437 cr1 &= ~UARTCR1_PT; 1438 } 1439 } 1440 1441 /* ask the core to calculate the divisor */ 1442 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1443 1444 /* 1445 * Need to update the Ring buffer length according to the selected 1446 * baud rate and restart Rx DMA path. 1447 * 1448 * Since timer function acqures sport->port.lock, need to stop before 1449 * acquring same lock because otherwise del_timer_sync() can deadlock. 1450 */ 1451 if (old && sport->lpuart_dma_rx_use) { 1452 del_timer_sync(&sport->lpuart_timer); 1453 lpuart_dma_rx_free(&sport->port); 1454 } 1455 1456 spin_lock_irqsave(&sport->port.lock, flags); 1457 1458 sport->port.read_status_mask = 0; 1459 if (termios->c_iflag & INPCK) 1460 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE); 1461 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1462 sport->port.read_status_mask |= UARTSR1_FE; 1463 1464 /* characters to ignore */ 1465 sport->port.ignore_status_mask = 0; 1466 if (termios->c_iflag & IGNPAR) 1467 sport->port.ignore_status_mask |= UARTSR1_PE; 1468 if (termios->c_iflag & IGNBRK) { 1469 sport->port.ignore_status_mask |= UARTSR1_FE; 1470 /* 1471 * if we're ignoring parity and break indicators, 1472 * ignore overruns too (for real raw support). 1473 */ 1474 if (termios->c_iflag & IGNPAR) 1475 sport->port.ignore_status_mask |= UARTSR1_OR; 1476 } 1477 1478 /* update the per-port timeout */ 1479 uart_update_timeout(port, termios->c_cflag, baud); 1480 1481 /* wait transmit engin complete */ 1482 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1483 barrier(); 1484 1485 /* disable transmit and receive */ 1486 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1487 sport->port.membase + UARTCR2); 1488 1489 sbr = sport->port.uartclk / (16 * baud); 1490 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1491 bdh &= ~UARTBDH_SBR_MASK; 1492 bdh |= (sbr >> 8) & 0x1F; 1493 cr4 &= ~UARTCR4_BRFA_MASK; 1494 brfa &= UARTCR4_BRFA_MASK; 1495 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1496 writeb(bdh, sport->port.membase + UARTBDH); 1497 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1498 writeb(cr3, sport->port.membase + UARTCR3); 1499 writeb(cr1, sport->port.membase + UARTCR1); 1500 writeb(modem, sport->port.membase + UARTMODEM); 1501 1502 /* restore control register */ 1503 writeb(old_cr2, sport->port.membase + UARTCR2); 1504 1505 if (old && sport->lpuart_dma_rx_use) { 1506 if (!lpuart_start_rx_dma(sport)) 1507 rx_dma_timer_init(sport); 1508 else 1509 sport->lpuart_dma_rx_use = false; 1510 } 1511 1512 spin_unlock_irqrestore(&sport->port.lock, flags); 1513 } 1514 1515 static void 1516 lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate) 1517 { 1518 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; 1519 u32 clk = sport->port.uartclk; 1520 1521 /* 1522 * The idea is to use the best OSR (over-sampling rate) possible. 1523 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 1524 * Loop to find the best OSR value possible, one that generates minimum 1525 * baud_diff iterate through the rest of the supported values of OSR. 1526 * 1527 * Calculation Formula: 1528 * Baud Rate = baud clock / ((OSR+1) × SBR) 1529 */ 1530 baud_diff = baudrate; 1531 osr = 0; 1532 sbr = 0; 1533 1534 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 1535 /* calculate the temporary sbr value */ 1536 tmp_sbr = (clk / (baudrate * tmp_osr)); 1537 if (tmp_sbr == 0) 1538 tmp_sbr = 1; 1539 1540 /* 1541 * calculate the baud rate difference based on the temporary 1542 * osr and sbr values 1543 */ 1544 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 1545 1546 /* select best values between sbr and sbr+1 */ 1547 tmp = clk / (tmp_osr * (tmp_sbr + 1)); 1548 if (tmp_diff > (baudrate - tmp)) { 1549 tmp_diff = baudrate - tmp; 1550 tmp_sbr++; 1551 } 1552 1553 if (tmp_diff <= baud_diff) { 1554 baud_diff = tmp_diff; 1555 osr = tmp_osr; 1556 sbr = tmp_sbr; 1557 1558 if (!baud_diff) 1559 break; 1560 } 1561 } 1562 1563 /* handle buadrate outside acceptable rate */ 1564 if (baud_diff > ((baudrate / 100) * 3)) 1565 dev_warn(sport->port.dev, 1566 "unacceptable baud rate difference of more than 3%%\n"); 1567 1568 tmp = lpuart32_read(&sport->port, UARTBAUD); 1569 1570 if ((osr > 3) && (osr < 8)) 1571 tmp |= UARTBAUD_BOTHEDGE; 1572 1573 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 1574 tmp |= (((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT); 1575 1576 tmp &= ~UARTBAUD_SBR_MASK; 1577 tmp |= sbr & UARTBAUD_SBR_MASK; 1578 1579 tmp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); 1580 1581 lpuart32_write(&sport->port, tmp, UARTBAUD); 1582 } 1583 1584 static void 1585 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 1586 struct ktermios *old) 1587 { 1588 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1589 unsigned long flags; 1590 unsigned long ctrl, old_ctrl, bd, modem; 1591 unsigned int baud; 1592 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1593 1594 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); 1595 bd = lpuart32_read(&sport->port, UARTBAUD); 1596 modem = lpuart32_read(&sport->port, UARTMODIR); 1597 /* 1598 * only support CS8 and CS7, and for CS7 must enable PE. 1599 * supported mode: 1600 * - (7,e/o,1) 1601 * - (8,n,1) 1602 * - (8,m/s,1) 1603 * - (8,e/o,1) 1604 */ 1605 while ((termios->c_cflag & CSIZE) != CS8 && 1606 (termios->c_cflag & CSIZE) != CS7) { 1607 termios->c_cflag &= ~CSIZE; 1608 termios->c_cflag |= old_csize; 1609 old_csize = CS8; 1610 } 1611 1612 if ((termios->c_cflag & CSIZE) == CS8 || 1613 (termios->c_cflag & CSIZE) == CS7) 1614 ctrl = old_ctrl & ~UARTCTRL_M; 1615 1616 if (termios->c_cflag & CMSPAR) { 1617 if ((termios->c_cflag & CSIZE) != CS8) { 1618 termios->c_cflag &= ~CSIZE; 1619 termios->c_cflag |= CS8; 1620 } 1621 ctrl |= UARTCTRL_M; 1622 } 1623 1624 if (termios->c_cflag & CRTSCTS) { 1625 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1626 } else { 1627 termios->c_cflag &= ~CRTSCTS; 1628 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1629 } 1630 1631 if (termios->c_cflag & CSTOPB) 1632 termios->c_cflag &= ~CSTOPB; 1633 1634 /* parity must be enabled when CS7 to match 8-bits format */ 1635 if ((termios->c_cflag & CSIZE) == CS7) 1636 termios->c_cflag |= PARENB; 1637 1638 if ((termios->c_cflag & PARENB)) { 1639 if (termios->c_cflag & CMSPAR) { 1640 ctrl &= ~UARTCTRL_PE; 1641 ctrl |= UARTCTRL_M; 1642 } else { 1643 ctrl |= UARTCR1_PE; 1644 if ((termios->c_cflag & CSIZE) == CS8) 1645 ctrl |= UARTCTRL_M; 1646 if (termios->c_cflag & PARODD) 1647 ctrl |= UARTCTRL_PT; 1648 else 1649 ctrl &= ~UARTCTRL_PT; 1650 } 1651 } 1652 1653 /* ask the core to calculate the divisor */ 1654 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1655 1656 spin_lock_irqsave(&sport->port.lock, flags); 1657 1658 sport->port.read_status_mask = 0; 1659 if (termios->c_iflag & INPCK) 1660 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE); 1661 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1662 sport->port.read_status_mask |= UARTSTAT_FE; 1663 1664 /* characters to ignore */ 1665 sport->port.ignore_status_mask = 0; 1666 if (termios->c_iflag & IGNPAR) 1667 sport->port.ignore_status_mask |= UARTSTAT_PE; 1668 if (termios->c_iflag & IGNBRK) { 1669 sport->port.ignore_status_mask |= UARTSTAT_FE; 1670 /* 1671 * if we're ignoring parity and break indicators, 1672 * ignore overruns too (for real raw support). 1673 */ 1674 if (termios->c_iflag & IGNPAR) 1675 sport->port.ignore_status_mask |= UARTSTAT_OR; 1676 } 1677 1678 /* update the per-port timeout */ 1679 uart_update_timeout(port, termios->c_cflag, baud); 1680 1681 /* wait transmit engin complete */ 1682 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC)) 1683 barrier(); 1684 1685 /* disable transmit and receive */ 1686 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 1687 UARTCTRL); 1688 1689 lpuart32_serial_setbrg(sport, baud); 1690 lpuart32_write(&sport->port, modem, UARTMODIR); 1691 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1692 /* restore control register */ 1693 1694 spin_unlock_irqrestore(&sport->port.lock, flags); 1695 } 1696 1697 static const char *lpuart_type(struct uart_port *port) 1698 { 1699 return "FSL_LPUART"; 1700 } 1701 1702 static void lpuart_release_port(struct uart_port *port) 1703 { 1704 /* nothing to do */ 1705 } 1706 1707 static int lpuart_request_port(struct uart_port *port) 1708 { 1709 return 0; 1710 } 1711 1712 /* configure/autoconfigure the port */ 1713 static void lpuart_config_port(struct uart_port *port, int flags) 1714 { 1715 if (flags & UART_CONFIG_TYPE) 1716 port->type = PORT_LPUART; 1717 } 1718 1719 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 1720 { 1721 int ret = 0; 1722 1723 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 1724 ret = -EINVAL; 1725 if (port->irq != ser->irq) 1726 ret = -EINVAL; 1727 if (ser->io_type != UPIO_MEM) 1728 ret = -EINVAL; 1729 if (port->uartclk / 16 != ser->baud_base) 1730 ret = -EINVAL; 1731 if (port->iobase != ser->port) 1732 ret = -EINVAL; 1733 if (ser->hub6 != 0) 1734 ret = -EINVAL; 1735 return ret; 1736 } 1737 1738 static const struct uart_ops lpuart_pops = { 1739 .tx_empty = lpuart_tx_empty, 1740 .set_mctrl = lpuart_set_mctrl, 1741 .get_mctrl = lpuart_get_mctrl, 1742 .stop_tx = lpuart_stop_tx, 1743 .start_tx = lpuart_start_tx, 1744 .stop_rx = lpuart_stop_rx, 1745 .break_ctl = lpuart_break_ctl, 1746 .startup = lpuart_startup, 1747 .shutdown = lpuart_shutdown, 1748 .set_termios = lpuart_set_termios, 1749 .type = lpuart_type, 1750 .request_port = lpuart_request_port, 1751 .release_port = lpuart_release_port, 1752 .config_port = lpuart_config_port, 1753 .verify_port = lpuart_verify_port, 1754 .flush_buffer = lpuart_flush_buffer, 1755 #if defined(CONFIG_CONSOLE_POLL) 1756 .poll_init = lpuart_poll_init, 1757 .poll_get_char = lpuart_poll_get_char, 1758 .poll_put_char = lpuart_poll_put_char, 1759 #endif 1760 }; 1761 1762 static const struct uart_ops lpuart32_pops = { 1763 .tx_empty = lpuart32_tx_empty, 1764 .set_mctrl = lpuart32_set_mctrl, 1765 .get_mctrl = lpuart32_get_mctrl, 1766 .stop_tx = lpuart32_stop_tx, 1767 .start_tx = lpuart32_start_tx, 1768 .stop_rx = lpuart32_stop_rx, 1769 .break_ctl = lpuart32_break_ctl, 1770 .startup = lpuart32_startup, 1771 .shutdown = lpuart32_shutdown, 1772 .set_termios = lpuart32_set_termios, 1773 .type = lpuart_type, 1774 .request_port = lpuart_request_port, 1775 .release_port = lpuart_release_port, 1776 .config_port = lpuart_config_port, 1777 .verify_port = lpuart_verify_port, 1778 .flush_buffer = lpuart_flush_buffer, 1779 }; 1780 1781 static struct lpuart_port *lpuart_ports[UART_NR]; 1782 1783 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 1784 static void lpuart_console_putchar(struct uart_port *port, int ch) 1785 { 1786 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) 1787 barrier(); 1788 1789 writeb(ch, port->membase + UARTDR); 1790 } 1791 1792 static void lpuart32_console_putchar(struct uart_port *port, int ch) 1793 { 1794 while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)) 1795 barrier(); 1796 1797 lpuart32_write(port, ch, UARTDATA); 1798 } 1799 1800 static void 1801 lpuart_console_write(struct console *co, const char *s, unsigned int count) 1802 { 1803 struct lpuart_port *sport = lpuart_ports[co->index]; 1804 unsigned char old_cr2, cr2; 1805 unsigned long flags; 1806 int locked = 1; 1807 1808 if (sport->port.sysrq || oops_in_progress) 1809 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1810 else 1811 spin_lock_irqsave(&sport->port.lock, flags); 1812 1813 /* first save CR2 and then disable interrupts */ 1814 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 1815 cr2 |= (UARTCR2_TE | UARTCR2_RE); 1816 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1817 writeb(cr2, sport->port.membase + UARTCR2); 1818 1819 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 1820 1821 /* wait for transmitter finish complete and restore CR2 */ 1822 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1823 barrier(); 1824 1825 writeb(old_cr2, sport->port.membase + UARTCR2); 1826 1827 if (locked) 1828 spin_unlock_irqrestore(&sport->port.lock, flags); 1829 } 1830 1831 static void 1832 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 1833 { 1834 struct lpuart_port *sport = lpuart_ports[co->index]; 1835 unsigned long old_cr, cr; 1836 unsigned long flags; 1837 int locked = 1; 1838 1839 if (sport->port.sysrq || oops_in_progress) 1840 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1841 else 1842 spin_lock_irqsave(&sport->port.lock, flags); 1843 1844 /* first save CR2 and then disable interrupts */ 1845 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 1846 cr |= (UARTCTRL_TE | UARTCTRL_RE); 1847 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1848 lpuart32_write(&sport->port, cr, UARTCTRL); 1849 1850 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 1851 1852 /* wait for transmitter finish complete and restore CR2 */ 1853 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC)) 1854 barrier(); 1855 1856 lpuart32_write(&sport->port, old_cr, UARTCTRL); 1857 1858 if (locked) 1859 spin_unlock_irqrestore(&sport->port.lock, flags); 1860 } 1861 1862 /* 1863 * if the port was already initialised (eg, by a boot loader), 1864 * try to determine the current setup. 1865 */ 1866 static void __init 1867 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 1868 int *parity, int *bits) 1869 { 1870 unsigned char cr, bdh, bdl, brfa; 1871 unsigned int sbr, uartclk, baud_raw; 1872 1873 cr = readb(sport->port.membase + UARTCR2); 1874 cr &= UARTCR2_TE | UARTCR2_RE; 1875 if (!cr) 1876 return; 1877 1878 /* ok, the port was enabled */ 1879 1880 cr = readb(sport->port.membase + UARTCR1); 1881 1882 *parity = 'n'; 1883 if (cr & UARTCR1_PE) { 1884 if (cr & UARTCR1_PT) 1885 *parity = 'o'; 1886 else 1887 *parity = 'e'; 1888 } 1889 1890 if (cr & UARTCR1_M) 1891 *bits = 9; 1892 else 1893 *bits = 8; 1894 1895 bdh = readb(sport->port.membase + UARTBDH); 1896 bdh &= UARTBDH_SBR_MASK; 1897 bdl = readb(sport->port.membase + UARTBDL); 1898 sbr = bdh; 1899 sbr <<= 8; 1900 sbr |= bdl; 1901 brfa = readb(sport->port.membase + UARTCR4); 1902 brfa &= UARTCR4_BRFA_MASK; 1903 1904 uartclk = clk_get_rate(sport->clk); 1905 /* 1906 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 1907 */ 1908 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 1909 1910 if (*baud != baud_raw) 1911 printk(KERN_INFO "Serial: Console lpuart rounded baud rate" 1912 "from %d to %d\n", baud_raw, *baud); 1913 } 1914 1915 static void __init 1916 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 1917 int *parity, int *bits) 1918 { 1919 unsigned long cr, bd; 1920 unsigned int sbr, uartclk, baud_raw; 1921 1922 cr = lpuart32_read(&sport->port, UARTCTRL); 1923 cr &= UARTCTRL_TE | UARTCTRL_RE; 1924 if (!cr) 1925 return; 1926 1927 /* ok, the port was enabled */ 1928 1929 cr = lpuart32_read(&sport->port, UARTCTRL); 1930 1931 *parity = 'n'; 1932 if (cr & UARTCTRL_PE) { 1933 if (cr & UARTCTRL_PT) 1934 *parity = 'o'; 1935 else 1936 *parity = 'e'; 1937 } 1938 1939 if (cr & UARTCTRL_M) 1940 *bits = 9; 1941 else 1942 *bits = 8; 1943 1944 bd = lpuart32_read(&sport->port, UARTBAUD); 1945 bd &= UARTBAUD_SBR_MASK; 1946 sbr = bd; 1947 uartclk = clk_get_rate(sport->clk); 1948 /* 1949 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 1950 */ 1951 baud_raw = uartclk / (16 * sbr); 1952 1953 if (*baud != baud_raw) 1954 printk(KERN_INFO "Serial: Console lpuart rounded baud rate" 1955 "from %d to %d\n", baud_raw, *baud); 1956 } 1957 1958 static int __init lpuart_console_setup(struct console *co, char *options) 1959 { 1960 struct lpuart_port *sport; 1961 int baud = 115200; 1962 int bits = 8; 1963 int parity = 'n'; 1964 int flow = 'n'; 1965 1966 /* 1967 * check whether an invalid uart number has been specified, and 1968 * if so, search for the first available port that does have 1969 * console support. 1970 */ 1971 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 1972 co->index = 0; 1973 1974 sport = lpuart_ports[co->index]; 1975 if (sport == NULL) 1976 return -ENODEV; 1977 1978 if (options) 1979 uart_parse_options(options, &baud, &parity, &bits, &flow); 1980 else 1981 if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE)) 1982 lpuart32_console_get_options(sport, &baud, &parity, &bits); 1983 else 1984 lpuart_console_get_options(sport, &baud, &parity, &bits); 1985 1986 if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE)) 1987 lpuart32_setup_watermark(sport); 1988 else 1989 lpuart_setup_watermark(sport); 1990 1991 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 1992 } 1993 1994 static struct uart_driver lpuart_reg; 1995 static struct console lpuart_console = { 1996 .name = DEV_NAME, 1997 .write = lpuart_console_write, 1998 .device = uart_console_device, 1999 .setup = lpuart_console_setup, 2000 .flags = CON_PRINTBUFFER, 2001 .index = -1, 2002 .data = &lpuart_reg, 2003 }; 2004 2005 static struct console lpuart32_console = { 2006 .name = DEV_NAME, 2007 .write = lpuart32_console_write, 2008 .device = uart_console_device, 2009 .setup = lpuart_console_setup, 2010 .flags = CON_PRINTBUFFER, 2011 .index = -1, 2012 .data = &lpuart_reg, 2013 }; 2014 2015 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2016 { 2017 struct earlycon_device *dev = con->data; 2018 2019 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2020 } 2021 2022 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2023 { 2024 struct earlycon_device *dev = con->data; 2025 2026 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2027 } 2028 2029 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2030 const char *opt) 2031 { 2032 if (!device->port.membase) 2033 return -ENODEV; 2034 2035 device->con->write = lpuart_early_write; 2036 return 0; 2037 } 2038 2039 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2040 const char *opt) 2041 { 2042 if (!device->port.membase) 2043 return -ENODEV; 2044 2045 device->port.iotype = UPIO_MEM32BE; 2046 device->con->write = lpuart32_early_write; 2047 return 0; 2048 } 2049 2050 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2051 const char *opt) 2052 { 2053 if (!device->port.membase) 2054 return -ENODEV; 2055 2056 device->port.iotype = UPIO_MEM32; 2057 device->port.membase += IMX_REG_OFF; 2058 device->con->write = lpuart32_early_write; 2059 2060 return 0; 2061 } 2062 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2063 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2064 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2065 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2066 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2067 2068 #define LPUART_CONSOLE (&lpuart_console) 2069 #define LPUART32_CONSOLE (&lpuart32_console) 2070 #else 2071 #define LPUART_CONSOLE NULL 2072 #define LPUART32_CONSOLE NULL 2073 #endif 2074 2075 static struct uart_driver lpuart_reg = { 2076 .owner = THIS_MODULE, 2077 .driver_name = DRIVER_NAME, 2078 .dev_name = DEV_NAME, 2079 .nr = ARRAY_SIZE(lpuart_ports), 2080 .cons = LPUART_CONSOLE, 2081 }; 2082 2083 static int lpuart_probe(struct platform_device *pdev) 2084 { 2085 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids, 2086 &pdev->dev); 2087 const struct lpuart_soc_data *sdata = of_id->data; 2088 struct device_node *np = pdev->dev.of_node; 2089 struct lpuart_port *sport; 2090 struct resource *res; 2091 int ret; 2092 2093 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2094 if (!sport) 2095 return -ENOMEM; 2096 2097 pdev->dev.coherent_dma_mask = 0; 2098 2099 ret = of_alias_get_id(np, "serial"); 2100 if (ret < 0) { 2101 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2102 return ret; 2103 } 2104 sport->port.line = ret; 2105 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2106 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 2107 if (IS_ERR(sport->port.membase)) 2108 return PTR_ERR(sport->port.membase); 2109 2110 sport->port.membase += sdata->reg_off; 2111 sport->port.mapbase = res->start; 2112 sport->port.dev = &pdev->dev; 2113 sport->port.type = PORT_LPUART; 2114 ret = platform_get_irq(pdev, 0); 2115 if (ret < 0) { 2116 dev_err(&pdev->dev, "cannot obtain irq\n"); 2117 return ret; 2118 } 2119 sport->port.irq = ret; 2120 sport->port.iotype = sdata->iotype; 2121 if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE)) 2122 sport->port.ops = &lpuart32_pops; 2123 else 2124 sport->port.ops = &lpuart_pops; 2125 sport->port.flags = UPF_BOOT_AUTOCONF; 2126 2127 sport->port.rs485_config = lpuart_config_rs485; 2128 2129 sport->clk = devm_clk_get(&pdev->dev, "ipg"); 2130 if (IS_ERR(sport->clk)) { 2131 ret = PTR_ERR(sport->clk); 2132 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret); 2133 return ret; 2134 } 2135 2136 ret = clk_prepare_enable(sport->clk); 2137 if (ret) { 2138 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret); 2139 return ret; 2140 } 2141 2142 sport->port.uartclk = clk_get_rate(sport->clk); 2143 2144 lpuart_ports[sport->port.line] = sport; 2145 2146 platform_set_drvdata(pdev, &sport->port); 2147 2148 if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE)) 2149 lpuart_reg.cons = LPUART32_CONSOLE; 2150 else 2151 lpuart_reg.cons = LPUART_CONSOLE; 2152 2153 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2154 if (ret) { 2155 clk_disable_unprepare(sport->clk); 2156 return ret; 2157 } 2158 2159 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx"); 2160 if (!sport->dma_tx_chan) 2161 dev_info(sport->port.dev, "DMA tx channel request failed, " 2162 "operating without tx DMA\n"); 2163 2164 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx"); 2165 if (!sport->dma_rx_chan) 2166 dev_info(sport->port.dev, "DMA rx channel request failed, " 2167 "operating without rx DMA\n"); 2168 2169 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) { 2170 sport->port.rs485.flags |= SER_RS485_ENABLED; 2171 sport->port.rs485.flags |= SER_RS485_RTS_ON_SEND; 2172 writeb(UARTMODEM_TXRTSE, sport->port.membase + UARTMODEM); 2173 } 2174 2175 return 0; 2176 } 2177 2178 static int lpuart_remove(struct platform_device *pdev) 2179 { 2180 struct lpuart_port *sport = platform_get_drvdata(pdev); 2181 2182 uart_remove_one_port(&lpuart_reg, &sport->port); 2183 2184 clk_disable_unprepare(sport->clk); 2185 2186 if (sport->dma_tx_chan) 2187 dma_release_channel(sport->dma_tx_chan); 2188 2189 if (sport->dma_rx_chan) 2190 dma_release_channel(sport->dma_rx_chan); 2191 2192 return 0; 2193 } 2194 2195 #ifdef CONFIG_PM_SLEEP 2196 static int lpuart_suspend(struct device *dev) 2197 { 2198 struct lpuart_port *sport = dev_get_drvdata(dev); 2199 unsigned long temp; 2200 2201 if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE)) { 2202 /* disable Rx/Tx and interrupts */ 2203 temp = lpuart32_read(&sport->port, UARTCTRL); 2204 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2205 lpuart32_write(&sport->port, temp, UARTCTRL); 2206 } else { 2207 /* disable Rx/Tx and interrupts */ 2208 temp = readb(sport->port.membase + UARTCR2); 2209 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2210 writeb(temp, sport->port.membase + UARTCR2); 2211 } 2212 2213 uart_suspend_port(&lpuart_reg, &sport->port); 2214 2215 if (sport->lpuart_dma_rx_use) { 2216 /* 2217 * EDMA driver during suspend will forcefully release any 2218 * non-idle DMA channels. If port wakeup is enabled or if port 2219 * is console port or 'no_console_suspend' is set the Rx DMA 2220 * cannot resume as as expected, hence gracefully release the 2221 * Rx DMA path before suspend and start Rx DMA path on resume. 2222 */ 2223 if (sport->port.irq_wake) { 2224 del_timer_sync(&sport->lpuart_timer); 2225 lpuart_dma_rx_free(&sport->port); 2226 } 2227 2228 /* Disable Rx DMA to use UART port as wakeup source */ 2229 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS, 2230 sport->port.membase + UARTCR5); 2231 } 2232 2233 if (sport->lpuart_dma_tx_use) { 2234 sport->dma_tx_in_progress = false; 2235 dmaengine_terminate_all(sport->dma_tx_chan); 2236 } 2237 2238 if (sport->port.suspended && !sport->port.irq_wake) 2239 clk_disable_unprepare(sport->clk); 2240 2241 return 0; 2242 } 2243 2244 static int lpuart_resume(struct device *dev) 2245 { 2246 struct lpuart_port *sport = dev_get_drvdata(dev); 2247 unsigned long temp; 2248 2249 if (sport->port.suspended && !sport->port.irq_wake) 2250 clk_prepare_enable(sport->clk); 2251 2252 if (sport->port.iotype & (UPIO_MEM32 | UPIO_MEM32BE)) { 2253 lpuart32_setup_watermark(sport); 2254 temp = lpuart32_read(&sport->port, UARTCTRL); 2255 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | 2256 UARTCTRL_TE | UARTCTRL_ILIE); 2257 lpuart32_write(&sport->port, temp, UARTCTRL); 2258 } else { 2259 lpuart_setup_watermark(sport); 2260 temp = readb(sport->port.membase + UARTCR2); 2261 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 2262 writeb(temp, sport->port.membase + UARTCR2); 2263 } 2264 2265 if (sport->lpuart_dma_rx_use) { 2266 if (sport->port.irq_wake) { 2267 if (!lpuart_start_rx_dma(sport)) 2268 rx_dma_timer_init(sport); 2269 else 2270 sport->lpuart_dma_rx_use = false; 2271 } 2272 } 2273 2274 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) { 2275 init_waitqueue_head(&sport->dma_wait); 2276 sport->lpuart_dma_tx_use = true; 2277 writeb(readb(sport->port.membase + UARTCR5) | 2278 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 2279 } else { 2280 sport->lpuart_dma_tx_use = false; 2281 } 2282 2283 uart_resume_port(&lpuart_reg, &sport->port); 2284 2285 return 0; 2286 } 2287 #endif 2288 2289 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2290 2291 static struct platform_driver lpuart_driver = { 2292 .probe = lpuart_probe, 2293 .remove = lpuart_remove, 2294 .driver = { 2295 .name = "fsl-lpuart", 2296 .of_match_table = lpuart_dt_ids, 2297 .pm = &lpuart_pm_ops, 2298 }, 2299 }; 2300 2301 static int __init lpuart_serial_init(void) 2302 { 2303 int ret = uart_register_driver(&lpuart_reg); 2304 2305 if (ret) 2306 return ret; 2307 2308 ret = platform_driver_register(&lpuart_driver); 2309 if (ret) 2310 uart_unregister_driver(&lpuart_reg); 2311 2312 return ret; 2313 } 2314 2315 static void __exit lpuart_serial_exit(void) 2316 { 2317 platform_driver_unregister(&lpuart_driver); 2318 uart_unregister_driver(&lpuart_reg); 2319 } 2320 2321 module_init(lpuart_serial_init); 2322 module_exit(lpuart_serial_exit); 2323 2324 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2325 MODULE_LICENSE("GPL v2"); 2326