1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale lpuart serial port driver 4 * 5 * Copyright 2012-2014 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/console.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/dmapool.h> 14 #include <linux/io.h> 15 #include <linux/irq.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/of_dma.h> 20 #include <linux/serial_core.h> 21 #include <linux/slab.h> 22 #include <linux/tty_flip.h> 23 24 /* All registers are 8-bit width */ 25 #define UARTBDH 0x00 26 #define UARTBDL 0x01 27 #define UARTCR1 0x02 28 #define UARTCR2 0x03 29 #define UARTSR1 0x04 30 #define UARTCR3 0x06 31 #define UARTDR 0x07 32 #define UARTCR4 0x0a 33 #define UARTCR5 0x0b 34 #define UARTMODEM 0x0d 35 #define UARTPFIFO 0x10 36 #define UARTCFIFO 0x11 37 #define UARTSFIFO 0x12 38 #define UARTTWFIFO 0x13 39 #define UARTTCFIFO 0x14 40 #define UARTRWFIFO 0x15 41 42 #define UARTBDH_LBKDIE 0x80 43 #define UARTBDH_RXEDGIE 0x40 44 #define UARTBDH_SBR_MASK 0x1f 45 46 #define UARTCR1_LOOPS 0x80 47 #define UARTCR1_RSRC 0x20 48 #define UARTCR1_M 0x10 49 #define UARTCR1_WAKE 0x08 50 #define UARTCR1_ILT 0x04 51 #define UARTCR1_PE 0x02 52 #define UARTCR1_PT 0x01 53 54 #define UARTCR2_TIE 0x80 55 #define UARTCR2_TCIE 0x40 56 #define UARTCR2_RIE 0x20 57 #define UARTCR2_ILIE 0x10 58 #define UARTCR2_TE 0x08 59 #define UARTCR2_RE 0x04 60 #define UARTCR2_RWU 0x02 61 #define UARTCR2_SBK 0x01 62 63 #define UARTSR1_TDRE 0x80 64 #define UARTSR1_TC 0x40 65 #define UARTSR1_RDRF 0x20 66 #define UARTSR1_IDLE 0x10 67 #define UARTSR1_OR 0x08 68 #define UARTSR1_NF 0x04 69 #define UARTSR1_FE 0x02 70 #define UARTSR1_PE 0x01 71 72 #define UARTCR3_R8 0x80 73 #define UARTCR3_T8 0x40 74 #define UARTCR3_TXDIR 0x20 75 #define UARTCR3_TXINV 0x10 76 #define UARTCR3_ORIE 0x08 77 #define UARTCR3_NEIE 0x04 78 #define UARTCR3_FEIE 0x02 79 #define UARTCR3_PEIE 0x01 80 81 #define UARTCR4_MAEN1 0x80 82 #define UARTCR4_MAEN2 0x40 83 #define UARTCR4_M10 0x20 84 #define UARTCR4_BRFA_MASK 0x1f 85 #define UARTCR4_BRFA_OFF 0 86 87 #define UARTCR5_TDMAS 0x80 88 #define UARTCR5_RDMAS 0x20 89 90 #define UARTMODEM_RXRTSE 0x08 91 #define UARTMODEM_TXRTSPOL 0x04 92 #define UARTMODEM_TXRTSE 0x02 93 #define UARTMODEM_TXCTSE 0x01 94 95 #define UARTPFIFO_TXFE 0x80 96 #define UARTPFIFO_FIFOSIZE_MASK 0x7 97 #define UARTPFIFO_TXSIZE_OFF 4 98 #define UARTPFIFO_RXFE 0x08 99 #define UARTPFIFO_RXSIZE_OFF 0 100 101 #define UARTCFIFO_TXFLUSH 0x80 102 #define UARTCFIFO_RXFLUSH 0x40 103 #define UARTCFIFO_RXOFE 0x04 104 #define UARTCFIFO_TXOFE 0x02 105 #define UARTCFIFO_RXUFE 0x01 106 107 #define UARTSFIFO_TXEMPT 0x80 108 #define UARTSFIFO_RXEMPT 0x40 109 #define UARTSFIFO_RXOF 0x04 110 #define UARTSFIFO_TXOF 0x02 111 #define UARTSFIFO_RXUF 0x01 112 113 /* 32-bit global registers only for i.MX7ULP/i.MX8x 114 * Used to reset all internal logic and registers, except the Global Register. 115 */ 116 #define UART_GLOBAL 0x8 117 118 /* 32-bit register definition */ 119 #define UARTBAUD 0x00 120 #define UARTSTAT 0x04 121 #define UARTCTRL 0x08 122 #define UARTDATA 0x0C 123 #define UARTMATCH 0x10 124 #define UARTMODIR 0x14 125 #define UARTFIFO 0x18 126 #define UARTWATER 0x1c 127 128 #define UARTBAUD_MAEN1 0x80000000 129 #define UARTBAUD_MAEN2 0x40000000 130 #define UARTBAUD_M10 0x20000000 131 #define UARTBAUD_TDMAE 0x00800000 132 #define UARTBAUD_RDMAE 0x00200000 133 #define UARTBAUD_MATCFG 0x00400000 134 #define UARTBAUD_BOTHEDGE 0x00020000 135 #define UARTBAUD_RESYNCDIS 0x00010000 136 #define UARTBAUD_LBKDIE 0x00008000 137 #define UARTBAUD_RXEDGIE 0x00004000 138 #define UARTBAUD_SBNS 0x00002000 139 #define UARTBAUD_SBR 0x00000000 140 #define UARTBAUD_SBR_MASK 0x1fff 141 #define UARTBAUD_OSR_MASK 0x1f 142 #define UARTBAUD_OSR_SHIFT 24 143 144 #define UARTSTAT_LBKDIF 0x80000000 145 #define UARTSTAT_RXEDGIF 0x40000000 146 #define UARTSTAT_MSBF 0x20000000 147 #define UARTSTAT_RXINV 0x10000000 148 #define UARTSTAT_RWUID 0x08000000 149 #define UARTSTAT_BRK13 0x04000000 150 #define UARTSTAT_LBKDE 0x02000000 151 #define UARTSTAT_RAF 0x01000000 152 #define UARTSTAT_TDRE 0x00800000 153 #define UARTSTAT_TC 0x00400000 154 #define UARTSTAT_RDRF 0x00200000 155 #define UARTSTAT_IDLE 0x00100000 156 #define UARTSTAT_OR 0x00080000 157 #define UARTSTAT_NF 0x00040000 158 #define UARTSTAT_FE 0x00020000 159 #define UARTSTAT_PE 0x00010000 160 #define UARTSTAT_MA1F 0x00008000 161 #define UARTSTAT_M21F 0x00004000 162 163 #define UARTCTRL_R8T9 0x80000000 164 #define UARTCTRL_R9T8 0x40000000 165 #define UARTCTRL_TXDIR 0x20000000 166 #define UARTCTRL_TXINV 0x10000000 167 #define UARTCTRL_ORIE 0x08000000 168 #define UARTCTRL_NEIE 0x04000000 169 #define UARTCTRL_FEIE 0x02000000 170 #define UARTCTRL_PEIE 0x01000000 171 #define UARTCTRL_TIE 0x00800000 172 #define UARTCTRL_TCIE 0x00400000 173 #define UARTCTRL_RIE 0x00200000 174 #define UARTCTRL_ILIE 0x00100000 175 #define UARTCTRL_TE 0x00080000 176 #define UARTCTRL_RE 0x00040000 177 #define UARTCTRL_RWU 0x00020000 178 #define UARTCTRL_SBK 0x00010000 179 #define UARTCTRL_MA1IE 0x00008000 180 #define UARTCTRL_MA2IE 0x00004000 181 #define UARTCTRL_IDLECFG 0x00000100 182 #define UARTCTRL_LOOPS 0x00000080 183 #define UARTCTRL_DOZEEN 0x00000040 184 #define UARTCTRL_RSRC 0x00000020 185 #define UARTCTRL_M 0x00000010 186 #define UARTCTRL_WAKE 0x00000008 187 #define UARTCTRL_ILT 0x00000004 188 #define UARTCTRL_PE 0x00000002 189 #define UARTCTRL_PT 0x00000001 190 191 #define UARTDATA_NOISY 0x00008000 192 #define UARTDATA_PARITYE 0x00004000 193 #define UARTDATA_FRETSC 0x00002000 194 #define UARTDATA_RXEMPT 0x00001000 195 #define UARTDATA_IDLINE 0x00000800 196 #define UARTDATA_MASK 0x3ff 197 198 #define UARTMODIR_IREN 0x00020000 199 #define UARTMODIR_TXCTSSRC 0x00000020 200 #define UARTMODIR_TXCTSC 0x00000010 201 #define UARTMODIR_RXRTSE 0x00000008 202 #define UARTMODIR_TXRTSPOL 0x00000004 203 #define UARTMODIR_TXRTSE 0x00000002 204 #define UARTMODIR_TXCTSE 0x00000001 205 206 #define UARTFIFO_TXEMPT 0x00800000 207 #define UARTFIFO_RXEMPT 0x00400000 208 #define UARTFIFO_TXOF 0x00020000 209 #define UARTFIFO_RXUF 0x00010000 210 #define UARTFIFO_TXFLUSH 0x00008000 211 #define UARTFIFO_RXFLUSH 0x00004000 212 #define UARTFIFO_TXOFE 0x00000200 213 #define UARTFIFO_RXUFE 0x00000100 214 #define UARTFIFO_TXFE 0x00000080 215 #define UARTFIFO_FIFOSIZE_MASK 0x7 216 #define UARTFIFO_TXSIZE_OFF 4 217 #define UARTFIFO_RXFE 0x00000008 218 #define UARTFIFO_RXSIZE_OFF 0 219 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0)) 220 221 #define UARTWATER_COUNT_MASK 0xff 222 #define UARTWATER_TXCNT_OFF 8 223 #define UARTWATER_RXCNT_OFF 24 224 #define UARTWATER_WATER_MASK 0xff 225 #define UARTWATER_TXWATER_OFF 0 226 #define UARTWATER_RXWATER_OFF 16 227 228 #define UART_GLOBAL_RST 0x2 229 #define GLOBAL_RST_MIN_US 20 230 #define GLOBAL_RST_MAX_US 40 231 232 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 233 #define DMA_RX_TIMEOUT (10) 234 235 #define DRIVER_NAME "fsl-lpuart" 236 #define DEV_NAME "ttyLP" 237 #define UART_NR 6 238 239 /* IMX lpuart has four extra unused regs located at the beginning */ 240 #define IMX_REG_OFF 0x10 241 242 static DEFINE_IDA(fsl_lpuart_ida); 243 244 enum lpuart_type { 245 VF610_LPUART, 246 LS1021A_LPUART, 247 LS1028A_LPUART, 248 IMX7ULP_LPUART, 249 IMX8QXP_LPUART, 250 IMXRT1050_LPUART, 251 }; 252 253 struct lpuart_port { 254 struct uart_port port; 255 enum lpuart_type devtype; 256 struct clk *ipg_clk; 257 struct clk *baud_clk; 258 unsigned int txfifo_size; 259 unsigned int rxfifo_size; 260 261 bool lpuart_dma_tx_use; 262 bool lpuart_dma_rx_use; 263 struct dma_chan *dma_tx_chan; 264 struct dma_chan *dma_rx_chan; 265 struct dma_async_tx_descriptor *dma_tx_desc; 266 struct dma_async_tx_descriptor *dma_rx_desc; 267 dma_cookie_t dma_tx_cookie; 268 dma_cookie_t dma_rx_cookie; 269 unsigned int dma_tx_bytes; 270 unsigned int dma_rx_bytes; 271 bool dma_tx_in_progress; 272 unsigned int dma_rx_timeout; 273 struct timer_list lpuart_timer; 274 struct scatterlist rx_sgl, tx_sgl[2]; 275 struct circ_buf rx_ring; 276 int rx_dma_rng_buf_len; 277 unsigned int dma_tx_nents; 278 wait_queue_head_t dma_wait; 279 bool id_allocated; 280 }; 281 282 struct lpuart_soc_data { 283 enum lpuart_type devtype; 284 char iotype; 285 u8 reg_off; 286 }; 287 288 static const struct lpuart_soc_data vf_data = { 289 .devtype = VF610_LPUART, 290 .iotype = UPIO_MEM, 291 }; 292 293 static const struct lpuart_soc_data ls1021a_data = { 294 .devtype = LS1021A_LPUART, 295 .iotype = UPIO_MEM32BE, 296 }; 297 298 static const struct lpuart_soc_data ls1028a_data = { 299 .devtype = LS1028A_LPUART, 300 .iotype = UPIO_MEM32, 301 }; 302 303 static struct lpuart_soc_data imx7ulp_data = { 304 .devtype = IMX7ULP_LPUART, 305 .iotype = UPIO_MEM32, 306 .reg_off = IMX_REG_OFF, 307 }; 308 309 static struct lpuart_soc_data imx8qxp_data = { 310 .devtype = IMX8QXP_LPUART, 311 .iotype = UPIO_MEM32, 312 .reg_off = IMX_REG_OFF, 313 }; 314 static struct lpuart_soc_data imxrt1050_data = { 315 .devtype = IMXRT1050_LPUART, 316 .iotype = UPIO_MEM32, 317 .reg_off = IMX_REG_OFF, 318 }; 319 320 static const struct of_device_id lpuart_dt_ids[] = { 321 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 322 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, }, 323 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, }, 324 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, 325 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, 326 { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data}, 327 { /* sentinel */ } 328 }; 329 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 330 331 /* Forward declare this for the dma callbacks*/ 332 static void lpuart_dma_tx_complete(void *arg); 333 334 static inline bool is_layerscape_lpuart(struct lpuart_port *sport) 335 { 336 return (sport->devtype == LS1021A_LPUART || 337 sport->devtype == LS1028A_LPUART); 338 } 339 340 static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport) 341 { 342 return sport->devtype == IMX7ULP_LPUART; 343 } 344 345 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) 346 { 347 return sport->devtype == IMX8QXP_LPUART; 348 } 349 350 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 351 { 352 switch (port->iotype) { 353 case UPIO_MEM32: 354 return readl(port->membase + off); 355 case UPIO_MEM32BE: 356 return ioread32be(port->membase + off); 357 default: 358 return 0; 359 } 360 } 361 362 static inline void lpuart32_write(struct uart_port *port, u32 val, 363 u32 off) 364 { 365 switch (port->iotype) { 366 case UPIO_MEM32: 367 writel(val, port->membase + off); 368 break; 369 case UPIO_MEM32BE: 370 iowrite32be(val, port->membase + off); 371 break; 372 } 373 } 374 375 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) 376 { 377 int ret = 0; 378 379 if (is_en) { 380 ret = clk_prepare_enable(sport->ipg_clk); 381 if (ret) 382 return ret; 383 384 ret = clk_prepare_enable(sport->baud_clk); 385 if (ret) { 386 clk_disable_unprepare(sport->ipg_clk); 387 return ret; 388 } 389 } else { 390 clk_disable_unprepare(sport->baud_clk); 391 clk_disable_unprepare(sport->ipg_clk); 392 } 393 394 return 0; 395 } 396 397 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) 398 { 399 if (is_imx8qxp_lpuart(sport)) 400 return clk_get_rate(sport->baud_clk); 401 402 return clk_get_rate(sport->ipg_clk); 403 } 404 405 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true) 406 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false) 407 408 static int lpuart_global_reset(struct lpuart_port *sport) 409 { 410 struct uart_port *port = &sport->port; 411 void __iomem *global_addr; 412 int ret; 413 414 if (uart_console(port)) 415 return 0; 416 417 ret = clk_prepare_enable(sport->ipg_clk); 418 if (ret) { 419 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret); 420 return ret; 421 } 422 423 if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) { 424 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF; 425 writel(UART_GLOBAL_RST, global_addr); 426 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); 427 writel(0, global_addr); 428 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); 429 } 430 431 clk_disable_unprepare(sport->ipg_clk); 432 return 0; 433 } 434 435 static void lpuart_stop_tx(struct uart_port *port) 436 { 437 unsigned char temp; 438 439 temp = readb(port->membase + UARTCR2); 440 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 441 writeb(temp, port->membase + UARTCR2); 442 } 443 444 static void lpuart32_stop_tx(struct uart_port *port) 445 { 446 unsigned long temp; 447 448 temp = lpuart32_read(port, UARTCTRL); 449 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 450 lpuart32_write(port, temp, UARTCTRL); 451 } 452 453 static void lpuart_stop_rx(struct uart_port *port) 454 { 455 unsigned char temp; 456 457 temp = readb(port->membase + UARTCR2); 458 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 459 } 460 461 static void lpuart32_stop_rx(struct uart_port *port) 462 { 463 unsigned long temp; 464 465 temp = lpuart32_read(port, UARTCTRL); 466 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); 467 } 468 469 static void lpuart_dma_tx(struct lpuart_port *sport) 470 { 471 struct circ_buf *xmit = &sport->port.state->xmit; 472 struct scatterlist *sgl = sport->tx_sgl; 473 struct device *dev = sport->port.dev; 474 struct dma_chan *chan = sport->dma_tx_chan; 475 int ret; 476 477 if (sport->dma_tx_in_progress) 478 return; 479 480 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 481 482 if (xmit->tail < xmit->head || xmit->head == 0) { 483 sport->dma_tx_nents = 1; 484 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 485 } else { 486 sport->dma_tx_nents = 2; 487 sg_init_table(sgl, 2); 488 sg_set_buf(sgl, xmit->buf + xmit->tail, 489 UART_XMIT_SIZE - xmit->tail); 490 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 491 } 492 493 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, 494 DMA_TO_DEVICE); 495 if (!ret) { 496 dev_err(dev, "DMA mapping error for TX.\n"); 497 return; 498 } 499 500 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, 501 ret, DMA_MEM_TO_DEV, 502 DMA_PREP_INTERRUPT); 503 if (!sport->dma_tx_desc) { 504 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 505 DMA_TO_DEVICE); 506 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 507 return; 508 } 509 510 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 511 sport->dma_tx_desc->callback_param = sport; 512 sport->dma_tx_in_progress = true; 513 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 514 dma_async_issue_pending(chan); 515 } 516 517 static bool lpuart_stopped_or_empty(struct uart_port *port) 518 { 519 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); 520 } 521 522 static void lpuart_dma_tx_complete(void *arg) 523 { 524 struct lpuart_port *sport = arg; 525 struct scatterlist *sgl = &sport->tx_sgl[0]; 526 struct circ_buf *xmit = &sport->port.state->xmit; 527 struct dma_chan *chan = sport->dma_tx_chan; 528 unsigned long flags; 529 530 spin_lock_irqsave(&sport->port.lock, flags); 531 if (!sport->dma_tx_in_progress) { 532 spin_unlock_irqrestore(&sport->port.lock, flags); 533 return; 534 } 535 536 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 537 DMA_TO_DEVICE); 538 539 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 540 541 sport->port.icount.tx += sport->dma_tx_bytes; 542 sport->dma_tx_in_progress = false; 543 spin_unlock_irqrestore(&sport->port.lock, flags); 544 545 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 546 uart_write_wakeup(&sport->port); 547 548 if (waitqueue_active(&sport->dma_wait)) { 549 wake_up(&sport->dma_wait); 550 return; 551 } 552 553 spin_lock_irqsave(&sport->port.lock, flags); 554 555 if (!lpuart_stopped_or_empty(&sport->port)) 556 lpuart_dma_tx(sport); 557 558 spin_unlock_irqrestore(&sport->port.lock, flags); 559 } 560 561 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) 562 { 563 switch (sport->port.iotype) { 564 case UPIO_MEM32: 565 return sport->port.mapbase + UARTDATA; 566 case UPIO_MEM32BE: 567 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; 568 } 569 return sport->port.mapbase + UARTDR; 570 } 571 572 static int lpuart_dma_tx_request(struct uart_port *port) 573 { 574 struct lpuart_port *sport = container_of(port, 575 struct lpuart_port, port); 576 struct dma_slave_config dma_tx_sconfig = {}; 577 int ret; 578 579 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); 580 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 581 dma_tx_sconfig.dst_maxburst = 1; 582 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 583 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 584 585 if (ret) { 586 dev_err(sport->port.dev, 587 "DMA slave config failed, err = %d\n", ret); 588 return ret; 589 } 590 591 return 0; 592 } 593 594 static bool lpuart_is_32(struct lpuart_port *sport) 595 { 596 return sport->port.iotype == UPIO_MEM32 || 597 sport->port.iotype == UPIO_MEM32BE; 598 } 599 600 static void lpuart_flush_buffer(struct uart_port *port) 601 { 602 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 603 struct dma_chan *chan = sport->dma_tx_chan; 604 u32 val; 605 606 if (sport->lpuart_dma_tx_use) { 607 if (sport->dma_tx_in_progress) { 608 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], 609 sport->dma_tx_nents, DMA_TO_DEVICE); 610 sport->dma_tx_in_progress = false; 611 } 612 dmaengine_terminate_all(chan); 613 } 614 615 if (lpuart_is_32(sport)) { 616 val = lpuart32_read(&sport->port, UARTFIFO); 617 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 618 lpuart32_write(&sport->port, val, UARTFIFO); 619 } else { 620 val = readb(sport->port.membase + UARTCFIFO); 621 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; 622 writeb(val, sport->port.membase + UARTCFIFO); 623 } 624 } 625 626 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset, 627 u8 bit) 628 { 629 while (!(readb(port->membase + offset) & bit)) 630 cpu_relax(); 631 } 632 633 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset, 634 u32 bit) 635 { 636 while (!(lpuart32_read(port, offset) & bit)) 637 cpu_relax(); 638 } 639 640 #if defined(CONFIG_CONSOLE_POLL) 641 642 static int lpuart_poll_init(struct uart_port *port) 643 { 644 struct lpuart_port *sport = container_of(port, 645 struct lpuart_port, port); 646 unsigned long flags; 647 unsigned char temp; 648 649 sport->port.fifosize = 0; 650 651 spin_lock_irqsave(&sport->port.lock, flags); 652 /* Disable Rx & Tx */ 653 writeb(0, sport->port.membase + UARTCR2); 654 655 temp = readb(sport->port.membase + UARTPFIFO); 656 /* Enable Rx and Tx FIFO */ 657 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 658 sport->port.membase + UARTPFIFO); 659 660 /* flush Tx and Rx FIFO */ 661 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 662 sport->port.membase + UARTCFIFO); 663 664 /* explicitly clear RDRF */ 665 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 666 readb(sport->port.membase + UARTDR); 667 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 668 } 669 670 writeb(0, sport->port.membase + UARTTWFIFO); 671 writeb(1, sport->port.membase + UARTRWFIFO); 672 673 /* Enable Rx and Tx */ 674 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 675 spin_unlock_irqrestore(&sport->port.lock, flags); 676 677 return 0; 678 } 679 680 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 681 { 682 /* drain */ 683 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 684 writeb(c, port->membase + UARTDR); 685 } 686 687 static int lpuart_poll_get_char(struct uart_port *port) 688 { 689 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 690 return NO_POLL_CHAR; 691 692 return readb(port->membase + UARTDR); 693 } 694 695 static int lpuart32_poll_init(struct uart_port *port) 696 { 697 unsigned long flags; 698 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 699 u32 temp; 700 701 sport->port.fifosize = 0; 702 703 spin_lock_irqsave(&sport->port.lock, flags); 704 705 /* Disable Rx & Tx */ 706 lpuart32_write(&sport->port, 0, UARTCTRL); 707 708 temp = lpuart32_read(&sport->port, UARTFIFO); 709 710 /* Enable Rx and Tx FIFO */ 711 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); 712 713 /* flush Tx and Rx FIFO */ 714 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); 715 716 /* explicitly clear RDRF */ 717 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { 718 lpuart32_read(&sport->port, UARTDATA); 719 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); 720 } 721 722 /* Enable Rx and Tx */ 723 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); 724 spin_unlock_irqrestore(&sport->port.lock, flags); 725 726 return 0; 727 } 728 729 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 730 { 731 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 732 lpuart32_write(port, c, UARTDATA); 733 } 734 735 static int lpuart32_poll_get_char(struct uart_port *port) 736 { 737 if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF)) 738 return NO_POLL_CHAR; 739 740 return lpuart32_read(port, UARTDATA); 741 } 742 #endif 743 744 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 745 { 746 struct circ_buf *xmit = &sport->port.state->xmit; 747 748 if (sport->port.x_char) { 749 writeb(sport->port.x_char, sport->port.membase + UARTDR); 750 sport->port.icount.tx++; 751 sport->port.x_char = 0; 752 return; 753 } 754 755 if (lpuart_stopped_or_empty(&sport->port)) { 756 lpuart_stop_tx(&sport->port); 757 return; 758 } 759 760 while (!uart_circ_empty(xmit) && 761 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 762 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 763 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 764 sport->port.icount.tx++; 765 } 766 767 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 768 uart_write_wakeup(&sport->port); 769 770 if (uart_circ_empty(xmit)) 771 lpuart_stop_tx(&sport->port); 772 } 773 774 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 775 { 776 struct circ_buf *xmit = &sport->port.state->xmit; 777 unsigned long txcnt; 778 779 if (sport->port.x_char) { 780 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 781 sport->port.icount.tx++; 782 sport->port.x_char = 0; 783 return; 784 } 785 786 if (lpuart_stopped_or_empty(&sport->port)) { 787 lpuart32_stop_tx(&sport->port); 788 return; 789 } 790 791 txcnt = lpuart32_read(&sport->port, UARTWATER); 792 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 793 txcnt &= UARTWATER_COUNT_MASK; 794 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 795 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); 796 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 797 sport->port.icount.tx++; 798 txcnt = lpuart32_read(&sport->port, UARTWATER); 799 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 800 txcnt &= UARTWATER_COUNT_MASK; 801 } 802 803 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 804 uart_write_wakeup(&sport->port); 805 806 if (uart_circ_empty(xmit)) 807 lpuart32_stop_tx(&sport->port); 808 } 809 810 static void lpuart_start_tx(struct uart_port *port) 811 { 812 struct lpuart_port *sport = container_of(port, 813 struct lpuart_port, port); 814 unsigned char temp; 815 816 temp = readb(port->membase + UARTCR2); 817 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 818 819 if (sport->lpuart_dma_tx_use) { 820 if (!lpuart_stopped_or_empty(port)) 821 lpuart_dma_tx(sport); 822 } else { 823 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 824 lpuart_transmit_buffer(sport); 825 } 826 } 827 828 static void lpuart32_start_tx(struct uart_port *port) 829 { 830 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 831 unsigned long temp; 832 833 if (sport->lpuart_dma_tx_use) { 834 if (!lpuart_stopped_or_empty(port)) 835 lpuart_dma_tx(sport); 836 } else { 837 temp = lpuart32_read(port, UARTCTRL); 838 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); 839 840 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 841 lpuart32_transmit_buffer(sport); 842 } 843 } 844 845 /* return TIOCSER_TEMT when transmitter is not busy */ 846 static unsigned int lpuart_tx_empty(struct uart_port *port) 847 { 848 struct lpuart_port *sport = container_of(port, 849 struct lpuart_port, port); 850 unsigned char sr1 = readb(port->membase + UARTSR1); 851 unsigned char sfifo = readb(port->membase + UARTSFIFO); 852 853 if (sport->dma_tx_in_progress) 854 return 0; 855 856 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 857 return TIOCSER_TEMT; 858 859 return 0; 860 } 861 862 static unsigned int lpuart32_tx_empty(struct uart_port *port) 863 { 864 struct lpuart_port *sport = container_of(port, 865 struct lpuart_port, port); 866 unsigned long stat = lpuart32_read(port, UARTSTAT); 867 unsigned long sfifo = lpuart32_read(port, UARTFIFO); 868 869 if (sport->dma_tx_in_progress) 870 return 0; 871 872 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) 873 return TIOCSER_TEMT; 874 875 return 0; 876 } 877 878 static void lpuart_txint(struct lpuart_port *sport) 879 { 880 spin_lock(&sport->port.lock); 881 lpuart_transmit_buffer(sport); 882 spin_unlock(&sport->port.lock); 883 } 884 885 static void lpuart_rxint(struct lpuart_port *sport) 886 { 887 unsigned int flg, ignored = 0, overrun = 0; 888 struct tty_port *port = &sport->port.state->port; 889 unsigned char rx, sr; 890 891 spin_lock(&sport->port.lock); 892 893 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 894 flg = TTY_NORMAL; 895 sport->port.icount.rx++; 896 /* 897 * to clear the FE, OR, NF, FE, PE flags, 898 * read SR1 then read DR 899 */ 900 sr = readb(sport->port.membase + UARTSR1); 901 rx = readb(sport->port.membase + UARTDR); 902 903 if (uart_prepare_sysrq_char(&sport->port, rx)) 904 continue; 905 906 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 907 if (sr & UARTSR1_PE) 908 sport->port.icount.parity++; 909 else if (sr & UARTSR1_FE) 910 sport->port.icount.frame++; 911 912 if (sr & UARTSR1_OR) 913 overrun++; 914 915 if (sr & sport->port.ignore_status_mask) { 916 if (++ignored > 100) 917 goto out; 918 continue; 919 } 920 921 sr &= sport->port.read_status_mask; 922 923 if (sr & UARTSR1_PE) 924 flg = TTY_PARITY; 925 else if (sr & UARTSR1_FE) 926 flg = TTY_FRAME; 927 928 if (sr & UARTSR1_OR) 929 flg = TTY_OVERRUN; 930 931 sport->port.sysrq = 0; 932 } 933 934 tty_insert_flip_char(port, rx, flg); 935 } 936 937 out: 938 if (overrun) { 939 sport->port.icount.overrun += overrun; 940 941 /* 942 * Overruns cause FIFO pointers to become missaligned. 943 * Flushing the receive FIFO reinitializes the pointers. 944 */ 945 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 946 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); 947 } 948 949 uart_unlock_and_check_sysrq(&sport->port); 950 951 tty_flip_buffer_push(port); 952 } 953 954 static void lpuart32_txint(struct lpuart_port *sport) 955 { 956 spin_lock(&sport->port.lock); 957 lpuart32_transmit_buffer(sport); 958 spin_unlock(&sport->port.lock); 959 } 960 961 static void lpuart32_rxint(struct lpuart_port *sport) 962 { 963 unsigned int flg, ignored = 0; 964 struct tty_port *port = &sport->port.state->port; 965 unsigned long rx, sr; 966 bool is_break; 967 968 spin_lock(&sport->port.lock); 969 970 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 971 flg = TTY_NORMAL; 972 sport->port.icount.rx++; 973 /* 974 * to clear the FE, OR, NF, FE, PE flags, 975 * read STAT then read DATA reg 976 */ 977 sr = lpuart32_read(&sport->port, UARTSTAT); 978 rx = lpuart32_read(&sport->port, UARTDATA); 979 rx &= UARTDATA_MASK; 980 981 /* 982 * The LPUART can't distinguish between a break and a framing error, 983 * thus we assume it is a break if the received data is zero. 984 */ 985 is_break = (sr & UARTSTAT_FE) && !rx; 986 987 if (is_break && uart_handle_break(&sport->port)) 988 continue; 989 990 if (uart_prepare_sysrq_char(&sport->port, rx)) 991 continue; 992 993 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 994 if (sr & UARTSTAT_PE) { 995 if (is_break) 996 sport->port.icount.brk++; 997 else 998 sport->port.icount.parity++; 999 } else if (sr & UARTSTAT_FE) { 1000 sport->port.icount.frame++; 1001 } 1002 1003 if (sr & UARTSTAT_OR) 1004 sport->port.icount.overrun++; 1005 1006 if (sr & sport->port.ignore_status_mask) { 1007 if (++ignored > 100) 1008 goto out; 1009 continue; 1010 } 1011 1012 sr &= sport->port.read_status_mask; 1013 1014 if (sr & UARTSTAT_PE) { 1015 if (is_break) 1016 flg = TTY_BREAK; 1017 else 1018 flg = TTY_PARITY; 1019 } else if (sr & UARTSTAT_FE) { 1020 flg = TTY_FRAME; 1021 } 1022 1023 if (sr & UARTSTAT_OR) 1024 flg = TTY_OVERRUN; 1025 } 1026 1027 tty_insert_flip_char(port, rx, flg); 1028 } 1029 1030 out: 1031 uart_unlock_and_check_sysrq(&sport->port); 1032 1033 tty_flip_buffer_push(port); 1034 } 1035 1036 static irqreturn_t lpuart_int(int irq, void *dev_id) 1037 { 1038 struct lpuart_port *sport = dev_id; 1039 unsigned char sts; 1040 1041 sts = readb(sport->port.membase + UARTSR1); 1042 1043 /* SysRq, using dma, check for linebreak by framing err. */ 1044 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { 1045 readb(sport->port.membase + UARTDR); 1046 uart_handle_break(&sport->port); 1047 /* linebreak produces some garbage, removing it */ 1048 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 1049 return IRQ_HANDLED; 1050 } 1051 1052 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) 1053 lpuart_rxint(sport); 1054 1055 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) 1056 lpuart_txint(sport); 1057 1058 return IRQ_HANDLED; 1059 } 1060 1061 static irqreturn_t lpuart32_int(int irq, void *dev_id) 1062 { 1063 struct lpuart_port *sport = dev_id; 1064 unsigned long sts, rxcount; 1065 1066 sts = lpuart32_read(&sport->port, UARTSTAT); 1067 rxcount = lpuart32_read(&sport->port, UARTWATER); 1068 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 1069 1070 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) 1071 lpuart32_rxint(sport); 1072 1073 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) 1074 lpuart32_txint(sport); 1075 1076 lpuart32_write(&sport->port, sts, UARTSTAT); 1077 return IRQ_HANDLED; 1078 } 1079 1080 1081 static inline void lpuart_handle_sysrq_chars(struct uart_port *port, 1082 unsigned char *p, int count) 1083 { 1084 while (count--) { 1085 if (*p && uart_handle_sysrq_char(port, *p)) 1086 return; 1087 p++; 1088 } 1089 } 1090 1091 static void lpuart_handle_sysrq(struct lpuart_port *sport) 1092 { 1093 struct circ_buf *ring = &sport->rx_ring; 1094 int count; 1095 1096 if (ring->head < ring->tail) { 1097 count = sport->rx_sgl.length - ring->tail; 1098 lpuart_handle_sysrq_chars(&sport->port, 1099 ring->buf + ring->tail, count); 1100 ring->tail = 0; 1101 } 1102 1103 if (ring->head > ring->tail) { 1104 count = ring->head - ring->tail; 1105 lpuart_handle_sysrq_chars(&sport->port, 1106 ring->buf + ring->tail, count); 1107 ring->tail = ring->head; 1108 } 1109 } 1110 1111 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 1112 { 1113 struct tty_port *port = &sport->port.state->port; 1114 struct dma_tx_state state; 1115 enum dma_status dmastat; 1116 struct dma_chan *chan = sport->dma_rx_chan; 1117 struct circ_buf *ring = &sport->rx_ring; 1118 unsigned long flags; 1119 int count = 0; 1120 1121 if (lpuart_is_32(sport)) { 1122 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); 1123 1124 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { 1125 /* Read DR to clear the error flags */ 1126 lpuart32_read(&sport->port, UARTDATA); 1127 1128 if (sr & UARTSTAT_PE) 1129 sport->port.icount.parity++; 1130 else if (sr & UARTSTAT_FE) 1131 sport->port.icount.frame++; 1132 } 1133 } else { 1134 unsigned char sr = readb(sport->port.membase + UARTSR1); 1135 1136 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 1137 unsigned char cr2; 1138 1139 /* Disable receiver during this operation... */ 1140 cr2 = readb(sport->port.membase + UARTCR2); 1141 cr2 &= ~UARTCR2_RE; 1142 writeb(cr2, sport->port.membase + UARTCR2); 1143 1144 /* Read DR to clear the error flags */ 1145 readb(sport->port.membase + UARTDR); 1146 1147 if (sr & UARTSR1_PE) 1148 sport->port.icount.parity++; 1149 else if (sr & UARTSR1_FE) 1150 sport->port.icount.frame++; 1151 /* 1152 * At this point parity/framing error is 1153 * cleared However, since the DMA already read 1154 * the data register and we had to read it 1155 * again after reading the status register to 1156 * properly clear the flags, the FIFO actually 1157 * underflowed... This requires a clearing of 1158 * the FIFO... 1159 */ 1160 if (readb(sport->port.membase + UARTSFIFO) & 1161 UARTSFIFO_RXUF) { 1162 writeb(UARTSFIFO_RXUF, 1163 sport->port.membase + UARTSFIFO); 1164 writeb(UARTCFIFO_RXFLUSH, 1165 sport->port.membase + UARTCFIFO); 1166 } 1167 1168 cr2 |= UARTCR2_RE; 1169 writeb(cr2, sport->port.membase + UARTCR2); 1170 } 1171 } 1172 1173 async_tx_ack(sport->dma_rx_desc); 1174 1175 spin_lock_irqsave(&sport->port.lock, flags); 1176 1177 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1178 if (dmastat == DMA_ERROR) { 1179 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1180 spin_unlock_irqrestore(&sport->port.lock, flags); 1181 return; 1182 } 1183 1184 /* CPU claims ownership of RX DMA buffer */ 1185 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, 1186 DMA_FROM_DEVICE); 1187 1188 /* 1189 * ring->head points to the end of data already written by the DMA. 1190 * ring->tail points to the beginning of data to be read by the 1191 * framework. 1192 * The current transfer size should not be larger than the dma buffer 1193 * length. 1194 */ 1195 ring->head = sport->rx_sgl.length - state.residue; 1196 BUG_ON(ring->head > sport->rx_sgl.length); 1197 1198 /* 1199 * Silent handling of keys pressed in the sysrq timeframe 1200 */ 1201 if (sport->port.sysrq) { 1202 lpuart_handle_sysrq(sport); 1203 goto exit; 1204 } 1205 1206 /* 1207 * At this point ring->head may point to the first byte right after the 1208 * last byte of the dma buffer: 1209 * 0 <= ring->head <= sport->rx_sgl.length 1210 * 1211 * However ring->tail must always points inside the dma buffer: 1212 * 0 <= ring->tail <= sport->rx_sgl.length - 1 1213 * 1214 * Since we use a ring buffer, we have to handle the case 1215 * where head is lower than tail. In such a case, we first read from 1216 * tail to the end of the buffer then reset tail. 1217 */ 1218 if (ring->head < ring->tail) { 1219 count = sport->rx_sgl.length - ring->tail; 1220 1221 tty_insert_flip_string(port, ring->buf + ring->tail, count); 1222 ring->tail = 0; 1223 sport->port.icount.rx += count; 1224 } 1225 1226 /* Finally we read data from tail to head */ 1227 if (ring->tail < ring->head) { 1228 count = ring->head - ring->tail; 1229 tty_insert_flip_string(port, ring->buf + ring->tail, count); 1230 /* Wrap ring->head if needed */ 1231 if (ring->head >= sport->rx_sgl.length) 1232 ring->head = 0; 1233 ring->tail = ring->head; 1234 sport->port.icount.rx += count; 1235 } 1236 1237 exit: 1238 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, 1239 DMA_FROM_DEVICE); 1240 1241 spin_unlock_irqrestore(&sport->port.lock, flags); 1242 1243 tty_flip_buffer_push(port); 1244 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 1245 } 1246 1247 static void lpuart_dma_rx_complete(void *arg) 1248 { 1249 struct lpuart_port *sport = arg; 1250 1251 lpuart_copy_rx_to_tty(sport); 1252 } 1253 1254 static void lpuart_timer_func(struct timer_list *t) 1255 { 1256 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); 1257 1258 lpuart_copy_rx_to_tty(sport); 1259 } 1260 1261 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 1262 { 1263 struct dma_slave_config dma_rx_sconfig = {}; 1264 struct circ_buf *ring = &sport->rx_ring; 1265 int ret, nent; 1266 int bits, baud; 1267 struct tty_port *port = &sport->port.state->port; 1268 struct tty_struct *tty = port->tty; 1269 struct ktermios *termios = &tty->termios; 1270 struct dma_chan *chan = sport->dma_rx_chan; 1271 1272 baud = tty_get_baud_rate(tty); 1273 1274 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; 1275 if (termios->c_cflag & PARENB) 1276 bits++; 1277 1278 /* 1279 * Calculate length of one DMA buffer size to keep latency below 1280 * 10ms at any baud rate. 1281 */ 1282 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 1283 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 1284 if (sport->rx_dma_rng_buf_len < 16) 1285 sport->rx_dma_rng_buf_len = 16; 1286 1287 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1288 if (!ring->buf) 1289 return -ENOMEM; 1290 1291 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1292 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, 1293 DMA_FROM_DEVICE); 1294 1295 if (!nent) { 1296 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1297 return -EINVAL; 1298 } 1299 1300 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); 1301 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1302 dma_rx_sconfig.src_maxburst = 1; 1303 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1304 ret = dmaengine_slave_config(chan, &dma_rx_sconfig); 1305 1306 if (ret < 0) { 1307 dev_err(sport->port.dev, 1308 "DMA Rx slave config failed, err = %d\n", ret); 1309 return ret; 1310 } 1311 1312 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, 1313 sg_dma_address(&sport->rx_sgl), 1314 sport->rx_sgl.length, 1315 sport->rx_sgl.length / 2, 1316 DMA_DEV_TO_MEM, 1317 DMA_PREP_INTERRUPT); 1318 if (!sport->dma_rx_desc) { 1319 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1320 return -EFAULT; 1321 } 1322 1323 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1324 sport->dma_rx_desc->callback_param = sport; 1325 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1326 dma_async_issue_pending(chan); 1327 1328 if (lpuart_is_32(sport)) { 1329 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); 1330 1331 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); 1332 } else { 1333 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1334 sport->port.membase + UARTCR5); 1335 } 1336 1337 return 0; 1338 } 1339 1340 static void lpuart_dma_rx_free(struct uart_port *port) 1341 { 1342 struct lpuart_port *sport = container_of(port, 1343 struct lpuart_port, port); 1344 struct dma_chan *chan = sport->dma_rx_chan; 1345 1346 dmaengine_terminate_all(chan); 1347 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1348 kfree(sport->rx_ring.buf); 1349 sport->rx_ring.tail = 0; 1350 sport->rx_ring.head = 0; 1351 sport->dma_rx_desc = NULL; 1352 sport->dma_rx_cookie = -EINVAL; 1353 } 1354 1355 static int lpuart_config_rs485(struct uart_port *port, 1356 struct serial_rs485 *rs485) 1357 { 1358 struct lpuart_port *sport = container_of(port, 1359 struct lpuart_port, port); 1360 1361 u8 modem = readb(sport->port.membase + UARTMODEM) & 1362 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1363 writeb(modem, sport->port.membase + UARTMODEM); 1364 1365 /* clear unsupported configurations */ 1366 rs485->delay_rts_before_send = 0; 1367 rs485->delay_rts_after_send = 0; 1368 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1369 1370 if (rs485->flags & SER_RS485_ENABLED) { 1371 /* Enable auto RS-485 RTS mode */ 1372 modem |= UARTMODEM_TXRTSE; 1373 1374 /* 1375 * RTS needs to be logic HIGH either during transfer _or_ after 1376 * transfer, other variants are not supported by the hardware. 1377 */ 1378 1379 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1380 SER_RS485_RTS_AFTER_SEND))) 1381 rs485->flags |= SER_RS485_RTS_ON_SEND; 1382 1383 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1384 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1385 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1386 1387 /* 1388 * The hardware defaults to RTS logic HIGH while transfer. 1389 * Switch polarity in case RTS shall be logic HIGH 1390 * after transfer. 1391 * Note: UART is assumed to be active high. 1392 */ 1393 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1394 modem &= ~UARTMODEM_TXRTSPOL; 1395 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1396 modem |= UARTMODEM_TXRTSPOL; 1397 } 1398 1399 /* Store the new configuration */ 1400 sport->port.rs485 = *rs485; 1401 1402 writeb(modem, sport->port.membase + UARTMODEM); 1403 return 0; 1404 } 1405 1406 static int lpuart32_config_rs485(struct uart_port *port, 1407 struct serial_rs485 *rs485) 1408 { 1409 struct lpuart_port *sport = container_of(port, 1410 struct lpuart_port, port); 1411 1412 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) 1413 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1414 lpuart32_write(&sport->port, modem, UARTMODIR); 1415 1416 /* clear unsupported configurations */ 1417 rs485->delay_rts_before_send = 0; 1418 rs485->delay_rts_after_send = 0; 1419 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1420 1421 if (rs485->flags & SER_RS485_ENABLED) { 1422 /* Enable auto RS-485 RTS mode */ 1423 modem |= UARTMODEM_TXRTSE; 1424 1425 /* 1426 * RTS needs to be logic HIGH either during transfer _or_ after 1427 * transfer, other variants are not supported by the hardware. 1428 */ 1429 1430 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1431 SER_RS485_RTS_AFTER_SEND))) 1432 rs485->flags |= SER_RS485_RTS_ON_SEND; 1433 1434 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1435 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1436 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1437 1438 /* 1439 * The hardware defaults to RTS logic HIGH while transfer. 1440 * Switch polarity in case RTS shall be logic HIGH 1441 * after transfer. 1442 * Note: UART is assumed to be active high. 1443 */ 1444 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1445 modem &= ~UARTMODEM_TXRTSPOL; 1446 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1447 modem |= UARTMODEM_TXRTSPOL; 1448 } 1449 1450 /* Store the new configuration */ 1451 sport->port.rs485 = *rs485; 1452 1453 lpuart32_write(&sport->port, modem, UARTMODIR); 1454 return 0; 1455 } 1456 1457 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1458 { 1459 unsigned int mctrl = 0; 1460 u8 reg; 1461 1462 reg = readb(port->membase + UARTCR1); 1463 if (reg & UARTCR1_LOOPS) 1464 mctrl |= TIOCM_LOOP; 1465 1466 return mctrl; 1467 } 1468 1469 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1470 { 1471 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 1472 u32 reg; 1473 1474 reg = lpuart32_read(port, UARTCTRL); 1475 if (reg & UARTCTRL_LOOPS) 1476 mctrl |= TIOCM_LOOP; 1477 1478 return mctrl; 1479 } 1480 1481 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1482 { 1483 u8 reg; 1484 1485 reg = readb(port->membase + UARTCR1); 1486 1487 /* for internal loopback we need LOOPS=1 and RSRC=0 */ 1488 reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC); 1489 if (mctrl & TIOCM_LOOP) 1490 reg |= UARTCR1_LOOPS; 1491 1492 writeb(reg, port->membase + UARTCR1); 1493 } 1494 1495 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1496 { 1497 u32 reg; 1498 1499 reg = lpuart32_read(port, UARTCTRL); 1500 1501 /* for internal loopback we need LOOPS=1 and RSRC=0 */ 1502 reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC); 1503 if (mctrl & TIOCM_LOOP) 1504 reg |= UARTCTRL_LOOPS; 1505 1506 lpuart32_write(port, reg, UARTCTRL); 1507 } 1508 1509 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1510 { 1511 unsigned char temp; 1512 1513 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1514 1515 if (break_state != 0) 1516 temp |= UARTCR2_SBK; 1517 1518 writeb(temp, port->membase + UARTCR2); 1519 } 1520 1521 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1522 { 1523 unsigned long temp; 1524 1525 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; 1526 1527 if (break_state != 0) 1528 temp |= UARTCTRL_SBK; 1529 1530 lpuart32_write(port, temp, UARTCTRL); 1531 } 1532 1533 static void lpuart_setup_watermark(struct lpuart_port *sport) 1534 { 1535 unsigned char val, cr2; 1536 unsigned char cr2_saved; 1537 1538 cr2 = readb(sport->port.membase + UARTCR2); 1539 cr2_saved = cr2; 1540 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1541 UARTCR2_RIE | UARTCR2_RE); 1542 writeb(cr2, sport->port.membase + UARTCR2); 1543 1544 val = readb(sport->port.membase + UARTPFIFO); 1545 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1546 sport->port.membase + UARTPFIFO); 1547 1548 /* flush Tx and Rx FIFO */ 1549 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1550 sport->port.membase + UARTCFIFO); 1551 1552 /* explicitly clear RDRF */ 1553 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1554 readb(sport->port.membase + UARTDR); 1555 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1556 } 1557 1558 writeb(0, sport->port.membase + UARTTWFIFO); 1559 writeb(1, sport->port.membase + UARTRWFIFO); 1560 1561 /* Restore cr2 */ 1562 writeb(cr2_saved, sport->port.membase + UARTCR2); 1563 } 1564 1565 static void lpuart_setup_watermark_enable(struct lpuart_port *sport) 1566 { 1567 unsigned char cr2; 1568 1569 lpuart_setup_watermark(sport); 1570 1571 cr2 = readb(sport->port.membase + UARTCR2); 1572 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE; 1573 writeb(cr2, sport->port.membase + UARTCR2); 1574 } 1575 1576 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1577 { 1578 unsigned long val, ctrl; 1579 unsigned long ctrl_saved; 1580 1581 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1582 ctrl_saved = ctrl; 1583 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1584 UARTCTRL_RIE | UARTCTRL_RE); 1585 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1586 1587 /* enable FIFO mode */ 1588 val = lpuart32_read(&sport->port, UARTFIFO); 1589 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1590 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1591 lpuart32_write(&sport->port, val, UARTFIFO); 1592 1593 /* set the watermark */ 1594 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1595 lpuart32_write(&sport->port, val, UARTWATER); 1596 1597 /* Restore cr2 */ 1598 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1599 } 1600 1601 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) 1602 { 1603 u32 temp; 1604 1605 lpuart32_setup_watermark(sport); 1606 1607 temp = lpuart32_read(&sport->port, UARTCTRL); 1608 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE; 1609 lpuart32_write(&sport->port, temp, UARTCTRL); 1610 } 1611 1612 static void rx_dma_timer_init(struct lpuart_port *sport) 1613 { 1614 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); 1615 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1616 add_timer(&sport->lpuart_timer); 1617 } 1618 1619 static void lpuart_request_dma(struct lpuart_port *sport) 1620 { 1621 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); 1622 if (IS_ERR(sport->dma_tx_chan)) { 1623 dev_dbg_once(sport->port.dev, 1624 "DMA tx channel request failed, operating without tx DMA (%ld)\n", 1625 PTR_ERR(sport->dma_tx_chan)); 1626 sport->dma_tx_chan = NULL; 1627 } 1628 1629 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); 1630 if (IS_ERR(sport->dma_rx_chan)) { 1631 dev_dbg_once(sport->port.dev, 1632 "DMA rx channel request failed, operating without rx DMA (%ld)\n", 1633 PTR_ERR(sport->dma_rx_chan)); 1634 sport->dma_rx_chan = NULL; 1635 } 1636 } 1637 1638 static void lpuart_tx_dma_startup(struct lpuart_port *sport) 1639 { 1640 u32 uartbaud; 1641 int ret; 1642 1643 if (uart_console(&sport->port)) 1644 goto err; 1645 1646 if (!sport->dma_tx_chan) 1647 goto err; 1648 1649 ret = lpuart_dma_tx_request(&sport->port); 1650 if (ret) 1651 goto err; 1652 1653 init_waitqueue_head(&sport->dma_wait); 1654 sport->lpuart_dma_tx_use = true; 1655 if (lpuart_is_32(sport)) { 1656 uartbaud = lpuart32_read(&sport->port, UARTBAUD); 1657 lpuart32_write(&sport->port, 1658 uartbaud | UARTBAUD_TDMAE, UARTBAUD); 1659 } else { 1660 writeb(readb(sport->port.membase + UARTCR5) | 1661 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 1662 } 1663 1664 return; 1665 1666 err: 1667 sport->lpuart_dma_tx_use = false; 1668 } 1669 1670 static void lpuart_rx_dma_startup(struct lpuart_port *sport) 1671 { 1672 int ret; 1673 unsigned char cr3; 1674 1675 if (uart_console(&sport->port)) 1676 goto err; 1677 1678 if (!sport->dma_rx_chan) 1679 goto err; 1680 1681 ret = lpuart_start_rx_dma(sport); 1682 if (ret) 1683 goto err; 1684 1685 /* set Rx DMA timeout */ 1686 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1687 if (!sport->dma_rx_timeout) 1688 sport->dma_rx_timeout = 1; 1689 1690 sport->lpuart_dma_rx_use = true; 1691 rx_dma_timer_init(sport); 1692 1693 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { 1694 cr3 = readb(sport->port.membase + UARTCR3); 1695 cr3 |= UARTCR3_FEIE; 1696 writeb(cr3, sport->port.membase + UARTCR3); 1697 } 1698 1699 return; 1700 1701 err: 1702 sport->lpuart_dma_rx_use = false; 1703 } 1704 1705 static int lpuart_startup(struct uart_port *port) 1706 { 1707 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1708 unsigned long flags; 1709 unsigned char temp; 1710 1711 /* determine FIFO size and enable FIFO mode */ 1712 temp = readb(sport->port.membase + UARTPFIFO); 1713 1714 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & 1715 UARTPFIFO_FIFOSIZE_MASK); 1716 sport->port.fifosize = sport->txfifo_size; 1717 1718 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & 1719 UARTPFIFO_FIFOSIZE_MASK); 1720 1721 lpuart_request_dma(sport); 1722 1723 spin_lock_irqsave(&sport->port.lock, flags); 1724 1725 lpuart_setup_watermark_enable(sport); 1726 1727 lpuart_rx_dma_startup(sport); 1728 lpuart_tx_dma_startup(sport); 1729 1730 spin_unlock_irqrestore(&sport->port.lock, flags); 1731 1732 return 0; 1733 } 1734 1735 static void lpuart32_configure(struct lpuart_port *sport) 1736 { 1737 unsigned long temp; 1738 1739 if (sport->lpuart_dma_rx_use) { 1740 /* RXWATER must be 0 */ 1741 temp = lpuart32_read(&sport->port, UARTWATER); 1742 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF); 1743 lpuart32_write(&sport->port, temp, UARTWATER); 1744 } 1745 temp = lpuart32_read(&sport->port, UARTCTRL); 1746 if (!sport->lpuart_dma_rx_use) 1747 temp |= UARTCTRL_RIE; 1748 if (!sport->lpuart_dma_tx_use) 1749 temp |= UARTCTRL_TIE; 1750 lpuart32_write(&sport->port, temp, UARTCTRL); 1751 } 1752 1753 static int lpuart32_startup(struct uart_port *port) 1754 { 1755 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1756 unsigned long flags; 1757 unsigned long temp; 1758 1759 /* determine FIFO size */ 1760 temp = lpuart32_read(&sport->port, UARTFIFO); 1761 1762 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & 1763 UARTFIFO_FIFOSIZE_MASK); 1764 sport->port.fifosize = sport->txfifo_size; 1765 1766 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & 1767 UARTFIFO_FIFOSIZE_MASK); 1768 1769 /* 1770 * The LS1021A and LS1028A have a fixed FIFO depth of 16 words. 1771 * Although they support the RX/TXSIZE fields, their encoding is 1772 * different. Eg the reference manual states 0b101 is 16 words. 1773 */ 1774 if (is_layerscape_lpuart(sport)) { 1775 sport->rxfifo_size = 16; 1776 sport->txfifo_size = 16; 1777 sport->port.fifosize = sport->txfifo_size; 1778 } 1779 1780 lpuart_request_dma(sport); 1781 1782 spin_lock_irqsave(&sport->port.lock, flags); 1783 1784 lpuart32_setup_watermark_enable(sport); 1785 1786 lpuart_rx_dma_startup(sport); 1787 lpuart_tx_dma_startup(sport); 1788 1789 lpuart32_configure(sport); 1790 1791 spin_unlock_irqrestore(&sport->port.lock, flags); 1792 return 0; 1793 } 1794 1795 static void lpuart_dma_shutdown(struct lpuart_port *sport) 1796 { 1797 if (sport->lpuart_dma_rx_use) { 1798 del_timer_sync(&sport->lpuart_timer); 1799 lpuart_dma_rx_free(&sport->port); 1800 } 1801 1802 if (sport->lpuart_dma_tx_use) { 1803 if (wait_event_interruptible_timeout(sport->dma_wait, 1804 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { 1805 sport->dma_tx_in_progress = false; 1806 dmaengine_terminate_all(sport->dma_tx_chan); 1807 } 1808 } 1809 1810 if (sport->dma_tx_chan) 1811 dma_release_channel(sport->dma_tx_chan); 1812 if (sport->dma_rx_chan) 1813 dma_release_channel(sport->dma_rx_chan); 1814 } 1815 1816 static void lpuart_shutdown(struct uart_port *port) 1817 { 1818 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1819 unsigned char temp; 1820 unsigned long flags; 1821 1822 spin_lock_irqsave(&port->lock, flags); 1823 1824 /* disable Rx/Tx and interrupts */ 1825 temp = readb(port->membase + UARTCR2); 1826 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1827 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1828 writeb(temp, port->membase + UARTCR2); 1829 1830 spin_unlock_irqrestore(&port->lock, flags); 1831 1832 lpuart_dma_shutdown(sport); 1833 } 1834 1835 static void lpuart32_shutdown(struct uart_port *port) 1836 { 1837 struct lpuart_port *sport = 1838 container_of(port, struct lpuart_port, port); 1839 unsigned long temp; 1840 unsigned long flags; 1841 1842 spin_lock_irqsave(&port->lock, flags); 1843 1844 /* disable Rx/Tx and interrupts */ 1845 temp = lpuart32_read(port, UARTCTRL); 1846 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1847 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1848 lpuart32_write(port, temp, UARTCTRL); 1849 1850 spin_unlock_irqrestore(&port->lock, flags); 1851 1852 lpuart_dma_shutdown(sport); 1853 } 1854 1855 static void 1856 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1857 struct ktermios *old) 1858 { 1859 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1860 unsigned long flags; 1861 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1862 unsigned int baud; 1863 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1864 unsigned int sbr, brfa; 1865 1866 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1867 old_cr2 = readb(sport->port.membase + UARTCR2); 1868 cr3 = readb(sport->port.membase + UARTCR3); 1869 cr4 = readb(sport->port.membase + UARTCR4); 1870 bdh = readb(sport->port.membase + UARTBDH); 1871 modem = readb(sport->port.membase + UARTMODEM); 1872 /* 1873 * only support CS8 and CS7, and for CS7 must enable PE. 1874 * supported mode: 1875 * - (7,e/o,1) 1876 * - (8,n,1) 1877 * - (8,m/s,1) 1878 * - (8,e/o,1) 1879 */ 1880 while ((termios->c_cflag & CSIZE) != CS8 && 1881 (termios->c_cflag & CSIZE) != CS7) { 1882 termios->c_cflag &= ~CSIZE; 1883 termios->c_cflag |= old_csize; 1884 old_csize = CS8; 1885 } 1886 1887 if ((termios->c_cflag & CSIZE) == CS8 || 1888 (termios->c_cflag & CSIZE) == CS7) 1889 cr1 = old_cr1 & ~UARTCR1_M; 1890 1891 if (termios->c_cflag & CMSPAR) { 1892 if ((termios->c_cflag & CSIZE) != CS8) { 1893 termios->c_cflag &= ~CSIZE; 1894 termios->c_cflag |= CS8; 1895 } 1896 cr1 |= UARTCR1_M; 1897 } 1898 1899 /* 1900 * When auto RS-485 RTS mode is enabled, 1901 * hardware flow control need to be disabled. 1902 */ 1903 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1904 termios->c_cflag &= ~CRTSCTS; 1905 1906 if (termios->c_cflag & CRTSCTS) 1907 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE; 1908 else 1909 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1910 1911 termios->c_cflag &= ~CSTOPB; 1912 1913 /* parity must be enabled when CS7 to match 8-bits format */ 1914 if ((termios->c_cflag & CSIZE) == CS7) 1915 termios->c_cflag |= PARENB; 1916 1917 if (termios->c_cflag & PARENB) { 1918 if (termios->c_cflag & CMSPAR) { 1919 cr1 &= ~UARTCR1_PE; 1920 if (termios->c_cflag & PARODD) 1921 cr3 |= UARTCR3_T8; 1922 else 1923 cr3 &= ~UARTCR3_T8; 1924 } else { 1925 cr1 |= UARTCR1_PE; 1926 if ((termios->c_cflag & CSIZE) == CS8) 1927 cr1 |= UARTCR1_M; 1928 if (termios->c_cflag & PARODD) 1929 cr1 |= UARTCR1_PT; 1930 else 1931 cr1 &= ~UARTCR1_PT; 1932 } 1933 } else { 1934 cr1 &= ~UARTCR1_PE; 1935 } 1936 1937 /* ask the core to calculate the divisor */ 1938 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1939 1940 /* 1941 * Need to update the Ring buffer length according to the selected 1942 * baud rate and restart Rx DMA path. 1943 * 1944 * Since timer function acqures sport->port.lock, need to stop before 1945 * acquring same lock because otherwise del_timer_sync() can deadlock. 1946 */ 1947 if (old && sport->lpuart_dma_rx_use) { 1948 del_timer_sync(&sport->lpuart_timer); 1949 lpuart_dma_rx_free(&sport->port); 1950 } 1951 1952 spin_lock_irqsave(&sport->port.lock, flags); 1953 1954 sport->port.read_status_mask = 0; 1955 if (termios->c_iflag & INPCK) 1956 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; 1957 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1958 sport->port.read_status_mask |= UARTSR1_FE; 1959 1960 /* characters to ignore */ 1961 sport->port.ignore_status_mask = 0; 1962 if (termios->c_iflag & IGNPAR) 1963 sport->port.ignore_status_mask |= UARTSR1_PE; 1964 if (termios->c_iflag & IGNBRK) { 1965 sport->port.ignore_status_mask |= UARTSR1_FE; 1966 /* 1967 * if we're ignoring parity and break indicators, 1968 * ignore overruns too (for real raw support). 1969 */ 1970 if (termios->c_iflag & IGNPAR) 1971 sport->port.ignore_status_mask |= UARTSR1_OR; 1972 } 1973 1974 /* update the per-port timeout */ 1975 uart_update_timeout(port, termios->c_cflag, baud); 1976 1977 /* wait transmit engin complete */ 1978 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 1979 1980 /* disable transmit and receive */ 1981 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1982 sport->port.membase + UARTCR2); 1983 1984 sbr = sport->port.uartclk / (16 * baud); 1985 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1986 bdh &= ~UARTBDH_SBR_MASK; 1987 bdh |= (sbr >> 8) & 0x1F; 1988 cr4 &= ~UARTCR4_BRFA_MASK; 1989 brfa &= UARTCR4_BRFA_MASK; 1990 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1991 writeb(bdh, sport->port.membase + UARTBDH); 1992 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1993 writeb(cr3, sport->port.membase + UARTCR3); 1994 writeb(cr1, sport->port.membase + UARTCR1); 1995 writeb(modem, sport->port.membase + UARTMODEM); 1996 1997 /* restore control register */ 1998 writeb(old_cr2, sport->port.membase + UARTCR2); 1999 2000 if (old && sport->lpuart_dma_rx_use) { 2001 if (!lpuart_start_rx_dma(sport)) 2002 rx_dma_timer_init(sport); 2003 else 2004 sport->lpuart_dma_rx_use = false; 2005 } 2006 2007 spin_unlock_irqrestore(&sport->port.lock, flags); 2008 } 2009 2010 static void __lpuart32_serial_setbrg(struct uart_port *port, 2011 unsigned int baudrate, bool use_rx_dma, 2012 bool use_tx_dma) 2013 { 2014 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; 2015 u32 clk = port->uartclk; 2016 2017 /* 2018 * The idea is to use the best OSR (over-sampling rate) possible. 2019 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 2020 * Loop to find the best OSR value possible, one that generates minimum 2021 * baud_diff iterate through the rest of the supported values of OSR. 2022 * 2023 * Calculation Formula: 2024 * Baud Rate = baud clock / ((OSR+1) × SBR) 2025 */ 2026 baud_diff = baudrate; 2027 osr = 0; 2028 sbr = 0; 2029 2030 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 2031 /* calculate the temporary sbr value */ 2032 tmp_sbr = (clk / (baudrate * tmp_osr)); 2033 if (tmp_sbr == 0) 2034 tmp_sbr = 1; 2035 2036 /* 2037 * calculate the baud rate difference based on the temporary 2038 * osr and sbr values 2039 */ 2040 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 2041 2042 /* select best values between sbr and sbr+1 */ 2043 tmp = clk / (tmp_osr * (tmp_sbr + 1)); 2044 if (tmp_diff > (baudrate - tmp)) { 2045 tmp_diff = baudrate - tmp; 2046 tmp_sbr++; 2047 } 2048 2049 if (tmp_sbr > UARTBAUD_SBR_MASK) 2050 continue; 2051 2052 if (tmp_diff <= baud_diff) { 2053 baud_diff = tmp_diff; 2054 osr = tmp_osr; 2055 sbr = tmp_sbr; 2056 2057 if (!baud_diff) 2058 break; 2059 } 2060 } 2061 2062 /* handle buadrate outside acceptable rate */ 2063 if (baud_diff > ((baudrate / 100) * 3)) 2064 dev_warn(port->dev, 2065 "unacceptable baud rate difference of more than 3%%\n"); 2066 2067 tmp = lpuart32_read(port, UARTBAUD); 2068 2069 if ((osr > 3) && (osr < 8)) 2070 tmp |= UARTBAUD_BOTHEDGE; 2071 2072 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 2073 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; 2074 2075 tmp &= ~UARTBAUD_SBR_MASK; 2076 tmp |= sbr & UARTBAUD_SBR_MASK; 2077 2078 if (!use_rx_dma) 2079 tmp &= ~UARTBAUD_RDMAE; 2080 if (!use_tx_dma) 2081 tmp &= ~UARTBAUD_TDMAE; 2082 2083 lpuart32_write(port, tmp, UARTBAUD); 2084 } 2085 2086 static void lpuart32_serial_setbrg(struct lpuart_port *sport, 2087 unsigned int baudrate) 2088 { 2089 __lpuart32_serial_setbrg(&sport->port, baudrate, 2090 sport->lpuart_dma_rx_use, 2091 sport->lpuart_dma_tx_use); 2092 } 2093 2094 2095 static void 2096 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 2097 struct ktermios *old) 2098 { 2099 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 2100 unsigned long flags; 2101 unsigned long ctrl, old_ctrl, bd, modem; 2102 unsigned int baud; 2103 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 2104 2105 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); 2106 bd = lpuart32_read(&sport->port, UARTBAUD); 2107 modem = lpuart32_read(&sport->port, UARTMODIR); 2108 /* 2109 * only support CS8 and CS7, and for CS7 must enable PE. 2110 * supported mode: 2111 * - (7,e/o,1) 2112 * - (8,n,1) 2113 * - (8,m/s,1) 2114 * - (8,e/o,1) 2115 */ 2116 while ((termios->c_cflag & CSIZE) != CS8 && 2117 (termios->c_cflag & CSIZE) != CS7) { 2118 termios->c_cflag &= ~CSIZE; 2119 termios->c_cflag |= old_csize; 2120 old_csize = CS8; 2121 } 2122 2123 if ((termios->c_cflag & CSIZE) == CS8 || 2124 (termios->c_cflag & CSIZE) == CS7) 2125 ctrl = old_ctrl & ~UARTCTRL_M; 2126 2127 if (termios->c_cflag & CMSPAR) { 2128 if ((termios->c_cflag & CSIZE) != CS8) { 2129 termios->c_cflag &= ~CSIZE; 2130 termios->c_cflag |= CS8; 2131 } 2132 ctrl |= UARTCTRL_M; 2133 } 2134 2135 /* 2136 * When auto RS-485 RTS mode is enabled, 2137 * hardware flow control need to be disabled. 2138 */ 2139 if (sport->port.rs485.flags & SER_RS485_ENABLED) 2140 termios->c_cflag &= ~CRTSCTS; 2141 2142 if (termios->c_cflag & CRTSCTS) { 2143 modem |= (UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 2144 } else { 2145 termios->c_cflag &= ~CRTSCTS; 2146 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 2147 } 2148 2149 if (termios->c_cflag & CSTOPB) 2150 bd |= UARTBAUD_SBNS; 2151 else 2152 bd &= ~UARTBAUD_SBNS; 2153 2154 /* parity must be enabled when CS7 to match 8-bits format */ 2155 if ((termios->c_cflag & CSIZE) == CS7) 2156 termios->c_cflag |= PARENB; 2157 2158 if ((termios->c_cflag & PARENB)) { 2159 if (termios->c_cflag & CMSPAR) { 2160 ctrl &= ~UARTCTRL_PE; 2161 ctrl |= UARTCTRL_M; 2162 } else { 2163 ctrl |= UARTCTRL_PE; 2164 if ((termios->c_cflag & CSIZE) == CS8) 2165 ctrl |= UARTCTRL_M; 2166 if (termios->c_cflag & PARODD) 2167 ctrl |= UARTCTRL_PT; 2168 else 2169 ctrl &= ~UARTCTRL_PT; 2170 } 2171 } else { 2172 ctrl &= ~UARTCTRL_PE; 2173 } 2174 2175 /* ask the core to calculate the divisor */ 2176 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); 2177 2178 /* 2179 * Need to update the Ring buffer length according to the selected 2180 * baud rate and restart Rx DMA path. 2181 * 2182 * Since timer function acqures sport->port.lock, need to stop before 2183 * acquring same lock because otherwise del_timer_sync() can deadlock. 2184 */ 2185 if (old && sport->lpuart_dma_rx_use) { 2186 del_timer_sync(&sport->lpuart_timer); 2187 lpuart_dma_rx_free(&sport->port); 2188 } 2189 2190 spin_lock_irqsave(&sport->port.lock, flags); 2191 2192 sport->port.read_status_mask = 0; 2193 if (termios->c_iflag & INPCK) 2194 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; 2195 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2196 sport->port.read_status_mask |= UARTSTAT_FE; 2197 2198 /* characters to ignore */ 2199 sport->port.ignore_status_mask = 0; 2200 if (termios->c_iflag & IGNPAR) 2201 sport->port.ignore_status_mask |= UARTSTAT_PE; 2202 if (termios->c_iflag & IGNBRK) { 2203 sport->port.ignore_status_mask |= UARTSTAT_FE; 2204 /* 2205 * if we're ignoring parity and break indicators, 2206 * ignore overruns too (for real raw support). 2207 */ 2208 if (termios->c_iflag & IGNPAR) 2209 sport->port.ignore_status_mask |= UARTSTAT_OR; 2210 } 2211 2212 /* update the per-port timeout */ 2213 uart_update_timeout(port, termios->c_cflag, baud); 2214 2215 /* wait transmit engin complete */ 2216 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2217 2218 /* disable transmit and receive */ 2219 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 2220 UARTCTRL); 2221 2222 lpuart32_write(&sport->port, bd, UARTBAUD); 2223 lpuart32_serial_setbrg(sport, baud); 2224 lpuart32_write(&sport->port, modem, UARTMODIR); 2225 lpuart32_write(&sport->port, ctrl, UARTCTRL); 2226 /* restore control register */ 2227 2228 if (old && sport->lpuart_dma_rx_use) { 2229 if (!lpuart_start_rx_dma(sport)) 2230 rx_dma_timer_init(sport); 2231 else 2232 sport->lpuart_dma_rx_use = false; 2233 } 2234 2235 spin_unlock_irqrestore(&sport->port.lock, flags); 2236 } 2237 2238 static const char *lpuart_type(struct uart_port *port) 2239 { 2240 return "FSL_LPUART"; 2241 } 2242 2243 static void lpuart_release_port(struct uart_port *port) 2244 { 2245 /* nothing to do */ 2246 } 2247 2248 static int lpuart_request_port(struct uart_port *port) 2249 { 2250 return 0; 2251 } 2252 2253 /* configure/autoconfigure the port */ 2254 static void lpuart_config_port(struct uart_port *port, int flags) 2255 { 2256 if (flags & UART_CONFIG_TYPE) 2257 port->type = PORT_LPUART; 2258 } 2259 2260 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 2261 { 2262 int ret = 0; 2263 2264 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 2265 ret = -EINVAL; 2266 if (port->irq != ser->irq) 2267 ret = -EINVAL; 2268 if (ser->io_type != UPIO_MEM) 2269 ret = -EINVAL; 2270 if (port->uartclk / 16 != ser->baud_base) 2271 ret = -EINVAL; 2272 if (port->iobase != ser->port) 2273 ret = -EINVAL; 2274 if (ser->hub6 != 0) 2275 ret = -EINVAL; 2276 return ret; 2277 } 2278 2279 static const struct uart_ops lpuart_pops = { 2280 .tx_empty = lpuart_tx_empty, 2281 .set_mctrl = lpuart_set_mctrl, 2282 .get_mctrl = lpuart_get_mctrl, 2283 .stop_tx = lpuart_stop_tx, 2284 .start_tx = lpuart_start_tx, 2285 .stop_rx = lpuart_stop_rx, 2286 .break_ctl = lpuart_break_ctl, 2287 .startup = lpuart_startup, 2288 .shutdown = lpuart_shutdown, 2289 .set_termios = lpuart_set_termios, 2290 .type = lpuart_type, 2291 .request_port = lpuart_request_port, 2292 .release_port = lpuart_release_port, 2293 .config_port = lpuart_config_port, 2294 .verify_port = lpuart_verify_port, 2295 .flush_buffer = lpuart_flush_buffer, 2296 #if defined(CONFIG_CONSOLE_POLL) 2297 .poll_init = lpuart_poll_init, 2298 .poll_get_char = lpuart_poll_get_char, 2299 .poll_put_char = lpuart_poll_put_char, 2300 #endif 2301 }; 2302 2303 static const struct uart_ops lpuart32_pops = { 2304 .tx_empty = lpuart32_tx_empty, 2305 .set_mctrl = lpuart32_set_mctrl, 2306 .get_mctrl = lpuart32_get_mctrl, 2307 .stop_tx = lpuart32_stop_tx, 2308 .start_tx = lpuart32_start_tx, 2309 .stop_rx = lpuart32_stop_rx, 2310 .break_ctl = lpuart32_break_ctl, 2311 .startup = lpuart32_startup, 2312 .shutdown = lpuart32_shutdown, 2313 .set_termios = lpuart32_set_termios, 2314 .type = lpuart_type, 2315 .request_port = lpuart_request_port, 2316 .release_port = lpuart_release_port, 2317 .config_port = lpuart_config_port, 2318 .verify_port = lpuart_verify_port, 2319 .flush_buffer = lpuart_flush_buffer, 2320 #if defined(CONFIG_CONSOLE_POLL) 2321 .poll_init = lpuart32_poll_init, 2322 .poll_get_char = lpuart32_poll_get_char, 2323 .poll_put_char = lpuart32_poll_put_char, 2324 #endif 2325 }; 2326 2327 static struct lpuart_port *lpuart_ports[UART_NR]; 2328 2329 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 2330 static void lpuart_console_putchar(struct uart_port *port, int ch) 2331 { 2332 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 2333 writeb(ch, port->membase + UARTDR); 2334 } 2335 2336 static void lpuart32_console_putchar(struct uart_port *port, int ch) 2337 { 2338 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 2339 lpuart32_write(port, ch, UARTDATA); 2340 } 2341 2342 static void 2343 lpuart_console_write(struct console *co, const char *s, unsigned int count) 2344 { 2345 struct lpuart_port *sport = lpuart_ports[co->index]; 2346 unsigned char old_cr2, cr2; 2347 unsigned long flags; 2348 int locked = 1; 2349 2350 if (oops_in_progress) 2351 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2352 else 2353 spin_lock_irqsave(&sport->port.lock, flags); 2354 2355 /* first save CR2 and then disable interrupts */ 2356 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 2357 cr2 |= UARTCR2_TE | UARTCR2_RE; 2358 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 2359 writeb(cr2, sport->port.membase + UARTCR2); 2360 2361 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 2362 2363 /* wait for transmitter finish complete and restore CR2 */ 2364 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 2365 2366 writeb(old_cr2, sport->port.membase + UARTCR2); 2367 2368 if (locked) 2369 spin_unlock_irqrestore(&sport->port.lock, flags); 2370 } 2371 2372 static void 2373 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 2374 { 2375 struct lpuart_port *sport = lpuart_ports[co->index]; 2376 unsigned long old_cr, cr; 2377 unsigned long flags; 2378 int locked = 1; 2379 2380 if (oops_in_progress) 2381 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2382 else 2383 spin_lock_irqsave(&sport->port.lock, flags); 2384 2385 /* first save CR2 and then disable interrupts */ 2386 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 2387 cr |= UARTCTRL_TE | UARTCTRL_RE; 2388 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 2389 lpuart32_write(&sport->port, cr, UARTCTRL); 2390 2391 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 2392 2393 /* wait for transmitter finish complete and restore CR2 */ 2394 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2395 2396 lpuart32_write(&sport->port, old_cr, UARTCTRL); 2397 2398 if (locked) 2399 spin_unlock_irqrestore(&sport->port.lock, flags); 2400 } 2401 2402 /* 2403 * if the port was already initialised (eg, by a boot loader), 2404 * try to determine the current setup. 2405 */ 2406 static void __init 2407 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 2408 int *parity, int *bits) 2409 { 2410 unsigned char cr, bdh, bdl, brfa; 2411 unsigned int sbr, uartclk, baud_raw; 2412 2413 cr = readb(sport->port.membase + UARTCR2); 2414 cr &= UARTCR2_TE | UARTCR2_RE; 2415 if (!cr) 2416 return; 2417 2418 /* ok, the port was enabled */ 2419 2420 cr = readb(sport->port.membase + UARTCR1); 2421 2422 *parity = 'n'; 2423 if (cr & UARTCR1_PE) { 2424 if (cr & UARTCR1_PT) 2425 *parity = 'o'; 2426 else 2427 *parity = 'e'; 2428 } 2429 2430 if (cr & UARTCR1_M) 2431 *bits = 9; 2432 else 2433 *bits = 8; 2434 2435 bdh = readb(sport->port.membase + UARTBDH); 2436 bdh &= UARTBDH_SBR_MASK; 2437 bdl = readb(sport->port.membase + UARTBDL); 2438 sbr = bdh; 2439 sbr <<= 8; 2440 sbr |= bdl; 2441 brfa = readb(sport->port.membase + UARTCR4); 2442 brfa &= UARTCR4_BRFA_MASK; 2443 2444 uartclk = lpuart_get_baud_clk_rate(sport); 2445 /* 2446 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2447 */ 2448 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 2449 2450 if (*baud != baud_raw) 2451 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2452 "from %d to %d\n", baud_raw, *baud); 2453 } 2454 2455 static void __init 2456 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 2457 int *parity, int *bits) 2458 { 2459 unsigned long cr, bd; 2460 unsigned int sbr, uartclk, baud_raw; 2461 2462 cr = lpuart32_read(&sport->port, UARTCTRL); 2463 cr &= UARTCTRL_TE | UARTCTRL_RE; 2464 if (!cr) 2465 return; 2466 2467 /* ok, the port was enabled */ 2468 2469 cr = lpuart32_read(&sport->port, UARTCTRL); 2470 2471 *parity = 'n'; 2472 if (cr & UARTCTRL_PE) { 2473 if (cr & UARTCTRL_PT) 2474 *parity = 'o'; 2475 else 2476 *parity = 'e'; 2477 } 2478 2479 if (cr & UARTCTRL_M) 2480 *bits = 9; 2481 else 2482 *bits = 8; 2483 2484 bd = lpuart32_read(&sport->port, UARTBAUD); 2485 bd &= UARTBAUD_SBR_MASK; 2486 if (!bd) 2487 return; 2488 2489 sbr = bd; 2490 uartclk = lpuart_get_baud_clk_rate(sport); 2491 /* 2492 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2493 */ 2494 baud_raw = uartclk / (16 * sbr); 2495 2496 if (*baud != baud_raw) 2497 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2498 "from %d to %d\n", baud_raw, *baud); 2499 } 2500 2501 static int __init lpuart_console_setup(struct console *co, char *options) 2502 { 2503 struct lpuart_port *sport; 2504 int baud = 115200; 2505 int bits = 8; 2506 int parity = 'n'; 2507 int flow = 'n'; 2508 2509 /* 2510 * check whether an invalid uart number has been specified, and 2511 * if so, search for the first available port that does have 2512 * console support. 2513 */ 2514 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2515 co->index = 0; 2516 2517 sport = lpuart_ports[co->index]; 2518 if (sport == NULL) 2519 return -ENODEV; 2520 2521 if (options) 2522 uart_parse_options(options, &baud, &parity, &bits, &flow); 2523 else 2524 if (lpuart_is_32(sport)) 2525 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2526 else 2527 lpuart_console_get_options(sport, &baud, &parity, &bits); 2528 2529 if (lpuart_is_32(sport)) 2530 lpuart32_setup_watermark(sport); 2531 else 2532 lpuart_setup_watermark(sport); 2533 2534 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2535 } 2536 2537 static struct uart_driver lpuart_reg; 2538 static struct console lpuart_console = { 2539 .name = DEV_NAME, 2540 .write = lpuart_console_write, 2541 .device = uart_console_device, 2542 .setup = lpuart_console_setup, 2543 .flags = CON_PRINTBUFFER, 2544 .index = -1, 2545 .data = &lpuart_reg, 2546 }; 2547 2548 static struct console lpuart32_console = { 2549 .name = DEV_NAME, 2550 .write = lpuart32_console_write, 2551 .device = uart_console_device, 2552 .setup = lpuart_console_setup, 2553 .flags = CON_PRINTBUFFER, 2554 .index = -1, 2555 .data = &lpuart_reg, 2556 }; 2557 2558 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2559 { 2560 struct earlycon_device *dev = con->data; 2561 2562 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2563 } 2564 2565 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2566 { 2567 struct earlycon_device *dev = con->data; 2568 2569 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2570 } 2571 2572 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2573 const char *opt) 2574 { 2575 if (!device->port.membase) 2576 return -ENODEV; 2577 2578 device->con->write = lpuart_early_write; 2579 return 0; 2580 } 2581 2582 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2583 const char *opt) 2584 { 2585 if (!device->port.membase) 2586 return -ENODEV; 2587 2588 if (device->port.iotype != UPIO_MEM32) 2589 device->port.iotype = UPIO_MEM32BE; 2590 2591 device->con->write = lpuart32_early_write; 2592 return 0; 2593 } 2594 2595 static int __init ls1028a_early_console_setup(struct earlycon_device *device, 2596 const char *opt) 2597 { 2598 u32 cr; 2599 2600 if (!device->port.membase) 2601 return -ENODEV; 2602 2603 device->port.iotype = UPIO_MEM32; 2604 device->con->write = lpuart32_early_write; 2605 2606 /* set the baudrate */ 2607 if (device->port.uartclk && device->baud) 2608 __lpuart32_serial_setbrg(&device->port, device->baud, 2609 false, false); 2610 2611 /* enable transmitter */ 2612 cr = lpuart32_read(&device->port, UARTCTRL); 2613 cr |= UARTCTRL_TE; 2614 lpuart32_write(&device->port, cr, UARTCTRL); 2615 2616 return 0; 2617 } 2618 2619 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2620 const char *opt) 2621 { 2622 if (!device->port.membase) 2623 return -ENODEV; 2624 2625 device->port.iotype = UPIO_MEM32; 2626 device->port.membase += IMX_REG_OFF; 2627 device->con->write = lpuart32_early_write; 2628 2629 return 0; 2630 } 2631 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2632 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2633 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup); 2634 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2635 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup); 2636 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup); 2637 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2638 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2639 2640 #define LPUART_CONSOLE (&lpuart_console) 2641 #define LPUART32_CONSOLE (&lpuart32_console) 2642 #else 2643 #define LPUART_CONSOLE NULL 2644 #define LPUART32_CONSOLE NULL 2645 #endif 2646 2647 static struct uart_driver lpuart_reg = { 2648 .owner = THIS_MODULE, 2649 .driver_name = DRIVER_NAME, 2650 .dev_name = DEV_NAME, 2651 .nr = ARRAY_SIZE(lpuart_ports), 2652 .cons = LPUART_CONSOLE, 2653 }; 2654 2655 static int lpuart_probe(struct platform_device *pdev) 2656 { 2657 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev); 2658 struct device_node *np = pdev->dev.of_node; 2659 struct lpuart_port *sport; 2660 struct resource *res; 2661 int ret; 2662 2663 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2664 if (!sport) 2665 return -ENOMEM; 2666 2667 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2668 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 2669 if (IS_ERR(sport->port.membase)) 2670 return PTR_ERR(sport->port.membase); 2671 2672 sport->port.membase += sdata->reg_off; 2673 sport->port.mapbase = res->start + sdata->reg_off; 2674 sport->port.dev = &pdev->dev; 2675 sport->port.type = PORT_LPUART; 2676 sport->devtype = sdata->devtype; 2677 ret = platform_get_irq(pdev, 0); 2678 if (ret < 0) 2679 return ret; 2680 sport->port.irq = ret; 2681 sport->port.iotype = sdata->iotype; 2682 if (lpuart_is_32(sport)) 2683 sport->port.ops = &lpuart32_pops; 2684 else 2685 sport->port.ops = &lpuart_pops; 2686 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); 2687 sport->port.flags = UPF_BOOT_AUTOCONF; 2688 2689 if (lpuart_is_32(sport)) 2690 sport->port.rs485_config = lpuart32_config_rs485; 2691 else 2692 sport->port.rs485_config = lpuart_config_rs485; 2693 2694 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 2695 if (IS_ERR(sport->ipg_clk)) { 2696 ret = PTR_ERR(sport->ipg_clk); 2697 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); 2698 return ret; 2699 } 2700 2701 sport->baud_clk = NULL; 2702 if (is_imx8qxp_lpuart(sport)) { 2703 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); 2704 if (IS_ERR(sport->baud_clk)) { 2705 ret = PTR_ERR(sport->baud_clk); 2706 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); 2707 return ret; 2708 } 2709 } 2710 2711 ret = of_alias_get_id(np, "serial"); 2712 if (ret < 0) { 2713 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL); 2714 if (ret < 0) { 2715 dev_err(&pdev->dev, "port line is full, add device failed\n"); 2716 return ret; 2717 } 2718 sport->id_allocated = true; 2719 } 2720 if (ret >= ARRAY_SIZE(lpuart_ports)) { 2721 dev_err(&pdev->dev, "serial%d out of range\n", ret); 2722 ret = -EINVAL; 2723 goto failed_out_of_range; 2724 } 2725 sport->port.line = ret; 2726 2727 ret = lpuart_enable_clks(sport); 2728 if (ret) 2729 goto failed_clock_enable; 2730 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); 2731 2732 lpuart_ports[sport->port.line] = sport; 2733 2734 platform_set_drvdata(pdev, &sport->port); 2735 2736 if (lpuart_is_32(sport)) { 2737 lpuart_reg.cons = LPUART32_CONSOLE; 2738 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0, 2739 DRIVER_NAME, sport); 2740 } else { 2741 lpuart_reg.cons = LPUART_CONSOLE; 2742 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0, 2743 DRIVER_NAME, sport); 2744 } 2745 2746 if (ret) 2747 goto failed_irq_request; 2748 2749 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2750 if (ret) 2751 goto failed_attach_port; 2752 2753 ret = lpuart_global_reset(sport); 2754 if (ret) 2755 goto failed_reset; 2756 2757 ret = uart_get_rs485_mode(&sport->port); 2758 if (ret) 2759 goto failed_get_rs485; 2760 2761 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX) 2762 dev_err(&pdev->dev, "driver doesn't support RX during TX\n"); 2763 2764 if (sport->port.rs485.delay_rts_before_send || 2765 sport->port.rs485.delay_rts_after_send) 2766 dev_err(&pdev->dev, "driver doesn't support RTS delays\n"); 2767 2768 sport->port.rs485_config(&sport->port, &sport->port.rs485); 2769 2770 return 0; 2771 2772 failed_get_rs485: 2773 failed_reset: 2774 uart_remove_one_port(&lpuart_reg, &sport->port); 2775 failed_attach_port: 2776 failed_irq_request: 2777 lpuart_disable_clks(sport); 2778 failed_clock_enable: 2779 failed_out_of_range: 2780 if (sport->id_allocated) 2781 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); 2782 return ret; 2783 } 2784 2785 static int lpuart_remove(struct platform_device *pdev) 2786 { 2787 struct lpuart_port *sport = platform_get_drvdata(pdev); 2788 2789 uart_remove_one_port(&lpuart_reg, &sport->port); 2790 2791 if (sport->id_allocated) 2792 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); 2793 2794 lpuart_disable_clks(sport); 2795 2796 if (sport->dma_tx_chan) 2797 dma_release_channel(sport->dma_tx_chan); 2798 2799 if (sport->dma_rx_chan) 2800 dma_release_channel(sport->dma_rx_chan); 2801 2802 return 0; 2803 } 2804 2805 static int __maybe_unused lpuart_suspend(struct device *dev) 2806 { 2807 struct lpuart_port *sport = dev_get_drvdata(dev); 2808 unsigned long temp; 2809 bool irq_wake; 2810 2811 if (lpuart_is_32(sport)) { 2812 /* disable Rx/Tx and interrupts */ 2813 temp = lpuart32_read(&sport->port, UARTCTRL); 2814 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2815 lpuart32_write(&sport->port, temp, UARTCTRL); 2816 } else { 2817 /* disable Rx/Tx and interrupts */ 2818 temp = readb(sport->port.membase + UARTCR2); 2819 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2820 writeb(temp, sport->port.membase + UARTCR2); 2821 } 2822 2823 uart_suspend_port(&lpuart_reg, &sport->port); 2824 2825 /* uart_suspend_port() might set wakeup flag */ 2826 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2827 2828 if (sport->lpuart_dma_rx_use) { 2829 /* 2830 * EDMA driver during suspend will forcefully release any 2831 * non-idle DMA channels. If port wakeup is enabled or if port 2832 * is console port or 'no_console_suspend' is set the Rx DMA 2833 * cannot resume as as expected, hence gracefully release the 2834 * Rx DMA path before suspend and start Rx DMA path on resume. 2835 */ 2836 if (irq_wake) { 2837 del_timer_sync(&sport->lpuart_timer); 2838 lpuart_dma_rx_free(&sport->port); 2839 } 2840 2841 /* Disable Rx DMA to use UART port as wakeup source */ 2842 if (lpuart_is_32(sport)) { 2843 temp = lpuart32_read(&sport->port, UARTBAUD); 2844 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, 2845 UARTBAUD); 2846 } else { 2847 writeb(readb(sport->port.membase + UARTCR5) & 2848 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 2849 } 2850 } 2851 2852 if (sport->lpuart_dma_tx_use) { 2853 sport->dma_tx_in_progress = false; 2854 dmaengine_terminate_all(sport->dma_tx_chan); 2855 } 2856 2857 if (sport->port.suspended && !irq_wake) 2858 lpuart_disable_clks(sport); 2859 2860 return 0; 2861 } 2862 2863 static int __maybe_unused lpuart_resume(struct device *dev) 2864 { 2865 struct lpuart_port *sport = dev_get_drvdata(dev); 2866 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2867 2868 if (sport->port.suspended && !irq_wake) 2869 lpuart_enable_clks(sport); 2870 2871 if (lpuart_is_32(sport)) 2872 lpuart32_setup_watermark_enable(sport); 2873 else 2874 lpuart_setup_watermark_enable(sport); 2875 2876 if (sport->lpuart_dma_rx_use) { 2877 if (irq_wake) { 2878 if (!lpuart_start_rx_dma(sport)) 2879 rx_dma_timer_init(sport); 2880 else 2881 sport->lpuart_dma_rx_use = false; 2882 } 2883 } 2884 2885 lpuart_tx_dma_startup(sport); 2886 2887 if (lpuart_is_32(sport)) 2888 lpuart32_configure(sport); 2889 2890 uart_resume_port(&lpuart_reg, &sport->port); 2891 2892 return 0; 2893 } 2894 2895 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2896 2897 static struct platform_driver lpuart_driver = { 2898 .probe = lpuart_probe, 2899 .remove = lpuart_remove, 2900 .driver = { 2901 .name = "fsl-lpuart", 2902 .of_match_table = lpuart_dt_ids, 2903 .pm = &lpuart_pm_ops, 2904 }, 2905 }; 2906 2907 static int __init lpuart_serial_init(void) 2908 { 2909 int ret = uart_register_driver(&lpuart_reg); 2910 2911 if (ret) 2912 return ret; 2913 2914 ret = platform_driver_register(&lpuart_driver); 2915 if (ret) 2916 uart_unregister_driver(&lpuart_reg); 2917 2918 return ret; 2919 } 2920 2921 static void __exit lpuart_serial_exit(void) 2922 { 2923 ida_destroy(&fsl_lpuart_ida); 2924 platform_driver_unregister(&lpuart_driver); 2925 uart_unregister_driver(&lpuart_reg); 2926 } 2927 2928 module_init(lpuart_serial_init); 2929 module_exit(lpuart_serial_exit); 2930 2931 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2932 MODULE_LICENSE("GPL v2"); 2933