1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale lpuart serial port driver 4 * 5 * Copyright 2012-2014 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/console.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/dmapool.h> 14 #include <linux/io.h> 15 #include <linux/irq.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/of_dma.h> 20 #include <linux/serial_core.h> 21 #include <linux/slab.h> 22 #include <linux/tty_flip.h> 23 24 /* All registers are 8-bit width */ 25 #define UARTBDH 0x00 26 #define UARTBDL 0x01 27 #define UARTCR1 0x02 28 #define UARTCR2 0x03 29 #define UARTSR1 0x04 30 #define UARTCR3 0x06 31 #define UARTDR 0x07 32 #define UARTCR4 0x0a 33 #define UARTCR5 0x0b 34 #define UARTMODEM 0x0d 35 #define UARTPFIFO 0x10 36 #define UARTCFIFO 0x11 37 #define UARTSFIFO 0x12 38 #define UARTTWFIFO 0x13 39 #define UARTTCFIFO 0x14 40 #define UARTRWFIFO 0x15 41 42 #define UARTBDH_LBKDIE 0x80 43 #define UARTBDH_RXEDGIE 0x40 44 #define UARTBDH_SBR_MASK 0x1f 45 46 #define UARTCR1_LOOPS 0x80 47 #define UARTCR1_RSRC 0x20 48 #define UARTCR1_M 0x10 49 #define UARTCR1_WAKE 0x08 50 #define UARTCR1_ILT 0x04 51 #define UARTCR1_PE 0x02 52 #define UARTCR1_PT 0x01 53 54 #define UARTCR2_TIE 0x80 55 #define UARTCR2_TCIE 0x40 56 #define UARTCR2_RIE 0x20 57 #define UARTCR2_ILIE 0x10 58 #define UARTCR2_TE 0x08 59 #define UARTCR2_RE 0x04 60 #define UARTCR2_RWU 0x02 61 #define UARTCR2_SBK 0x01 62 63 #define UARTSR1_TDRE 0x80 64 #define UARTSR1_TC 0x40 65 #define UARTSR1_RDRF 0x20 66 #define UARTSR1_IDLE 0x10 67 #define UARTSR1_OR 0x08 68 #define UARTSR1_NF 0x04 69 #define UARTSR1_FE 0x02 70 #define UARTSR1_PE 0x01 71 72 #define UARTCR3_R8 0x80 73 #define UARTCR3_T8 0x40 74 #define UARTCR3_TXDIR 0x20 75 #define UARTCR3_TXINV 0x10 76 #define UARTCR3_ORIE 0x08 77 #define UARTCR3_NEIE 0x04 78 #define UARTCR3_FEIE 0x02 79 #define UARTCR3_PEIE 0x01 80 81 #define UARTCR4_MAEN1 0x80 82 #define UARTCR4_MAEN2 0x40 83 #define UARTCR4_M10 0x20 84 #define UARTCR4_BRFA_MASK 0x1f 85 #define UARTCR4_BRFA_OFF 0 86 87 #define UARTCR5_TDMAS 0x80 88 #define UARTCR5_RDMAS 0x20 89 90 #define UARTMODEM_RXRTSE 0x08 91 #define UARTMODEM_TXRTSPOL 0x04 92 #define UARTMODEM_TXRTSE 0x02 93 #define UARTMODEM_TXCTSE 0x01 94 95 #define UARTPFIFO_TXFE 0x80 96 #define UARTPFIFO_FIFOSIZE_MASK 0x7 97 #define UARTPFIFO_TXSIZE_OFF 4 98 #define UARTPFIFO_RXFE 0x08 99 #define UARTPFIFO_RXSIZE_OFF 0 100 101 #define UARTCFIFO_TXFLUSH 0x80 102 #define UARTCFIFO_RXFLUSH 0x40 103 #define UARTCFIFO_RXOFE 0x04 104 #define UARTCFIFO_TXOFE 0x02 105 #define UARTCFIFO_RXUFE 0x01 106 107 #define UARTSFIFO_TXEMPT 0x80 108 #define UARTSFIFO_RXEMPT 0x40 109 #define UARTSFIFO_RXOF 0x04 110 #define UARTSFIFO_TXOF 0x02 111 #define UARTSFIFO_RXUF 0x01 112 113 /* 32-bit global registers only for i.MX7ULP/i.MX8x 114 * Used to reset all internal logic and registers, except the Global Register. 115 */ 116 #define UART_GLOBAL 0x8 117 118 /* 32-bit register definition */ 119 #define UARTBAUD 0x00 120 #define UARTSTAT 0x04 121 #define UARTCTRL 0x08 122 #define UARTDATA 0x0C 123 #define UARTMATCH 0x10 124 #define UARTMODIR 0x14 125 #define UARTFIFO 0x18 126 #define UARTWATER 0x1c 127 128 #define UARTBAUD_MAEN1 0x80000000 129 #define UARTBAUD_MAEN2 0x40000000 130 #define UARTBAUD_M10 0x20000000 131 #define UARTBAUD_TDMAE 0x00800000 132 #define UARTBAUD_RDMAE 0x00200000 133 #define UARTBAUD_MATCFG 0x00400000 134 #define UARTBAUD_BOTHEDGE 0x00020000 135 #define UARTBAUD_RESYNCDIS 0x00010000 136 #define UARTBAUD_LBKDIE 0x00008000 137 #define UARTBAUD_RXEDGIE 0x00004000 138 #define UARTBAUD_SBNS 0x00002000 139 #define UARTBAUD_SBR 0x00000000 140 #define UARTBAUD_SBR_MASK 0x1fff 141 #define UARTBAUD_OSR_MASK 0x1f 142 #define UARTBAUD_OSR_SHIFT 24 143 144 #define UARTSTAT_LBKDIF 0x80000000 145 #define UARTSTAT_RXEDGIF 0x40000000 146 #define UARTSTAT_MSBF 0x20000000 147 #define UARTSTAT_RXINV 0x10000000 148 #define UARTSTAT_RWUID 0x08000000 149 #define UARTSTAT_BRK13 0x04000000 150 #define UARTSTAT_LBKDE 0x02000000 151 #define UARTSTAT_RAF 0x01000000 152 #define UARTSTAT_TDRE 0x00800000 153 #define UARTSTAT_TC 0x00400000 154 #define UARTSTAT_RDRF 0x00200000 155 #define UARTSTAT_IDLE 0x00100000 156 #define UARTSTAT_OR 0x00080000 157 #define UARTSTAT_NF 0x00040000 158 #define UARTSTAT_FE 0x00020000 159 #define UARTSTAT_PE 0x00010000 160 #define UARTSTAT_MA1F 0x00008000 161 #define UARTSTAT_M21F 0x00004000 162 163 #define UARTCTRL_R8T9 0x80000000 164 #define UARTCTRL_R9T8 0x40000000 165 #define UARTCTRL_TXDIR 0x20000000 166 #define UARTCTRL_TXINV 0x10000000 167 #define UARTCTRL_ORIE 0x08000000 168 #define UARTCTRL_NEIE 0x04000000 169 #define UARTCTRL_FEIE 0x02000000 170 #define UARTCTRL_PEIE 0x01000000 171 #define UARTCTRL_TIE 0x00800000 172 #define UARTCTRL_TCIE 0x00400000 173 #define UARTCTRL_RIE 0x00200000 174 #define UARTCTRL_ILIE 0x00100000 175 #define UARTCTRL_TE 0x00080000 176 #define UARTCTRL_RE 0x00040000 177 #define UARTCTRL_RWU 0x00020000 178 #define UARTCTRL_SBK 0x00010000 179 #define UARTCTRL_MA1IE 0x00008000 180 #define UARTCTRL_MA2IE 0x00004000 181 #define UARTCTRL_IDLECFG 0x00000100 182 #define UARTCTRL_LOOPS 0x00000080 183 #define UARTCTRL_DOZEEN 0x00000040 184 #define UARTCTRL_RSRC 0x00000020 185 #define UARTCTRL_M 0x00000010 186 #define UARTCTRL_WAKE 0x00000008 187 #define UARTCTRL_ILT 0x00000004 188 #define UARTCTRL_PE 0x00000002 189 #define UARTCTRL_PT 0x00000001 190 191 #define UARTDATA_NOISY 0x00008000 192 #define UARTDATA_PARITYE 0x00004000 193 #define UARTDATA_FRETSC 0x00002000 194 #define UARTDATA_RXEMPT 0x00001000 195 #define UARTDATA_IDLINE 0x00000800 196 #define UARTDATA_MASK 0x3ff 197 198 #define UARTMODIR_IREN 0x00020000 199 #define UARTMODIR_TXCTSSRC 0x00000020 200 #define UARTMODIR_TXCTSC 0x00000010 201 #define UARTMODIR_RXRTSE 0x00000008 202 #define UARTMODIR_TXRTSPOL 0x00000004 203 #define UARTMODIR_TXRTSE 0x00000002 204 #define UARTMODIR_TXCTSE 0x00000001 205 206 #define UARTFIFO_TXEMPT 0x00800000 207 #define UARTFIFO_RXEMPT 0x00400000 208 #define UARTFIFO_TXOF 0x00020000 209 #define UARTFIFO_RXUF 0x00010000 210 #define UARTFIFO_TXFLUSH 0x00008000 211 #define UARTFIFO_RXFLUSH 0x00004000 212 #define UARTFIFO_TXOFE 0x00000200 213 #define UARTFIFO_RXUFE 0x00000100 214 #define UARTFIFO_TXFE 0x00000080 215 #define UARTFIFO_FIFOSIZE_MASK 0x7 216 #define UARTFIFO_TXSIZE_OFF 4 217 #define UARTFIFO_RXFE 0x00000008 218 #define UARTFIFO_RXSIZE_OFF 0 219 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0)) 220 221 #define UARTWATER_COUNT_MASK 0xff 222 #define UARTWATER_TXCNT_OFF 8 223 #define UARTWATER_RXCNT_OFF 24 224 #define UARTWATER_WATER_MASK 0xff 225 #define UARTWATER_TXWATER_OFF 0 226 #define UARTWATER_RXWATER_OFF 16 227 228 #define UART_GLOBAL_RST 0x2 229 #define GLOBAL_RST_MIN_US 20 230 #define GLOBAL_RST_MAX_US 40 231 232 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 233 #define DMA_RX_TIMEOUT (10) 234 235 #define DRIVER_NAME "fsl-lpuart" 236 #define DEV_NAME "ttyLP" 237 #define UART_NR 6 238 239 /* IMX lpuart has four extra unused regs located at the beginning */ 240 #define IMX_REG_OFF 0x10 241 242 enum lpuart_type { 243 VF610_LPUART, 244 LS1021A_LPUART, 245 LS1028A_LPUART, 246 IMX7ULP_LPUART, 247 IMX8QXP_LPUART, 248 IMXRT1050_LPUART, 249 }; 250 251 struct lpuart_port { 252 struct uart_port port; 253 enum lpuart_type devtype; 254 struct clk *ipg_clk; 255 struct clk *baud_clk; 256 unsigned int txfifo_size; 257 unsigned int rxfifo_size; 258 259 bool lpuart_dma_tx_use; 260 bool lpuart_dma_rx_use; 261 struct dma_chan *dma_tx_chan; 262 struct dma_chan *dma_rx_chan; 263 struct dma_async_tx_descriptor *dma_tx_desc; 264 struct dma_async_tx_descriptor *dma_rx_desc; 265 dma_cookie_t dma_tx_cookie; 266 dma_cookie_t dma_rx_cookie; 267 unsigned int dma_tx_bytes; 268 unsigned int dma_rx_bytes; 269 bool dma_tx_in_progress; 270 unsigned int dma_rx_timeout; 271 struct timer_list lpuart_timer; 272 struct scatterlist rx_sgl, tx_sgl[2]; 273 struct circ_buf rx_ring; 274 int rx_dma_rng_buf_len; 275 unsigned int dma_tx_nents; 276 wait_queue_head_t dma_wait; 277 bool is_cs7; /* Set to true when character size is 7 */ 278 /* and the parity is enabled */ 279 }; 280 281 struct lpuart_soc_data { 282 enum lpuart_type devtype; 283 char iotype; 284 u8 reg_off; 285 }; 286 287 static const struct lpuart_soc_data vf_data = { 288 .devtype = VF610_LPUART, 289 .iotype = UPIO_MEM, 290 }; 291 292 static const struct lpuart_soc_data ls1021a_data = { 293 .devtype = LS1021A_LPUART, 294 .iotype = UPIO_MEM32BE, 295 }; 296 297 static const struct lpuart_soc_data ls1028a_data = { 298 .devtype = LS1028A_LPUART, 299 .iotype = UPIO_MEM32, 300 }; 301 302 static struct lpuart_soc_data imx7ulp_data = { 303 .devtype = IMX7ULP_LPUART, 304 .iotype = UPIO_MEM32, 305 .reg_off = IMX_REG_OFF, 306 }; 307 308 static struct lpuart_soc_data imx8qxp_data = { 309 .devtype = IMX8QXP_LPUART, 310 .iotype = UPIO_MEM32, 311 .reg_off = IMX_REG_OFF, 312 }; 313 static struct lpuart_soc_data imxrt1050_data = { 314 .devtype = IMXRT1050_LPUART, 315 .iotype = UPIO_MEM32, 316 .reg_off = IMX_REG_OFF, 317 }; 318 319 static const struct of_device_id lpuart_dt_ids[] = { 320 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 321 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, }, 322 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, }, 323 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, 324 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, 325 { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data}, 326 { /* sentinel */ } 327 }; 328 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 329 330 /* Forward declare this for the dma callbacks*/ 331 static void lpuart_dma_tx_complete(void *arg); 332 333 static inline bool is_layerscape_lpuart(struct lpuart_port *sport) 334 { 335 return (sport->devtype == LS1021A_LPUART || 336 sport->devtype == LS1028A_LPUART); 337 } 338 339 static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport) 340 { 341 return sport->devtype == IMX7ULP_LPUART; 342 } 343 344 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) 345 { 346 return sport->devtype == IMX8QXP_LPUART; 347 } 348 349 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 350 { 351 switch (port->iotype) { 352 case UPIO_MEM32: 353 return readl(port->membase + off); 354 case UPIO_MEM32BE: 355 return ioread32be(port->membase + off); 356 default: 357 return 0; 358 } 359 } 360 361 static inline void lpuart32_write(struct uart_port *port, u32 val, 362 u32 off) 363 { 364 switch (port->iotype) { 365 case UPIO_MEM32: 366 writel(val, port->membase + off); 367 break; 368 case UPIO_MEM32BE: 369 iowrite32be(val, port->membase + off); 370 break; 371 } 372 } 373 374 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) 375 { 376 int ret = 0; 377 378 if (is_en) { 379 ret = clk_prepare_enable(sport->ipg_clk); 380 if (ret) 381 return ret; 382 383 ret = clk_prepare_enable(sport->baud_clk); 384 if (ret) { 385 clk_disable_unprepare(sport->ipg_clk); 386 return ret; 387 } 388 } else { 389 clk_disable_unprepare(sport->baud_clk); 390 clk_disable_unprepare(sport->ipg_clk); 391 } 392 393 return 0; 394 } 395 396 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) 397 { 398 if (is_imx8qxp_lpuart(sport)) 399 return clk_get_rate(sport->baud_clk); 400 401 return clk_get_rate(sport->ipg_clk); 402 } 403 404 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true) 405 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false) 406 407 static int lpuart_global_reset(struct lpuart_port *sport) 408 { 409 struct uart_port *port = &sport->port; 410 void __iomem *global_addr; 411 int ret; 412 413 if (uart_console(port)) 414 return 0; 415 416 ret = clk_prepare_enable(sport->ipg_clk); 417 if (ret) { 418 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret); 419 return ret; 420 } 421 422 if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) { 423 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF; 424 writel(UART_GLOBAL_RST, global_addr); 425 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); 426 writel(0, global_addr); 427 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); 428 } 429 430 clk_disable_unprepare(sport->ipg_clk); 431 return 0; 432 } 433 434 static void lpuart_stop_tx(struct uart_port *port) 435 { 436 unsigned char temp; 437 438 temp = readb(port->membase + UARTCR2); 439 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 440 writeb(temp, port->membase + UARTCR2); 441 } 442 443 static void lpuart32_stop_tx(struct uart_port *port) 444 { 445 unsigned long temp; 446 447 temp = lpuart32_read(port, UARTCTRL); 448 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 449 lpuart32_write(port, temp, UARTCTRL); 450 } 451 452 static void lpuart_stop_rx(struct uart_port *port) 453 { 454 unsigned char temp; 455 456 temp = readb(port->membase + UARTCR2); 457 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 458 } 459 460 static void lpuart32_stop_rx(struct uart_port *port) 461 { 462 unsigned long temp; 463 464 temp = lpuart32_read(port, UARTCTRL); 465 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); 466 } 467 468 static void lpuart_dma_tx(struct lpuart_port *sport) 469 { 470 struct circ_buf *xmit = &sport->port.state->xmit; 471 struct scatterlist *sgl = sport->tx_sgl; 472 struct device *dev = sport->port.dev; 473 struct dma_chan *chan = sport->dma_tx_chan; 474 int ret; 475 476 if (sport->dma_tx_in_progress) 477 return; 478 479 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 480 481 if (xmit->tail < xmit->head || xmit->head == 0) { 482 sport->dma_tx_nents = 1; 483 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 484 } else { 485 sport->dma_tx_nents = 2; 486 sg_init_table(sgl, 2); 487 sg_set_buf(sgl, xmit->buf + xmit->tail, 488 UART_XMIT_SIZE - xmit->tail); 489 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 490 } 491 492 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, 493 DMA_TO_DEVICE); 494 if (!ret) { 495 dev_err(dev, "DMA mapping error for TX.\n"); 496 return; 497 } 498 499 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, 500 ret, DMA_MEM_TO_DEV, 501 DMA_PREP_INTERRUPT); 502 if (!sport->dma_tx_desc) { 503 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 504 DMA_TO_DEVICE); 505 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 506 return; 507 } 508 509 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 510 sport->dma_tx_desc->callback_param = sport; 511 sport->dma_tx_in_progress = true; 512 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 513 dma_async_issue_pending(chan); 514 } 515 516 static bool lpuart_stopped_or_empty(struct uart_port *port) 517 { 518 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); 519 } 520 521 static void lpuart_dma_tx_complete(void *arg) 522 { 523 struct lpuart_port *sport = arg; 524 struct scatterlist *sgl = &sport->tx_sgl[0]; 525 struct circ_buf *xmit = &sport->port.state->xmit; 526 struct dma_chan *chan = sport->dma_tx_chan; 527 unsigned long flags; 528 529 spin_lock_irqsave(&sport->port.lock, flags); 530 if (!sport->dma_tx_in_progress) { 531 spin_unlock_irqrestore(&sport->port.lock, flags); 532 return; 533 } 534 535 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 536 DMA_TO_DEVICE); 537 538 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 539 540 sport->port.icount.tx += sport->dma_tx_bytes; 541 sport->dma_tx_in_progress = false; 542 spin_unlock_irqrestore(&sport->port.lock, flags); 543 544 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 545 uart_write_wakeup(&sport->port); 546 547 if (waitqueue_active(&sport->dma_wait)) { 548 wake_up(&sport->dma_wait); 549 return; 550 } 551 552 spin_lock_irqsave(&sport->port.lock, flags); 553 554 if (!lpuart_stopped_or_empty(&sport->port)) 555 lpuart_dma_tx(sport); 556 557 spin_unlock_irqrestore(&sport->port.lock, flags); 558 } 559 560 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) 561 { 562 switch (sport->port.iotype) { 563 case UPIO_MEM32: 564 return sport->port.mapbase + UARTDATA; 565 case UPIO_MEM32BE: 566 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; 567 } 568 return sport->port.mapbase + UARTDR; 569 } 570 571 static int lpuart_dma_tx_request(struct uart_port *port) 572 { 573 struct lpuart_port *sport = container_of(port, 574 struct lpuart_port, port); 575 struct dma_slave_config dma_tx_sconfig = {}; 576 int ret; 577 578 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); 579 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 580 dma_tx_sconfig.dst_maxburst = 1; 581 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 582 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 583 584 if (ret) { 585 dev_err(sport->port.dev, 586 "DMA slave config failed, err = %d\n", ret); 587 return ret; 588 } 589 590 return 0; 591 } 592 593 static bool lpuart_is_32(struct lpuart_port *sport) 594 { 595 return sport->port.iotype == UPIO_MEM32 || 596 sport->port.iotype == UPIO_MEM32BE; 597 } 598 599 static void lpuart_flush_buffer(struct uart_port *port) 600 { 601 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 602 struct dma_chan *chan = sport->dma_tx_chan; 603 u32 val; 604 605 if (sport->lpuart_dma_tx_use) { 606 if (sport->dma_tx_in_progress) { 607 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], 608 sport->dma_tx_nents, DMA_TO_DEVICE); 609 sport->dma_tx_in_progress = false; 610 } 611 dmaengine_terminate_all(chan); 612 } 613 614 if (lpuart_is_32(sport)) { 615 val = lpuart32_read(&sport->port, UARTFIFO); 616 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 617 lpuart32_write(&sport->port, val, UARTFIFO); 618 } else { 619 val = readb(sport->port.membase + UARTCFIFO); 620 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; 621 writeb(val, sport->port.membase + UARTCFIFO); 622 } 623 } 624 625 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset, 626 u8 bit) 627 { 628 while (!(readb(port->membase + offset) & bit)) 629 cpu_relax(); 630 } 631 632 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset, 633 u32 bit) 634 { 635 while (!(lpuart32_read(port, offset) & bit)) 636 cpu_relax(); 637 } 638 639 #if defined(CONFIG_CONSOLE_POLL) 640 641 static int lpuart_poll_init(struct uart_port *port) 642 { 643 struct lpuart_port *sport = container_of(port, 644 struct lpuart_port, port); 645 unsigned long flags; 646 unsigned char temp; 647 648 sport->port.fifosize = 0; 649 650 spin_lock_irqsave(&sport->port.lock, flags); 651 /* Disable Rx & Tx */ 652 writeb(0, sport->port.membase + UARTCR2); 653 654 temp = readb(sport->port.membase + UARTPFIFO); 655 /* Enable Rx and Tx FIFO */ 656 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 657 sport->port.membase + UARTPFIFO); 658 659 /* flush Tx and Rx FIFO */ 660 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 661 sport->port.membase + UARTCFIFO); 662 663 /* explicitly clear RDRF */ 664 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 665 readb(sport->port.membase + UARTDR); 666 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 667 } 668 669 writeb(0, sport->port.membase + UARTTWFIFO); 670 writeb(1, sport->port.membase + UARTRWFIFO); 671 672 /* Enable Rx and Tx */ 673 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 674 spin_unlock_irqrestore(&sport->port.lock, flags); 675 676 return 0; 677 } 678 679 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 680 { 681 /* drain */ 682 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 683 writeb(c, port->membase + UARTDR); 684 } 685 686 static int lpuart_poll_get_char(struct uart_port *port) 687 { 688 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 689 return NO_POLL_CHAR; 690 691 return readb(port->membase + UARTDR); 692 } 693 694 static int lpuart32_poll_init(struct uart_port *port) 695 { 696 unsigned long flags; 697 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 698 u32 temp; 699 700 sport->port.fifosize = 0; 701 702 spin_lock_irqsave(&sport->port.lock, flags); 703 704 /* Disable Rx & Tx */ 705 lpuart32_write(&sport->port, 0, UARTCTRL); 706 707 temp = lpuart32_read(&sport->port, UARTFIFO); 708 709 /* Enable Rx and Tx FIFO */ 710 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); 711 712 /* flush Tx and Rx FIFO */ 713 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); 714 715 /* explicitly clear RDRF */ 716 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { 717 lpuart32_read(&sport->port, UARTDATA); 718 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); 719 } 720 721 /* Enable Rx and Tx */ 722 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); 723 spin_unlock_irqrestore(&sport->port.lock, flags); 724 725 return 0; 726 } 727 728 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 729 { 730 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 731 lpuart32_write(port, c, UARTDATA); 732 } 733 734 static int lpuart32_poll_get_char(struct uart_port *port) 735 { 736 if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF)) 737 return NO_POLL_CHAR; 738 739 return lpuart32_read(port, UARTDATA); 740 } 741 #endif 742 743 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 744 { 745 struct circ_buf *xmit = &sport->port.state->xmit; 746 747 if (sport->port.x_char) { 748 writeb(sport->port.x_char, sport->port.membase + UARTDR); 749 sport->port.icount.tx++; 750 sport->port.x_char = 0; 751 return; 752 } 753 754 if (lpuart_stopped_or_empty(&sport->port)) { 755 lpuart_stop_tx(&sport->port); 756 return; 757 } 758 759 while (!uart_circ_empty(xmit) && 760 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 761 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 762 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 763 sport->port.icount.tx++; 764 } 765 766 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 767 uart_write_wakeup(&sport->port); 768 769 if (uart_circ_empty(xmit)) 770 lpuart_stop_tx(&sport->port); 771 } 772 773 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 774 { 775 struct circ_buf *xmit = &sport->port.state->xmit; 776 unsigned long txcnt; 777 778 if (sport->port.x_char) { 779 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 780 sport->port.icount.tx++; 781 sport->port.x_char = 0; 782 return; 783 } 784 785 if (lpuart_stopped_or_empty(&sport->port)) { 786 lpuart32_stop_tx(&sport->port); 787 return; 788 } 789 790 txcnt = lpuart32_read(&sport->port, UARTWATER); 791 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 792 txcnt &= UARTWATER_COUNT_MASK; 793 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 794 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); 795 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 796 sport->port.icount.tx++; 797 txcnt = lpuart32_read(&sport->port, UARTWATER); 798 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 799 txcnt &= UARTWATER_COUNT_MASK; 800 } 801 802 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 803 uart_write_wakeup(&sport->port); 804 805 if (uart_circ_empty(xmit)) 806 lpuart32_stop_tx(&sport->port); 807 } 808 809 static void lpuart_start_tx(struct uart_port *port) 810 { 811 struct lpuart_port *sport = container_of(port, 812 struct lpuart_port, port); 813 unsigned char temp; 814 815 temp = readb(port->membase + UARTCR2); 816 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 817 818 if (sport->lpuart_dma_tx_use) { 819 if (!lpuart_stopped_or_empty(port)) 820 lpuart_dma_tx(sport); 821 } else { 822 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 823 lpuart_transmit_buffer(sport); 824 } 825 } 826 827 static void lpuart32_start_tx(struct uart_port *port) 828 { 829 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 830 unsigned long temp; 831 832 if (sport->lpuart_dma_tx_use) { 833 if (!lpuart_stopped_or_empty(port)) 834 lpuart_dma_tx(sport); 835 } else { 836 temp = lpuart32_read(port, UARTCTRL); 837 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); 838 839 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 840 lpuart32_transmit_buffer(sport); 841 } 842 } 843 844 /* return TIOCSER_TEMT when transmitter is not busy */ 845 static unsigned int lpuart_tx_empty(struct uart_port *port) 846 { 847 struct lpuart_port *sport = container_of(port, 848 struct lpuart_port, port); 849 unsigned char sr1 = readb(port->membase + UARTSR1); 850 unsigned char sfifo = readb(port->membase + UARTSFIFO); 851 852 if (sport->dma_tx_in_progress) 853 return 0; 854 855 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 856 return TIOCSER_TEMT; 857 858 return 0; 859 } 860 861 static unsigned int lpuart32_tx_empty(struct uart_port *port) 862 { 863 struct lpuart_port *sport = container_of(port, 864 struct lpuart_port, port); 865 unsigned long stat = lpuart32_read(port, UARTSTAT); 866 unsigned long sfifo = lpuart32_read(port, UARTFIFO); 867 868 if (sport->dma_tx_in_progress) 869 return 0; 870 871 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) 872 return TIOCSER_TEMT; 873 874 return 0; 875 } 876 877 static void lpuart_txint(struct lpuart_port *sport) 878 { 879 spin_lock(&sport->port.lock); 880 lpuart_transmit_buffer(sport); 881 spin_unlock(&sport->port.lock); 882 } 883 884 static void lpuart_rxint(struct lpuart_port *sport) 885 { 886 unsigned int flg, ignored = 0, overrun = 0; 887 struct tty_port *port = &sport->port.state->port; 888 unsigned char rx, sr; 889 890 spin_lock(&sport->port.lock); 891 892 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 893 flg = TTY_NORMAL; 894 sport->port.icount.rx++; 895 /* 896 * to clear the FE, OR, NF, FE, PE flags, 897 * read SR1 then read DR 898 */ 899 sr = readb(sport->port.membase + UARTSR1); 900 rx = readb(sport->port.membase + UARTDR); 901 902 if (uart_prepare_sysrq_char(&sport->port, rx)) 903 continue; 904 905 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 906 if (sr & UARTSR1_PE) 907 sport->port.icount.parity++; 908 else if (sr & UARTSR1_FE) 909 sport->port.icount.frame++; 910 911 if (sr & UARTSR1_OR) 912 overrun++; 913 914 if (sr & sport->port.ignore_status_mask) { 915 if (++ignored > 100) 916 goto out; 917 continue; 918 } 919 920 sr &= sport->port.read_status_mask; 921 922 if (sr & UARTSR1_PE) 923 flg = TTY_PARITY; 924 else if (sr & UARTSR1_FE) 925 flg = TTY_FRAME; 926 927 if (sr & UARTSR1_OR) 928 flg = TTY_OVERRUN; 929 930 sport->port.sysrq = 0; 931 } 932 933 if (tty_insert_flip_char(port, rx, flg) == 0) 934 sport->port.icount.buf_overrun++; 935 } 936 937 out: 938 if (overrun) { 939 sport->port.icount.overrun += overrun; 940 941 /* 942 * Overruns cause FIFO pointers to become missaligned. 943 * Flushing the receive FIFO reinitializes the pointers. 944 */ 945 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 946 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); 947 } 948 949 uart_unlock_and_check_sysrq(&sport->port); 950 951 tty_flip_buffer_push(port); 952 } 953 954 static void lpuart32_txint(struct lpuart_port *sport) 955 { 956 spin_lock(&sport->port.lock); 957 lpuart32_transmit_buffer(sport); 958 spin_unlock(&sport->port.lock); 959 } 960 961 static void lpuart32_rxint(struct lpuart_port *sport) 962 { 963 unsigned int flg, ignored = 0; 964 struct tty_port *port = &sport->port.state->port; 965 unsigned long rx, sr; 966 bool is_break; 967 968 spin_lock(&sport->port.lock); 969 970 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 971 flg = TTY_NORMAL; 972 sport->port.icount.rx++; 973 /* 974 * to clear the FE, OR, NF, FE, PE flags, 975 * read STAT then read DATA reg 976 */ 977 sr = lpuart32_read(&sport->port, UARTSTAT); 978 rx = lpuart32_read(&sport->port, UARTDATA); 979 rx &= UARTDATA_MASK; 980 981 /* 982 * The LPUART can't distinguish between a break and a framing error, 983 * thus we assume it is a break if the received data is zero. 984 */ 985 is_break = (sr & UARTSTAT_FE) && !rx; 986 987 if (is_break && uart_handle_break(&sport->port)) 988 continue; 989 990 if (uart_prepare_sysrq_char(&sport->port, rx)) 991 continue; 992 993 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 994 if (sr & UARTSTAT_PE) { 995 sport->port.icount.parity++; 996 } else if (sr & UARTSTAT_FE) { 997 if (is_break) 998 sport->port.icount.brk++; 999 else 1000 sport->port.icount.frame++; 1001 } 1002 1003 if (sr & UARTSTAT_OR) 1004 sport->port.icount.overrun++; 1005 1006 if (sr & sport->port.ignore_status_mask) { 1007 if (++ignored > 100) 1008 goto out; 1009 continue; 1010 } 1011 1012 sr &= sport->port.read_status_mask; 1013 1014 if (sr & UARTSTAT_PE) { 1015 flg = TTY_PARITY; 1016 } else if (sr & UARTSTAT_FE) { 1017 if (is_break) 1018 flg = TTY_BREAK; 1019 else 1020 flg = TTY_FRAME; 1021 } 1022 1023 if (sr & UARTSTAT_OR) 1024 flg = TTY_OVERRUN; 1025 } 1026 1027 if (sport->is_cs7) 1028 rx &= 0x7F; 1029 1030 if (tty_insert_flip_char(port, rx, flg) == 0) 1031 sport->port.icount.buf_overrun++; 1032 } 1033 1034 out: 1035 uart_unlock_and_check_sysrq(&sport->port); 1036 1037 tty_flip_buffer_push(port); 1038 } 1039 1040 static irqreturn_t lpuart_int(int irq, void *dev_id) 1041 { 1042 struct lpuart_port *sport = dev_id; 1043 unsigned char sts; 1044 1045 sts = readb(sport->port.membase + UARTSR1); 1046 1047 /* SysRq, using dma, check for linebreak by framing err. */ 1048 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { 1049 readb(sport->port.membase + UARTDR); 1050 uart_handle_break(&sport->port); 1051 /* linebreak produces some garbage, removing it */ 1052 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 1053 return IRQ_HANDLED; 1054 } 1055 1056 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) 1057 lpuart_rxint(sport); 1058 1059 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) 1060 lpuart_txint(sport); 1061 1062 return IRQ_HANDLED; 1063 } 1064 1065 static irqreturn_t lpuart32_int(int irq, void *dev_id) 1066 { 1067 struct lpuart_port *sport = dev_id; 1068 unsigned long sts, rxcount; 1069 1070 sts = lpuart32_read(&sport->port, UARTSTAT); 1071 rxcount = lpuart32_read(&sport->port, UARTWATER); 1072 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 1073 1074 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) 1075 lpuart32_rxint(sport); 1076 1077 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) 1078 lpuart32_txint(sport); 1079 1080 lpuart32_write(&sport->port, sts, UARTSTAT); 1081 return IRQ_HANDLED; 1082 } 1083 1084 1085 static inline void lpuart_handle_sysrq_chars(struct uart_port *port, 1086 unsigned char *p, int count) 1087 { 1088 while (count--) { 1089 if (*p && uart_handle_sysrq_char(port, *p)) 1090 return; 1091 p++; 1092 } 1093 } 1094 1095 static void lpuart_handle_sysrq(struct lpuart_port *sport) 1096 { 1097 struct circ_buf *ring = &sport->rx_ring; 1098 int count; 1099 1100 if (ring->head < ring->tail) { 1101 count = sport->rx_sgl.length - ring->tail; 1102 lpuart_handle_sysrq_chars(&sport->port, 1103 ring->buf + ring->tail, count); 1104 ring->tail = 0; 1105 } 1106 1107 if (ring->head > ring->tail) { 1108 count = ring->head - ring->tail; 1109 lpuart_handle_sysrq_chars(&sport->port, 1110 ring->buf + ring->tail, count); 1111 ring->tail = ring->head; 1112 } 1113 } 1114 1115 static int lpuart_tty_insert_flip_string(struct tty_port *port, 1116 unsigned char *chars, size_t size, bool is_cs7) 1117 { 1118 int i; 1119 1120 if (is_cs7) 1121 for (i = 0; i < size; i++) 1122 chars[i] &= 0x7F; 1123 return tty_insert_flip_string(port, chars, size); 1124 } 1125 1126 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 1127 { 1128 struct tty_port *port = &sport->port.state->port; 1129 struct dma_tx_state state; 1130 enum dma_status dmastat; 1131 struct dma_chan *chan = sport->dma_rx_chan; 1132 struct circ_buf *ring = &sport->rx_ring; 1133 unsigned long flags; 1134 int count, copied; 1135 1136 if (lpuart_is_32(sport)) { 1137 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); 1138 1139 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { 1140 /* Read DR to clear the error flags */ 1141 lpuart32_read(&sport->port, UARTDATA); 1142 1143 if (sr & UARTSTAT_PE) 1144 sport->port.icount.parity++; 1145 else if (sr & UARTSTAT_FE) 1146 sport->port.icount.frame++; 1147 } 1148 } else { 1149 unsigned char sr = readb(sport->port.membase + UARTSR1); 1150 1151 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 1152 unsigned char cr2; 1153 1154 /* Disable receiver during this operation... */ 1155 cr2 = readb(sport->port.membase + UARTCR2); 1156 cr2 &= ~UARTCR2_RE; 1157 writeb(cr2, sport->port.membase + UARTCR2); 1158 1159 /* Read DR to clear the error flags */ 1160 readb(sport->port.membase + UARTDR); 1161 1162 if (sr & UARTSR1_PE) 1163 sport->port.icount.parity++; 1164 else if (sr & UARTSR1_FE) 1165 sport->port.icount.frame++; 1166 /* 1167 * At this point parity/framing error is 1168 * cleared However, since the DMA already read 1169 * the data register and we had to read it 1170 * again after reading the status register to 1171 * properly clear the flags, the FIFO actually 1172 * underflowed... This requires a clearing of 1173 * the FIFO... 1174 */ 1175 if (readb(sport->port.membase + UARTSFIFO) & 1176 UARTSFIFO_RXUF) { 1177 writeb(UARTSFIFO_RXUF, 1178 sport->port.membase + UARTSFIFO); 1179 writeb(UARTCFIFO_RXFLUSH, 1180 sport->port.membase + UARTCFIFO); 1181 } 1182 1183 cr2 |= UARTCR2_RE; 1184 writeb(cr2, sport->port.membase + UARTCR2); 1185 } 1186 } 1187 1188 async_tx_ack(sport->dma_rx_desc); 1189 1190 spin_lock_irqsave(&sport->port.lock, flags); 1191 1192 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1193 if (dmastat == DMA_ERROR) { 1194 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1195 spin_unlock_irqrestore(&sport->port.lock, flags); 1196 return; 1197 } 1198 1199 /* CPU claims ownership of RX DMA buffer */ 1200 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, 1201 DMA_FROM_DEVICE); 1202 1203 /* 1204 * ring->head points to the end of data already written by the DMA. 1205 * ring->tail points to the beginning of data to be read by the 1206 * framework. 1207 * The current transfer size should not be larger than the dma buffer 1208 * length. 1209 */ 1210 ring->head = sport->rx_sgl.length - state.residue; 1211 BUG_ON(ring->head > sport->rx_sgl.length); 1212 1213 /* 1214 * Silent handling of keys pressed in the sysrq timeframe 1215 */ 1216 if (sport->port.sysrq) { 1217 lpuart_handle_sysrq(sport); 1218 goto exit; 1219 } 1220 1221 /* 1222 * At this point ring->head may point to the first byte right after the 1223 * last byte of the dma buffer: 1224 * 0 <= ring->head <= sport->rx_sgl.length 1225 * 1226 * However ring->tail must always points inside the dma buffer: 1227 * 0 <= ring->tail <= sport->rx_sgl.length - 1 1228 * 1229 * Since we use a ring buffer, we have to handle the case 1230 * where head is lower than tail. In such a case, we first read from 1231 * tail to the end of the buffer then reset tail. 1232 */ 1233 if (ring->head < ring->tail) { 1234 count = sport->rx_sgl.length - ring->tail; 1235 1236 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, 1237 count, sport->is_cs7); 1238 if (copied != count) 1239 sport->port.icount.buf_overrun++; 1240 ring->tail = 0; 1241 sport->port.icount.rx += copied; 1242 } 1243 1244 /* Finally we read data from tail to head */ 1245 if (ring->tail < ring->head) { 1246 count = ring->head - ring->tail; 1247 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, 1248 count, sport->is_cs7); 1249 if (copied != count) 1250 sport->port.icount.buf_overrun++; 1251 /* Wrap ring->head if needed */ 1252 if (ring->head >= sport->rx_sgl.length) 1253 ring->head = 0; 1254 ring->tail = ring->head; 1255 sport->port.icount.rx += copied; 1256 } 1257 1258 exit: 1259 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, 1260 DMA_FROM_DEVICE); 1261 1262 spin_unlock_irqrestore(&sport->port.lock, flags); 1263 1264 tty_flip_buffer_push(port); 1265 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 1266 } 1267 1268 static void lpuart_dma_rx_complete(void *arg) 1269 { 1270 struct lpuart_port *sport = arg; 1271 1272 lpuart_copy_rx_to_tty(sport); 1273 } 1274 1275 static void lpuart_timer_func(struct timer_list *t) 1276 { 1277 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); 1278 1279 lpuart_copy_rx_to_tty(sport); 1280 } 1281 1282 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 1283 { 1284 struct dma_slave_config dma_rx_sconfig = {}; 1285 struct circ_buf *ring = &sport->rx_ring; 1286 int ret, nent; 1287 int bits, baud; 1288 struct tty_port *port = &sport->port.state->port; 1289 struct tty_struct *tty = port->tty; 1290 struct ktermios *termios = &tty->termios; 1291 struct dma_chan *chan = sport->dma_rx_chan; 1292 1293 baud = tty_get_baud_rate(tty); 1294 1295 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; 1296 if (termios->c_cflag & PARENB) 1297 bits++; 1298 1299 /* 1300 * Calculate length of one DMA buffer size to keep latency below 1301 * 10ms at any baud rate. 1302 */ 1303 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 1304 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 1305 if (sport->rx_dma_rng_buf_len < 16) 1306 sport->rx_dma_rng_buf_len = 16; 1307 1308 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1309 if (!ring->buf) 1310 return -ENOMEM; 1311 1312 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1313 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, 1314 DMA_FROM_DEVICE); 1315 1316 if (!nent) { 1317 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1318 return -EINVAL; 1319 } 1320 1321 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); 1322 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1323 dma_rx_sconfig.src_maxburst = 1; 1324 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1325 ret = dmaengine_slave_config(chan, &dma_rx_sconfig); 1326 1327 if (ret < 0) { 1328 dev_err(sport->port.dev, 1329 "DMA Rx slave config failed, err = %d\n", ret); 1330 return ret; 1331 } 1332 1333 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, 1334 sg_dma_address(&sport->rx_sgl), 1335 sport->rx_sgl.length, 1336 sport->rx_sgl.length / 2, 1337 DMA_DEV_TO_MEM, 1338 DMA_PREP_INTERRUPT); 1339 if (!sport->dma_rx_desc) { 1340 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1341 return -EFAULT; 1342 } 1343 1344 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1345 sport->dma_rx_desc->callback_param = sport; 1346 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1347 dma_async_issue_pending(chan); 1348 1349 if (lpuart_is_32(sport)) { 1350 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); 1351 1352 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); 1353 } else { 1354 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1355 sport->port.membase + UARTCR5); 1356 } 1357 1358 return 0; 1359 } 1360 1361 static void lpuart_dma_rx_free(struct uart_port *port) 1362 { 1363 struct lpuart_port *sport = container_of(port, 1364 struct lpuart_port, port); 1365 struct dma_chan *chan = sport->dma_rx_chan; 1366 1367 dmaengine_terminate_all(chan); 1368 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1369 kfree(sport->rx_ring.buf); 1370 sport->rx_ring.tail = 0; 1371 sport->rx_ring.head = 0; 1372 sport->dma_rx_desc = NULL; 1373 sport->dma_rx_cookie = -EINVAL; 1374 } 1375 1376 static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios, 1377 struct serial_rs485 *rs485) 1378 { 1379 struct lpuart_port *sport = container_of(port, 1380 struct lpuart_port, port); 1381 1382 u8 modem = readb(sport->port.membase + UARTMODEM) & 1383 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1384 writeb(modem, sport->port.membase + UARTMODEM); 1385 1386 if (rs485->flags & SER_RS485_ENABLED) { 1387 /* Enable auto RS-485 RTS mode */ 1388 modem |= UARTMODEM_TXRTSE; 1389 1390 /* 1391 * The hardware defaults to RTS logic HIGH while transfer. 1392 * Switch polarity in case RTS shall be logic HIGH 1393 * after transfer. 1394 * Note: UART is assumed to be active high. 1395 */ 1396 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1397 modem |= UARTMODEM_TXRTSPOL; 1398 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1399 modem &= ~UARTMODEM_TXRTSPOL; 1400 } 1401 1402 writeb(modem, sport->port.membase + UARTMODEM); 1403 return 0; 1404 } 1405 1406 static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios, 1407 struct serial_rs485 *rs485) 1408 { 1409 struct lpuart_port *sport = container_of(port, 1410 struct lpuart_port, port); 1411 1412 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) 1413 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1414 lpuart32_write(&sport->port, modem, UARTMODIR); 1415 1416 if (rs485->flags & SER_RS485_ENABLED) { 1417 /* Enable auto RS-485 RTS mode */ 1418 modem |= UARTMODEM_TXRTSE; 1419 1420 /* 1421 * The hardware defaults to RTS logic HIGH while transfer. 1422 * Switch polarity in case RTS shall be logic HIGH 1423 * after transfer. 1424 * Note: UART is assumed to be active high. 1425 */ 1426 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1427 modem &= ~UARTMODEM_TXRTSPOL; 1428 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1429 modem |= UARTMODEM_TXRTSPOL; 1430 } 1431 1432 lpuart32_write(&sport->port, modem, UARTMODIR); 1433 return 0; 1434 } 1435 1436 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1437 { 1438 unsigned int mctrl = 0; 1439 u8 reg; 1440 1441 reg = readb(port->membase + UARTCR1); 1442 if (reg & UARTCR1_LOOPS) 1443 mctrl |= TIOCM_LOOP; 1444 1445 return mctrl; 1446 } 1447 1448 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1449 { 1450 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 1451 u32 reg; 1452 1453 reg = lpuart32_read(port, UARTCTRL); 1454 if (reg & UARTCTRL_LOOPS) 1455 mctrl |= TIOCM_LOOP; 1456 1457 return mctrl; 1458 } 1459 1460 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1461 { 1462 u8 reg; 1463 1464 reg = readb(port->membase + UARTCR1); 1465 1466 /* for internal loopback we need LOOPS=1 and RSRC=0 */ 1467 reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC); 1468 if (mctrl & TIOCM_LOOP) 1469 reg |= UARTCR1_LOOPS; 1470 1471 writeb(reg, port->membase + UARTCR1); 1472 } 1473 1474 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1475 { 1476 u32 reg; 1477 1478 reg = lpuart32_read(port, UARTCTRL); 1479 1480 /* for internal loopback we need LOOPS=1 and RSRC=0 */ 1481 reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC); 1482 if (mctrl & TIOCM_LOOP) 1483 reg |= UARTCTRL_LOOPS; 1484 1485 lpuart32_write(port, reg, UARTCTRL); 1486 } 1487 1488 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1489 { 1490 unsigned char temp; 1491 1492 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1493 1494 if (break_state != 0) 1495 temp |= UARTCR2_SBK; 1496 1497 writeb(temp, port->membase + UARTCR2); 1498 } 1499 1500 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1501 { 1502 unsigned long temp; 1503 1504 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; 1505 1506 if (break_state != 0) 1507 temp |= UARTCTRL_SBK; 1508 1509 lpuart32_write(port, temp, UARTCTRL); 1510 } 1511 1512 static void lpuart_setup_watermark(struct lpuart_port *sport) 1513 { 1514 unsigned char val, cr2; 1515 unsigned char cr2_saved; 1516 1517 cr2 = readb(sport->port.membase + UARTCR2); 1518 cr2_saved = cr2; 1519 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1520 UARTCR2_RIE | UARTCR2_RE); 1521 writeb(cr2, sport->port.membase + UARTCR2); 1522 1523 val = readb(sport->port.membase + UARTPFIFO); 1524 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1525 sport->port.membase + UARTPFIFO); 1526 1527 /* flush Tx and Rx FIFO */ 1528 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1529 sport->port.membase + UARTCFIFO); 1530 1531 /* explicitly clear RDRF */ 1532 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1533 readb(sport->port.membase + UARTDR); 1534 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1535 } 1536 1537 writeb(0, sport->port.membase + UARTTWFIFO); 1538 writeb(1, sport->port.membase + UARTRWFIFO); 1539 1540 /* Restore cr2 */ 1541 writeb(cr2_saved, sport->port.membase + UARTCR2); 1542 } 1543 1544 static void lpuart_setup_watermark_enable(struct lpuart_port *sport) 1545 { 1546 unsigned char cr2; 1547 1548 lpuart_setup_watermark(sport); 1549 1550 cr2 = readb(sport->port.membase + UARTCR2); 1551 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE; 1552 writeb(cr2, sport->port.membase + UARTCR2); 1553 } 1554 1555 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1556 { 1557 unsigned long val, ctrl; 1558 unsigned long ctrl_saved; 1559 1560 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1561 ctrl_saved = ctrl; 1562 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1563 UARTCTRL_RIE | UARTCTRL_RE); 1564 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1565 1566 /* enable FIFO mode */ 1567 val = lpuart32_read(&sport->port, UARTFIFO); 1568 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1569 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1570 lpuart32_write(&sport->port, val, UARTFIFO); 1571 1572 /* set the watermark */ 1573 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1574 lpuart32_write(&sport->port, val, UARTWATER); 1575 1576 /* Restore cr2 */ 1577 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1578 } 1579 1580 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) 1581 { 1582 u32 temp; 1583 1584 lpuart32_setup_watermark(sport); 1585 1586 temp = lpuart32_read(&sport->port, UARTCTRL); 1587 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE; 1588 lpuart32_write(&sport->port, temp, UARTCTRL); 1589 } 1590 1591 static void rx_dma_timer_init(struct lpuart_port *sport) 1592 { 1593 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); 1594 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1595 add_timer(&sport->lpuart_timer); 1596 } 1597 1598 static void lpuart_request_dma(struct lpuart_port *sport) 1599 { 1600 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); 1601 if (IS_ERR(sport->dma_tx_chan)) { 1602 dev_dbg_once(sport->port.dev, 1603 "DMA tx channel request failed, operating without tx DMA (%ld)\n", 1604 PTR_ERR(sport->dma_tx_chan)); 1605 sport->dma_tx_chan = NULL; 1606 } 1607 1608 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); 1609 if (IS_ERR(sport->dma_rx_chan)) { 1610 dev_dbg_once(sport->port.dev, 1611 "DMA rx channel request failed, operating without rx DMA (%ld)\n", 1612 PTR_ERR(sport->dma_rx_chan)); 1613 sport->dma_rx_chan = NULL; 1614 } 1615 } 1616 1617 static void lpuart_tx_dma_startup(struct lpuart_port *sport) 1618 { 1619 u32 uartbaud; 1620 int ret; 1621 1622 if (uart_console(&sport->port)) 1623 goto err; 1624 1625 if (!sport->dma_tx_chan) 1626 goto err; 1627 1628 ret = lpuart_dma_tx_request(&sport->port); 1629 if (ret) 1630 goto err; 1631 1632 init_waitqueue_head(&sport->dma_wait); 1633 sport->lpuart_dma_tx_use = true; 1634 if (lpuart_is_32(sport)) { 1635 uartbaud = lpuart32_read(&sport->port, UARTBAUD); 1636 lpuart32_write(&sport->port, 1637 uartbaud | UARTBAUD_TDMAE, UARTBAUD); 1638 } else { 1639 writeb(readb(sport->port.membase + UARTCR5) | 1640 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 1641 } 1642 1643 return; 1644 1645 err: 1646 sport->lpuart_dma_tx_use = false; 1647 } 1648 1649 static void lpuart_rx_dma_startup(struct lpuart_port *sport) 1650 { 1651 int ret; 1652 unsigned char cr3; 1653 1654 if (uart_console(&sport->port)) 1655 goto err; 1656 1657 if (!sport->dma_rx_chan) 1658 goto err; 1659 1660 ret = lpuart_start_rx_dma(sport); 1661 if (ret) 1662 goto err; 1663 1664 /* set Rx DMA timeout */ 1665 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1666 if (!sport->dma_rx_timeout) 1667 sport->dma_rx_timeout = 1; 1668 1669 sport->lpuart_dma_rx_use = true; 1670 rx_dma_timer_init(sport); 1671 1672 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { 1673 cr3 = readb(sport->port.membase + UARTCR3); 1674 cr3 |= UARTCR3_FEIE; 1675 writeb(cr3, sport->port.membase + UARTCR3); 1676 } 1677 1678 return; 1679 1680 err: 1681 sport->lpuart_dma_rx_use = false; 1682 } 1683 1684 static int lpuart_startup(struct uart_port *port) 1685 { 1686 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1687 unsigned long flags; 1688 unsigned char temp; 1689 1690 /* determine FIFO size and enable FIFO mode */ 1691 temp = readb(sport->port.membase + UARTPFIFO); 1692 1693 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & 1694 UARTPFIFO_FIFOSIZE_MASK); 1695 sport->port.fifosize = sport->txfifo_size; 1696 1697 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & 1698 UARTPFIFO_FIFOSIZE_MASK); 1699 1700 lpuart_request_dma(sport); 1701 1702 spin_lock_irqsave(&sport->port.lock, flags); 1703 1704 lpuart_setup_watermark_enable(sport); 1705 1706 lpuart_rx_dma_startup(sport); 1707 lpuart_tx_dma_startup(sport); 1708 1709 spin_unlock_irqrestore(&sport->port.lock, flags); 1710 1711 return 0; 1712 } 1713 1714 static void lpuart32_configure(struct lpuart_port *sport) 1715 { 1716 unsigned long temp; 1717 1718 if (sport->lpuart_dma_rx_use) { 1719 /* RXWATER must be 0 */ 1720 temp = lpuart32_read(&sport->port, UARTWATER); 1721 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF); 1722 lpuart32_write(&sport->port, temp, UARTWATER); 1723 } 1724 temp = lpuart32_read(&sport->port, UARTCTRL); 1725 if (!sport->lpuart_dma_rx_use) 1726 temp |= UARTCTRL_RIE; 1727 if (!sport->lpuart_dma_tx_use) 1728 temp |= UARTCTRL_TIE; 1729 lpuart32_write(&sport->port, temp, UARTCTRL); 1730 } 1731 1732 static int lpuart32_startup(struct uart_port *port) 1733 { 1734 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1735 unsigned long flags; 1736 unsigned long temp; 1737 1738 /* determine FIFO size */ 1739 temp = lpuart32_read(&sport->port, UARTFIFO); 1740 1741 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & 1742 UARTFIFO_FIFOSIZE_MASK); 1743 sport->port.fifosize = sport->txfifo_size; 1744 1745 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & 1746 UARTFIFO_FIFOSIZE_MASK); 1747 1748 /* 1749 * The LS1021A and LS1028A have a fixed FIFO depth of 16 words. 1750 * Although they support the RX/TXSIZE fields, their encoding is 1751 * different. Eg the reference manual states 0b101 is 16 words. 1752 */ 1753 if (is_layerscape_lpuart(sport)) { 1754 sport->rxfifo_size = 16; 1755 sport->txfifo_size = 16; 1756 sport->port.fifosize = sport->txfifo_size; 1757 } 1758 1759 lpuart_request_dma(sport); 1760 1761 spin_lock_irqsave(&sport->port.lock, flags); 1762 1763 lpuart32_setup_watermark_enable(sport); 1764 1765 lpuart_rx_dma_startup(sport); 1766 lpuart_tx_dma_startup(sport); 1767 1768 lpuart32_configure(sport); 1769 1770 spin_unlock_irqrestore(&sport->port.lock, flags); 1771 return 0; 1772 } 1773 1774 static void lpuart_dma_shutdown(struct lpuart_port *sport) 1775 { 1776 if (sport->lpuart_dma_rx_use) { 1777 del_timer_sync(&sport->lpuart_timer); 1778 lpuart_dma_rx_free(&sport->port); 1779 } 1780 1781 if (sport->lpuart_dma_tx_use) { 1782 if (wait_event_interruptible_timeout(sport->dma_wait, 1783 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { 1784 sport->dma_tx_in_progress = false; 1785 dmaengine_terminate_all(sport->dma_tx_chan); 1786 } 1787 } 1788 1789 if (sport->dma_tx_chan) 1790 dma_release_channel(sport->dma_tx_chan); 1791 if (sport->dma_rx_chan) 1792 dma_release_channel(sport->dma_rx_chan); 1793 } 1794 1795 static void lpuart_shutdown(struct uart_port *port) 1796 { 1797 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1798 unsigned char temp; 1799 unsigned long flags; 1800 1801 spin_lock_irqsave(&port->lock, flags); 1802 1803 /* disable Rx/Tx and interrupts */ 1804 temp = readb(port->membase + UARTCR2); 1805 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1806 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1807 writeb(temp, port->membase + UARTCR2); 1808 1809 spin_unlock_irqrestore(&port->lock, flags); 1810 1811 lpuart_dma_shutdown(sport); 1812 } 1813 1814 static void lpuart32_shutdown(struct uart_port *port) 1815 { 1816 struct lpuart_port *sport = 1817 container_of(port, struct lpuart_port, port); 1818 unsigned long temp; 1819 unsigned long flags; 1820 1821 spin_lock_irqsave(&port->lock, flags); 1822 1823 /* disable Rx/Tx and interrupts */ 1824 temp = lpuart32_read(port, UARTCTRL); 1825 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1826 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1827 lpuart32_write(port, temp, UARTCTRL); 1828 1829 spin_unlock_irqrestore(&port->lock, flags); 1830 1831 lpuart_dma_shutdown(sport); 1832 } 1833 1834 static void 1835 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1836 struct ktermios *old) 1837 { 1838 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1839 unsigned long flags; 1840 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1841 unsigned int baud; 1842 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1843 unsigned int sbr, brfa; 1844 1845 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1846 old_cr2 = readb(sport->port.membase + UARTCR2); 1847 cr3 = readb(sport->port.membase + UARTCR3); 1848 cr4 = readb(sport->port.membase + UARTCR4); 1849 bdh = readb(sport->port.membase + UARTBDH); 1850 modem = readb(sport->port.membase + UARTMODEM); 1851 /* 1852 * only support CS8 and CS7, and for CS7 must enable PE. 1853 * supported mode: 1854 * - (7,e/o,1) 1855 * - (8,n,1) 1856 * - (8,m/s,1) 1857 * - (8,e/o,1) 1858 */ 1859 while ((termios->c_cflag & CSIZE) != CS8 && 1860 (termios->c_cflag & CSIZE) != CS7) { 1861 termios->c_cflag &= ~CSIZE; 1862 termios->c_cflag |= old_csize; 1863 old_csize = CS8; 1864 } 1865 1866 if ((termios->c_cflag & CSIZE) == CS8 || 1867 (termios->c_cflag & CSIZE) == CS7) 1868 cr1 = old_cr1 & ~UARTCR1_M; 1869 1870 if (termios->c_cflag & CMSPAR) { 1871 if ((termios->c_cflag & CSIZE) != CS8) { 1872 termios->c_cflag &= ~CSIZE; 1873 termios->c_cflag |= CS8; 1874 } 1875 cr1 |= UARTCR1_M; 1876 } 1877 1878 /* 1879 * When auto RS-485 RTS mode is enabled, 1880 * hardware flow control need to be disabled. 1881 */ 1882 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1883 termios->c_cflag &= ~CRTSCTS; 1884 1885 if (termios->c_cflag & CRTSCTS) 1886 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE; 1887 else 1888 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1889 1890 termios->c_cflag &= ~CSTOPB; 1891 1892 /* parity must be enabled when CS7 to match 8-bits format */ 1893 if ((termios->c_cflag & CSIZE) == CS7) 1894 termios->c_cflag |= PARENB; 1895 1896 if (termios->c_cflag & PARENB) { 1897 if (termios->c_cflag & CMSPAR) { 1898 cr1 &= ~UARTCR1_PE; 1899 if (termios->c_cflag & PARODD) 1900 cr3 |= UARTCR3_T8; 1901 else 1902 cr3 &= ~UARTCR3_T8; 1903 } else { 1904 cr1 |= UARTCR1_PE; 1905 if ((termios->c_cflag & CSIZE) == CS8) 1906 cr1 |= UARTCR1_M; 1907 if (termios->c_cflag & PARODD) 1908 cr1 |= UARTCR1_PT; 1909 else 1910 cr1 &= ~UARTCR1_PT; 1911 } 1912 } else { 1913 cr1 &= ~UARTCR1_PE; 1914 } 1915 1916 /* ask the core to calculate the divisor */ 1917 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1918 1919 /* 1920 * Need to update the Ring buffer length according to the selected 1921 * baud rate and restart Rx DMA path. 1922 * 1923 * Since timer function acqures sport->port.lock, need to stop before 1924 * acquring same lock because otherwise del_timer_sync() can deadlock. 1925 */ 1926 if (old && sport->lpuart_dma_rx_use) { 1927 del_timer_sync(&sport->lpuart_timer); 1928 lpuart_dma_rx_free(&sport->port); 1929 } 1930 1931 spin_lock_irqsave(&sport->port.lock, flags); 1932 1933 sport->port.read_status_mask = 0; 1934 if (termios->c_iflag & INPCK) 1935 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; 1936 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1937 sport->port.read_status_mask |= UARTSR1_FE; 1938 1939 /* characters to ignore */ 1940 sport->port.ignore_status_mask = 0; 1941 if (termios->c_iflag & IGNPAR) 1942 sport->port.ignore_status_mask |= UARTSR1_PE; 1943 if (termios->c_iflag & IGNBRK) { 1944 sport->port.ignore_status_mask |= UARTSR1_FE; 1945 /* 1946 * if we're ignoring parity and break indicators, 1947 * ignore overruns too (for real raw support). 1948 */ 1949 if (termios->c_iflag & IGNPAR) 1950 sport->port.ignore_status_mask |= UARTSR1_OR; 1951 } 1952 1953 /* update the per-port timeout */ 1954 uart_update_timeout(port, termios->c_cflag, baud); 1955 1956 /* wait transmit engin complete */ 1957 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 1958 1959 /* disable transmit and receive */ 1960 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1961 sport->port.membase + UARTCR2); 1962 1963 sbr = sport->port.uartclk / (16 * baud); 1964 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1965 bdh &= ~UARTBDH_SBR_MASK; 1966 bdh |= (sbr >> 8) & 0x1F; 1967 cr4 &= ~UARTCR4_BRFA_MASK; 1968 brfa &= UARTCR4_BRFA_MASK; 1969 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1970 writeb(bdh, sport->port.membase + UARTBDH); 1971 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1972 writeb(cr3, sport->port.membase + UARTCR3); 1973 writeb(cr1, sport->port.membase + UARTCR1); 1974 writeb(modem, sport->port.membase + UARTMODEM); 1975 1976 /* restore control register */ 1977 writeb(old_cr2, sport->port.membase + UARTCR2); 1978 1979 if (old && sport->lpuart_dma_rx_use) { 1980 if (!lpuart_start_rx_dma(sport)) 1981 rx_dma_timer_init(sport); 1982 else 1983 sport->lpuart_dma_rx_use = false; 1984 } 1985 1986 spin_unlock_irqrestore(&sport->port.lock, flags); 1987 } 1988 1989 static void __lpuart32_serial_setbrg(struct uart_port *port, 1990 unsigned int baudrate, bool use_rx_dma, 1991 bool use_tx_dma) 1992 { 1993 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; 1994 u32 clk = port->uartclk; 1995 1996 /* 1997 * The idea is to use the best OSR (over-sampling rate) possible. 1998 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 1999 * Loop to find the best OSR value possible, one that generates minimum 2000 * baud_diff iterate through the rest of the supported values of OSR. 2001 * 2002 * Calculation Formula: 2003 * Baud Rate = baud clock / ((OSR+1) × SBR) 2004 */ 2005 baud_diff = baudrate; 2006 osr = 0; 2007 sbr = 0; 2008 2009 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 2010 /* calculate the temporary sbr value */ 2011 tmp_sbr = (clk / (baudrate * tmp_osr)); 2012 if (tmp_sbr == 0) 2013 tmp_sbr = 1; 2014 2015 /* 2016 * calculate the baud rate difference based on the temporary 2017 * osr and sbr values 2018 */ 2019 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 2020 2021 /* select best values between sbr and sbr+1 */ 2022 tmp = clk / (tmp_osr * (tmp_sbr + 1)); 2023 if (tmp_diff > (baudrate - tmp)) { 2024 tmp_diff = baudrate - tmp; 2025 tmp_sbr++; 2026 } 2027 2028 if (tmp_sbr > UARTBAUD_SBR_MASK) 2029 continue; 2030 2031 if (tmp_diff <= baud_diff) { 2032 baud_diff = tmp_diff; 2033 osr = tmp_osr; 2034 sbr = tmp_sbr; 2035 2036 if (!baud_diff) 2037 break; 2038 } 2039 } 2040 2041 /* handle buadrate outside acceptable rate */ 2042 if (baud_diff > ((baudrate / 100) * 3)) 2043 dev_warn(port->dev, 2044 "unacceptable baud rate difference of more than 3%%\n"); 2045 2046 tmp = lpuart32_read(port, UARTBAUD); 2047 2048 if ((osr > 3) && (osr < 8)) 2049 tmp |= UARTBAUD_BOTHEDGE; 2050 2051 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 2052 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; 2053 2054 tmp &= ~UARTBAUD_SBR_MASK; 2055 tmp |= sbr & UARTBAUD_SBR_MASK; 2056 2057 if (!use_rx_dma) 2058 tmp &= ~UARTBAUD_RDMAE; 2059 if (!use_tx_dma) 2060 tmp &= ~UARTBAUD_TDMAE; 2061 2062 lpuart32_write(port, tmp, UARTBAUD); 2063 } 2064 2065 static void lpuart32_serial_setbrg(struct lpuart_port *sport, 2066 unsigned int baudrate) 2067 { 2068 __lpuart32_serial_setbrg(&sport->port, baudrate, 2069 sport->lpuart_dma_rx_use, 2070 sport->lpuart_dma_tx_use); 2071 } 2072 2073 2074 static void 2075 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 2076 struct ktermios *old) 2077 { 2078 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 2079 unsigned long flags; 2080 unsigned long ctrl, old_ctrl, bd, modem; 2081 unsigned int baud; 2082 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 2083 2084 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); 2085 bd = lpuart32_read(&sport->port, UARTBAUD); 2086 modem = lpuart32_read(&sport->port, UARTMODIR); 2087 sport->is_cs7 = false; 2088 /* 2089 * only support CS8 and CS7, and for CS7 must enable PE. 2090 * supported mode: 2091 * - (7,e/o,1) 2092 * - (8,n,1) 2093 * - (8,m/s,1) 2094 * - (8,e/o,1) 2095 */ 2096 while ((termios->c_cflag & CSIZE) != CS8 && 2097 (termios->c_cflag & CSIZE) != CS7) { 2098 termios->c_cflag &= ~CSIZE; 2099 termios->c_cflag |= old_csize; 2100 old_csize = CS8; 2101 } 2102 2103 if ((termios->c_cflag & CSIZE) == CS8 || 2104 (termios->c_cflag & CSIZE) == CS7) 2105 ctrl = old_ctrl & ~UARTCTRL_M; 2106 2107 if (termios->c_cflag & CMSPAR) { 2108 if ((termios->c_cflag & CSIZE) != CS8) { 2109 termios->c_cflag &= ~CSIZE; 2110 termios->c_cflag |= CS8; 2111 } 2112 ctrl |= UARTCTRL_M; 2113 } 2114 2115 /* 2116 * When auto RS-485 RTS mode is enabled, 2117 * hardware flow control need to be disabled. 2118 */ 2119 if (sport->port.rs485.flags & SER_RS485_ENABLED) 2120 termios->c_cflag &= ~CRTSCTS; 2121 2122 if (termios->c_cflag & CRTSCTS) 2123 modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE; 2124 else 2125 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 2126 2127 if (termios->c_cflag & CSTOPB) 2128 bd |= UARTBAUD_SBNS; 2129 else 2130 bd &= ~UARTBAUD_SBNS; 2131 2132 /* parity must be enabled when CS7 to match 8-bits format */ 2133 if ((termios->c_cflag & CSIZE) == CS7) 2134 termios->c_cflag |= PARENB; 2135 2136 if ((termios->c_cflag & PARENB)) { 2137 if (termios->c_cflag & CMSPAR) { 2138 ctrl &= ~UARTCTRL_PE; 2139 ctrl |= UARTCTRL_M; 2140 } else { 2141 ctrl |= UARTCTRL_PE; 2142 if ((termios->c_cflag & CSIZE) == CS8) 2143 ctrl |= UARTCTRL_M; 2144 if (termios->c_cflag & PARODD) 2145 ctrl |= UARTCTRL_PT; 2146 else 2147 ctrl &= ~UARTCTRL_PT; 2148 } 2149 } else { 2150 ctrl &= ~UARTCTRL_PE; 2151 } 2152 2153 /* ask the core to calculate the divisor */ 2154 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); 2155 2156 /* 2157 * Need to update the Ring buffer length according to the selected 2158 * baud rate and restart Rx DMA path. 2159 * 2160 * Since timer function acqures sport->port.lock, need to stop before 2161 * acquring same lock because otherwise del_timer_sync() can deadlock. 2162 */ 2163 if (old && sport->lpuart_dma_rx_use) { 2164 del_timer_sync(&sport->lpuart_timer); 2165 lpuart_dma_rx_free(&sport->port); 2166 } 2167 2168 spin_lock_irqsave(&sport->port.lock, flags); 2169 2170 sport->port.read_status_mask = 0; 2171 if (termios->c_iflag & INPCK) 2172 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; 2173 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2174 sport->port.read_status_mask |= UARTSTAT_FE; 2175 2176 /* characters to ignore */ 2177 sport->port.ignore_status_mask = 0; 2178 if (termios->c_iflag & IGNPAR) 2179 sport->port.ignore_status_mask |= UARTSTAT_PE; 2180 if (termios->c_iflag & IGNBRK) { 2181 sport->port.ignore_status_mask |= UARTSTAT_FE; 2182 /* 2183 * if we're ignoring parity and break indicators, 2184 * ignore overruns too (for real raw support). 2185 */ 2186 if (termios->c_iflag & IGNPAR) 2187 sport->port.ignore_status_mask |= UARTSTAT_OR; 2188 } 2189 2190 /* update the per-port timeout */ 2191 uart_update_timeout(port, termios->c_cflag, baud); 2192 2193 /* wait transmit engin complete */ 2194 lpuart32_write(&sport->port, 0, UARTMODIR); 2195 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2196 2197 /* disable transmit and receive */ 2198 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 2199 UARTCTRL); 2200 2201 lpuart32_write(&sport->port, bd, UARTBAUD); 2202 lpuart32_serial_setbrg(sport, baud); 2203 lpuart32_write(&sport->port, modem, UARTMODIR); 2204 lpuart32_write(&sport->port, ctrl, UARTCTRL); 2205 /* restore control register */ 2206 2207 if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE) 2208 sport->is_cs7 = true; 2209 2210 if (old && sport->lpuart_dma_rx_use) { 2211 if (!lpuart_start_rx_dma(sport)) 2212 rx_dma_timer_init(sport); 2213 else 2214 sport->lpuart_dma_rx_use = false; 2215 } 2216 2217 spin_unlock_irqrestore(&sport->port.lock, flags); 2218 } 2219 2220 static const char *lpuart_type(struct uart_port *port) 2221 { 2222 return "FSL_LPUART"; 2223 } 2224 2225 static void lpuart_release_port(struct uart_port *port) 2226 { 2227 /* nothing to do */ 2228 } 2229 2230 static int lpuart_request_port(struct uart_port *port) 2231 { 2232 return 0; 2233 } 2234 2235 /* configure/autoconfigure the port */ 2236 static void lpuart_config_port(struct uart_port *port, int flags) 2237 { 2238 if (flags & UART_CONFIG_TYPE) 2239 port->type = PORT_LPUART; 2240 } 2241 2242 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 2243 { 2244 int ret = 0; 2245 2246 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 2247 ret = -EINVAL; 2248 if (port->irq != ser->irq) 2249 ret = -EINVAL; 2250 if (ser->io_type != UPIO_MEM) 2251 ret = -EINVAL; 2252 if (port->uartclk / 16 != ser->baud_base) 2253 ret = -EINVAL; 2254 if (port->iobase != ser->port) 2255 ret = -EINVAL; 2256 if (ser->hub6 != 0) 2257 ret = -EINVAL; 2258 return ret; 2259 } 2260 2261 static const struct uart_ops lpuart_pops = { 2262 .tx_empty = lpuart_tx_empty, 2263 .set_mctrl = lpuart_set_mctrl, 2264 .get_mctrl = lpuart_get_mctrl, 2265 .stop_tx = lpuart_stop_tx, 2266 .start_tx = lpuart_start_tx, 2267 .stop_rx = lpuart_stop_rx, 2268 .break_ctl = lpuart_break_ctl, 2269 .startup = lpuart_startup, 2270 .shutdown = lpuart_shutdown, 2271 .set_termios = lpuart_set_termios, 2272 .type = lpuart_type, 2273 .request_port = lpuart_request_port, 2274 .release_port = lpuart_release_port, 2275 .config_port = lpuart_config_port, 2276 .verify_port = lpuart_verify_port, 2277 .flush_buffer = lpuart_flush_buffer, 2278 #if defined(CONFIG_CONSOLE_POLL) 2279 .poll_init = lpuart_poll_init, 2280 .poll_get_char = lpuart_poll_get_char, 2281 .poll_put_char = lpuart_poll_put_char, 2282 #endif 2283 }; 2284 2285 static const struct uart_ops lpuart32_pops = { 2286 .tx_empty = lpuart32_tx_empty, 2287 .set_mctrl = lpuart32_set_mctrl, 2288 .get_mctrl = lpuart32_get_mctrl, 2289 .stop_tx = lpuart32_stop_tx, 2290 .start_tx = lpuart32_start_tx, 2291 .stop_rx = lpuart32_stop_rx, 2292 .break_ctl = lpuart32_break_ctl, 2293 .startup = lpuart32_startup, 2294 .shutdown = lpuart32_shutdown, 2295 .set_termios = lpuart32_set_termios, 2296 .type = lpuart_type, 2297 .request_port = lpuart_request_port, 2298 .release_port = lpuart_release_port, 2299 .config_port = lpuart_config_port, 2300 .verify_port = lpuart_verify_port, 2301 .flush_buffer = lpuart_flush_buffer, 2302 #if defined(CONFIG_CONSOLE_POLL) 2303 .poll_init = lpuart32_poll_init, 2304 .poll_get_char = lpuart32_poll_get_char, 2305 .poll_put_char = lpuart32_poll_put_char, 2306 #endif 2307 }; 2308 2309 static struct lpuart_port *lpuart_ports[UART_NR]; 2310 2311 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 2312 static void lpuart_console_putchar(struct uart_port *port, unsigned char ch) 2313 { 2314 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 2315 writeb(ch, port->membase + UARTDR); 2316 } 2317 2318 static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch) 2319 { 2320 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 2321 lpuart32_write(port, ch, UARTDATA); 2322 } 2323 2324 static void 2325 lpuart_console_write(struct console *co, const char *s, unsigned int count) 2326 { 2327 struct lpuart_port *sport = lpuart_ports[co->index]; 2328 unsigned char old_cr2, cr2; 2329 unsigned long flags; 2330 int locked = 1; 2331 2332 if (oops_in_progress) 2333 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2334 else 2335 spin_lock_irqsave(&sport->port.lock, flags); 2336 2337 /* first save CR2 and then disable interrupts */ 2338 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 2339 cr2 |= UARTCR2_TE | UARTCR2_RE; 2340 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 2341 writeb(cr2, sport->port.membase + UARTCR2); 2342 2343 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 2344 2345 /* wait for transmitter finish complete and restore CR2 */ 2346 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 2347 2348 writeb(old_cr2, sport->port.membase + UARTCR2); 2349 2350 if (locked) 2351 spin_unlock_irqrestore(&sport->port.lock, flags); 2352 } 2353 2354 static void 2355 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 2356 { 2357 struct lpuart_port *sport = lpuart_ports[co->index]; 2358 unsigned long old_cr, cr; 2359 unsigned long flags; 2360 int locked = 1; 2361 2362 if (oops_in_progress) 2363 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2364 else 2365 spin_lock_irqsave(&sport->port.lock, flags); 2366 2367 /* first save CR2 and then disable interrupts */ 2368 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 2369 cr |= UARTCTRL_TE | UARTCTRL_RE; 2370 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 2371 lpuart32_write(&sport->port, cr, UARTCTRL); 2372 2373 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 2374 2375 /* wait for transmitter finish complete and restore CR2 */ 2376 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2377 2378 lpuart32_write(&sport->port, old_cr, UARTCTRL); 2379 2380 if (locked) 2381 spin_unlock_irqrestore(&sport->port.lock, flags); 2382 } 2383 2384 /* 2385 * if the port was already initialised (eg, by a boot loader), 2386 * try to determine the current setup. 2387 */ 2388 static void __init 2389 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 2390 int *parity, int *bits) 2391 { 2392 unsigned char cr, bdh, bdl, brfa; 2393 unsigned int sbr, uartclk, baud_raw; 2394 2395 cr = readb(sport->port.membase + UARTCR2); 2396 cr &= UARTCR2_TE | UARTCR2_RE; 2397 if (!cr) 2398 return; 2399 2400 /* ok, the port was enabled */ 2401 2402 cr = readb(sport->port.membase + UARTCR1); 2403 2404 *parity = 'n'; 2405 if (cr & UARTCR1_PE) { 2406 if (cr & UARTCR1_PT) 2407 *parity = 'o'; 2408 else 2409 *parity = 'e'; 2410 } 2411 2412 if (cr & UARTCR1_M) 2413 *bits = 9; 2414 else 2415 *bits = 8; 2416 2417 bdh = readb(sport->port.membase + UARTBDH); 2418 bdh &= UARTBDH_SBR_MASK; 2419 bdl = readb(sport->port.membase + UARTBDL); 2420 sbr = bdh; 2421 sbr <<= 8; 2422 sbr |= bdl; 2423 brfa = readb(sport->port.membase + UARTCR4); 2424 brfa &= UARTCR4_BRFA_MASK; 2425 2426 uartclk = lpuart_get_baud_clk_rate(sport); 2427 /* 2428 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2429 */ 2430 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 2431 2432 if (*baud != baud_raw) 2433 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2434 "from %d to %d\n", baud_raw, *baud); 2435 } 2436 2437 static void __init 2438 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 2439 int *parity, int *bits) 2440 { 2441 unsigned long cr, bd; 2442 unsigned int sbr, uartclk, baud_raw; 2443 2444 cr = lpuart32_read(&sport->port, UARTCTRL); 2445 cr &= UARTCTRL_TE | UARTCTRL_RE; 2446 if (!cr) 2447 return; 2448 2449 /* ok, the port was enabled */ 2450 2451 cr = lpuart32_read(&sport->port, UARTCTRL); 2452 2453 *parity = 'n'; 2454 if (cr & UARTCTRL_PE) { 2455 if (cr & UARTCTRL_PT) 2456 *parity = 'o'; 2457 else 2458 *parity = 'e'; 2459 } 2460 2461 if (cr & UARTCTRL_M) 2462 *bits = 9; 2463 else 2464 *bits = 8; 2465 2466 bd = lpuart32_read(&sport->port, UARTBAUD); 2467 bd &= UARTBAUD_SBR_MASK; 2468 if (!bd) 2469 return; 2470 2471 sbr = bd; 2472 uartclk = lpuart_get_baud_clk_rate(sport); 2473 /* 2474 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2475 */ 2476 baud_raw = uartclk / (16 * sbr); 2477 2478 if (*baud != baud_raw) 2479 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2480 "from %d to %d\n", baud_raw, *baud); 2481 } 2482 2483 static int __init lpuart_console_setup(struct console *co, char *options) 2484 { 2485 struct lpuart_port *sport; 2486 int baud = 115200; 2487 int bits = 8; 2488 int parity = 'n'; 2489 int flow = 'n'; 2490 2491 /* 2492 * check whether an invalid uart number has been specified, and 2493 * if so, search for the first available port that does have 2494 * console support. 2495 */ 2496 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2497 co->index = 0; 2498 2499 sport = lpuart_ports[co->index]; 2500 if (sport == NULL) 2501 return -ENODEV; 2502 2503 if (options) 2504 uart_parse_options(options, &baud, &parity, &bits, &flow); 2505 else 2506 if (lpuart_is_32(sport)) 2507 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2508 else 2509 lpuart_console_get_options(sport, &baud, &parity, &bits); 2510 2511 if (lpuart_is_32(sport)) 2512 lpuart32_setup_watermark(sport); 2513 else 2514 lpuart_setup_watermark(sport); 2515 2516 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2517 } 2518 2519 static struct uart_driver lpuart_reg; 2520 static struct console lpuart_console = { 2521 .name = DEV_NAME, 2522 .write = lpuart_console_write, 2523 .device = uart_console_device, 2524 .setup = lpuart_console_setup, 2525 .flags = CON_PRINTBUFFER, 2526 .index = -1, 2527 .data = &lpuart_reg, 2528 }; 2529 2530 static struct console lpuart32_console = { 2531 .name = DEV_NAME, 2532 .write = lpuart32_console_write, 2533 .device = uart_console_device, 2534 .setup = lpuart_console_setup, 2535 .flags = CON_PRINTBUFFER, 2536 .index = -1, 2537 .data = &lpuart_reg, 2538 }; 2539 2540 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2541 { 2542 struct earlycon_device *dev = con->data; 2543 2544 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2545 } 2546 2547 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2548 { 2549 struct earlycon_device *dev = con->data; 2550 2551 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2552 } 2553 2554 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2555 const char *opt) 2556 { 2557 if (!device->port.membase) 2558 return -ENODEV; 2559 2560 device->con->write = lpuart_early_write; 2561 return 0; 2562 } 2563 2564 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2565 const char *opt) 2566 { 2567 if (!device->port.membase) 2568 return -ENODEV; 2569 2570 if (device->port.iotype != UPIO_MEM32) 2571 device->port.iotype = UPIO_MEM32BE; 2572 2573 device->con->write = lpuart32_early_write; 2574 return 0; 2575 } 2576 2577 static int __init ls1028a_early_console_setup(struct earlycon_device *device, 2578 const char *opt) 2579 { 2580 u32 cr; 2581 2582 if (!device->port.membase) 2583 return -ENODEV; 2584 2585 device->port.iotype = UPIO_MEM32; 2586 device->con->write = lpuart32_early_write; 2587 2588 /* set the baudrate */ 2589 if (device->port.uartclk && device->baud) 2590 __lpuart32_serial_setbrg(&device->port, device->baud, 2591 false, false); 2592 2593 /* enable transmitter */ 2594 cr = lpuart32_read(&device->port, UARTCTRL); 2595 cr |= UARTCTRL_TE; 2596 lpuart32_write(&device->port, cr, UARTCTRL); 2597 2598 return 0; 2599 } 2600 2601 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2602 const char *opt) 2603 { 2604 if (!device->port.membase) 2605 return -ENODEV; 2606 2607 device->port.iotype = UPIO_MEM32; 2608 device->port.membase += IMX_REG_OFF; 2609 device->con->write = lpuart32_early_write; 2610 2611 return 0; 2612 } 2613 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2614 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2615 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup); 2616 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2617 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup); 2618 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup); 2619 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2620 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2621 2622 #define LPUART_CONSOLE (&lpuart_console) 2623 #define LPUART32_CONSOLE (&lpuart32_console) 2624 #else 2625 #define LPUART_CONSOLE NULL 2626 #define LPUART32_CONSOLE NULL 2627 #endif 2628 2629 static struct uart_driver lpuart_reg = { 2630 .owner = THIS_MODULE, 2631 .driver_name = DRIVER_NAME, 2632 .dev_name = DEV_NAME, 2633 .nr = ARRAY_SIZE(lpuart_ports), 2634 .cons = LPUART_CONSOLE, 2635 }; 2636 2637 static const struct serial_rs485 lpuart_rs485_supported = { 2638 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND, 2639 /* delay_rts_* and RX_DURING_TX are not supported */ 2640 }; 2641 2642 static int lpuart_probe(struct platform_device *pdev) 2643 { 2644 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev); 2645 struct device_node *np = pdev->dev.of_node; 2646 struct lpuart_port *sport; 2647 struct resource *res; 2648 irq_handler_t handler; 2649 int ret; 2650 2651 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2652 if (!sport) 2653 return -ENOMEM; 2654 2655 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2656 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 2657 if (IS_ERR(sport->port.membase)) 2658 return PTR_ERR(sport->port.membase); 2659 2660 sport->port.membase += sdata->reg_off; 2661 sport->port.mapbase = res->start + sdata->reg_off; 2662 sport->port.dev = &pdev->dev; 2663 sport->port.type = PORT_LPUART; 2664 sport->devtype = sdata->devtype; 2665 ret = platform_get_irq(pdev, 0); 2666 if (ret < 0) 2667 return ret; 2668 sport->port.irq = ret; 2669 sport->port.iotype = sdata->iotype; 2670 if (lpuart_is_32(sport)) 2671 sport->port.ops = &lpuart32_pops; 2672 else 2673 sport->port.ops = &lpuart_pops; 2674 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); 2675 sport->port.flags = UPF_BOOT_AUTOCONF; 2676 2677 if (lpuart_is_32(sport)) 2678 sport->port.rs485_config = lpuart32_config_rs485; 2679 else 2680 sport->port.rs485_config = lpuart_config_rs485; 2681 sport->port.rs485_supported = lpuart_rs485_supported; 2682 2683 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 2684 if (IS_ERR(sport->ipg_clk)) { 2685 ret = PTR_ERR(sport->ipg_clk); 2686 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); 2687 return ret; 2688 } 2689 2690 sport->baud_clk = NULL; 2691 if (is_imx8qxp_lpuart(sport)) { 2692 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); 2693 if (IS_ERR(sport->baud_clk)) { 2694 ret = PTR_ERR(sport->baud_clk); 2695 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); 2696 return ret; 2697 } 2698 } 2699 2700 ret = of_alias_get_id(np, "serial"); 2701 if (ret < 0) { 2702 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2703 return ret; 2704 } 2705 if (ret >= ARRAY_SIZE(lpuart_ports)) { 2706 dev_err(&pdev->dev, "serial%d out of range\n", ret); 2707 return -EINVAL; 2708 } 2709 sport->port.line = ret; 2710 2711 ret = lpuart_enable_clks(sport); 2712 if (ret) 2713 return ret; 2714 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); 2715 2716 lpuart_ports[sport->port.line] = sport; 2717 2718 platform_set_drvdata(pdev, &sport->port); 2719 2720 if (lpuart_is_32(sport)) { 2721 lpuart_reg.cons = LPUART32_CONSOLE; 2722 handler = lpuart32_int; 2723 } else { 2724 lpuart_reg.cons = LPUART_CONSOLE; 2725 handler = lpuart_int; 2726 } 2727 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2728 if (ret) 2729 goto failed_attach_port; 2730 2731 ret = lpuart_global_reset(sport); 2732 if (ret) 2733 goto failed_reset; 2734 2735 ret = uart_get_rs485_mode(&sport->port); 2736 if (ret) 2737 goto failed_get_rs485; 2738 2739 uart_rs485_config(&sport->port); 2740 2741 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0, 2742 DRIVER_NAME, sport); 2743 if (ret) 2744 goto failed_irq_request; 2745 2746 return 0; 2747 2748 failed_irq_request: 2749 failed_get_rs485: 2750 failed_reset: 2751 uart_remove_one_port(&lpuart_reg, &sport->port); 2752 failed_attach_port: 2753 lpuart_disable_clks(sport); 2754 return ret; 2755 } 2756 2757 static int lpuart_remove(struct platform_device *pdev) 2758 { 2759 struct lpuart_port *sport = platform_get_drvdata(pdev); 2760 2761 uart_remove_one_port(&lpuart_reg, &sport->port); 2762 2763 lpuart_disable_clks(sport); 2764 2765 if (sport->dma_tx_chan) 2766 dma_release_channel(sport->dma_tx_chan); 2767 2768 if (sport->dma_rx_chan) 2769 dma_release_channel(sport->dma_rx_chan); 2770 2771 return 0; 2772 } 2773 2774 static int __maybe_unused lpuart_suspend(struct device *dev) 2775 { 2776 struct lpuart_port *sport = dev_get_drvdata(dev); 2777 unsigned long temp; 2778 bool irq_wake; 2779 2780 if (lpuart_is_32(sport)) { 2781 /* disable Rx/Tx and interrupts */ 2782 temp = lpuart32_read(&sport->port, UARTCTRL); 2783 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2784 lpuart32_write(&sport->port, temp, UARTCTRL); 2785 } else { 2786 /* disable Rx/Tx and interrupts */ 2787 temp = readb(sport->port.membase + UARTCR2); 2788 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2789 writeb(temp, sport->port.membase + UARTCR2); 2790 } 2791 2792 uart_suspend_port(&lpuart_reg, &sport->port); 2793 2794 /* uart_suspend_port() might set wakeup flag */ 2795 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2796 2797 if (sport->lpuart_dma_rx_use) { 2798 /* 2799 * EDMA driver during suspend will forcefully release any 2800 * non-idle DMA channels. If port wakeup is enabled or if port 2801 * is console port or 'no_console_suspend' is set the Rx DMA 2802 * cannot resume as as expected, hence gracefully release the 2803 * Rx DMA path before suspend and start Rx DMA path on resume. 2804 */ 2805 if (irq_wake) { 2806 del_timer_sync(&sport->lpuart_timer); 2807 lpuart_dma_rx_free(&sport->port); 2808 } 2809 2810 /* Disable Rx DMA to use UART port as wakeup source */ 2811 if (lpuart_is_32(sport)) { 2812 temp = lpuart32_read(&sport->port, UARTBAUD); 2813 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, 2814 UARTBAUD); 2815 } else { 2816 writeb(readb(sport->port.membase + UARTCR5) & 2817 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 2818 } 2819 } 2820 2821 if (sport->lpuart_dma_tx_use) { 2822 sport->dma_tx_in_progress = false; 2823 dmaengine_terminate_all(sport->dma_tx_chan); 2824 } 2825 2826 if (sport->port.suspended && !irq_wake) 2827 lpuart_disable_clks(sport); 2828 2829 return 0; 2830 } 2831 2832 static int __maybe_unused lpuart_resume(struct device *dev) 2833 { 2834 struct lpuart_port *sport = dev_get_drvdata(dev); 2835 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2836 2837 if (sport->port.suspended && !irq_wake) 2838 lpuart_enable_clks(sport); 2839 2840 if (lpuart_is_32(sport)) 2841 lpuart32_setup_watermark_enable(sport); 2842 else 2843 lpuart_setup_watermark_enable(sport); 2844 2845 if (sport->lpuart_dma_rx_use) { 2846 if (irq_wake) { 2847 if (!lpuart_start_rx_dma(sport)) 2848 rx_dma_timer_init(sport); 2849 else 2850 sport->lpuart_dma_rx_use = false; 2851 } 2852 } 2853 2854 lpuart_tx_dma_startup(sport); 2855 2856 if (lpuart_is_32(sport)) 2857 lpuart32_configure(sport); 2858 2859 uart_resume_port(&lpuart_reg, &sport->port); 2860 2861 return 0; 2862 } 2863 2864 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2865 2866 static struct platform_driver lpuart_driver = { 2867 .probe = lpuart_probe, 2868 .remove = lpuart_remove, 2869 .driver = { 2870 .name = "fsl-lpuart", 2871 .of_match_table = lpuart_dt_ids, 2872 .pm = &lpuart_pm_ops, 2873 }, 2874 }; 2875 2876 static int __init lpuart_serial_init(void) 2877 { 2878 int ret = uart_register_driver(&lpuart_reg); 2879 2880 if (ret) 2881 return ret; 2882 2883 ret = platform_driver_register(&lpuart_driver); 2884 if (ret) 2885 uart_unregister_driver(&lpuart_reg); 2886 2887 return ret; 2888 } 2889 2890 static void __exit lpuart_serial_exit(void) 2891 { 2892 platform_driver_unregister(&lpuart_driver); 2893 uart_unregister_driver(&lpuart_reg); 2894 } 2895 2896 module_init(lpuart_serial_init); 2897 module_exit(lpuart_serial_exit); 2898 2899 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2900 MODULE_LICENSE("GPL v2"); 2901