1 /* 2 * Driver for CLPS711x serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright 1999 ARM Limited 7 * Copyright (C) 2000 Deep Blue Solutions Ltd. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 16 #define SUPPORT_SYSRQ 17 #endif 18 19 #include <linux/module.h> 20 #include <linux/device.h> 21 #include <linux/console.h> 22 #include <linux/serial_core.h> 23 #include <linux/serial.h> 24 #include <linux/clk.h> 25 #include <linux/io.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/ioport.h> 29 #include <linux/of.h> 30 #include <linux/platform_device.h> 31 #include <linux/regmap.h> 32 33 #include <linux/mfd/syscon.h> 34 #include <linux/mfd/syscon/clps711x.h> 35 36 #define UART_CLPS711X_DEVNAME "ttyCL" 37 #define UART_CLPS711X_NR 2 38 #define UART_CLPS711X_MAJOR 204 39 #define UART_CLPS711X_MINOR 40 40 41 #define UARTDR_OFFSET (0x00) 42 #define UBRLCR_OFFSET (0x40) 43 44 #define UARTDR_FRMERR (1 << 8) 45 #define UARTDR_PARERR (1 << 9) 46 #define UARTDR_OVERR (1 << 10) 47 48 #define UBRLCR_BAUD_MASK ((1 << 12) - 1) 49 #define UBRLCR_BREAK (1 << 12) 50 #define UBRLCR_PRTEN (1 << 13) 51 #define UBRLCR_EVENPRT (1 << 14) 52 #define UBRLCR_XSTOP (1 << 15) 53 #define UBRLCR_FIFOEN (1 << 16) 54 #define UBRLCR_WRDLEN5 (0 << 17) 55 #define UBRLCR_WRDLEN6 (1 << 17) 56 #define UBRLCR_WRDLEN7 (2 << 17) 57 #define UBRLCR_WRDLEN8 (3 << 17) 58 #define UBRLCR_WRDLEN_MASK (3 << 17) 59 60 struct clps711x_port { 61 struct uart_port port; 62 unsigned int tx_enabled; 63 int rx_irq; 64 struct regmap *syscon; 65 bool use_ms; 66 }; 67 68 static struct uart_driver clps711x_uart = { 69 .owner = THIS_MODULE, 70 .driver_name = UART_CLPS711X_DEVNAME, 71 .dev_name = UART_CLPS711X_DEVNAME, 72 .major = UART_CLPS711X_MAJOR, 73 .minor = UART_CLPS711X_MINOR, 74 .nr = UART_CLPS711X_NR, 75 }; 76 77 static void uart_clps711x_stop_tx(struct uart_port *port) 78 { 79 struct clps711x_port *s = dev_get_drvdata(port->dev); 80 81 if (s->tx_enabled) { 82 disable_irq(port->irq); 83 s->tx_enabled = 0; 84 } 85 } 86 87 static void uart_clps711x_start_tx(struct uart_port *port) 88 { 89 struct clps711x_port *s = dev_get_drvdata(port->dev); 90 91 if (!s->tx_enabled) { 92 s->tx_enabled = 1; 93 enable_irq(port->irq); 94 } 95 } 96 97 static irqreturn_t uart_clps711x_int_rx(int irq, void *dev_id) 98 { 99 struct uart_port *port = dev_id; 100 struct clps711x_port *s = dev_get_drvdata(port->dev); 101 unsigned int status, flg; 102 u32 sysflg; 103 u16 ch; 104 105 for (;;) { 106 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 107 if (sysflg & SYSFLG_URXFE) 108 break; 109 110 ch = readw_relaxed(port->membase + UARTDR_OFFSET); 111 status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR); 112 ch &= 0xff; 113 114 port->icount.rx++; 115 flg = TTY_NORMAL; 116 117 if (unlikely(status)) { 118 if (status & UARTDR_PARERR) 119 port->icount.parity++; 120 else if (status & UARTDR_FRMERR) 121 port->icount.frame++; 122 else if (status & UARTDR_OVERR) 123 port->icount.overrun++; 124 125 status &= port->read_status_mask; 126 127 if (status & UARTDR_PARERR) 128 flg = TTY_PARITY; 129 else if (status & UARTDR_FRMERR) 130 flg = TTY_FRAME; 131 else if (status & UARTDR_OVERR) 132 flg = TTY_OVERRUN; 133 } 134 135 if (uart_handle_sysrq_char(port, ch)) 136 continue; 137 138 if (status & port->ignore_status_mask) 139 continue; 140 141 uart_insert_char(port, status, UARTDR_OVERR, ch, flg); 142 } 143 144 tty_flip_buffer_push(&port->state->port); 145 146 return IRQ_HANDLED; 147 } 148 149 static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id) 150 { 151 struct uart_port *port = dev_id; 152 struct clps711x_port *s = dev_get_drvdata(port->dev); 153 struct circ_buf *xmit = &port->state->xmit; 154 u32 sysflg; 155 156 if (port->x_char) { 157 writew_relaxed(port->x_char, port->membase + UARTDR_OFFSET); 158 port->icount.tx++; 159 port->x_char = 0; 160 return IRQ_HANDLED; 161 } 162 163 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 164 if (s->tx_enabled) { 165 disable_irq_nosync(port->irq); 166 s->tx_enabled = 0; 167 } 168 return IRQ_HANDLED; 169 } 170 171 while (!uart_circ_empty(xmit)) { 172 writew_relaxed(xmit->buf[xmit->tail], 173 port->membase + UARTDR_OFFSET); 174 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 175 port->icount.tx++; 176 177 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 178 if (sysflg & SYSFLG_UTXFF) 179 break; 180 } 181 182 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 183 uart_write_wakeup(port); 184 185 return IRQ_HANDLED; 186 } 187 188 static unsigned int uart_clps711x_tx_empty(struct uart_port *port) 189 { 190 struct clps711x_port *s = dev_get_drvdata(port->dev); 191 u32 sysflg; 192 193 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 194 195 return (sysflg & SYSFLG_UBUSY) ? 0 : TIOCSER_TEMT; 196 } 197 198 static unsigned int uart_clps711x_get_mctrl(struct uart_port *port) 199 { 200 struct clps711x_port *s = dev_get_drvdata(port->dev); 201 unsigned int result = 0; 202 u32 sysflg; 203 204 if (s->use_ms) { 205 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 206 if (sysflg & SYSFLG1_DCD) 207 result |= TIOCM_CAR; 208 if (sysflg & SYSFLG1_DSR) 209 result |= TIOCM_DSR; 210 if (sysflg & SYSFLG1_CTS) 211 result |= TIOCM_CTS; 212 } else 213 result = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; 214 215 return result; 216 } 217 218 static void uart_clps711x_set_mctrl(struct uart_port *port, unsigned int mctrl) 219 { 220 /* Do nothing */ 221 } 222 223 static void uart_clps711x_break_ctl(struct uart_port *port, int break_state) 224 { 225 unsigned int ubrlcr; 226 227 ubrlcr = readl_relaxed(port->membase + UBRLCR_OFFSET); 228 if (break_state) 229 ubrlcr |= UBRLCR_BREAK; 230 else 231 ubrlcr &= ~UBRLCR_BREAK; 232 writel_relaxed(ubrlcr, port->membase + UBRLCR_OFFSET); 233 } 234 235 static int uart_clps711x_startup(struct uart_port *port) 236 { 237 struct clps711x_port *s = dev_get_drvdata(port->dev); 238 239 /* Disable break */ 240 writel_relaxed(readl_relaxed(port->membase + UBRLCR_OFFSET) & 241 ~UBRLCR_BREAK, port->membase + UBRLCR_OFFSET); 242 243 /* Enable the port */ 244 return regmap_update_bits(s->syscon, SYSCON_OFFSET, 245 SYSCON_UARTEN, SYSCON_UARTEN); 246 } 247 248 static void uart_clps711x_shutdown(struct uart_port *port) 249 { 250 struct clps711x_port *s = dev_get_drvdata(port->dev); 251 252 /* Disable the port */ 253 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0); 254 } 255 256 static void uart_clps711x_set_termios(struct uart_port *port, 257 struct ktermios *termios, 258 struct ktermios *old) 259 { 260 u32 ubrlcr; 261 unsigned int baud, quot; 262 263 /* Mask termios capabilities we don't support */ 264 termios->c_cflag &= ~CMSPAR; 265 termios->c_iflag &= ~(BRKINT | IGNBRK); 266 267 /* Ask the core to calculate the divisor for us */ 268 baud = uart_get_baud_rate(port, termios, old, port->uartclk / 4096, 269 port->uartclk / 16); 270 quot = uart_get_divisor(port, baud); 271 272 switch (termios->c_cflag & CSIZE) { 273 case CS5: 274 ubrlcr = UBRLCR_WRDLEN5; 275 break; 276 case CS6: 277 ubrlcr = UBRLCR_WRDLEN6; 278 break; 279 case CS7: 280 ubrlcr = UBRLCR_WRDLEN7; 281 break; 282 case CS8: 283 default: 284 ubrlcr = UBRLCR_WRDLEN8; 285 break; 286 } 287 288 if (termios->c_cflag & CSTOPB) 289 ubrlcr |= UBRLCR_XSTOP; 290 291 if (termios->c_cflag & PARENB) { 292 ubrlcr |= UBRLCR_PRTEN; 293 if (!(termios->c_cflag & PARODD)) 294 ubrlcr |= UBRLCR_EVENPRT; 295 } 296 297 /* Enable FIFO */ 298 ubrlcr |= UBRLCR_FIFOEN; 299 300 /* Set read status mask */ 301 port->read_status_mask = UARTDR_OVERR; 302 if (termios->c_iflag & INPCK) 303 port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR; 304 305 /* Set status ignore mask */ 306 port->ignore_status_mask = 0; 307 if (!(termios->c_cflag & CREAD)) 308 port->ignore_status_mask |= UARTDR_OVERR | UARTDR_PARERR | 309 UARTDR_FRMERR; 310 311 uart_update_timeout(port, termios->c_cflag, baud); 312 313 writel_relaxed(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET); 314 } 315 316 static const char *uart_clps711x_type(struct uart_port *port) 317 { 318 return (port->type == PORT_CLPS711X) ? "CLPS711X" : NULL; 319 } 320 321 static void uart_clps711x_config_port(struct uart_port *port, int flags) 322 { 323 if (flags & UART_CONFIG_TYPE) 324 port->type = PORT_CLPS711X; 325 } 326 327 static void uart_clps711x_nop_void(struct uart_port *port) 328 { 329 } 330 331 static int uart_clps711x_nop_int(struct uart_port *port) 332 { 333 return 0; 334 } 335 336 static const struct uart_ops uart_clps711x_ops = { 337 .tx_empty = uart_clps711x_tx_empty, 338 .set_mctrl = uart_clps711x_set_mctrl, 339 .get_mctrl = uart_clps711x_get_mctrl, 340 .stop_tx = uart_clps711x_stop_tx, 341 .start_tx = uart_clps711x_start_tx, 342 .stop_rx = uart_clps711x_nop_void, 343 .enable_ms = uart_clps711x_nop_void, 344 .break_ctl = uart_clps711x_break_ctl, 345 .startup = uart_clps711x_startup, 346 .shutdown = uart_clps711x_shutdown, 347 .set_termios = uart_clps711x_set_termios, 348 .type = uart_clps711x_type, 349 .config_port = uart_clps711x_config_port, 350 .release_port = uart_clps711x_nop_void, 351 .request_port = uart_clps711x_nop_int, 352 }; 353 354 #ifdef CONFIG_SERIAL_CLPS711X_CONSOLE 355 static void uart_clps711x_console_putchar(struct uart_port *port, int ch) 356 { 357 struct clps711x_port *s = dev_get_drvdata(port->dev); 358 u32 sysflg; 359 360 do { 361 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 362 } while (sysflg & SYSFLG_UTXFF); 363 364 writew_relaxed(ch, port->membase + UARTDR_OFFSET); 365 } 366 367 static void uart_clps711x_console_write(struct console *co, const char *c, 368 unsigned n) 369 { 370 struct uart_port *port = clps711x_uart.state[co->index].uart_port; 371 struct clps711x_port *s = dev_get_drvdata(port->dev); 372 u32 sysflg; 373 374 uart_console_write(port, c, n, uart_clps711x_console_putchar); 375 376 /* Wait for transmitter to become empty */ 377 do { 378 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 379 } while (sysflg & SYSFLG_UBUSY); 380 } 381 382 static int uart_clps711x_console_setup(struct console *co, char *options) 383 { 384 int baud = 38400, bits = 8, parity = 'n', flow = 'n'; 385 int ret, index = co->index; 386 struct clps711x_port *s; 387 struct uart_port *port; 388 u32 ubrlcr, syscon; 389 unsigned int quot; 390 391 if (index < 0 || index >= UART_CLPS711X_NR) 392 return -EINVAL; 393 394 port = clps711x_uart.state[index].uart_port; 395 if (!port) 396 return -ENODEV; 397 398 s = dev_get_drvdata(port->dev); 399 400 if (!options) { 401 regmap_read(s->syscon, SYSCON_OFFSET, &syscon); 402 if (syscon & SYSCON_UARTEN) { 403 ubrlcr = readl_relaxed(port->membase + UBRLCR_OFFSET); 404 405 if (ubrlcr & UBRLCR_PRTEN) { 406 if (ubrlcr & UBRLCR_EVENPRT) 407 parity = 'e'; 408 else 409 parity = 'o'; 410 } 411 412 if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7) 413 bits = 7; 414 415 quot = ubrlcr & UBRLCR_BAUD_MASK; 416 baud = port->uartclk / (16 * (quot + 1)); 417 } 418 } else 419 uart_parse_options(options, &baud, &parity, &bits, &flow); 420 421 ret = uart_set_options(port, co, baud, parity, bits, flow); 422 if (ret) 423 return ret; 424 425 return regmap_update_bits(s->syscon, SYSCON_OFFSET, 426 SYSCON_UARTEN, SYSCON_UARTEN); 427 } 428 429 static struct console clps711x_console = { 430 .name = UART_CLPS711X_DEVNAME, 431 .device = uart_console_device, 432 .write = uart_clps711x_console_write, 433 .setup = uart_clps711x_console_setup, 434 .flags = CON_PRINTBUFFER, 435 .index = -1, 436 }; 437 #endif 438 439 static int uart_clps711x_probe(struct platform_device *pdev) 440 { 441 struct device_node *np = pdev->dev.of_node; 442 int ret, index = np ? of_alias_get_id(np, "serial") : pdev->id; 443 struct clps711x_port *s; 444 struct resource *res; 445 struct clk *uart_clk; 446 447 if (index < 0 || index >= UART_CLPS711X_NR) 448 return -EINVAL; 449 450 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL); 451 if (!s) 452 return -ENOMEM; 453 454 uart_clk = devm_clk_get(&pdev->dev, NULL); 455 if (IS_ERR(uart_clk)) 456 return PTR_ERR(uart_clk); 457 458 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 459 s->port.membase = devm_ioremap_resource(&pdev->dev, res); 460 if (IS_ERR(s->port.membase)) 461 return PTR_ERR(s->port.membase); 462 463 s->port.irq = platform_get_irq(pdev, 0); 464 if (IS_ERR_VALUE(s->port.irq)) 465 return s->port.irq; 466 467 s->rx_irq = platform_get_irq(pdev, 1); 468 if (IS_ERR_VALUE(s->rx_irq)) 469 return s->rx_irq; 470 471 if (!np) { 472 char syscon_name[9]; 473 474 sprintf(syscon_name, "syscon.%i", index + 1); 475 s->syscon = syscon_regmap_lookup_by_pdevname(syscon_name); 476 if (IS_ERR(s->syscon)) 477 return PTR_ERR(s->syscon); 478 479 s->use_ms = !index; 480 } else { 481 s->syscon = syscon_regmap_lookup_by_phandle(np, "syscon"); 482 if (IS_ERR(s->syscon)) 483 return PTR_ERR(s->syscon); 484 485 if (!index) { 486 bool use_irda; 487 488 s->use_ms = of_property_read_bool(np, "uart-use-ms"); 489 use_irda = of_property_read_bool(np, "uart-use-irda"); 490 regmap_update_bits(s->syscon, SYSCON_OFFSET, 491 SYSCON1_SIREN, 492 use_irda ? SYSCON1_SIREN : 0); 493 } 494 } 495 496 s->port.line = index; 497 s->port.dev = &pdev->dev; 498 s->port.iotype = UPIO_MEM32; 499 s->port.mapbase = res->start; 500 s->port.type = PORT_CLPS711X; 501 s->port.fifosize = 16; 502 s->port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; 503 s->port.uartclk = clk_get_rate(uart_clk); 504 s->port.ops = &uart_clps711x_ops; 505 506 platform_set_drvdata(pdev, s); 507 508 ret = uart_add_one_port(&clps711x_uart, &s->port); 509 if (ret) 510 return ret; 511 512 /* Disable port */ 513 if (!uart_console(&s->port)) 514 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0); 515 516 s->tx_enabled = 1; 517 518 ret = devm_request_irq(&pdev->dev, s->port.irq, uart_clps711x_int_tx, 0, 519 dev_name(&pdev->dev), &s->port); 520 if (ret) { 521 uart_remove_one_port(&clps711x_uart, &s->port); 522 return ret; 523 } 524 525 ret = devm_request_irq(&pdev->dev, s->rx_irq, uart_clps711x_int_rx, 0, 526 dev_name(&pdev->dev), &s->port); 527 if (ret) 528 uart_remove_one_port(&clps711x_uart, &s->port); 529 530 return ret; 531 } 532 533 static int uart_clps711x_remove(struct platform_device *pdev) 534 { 535 struct clps711x_port *s = platform_get_drvdata(pdev); 536 537 return uart_remove_one_port(&clps711x_uart, &s->port); 538 } 539 540 static const struct of_device_id __maybe_unused clps711x_uart_dt_ids[] = { 541 { .compatible = "cirrus,clps711x-uart", }, 542 { } 543 }; 544 MODULE_DEVICE_TABLE(of, clps711x_uart_dt_ids); 545 546 static struct platform_driver clps711x_uart_platform = { 547 .driver = { 548 .name = "clps711x-uart", 549 .owner = THIS_MODULE, 550 .of_match_table = of_match_ptr(clps711x_uart_dt_ids), 551 }, 552 .probe = uart_clps711x_probe, 553 .remove = uart_clps711x_remove, 554 }; 555 556 static int __init uart_clps711x_init(void) 557 { 558 int ret; 559 560 #ifdef CONFIG_SERIAL_CLPS711X_CONSOLE 561 clps711x_uart.cons = &clps711x_console; 562 clps711x_console.data = &clps711x_uart; 563 #endif 564 565 ret = uart_register_driver(&clps711x_uart); 566 if (ret) 567 return ret; 568 569 return platform_driver_register(&clps711x_uart_platform); 570 } 571 module_init(uart_clps711x_init); 572 573 static void __exit uart_clps711x_exit(void) 574 { 575 platform_driver_unregister(&clps711x_uart_platform); 576 uart_unregister_driver(&clps711x_uart); 577 } 578 module_exit(uart_clps711x_exit); 579 580 MODULE_AUTHOR("Deep Blue Solutions Ltd"); 581 MODULE_DESCRIPTION("CLPS711X serial driver"); 582 MODULE_LICENSE("GPL"); 583