1 /* 2 * Driver for CLPS711x serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright 1999 ARM Limited 7 * Copyright (C) 2000 Deep Blue Solutions Ltd. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 16 #define SUPPORT_SYSRQ 17 #endif 18 19 #include <linux/module.h> 20 #include <linux/device.h> 21 #include <linux/console.h> 22 #include <linux/serial_core.h> 23 #include <linux/serial.h> 24 #include <linux/clk.h> 25 #include <linux/io.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/ioport.h> 29 #include <linux/of.h> 30 #include <linux/platform_device.h> 31 #include <linux/regmap.h> 32 33 #include <linux/mfd/syscon.h> 34 #include <linux/mfd/syscon/clps711x.h> 35 36 #include "serial_mctrl_gpio.h" 37 38 #define UART_CLPS711X_DEVNAME "ttyCL" 39 #define UART_CLPS711X_NR 2 40 #define UART_CLPS711X_MAJOR 204 41 #define UART_CLPS711X_MINOR 40 42 43 #define UARTDR_OFFSET (0x00) 44 #define UBRLCR_OFFSET (0x40) 45 46 #define UARTDR_FRMERR (1 << 8) 47 #define UARTDR_PARERR (1 << 9) 48 #define UARTDR_OVERR (1 << 10) 49 50 #define UBRLCR_BAUD_MASK ((1 << 12) - 1) 51 #define UBRLCR_BREAK (1 << 12) 52 #define UBRLCR_PRTEN (1 << 13) 53 #define UBRLCR_EVENPRT (1 << 14) 54 #define UBRLCR_XSTOP (1 << 15) 55 #define UBRLCR_FIFOEN (1 << 16) 56 #define UBRLCR_WRDLEN5 (0 << 17) 57 #define UBRLCR_WRDLEN6 (1 << 17) 58 #define UBRLCR_WRDLEN7 (2 << 17) 59 #define UBRLCR_WRDLEN8 (3 << 17) 60 #define UBRLCR_WRDLEN_MASK (3 << 17) 61 62 struct clps711x_port { 63 struct uart_port port; 64 unsigned int tx_enabled; 65 int rx_irq; 66 struct regmap *syscon; 67 struct mctrl_gpios *gpios; 68 }; 69 70 static struct uart_driver clps711x_uart = { 71 .owner = THIS_MODULE, 72 .driver_name = UART_CLPS711X_DEVNAME, 73 .dev_name = UART_CLPS711X_DEVNAME, 74 .major = UART_CLPS711X_MAJOR, 75 .minor = UART_CLPS711X_MINOR, 76 .nr = UART_CLPS711X_NR, 77 }; 78 79 static void uart_clps711x_stop_tx(struct uart_port *port) 80 { 81 struct clps711x_port *s = dev_get_drvdata(port->dev); 82 83 if (s->tx_enabled) { 84 disable_irq(port->irq); 85 s->tx_enabled = 0; 86 } 87 } 88 89 static void uart_clps711x_start_tx(struct uart_port *port) 90 { 91 struct clps711x_port *s = dev_get_drvdata(port->dev); 92 93 if (!s->tx_enabled) { 94 s->tx_enabled = 1; 95 enable_irq(port->irq); 96 } 97 } 98 99 static irqreturn_t uart_clps711x_int_rx(int irq, void *dev_id) 100 { 101 struct uart_port *port = dev_id; 102 struct clps711x_port *s = dev_get_drvdata(port->dev); 103 unsigned int status, flg; 104 u16 ch; 105 106 for (;;) { 107 u32 sysflg = 0; 108 109 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 110 if (sysflg & SYSFLG_URXFE) 111 break; 112 113 ch = readw(port->membase + UARTDR_OFFSET); 114 status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR); 115 ch &= 0xff; 116 117 port->icount.rx++; 118 flg = TTY_NORMAL; 119 120 if (unlikely(status)) { 121 if (status & UARTDR_PARERR) 122 port->icount.parity++; 123 else if (status & UARTDR_FRMERR) 124 port->icount.frame++; 125 else if (status & UARTDR_OVERR) 126 port->icount.overrun++; 127 128 status &= port->read_status_mask; 129 130 if (status & UARTDR_PARERR) 131 flg = TTY_PARITY; 132 else if (status & UARTDR_FRMERR) 133 flg = TTY_FRAME; 134 else if (status & UARTDR_OVERR) 135 flg = TTY_OVERRUN; 136 } 137 138 if (uart_handle_sysrq_char(port, ch)) 139 continue; 140 141 if (status & port->ignore_status_mask) 142 continue; 143 144 uart_insert_char(port, status, UARTDR_OVERR, ch, flg); 145 } 146 147 tty_flip_buffer_push(&port->state->port); 148 149 return IRQ_HANDLED; 150 } 151 152 static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id) 153 { 154 struct uart_port *port = dev_id; 155 struct clps711x_port *s = dev_get_drvdata(port->dev); 156 struct circ_buf *xmit = &port->state->xmit; 157 158 if (port->x_char) { 159 writew(port->x_char, port->membase + UARTDR_OFFSET); 160 port->icount.tx++; 161 port->x_char = 0; 162 return IRQ_HANDLED; 163 } 164 165 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 166 if (s->tx_enabled) { 167 disable_irq_nosync(port->irq); 168 s->tx_enabled = 0; 169 } 170 return IRQ_HANDLED; 171 } 172 173 while (!uart_circ_empty(xmit)) { 174 u32 sysflg = 0; 175 176 writew(xmit->buf[xmit->tail], port->membase + UARTDR_OFFSET); 177 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 178 port->icount.tx++; 179 180 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 181 if (sysflg & SYSFLG_UTXFF) 182 break; 183 } 184 185 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 186 uart_write_wakeup(port); 187 188 return IRQ_HANDLED; 189 } 190 191 static unsigned int uart_clps711x_tx_empty(struct uart_port *port) 192 { 193 struct clps711x_port *s = dev_get_drvdata(port->dev); 194 u32 sysflg = 0; 195 196 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 197 198 return (sysflg & SYSFLG_UBUSY) ? 0 : TIOCSER_TEMT; 199 } 200 201 static unsigned int uart_clps711x_get_mctrl(struct uart_port *port) 202 { 203 unsigned int result = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; 204 struct clps711x_port *s = dev_get_drvdata(port->dev); 205 206 return mctrl_gpio_get(s->gpios, &result); 207 } 208 209 static void uart_clps711x_set_mctrl(struct uart_port *port, unsigned int mctrl) 210 { 211 struct clps711x_port *s = dev_get_drvdata(port->dev); 212 213 mctrl_gpio_set(s->gpios, mctrl); 214 } 215 216 static void uart_clps711x_break_ctl(struct uart_port *port, int break_state) 217 { 218 unsigned int ubrlcr; 219 220 ubrlcr = readl(port->membase + UBRLCR_OFFSET); 221 if (break_state) 222 ubrlcr |= UBRLCR_BREAK; 223 else 224 ubrlcr &= ~UBRLCR_BREAK; 225 writel(ubrlcr, port->membase + UBRLCR_OFFSET); 226 } 227 228 static void uart_clps711x_set_ldisc(struct uart_port *port, int ld) 229 { 230 if (!port->line) { 231 struct clps711x_port *s = dev_get_drvdata(port->dev); 232 233 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON1_SIREN, 234 (ld == N_IRDA) ? SYSCON1_SIREN : 0); 235 } 236 } 237 238 static int uart_clps711x_startup(struct uart_port *port) 239 { 240 struct clps711x_port *s = dev_get_drvdata(port->dev); 241 242 /* Disable break */ 243 writel(readl(port->membase + UBRLCR_OFFSET) & ~UBRLCR_BREAK, 244 port->membase + UBRLCR_OFFSET); 245 246 /* Enable the port */ 247 return regmap_update_bits(s->syscon, SYSCON_OFFSET, 248 SYSCON_UARTEN, SYSCON_UARTEN); 249 } 250 251 static void uart_clps711x_shutdown(struct uart_port *port) 252 { 253 struct clps711x_port *s = dev_get_drvdata(port->dev); 254 255 /* Disable the port */ 256 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0); 257 } 258 259 static void uart_clps711x_set_termios(struct uart_port *port, 260 struct ktermios *termios, 261 struct ktermios *old) 262 { 263 u32 ubrlcr; 264 unsigned int baud, quot; 265 266 /* Mask termios capabilities we don't support */ 267 termios->c_cflag &= ~CMSPAR; 268 termios->c_iflag &= ~(BRKINT | IGNBRK); 269 270 /* Ask the core to calculate the divisor for us */ 271 baud = uart_get_baud_rate(port, termios, old, port->uartclk / 4096, 272 port->uartclk / 16); 273 quot = uart_get_divisor(port, baud); 274 275 switch (termios->c_cflag & CSIZE) { 276 case CS5: 277 ubrlcr = UBRLCR_WRDLEN5; 278 break; 279 case CS6: 280 ubrlcr = UBRLCR_WRDLEN6; 281 break; 282 case CS7: 283 ubrlcr = UBRLCR_WRDLEN7; 284 break; 285 case CS8: 286 default: 287 ubrlcr = UBRLCR_WRDLEN8; 288 break; 289 } 290 291 if (termios->c_cflag & CSTOPB) 292 ubrlcr |= UBRLCR_XSTOP; 293 294 if (termios->c_cflag & PARENB) { 295 ubrlcr |= UBRLCR_PRTEN; 296 if (!(termios->c_cflag & PARODD)) 297 ubrlcr |= UBRLCR_EVENPRT; 298 } 299 300 /* Enable FIFO */ 301 ubrlcr |= UBRLCR_FIFOEN; 302 303 /* Set read status mask */ 304 port->read_status_mask = UARTDR_OVERR; 305 if (termios->c_iflag & INPCK) 306 port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR; 307 308 /* Set status ignore mask */ 309 port->ignore_status_mask = 0; 310 if (!(termios->c_cflag & CREAD)) 311 port->ignore_status_mask |= UARTDR_OVERR | UARTDR_PARERR | 312 UARTDR_FRMERR; 313 314 uart_update_timeout(port, termios->c_cflag, baud); 315 316 writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET); 317 } 318 319 static const char *uart_clps711x_type(struct uart_port *port) 320 { 321 return (port->type == PORT_CLPS711X) ? "CLPS711X" : NULL; 322 } 323 324 static void uart_clps711x_config_port(struct uart_port *port, int flags) 325 { 326 if (flags & UART_CONFIG_TYPE) 327 port->type = PORT_CLPS711X; 328 } 329 330 static void uart_clps711x_nop_void(struct uart_port *port) 331 { 332 } 333 334 static int uart_clps711x_nop_int(struct uart_port *port) 335 { 336 return 0; 337 } 338 339 static const struct uart_ops uart_clps711x_ops = { 340 .tx_empty = uart_clps711x_tx_empty, 341 .set_mctrl = uart_clps711x_set_mctrl, 342 .get_mctrl = uart_clps711x_get_mctrl, 343 .stop_tx = uart_clps711x_stop_tx, 344 .start_tx = uart_clps711x_start_tx, 345 .stop_rx = uart_clps711x_nop_void, 346 .break_ctl = uart_clps711x_break_ctl, 347 .set_ldisc = uart_clps711x_set_ldisc, 348 .startup = uart_clps711x_startup, 349 .shutdown = uart_clps711x_shutdown, 350 .set_termios = uart_clps711x_set_termios, 351 .type = uart_clps711x_type, 352 .config_port = uart_clps711x_config_port, 353 .release_port = uart_clps711x_nop_void, 354 .request_port = uart_clps711x_nop_int, 355 }; 356 357 #ifdef CONFIG_SERIAL_CLPS711X_CONSOLE 358 static void uart_clps711x_console_putchar(struct uart_port *port, int ch) 359 { 360 struct clps711x_port *s = dev_get_drvdata(port->dev); 361 u32 sysflg = 0; 362 363 /* Wait for FIFO is not full */ 364 do { 365 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 366 } while (sysflg & SYSFLG_UTXFF); 367 368 writew(ch, port->membase + UARTDR_OFFSET); 369 } 370 371 static void uart_clps711x_console_write(struct console *co, const char *c, 372 unsigned n) 373 { 374 struct uart_port *port = clps711x_uart.state[co->index].uart_port; 375 struct clps711x_port *s = dev_get_drvdata(port->dev); 376 u32 sysflg = 0; 377 378 uart_console_write(port, c, n, uart_clps711x_console_putchar); 379 380 /* Wait for transmitter to become empty */ 381 do { 382 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 383 } while (sysflg & SYSFLG_UBUSY); 384 } 385 386 static int uart_clps711x_console_setup(struct console *co, char *options) 387 { 388 int baud = 38400, bits = 8, parity = 'n', flow = 'n'; 389 int ret, index = co->index; 390 struct clps711x_port *s; 391 struct uart_port *port; 392 unsigned int quot; 393 u32 ubrlcr; 394 395 if (index < 0 || index >= UART_CLPS711X_NR) 396 return -EINVAL; 397 398 port = clps711x_uart.state[index].uart_port; 399 if (!port) 400 return -ENODEV; 401 402 s = dev_get_drvdata(port->dev); 403 404 if (!options) { 405 u32 syscon = 0; 406 407 regmap_read(s->syscon, SYSCON_OFFSET, &syscon); 408 if (syscon & SYSCON_UARTEN) { 409 ubrlcr = readl(port->membase + UBRLCR_OFFSET); 410 411 if (ubrlcr & UBRLCR_PRTEN) { 412 if (ubrlcr & UBRLCR_EVENPRT) 413 parity = 'e'; 414 else 415 parity = 'o'; 416 } 417 418 if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7) 419 bits = 7; 420 421 quot = ubrlcr & UBRLCR_BAUD_MASK; 422 baud = port->uartclk / (16 * (quot + 1)); 423 } 424 } else 425 uart_parse_options(options, &baud, &parity, &bits, &flow); 426 427 ret = uart_set_options(port, co, baud, parity, bits, flow); 428 if (ret) 429 return ret; 430 431 return regmap_update_bits(s->syscon, SYSCON_OFFSET, 432 SYSCON_UARTEN, SYSCON_UARTEN); 433 } 434 435 static struct console clps711x_console = { 436 .name = UART_CLPS711X_DEVNAME, 437 .device = uart_console_device, 438 .write = uart_clps711x_console_write, 439 .setup = uart_clps711x_console_setup, 440 .flags = CON_PRINTBUFFER, 441 .index = -1, 442 }; 443 #endif 444 445 static int uart_clps711x_probe(struct platform_device *pdev) 446 { 447 struct device_node *np = pdev->dev.of_node; 448 int ret, index = np ? of_alias_get_id(np, "serial") : pdev->id; 449 struct clps711x_port *s; 450 struct resource *res; 451 struct clk *uart_clk; 452 453 if (index < 0 || index >= UART_CLPS711X_NR) 454 return -EINVAL; 455 456 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL); 457 if (!s) 458 return -ENOMEM; 459 460 uart_clk = devm_clk_get(&pdev->dev, NULL); 461 if (IS_ERR(uart_clk)) 462 return PTR_ERR(uart_clk); 463 464 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 465 s->port.membase = devm_ioremap_resource(&pdev->dev, res); 466 if (IS_ERR(s->port.membase)) 467 return PTR_ERR(s->port.membase); 468 469 s->port.irq = platform_get_irq(pdev, 0); 470 if (IS_ERR_VALUE(s->port.irq)) 471 return s->port.irq; 472 473 s->rx_irq = platform_get_irq(pdev, 1); 474 if (IS_ERR_VALUE(s->rx_irq)) 475 return s->rx_irq; 476 477 if (!np) { 478 char syscon_name[9]; 479 480 sprintf(syscon_name, "syscon.%i", index + 1); 481 s->syscon = syscon_regmap_lookup_by_pdevname(syscon_name); 482 if (IS_ERR(s->syscon)) 483 return PTR_ERR(s->syscon); 484 } else { 485 s->syscon = syscon_regmap_lookup_by_phandle(np, "syscon"); 486 if (IS_ERR(s->syscon)) 487 return PTR_ERR(s->syscon); 488 } 489 490 s->port.line = index; 491 s->port.dev = &pdev->dev; 492 s->port.iotype = UPIO_MEM32; 493 s->port.mapbase = res->start; 494 s->port.type = PORT_CLPS711X; 495 s->port.fifosize = 16; 496 s->port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; 497 s->port.uartclk = clk_get_rate(uart_clk); 498 s->port.ops = &uart_clps711x_ops; 499 500 platform_set_drvdata(pdev, s); 501 502 s->gpios = mctrl_gpio_init(&pdev->dev, 0); 503 504 ret = uart_add_one_port(&clps711x_uart, &s->port); 505 if (ret) 506 return ret; 507 508 /* Disable port */ 509 if (!uart_console(&s->port)) 510 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0); 511 512 s->tx_enabled = 1; 513 514 ret = devm_request_irq(&pdev->dev, s->port.irq, uart_clps711x_int_tx, 0, 515 dev_name(&pdev->dev), &s->port); 516 if (ret) { 517 uart_remove_one_port(&clps711x_uart, &s->port); 518 return ret; 519 } 520 521 ret = devm_request_irq(&pdev->dev, s->rx_irq, uart_clps711x_int_rx, 0, 522 dev_name(&pdev->dev), &s->port); 523 if (ret) 524 uart_remove_one_port(&clps711x_uart, &s->port); 525 526 return ret; 527 } 528 529 static int uart_clps711x_remove(struct platform_device *pdev) 530 { 531 struct clps711x_port *s = platform_get_drvdata(pdev); 532 533 return uart_remove_one_port(&clps711x_uart, &s->port); 534 } 535 536 static const struct of_device_id __maybe_unused clps711x_uart_dt_ids[] = { 537 { .compatible = "cirrus,clps711x-uart", }, 538 { } 539 }; 540 MODULE_DEVICE_TABLE(of, clps711x_uart_dt_ids); 541 542 static struct platform_driver clps711x_uart_platform = { 543 .driver = { 544 .name = "clps711x-uart", 545 .owner = THIS_MODULE, 546 .of_match_table = of_match_ptr(clps711x_uart_dt_ids), 547 }, 548 .probe = uart_clps711x_probe, 549 .remove = uart_clps711x_remove, 550 }; 551 552 static int __init uart_clps711x_init(void) 553 { 554 int ret; 555 556 #ifdef CONFIG_SERIAL_CLPS711X_CONSOLE 557 clps711x_uart.cons = &clps711x_console; 558 clps711x_console.data = &clps711x_uart; 559 #endif 560 561 ret = uart_register_driver(&clps711x_uart); 562 if (ret) 563 return ret; 564 565 return platform_driver_register(&clps711x_uart_platform); 566 } 567 module_init(uart_clps711x_init); 568 569 static void __exit uart_clps711x_exit(void) 570 { 571 platform_driver_unregister(&clps711x_uart_platform); 572 uart_unregister_driver(&clps711x_uart); 573 } 574 module_exit(uart_clps711x_exit); 575 576 MODULE_AUTHOR("Deep Blue Solutions Ltd"); 577 MODULE_DESCRIPTION("CLPS711X serial driver"); 578 MODULE_LICENSE("GPL"); 579