1 /* 2 * Driver for CLPS711x serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright 1999 ARM Limited 7 * Copyright (C) 2000 Deep Blue Solutions Ltd. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 16 #define SUPPORT_SYSRQ 17 #endif 18 19 #include <linux/module.h> 20 #include <linux/device.h> 21 #include <linux/console.h> 22 #include <linux/serial_core.h> 23 #include <linux/serial.h> 24 #include <linux/clk.h> 25 #include <linux/io.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/ioport.h> 29 #include <linux/of.h> 30 #include <linux/platform_device.h> 31 #include <linux/regmap.h> 32 33 #include <linux/mfd/syscon.h> 34 #include <linux/mfd/syscon/clps711x.h> 35 36 #include "serial_mctrl_gpio.h" 37 38 #define UART_CLPS711X_DEVNAME "ttyCL" 39 #define UART_CLPS711X_NR 2 40 #define UART_CLPS711X_MAJOR 204 41 #define UART_CLPS711X_MINOR 40 42 43 #define UARTDR_OFFSET (0x00) 44 #define UBRLCR_OFFSET (0x40) 45 46 #define UARTDR_FRMERR (1 << 8) 47 #define UARTDR_PARERR (1 << 9) 48 #define UARTDR_OVERR (1 << 10) 49 50 #define UBRLCR_BAUD_MASK ((1 << 12) - 1) 51 #define UBRLCR_BREAK (1 << 12) 52 #define UBRLCR_PRTEN (1 << 13) 53 #define UBRLCR_EVENPRT (1 << 14) 54 #define UBRLCR_XSTOP (1 << 15) 55 #define UBRLCR_FIFOEN (1 << 16) 56 #define UBRLCR_WRDLEN5 (0 << 17) 57 #define UBRLCR_WRDLEN6 (1 << 17) 58 #define UBRLCR_WRDLEN7 (2 << 17) 59 #define UBRLCR_WRDLEN8 (3 << 17) 60 #define UBRLCR_WRDLEN_MASK (3 << 17) 61 62 struct clps711x_port { 63 struct uart_port port; 64 unsigned int tx_enabled; 65 int rx_irq; 66 struct regmap *syscon; 67 struct mctrl_gpios *gpios; 68 }; 69 70 static struct uart_driver clps711x_uart = { 71 .owner = THIS_MODULE, 72 .driver_name = UART_CLPS711X_DEVNAME, 73 .dev_name = UART_CLPS711X_DEVNAME, 74 .major = UART_CLPS711X_MAJOR, 75 .minor = UART_CLPS711X_MINOR, 76 .nr = UART_CLPS711X_NR, 77 }; 78 79 static void uart_clps711x_stop_tx(struct uart_port *port) 80 { 81 struct clps711x_port *s = dev_get_drvdata(port->dev); 82 83 if (s->tx_enabled) { 84 disable_irq(port->irq); 85 s->tx_enabled = 0; 86 } 87 } 88 89 static void uart_clps711x_start_tx(struct uart_port *port) 90 { 91 struct clps711x_port *s = dev_get_drvdata(port->dev); 92 93 if (!s->tx_enabled) { 94 s->tx_enabled = 1; 95 enable_irq(port->irq); 96 } 97 } 98 99 static irqreturn_t uart_clps711x_int_rx(int irq, void *dev_id) 100 { 101 struct uart_port *port = dev_id; 102 struct clps711x_port *s = dev_get_drvdata(port->dev); 103 unsigned int status, flg; 104 u16 ch; 105 106 for (;;) { 107 u32 sysflg = 0; 108 109 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 110 if (sysflg & SYSFLG_URXFE) 111 break; 112 113 ch = readw(port->membase + UARTDR_OFFSET); 114 status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR); 115 ch &= 0xff; 116 117 port->icount.rx++; 118 flg = TTY_NORMAL; 119 120 if (unlikely(status)) { 121 if (status & UARTDR_PARERR) 122 port->icount.parity++; 123 else if (status & UARTDR_FRMERR) 124 port->icount.frame++; 125 else if (status & UARTDR_OVERR) 126 port->icount.overrun++; 127 128 status &= port->read_status_mask; 129 130 if (status & UARTDR_PARERR) 131 flg = TTY_PARITY; 132 else if (status & UARTDR_FRMERR) 133 flg = TTY_FRAME; 134 else if (status & UARTDR_OVERR) 135 flg = TTY_OVERRUN; 136 } 137 138 if (uart_handle_sysrq_char(port, ch)) 139 continue; 140 141 if (status & port->ignore_status_mask) 142 continue; 143 144 uart_insert_char(port, status, UARTDR_OVERR, ch, flg); 145 } 146 147 tty_flip_buffer_push(&port->state->port); 148 149 return IRQ_HANDLED; 150 } 151 152 static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id) 153 { 154 struct uart_port *port = dev_id; 155 struct clps711x_port *s = dev_get_drvdata(port->dev); 156 struct circ_buf *xmit = &port->state->xmit; 157 158 if (port->x_char) { 159 writew(port->x_char, port->membase + UARTDR_OFFSET); 160 port->icount.tx++; 161 port->x_char = 0; 162 return IRQ_HANDLED; 163 } 164 165 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 166 if (s->tx_enabled) { 167 disable_irq_nosync(port->irq); 168 s->tx_enabled = 0; 169 } 170 return IRQ_HANDLED; 171 } 172 173 while (!uart_circ_empty(xmit)) { 174 u32 sysflg = 0; 175 176 writew(xmit->buf[xmit->tail], port->membase + UARTDR_OFFSET); 177 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 178 port->icount.tx++; 179 180 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 181 if (sysflg & SYSFLG_UTXFF) 182 break; 183 } 184 185 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 186 uart_write_wakeup(port); 187 188 return IRQ_HANDLED; 189 } 190 191 static unsigned int uart_clps711x_tx_empty(struct uart_port *port) 192 { 193 struct clps711x_port *s = dev_get_drvdata(port->dev); 194 u32 sysflg = 0; 195 196 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 197 198 return (sysflg & SYSFLG_UBUSY) ? 0 : TIOCSER_TEMT; 199 } 200 201 static unsigned int uart_clps711x_get_mctrl(struct uart_port *port) 202 { 203 unsigned int result = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; 204 struct clps711x_port *s = dev_get_drvdata(port->dev); 205 206 return mctrl_gpio_get(s->gpios, &result); 207 } 208 209 static void uart_clps711x_set_mctrl(struct uart_port *port, unsigned int mctrl) 210 { 211 struct clps711x_port *s = dev_get_drvdata(port->dev); 212 213 mctrl_gpio_set(s->gpios, mctrl); 214 } 215 216 static void uart_clps711x_break_ctl(struct uart_port *port, int break_state) 217 { 218 unsigned int ubrlcr; 219 220 ubrlcr = readl(port->membase + UBRLCR_OFFSET); 221 if (break_state) 222 ubrlcr |= UBRLCR_BREAK; 223 else 224 ubrlcr &= ~UBRLCR_BREAK; 225 writel(ubrlcr, port->membase + UBRLCR_OFFSET); 226 } 227 228 static void uart_clps711x_set_ldisc(struct uart_port *port, 229 struct ktermios *termios) 230 { 231 if (!port->line) { 232 struct clps711x_port *s = dev_get_drvdata(port->dev); 233 234 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON1_SIREN, 235 (termios->c_line == N_IRDA) ? SYSCON1_SIREN : 0); 236 } 237 } 238 239 static int uart_clps711x_startup(struct uart_port *port) 240 { 241 struct clps711x_port *s = dev_get_drvdata(port->dev); 242 243 /* Disable break */ 244 writel(readl(port->membase + UBRLCR_OFFSET) & ~UBRLCR_BREAK, 245 port->membase + UBRLCR_OFFSET); 246 247 /* Enable the port */ 248 return regmap_update_bits(s->syscon, SYSCON_OFFSET, 249 SYSCON_UARTEN, SYSCON_UARTEN); 250 } 251 252 static void uart_clps711x_shutdown(struct uart_port *port) 253 { 254 struct clps711x_port *s = dev_get_drvdata(port->dev); 255 256 /* Disable the port */ 257 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0); 258 } 259 260 static void uart_clps711x_set_termios(struct uart_port *port, 261 struct ktermios *termios, 262 struct ktermios *old) 263 { 264 u32 ubrlcr; 265 unsigned int baud, quot; 266 267 /* Mask termios capabilities we don't support */ 268 termios->c_cflag &= ~CMSPAR; 269 termios->c_iflag &= ~(BRKINT | IGNBRK); 270 271 /* Ask the core to calculate the divisor for us */ 272 baud = uart_get_baud_rate(port, termios, old, port->uartclk / 4096, 273 port->uartclk / 16); 274 quot = uart_get_divisor(port, baud); 275 276 switch (termios->c_cflag & CSIZE) { 277 case CS5: 278 ubrlcr = UBRLCR_WRDLEN5; 279 break; 280 case CS6: 281 ubrlcr = UBRLCR_WRDLEN6; 282 break; 283 case CS7: 284 ubrlcr = UBRLCR_WRDLEN7; 285 break; 286 case CS8: 287 default: 288 ubrlcr = UBRLCR_WRDLEN8; 289 break; 290 } 291 292 if (termios->c_cflag & CSTOPB) 293 ubrlcr |= UBRLCR_XSTOP; 294 295 if (termios->c_cflag & PARENB) { 296 ubrlcr |= UBRLCR_PRTEN; 297 if (!(termios->c_cflag & PARODD)) 298 ubrlcr |= UBRLCR_EVENPRT; 299 } 300 301 /* Enable FIFO */ 302 ubrlcr |= UBRLCR_FIFOEN; 303 304 /* Set read status mask */ 305 port->read_status_mask = UARTDR_OVERR; 306 if (termios->c_iflag & INPCK) 307 port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR; 308 309 /* Set status ignore mask */ 310 port->ignore_status_mask = 0; 311 if (!(termios->c_cflag & CREAD)) 312 port->ignore_status_mask |= UARTDR_OVERR | UARTDR_PARERR | 313 UARTDR_FRMERR; 314 315 uart_update_timeout(port, termios->c_cflag, baud); 316 317 writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET); 318 } 319 320 static const char *uart_clps711x_type(struct uart_port *port) 321 { 322 return (port->type == PORT_CLPS711X) ? "CLPS711X" : NULL; 323 } 324 325 static void uart_clps711x_config_port(struct uart_port *port, int flags) 326 { 327 if (flags & UART_CONFIG_TYPE) 328 port->type = PORT_CLPS711X; 329 } 330 331 static void uart_clps711x_nop_void(struct uart_port *port) 332 { 333 } 334 335 static int uart_clps711x_nop_int(struct uart_port *port) 336 { 337 return 0; 338 } 339 340 static const struct uart_ops uart_clps711x_ops = { 341 .tx_empty = uart_clps711x_tx_empty, 342 .set_mctrl = uart_clps711x_set_mctrl, 343 .get_mctrl = uart_clps711x_get_mctrl, 344 .stop_tx = uart_clps711x_stop_tx, 345 .start_tx = uart_clps711x_start_tx, 346 .stop_rx = uart_clps711x_nop_void, 347 .break_ctl = uart_clps711x_break_ctl, 348 .set_ldisc = uart_clps711x_set_ldisc, 349 .startup = uart_clps711x_startup, 350 .shutdown = uart_clps711x_shutdown, 351 .set_termios = uart_clps711x_set_termios, 352 .type = uart_clps711x_type, 353 .config_port = uart_clps711x_config_port, 354 .release_port = uart_clps711x_nop_void, 355 .request_port = uart_clps711x_nop_int, 356 }; 357 358 #ifdef CONFIG_SERIAL_CLPS711X_CONSOLE 359 static void uart_clps711x_console_putchar(struct uart_port *port, int ch) 360 { 361 struct clps711x_port *s = dev_get_drvdata(port->dev); 362 u32 sysflg = 0; 363 364 /* Wait for FIFO is not full */ 365 do { 366 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 367 } while (sysflg & SYSFLG_UTXFF); 368 369 writew(ch, port->membase + UARTDR_OFFSET); 370 } 371 372 static void uart_clps711x_console_write(struct console *co, const char *c, 373 unsigned n) 374 { 375 struct uart_port *port = clps711x_uart.state[co->index].uart_port; 376 struct clps711x_port *s = dev_get_drvdata(port->dev); 377 u32 sysflg = 0; 378 379 uart_console_write(port, c, n, uart_clps711x_console_putchar); 380 381 /* Wait for transmitter to become empty */ 382 do { 383 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); 384 } while (sysflg & SYSFLG_UBUSY); 385 } 386 387 static int uart_clps711x_console_setup(struct console *co, char *options) 388 { 389 int baud = 38400, bits = 8, parity = 'n', flow = 'n'; 390 int ret, index = co->index; 391 struct clps711x_port *s; 392 struct uart_port *port; 393 unsigned int quot; 394 u32 ubrlcr; 395 396 if (index < 0 || index >= UART_CLPS711X_NR) 397 return -EINVAL; 398 399 port = clps711x_uart.state[index].uart_port; 400 if (!port) 401 return -ENODEV; 402 403 s = dev_get_drvdata(port->dev); 404 405 if (!options) { 406 u32 syscon = 0; 407 408 regmap_read(s->syscon, SYSCON_OFFSET, &syscon); 409 if (syscon & SYSCON_UARTEN) { 410 ubrlcr = readl(port->membase + UBRLCR_OFFSET); 411 412 if (ubrlcr & UBRLCR_PRTEN) { 413 if (ubrlcr & UBRLCR_EVENPRT) 414 parity = 'e'; 415 else 416 parity = 'o'; 417 } 418 419 if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7) 420 bits = 7; 421 422 quot = ubrlcr & UBRLCR_BAUD_MASK; 423 baud = port->uartclk / (16 * (quot + 1)); 424 } 425 } else 426 uart_parse_options(options, &baud, &parity, &bits, &flow); 427 428 ret = uart_set_options(port, co, baud, parity, bits, flow); 429 if (ret) 430 return ret; 431 432 return regmap_update_bits(s->syscon, SYSCON_OFFSET, 433 SYSCON_UARTEN, SYSCON_UARTEN); 434 } 435 436 static struct console clps711x_console = { 437 .name = UART_CLPS711X_DEVNAME, 438 .device = uart_console_device, 439 .write = uart_clps711x_console_write, 440 .setup = uart_clps711x_console_setup, 441 .flags = CON_PRINTBUFFER, 442 .index = -1, 443 }; 444 #endif 445 446 static int uart_clps711x_probe(struct platform_device *pdev) 447 { 448 struct device_node *np = pdev->dev.of_node; 449 int ret, index = np ? of_alias_get_id(np, "serial") : pdev->id; 450 struct clps711x_port *s; 451 struct resource *res; 452 struct clk *uart_clk; 453 454 if (index < 0 || index >= UART_CLPS711X_NR) 455 return -EINVAL; 456 457 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL); 458 if (!s) 459 return -ENOMEM; 460 461 uart_clk = devm_clk_get(&pdev->dev, NULL); 462 if (IS_ERR(uart_clk)) 463 return PTR_ERR(uart_clk); 464 465 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 466 s->port.membase = devm_ioremap_resource(&pdev->dev, res); 467 if (IS_ERR(s->port.membase)) 468 return PTR_ERR(s->port.membase); 469 470 s->port.irq = platform_get_irq(pdev, 0); 471 if (IS_ERR_VALUE(s->port.irq)) 472 return s->port.irq; 473 474 s->rx_irq = platform_get_irq(pdev, 1); 475 if (IS_ERR_VALUE(s->rx_irq)) 476 return s->rx_irq; 477 478 if (!np) { 479 char syscon_name[9]; 480 481 sprintf(syscon_name, "syscon.%i", index + 1); 482 s->syscon = syscon_regmap_lookup_by_pdevname(syscon_name); 483 if (IS_ERR(s->syscon)) 484 return PTR_ERR(s->syscon); 485 } else { 486 s->syscon = syscon_regmap_lookup_by_phandle(np, "syscon"); 487 if (IS_ERR(s->syscon)) 488 return PTR_ERR(s->syscon); 489 } 490 491 s->port.line = index; 492 s->port.dev = &pdev->dev; 493 s->port.iotype = UPIO_MEM32; 494 s->port.mapbase = res->start; 495 s->port.type = PORT_CLPS711X; 496 s->port.fifosize = 16; 497 s->port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; 498 s->port.uartclk = clk_get_rate(uart_clk); 499 s->port.ops = &uart_clps711x_ops; 500 501 platform_set_drvdata(pdev, s); 502 503 s->gpios = mctrl_gpio_init(&pdev->dev, 0); 504 if (IS_ERR(s->gpios)) 505 return PTR_ERR(s->gpios); 506 507 ret = uart_add_one_port(&clps711x_uart, &s->port); 508 if (ret) 509 return ret; 510 511 /* Disable port */ 512 if (!uart_console(&s->port)) 513 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0); 514 515 s->tx_enabled = 1; 516 517 ret = devm_request_irq(&pdev->dev, s->port.irq, uart_clps711x_int_tx, 0, 518 dev_name(&pdev->dev), &s->port); 519 if (ret) { 520 uart_remove_one_port(&clps711x_uart, &s->port); 521 return ret; 522 } 523 524 ret = devm_request_irq(&pdev->dev, s->rx_irq, uart_clps711x_int_rx, 0, 525 dev_name(&pdev->dev), &s->port); 526 if (ret) 527 uart_remove_one_port(&clps711x_uart, &s->port); 528 529 return ret; 530 } 531 532 static int uart_clps711x_remove(struct platform_device *pdev) 533 { 534 struct clps711x_port *s = platform_get_drvdata(pdev); 535 536 return uart_remove_one_port(&clps711x_uart, &s->port); 537 } 538 539 static const struct of_device_id __maybe_unused clps711x_uart_dt_ids[] = { 540 { .compatible = "cirrus,clps711x-uart", }, 541 { } 542 }; 543 MODULE_DEVICE_TABLE(of, clps711x_uart_dt_ids); 544 545 static struct platform_driver clps711x_uart_platform = { 546 .driver = { 547 .name = "clps711x-uart", 548 .of_match_table = of_match_ptr(clps711x_uart_dt_ids), 549 }, 550 .probe = uart_clps711x_probe, 551 .remove = uart_clps711x_remove, 552 }; 553 554 static int __init uart_clps711x_init(void) 555 { 556 int ret; 557 558 #ifdef CONFIG_SERIAL_CLPS711X_CONSOLE 559 clps711x_uart.cons = &clps711x_console; 560 clps711x_console.data = &clps711x_uart; 561 #endif 562 563 ret = uart_register_driver(&clps711x_uart); 564 if (ret) 565 return ret; 566 567 return platform_driver_register(&clps711x_uart_platform); 568 } 569 module_init(uart_clps711x_init); 570 571 static void __exit uart_clps711x_exit(void) 572 { 573 platform_driver_unregister(&clps711x_uart_platform); 574 uart_unregister_driver(&clps711x_uart); 575 } 576 module_exit(uart_clps711x_exit); 577 578 MODULE_AUTHOR("Deep Blue Solutions Ltd"); 579 MODULE_DESCRIPTION("CLPS711X serial driver"); 580 MODULE_LICENSE("GPL"); 581