1 /* 2 * Driver for CLPS711x serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright 1999 ARM Limited 7 * Copyright (C) 2000 Deep Blue Solutions Ltd. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 16 #define SUPPORT_SYSRQ 17 #endif 18 19 #include <linux/module.h> 20 #include <linux/device.h> 21 #include <linux/console.h> 22 #include <linux/serial_core.h> 23 #include <linux/serial.h> 24 #include <linux/io.h> 25 #include <linux/clk.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/ioport.h> 29 #include <linux/platform_device.h> 30 31 #include <mach/hardware.h> 32 33 #define UART_CLPS711X_NAME "uart-clps711x" 34 #define UART_CLPS711X_NR 2 35 #define UART_CLPS711X_MAJOR 204 36 #define UART_CLPS711X_MINOR 40 37 38 #define UBRLCR(port) ((port)->line ? UBRLCR2 : UBRLCR1) 39 #define UARTDR(port) ((port)->line ? UARTDR2 : UARTDR1) 40 #define SYSFLG(port) ((port)->line ? SYSFLG2 : SYSFLG1) 41 #define SYSCON(port) ((port)->line ? SYSCON2 : SYSCON1) 42 #define TX_IRQ(port) ((port)->line ? IRQ_UTXINT2 : IRQ_UTXINT1) 43 #define RX_IRQ(port) ((port)->line ? IRQ_URXINT2 : IRQ_URXINT1) 44 45 struct clps711x_port { 46 struct uart_driver uart; 47 struct clk *uart_clk; 48 struct uart_port port[UART_CLPS711X_NR]; 49 int tx_enabled[UART_CLPS711X_NR]; 50 #ifdef CONFIG_SERIAL_CLPS711X_CONSOLE 51 struct console console; 52 #endif 53 }; 54 55 static void uart_clps711x_stop_tx(struct uart_port *port) 56 { 57 struct clps711x_port *s = dev_get_drvdata(port->dev); 58 59 if (s->tx_enabled[port->line]) { 60 disable_irq(TX_IRQ(port)); 61 s->tx_enabled[port->line] = 0; 62 } 63 } 64 65 static void uart_clps711x_start_tx(struct uart_port *port) 66 { 67 struct clps711x_port *s = dev_get_drvdata(port->dev); 68 69 if (!s->tx_enabled[port->line]) { 70 enable_irq(TX_IRQ(port)); 71 s->tx_enabled[port->line] = 1; 72 } 73 } 74 75 static void uart_clps711x_stop_rx(struct uart_port *port) 76 { 77 disable_irq(RX_IRQ(port)); 78 } 79 80 static void uart_clps711x_enable_ms(struct uart_port *port) 81 { 82 /* Do nothing */ 83 } 84 85 static irqreturn_t uart_clps711x_int_rx(int irq, void *dev_id) 86 { 87 struct uart_port *port = dev_id; 88 unsigned int status, ch, flg; 89 90 for (;;) { 91 status = clps_readl(SYSFLG(port)); 92 if (status & SYSFLG_URXFE) 93 break; 94 95 ch = clps_readw(UARTDR(port)); 96 status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR); 97 ch &= 0xff; 98 99 port->icount.rx++; 100 flg = TTY_NORMAL; 101 102 if (unlikely(status)) { 103 if (status & UARTDR_PARERR) 104 port->icount.parity++; 105 else if (status & UARTDR_FRMERR) 106 port->icount.frame++; 107 else if (status & UARTDR_OVERR) 108 port->icount.overrun++; 109 110 status &= port->read_status_mask; 111 112 if (status & UARTDR_PARERR) 113 flg = TTY_PARITY; 114 else if (status & UARTDR_FRMERR) 115 flg = TTY_FRAME; 116 else if (status & UARTDR_OVERR) 117 flg = TTY_OVERRUN; 118 } 119 120 if (uart_handle_sysrq_char(port, ch)) 121 continue; 122 123 if (status & port->ignore_status_mask) 124 continue; 125 126 uart_insert_char(port, status, UARTDR_OVERR, ch, flg); 127 } 128 129 tty_flip_buffer_push(&port->state->port); 130 131 return IRQ_HANDLED; 132 } 133 134 static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id) 135 { 136 struct uart_port *port = dev_id; 137 struct clps711x_port *s = dev_get_drvdata(port->dev); 138 struct circ_buf *xmit = &port->state->xmit; 139 140 if (port->x_char) { 141 clps_writew(port->x_char, UARTDR(port)); 142 port->icount.tx++; 143 port->x_char = 0; 144 return IRQ_HANDLED; 145 } 146 147 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 148 disable_irq_nosync(TX_IRQ(port)); 149 s->tx_enabled[port->line] = 0; 150 return IRQ_HANDLED; 151 } 152 153 while (!uart_circ_empty(xmit)) { 154 clps_writew(xmit->buf[xmit->tail], UARTDR(port)); 155 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 156 port->icount.tx++; 157 if (clps_readl(SYSFLG(port) & SYSFLG_UTXFF)) 158 break; 159 } 160 161 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 162 uart_write_wakeup(port); 163 164 return IRQ_HANDLED; 165 } 166 167 static unsigned int uart_clps711x_tx_empty(struct uart_port *port) 168 { 169 return (clps_readl(SYSFLG(port) & SYSFLG_UBUSY)) ? 0 : TIOCSER_TEMT; 170 } 171 172 static unsigned int uart_clps711x_get_mctrl(struct uart_port *port) 173 { 174 unsigned int status, result = 0; 175 176 if (port->line == 0) { 177 status = clps_readl(SYSFLG1); 178 if (status & SYSFLG1_DCD) 179 result |= TIOCM_CAR; 180 if (status & SYSFLG1_DSR) 181 result |= TIOCM_DSR; 182 if (status & SYSFLG1_CTS) 183 result |= TIOCM_CTS; 184 } else 185 result = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; 186 187 return result; 188 } 189 190 static void uart_clps711x_set_mctrl(struct uart_port *port, unsigned int mctrl) 191 { 192 /* Do nothing */ 193 } 194 195 static void uart_clps711x_break_ctl(struct uart_port *port, int break_state) 196 { 197 unsigned long flags; 198 unsigned int ubrlcr; 199 200 spin_lock_irqsave(&port->lock, flags); 201 202 ubrlcr = clps_readl(UBRLCR(port)); 203 if (break_state) 204 ubrlcr |= UBRLCR_BREAK; 205 else 206 ubrlcr &= ~UBRLCR_BREAK; 207 clps_writel(ubrlcr, UBRLCR(port)); 208 209 spin_unlock_irqrestore(&port->lock, flags); 210 } 211 212 static int uart_clps711x_startup(struct uart_port *port) 213 { 214 struct clps711x_port *s = dev_get_drvdata(port->dev); 215 int ret; 216 217 s->tx_enabled[port->line] = 1; 218 /* Allocate the IRQs */ 219 ret = devm_request_irq(port->dev, TX_IRQ(port), uart_clps711x_int_tx, 220 0, UART_CLPS711X_NAME " TX", port); 221 if (ret) 222 return ret; 223 224 ret = devm_request_irq(port->dev, RX_IRQ(port), uart_clps711x_int_rx, 225 0, UART_CLPS711X_NAME " RX", port); 226 if (ret) { 227 devm_free_irq(port->dev, TX_IRQ(port), port); 228 return ret; 229 } 230 231 /* Disable break */ 232 clps_writel(clps_readl(UBRLCR(port)) & ~UBRLCR_BREAK, UBRLCR(port)); 233 234 /* Enable the port */ 235 clps_writel(clps_readl(SYSCON(port)) | SYSCON_UARTEN, SYSCON(port)); 236 237 return 0; 238 } 239 240 static void uart_clps711x_shutdown(struct uart_port *port) 241 { 242 /* Free the interrupts */ 243 devm_free_irq(port->dev, TX_IRQ(port), port); 244 devm_free_irq(port->dev, RX_IRQ(port), port); 245 246 /* Disable the port */ 247 clps_writel(clps_readl(SYSCON(port)) & ~SYSCON_UARTEN, SYSCON(port)); 248 } 249 250 static void uart_clps711x_set_termios(struct uart_port *port, 251 struct ktermios *termios, 252 struct ktermios *old) 253 { 254 unsigned int ubrlcr, baud, quot; 255 unsigned long flags; 256 257 /* Mask termios capabilities we don't support */ 258 termios->c_cflag &= ~CMSPAR; 259 termios->c_iflag &= ~(BRKINT | IGNBRK); 260 261 /* Ask the core to calculate the divisor for us */ 262 baud = uart_get_baud_rate(port, termios, old, port->uartclk / 4096, 263 port->uartclk / 16); 264 quot = uart_get_divisor(port, baud); 265 266 switch (termios->c_cflag & CSIZE) { 267 case CS5: 268 ubrlcr = UBRLCR_WRDLEN5; 269 break; 270 case CS6: 271 ubrlcr = UBRLCR_WRDLEN6; 272 break; 273 case CS7: 274 ubrlcr = UBRLCR_WRDLEN7; 275 break; 276 case CS8: 277 default: 278 ubrlcr = UBRLCR_WRDLEN8; 279 break; 280 } 281 282 if (termios->c_cflag & CSTOPB) 283 ubrlcr |= UBRLCR_XSTOP; 284 285 if (termios->c_cflag & PARENB) { 286 ubrlcr |= UBRLCR_PRTEN; 287 if (!(termios->c_cflag & PARODD)) 288 ubrlcr |= UBRLCR_EVENPRT; 289 } 290 291 /* Enable FIFO */ 292 ubrlcr |= UBRLCR_FIFOEN; 293 294 spin_lock_irqsave(&port->lock, flags); 295 296 /* Set read status mask */ 297 port->read_status_mask = UARTDR_OVERR; 298 if (termios->c_iflag & INPCK) 299 port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR; 300 301 /* Set status ignore mask */ 302 port->ignore_status_mask = 0; 303 if (!(termios->c_cflag & CREAD)) 304 port->ignore_status_mask |= UARTDR_OVERR | UARTDR_PARERR | 305 UARTDR_FRMERR; 306 307 uart_update_timeout(port, termios->c_cflag, baud); 308 309 clps_writel(ubrlcr | (quot - 1), UBRLCR(port)); 310 311 spin_unlock_irqrestore(&port->lock, flags); 312 } 313 314 static const char *uart_clps711x_type(struct uart_port *port) 315 { 316 return (port->type == PORT_CLPS711X) ? "CLPS711X" : NULL; 317 } 318 319 static void uart_clps711x_config_port(struct uart_port *port, int flags) 320 { 321 if (flags & UART_CONFIG_TYPE) 322 port->type = PORT_CLPS711X; 323 } 324 325 static void uart_clps711x_release_port(struct uart_port *port) 326 { 327 /* Do nothing */ 328 } 329 330 static int uart_clps711x_request_port(struct uart_port *port) 331 { 332 /* Do nothing */ 333 return 0; 334 } 335 336 static const struct uart_ops uart_clps711x_ops = { 337 .tx_empty = uart_clps711x_tx_empty, 338 .set_mctrl = uart_clps711x_set_mctrl, 339 .get_mctrl = uart_clps711x_get_mctrl, 340 .stop_tx = uart_clps711x_stop_tx, 341 .start_tx = uart_clps711x_start_tx, 342 .stop_rx = uart_clps711x_stop_rx, 343 .enable_ms = uart_clps711x_enable_ms, 344 .break_ctl = uart_clps711x_break_ctl, 345 .startup = uart_clps711x_startup, 346 .shutdown = uart_clps711x_shutdown, 347 .set_termios = uart_clps711x_set_termios, 348 .type = uart_clps711x_type, 349 .config_port = uart_clps711x_config_port, 350 .release_port = uart_clps711x_release_port, 351 .request_port = uart_clps711x_request_port, 352 }; 353 354 #ifdef CONFIG_SERIAL_CLPS711X_CONSOLE 355 static void uart_clps711x_console_putchar(struct uart_port *port, int ch) 356 { 357 while (clps_readl(SYSFLG(port)) & SYSFLG_UTXFF) 358 barrier(); 359 360 clps_writew(ch, UARTDR(port)); 361 } 362 363 static void uart_clps711x_console_write(struct console *co, const char *c, 364 unsigned n) 365 { 366 struct clps711x_port *s = (struct clps711x_port *)co->data; 367 struct uart_port *port = &s->port[co->index]; 368 u32 syscon; 369 370 /* Ensure that the port is enabled */ 371 syscon = clps_readl(SYSCON(port)); 372 clps_writel(syscon | SYSCON_UARTEN, SYSCON(port)); 373 374 uart_console_write(port, c, n, uart_clps711x_console_putchar); 375 376 /* Wait for transmitter to become empty */ 377 while (clps_readl(SYSFLG(port)) & SYSFLG_UBUSY) 378 barrier(); 379 380 /* Restore the uart state */ 381 clps_writel(syscon, SYSCON(port)); 382 } 383 384 static void uart_clps711x_console_get_options(struct uart_port *port, 385 int *baud, int *parity, 386 int *bits) 387 { 388 if (clps_readl(SYSCON(port)) & SYSCON_UARTEN) { 389 unsigned int ubrlcr, quot; 390 391 ubrlcr = clps_readl(UBRLCR(port)); 392 393 *parity = 'n'; 394 if (ubrlcr & UBRLCR_PRTEN) { 395 if (ubrlcr & UBRLCR_EVENPRT) 396 *parity = 'e'; 397 else 398 *parity = 'o'; 399 } 400 401 if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7) 402 *bits = 7; 403 else 404 *bits = 8; 405 406 quot = ubrlcr & UBRLCR_BAUD_MASK; 407 *baud = port->uartclk / (16 * (quot + 1)); 408 } 409 } 410 411 static int uart_clps711x_console_setup(struct console *co, char *options) 412 { 413 int baud = 38400, bits = 8, parity = 'n', flow = 'n'; 414 struct clps711x_port *s = (struct clps711x_port *)co->data; 415 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0]; 416 417 if (options) 418 uart_parse_options(options, &baud, &parity, &bits, &flow); 419 else 420 uart_clps711x_console_get_options(port, &baud, &parity, &bits); 421 422 return uart_set_options(port, co, baud, parity, bits, flow); 423 } 424 #endif 425 426 static int uart_clps711x_probe(struct platform_device *pdev) 427 { 428 struct clps711x_port *s; 429 int ret, i; 430 431 s = devm_kzalloc(&pdev->dev, sizeof(struct clps711x_port), GFP_KERNEL); 432 if (!s) { 433 dev_err(&pdev->dev, "Error allocating port structure\n"); 434 return -ENOMEM; 435 } 436 platform_set_drvdata(pdev, s); 437 438 s->uart_clk = devm_clk_get(&pdev->dev, "uart"); 439 if (IS_ERR(s->uart_clk)) { 440 dev_err(&pdev->dev, "Can't get UART clocks\n"); 441 return PTR_ERR(s->uart_clk); 442 } 443 444 s->uart.owner = THIS_MODULE; 445 s->uart.dev_name = "ttyCL"; 446 s->uart.major = UART_CLPS711X_MAJOR; 447 s->uart.minor = UART_CLPS711X_MINOR; 448 s->uart.nr = UART_CLPS711X_NR; 449 #ifdef CONFIG_SERIAL_CLPS711X_CONSOLE 450 s->uart.cons = &s->console; 451 s->uart.cons->device = uart_console_device; 452 s->uart.cons->write = uart_clps711x_console_write; 453 s->uart.cons->setup = uart_clps711x_console_setup; 454 s->uart.cons->flags = CON_PRINTBUFFER; 455 s->uart.cons->index = -1; 456 s->uart.cons->data = s; 457 strcpy(s->uart.cons->name, "ttyCL"); 458 #endif 459 ret = uart_register_driver(&s->uart); 460 if (ret) { 461 dev_err(&pdev->dev, "Registering UART driver failed\n"); 462 return ret; 463 } 464 465 for (i = 0; i < UART_CLPS711X_NR; i++) { 466 s->port[i].line = i; 467 s->port[i].dev = &pdev->dev; 468 s->port[i].irq = TX_IRQ(&s->port[i]); 469 s->port[i].iobase = SYSCON(&s->port[i]); 470 s->port[i].type = PORT_CLPS711X; 471 s->port[i].fifosize = 16; 472 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; 473 s->port[i].uartclk = clk_get_rate(s->uart_clk); 474 s->port[i].ops = &uart_clps711x_ops; 475 WARN_ON(uart_add_one_port(&s->uart, &s->port[i])); 476 } 477 478 return 0; 479 } 480 481 static int uart_clps711x_remove(struct platform_device *pdev) 482 { 483 struct clps711x_port *s = platform_get_drvdata(pdev); 484 int i; 485 486 for (i = 0; i < UART_CLPS711X_NR; i++) 487 uart_remove_one_port(&s->uart, &s->port[i]); 488 489 uart_unregister_driver(&s->uart); 490 491 return 0; 492 } 493 494 static struct platform_driver clps711x_uart_driver = { 495 .driver = { 496 .name = UART_CLPS711X_NAME, 497 .owner = THIS_MODULE, 498 }, 499 .probe = uart_clps711x_probe, 500 .remove = uart_clps711x_remove, 501 }; 502 module_platform_driver(clps711x_uart_driver); 503 504 static struct platform_device clps711x_uart_device = { 505 .name = UART_CLPS711X_NAME, 506 }; 507 508 static int __init uart_clps711x_init(void) 509 { 510 return platform_device_register(&clps711x_uart_device); 511 } 512 module_init(uart_clps711x_init); 513 514 static void __exit uart_clps711x_exit(void) 515 { 516 platform_device_unregister(&clps711x_uart_device); 517 } 518 module_exit(uart_clps711x_exit); 519 520 MODULE_AUTHOR("Deep Blue Solutions Ltd"); 521 MODULE_DESCRIPTION("CLPS711X serial driver"); 522 MODULE_LICENSE("GPL"); 523