xref: /openbmc/linux/drivers/tty/serial/clps711x.c (revision 060f03e9) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Driver for CLPS711x serial ports
4  *
5  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6  *
7  *  Copyright 1999 ARM Limited
8  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
9  */
10 
11 #include <linux/module.h>
12 #include <linux/device.h>
13 #include <linux/console.h>
14 #include <linux/serial_core.h>
15 #include <linux/serial.h>
16 #include <linux/clk.h>
17 #include <linux/io.h>
18 #include <linux/tty.h>
19 #include <linux/tty_flip.h>
20 #include <linux/ioport.h>
21 #include <linux/of.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 
25 #include <linux/mfd/syscon.h>
26 #include <linux/mfd/syscon/clps711x.h>
27 
28 #include "serial_mctrl_gpio.h"
29 
30 #define UART_CLPS711X_DEVNAME	"ttyCL"
31 #define UART_CLPS711X_NR	2
32 #define UART_CLPS711X_MAJOR	204
33 #define UART_CLPS711X_MINOR	40
34 
35 #define UARTDR_OFFSET		(0x00)
36 #define UBRLCR_OFFSET		(0x40)
37 
38 #define UARTDR_FRMERR		(1 << 8)
39 #define UARTDR_PARERR		(1 << 9)
40 #define UARTDR_OVERR		(1 << 10)
41 
42 #define UBRLCR_BAUD_MASK	((1 << 12) - 1)
43 #define UBRLCR_BREAK		(1 << 12)
44 #define UBRLCR_PRTEN		(1 << 13)
45 #define UBRLCR_EVENPRT		(1 << 14)
46 #define UBRLCR_XSTOP		(1 << 15)
47 #define UBRLCR_FIFOEN		(1 << 16)
48 #define UBRLCR_WRDLEN5		(0 << 17)
49 #define UBRLCR_WRDLEN6		(1 << 17)
50 #define UBRLCR_WRDLEN7		(2 << 17)
51 #define UBRLCR_WRDLEN8		(3 << 17)
52 #define UBRLCR_WRDLEN_MASK	(3 << 17)
53 
54 struct clps711x_port {
55 	struct uart_port	port;
56 	unsigned int		tx_enabled;
57 	int			rx_irq;
58 	struct regmap		*syscon;
59 	struct mctrl_gpios	*gpios;
60 };
61 
62 static struct uart_driver clps711x_uart = {
63 	.owner		= THIS_MODULE,
64 	.driver_name	= UART_CLPS711X_DEVNAME,
65 	.dev_name	= UART_CLPS711X_DEVNAME,
66 	.major		= UART_CLPS711X_MAJOR,
67 	.minor		= UART_CLPS711X_MINOR,
68 	.nr		= UART_CLPS711X_NR,
69 };
70 
71 static void uart_clps711x_stop_tx(struct uart_port *port)
72 {
73 	struct clps711x_port *s = dev_get_drvdata(port->dev);
74 
75 	if (s->tx_enabled) {
76 		disable_irq(port->irq);
77 		s->tx_enabled = 0;
78 	}
79 }
80 
81 static void uart_clps711x_start_tx(struct uart_port *port)
82 {
83 	struct clps711x_port *s = dev_get_drvdata(port->dev);
84 
85 	if (!s->tx_enabled) {
86 		s->tx_enabled = 1;
87 		enable_irq(port->irq);
88 	}
89 }
90 
91 static irqreturn_t uart_clps711x_int_rx(int irq, void *dev_id)
92 {
93 	struct uart_port *port = dev_id;
94 	struct clps711x_port *s = dev_get_drvdata(port->dev);
95 	unsigned int status, flg;
96 	u16 ch;
97 
98 	for (;;) {
99 		u32 sysflg = 0;
100 
101 		regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
102 		if (sysflg & SYSFLG_URXFE)
103 			break;
104 
105 		ch = readw(port->membase + UARTDR_OFFSET);
106 		status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR);
107 		ch &= 0xff;
108 
109 		port->icount.rx++;
110 		flg = TTY_NORMAL;
111 
112 		if (unlikely(status)) {
113 			if (status & UARTDR_PARERR)
114 				port->icount.parity++;
115 			else if (status & UARTDR_FRMERR)
116 				port->icount.frame++;
117 			else if (status & UARTDR_OVERR)
118 				port->icount.overrun++;
119 
120 			status &= port->read_status_mask;
121 
122 			if (status & UARTDR_PARERR)
123 				flg = TTY_PARITY;
124 			else if (status & UARTDR_FRMERR)
125 				flg = TTY_FRAME;
126 			else if (status & UARTDR_OVERR)
127 				flg = TTY_OVERRUN;
128 		}
129 
130 		if (uart_handle_sysrq_char(port, ch))
131 			continue;
132 
133 		if (status & port->ignore_status_mask)
134 			continue;
135 
136 		uart_insert_char(port, status, UARTDR_OVERR, ch, flg);
137 	}
138 
139 	tty_flip_buffer_push(&port->state->port);
140 
141 	return IRQ_HANDLED;
142 }
143 
144 static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id)
145 {
146 	struct uart_port *port = dev_id;
147 	struct clps711x_port *s = dev_get_drvdata(port->dev);
148 	struct circ_buf *xmit = &port->state->xmit;
149 
150 	if (port->x_char) {
151 		writew(port->x_char, port->membase + UARTDR_OFFSET);
152 		port->icount.tx++;
153 		port->x_char = 0;
154 		return IRQ_HANDLED;
155 	}
156 
157 	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
158 		if (s->tx_enabled) {
159 			disable_irq_nosync(port->irq);
160 			s->tx_enabled = 0;
161 		}
162 		return IRQ_HANDLED;
163 	}
164 
165 	while (!uart_circ_empty(xmit)) {
166 		u32 sysflg = 0;
167 
168 		writew(xmit->buf[xmit->tail], port->membase + UARTDR_OFFSET);
169 		uart_xmit_advance(port, 1);
170 
171 		regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
172 		if (sysflg & SYSFLG_UTXFF)
173 			break;
174 	}
175 
176 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
177 		uart_write_wakeup(port);
178 
179 	return IRQ_HANDLED;
180 }
181 
182 static unsigned int uart_clps711x_tx_empty(struct uart_port *port)
183 {
184 	struct clps711x_port *s = dev_get_drvdata(port->dev);
185 	u32 sysflg = 0;
186 
187 	regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
188 
189 	return (sysflg & SYSFLG_UBUSY) ? 0 : TIOCSER_TEMT;
190 }
191 
192 static unsigned int uart_clps711x_get_mctrl(struct uart_port *port)
193 {
194 	unsigned int result = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
195 	struct clps711x_port *s = dev_get_drvdata(port->dev);
196 
197 	return mctrl_gpio_get(s->gpios, &result);
198 }
199 
200 static void uart_clps711x_set_mctrl(struct uart_port *port, unsigned int mctrl)
201 {
202 	struct clps711x_port *s = dev_get_drvdata(port->dev);
203 
204 	mctrl_gpio_set(s->gpios, mctrl);
205 }
206 
207 static void uart_clps711x_break_ctl(struct uart_port *port, int break_state)
208 {
209 	unsigned int ubrlcr;
210 
211 	ubrlcr = readl(port->membase + UBRLCR_OFFSET);
212 	if (break_state)
213 		ubrlcr |= UBRLCR_BREAK;
214 	else
215 		ubrlcr &= ~UBRLCR_BREAK;
216 	writel(ubrlcr, port->membase + UBRLCR_OFFSET);
217 }
218 
219 static void uart_clps711x_set_ldisc(struct uart_port *port,
220 				    struct ktermios *termios)
221 {
222 	if (!port->line) {
223 		struct clps711x_port *s = dev_get_drvdata(port->dev);
224 
225 		regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON1_SIREN,
226 				   (termios->c_line == N_IRDA) ? SYSCON1_SIREN : 0);
227 	}
228 }
229 
230 static int uart_clps711x_startup(struct uart_port *port)
231 {
232 	struct clps711x_port *s = dev_get_drvdata(port->dev);
233 
234 	/* Disable break */
235 	writel(readl(port->membase + UBRLCR_OFFSET) & ~UBRLCR_BREAK,
236 	       port->membase + UBRLCR_OFFSET);
237 
238 	/* Enable the port */
239 	return regmap_update_bits(s->syscon, SYSCON_OFFSET,
240 				  SYSCON_UARTEN, SYSCON_UARTEN);
241 }
242 
243 static void uart_clps711x_shutdown(struct uart_port *port)
244 {
245 	struct clps711x_port *s = dev_get_drvdata(port->dev);
246 
247 	/* Disable the port */
248 	regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0);
249 }
250 
251 static void uart_clps711x_set_termios(struct uart_port *port,
252 				      struct ktermios *termios,
253 				      const struct ktermios *old)
254 {
255 	u32 ubrlcr;
256 	unsigned int baud, quot;
257 
258 	/* Mask termios capabilities we don't support */
259 	termios->c_cflag &= ~CMSPAR;
260 	termios->c_iflag &= ~(BRKINT | IGNBRK);
261 
262 	/* Ask the core to calculate the divisor for us */
263 	baud = uart_get_baud_rate(port, termios, old, port->uartclk / 4096,
264 						      port->uartclk / 16);
265 	quot = uart_get_divisor(port, baud);
266 
267 	switch (termios->c_cflag & CSIZE) {
268 	case CS5:
269 		ubrlcr = UBRLCR_WRDLEN5;
270 		break;
271 	case CS6:
272 		ubrlcr = UBRLCR_WRDLEN6;
273 		break;
274 	case CS7:
275 		ubrlcr = UBRLCR_WRDLEN7;
276 		break;
277 	case CS8:
278 	default:
279 		ubrlcr = UBRLCR_WRDLEN8;
280 		break;
281 	}
282 
283 	if (termios->c_cflag & CSTOPB)
284 		ubrlcr |= UBRLCR_XSTOP;
285 
286 	if (termios->c_cflag & PARENB) {
287 		ubrlcr |= UBRLCR_PRTEN;
288 		if (!(termios->c_cflag & PARODD))
289 			ubrlcr |= UBRLCR_EVENPRT;
290 	}
291 
292 	/* Enable FIFO */
293 	ubrlcr |= UBRLCR_FIFOEN;
294 
295 	/* Set read status mask */
296 	port->read_status_mask = UARTDR_OVERR;
297 	if (termios->c_iflag & INPCK)
298 		port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR;
299 
300 	/* Set status ignore mask */
301 	port->ignore_status_mask = 0;
302 	if (!(termios->c_cflag & CREAD))
303 		port->ignore_status_mask |= UARTDR_OVERR | UARTDR_PARERR |
304 					    UARTDR_FRMERR;
305 
306 	uart_update_timeout(port, termios->c_cflag, baud);
307 
308 	writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET);
309 }
310 
311 static const char *uart_clps711x_type(struct uart_port *port)
312 {
313 	return (port->type == PORT_CLPS711X) ? "CLPS711X" : NULL;
314 }
315 
316 static void uart_clps711x_config_port(struct uart_port *port, int flags)
317 {
318 	if (flags & UART_CONFIG_TYPE)
319 		port->type = PORT_CLPS711X;
320 }
321 
322 static void uart_clps711x_nop_void(struct uart_port *port)
323 {
324 }
325 
326 static int uart_clps711x_nop_int(struct uart_port *port)
327 {
328 	return 0;
329 }
330 
331 static const struct uart_ops uart_clps711x_ops = {
332 	.tx_empty	= uart_clps711x_tx_empty,
333 	.set_mctrl	= uart_clps711x_set_mctrl,
334 	.get_mctrl	= uart_clps711x_get_mctrl,
335 	.stop_tx	= uart_clps711x_stop_tx,
336 	.start_tx	= uart_clps711x_start_tx,
337 	.stop_rx	= uart_clps711x_nop_void,
338 	.break_ctl	= uart_clps711x_break_ctl,
339 	.set_ldisc	= uart_clps711x_set_ldisc,
340 	.startup	= uart_clps711x_startup,
341 	.shutdown	= uart_clps711x_shutdown,
342 	.set_termios	= uart_clps711x_set_termios,
343 	.type		= uart_clps711x_type,
344 	.config_port	= uart_clps711x_config_port,
345 	.release_port	= uart_clps711x_nop_void,
346 	.request_port	= uart_clps711x_nop_int,
347 };
348 
349 #ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
350 static void uart_clps711x_console_putchar(struct uart_port *port, unsigned char ch)
351 {
352 	struct clps711x_port *s = dev_get_drvdata(port->dev);
353 	u32 sysflg = 0;
354 
355 	/* Wait for FIFO is not full */
356 	do {
357 		regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
358 	} while (sysflg & SYSFLG_UTXFF);
359 
360 	writew(ch, port->membase + UARTDR_OFFSET);
361 }
362 
363 static void uart_clps711x_console_write(struct console *co, const char *c,
364 					unsigned n)
365 {
366 	struct uart_port *port = clps711x_uart.state[co->index].uart_port;
367 	struct clps711x_port *s = dev_get_drvdata(port->dev);
368 	u32 sysflg = 0;
369 
370 	uart_console_write(port, c, n, uart_clps711x_console_putchar);
371 
372 	/* Wait for transmitter to become empty */
373 	do {
374 		regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
375 	} while (sysflg & SYSFLG_UBUSY);
376 }
377 
378 static int uart_clps711x_console_setup(struct console *co, char *options)
379 {
380 	int baud = 38400, bits = 8, parity = 'n', flow = 'n';
381 	int ret, index = co->index;
382 	struct clps711x_port *s;
383 	struct uart_port *port;
384 	unsigned int quot;
385 	u32 ubrlcr;
386 
387 	if (index < 0 || index >= UART_CLPS711X_NR)
388 		return -EINVAL;
389 
390 	port = clps711x_uart.state[index].uart_port;
391 	if (!port)
392 		return -ENODEV;
393 
394 	s = dev_get_drvdata(port->dev);
395 
396 	if (!options) {
397 		u32 syscon = 0;
398 
399 		regmap_read(s->syscon, SYSCON_OFFSET, &syscon);
400 		if (syscon & SYSCON_UARTEN) {
401 			ubrlcr = readl(port->membase + UBRLCR_OFFSET);
402 
403 			if (ubrlcr & UBRLCR_PRTEN) {
404 				if (ubrlcr & UBRLCR_EVENPRT)
405 					parity = 'e';
406 				else
407 					parity = 'o';
408 			}
409 
410 			if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
411 				bits = 7;
412 
413 			quot = ubrlcr & UBRLCR_BAUD_MASK;
414 			baud = port->uartclk / (16 * (quot + 1));
415 		}
416 	} else
417 		uart_parse_options(options, &baud, &parity, &bits, &flow);
418 
419 	ret = uart_set_options(port, co, baud, parity, bits, flow);
420 	if (ret)
421 		return ret;
422 
423 	return regmap_update_bits(s->syscon, SYSCON_OFFSET,
424 				  SYSCON_UARTEN, SYSCON_UARTEN);
425 }
426 
427 static struct console clps711x_console = {
428 	.name	= UART_CLPS711X_DEVNAME,
429 	.device	= uart_console_device,
430 	.write	= uart_clps711x_console_write,
431 	.setup	= uart_clps711x_console_setup,
432 	.flags	= CON_PRINTBUFFER,
433 	.index	= -1,
434 };
435 #endif
436 
437 static int uart_clps711x_probe(struct platform_device *pdev)
438 {
439 	struct device_node *np = pdev->dev.of_node;
440 	struct clps711x_port *s;
441 	struct resource *res;
442 	struct clk *uart_clk;
443 	int irq, ret;
444 
445 	s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
446 	if (!s)
447 		return -ENOMEM;
448 
449 	uart_clk = devm_clk_get(&pdev->dev, NULL);
450 	if (IS_ERR(uart_clk))
451 		return PTR_ERR(uart_clk);
452 
453 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
454 	s->port.membase = devm_ioremap_resource(&pdev->dev, res);
455 	if (IS_ERR(s->port.membase))
456 		return PTR_ERR(s->port.membase);
457 
458 	irq = platform_get_irq(pdev, 0);
459 	if (irq < 0)
460 		return irq;
461 	s->port.irq = irq;
462 
463 	s->rx_irq = platform_get_irq(pdev, 1);
464 	if (s->rx_irq < 0)
465 		return s->rx_irq;
466 
467 	s->syscon = syscon_regmap_lookup_by_phandle(np, "syscon");
468 	if (IS_ERR(s->syscon))
469 		return PTR_ERR(s->syscon);
470 
471 	s->port.line		= of_alias_get_id(np, "serial");
472 	s->port.dev		= &pdev->dev;
473 	s->port.iotype		= UPIO_MEM32;
474 	s->port.mapbase		= res->start;
475 	s->port.type		= PORT_CLPS711X;
476 	s->port.fifosize	= 16;
477 	s->port.has_sysrq	= IS_ENABLED(CONFIG_SERIAL_CLPS711X_CONSOLE);
478 	s->port.flags		= UPF_SKIP_TEST | UPF_FIXED_TYPE;
479 	s->port.uartclk		= clk_get_rate(uart_clk);
480 	s->port.ops		= &uart_clps711x_ops;
481 
482 	platform_set_drvdata(pdev, s);
483 
484 	s->gpios = mctrl_gpio_init_noauto(&pdev->dev, 0);
485 	if (IS_ERR(s->gpios))
486 	    return PTR_ERR(s->gpios);
487 
488 	ret = uart_add_one_port(&clps711x_uart, &s->port);
489 	if (ret)
490 		return ret;
491 
492 	/* Disable port */
493 	if (!uart_console(&s->port))
494 		regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0);
495 
496 	s->tx_enabled = 1;
497 
498 	ret = devm_request_irq(&pdev->dev, s->port.irq, uart_clps711x_int_tx, 0,
499 			       dev_name(&pdev->dev), &s->port);
500 	if (ret) {
501 		uart_remove_one_port(&clps711x_uart, &s->port);
502 		return ret;
503 	}
504 
505 	ret = devm_request_irq(&pdev->dev, s->rx_irq, uart_clps711x_int_rx, 0,
506 			       dev_name(&pdev->dev), &s->port);
507 	if (ret)
508 		uart_remove_one_port(&clps711x_uart, &s->port);
509 
510 	return ret;
511 }
512 
513 static int uart_clps711x_remove(struct platform_device *pdev)
514 {
515 	struct clps711x_port *s = platform_get_drvdata(pdev);
516 
517 	uart_remove_one_port(&clps711x_uart, &s->port);
518 
519 	return 0;
520 }
521 
522 static const struct of_device_id __maybe_unused clps711x_uart_dt_ids[] = {
523 	{ .compatible = "cirrus,ep7209-uart", },
524 	{ }
525 };
526 MODULE_DEVICE_TABLE(of, clps711x_uart_dt_ids);
527 
528 static struct platform_driver clps711x_uart_platform = {
529 	.driver = {
530 		.name		= "clps711x-uart",
531 		.of_match_table	= of_match_ptr(clps711x_uart_dt_ids),
532 	},
533 	.probe	= uart_clps711x_probe,
534 	.remove	= uart_clps711x_remove,
535 };
536 
537 static int __init uart_clps711x_init(void)
538 {
539 	int ret;
540 
541 #ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
542 	clps711x_uart.cons = &clps711x_console;
543 	clps711x_console.data = &clps711x_uart;
544 #endif
545 
546 	ret = uart_register_driver(&clps711x_uart);
547 	if (ret)
548 		return ret;
549 
550 	return platform_driver_register(&clps711x_uart_platform);
551 }
552 module_init(uart_clps711x_init);
553 
554 static void __exit uart_clps711x_exit(void)
555 {
556 	platform_driver_unregister(&clps711x_uart_platform);
557 	uart_unregister_driver(&clps711x_uart);
558 }
559 module_exit(uart_clps711x_exit);
560 
561 MODULE_AUTHOR("Deep Blue Solutions Ltd");
562 MODULE_DESCRIPTION("CLPS711X serial driver");
563 MODULE_LICENSE("GPL");
564