1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Derived from many drivers using generic_serial interface. 7 * 8 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 9 * 10 * Serial driver for BCM63xx integrated UART. 11 * 12 * Hardware flow control was _not_ tested since I only have RX/TX on 13 * my board. 14 */ 15 16 #if defined(CONFIG_SERIAL_BCM63XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 17 #define SUPPORT_SYSRQ 18 #endif 19 20 #include <linux/kernel.h> 21 #include <linux/platform_device.h> 22 #include <linux/init.h> 23 #include <linux/delay.h> 24 #include <linux/module.h> 25 #include <linux/console.h> 26 #include <linux/clk.h> 27 #include <linux/tty.h> 28 #include <linux/tty_flip.h> 29 #include <linux/sysrq.h> 30 #include <linux/serial.h> 31 #include <linux/serial_core.h> 32 33 #include <bcm63xx_clk.h> 34 #include <bcm63xx_irq.h> 35 #include <bcm63xx_regs.h> 36 #include <bcm63xx_io.h> 37 38 #define BCM63XX_NR_UARTS 2 39 40 static struct uart_port ports[BCM63XX_NR_UARTS]; 41 42 /* 43 * rx interrupt mask / stat 44 * 45 * mask: 46 * - rx fifo full 47 * - rx fifo above threshold 48 * - rx fifo not empty for too long 49 */ 50 #define UART_RX_INT_MASK (UART_IR_MASK(UART_IR_RXOVER) | \ 51 UART_IR_MASK(UART_IR_RXTHRESH) | \ 52 UART_IR_MASK(UART_IR_RXTIMEOUT)) 53 54 #define UART_RX_INT_STAT (UART_IR_STAT(UART_IR_RXOVER) | \ 55 UART_IR_STAT(UART_IR_RXTHRESH) | \ 56 UART_IR_STAT(UART_IR_RXTIMEOUT)) 57 58 /* 59 * tx interrupt mask / stat 60 * 61 * mask: 62 * - tx fifo empty 63 * - tx fifo below threshold 64 */ 65 #define UART_TX_INT_MASK (UART_IR_MASK(UART_IR_TXEMPTY) | \ 66 UART_IR_MASK(UART_IR_TXTRESH)) 67 68 #define UART_TX_INT_STAT (UART_IR_STAT(UART_IR_TXEMPTY) | \ 69 UART_IR_STAT(UART_IR_TXTRESH)) 70 71 /* 72 * external input interrupt 73 * 74 * mask: any edge on CTS, DCD 75 */ 76 #define UART_EXTINP_INT_MASK (UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \ 77 UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD)) 78 79 /* 80 * handy uart register accessor 81 */ 82 static inline unsigned int bcm_uart_readl(struct uart_port *port, 83 unsigned int offset) 84 { 85 return bcm_readl(port->membase + offset); 86 } 87 88 static inline void bcm_uart_writel(struct uart_port *port, 89 unsigned int value, unsigned int offset) 90 { 91 bcm_writel(value, port->membase + offset); 92 } 93 94 /* 95 * serial core request to check if uart tx fifo is empty 96 */ 97 static unsigned int bcm_uart_tx_empty(struct uart_port *port) 98 { 99 unsigned int val; 100 101 val = bcm_uart_readl(port, UART_IR_REG); 102 return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0; 103 } 104 105 /* 106 * serial core request to set RTS and DTR pin state and loopback mode 107 */ 108 static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 109 { 110 unsigned int val; 111 112 val = bcm_uart_readl(port, UART_MCTL_REG); 113 val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK); 114 /* invert of written value is reflected on the pin */ 115 if (!(mctrl & TIOCM_DTR)) 116 val |= UART_MCTL_DTR_MASK; 117 if (!(mctrl & TIOCM_RTS)) 118 val |= UART_MCTL_RTS_MASK; 119 bcm_uart_writel(port, val, UART_MCTL_REG); 120 121 val = bcm_uart_readl(port, UART_CTL_REG); 122 if (mctrl & TIOCM_LOOP) 123 val |= UART_CTL_LOOPBACK_MASK; 124 else 125 val &= ~UART_CTL_LOOPBACK_MASK; 126 bcm_uart_writel(port, val, UART_CTL_REG); 127 } 128 129 /* 130 * serial core request to return RI, CTS, DCD and DSR pin state 131 */ 132 static unsigned int bcm_uart_get_mctrl(struct uart_port *port) 133 { 134 unsigned int val, mctrl; 135 136 mctrl = 0; 137 val = bcm_uart_readl(port, UART_EXTINP_REG); 138 if (val & UART_EXTINP_RI_MASK) 139 mctrl |= TIOCM_RI; 140 if (val & UART_EXTINP_CTS_MASK) 141 mctrl |= TIOCM_CTS; 142 if (val & UART_EXTINP_DCD_MASK) 143 mctrl |= TIOCM_CD; 144 if (val & UART_EXTINP_DSR_MASK) 145 mctrl |= TIOCM_DSR; 146 return mctrl; 147 } 148 149 /* 150 * serial core request to disable tx ASAP (used for flow control) 151 */ 152 static void bcm_uart_stop_tx(struct uart_port *port) 153 { 154 unsigned int val; 155 156 val = bcm_uart_readl(port, UART_CTL_REG); 157 val &= ~(UART_CTL_TXEN_MASK); 158 bcm_uart_writel(port, val, UART_CTL_REG); 159 160 val = bcm_uart_readl(port, UART_IR_REG); 161 val &= ~UART_TX_INT_MASK; 162 bcm_uart_writel(port, val, UART_IR_REG); 163 } 164 165 /* 166 * serial core request to (re)enable tx 167 */ 168 static void bcm_uart_start_tx(struct uart_port *port) 169 { 170 unsigned int val; 171 172 val = bcm_uart_readl(port, UART_IR_REG); 173 val |= UART_TX_INT_MASK; 174 bcm_uart_writel(port, val, UART_IR_REG); 175 176 val = bcm_uart_readl(port, UART_CTL_REG); 177 val |= UART_CTL_TXEN_MASK; 178 bcm_uart_writel(port, val, UART_CTL_REG); 179 } 180 181 /* 182 * serial core request to stop rx, called before port shutdown 183 */ 184 static void bcm_uart_stop_rx(struct uart_port *port) 185 { 186 unsigned int val; 187 188 val = bcm_uart_readl(port, UART_IR_REG); 189 val &= ~UART_RX_INT_MASK; 190 bcm_uart_writel(port, val, UART_IR_REG); 191 } 192 193 /* 194 * serial core request to enable modem status interrupt reporting 195 */ 196 static void bcm_uart_enable_ms(struct uart_port *port) 197 { 198 unsigned int val; 199 200 val = bcm_uart_readl(port, UART_IR_REG); 201 val |= UART_IR_MASK(UART_IR_EXTIP); 202 bcm_uart_writel(port, val, UART_IR_REG); 203 } 204 205 /* 206 * serial core request to start/stop emitting break char 207 */ 208 static void bcm_uart_break_ctl(struct uart_port *port, int ctl) 209 { 210 unsigned long flags; 211 unsigned int val; 212 213 spin_lock_irqsave(&port->lock, flags); 214 215 val = bcm_uart_readl(port, UART_CTL_REG); 216 if (ctl) 217 val |= UART_CTL_XMITBRK_MASK; 218 else 219 val &= ~UART_CTL_XMITBRK_MASK; 220 bcm_uart_writel(port, val, UART_CTL_REG); 221 222 spin_unlock_irqrestore(&port->lock, flags); 223 } 224 225 /* 226 * return port type in string format 227 */ 228 static const char *bcm_uart_type(struct uart_port *port) 229 { 230 return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL; 231 } 232 233 /* 234 * read all chars in rx fifo and send them to core 235 */ 236 static void bcm_uart_do_rx(struct uart_port *port) 237 { 238 struct tty_port *port = &port->state->port; 239 unsigned int max_count; 240 241 /* limit number of char read in interrupt, should not be 242 * higher than fifo size anyway since we're much faster than 243 * serial port */ 244 max_count = 32; 245 do { 246 unsigned int iestat, c, cstat; 247 char flag; 248 249 /* get overrun/fifo empty information from ier 250 * register */ 251 iestat = bcm_uart_readl(port, UART_IR_REG); 252 253 if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) { 254 unsigned int val; 255 256 /* fifo reset is required to clear 257 * interrupt */ 258 val = bcm_uart_readl(port, UART_CTL_REG); 259 val |= UART_CTL_RSTRXFIFO_MASK; 260 bcm_uart_writel(port, val, UART_CTL_REG); 261 262 port->icount.overrun++; 263 tty_insert_flip_char(port, 0, TTY_OVERRUN); 264 } 265 266 if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY))) 267 break; 268 269 cstat = c = bcm_uart_readl(port, UART_FIFO_REG); 270 port->icount.rx++; 271 flag = TTY_NORMAL; 272 c &= 0xff; 273 274 if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) { 275 /* do stats first */ 276 if (cstat & UART_FIFO_BRKDET_MASK) { 277 port->icount.brk++; 278 if (uart_handle_break(port)) 279 continue; 280 } 281 282 if (cstat & UART_FIFO_PARERR_MASK) 283 port->icount.parity++; 284 if (cstat & UART_FIFO_FRAMEERR_MASK) 285 port->icount.frame++; 286 287 /* update flag wrt read_status_mask */ 288 cstat &= port->read_status_mask; 289 if (cstat & UART_FIFO_BRKDET_MASK) 290 flag = TTY_BREAK; 291 if (cstat & UART_FIFO_FRAMEERR_MASK) 292 flag = TTY_FRAME; 293 if (cstat & UART_FIFO_PARERR_MASK) 294 flag = TTY_PARITY; 295 } 296 297 if (uart_handle_sysrq_char(port, c)) 298 continue; 299 300 301 if ((cstat & port->ignore_status_mask) == 0) 302 tty_insert_flip_char(port, c, flag); 303 304 } while (--max_count); 305 306 tty_flip_buffer_push(port); 307 } 308 309 /* 310 * fill tx fifo with chars to send, stop when fifo is about to be full 311 * or when all chars have been sent. 312 */ 313 static void bcm_uart_do_tx(struct uart_port *port) 314 { 315 struct circ_buf *xmit; 316 unsigned int val, max_count; 317 318 if (port->x_char) { 319 bcm_uart_writel(port, port->x_char, UART_FIFO_REG); 320 port->icount.tx++; 321 port->x_char = 0; 322 return; 323 } 324 325 if (uart_tx_stopped(port)) { 326 bcm_uart_stop_tx(port); 327 return; 328 } 329 330 xmit = &port->state->xmit; 331 if (uart_circ_empty(xmit)) 332 goto txq_empty; 333 334 val = bcm_uart_readl(port, UART_MCTL_REG); 335 val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT; 336 max_count = port->fifosize - val; 337 338 while (max_count--) { 339 unsigned int c; 340 341 c = xmit->buf[xmit->tail]; 342 bcm_uart_writel(port, c, UART_FIFO_REG); 343 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 344 port->icount.tx++; 345 if (uart_circ_empty(xmit)) 346 break; 347 } 348 349 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 350 uart_write_wakeup(port); 351 352 if (uart_circ_empty(xmit)) 353 goto txq_empty; 354 return; 355 356 txq_empty: 357 /* nothing to send, disable transmit interrupt */ 358 val = bcm_uart_readl(port, UART_IR_REG); 359 val &= ~UART_TX_INT_MASK; 360 bcm_uart_writel(port, val, UART_IR_REG); 361 return; 362 } 363 364 /* 365 * process uart interrupt 366 */ 367 static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id) 368 { 369 struct uart_port *port; 370 unsigned int irqstat; 371 372 port = dev_id; 373 spin_lock(&port->lock); 374 375 irqstat = bcm_uart_readl(port, UART_IR_REG); 376 if (irqstat & UART_RX_INT_STAT) 377 bcm_uart_do_rx(port); 378 379 if (irqstat & UART_TX_INT_STAT) 380 bcm_uart_do_tx(port); 381 382 if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) { 383 unsigned int estat; 384 385 estat = bcm_uart_readl(port, UART_EXTINP_REG); 386 if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS)) 387 uart_handle_cts_change(port, 388 estat & UART_EXTINP_CTS_MASK); 389 if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD)) 390 uart_handle_dcd_change(port, 391 estat & UART_EXTINP_DCD_MASK); 392 } 393 394 spin_unlock(&port->lock); 395 return IRQ_HANDLED; 396 } 397 398 /* 399 * enable rx & tx operation on uart 400 */ 401 static void bcm_uart_enable(struct uart_port *port) 402 { 403 unsigned int val; 404 405 val = bcm_uart_readl(port, UART_CTL_REG); 406 val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK); 407 bcm_uart_writel(port, val, UART_CTL_REG); 408 } 409 410 /* 411 * disable rx & tx operation on uart 412 */ 413 static void bcm_uart_disable(struct uart_port *port) 414 { 415 unsigned int val; 416 417 val = bcm_uart_readl(port, UART_CTL_REG); 418 val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | 419 UART_CTL_RXEN_MASK); 420 bcm_uart_writel(port, val, UART_CTL_REG); 421 } 422 423 /* 424 * clear all unread data in rx fifo and unsent data in tx fifo 425 */ 426 static void bcm_uart_flush(struct uart_port *port) 427 { 428 unsigned int val; 429 430 /* empty rx and tx fifo */ 431 val = bcm_uart_readl(port, UART_CTL_REG); 432 val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK; 433 bcm_uart_writel(port, val, UART_CTL_REG); 434 435 /* read any pending char to make sure all irq status are 436 * cleared */ 437 (void)bcm_uart_readl(port, UART_FIFO_REG); 438 } 439 440 /* 441 * serial core request to initialize uart and start rx operation 442 */ 443 static int bcm_uart_startup(struct uart_port *port) 444 { 445 unsigned int val; 446 int ret; 447 448 /* mask all irq and flush port */ 449 bcm_uart_disable(port); 450 bcm_uart_writel(port, 0, UART_IR_REG); 451 bcm_uart_flush(port); 452 453 /* clear any pending external input interrupt */ 454 (void)bcm_uart_readl(port, UART_EXTINP_REG); 455 456 /* set rx/tx fifo thresh to fifo half size */ 457 val = bcm_uart_readl(port, UART_MCTL_REG); 458 val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK); 459 val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT; 460 val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT; 461 bcm_uart_writel(port, val, UART_MCTL_REG); 462 463 /* set rx fifo timeout to 1 char time */ 464 val = bcm_uart_readl(port, UART_CTL_REG); 465 val &= ~UART_CTL_RXTMOUTCNT_MASK; 466 val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT; 467 bcm_uart_writel(port, val, UART_CTL_REG); 468 469 /* report any edge on dcd and cts */ 470 val = UART_EXTINP_INT_MASK; 471 val |= UART_EXTINP_DCD_NOSENSE_MASK; 472 val |= UART_EXTINP_CTS_NOSENSE_MASK; 473 bcm_uart_writel(port, val, UART_EXTINP_REG); 474 475 /* register irq and enable rx interrupts */ 476 ret = request_irq(port->irq, bcm_uart_interrupt, 0, 477 bcm_uart_type(port), port); 478 if (ret) 479 return ret; 480 bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG); 481 bcm_uart_enable(port); 482 return 0; 483 } 484 485 /* 486 * serial core request to flush & disable uart 487 */ 488 static void bcm_uart_shutdown(struct uart_port *port) 489 { 490 unsigned long flags; 491 492 spin_lock_irqsave(&port->lock, flags); 493 bcm_uart_writel(port, 0, UART_IR_REG); 494 spin_unlock_irqrestore(&port->lock, flags); 495 496 bcm_uart_disable(port); 497 bcm_uart_flush(port); 498 free_irq(port->irq, port); 499 } 500 501 /* 502 * serial core request to change current uart setting 503 */ 504 static void bcm_uart_set_termios(struct uart_port *port, 505 struct ktermios *new, 506 struct ktermios *old) 507 { 508 unsigned int ctl, baud, quot, ier; 509 unsigned long flags; 510 511 spin_lock_irqsave(&port->lock, flags); 512 513 /* disable uart while changing speed */ 514 bcm_uart_disable(port); 515 bcm_uart_flush(port); 516 517 /* update Control register */ 518 ctl = bcm_uart_readl(port, UART_CTL_REG); 519 ctl &= ~UART_CTL_BITSPERSYM_MASK; 520 521 switch (new->c_cflag & CSIZE) { 522 case CS5: 523 ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT); 524 break; 525 case CS6: 526 ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT); 527 break; 528 case CS7: 529 ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT); 530 break; 531 default: 532 ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT); 533 break; 534 } 535 536 ctl &= ~UART_CTL_STOPBITS_MASK; 537 if (new->c_cflag & CSTOPB) 538 ctl |= UART_CTL_STOPBITS_2; 539 else 540 ctl |= UART_CTL_STOPBITS_1; 541 542 ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK); 543 if (new->c_cflag & PARENB) 544 ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK); 545 ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK); 546 if (new->c_cflag & PARODD) 547 ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK); 548 bcm_uart_writel(port, ctl, UART_CTL_REG); 549 550 /* update Baudword register */ 551 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 552 quot = uart_get_divisor(port, baud) - 1; 553 bcm_uart_writel(port, quot, UART_BAUD_REG); 554 555 /* update Interrupt register */ 556 ier = bcm_uart_readl(port, UART_IR_REG); 557 558 ier &= ~UART_IR_MASK(UART_IR_EXTIP); 559 if (UART_ENABLE_MS(port, new->c_cflag)) 560 ier |= UART_IR_MASK(UART_IR_EXTIP); 561 562 bcm_uart_writel(port, ier, UART_IR_REG); 563 564 /* update read/ignore mask */ 565 port->read_status_mask = UART_FIFO_VALID_MASK; 566 if (new->c_iflag & INPCK) { 567 port->read_status_mask |= UART_FIFO_FRAMEERR_MASK; 568 port->read_status_mask |= UART_FIFO_PARERR_MASK; 569 } 570 if (new->c_iflag & (BRKINT)) 571 port->read_status_mask |= UART_FIFO_BRKDET_MASK; 572 573 port->ignore_status_mask = 0; 574 if (new->c_iflag & IGNPAR) 575 port->ignore_status_mask |= UART_FIFO_PARERR_MASK; 576 if (new->c_iflag & IGNBRK) 577 port->ignore_status_mask |= UART_FIFO_BRKDET_MASK; 578 if (!(new->c_cflag & CREAD)) 579 port->ignore_status_mask |= UART_FIFO_VALID_MASK; 580 581 uart_update_timeout(port, new->c_cflag, baud); 582 bcm_uart_enable(port); 583 spin_unlock_irqrestore(&port->lock, flags); 584 } 585 586 /* 587 * serial core request to claim uart iomem 588 */ 589 static int bcm_uart_request_port(struct uart_port *port) 590 { 591 unsigned int size; 592 593 size = RSET_UART_SIZE; 594 if (!request_mem_region(port->mapbase, size, "bcm63xx")) { 595 dev_err(port->dev, "Memory region busy\n"); 596 return -EBUSY; 597 } 598 599 port->membase = ioremap(port->mapbase, size); 600 if (!port->membase) { 601 dev_err(port->dev, "Unable to map registers\n"); 602 release_mem_region(port->mapbase, size); 603 return -EBUSY; 604 } 605 return 0; 606 } 607 608 /* 609 * serial core request to release uart iomem 610 */ 611 static void bcm_uart_release_port(struct uart_port *port) 612 { 613 release_mem_region(port->mapbase, RSET_UART_SIZE); 614 iounmap(port->membase); 615 } 616 617 /* 618 * serial core request to do any port required autoconfiguration 619 */ 620 static void bcm_uart_config_port(struct uart_port *port, int flags) 621 { 622 if (flags & UART_CONFIG_TYPE) { 623 if (bcm_uart_request_port(port)) 624 return; 625 port->type = PORT_BCM63XX; 626 } 627 } 628 629 /* 630 * serial core request to check that port information in serinfo are 631 * suitable 632 */ 633 static int bcm_uart_verify_port(struct uart_port *port, 634 struct serial_struct *serinfo) 635 { 636 if (port->type != PORT_BCM63XX) 637 return -EINVAL; 638 if (port->irq != serinfo->irq) 639 return -EINVAL; 640 if (port->iotype != serinfo->io_type) 641 return -EINVAL; 642 if (port->mapbase != (unsigned long)serinfo->iomem_base) 643 return -EINVAL; 644 return 0; 645 } 646 647 /* serial core callbacks */ 648 static struct uart_ops bcm_uart_ops = { 649 .tx_empty = bcm_uart_tx_empty, 650 .get_mctrl = bcm_uart_get_mctrl, 651 .set_mctrl = bcm_uart_set_mctrl, 652 .start_tx = bcm_uart_start_tx, 653 .stop_tx = bcm_uart_stop_tx, 654 .stop_rx = bcm_uart_stop_rx, 655 .enable_ms = bcm_uart_enable_ms, 656 .break_ctl = bcm_uart_break_ctl, 657 .startup = bcm_uart_startup, 658 .shutdown = bcm_uart_shutdown, 659 .set_termios = bcm_uart_set_termios, 660 .type = bcm_uart_type, 661 .release_port = bcm_uart_release_port, 662 .request_port = bcm_uart_request_port, 663 .config_port = bcm_uart_config_port, 664 .verify_port = bcm_uart_verify_port, 665 }; 666 667 668 669 #ifdef CONFIG_SERIAL_BCM63XX_CONSOLE 670 static inline void wait_for_xmitr(struct uart_port *port) 671 { 672 unsigned int tmout; 673 674 /* Wait up to 10ms for the character(s) to be sent. */ 675 tmout = 10000; 676 while (--tmout) { 677 unsigned int val; 678 679 val = bcm_uart_readl(port, UART_IR_REG); 680 if (val & UART_IR_STAT(UART_IR_TXEMPTY)) 681 break; 682 udelay(1); 683 } 684 685 /* Wait up to 1s for flow control if necessary */ 686 if (port->flags & UPF_CONS_FLOW) { 687 tmout = 1000000; 688 while (--tmout) { 689 unsigned int val; 690 691 val = bcm_uart_readl(port, UART_EXTINP_REG); 692 if (val & UART_EXTINP_CTS_MASK) 693 break; 694 udelay(1); 695 } 696 } 697 } 698 699 /* 700 * output given char 701 */ 702 static void bcm_console_putchar(struct uart_port *port, int ch) 703 { 704 wait_for_xmitr(port); 705 bcm_uart_writel(port, ch, UART_FIFO_REG); 706 } 707 708 /* 709 * console core request to output given string 710 */ 711 static void bcm_console_write(struct console *co, const char *s, 712 unsigned int count) 713 { 714 struct uart_port *port; 715 unsigned long flags; 716 int locked; 717 718 port = &ports[co->index]; 719 720 local_irq_save(flags); 721 if (port->sysrq) { 722 /* bcm_uart_interrupt() already took the lock */ 723 locked = 0; 724 } else if (oops_in_progress) { 725 locked = spin_trylock(&port->lock); 726 } else { 727 spin_lock(&port->lock); 728 locked = 1; 729 } 730 731 /* call helper to deal with \r\n */ 732 uart_console_write(port, s, count, bcm_console_putchar); 733 734 /* and wait for char to be transmitted */ 735 wait_for_xmitr(port); 736 737 if (locked) 738 spin_unlock(&port->lock); 739 local_irq_restore(flags); 740 } 741 742 /* 743 * console core request to setup given console, find matching uart 744 * port and setup it. 745 */ 746 static int bcm_console_setup(struct console *co, char *options) 747 { 748 struct uart_port *port; 749 int baud = 9600; 750 int bits = 8; 751 int parity = 'n'; 752 int flow = 'n'; 753 754 if (co->index < 0 || co->index >= BCM63XX_NR_UARTS) 755 return -EINVAL; 756 port = &ports[co->index]; 757 if (!port->membase) 758 return -ENODEV; 759 if (options) 760 uart_parse_options(options, &baud, &parity, &bits, &flow); 761 762 return uart_set_options(port, co, baud, parity, bits, flow); 763 } 764 765 static struct uart_driver bcm_uart_driver; 766 767 static struct console bcm63xx_console = { 768 .name = "ttyS", 769 .write = bcm_console_write, 770 .device = uart_console_device, 771 .setup = bcm_console_setup, 772 .flags = CON_PRINTBUFFER, 773 .index = -1, 774 .data = &bcm_uart_driver, 775 }; 776 777 static int __init bcm63xx_console_init(void) 778 { 779 register_console(&bcm63xx_console); 780 return 0; 781 } 782 783 console_initcall(bcm63xx_console_init); 784 785 #define BCM63XX_CONSOLE (&bcm63xx_console) 786 #else 787 #define BCM63XX_CONSOLE NULL 788 #endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */ 789 790 static struct uart_driver bcm_uart_driver = { 791 .owner = THIS_MODULE, 792 .driver_name = "bcm63xx_uart", 793 .dev_name = "ttyS", 794 .major = TTY_MAJOR, 795 .minor = 64, 796 .nr = BCM63XX_NR_UARTS, 797 .cons = BCM63XX_CONSOLE, 798 }; 799 800 /* 801 * platform driver probe/remove callback 802 */ 803 static int bcm_uart_probe(struct platform_device *pdev) 804 { 805 struct resource *res_mem, *res_irq; 806 struct uart_port *port; 807 struct clk *clk; 808 int ret; 809 810 if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS) 811 return -EINVAL; 812 813 if (ports[pdev->id].membase) 814 return -EBUSY; 815 816 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 817 if (!res_mem) 818 return -ENODEV; 819 820 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 821 if (!res_irq) 822 return -ENODEV; 823 824 clk = clk_get(&pdev->dev, "periph"); 825 if (IS_ERR(clk)) 826 return -ENODEV; 827 828 port = &ports[pdev->id]; 829 memset(port, 0, sizeof(*port)); 830 port->iotype = UPIO_MEM; 831 port->mapbase = res_mem->start; 832 port->irq = res_irq->start; 833 port->ops = &bcm_uart_ops; 834 port->flags = UPF_BOOT_AUTOCONF; 835 port->dev = &pdev->dev; 836 port->fifosize = 16; 837 port->uartclk = clk_get_rate(clk) / 2; 838 port->line = pdev->id; 839 clk_put(clk); 840 841 ret = uart_add_one_port(&bcm_uart_driver, port); 842 if (ret) { 843 ports[pdev->id].membase = 0; 844 return ret; 845 } 846 platform_set_drvdata(pdev, port); 847 return 0; 848 } 849 850 static int bcm_uart_remove(struct platform_device *pdev) 851 { 852 struct uart_port *port; 853 854 port = platform_get_drvdata(pdev); 855 uart_remove_one_port(&bcm_uart_driver, port); 856 platform_set_drvdata(pdev, NULL); 857 /* mark port as free */ 858 ports[pdev->id].membase = 0; 859 return 0; 860 } 861 862 /* 863 * platform driver stuff 864 */ 865 static struct platform_driver bcm_uart_platform_driver = { 866 .probe = bcm_uart_probe, 867 .remove = bcm_uart_remove, 868 .driver = { 869 .owner = THIS_MODULE, 870 .name = "bcm63xx_uart", 871 }, 872 }; 873 874 static int __init bcm_uart_init(void) 875 { 876 int ret; 877 878 ret = uart_register_driver(&bcm_uart_driver); 879 if (ret) 880 return ret; 881 882 ret = platform_driver_register(&bcm_uart_platform_driver); 883 if (ret) 884 uart_unregister_driver(&bcm_uart_driver); 885 886 return ret; 887 } 888 889 static void __exit bcm_uart_exit(void) 890 { 891 platform_driver_unregister(&bcm_uart_platform_driver); 892 uart_unregister_driver(&bcm_uart_driver); 893 } 894 895 module_init(bcm_uart_init); 896 module_exit(bcm_uart_exit); 897 898 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>"); 899 MODULE_DESCRIPTION("Broadcom 63<xx integrated uart driver"); 900 MODULE_LICENSE("GPL"); 901