1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Derived from many drivers using generic_serial interface.
4  *
5  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
6  *
7  *  Serial driver for BCM63xx integrated UART.
8  *
9  * Hardware flow control was _not_ tested since I only have RX/TX on
10  * my board.
11  */
12 
13 #include <linux/kernel.h>
14 #include <linux/platform_device.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/module.h>
18 #include <linux/console.h>
19 #include <linux/clk.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
22 #include <linux/sysrq.h>
23 #include <linux/serial.h>
24 #include <linux/serial_core.h>
25 #include <linux/serial_bcm63xx.h>
26 #include <linux/io.h>
27 #include <linux/of.h>
28 
29 #define BCM63XX_NR_UARTS	2
30 
31 static struct uart_port ports[BCM63XX_NR_UARTS];
32 
33 /*
34  * rx interrupt mask / stat
35  *
36  * mask:
37  *  - rx fifo full
38  *  - rx fifo above threshold
39  *  - rx fifo not empty for too long
40  */
41 #define UART_RX_INT_MASK	(UART_IR_MASK(UART_IR_RXOVER) |		\
42 				UART_IR_MASK(UART_IR_RXTHRESH) |	\
43 				UART_IR_MASK(UART_IR_RXTIMEOUT))
44 
45 #define UART_RX_INT_STAT	(UART_IR_STAT(UART_IR_RXOVER) |		\
46 				UART_IR_STAT(UART_IR_RXTHRESH) |	\
47 				UART_IR_STAT(UART_IR_RXTIMEOUT))
48 
49 /*
50  * tx interrupt mask / stat
51  *
52  * mask:
53  * - tx fifo empty
54  * - tx fifo below threshold
55  */
56 #define UART_TX_INT_MASK	(UART_IR_MASK(UART_IR_TXEMPTY) |	\
57 				UART_IR_MASK(UART_IR_TXTRESH))
58 
59 #define UART_TX_INT_STAT	(UART_IR_STAT(UART_IR_TXEMPTY) |	\
60 				UART_IR_STAT(UART_IR_TXTRESH))
61 
62 /*
63  * external input interrupt
64  *
65  * mask: any edge on CTS, DCD
66  */
67 #define UART_EXTINP_INT_MASK	(UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \
68 				 UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD))
69 
70 /*
71  * handy uart register accessor
72  */
73 static inline unsigned int bcm_uart_readl(struct uart_port *port,
74 					 unsigned int offset)
75 {
76 	return __raw_readl(port->membase + offset);
77 }
78 
79 static inline void bcm_uart_writel(struct uart_port *port,
80 				  unsigned int value, unsigned int offset)
81 {
82 	__raw_writel(value, port->membase + offset);
83 }
84 
85 /*
86  * serial core request to check if uart tx fifo is empty
87  */
88 static unsigned int bcm_uart_tx_empty(struct uart_port *port)
89 {
90 	unsigned int val;
91 
92 	val = bcm_uart_readl(port, UART_IR_REG);
93 	return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0;
94 }
95 
96 /*
97  * serial core request to set RTS and DTR pin state and loopback mode
98  */
99 static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
100 {
101 	unsigned int val;
102 
103 	val = bcm_uart_readl(port, UART_MCTL_REG);
104 	val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK);
105 	/* invert of written value is reflected on the pin */
106 	if (!(mctrl & TIOCM_DTR))
107 		val |= UART_MCTL_DTR_MASK;
108 	if (!(mctrl & TIOCM_RTS))
109 		val |= UART_MCTL_RTS_MASK;
110 	bcm_uart_writel(port, val, UART_MCTL_REG);
111 
112 	val = bcm_uart_readl(port, UART_CTL_REG);
113 	if (mctrl & TIOCM_LOOP)
114 		val |= UART_CTL_LOOPBACK_MASK;
115 	else
116 		val &= ~UART_CTL_LOOPBACK_MASK;
117 	bcm_uart_writel(port, val, UART_CTL_REG);
118 }
119 
120 /*
121  * serial core request to return RI, CTS, DCD and DSR pin state
122  */
123 static unsigned int bcm_uart_get_mctrl(struct uart_port *port)
124 {
125 	unsigned int val, mctrl;
126 
127 	mctrl = 0;
128 	val = bcm_uart_readl(port, UART_EXTINP_REG);
129 	if (val & UART_EXTINP_RI_MASK)
130 		mctrl |= TIOCM_RI;
131 	if (val & UART_EXTINP_CTS_MASK)
132 		mctrl |= TIOCM_CTS;
133 	if (val & UART_EXTINP_DCD_MASK)
134 		mctrl |= TIOCM_CD;
135 	if (val & UART_EXTINP_DSR_MASK)
136 		mctrl |= TIOCM_DSR;
137 	return mctrl;
138 }
139 
140 /*
141  * serial core request to disable tx ASAP (used for flow control)
142  */
143 static void bcm_uart_stop_tx(struct uart_port *port)
144 {
145 	unsigned int val;
146 
147 	val = bcm_uart_readl(port, UART_CTL_REG);
148 	val &= ~(UART_CTL_TXEN_MASK);
149 	bcm_uart_writel(port, val, UART_CTL_REG);
150 
151 	val = bcm_uart_readl(port, UART_IR_REG);
152 	val &= ~UART_TX_INT_MASK;
153 	bcm_uart_writel(port, val, UART_IR_REG);
154 }
155 
156 /*
157  * serial core request to (re)enable tx
158  */
159 static void bcm_uart_start_tx(struct uart_port *port)
160 {
161 	unsigned int val;
162 
163 	val = bcm_uart_readl(port, UART_IR_REG);
164 	val |= UART_TX_INT_MASK;
165 	bcm_uart_writel(port, val, UART_IR_REG);
166 
167 	val = bcm_uart_readl(port, UART_CTL_REG);
168 	val |= UART_CTL_TXEN_MASK;
169 	bcm_uart_writel(port, val, UART_CTL_REG);
170 }
171 
172 /*
173  * serial core request to stop rx, called before port shutdown
174  */
175 static void bcm_uart_stop_rx(struct uart_port *port)
176 {
177 	unsigned int val;
178 
179 	val = bcm_uart_readl(port, UART_IR_REG);
180 	val &= ~UART_RX_INT_MASK;
181 	bcm_uart_writel(port, val, UART_IR_REG);
182 }
183 
184 /*
185  * serial core request to enable modem status interrupt reporting
186  */
187 static void bcm_uart_enable_ms(struct uart_port *port)
188 {
189 	unsigned int val;
190 
191 	val = bcm_uart_readl(port, UART_IR_REG);
192 	val |= UART_IR_MASK(UART_IR_EXTIP);
193 	bcm_uart_writel(port, val, UART_IR_REG);
194 }
195 
196 /*
197  * serial core request to start/stop emitting break char
198  */
199 static void bcm_uart_break_ctl(struct uart_port *port, int ctl)
200 {
201 	unsigned long flags;
202 	unsigned int val;
203 
204 	spin_lock_irqsave(&port->lock, flags);
205 
206 	val = bcm_uart_readl(port, UART_CTL_REG);
207 	if (ctl)
208 		val |= UART_CTL_XMITBRK_MASK;
209 	else
210 		val &= ~UART_CTL_XMITBRK_MASK;
211 	bcm_uart_writel(port, val, UART_CTL_REG);
212 
213 	spin_unlock_irqrestore(&port->lock, flags);
214 }
215 
216 /*
217  * return port type in string format
218  */
219 static const char *bcm_uart_type(struct uart_port *port)
220 {
221 	return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL;
222 }
223 
224 /*
225  * read all chars in rx fifo and send them to core
226  */
227 static void bcm_uart_do_rx(struct uart_port *port)
228 {
229 	struct tty_port *tty_port = &port->state->port;
230 	unsigned int max_count;
231 
232 	/* limit number of char read in interrupt, should not be
233 	 * higher than fifo size anyway since we're much faster than
234 	 * serial port */
235 	max_count = 32;
236 	do {
237 		unsigned int iestat, c, cstat;
238 		char flag;
239 
240 		/* get overrun/fifo empty information from ier
241 		 * register */
242 		iestat = bcm_uart_readl(port, UART_IR_REG);
243 
244 		if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) {
245 			unsigned int val;
246 
247 			/* fifo reset is required to clear
248 			 * interrupt */
249 			val = bcm_uart_readl(port, UART_CTL_REG);
250 			val |= UART_CTL_RSTRXFIFO_MASK;
251 			bcm_uart_writel(port, val, UART_CTL_REG);
252 
253 			port->icount.overrun++;
254 			tty_insert_flip_char(tty_port, 0, TTY_OVERRUN);
255 		}
256 
257 		if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
258 			break;
259 
260 		cstat = c = bcm_uart_readl(port, UART_FIFO_REG);
261 		port->icount.rx++;
262 		flag = TTY_NORMAL;
263 		c &= 0xff;
264 
265 		if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) {
266 			/* do stats first */
267 			if (cstat & UART_FIFO_BRKDET_MASK) {
268 				port->icount.brk++;
269 				if (uart_handle_break(port))
270 					continue;
271 			}
272 
273 			if (cstat & UART_FIFO_PARERR_MASK)
274 				port->icount.parity++;
275 			if (cstat & UART_FIFO_FRAMEERR_MASK)
276 				port->icount.frame++;
277 
278 			/* update flag wrt read_status_mask */
279 			cstat &= port->read_status_mask;
280 			if (cstat & UART_FIFO_BRKDET_MASK)
281 				flag = TTY_BREAK;
282 			if (cstat & UART_FIFO_FRAMEERR_MASK)
283 				flag = TTY_FRAME;
284 			if (cstat & UART_FIFO_PARERR_MASK)
285 				flag = TTY_PARITY;
286 		}
287 
288 		if (uart_handle_sysrq_char(port, c))
289 			continue;
290 
291 
292 		if ((cstat & port->ignore_status_mask) == 0)
293 			tty_insert_flip_char(tty_port, c, flag);
294 
295 	} while (--max_count);
296 
297 	tty_flip_buffer_push(tty_port);
298 }
299 
300 /*
301  * fill tx fifo with chars to send, stop when fifo is about to be full
302  * or when all chars have been sent.
303  */
304 static void bcm_uart_do_tx(struct uart_port *port)
305 {
306 	unsigned int val;
307 	bool pending;
308 	u8 ch;
309 
310 	val = bcm_uart_readl(port, UART_MCTL_REG);
311 	val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
312 	pending = uart_port_tx_limited_flags(port, ch, UART_TX_NOSTOP,
313 		port->fifosize - val,
314 		true,
315 		bcm_uart_writel(port, ch, UART_FIFO_REG),
316 		({}));
317 	if (pending)
318 		return;
319 
320 	/* nothing to send, disable transmit interrupt */
321 	val = bcm_uart_readl(port, UART_IR_REG);
322 	val &= ~UART_TX_INT_MASK;
323 	bcm_uart_writel(port, val, UART_IR_REG);
324 
325 	if (uart_tx_stopped(port))
326 		bcm_uart_stop_tx(port);
327 }
328 
329 /*
330  * process uart interrupt
331  */
332 static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id)
333 {
334 	struct uart_port *port;
335 	unsigned int irqstat;
336 
337 	port = dev_id;
338 	spin_lock(&port->lock);
339 
340 	irqstat = bcm_uart_readl(port, UART_IR_REG);
341 	if (irqstat & UART_RX_INT_STAT)
342 		bcm_uart_do_rx(port);
343 
344 	if (irqstat & UART_TX_INT_STAT)
345 		bcm_uart_do_tx(port);
346 
347 	if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) {
348 		unsigned int estat;
349 
350 		estat = bcm_uart_readl(port, UART_EXTINP_REG);
351 		if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS))
352 			uart_handle_cts_change(port,
353 					       estat & UART_EXTINP_CTS_MASK);
354 		if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD))
355 			uart_handle_dcd_change(port,
356 					       estat & UART_EXTINP_DCD_MASK);
357 	}
358 
359 	spin_unlock(&port->lock);
360 	return IRQ_HANDLED;
361 }
362 
363 /*
364  * enable rx & tx operation on uart
365  */
366 static void bcm_uart_enable(struct uart_port *port)
367 {
368 	unsigned int val;
369 
370 	val = bcm_uart_readl(port, UART_CTL_REG);
371 	val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
372 	bcm_uart_writel(port, val, UART_CTL_REG);
373 }
374 
375 /*
376  * disable rx & tx operation on uart
377  */
378 static void bcm_uart_disable(struct uart_port *port)
379 {
380 	unsigned int val;
381 
382 	val = bcm_uart_readl(port, UART_CTL_REG);
383 	val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
384 		 UART_CTL_RXEN_MASK);
385 	bcm_uart_writel(port, val, UART_CTL_REG);
386 }
387 
388 /*
389  * clear all unread data in rx fifo and unsent data in tx fifo
390  */
391 static void bcm_uart_flush(struct uart_port *port)
392 {
393 	unsigned int val;
394 
395 	/* empty rx and tx fifo */
396 	val = bcm_uart_readl(port, UART_CTL_REG);
397 	val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
398 	bcm_uart_writel(port, val, UART_CTL_REG);
399 
400 	/* read any pending char to make sure all irq status are
401 	 * cleared */
402 	(void)bcm_uart_readl(port, UART_FIFO_REG);
403 }
404 
405 /*
406  * serial core request to initialize uart and start rx operation
407  */
408 static int bcm_uart_startup(struct uart_port *port)
409 {
410 	unsigned int val;
411 	int ret;
412 
413 	/* mask all irq and flush port */
414 	bcm_uart_disable(port);
415 	bcm_uart_writel(port, 0, UART_IR_REG);
416 	bcm_uart_flush(port);
417 
418 	/* clear any pending external input interrupt */
419 	(void)bcm_uart_readl(port, UART_EXTINP_REG);
420 
421 	/* set rx/tx fifo thresh to fifo half size */
422 	val = bcm_uart_readl(port, UART_MCTL_REG);
423 	val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK);
424 	val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT;
425 	val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT;
426 	bcm_uart_writel(port, val, UART_MCTL_REG);
427 
428 	/* set rx fifo timeout to 1 char time */
429 	val = bcm_uart_readl(port, UART_CTL_REG);
430 	val &= ~UART_CTL_RXTMOUTCNT_MASK;
431 	val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT;
432 	bcm_uart_writel(port, val, UART_CTL_REG);
433 
434 	/* report any edge on dcd and cts */
435 	val = UART_EXTINP_INT_MASK;
436 	val |= UART_EXTINP_DCD_NOSENSE_MASK;
437 	val |= UART_EXTINP_CTS_NOSENSE_MASK;
438 	bcm_uart_writel(port, val, UART_EXTINP_REG);
439 
440 	/* register irq and enable rx interrupts */
441 	ret = request_irq(port->irq, bcm_uart_interrupt, 0,
442 			  dev_name(port->dev), port);
443 	if (ret)
444 		return ret;
445 	bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG);
446 	bcm_uart_enable(port);
447 	return 0;
448 }
449 
450 /*
451  * serial core request to flush & disable uart
452  */
453 static void bcm_uart_shutdown(struct uart_port *port)
454 {
455 	unsigned long flags;
456 
457 	spin_lock_irqsave(&port->lock, flags);
458 	bcm_uart_writel(port, 0, UART_IR_REG);
459 	spin_unlock_irqrestore(&port->lock, flags);
460 
461 	bcm_uart_disable(port);
462 	bcm_uart_flush(port);
463 	free_irq(port->irq, port);
464 }
465 
466 /*
467  * serial core request to change current uart setting
468  */
469 static void bcm_uart_set_termios(struct uart_port *port, struct ktermios *new,
470 				 const struct ktermios *old)
471 {
472 	unsigned int ctl, baud, quot, ier;
473 	unsigned long flags;
474 	int tries;
475 
476 	spin_lock_irqsave(&port->lock, flags);
477 
478 	/* Drain the hot tub fully before we power it off for the winter. */
479 	for (tries = 3; !bcm_uart_tx_empty(port) && tries; tries--)
480 		mdelay(10);
481 
482 	/* disable uart while changing speed */
483 	bcm_uart_disable(port);
484 	bcm_uart_flush(port);
485 
486 	/* update Control register */
487 	ctl = bcm_uart_readl(port, UART_CTL_REG);
488 	ctl &= ~UART_CTL_BITSPERSYM_MASK;
489 
490 	switch (new->c_cflag & CSIZE) {
491 	case CS5:
492 		ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT);
493 		break;
494 	case CS6:
495 		ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT);
496 		break;
497 	case CS7:
498 		ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT);
499 		break;
500 	default:
501 		ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT);
502 		break;
503 	}
504 
505 	ctl &= ~UART_CTL_STOPBITS_MASK;
506 	if (new->c_cflag & CSTOPB)
507 		ctl |= UART_CTL_STOPBITS_2;
508 	else
509 		ctl |= UART_CTL_STOPBITS_1;
510 
511 	ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
512 	if (new->c_cflag & PARENB)
513 		ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
514 	ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
515 	if (new->c_cflag & PARODD)
516 		ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
517 	bcm_uart_writel(port, ctl, UART_CTL_REG);
518 
519 	/* update Baudword register */
520 	baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
521 	quot = uart_get_divisor(port, baud) - 1;
522 	bcm_uart_writel(port, quot, UART_BAUD_REG);
523 
524 	/* update Interrupt register */
525 	ier = bcm_uart_readl(port, UART_IR_REG);
526 
527 	ier &= ~UART_IR_MASK(UART_IR_EXTIP);
528 	if (UART_ENABLE_MS(port, new->c_cflag))
529 		ier |= UART_IR_MASK(UART_IR_EXTIP);
530 
531 	bcm_uart_writel(port, ier, UART_IR_REG);
532 
533 	/* update read/ignore mask */
534 	port->read_status_mask = UART_FIFO_VALID_MASK;
535 	if (new->c_iflag & INPCK) {
536 		port->read_status_mask |= UART_FIFO_FRAMEERR_MASK;
537 		port->read_status_mask |= UART_FIFO_PARERR_MASK;
538 	}
539 	if (new->c_iflag & (IGNBRK | BRKINT))
540 		port->read_status_mask |= UART_FIFO_BRKDET_MASK;
541 
542 	port->ignore_status_mask = 0;
543 	if (new->c_iflag & IGNPAR)
544 		port->ignore_status_mask |= UART_FIFO_PARERR_MASK;
545 	if (new->c_iflag & IGNBRK)
546 		port->ignore_status_mask |= UART_FIFO_BRKDET_MASK;
547 	if (!(new->c_cflag & CREAD))
548 		port->ignore_status_mask |= UART_FIFO_VALID_MASK;
549 
550 	uart_update_timeout(port, new->c_cflag, baud);
551 	bcm_uart_enable(port);
552 	spin_unlock_irqrestore(&port->lock, flags);
553 }
554 
555 /*
556  * serial core request to claim uart iomem
557  */
558 static int bcm_uart_request_port(struct uart_port *port)
559 {
560 	/* UARTs always present */
561 	return 0;
562 }
563 
564 /*
565  * serial core request to release uart iomem
566  */
567 static void bcm_uart_release_port(struct uart_port *port)
568 {
569 	/* Nothing to release ... */
570 }
571 
572 /*
573  * serial core request to do any port required autoconfiguration
574  */
575 static void bcm_uart_config_port(struct uart_port *port, int flags)
576 {
577 	if (flags & UART_CONFIG_TYPE) {
578 		if (bcm_uart_request_port(port))
579 			return;
580 		port->type = PORT_BCM63XX;
581 	}
582 }
583 
584 /*
585  * serial core request to check that port information in serinfo are
586  * suitable
587  */
588 static int bcm_uart_verify_port(struct uart_port *port,
589 				struct serial_struct *serinfo)
590 {
591 	if (port->type != PORT_BCM63XX)
592 		return -EINVAL;
593 	if (port->irq != serinfo->irq)
594 		return -EINVAL;
595 	if (port->iotype != serinfo->io_type)
596 		return -EINVAL;
597 	if (port->mapbase != (unsigned long)serinfo->iomem_base)
598 		return -EINVAL;
599 	return 0;
600 }
601 
602 #ifdef CONFIG_CONSOLE_POLL
603 /*
604  * return true when outstanding tx equals fifo size
605  */
606 static bool bcm_uart_tx_full(struct uart_port *port)
607 {
608 	unsigned int val;
609 
610 	val = bcm_uart_readl(port, UART_MCTL_REG);
611 	val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
612 	return !(port->fifosize - val);
613 }
614 
615 static int bcm_uart_poll_get_char(struct uart_port *port)
616 {
617 	unsigned int iestat;
618 
619 	iestat = bcm_uart_readl(port, UART_IR_REG);
620 	if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
621 		return NO_POLL_CHAR;
622 
623 	return bcm_uart_readl(port, UART_FIFO_REG);
624 }
625 
626 static void bcm_uart_poll_put_char(struct uart_port *port, unsigned char c)
627 {
628 	while (bcm_uart_tx_full(port)) {
629 		cpu_relax();
630 	}
631 
632 	bcm_uart_writel(port, c, UART_FIFO_REG);
633 }
634 #endif
635 
636 /* serial core callbacks */
637 static const struct uart_ops bcm_uart_ops = {
638 	.tx_empty	= bcm_uart_tx_empty,
639 	.get_mctrl	= bcm_uart_get_mctrl,
640 	.set_mctrl	= bcm_uart_set_mctrl,
641 	.start_tx	= bcm_uart_start_tx,
642 	.stop_tx	= bcm_uart_stop_tx,
643 	.stop_rx	= bcm_uart_stop_rx,
644 	.enable_ms	= bcm_uart_enable_ms,
645 	.break_ctl	= bcm_uart_break_ctl,
646 	.startup	= bcm_uart_startup,
647 	.shutdown	= bcm_uart_shutdown,
648 	.set_termios	= bcm_uart_set_termios,
649 	.type		= bcm_uart_type,
650 	.release_port	= bcm_uart_release_port,
651 	.request_port	= bcm_uart_request_port,
652 	.config_port	= bcm_uart_config_port,
653 	.verify_port	= bcm_uart_verify_port,
654 #ifdef CONFIG_CONSOLE_POLL
655 	.poll_get_char  = bcm_uart_poll_get_char,
656 	.poll_put_char  = bcm_uart_poll_put_char,
657 #endif
658 };
659 
660 
661 
662 #ifdef CONFIG_SERIAL_BCM63XX_CONSOLE
663 static void wait_for_xmitr(struct uart_port *port)
664 {
665 	unsigned int tmout;
666 
667 	/* Wait up to 10ms for the character(s) to be sent. */
668 	tmout = 10000;
669 	while (--tmout) {
670 		unsigned int val;
671 
672 		val = bcm_uart_readl(port, UART_IR_REG);
673 		if (val & UART_IR_STAT(UART_IR_TXEMPTY))
674 			break;
675 		udelay(1);
676 	}
677 
678 	/* Wait up to 1s for flow control if necessary */
679 	if (port->flags & UPF_CONS_FLOW) {
680 		tmout = 1000000;
681 		while (--tmout) {
682 			unsigned int val;
683 
684 			val = bcm_uart_readl(port, UART_EXTINP_REG);
685 			if (val & UART_EXTINP_CTS_MASK)
686 				break;
687 			udelay(1);
688 		}
689 	}
690 }
691 
692 /*
693  * output given char
694  */
695 static void bcm_console_putchar(struct uart_port *port, unsigned char ch)
696 {
697 	wait_for_xmitr(port);
698 	bcm_uart_writel(port, ch, UART_FIFO_REG);
699 }
700 
701 /*
702  * console core request to output given string
703  */
704 static void bcm_console_write(struct console *co, const char *s,
705 			      unsigned int count)
706 {
707 	struct uart_port *port;
708 	unsigned long flags;
709 	int locked;
710 
711 	port = &ports[co->index];
712 
713 	local_irq_save(flags);
714 	if (port->sysrq) {
715 		/* bcm_uart_interrupt() already took the lock */
716 		locked = 0;
717 	} else if (oops_in_progress) {
718 		locked = spin_trylock(&port->lock);
719 	} else {
720 		spin_lock(&port->lock);
721 		locked = 1;
722 	}
723 
724 	/* call helper to deal with \r\n */
725 	uart_console_write(port, s, count, bcm_console_putchar);
726 
727 	/* and wait for char to be transmitted */
728 	wait_for_xmitr(port);
729 
730 	if (locked)
731 		spin_unlock(&port->lock);
732 	local_irq_restore(flags);
733 }
734 
735 /*
736  * console core request to setup given console, find matching uart
737  * port and setup it.
738  */
739 static int bcm_console_setup(struct console *co, char *options)
740 {
741 	struct uart_port *port;
742 	int baud = 9600;
743 	int bits = 8;
744 	int parity = 'n';
745 	int flow = 'n';
746 
747 	if (co->index < 0 || co->index >= BCM63XX_NR_UARTS)
748 		return -EINVAL;
749 	port = &ports[co->index];
750 	if (!port->membase)
751 		return -ENODEV;
752 	if (options)
753 		uart_parse_options(options, &baud, &parity, &bits, &flow);
754 
755 	return uart_set_options(port, co, baud, parity, bits, flow);
756 }
757 
758 static struct uart_driver bcm_uart_driver;
759 
760 static struct console bcm63xx_console = {
761 	.name		= "ttyS",
762 	.write		= bcm_console_write,
763 	.device		= uart_console_device,
764 	.setup		= bcm_console_setup,
765 	.flags		= CON_PRINTBUFFER,
766 	.index		= -1,
767 	.data		= &bcm_uart_driver,
768 };
769 
770 static int __init bcm63xx_console_init(void)
771 {
772 	register_console(&bcm63xx_console);
773 	return 0;
774 }
775 
776 console_initcall(bcm63xx_console_init);
777 
778 static void bcm_early_write(struct console *con, const char *s, unsigned n)
779 {
780 	struct earlycon_device *dev = con->data;
781 
782 	uart_console_write(&dev->port, s, n, bcm_console_putchar);
783 	wait_for_xmitr(&dev->port);
784 }
785 
786 static int __init bcm_early_console_setup(struct earlycon_device *device,
787 					  const char *opt)
788 {
789 	if (!device->port.membase)
790 		return -ENODEV;
791 
792 	device->con->write = bcm_early_write;
793 	return 0;
794 }
795 
796 OF_EARLYCON_DECLARE(bcm63xx_uart, "brcm,bcm6345-uart", bcm_early_console_setup);
797 
798 #define BCM63XX_CONSOLE	(&bcm63xx_console)
799 #else
800 #define BCM63XX_CONSOLE	NULL
801 #endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */
802 
803 static struct uart_driver bcm_uart_driver = {
804 	.owner		= THIS_MODULE,
805 	.driver_name	= "bcm63xx_uart",
806 	.dev_name	= "ttyS",
807 	.major		= TTY_MAJOR,
808 	.minor		= 64,
809 	.nr		= BCM63XX_NR_UARTS,
810 	.cons		= BCM63XX_CONSOLE,
811 };
812 
813 /*
814  * platform driver probe/remove callback
815  */
816 static int bcm_uart_probe(struct platform_device *pdev)
817 {
818 	struct resource *res_mem;
819 	struct uart_port *port;
820 	struct clk *clk;
821 	int ret;
822 
823 	if (pdev->dev.of_node) {
824 		pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
825 
826 		if (pdev->id < 0)
827 			pdev->id = of_alias_get_id(pdev->dev.of_node, "uart");
828 	}
829 
830 	if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS)
831 		return -EINVAL;
832 
833 	port = &ports[pdev->id];
834 	if (port->membase)
835 		return -EBUSY;
836 	memset(port, 0, sizeof(*port));
837 
838 	port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res_mem);
839 	if (IS_ERR(port->membase))
840 		return PTR_ERR(port->membase);
841 	port->mapbase = res_mem->start;
842 
843 	ret = platform_get_irq(pdev, 0);
844 	if (ret < 0)
845 		return ret;
846 	port->irq = ret;
847 
848 	clk = clk_get(&pdev->dev, "refclk");
849 	if (IS_ERR(clk) && pdev->dev.of_node)
850 		clk = of_clk_get(pdev->dev.of_node, 0);
851 
852 	if (IS_ERR(clk))
853 		return -ENODEV;
854 
855 	port->iotype = UPIO_MEM;
856 	port->ops = &bcm_uart_ops;
857 	port->flags = UPF_BOOT_AUTOCONF;
858 	port->dev = &pdev->dev;
859 	port->fifosize = 16;
860 	port->uartclk = clk_get_rate(clk) / 2;
861 	port->line = pdev->id;
862 	port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_BCM63XX_CONSOLE);
863 	clk_put(clk);
864 
865 	ret = uart_add_one_port(&bcm_uart_driver, port);
866 	if (ret) {
867 		ports[pdev->id].membase = NULL;
868 		return ret;
869 	}
870 	platform_set_drvdata(pdev, port);
871 	return 0;
872 }
873 
874 static int bcm_uart_remove(struct platform_device *pdev)
875 {
876 	struct uart_port *port;
877 
878 	port = platform_get_drvdata(pdev);
879 	uart_remove_one_port(&bcm_uart_driver, port);
880 	/* mark port as free */
881 	ports[pdev->id].membase = NULL;
882 	return 0;
883 }
884 
885 static const struct of_device_id bcm63xx_of_match[] = {
886 	{ .compatible = "brcm,bcm6345-uart" },
887 	{ /* sentinel */ }
888 };
889 MODULE_DEVICE_TABLE(of, bcm63xx_of_match);
890 
891 /*
892  * platform driver stuff
893  */
894 static struct platform_driver bcm_uart_platform_driver = {
895 	.probe	= bcm_uart_probe,
896 	.remove	= bcm_uart_remove,
897 	.driver	= {
898 		.name  = "bcm63xx_uart",
899 		.of_match_table = bcm63xx_of_match,
900 	},
901 };
902 
903 static int __init bcm_uart_init(void)
904 {
905 	int ret;
906 
907 	ret = uart_register_driver(&bcm_uart_driver);
908 	if (ret)
909 		return ret;
910 
911 	ret = platform_driver_register(&bcm_uart_platform_driver);
912 	if (ret)
913 		uart_unregister_driver(&bcm_uart_driver);
914 
915 	return ret;
916 }
917 
918 static void __exit bcm_uart_exit(void)
919 {
920 	platform_driver_unregister(&bcm_uart_platform_driver);
921 	uart_unregister_driver(&bcm_uart_driver);
922 }
923 
924 module_init(bcm_uart_init);
925 module_exit(bcm_uart_exit);
926 
927 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
928 MODULE_DESCRIPTION("Broadcom 63xx integrated uart driver");
929 MODULE_LICENSE("GPL");
930