1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Derived from many drivers using generic_serial interface. 7 * 8 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 9 * 10 * Serial driver for BCM63xx integrated UART. 11 * 12 * Hardware flow control was _not_ tested since I only have RX/TX on 13 * my board. 14 */ 15 16 #if defined(CONFIG_SERIAL_BCM63XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 17 #define SUPPORT_SYSRQ 18 #endif 19 20 #include <linux/kernel.h> 21 #include <linux/platform_device.h> 22 #include <linux/init.h> 23 #include <linux/delay.h> 24 #include <linux/module.h> 25 #include <linux/console.h> 26 #include <linux/clk.h> 27 #include <linux/tty.h> 28 #include <linux/tty_flip.h> 29 #include <linux/sysrq.h> 30 #include <linux/serial.h> 31 #include <linux/serial_core.h> 32 33 #include <bcm63xx_irq.h> 34 #include <bcm63xx_regs.h> 35 #include <bcm63xx_io.h> 36 37 #define BCM63XX_NR_UARTS 2 38 39 static struct uart_port ports[BCM63XX_NR_UARTS]; 40 41 /* 42 * rx interrupt mask / stat 43 * 44 * mask: 45 * - rx fifo full 46 * - rx fifo above threshold 47 * - rx fifo not empty for too long 48 */ 49 #define UART_RX_INT_MASK (UART_IR_MASK(UART_IR_RXOVER) | \ 50 UART_IR_MASK(UART_IR_RXTHRESH) | \ 51 UART_IR_MASK(UART_IR_RXTIMEOUT)) 52 53 #define UART_RX_INT_STAT (UART_IR_STAT(UART_IR_RXOVER) | \ 54 UART_IR_STAT(UART_IR_RXTHRESH) | \ 55 UART_IR_STAT(UART_IR_RXTIMEOUT)) 56 57 /* 58 * tx interrupt mask / stat 59 * 60 * mask: 61 * - tx fifo empty 62 * - tx fifo below threshold 63 */ 64 #define UART_TX_INT_MASK (UART_IR_MASK(UART_IR_TXEMPTY) | \ 65 UART_IR_MASK(UART_IR_TXTRESH)) 66 67 #define UART_TX_INT_STAT (UART_IR_STAT(UART_IR_TXEMPTY) | \ 68 UART_IR_STAT(UART_IR_TXTRESH)) 69 70 /* 71 * external input interrupt 72 * 73 * mask: any edge on CTS, DCD 74 */ 75 #define UART_EXTINP_INT_MASK (UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \ 76 UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD)) 77 78 /* 79 * handy uart register accessor 80 */ 81 static inline unsigned int bcm_uart_readl(struct uart_port *port, 82 unsigned int offset) 83 { 84 return bcm_readl(port->membase + offset); 85 } 86 87 static inline void bcm_uart_writel(struct uart_port *port, 88 unsigned int value, unsigned int offset) 89 { 90 bcm_writel(value, port->membase + offset); 91 } 92 93 /* 94 * serial core request to check if uart tx fifo is empty 95 */ 96 static unsigned int bcm_uart_tx_empty(struct uart_port *port) 97 { 98 unsigned int val; 99 100 val = bcm_uart_readl(port, UART_IR_REG); 101 return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0; 102 } 103 104 /* 105 * serial core request to set RTS and DTR pin state and loopback mode 106 */ 107 static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 108 { 109 unsigned int val; 110 111 val = bcm_uart_readl(port, UART_MCTL_REG); 112 val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK); 113 /* invert of written value is reflected on the pin */ 114 if (!(mctrl & TIOCM_DTR)) 115 val |= UART_MCTL_DTR_MASK; 116 if (!(mctrl & TIOCM_RTS)) 117 val |= UART_MCTL_RTS_MASK; 118 bcm_uart_writel(port, val, UART_MCTL_REG); 119 120 val = bcm_uart_readl(port, UART_CTL_REG); 121 if (mctrl & TIOCM_LOOP) 122 val |= UART_CTL_LOOPBACK_MASK; 123 else 124 val &= ~UART_CTL_LOOPBACK_MASK; 125 bcm_uart_writel(port, val, UART_CTL_REG); 126 } 127 128 /* 129 * serial core request to return RI, CTS, DCD and DSR pin state 130 */ 131 static unsigned int bcm_uart_get_mctrl(struct uart_port *port) 132 { 133 unsigned int val, mctrl; 134 135 mctrl = 0; 136 val = bcm_uart_readl(port, UART_EXTINP_REG); 137 if (val & UART_EXTINP_RI_MASK) 138 mctrl |= TIOCM_RI; 139 if (val & UART_EXTINP_CTS_MASK) 140 mctrl |= TIOCM_CTS; 141 if (val & UART_EXTINP_DCD_MASK) 142 mctrl |= TIOCM_CD; 143 if (val & UART_EXTINP_DSR_MASK) 144 mctrl |= TIOCM_DSR; 145 return mctrl; 146 } 147 148 /* 149 * serial core request to disable tx ASAP (used for flow control) 150 */ 151 static void bcm_uart_stop_tx(struct uart_port *port) 152 { 153 unsigned int val; 154 155 val = bcm_uart_readl(port, UART_CTL_REG); 156 val &= ~(UART_CTL_TXEN_MASK); 157 bcm_uart_writel(port, val, UART_CTL_REG); 158 159 val = bcm_uart_readl(port, UART_IR_REG); 160 val &= ~UART_TX_INT_MASK; 161 bcm_uart_writel(port, val, UART_IR_REG); 162 } 163 164 /* 165 * serial core request to (re)enable tx 166 */ 167 static void bcm_uart_start_tx(struct uart_port *port) 168 { 169 unsigned int val; 170 171 val = bcm_uart_readl(port, UART_IR_REG); 172 val |= UART_TX_INT_MASK; 173 bcm_uart_writel(port, val, UART_IR_REG); 174 175 val = bcm_uart_readl(port, UART_CTL_REG); 176 val |= UART_CTL_TXEN_MASK; 177 bcm_uart_writel(port, val, UART_CTL_REG); 178 } 179 180 /* 181 * serial core request to stop rx, called before port shutdown 182 */ 183 static void bcm_uart_stop_rx(struct uart_port *port) 184 { 185 unsigned int val; 186 187 val = bcm_uart_readl(port, UART_IR_REG); 188 val &= ~UART_RX_INT_MASK; 189 bcm_uart_writel(port, val, UART_IR_REG); 190 } 191 192 /* 193 * serial core request to enable modem status interrupt reporting 194 */ 195 static void bcm_uart_enable_ms(struct uart_port *port) 196 { 197 unsigned int val; 198 199 val = bcm_uart_readl(port, UART_IR_REG); 200 val |= UART_IR_MASK(UART_IR_EXTIP); 201 bcm_uart_writel(port, val, UART_IR_REG); 202 } 203 204 /* 205 * serial core request to start/stop emitting break char 206 */ 207 static void bcm_uart_break_ctl(struct uart_port *port, int ctl) 208 { 209 unsigned long flags; 210 unsigned int val; 211 212 spin_lock_irqsave(&port->lock, flags); 213 214 val = bcm_uart_readl(port, UART_CTL_REG); 215 if (ctl) 216 val |= UART_CTL_XMITBRK_MASK; 217 else 218 val &= ~UART_CTL_XMITBRK_MASK; 219 bcm_uart_writel(port, val, UART_CTL_REG); 220 221 spin_unlock_irqrestore(&port->lock, flags); 222 } 223 224 /* 225 * return port type in string format 226 */ 227 static const char *bcm_uart_type(struct uart_port *port) 228 { 229 return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL; 230 } 231 232 /* 233 * read all chars in rx fifo and send them to core 234 */ 235 static void bcm_uart_do_rx(struct uart_port *port) 236 { 237 struct tty_port *tty_port = &port->state->port; 238 unsigned int max_count; 239 240 /* limit number of char read in interrupt, should not be 241 * higher than fifo size anyway since we're much faster than 242 * serial port */ 243 max_count = 32; 244 do { 245 unsigned int iestat, c, cstat; 246 char flag; 247 248 /* get overrun/fifo empty information from ier 249 * register */ 250 iestat = bcm_uart_readl(port, UART_IR_REG); 251 252 if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) { 253 unsigned int val; 254 255 /* fifo reset is required to clear 256 * interrupt */ 257 val = bcm_uart_readl(port, UART_CTL_REG); 258 val |= UART_CTL_RSTRXFIFO_MASK; 259 bcm_uart_writel(port, val, UART_CTL_REG); 260 261 port->icount.overrun++; 262 tty_insert_flip_char(tty_port, 0, TTY_OVERRUN); 263 } 264 265 if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY))) 266 break; 267 268 cstat = c = bcm_uart_readl(port, UART_FIFO_REG); 269 port->icount.rx++; 270 flag = TTY_NORMAL; 271 c &= 0xff; 272 273 if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) { 274 /* do stats first */ 275 if (cstat & UART_FIFO_BRKDET_MASK) { 276 port->icount.brk++; 277 if (uart_handle_break(port)) 278 continue; 279 } 280 281 if (cstat & UART_FIFO_PARERR_MASK) 282 port->icount.parity++; 283 if (cstat & UART_FIFO_FRAMEERR_MASK) 284 port->icount.frame++; 285 286 /* update flag wrt read_status_mask */ 287 cstat &= port->read_status_mask; 288 if (cstat & UART_FIFO_BRKDET_MASK) 289 flag = TTY_BREAK; 290 if (cstat & UART_FIFO_FRAMEERR_MASK) 291 flag = TTY_FRAME; 292 if (cstat & UART_FIFO_PARERR_MASK) 293 flag = TTY_PARITY; 294 } 295 296 if (uart_handle_sysrq_char(port, c)) 297 continue; 298 299 300 if ((cstat & port->ignore_status_mask) == 0) 301 tty_insert_flip_char(tty_port, c, flag); 302 303 } while (--max_count); 304 305 tty_flip_buffer_push(tty_port); 306 } 307 308 /* 309 * fill tx fifo with chars to send, stop when fifo is about to be full 310 * or when all chars have been sent. 311 */ 312 static void bcm_uart_do_tx(struct uart_port *port) 313 { 314 struct circ_buf *xmit; 315 unsigned int val, max_count; 316 317 if (port->x_char) { 318 bcm_uart_writel(port, port->x_char, UART_FIFO_REG); 319 port->icount.tx++; 320 port->x_char = 0; 321 return; 322 } 323 324 if (uart_tx_stopped(port)) { 325 bcm_uart_stop_tx(port); 326 return; 327 } 328 329 xmit = &port->state->xmit; 330 if (uart_circ_empty(xmit)) 331 goto txq_empty; 332 333 val = bcm_uart_readl(port, UART_MCTL_REG); 334 val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT; 335 max_count = port->fifosize - val; 336 337 while (max_count--) { 338 unsigned int c; 339 340 c = xmit->buf[xmit->tail]; 341 bcm_uart_writel(port, c, UART_FIFO_REG); 342 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 343 port->icount.tx++; 344 if (uart_circ_empty(xmit)) 345 break; 346 } 347 348 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 349 uart_write_wakeup(port); 350 351 if (uart_circ_empty(xmit)) 352 goto txq_empty; 353 return; 354 355 txq_empty: 356 /* nothing to send, disable transmit interrupt */ 357 val = bcm_uart_readl(port, UART_IR_REG); 358 val &= ~UART_TX_INT_MASK; 359 bcm_uart_writel(port, val, UART_IR_REG); 360 return; 361 } 362 363 /* 364 * process uart interrupt 365 */ 366 static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id) 367 { 368 struct uart_port *port; 369 unsigned int irqstat; 370 371 port = dev_id; 372 spin_lock(&port->lock); 373 374 irqstat = bcm_uart_readl(port, UART_IR_REG); 375 if (irqstat & UART_RX_INT_STAT) 376 bcm_uart_do_rx(port); 377 378 if (irqstat & UART_TX_INT_STAT) 379 bcm_uart_do_tx(port); 380 381 if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) { 382 unsigned int estat; 383 384 estat = bcm_uart_readl(port, UART_EXTINP_REG); 385 if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS)) 386 uart_handle_cts_change(port, 387 estat & UART_EXTINP_CTS_MASK); 388 if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD)) 389 uart_handle_dcd_change(port, 390 estat & UART_EXTINP_DCD_MASK); 391 } 392 393 spin_unlock(&port->lock); 394 return IRQ_HANDLED; 395 } 396 397 /* 398 * enable rx & tx operation on uart 399 */ 400 static void bcm_uart_enable(struct uart_port *port) 401 { 402 unsigned int val; 403 404 val = bcm_uart_readl(port, UART_CTL_REG); 405 val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK); 406 bcm_uart_writel(port, val, UART_CTL_REG); 407 } 408 409 /* 410 * disable rx & tx operation on uart 411 */ 412 static void bcm_uart_disable(struct uart_port *port) 413 { 414 unsigned int val; 415 416 val = bcm_uart_readl(port, UART_CTL_REG); 417 val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | 418 UART_CTL_RXEN_MASK); 419 bcm_uart_writel(port, val, UART_CTL_REG); 420 } 421 422 /* 423 * clear all unread data in rx fifo and unsent data in tx fifo 424 */ 425 static void bcm_uart_flush(struct uart_port *port) 426 { 427 unsigned int val; 428 429 /* empty rx and tx fifo */ 430 val = bcm_uart_readl(port, UART_CTL_REG); 431 val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK; 432 bcm_uart_writel(port, val, UART_CTL_REG); 433 434 /* read any pending char to make sure all irq status are 435 * cleared */ 436 (void)bcm_uart_readl(port, UART_FIFO_REG); 437 } 438 439 /* 440 * serial core request to initialize uart and start rx operation 441 */ 442 static int bcm_uart_startup(struct uart_port *port) 443 { 444 unsigned int val; 445 int ret; 446 447 /* mask all irq and flush port */ 448 bcm_uart_disable(port); 449 bcm_uart_writel(port, 0, UART_IR_REG); 450 bcm_uart_flush(port); 451 452 /* clear any pending external input interrupt */ 453 (void)bcm_uart_readl(port, UART_EXTINP_REG); 454 455 /* set rx/tx fifo thresh to fifo half size */ 456 val = bcm_uart_readl(port, UART_MCTL_REG); 457 val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK); 458 val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT; 459 val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT; 460 bcm_uart_writel(port, val, UART_MCTL_REG); 461 462 /* set rx fifo timeout to 1 char time */ 463 val = bcm_uart_readl(port, UART_CTL_REG); 464 val &= ~UART_CTL_RXTMOUTCNT_MASK; 465 val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT; 466 bcm_uart_writel(port, val, UART_CTL_REG); 467 468 /* report any edge on dcd and cts */ 469 val = UART_EXTINP_INT_MASK; 470 val |= UART_EXTINP_DCD_NOSENSE_MASK; 471 val |= UART_EXTINP_CTS_NOSENSE_MASK; 472 bcm_uart_writel(port, val, UART_EXTINP_REG); 473 474 /* register irq and enable rx interrupts */ 475 ret = request_irq(port->irq, bcm_uart_interrupt, 0, 476 bcm_uart_type(port), port); 477 if (ret) 478 return ret; 479 bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG); 480 bcm_uart_enable(port); 481 return 0; 482 } 483 484 /* 485 * serial core request to flush & disable uart 486 */ 487 static void bcm_uart_shutdown(struct uart_port *port) 488 { 489 unsigned long flags; 490 491 spin_lock_irqsave(&port->lock, flags); 492 bcm_uart_writel(port, 0, UART_IR_REG); 493 spin_unlock_irqrestore(&port->lock, flags); 494 495 bcm_uart_disable(port); 496 bcm_uart_flush(port); 497 free_irq(port->irq, port); 498 } 499 500 /* 501 * serial core request to change current uart setting 502 */ 503 static void bcm_uart_set_termios(struct uart_port *port, 504 struct ktermios *new, 505 struct ktermios *old) 506 { 507 unsigned int ctl, baud, quot, ier; 508 unsigned long flags; 509 510 spin_lock_irqsave(&port->lock, flags); 511 512 /* disable uart while changing speed */ 513 bcm_uart_disable(port); 514 bcm_uart_flush(port); 515 516 /* update Control register */ 517 ctl = bcm_uart_readl(port, UART_CTL_REG); 518 ctl &= ~UART_CTL_BITSPERSYM_MASK; 519 520 switch (new->c_cflag & CSIZE) { 521 case CS5: 522 ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT); 523 break; 524 case CS6: 525 ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT); 526 break; 527 case CS7: 528 ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT); 529 break; 530 default: 531 ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT); 532 break; 533 } 534 535 ctl &= ~UART_CTL_STOPBITS_MASK; 536 if (new->c_cflag & CSTOPB) 537 ctl |= UART_CTL_STOPBITS_2; 538 else 539 ctl |= UART_CTL_STOPBITS_1; 540 541 ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK); 542 if (new->c_cflag & PARENB) 543 ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK); 544 ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK); 545 if (new->c_cflag & PARODD) 546 ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK); 547 bcm_uart_writel(port, ctl, UART_CTL_REG); 548 549 /* update Baudword register */ 550 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 551 quot = uart_get_divisor(port, baud) - 1; 552 bcm_uart_writel(port, quot, UART_BAUD_REG); 553 554 /* update Interrupt register */ 555 ier = bcm_uart_readl(port, UART_IR_REG); 556 557 ier &= ~UART_IR_MASK(UART_IR_EXTIP); 558 if (UART_ENABLE_MS(port, new->c_cflag)) 559 ier |= UART_IR_MASK(UART_IR_EXTIP); 560 561 bcm_uart_writel(port, ier, UART_IR_REG); 562 563 /* update read/ignore mask */ 564 port->read_status_mask = UART_FIFO_VALID_MASK; 565 if (new->c_iflag & INPCK) { 566 port->read_status_mask |= UART_FIFO_FRAMEERR_MASK; 567 port->read_status_mask |= UART_FIFO_PARERR_MASK; 568 } 569 if (new->c_iflag & (BRKINT)) 570 port->read_status_mask |= UART_FIFO_BRKDET_MASK; 571 572 port->ignore_status_mask = 0; 573 if (new->c_iflag & IGNPAR) 574 port->ignore_status_mask |= UART_FIFO_PARERR_MASK; 575 if (new->c_iflag & IGNBRK) 576 port->ignore_status_mask |= UART_FIFO_BRKDET_MASK; 577 if (!(new->c_cflag & CREAD)) 578 port->ignore_status_mask |= UART_FIFO_VALID_MASK; 579 580 uart_update_timeout(port, new->c_cflag, baud); 581 bcm_uart_enable(port); 582 spin_unlock_irqrestore(&port->lock, flags); 583 } 584 585 /* 586 * serial core request to claim uart iomem 587 */ 588 static int bcm_uart_request_port(struct uart_port *port) 589 { 590 unsigned int size; 591 592 size = RSET_UART_SIZE; 593 if (!request_mem_region(port->mapbase, size, "bcm63xx")) { 594 dev_err(port->dev, "Memory region busy\n"); 595 return -EBUSY; 596 } 597 598 port->membase = ioremap(port->mapbase, size); 599 if (!port->membase) { 600 dev_err(port->dev, "Unable to map registers\n"); 601 release_mem_region(port->mapbase, size); 602 return -EBUSY; 603 } 604 return 0; 605 } 606 607 /* 608 * serial core request to release uart iomem 609 */ 610 static void bcm_uart_release_port(struct uart_port *port) 611 { 612 release_mem_region(port->mapbase, RSET_UART_SIZE); 613 iounmap(port->membase); 614 } 615 616 /* 617 * serial core request to do any port required autoconfiguration 618 */ 619 static void bcm_uart_config_port(struct uart_port *port, int flags) 620 { 621 if (flags & UART_CONFIG_TYPE) { 622 if (bcm_uart_request_port(port)) 623 return; 624 port->type = PORT_BCM63XX; 625 } 626 } 627 628 /* 629 * serial core request to check that port information in serinfo are 630 * suitable 631 */ 632 static int bcm_uart_verify_port(struct uart_port *port, 633 struct serial_struct *serinfo) 634 { 635 if (port->type != PORT_BCM63XX) 636 return -EINVAL; 637 if (port->irq != serinfo->irq) 638 return -EINVAL; 639 if (port->iotype != serinfo->io_type) 640 return -EINVAL; 641 if (port->mapbase != (unsigned long)serinfo->iomem_base) 642 return -EINVAL; 643 return 0; 644 } 645 646 /* serial core callbacks */ 647 static struct uart_ops bcm_uart_ops = { 648 .tx_empty = bcm_uart_tx_empty, 649 .get_mctrl = bcm_uart_get_mctrl, 650 .set_mctrl = bcm_uart_set_mctrl, 651 .start_tx = bcm_uart_start_tx, 652 .stop_tx = bcm_uart_stop_tx, 653 .stop_rx = bcm_uart_stop_rx, 654 .enable_ms = bcm_uart_enable_ms, 655 .break_ctl = bcm_uart_break_ctl, 656 .startup = bcm_uart_startup, 657 .shutdown = bcm_uart_shutdown, 658 .set_termios = bcm_uart_set_termios, 659 .type = bcm_uart_type, 660 .release_port = bcm_uart_release_port, 661 .request_port = bcm_uart_request_port, 662 .config_port = bcm_uart_config_port, 663 .verify_port = bcm_uart_verify_port, 664 }; 665 666 667 668 #ifdef CONFIG_SERIAL_BCM63XX_CONSOLE 669 static inline void wait_for_xmitr(struct uart_port *port) 670 { 671 unsigned int tmout; 672 673 /* Wait up to 10ms for the character(s) to be sent. */ 674 tmout = 10000; 675 while (--tmout) { 676 unsigned int val; 677 678 val = bcm_uart_readl(port, UART_IR_REG); 679 if (val & UART_IR_STAT(UART_IR_TXEMPTY)) 680 break; 681 udelay(1); 682 } 683 684 /* Wait up to 1s for flow control if necessary */ 685 if (port->flags & UPF_CONS_FLOW) { 686 tmout = 1000000; 687 while (--tmout) { 688 unsigned int val; 689 690 val = bcm_uart_readl(port, UART_EXTINP_REG); 691 if (val & UART_EXTINP_CTS_MASK) 692 break; 693 udelay(1); 694 } 695 } 696 } 697 698 /* 699 * output given char 700 */ 701 static void bcm_console_putchar(struct uart_port *port, int ch) 702 { 703 wait_for_xmitr(port); 704 bcm_uart_writel(port, ch, UART_FIFO_REG); 705 } 706 707 /* 708 * console core request to output given string 709 */ 710 static void bcm_console_write(struct console *co, const char *s, 711 unsigned int count) 712 { 713 struct uart_port *port; 714 unsigned long flags; 715 int locked; 716 717 port = &ports[co->index]; 718 719 local_irq_save(flags); 720 if (port->sysrq) { 721 /* bcm_uart_interrupt() already took the lock */ 722 locked = 0; 723 } else if (oops_in_progress) { 724 locked = spin_trylock(&port->lock); 725 } else { 726 spin_lock(&port->lock); 727 locked = 1; 728 } 729 730 /* call helper to deal with \r\n */ 731 uart_console_write(port, s, count, bcm_console_putchar); 732 733 /* and wait for char to be transmitted */ 734 wait_for_xmitr(port); 735 736 if (locked) 737 spin_unlock(&port->lock); 738 local_irq_restore(flags); 739 } 740 741 /* 742 * console core request to setup given console, find matching uart 743 * port and setup it. 744 */ 745 static int bcm_console_setup(struct console *co, char *options) 746 { 747 struct uart_port *port; 748 int baud = 9600; 749 int bits = 8; 750 int parity = 'n'; 751 int flow = 'n'; 752 753 if (co->index < 0 || co->index >= BCM63XX_NR_UARTS) 754 return -EINVAL; 755 port = &ports[co->index]; 756 if (!port->membase) 757 return -ENODEV; 758 if (options) 759 uart_parse_options(options, &baud, &parity, &bits, &flow); 760 761 return uart_set_options(port, co, baud, parity, bits, flow); 762 } 763 764 static struct uart_driver bcm_uart_driver; 765 766 static struct console bcm63xx_console = { 767 .name = "ttyS", 768 .write = bcm_console_write, 769 .device = uart_console_device, 770 .setup = bcm_console_setup, 771 .flags = CON_PRINTBUFFER, 772 .index = -1, 773 .data = &bcm_uart_driver, 774 }; 775 776 static int __init bcm63xx_console_init(void) 777 { 778 register_console(&bcm63xx_console); 779 return 0; 780 } 781 782 console_initcall(bcm63xx_console_init); 783 784 #define BCM63XX_CONSOLE (&bcm63xx_console) 785 #else 786 #define BCM63XX_CONSOLE NULL 787 #endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */ 788 789 static struct uart_driver bcm_uart_driver = { 790 .owner = THIS_MODULE, 791 .driver_name = "bcm63xx_uart", 792 .dev_name = "ttyS", 793 .major = TTY_MAJOR, 794 .minor = 64, 795 .nr = BCM63XX_NR_UARTS, 796 .cons = BCM63XX_CONSOLE, 797 }; 798 799 /* 800 * platform driver probe/remove callback 801 */ 802 static int bcm_uart_probe(struct platform_device *pdev) 803 { 804 struct resource *res_mem, *res_irq; 805 struct uart_port *port; 806 struct clk *clk; 807 int ret; 808 809 if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS) 810 return -EINVAL; 811 812 if (ports[pdev->id].membase) 813 return -EBUSY; 814 815 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 816 if (!res_mem) 817 return -ENODEV; 818 819 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 820 if (!res_irq) 821 return -ENODEV; 822 823 clk = clk_get(&pdev->dev, "periph"); 824 if (IS_ERR(clk)) 825 return -ENODEV; 826 827 port = &ports[pdev->id]; 828 memset(port, 0, sizeof(*port)); 829 port->iotype = UPIO_MEM; 830 port->mapbase = res_mem->start; 831 port->irq = res_irq->start; 832 port->ops = &bcm_uart_ops; 833 port->flags = UPF_BOOT_AUTOCONF; 834 port->dev = &pdev->dev; 835 port->fifosize = 16; 836 port->uartclk = clk_get_rate(clk) / 2; 837 port->line = pdev->id; 838 clk_put(clk); 839 840 ret = uart_add_one_port(&bcm_uart_driver, port); 841 if (ret) { 842 ports[pdev->id].membase = 0; 843 return ret; 844 } 845 platform_set_drvdata(pdev, port); 846 return 0; 847 } 848 849 static int bcm_uart_remove(struct platform_device *pdev) 850 { 851 struct uart_port *port; 852 853 port = platform_get_drvdata(pdev); 854 uart_remove_one_port(&bcm_uart_driver, port); 855 platform_set_drvdata(pdev, NULL); 856 /* mark port as free */ 857 ports[pdev->id].membase = 0; 858 return 0; 859 } 860 861 /* 862 * platform driver stuff 863 */ 864 static struct platform_driver bcm_uart_platform_driver = { 865 .probe = bcm_uart_probe, 866 .remove = bcm_uart_remove, 867 .driver = { 868 .owner = THIS_MODULE, 869 .name = "bcm63xx_uart", 870 }, 871 }; 872 873 static int __init bcm_uart_init(void) 874 { 875 int ret; 876 877 ret = uart_register_driver(&bcm_uart_driver); 878 if (ret) 879 return ret; 880 881 ret = platform_driver_register(&bcm_uart_platform_driver); 882 if (ret) 883 uart_unregister_driver(&bcm_uart_driver); 884 885 return ret; 886 } 887 888 static void __exit bcm_uart_exit(void) 889 { 890 platform_driver_unregister(&bcm_uart_platform_driver); 891 uart_unregister_driver(&bcm_uart_driver); 892 } 893 894 module_init(bcm_uart_init); 895 module_exit(bcm_uart_exit); 896 897 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>"); 898 MODULE_DESCRIPTION("Broadcom 63<xx integrated uart driver"); 899 MODULE_LICENSE("GPL"); 900