1 /* 2 * Driver for Atmel AT91 / AT32 Serial ports 3 * Copyright (C) 2003 Rick Bronson 4 * 5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. 6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 7 * 8 * DMA support added by Chip Coldwell. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 #include <linux/module.h> 26 #include <linux/tty.h> 27 #include <linux/ioport.h> 28 #include <linux/slab.h> 29 #include <linux/init.h> 30 #include <linux/serial.h> 31 #include <linux/clk.h> 32 #include <linux/console.h> 33 #include <linux/sysrq.h> 34 #include <linux/tty_flip.h> 35 #include <linux/platform_device.h> 36 #include <linux/of.h> 37 #include <linux/of_device.h> 38 #include <linux/of_gpio.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/dmaengine.h> 41 #include <linux/atmel_pdc.h> 42 #include <linux/atmel_serial.h> 43 #include <linux/uaccess.h> 44 #include <linux/platform_data/atmel.h> 45 #include <linux/timer.h> 46 #include <linux/gpio.h> 47 #include <linux/gpio/consumer.h> 48 #include <linux/err.h> 49 #include <linux/irq.h> 50 #include <linux/suspend.h> 51 52 #include <asm/io.h> 53 #include <asm/ioctls.h> 54 55 #define PDC_BUFFER_SIZE 512 56 /* Revisit: We should calculate this based on the actual port settings */ 57 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ 58 59 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 60 #define SUPPORT_SYSRQ 61 #endif 62 63 #include <linux/serial_core.h> 64 65 #include "serial_mctrl_gpio.h" 66 67 static void atmel_start_rx(struct uart_port *port); 68 static void atmel_stop_rx(struct uart_port *port); 69 70 #ifdef CONFIG_SERIAL_ATMEL_TTYAT 71 72 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we 73 * should coexist with the 8250 driver, such as if we have an external 16C550 74 * UART. */ 75 #define SERIAL_ATMEL_MAJOR 204 76 #define MINOR_START 154 77 #define ATMEL_DEVICENAME "ttyAT" 78 79 #else 80 81 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port 82 * name, but it is legally reserved for the 8250 driver. */ 83 #define SERIAL_ATMEL_MAJOR TTY_MAJOR 84 #define MINOR_START 64 85 #define ATMEL_DEVICENAME "ttyS" 86 87 #endif 88 89 #define ATMEL_ISR_PASS_LIMIT 256 90 91 /* UART registers. CR is write-only, hence no GET macro */ 92 #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) 93 #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) 94 #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) 95 #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) 96 #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) 97 #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) 98 #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) 99 #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) 100 #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) 101 #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) 102 #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) 103 #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) 104 #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR) 105 #define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME) 106 #define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION) 107 108 /* PDC registers */ 109 #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) 110 #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) 111 112 #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) 113 #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) 114 #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) 115 #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) 116 #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) 117 118 #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) 119 #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) 120 #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR) 121 122 struct atmel_dma_buffer { 123 unsigned char *buf; 124 dma_addr_t dma_addr; 125 unsigned int dma_size; 126 unsigned int ofs; 127 }; 128 129 struct atmel_uart_char { 130 u16 status; 131 u16 ch; 132 }; 133 134 #define ATMEL_SERIAL_RINGSIZE 1024 135 136 /* 137 * We wrap our port structure around the generic uart_port. 138 */ 139 struct atmel_uart_port { 140 struct uart_port uart; /* uart */ 141 struct clk *clk; /* uart clock */ 142 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ 143 u32 backup_imr; /* IMR saved during suspend */ 144 int break_active; /* break being received */ 145 146 bool use_dma_rx; /* enable DMA receiver */ 147 bool use_pdc_rx; /* enable PDC receiver */ 148 short pdc_rx_idx; /* current PDC RX buffer */ 149 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ 150 151 bool use_dma_tx; /* enable DMA transmitter */ 152 bool use_pdc_tx; /* enable PDC transmitter */ 153 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ 154 155 spinlock_t lock_tx; /* port lock */ 156 spinlock_t lock_rx; /* port lock */ 157 struct dma_chan *chan_tx; 158 struct dma_chan *chan_rx; 159 struct dma_async_tx_descriptor *desc_tx; 160 struct dma_async_tx_descriptor *desc_rx; 161 dma_cookie_t cookie_tx; 162 dma_cookie_t cookie_rx; 163 struct scatterlist sg_tx; 164 struct scatterlist sg_rx; 165 struct tasklet_struct tasklet; 166 unsigned int irq_status; 167 unsigned int irq_status_prev; 168 169 struct circ_buf rx_ring; 170 171 struct mctrl_gpios *gpios; 172 int gpio_irq[UART_GPIO_MAX]; 173 unsigned int tx_done_mask; 174 bool ms_irq_enabled; 175 bool is_usart; /* usart or uart */ 176 struct timer_list uart_timer; /* uart timer */ 177 178 bool suspended; 179 unsigned int pending; 180 unsigned int pending_status; 181 spinlock_t lock_suspended; 182 183 int (*prepare_rx)(struct uart_port *port); 184 int (*prepare_tx)(struct uart_port *port); 185 void (*schedule_rx)(struct uart_port *port); 186 void (*schedule_tx)(struct uart_port *port); 187 void (*release_rx)(struct uart_port *port); 188 void (*release_tx)(struct uart_port *port); 189 }; 190 191 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; 192 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); 193 194 #ifdef SUPPORT_SYSRQ 195 static struct console atmel_console; 196 #endif 197 198 #if defined(CONFIG_OF) 199 static const struct of_device_id atmel_serial_dt_ids[] = { 200 { .compatible = "atmel,at91rm9200-usart" }, 201 { .compatible = "atmel,at91sam9260-usart" }, 202 { /* sentinel */ } 203 }; 204 205 MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids); 206 #endif 207 208 static inline struct atmel_uart_port * 209 to_atmel_uart_port(struct uart_port *uart) 210 { 211 return container_of(uart, struct atmel_uart_port, uart); 212 } 213 214 #ifdef CONFIG_SERIAL_ATMEL_PDC 215 static bool atmel_use_pdc_rx(struct uart_port *port) 216 { 217 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 218 219 return atmel_port->use_pdc_rx; 220 } 221 222 static bool atmel_use_pdc_tx(struct uart_port *port) 223 { 224 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 225 226 return atmel_port->use_pdc_tx; 227 } 228 #else 229 static bool atmel_use_pdc_rx(struct uart_port *port) 230 { 231 return false; 232 } 233 234 static bool atmel_use_pdc_tx(struct uart_port *port) 235 { 236 return false; 237 } 238 #endif 239 240 static bool atmel_use_dma_tx(struct uart_port *port) 241 { 242 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 243 244 return atmel_port->use_dma_tx; 245 } 246 247 static bool atmel_use_dma_rx(struct uart_port *port) 248 { 249 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 250 251 return atmel_port->use_dma_rx; 252 } 253 254 static unsigned int atmel_get_lines_status(struct uart_port *port) 255 { 256 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 257 unsigned int status, ret = 0; 258 259 status = UART_GET_CSR(port); 260 261 mctrl_gpio_get(atmel_port->gpios, &ret); 262 263 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 264 UART_GPIO_CTS))) { 265 if (ret & TIOCM_CTS) 266 status &= ~ATMEL_US_CTS; 267 else 268 status |= ATMEL_US_CTS; 269 } 270 271 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 272 UART_GPIO_DSR))) { 273 if (ret & TIOCM_DSR) 274 status &= ~ATMEL_US_DSR; 275 else 276 status |= ATMEL_US_DSR; 277 } 278 279 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 280 UART_GPIO_RI))) { 281 if (ret & TIOCM_RI) 282 status &= ~ATMEL_US_RI; 283 else 284 status |= ATMEL_US_RI; 285 } 286 287 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 288 UART_GPIO_DCD))) { 289 if (ret & TIOCM_CD) 290 status &= ~ATMEL_US_DCD; 291 else 292 status |= ATMEL_US_DCD; 293 } 294 295 return status; 296 } 297 298 /* Enable or disable the rs485 support */ 299 static int atmel_config_rs485(struct uart_port *port, 300 struct serial_rs485 *rs485conf) 301 { 302 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 303 unsigned int mode; 304 305 /* Disable interrupts */ 306 UART_PUT_IDR(port, atmel_port->tx_done_mask); 307 308 mode = UART_GET_MR(port); 309 310 /* Resetting serial mode to RS232 (0x0) */ 311 mode &= ~ATMEL_US_USMODE; 312 313 port->rs485 = *rs485conf; 314 315 if (rs485conf->flags & SER_RS485_ENABLED) { 316 dev_dbg(port->dev, "Setting UART to RS485\n"); 317 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 318 if ((rs485conf->delay_rts_after_send) > 0) 319 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send); 320 mode |= ATMEL_US_USMODE_RS485; 321 } else { 322 dev_dbg(port->dev, "Setting UART to RS232\n"); 323 if (atmel_use_pdc_tx(port)) 324 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 325 ATMEL_US_TXBUFE; 326 else 327 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 328 } 329 UART_PUT_MR(port, mode); 330 331 /* Enable interrupts */ 332 UART_PUT_IER(port, atmel_port->tx_done_mask); 333 334 return 0; 335 } 336 337 /* 338 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. 339 */ 340 static u_int atmel_tx_empty(struct uart_port *port) 341 { 342 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; 343 } 344 345 /* 346 * Set state of the modem control output lines 347 */ 348 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) 349 { 350 unsigned int control = 0; 351 unsigned int mode = UART_GET_MR(port); 352 unsigned int rts_paused, rts_ready; 353 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 354 355 /* override mode to RS485 if needed, otherwise keep the current mode */ 356 if (port->rs485.flags & SER_RS485_ENABLED) { 357 if ((port->rs485.delay_rts_after_send) > 0) 358 UART_PUT_TTGR(port, port->rs485.delay_rts_after_send); 359 mode &= ~ATMEL_US_USMODE; 360 mode |= ATMEL_US_USMODE_RS485; 361 } 362 363 /* set the RTS line state according to the mode */ 364 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 365 /* force RTS line to high level */ 366 rts_paused = ATMEL_US_RTSEN; 367 368 /* give the control of the RTS line back to the hardware */ 369 rts_ready = ATMEL_US_RTSDIS; 370 } else { 371 /* force RTS line to high level */ 372 rts_paused = ATMEL_US_RTSDIS; 373 374 /* force RTS line to low level */ 375 rts_ready = ATMEL_US_RTSEN; 376 } 377 378 if (mctrl & TIOCM_RTS) 379 control |= rts_ready; 380 else 381 control |= rts_paused; 382 383 if (mctrl & TIOCM_DTR) 384 control |= ATMEL_US_DTREN; 385 else 386 control |= ATMEL_US_DTRDIS; 387 388 UART_PUT_CR(port, control); 389 390 mctrl_gpio_set(atmel_port->gpios, mctrl); 391 392 /* Local loopback mode? */ 393 mode &= ~ATMEL_US_CHMODE; 394 if (mctrl & TIOCM_LOOP) 395 mode |= ATMEL_US_CHMODE_LOC_LOOP; 396 else 397 mode |= ATMEL_US_CHMODE_NORMAL; 398 399 UART_PUT_MR(port, mode); 400 } 401 402 /* 403 * Get state of the modem control input lines 404 */ 405 static u_int atmel_get_mctrl(struct uart_port *port) 406 { 407 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 408 unsigned int ret = 0, status; 409 410 status = UART_GET_CSR(port); 411 412 /* 413 * The control signals are active low. 414 */ 415 if (!(status & ATMEL_US_DCD)) 416 ret |= TIOCM_CD; 417 if (!(status & ATMEL_US_CTS)) 418 ret |= TIOCM_CTS; 419 if (!(status & ATMEL_US_DSR)) 420 ret |= TIOCM_DSR; 421 if (!(status & ATMEL_US_RI)) 422 ret |= TIOCM_RI; 423 424 return mctrl_gpio_get(atmel_port->gpios, &ret); 425 } 426 427 /* 428 * Stop transmitting. 429 */ 430 static void atmel_stop_tx(struct uart_port *port) 431 { 432 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 433 434 if (atmel_use_pdc_tx(port)) { 435 /* disable PDC transmit */ 436 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 437 } 438 /* Disable interrupts */ 439 UART_PUT_IDR(port, atmel_port->tx_done_mask); 440 441 if ((port->rs485.flags & SER_RS485_ENABLED) && 442 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 443 atmel_start_rx(port); 444 } 445 446 /* 447 * Start transmitting. 448 */ 449 static void atmel_start_tx(struct uart_port *port) 450 { 451 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 452 453 if (atmel_use_pdc_tx(port)) { 454 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) 455 /* The transmitter is already running. Yes, we 456 really need this.*/ 457 return; 458 459 if ((port->rs485.flags & SER_RS485_ENABLED) && 460 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 461 atmel_stop_rx(port); 462 463 /* re-enable PDC transmit */ 464 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 465 } 466 /* Enable interrupts */ 467 UART_PUT_IER(port, atmel_port->tx_done_mask); 468 } 469 470 /* 471 * start receiving - port is in process of being opened. 472 */ 473 static void atmel_start_rx(struct uart_port *port) 474 { 475 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */ 476 477 UART_PUT_CR(port, ATMEL_US_RXEN); 478 479 if (atmel_use_pdc_rx(port)) { 480 /* enable PDC controller */ 481 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 482 port->read_status_mask); 483 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); 484 } else { 485 UART_PUT_IER(port, ATMEL_US_RXRDY); 486 } 487 } 488 489 /* 490 * Stop receiving - port is in process of being closed. 491 */ 492 static void atmel_stop_rx(struct uart_port *port) 493 { 494 UART_PUT_CR(port, ATMEL_US_RXDIS); 495 496 if (atmel_use_pdc_rx(port)) { 497 /* disable PDC receive */ 498 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); 499 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 500 port->read_status_mask); 501 } else { 502 UART_PUT_IDR(port, ATMEL_US_RXRDY); 503 } 504 } 505 506 /* 507 * Enable modem status interrupts 508 */ 509 static void atmel_enable_ms(struct uart_port *port) 510 { 511 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 512 uint32_t ier = 0; 513 514 /* 515 * Interrupt should not be enabled twice 516 */ 517 if (atmel_port->ms_irq_enabled) 518 return; 519 520 atmel_port->ms_irq_enabled = true; 521 522 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0) 523 enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]); 524 else 525 ier |= ATMEL_US_CTSIC; 526 527 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0) 528 enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]); 529 else 530 ier |= ATMEL_US_DSRIC; 531 532 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0) 533 enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]); 534 else 535 ier |= ATMEL_US_RIIC; 536 537 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0) 538 enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]); 539 else 540 ier |= ATMEL_US_DCDIC; 541 542 UART_PUT_IER(port, ier); 543 } 544 545 /* 546 * Disable modem status interrupts 547 */ 548 static void atmel_disable_ms(struct uart_port *port) 549 { 550 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 551 uint32_t idr = 0; 552 553 /* 554 * Interrupt should not be disabled twice 555 */ 556 if (!atmel_port->ms_irq_enabled) 557 return; 558 559 atmel_port->ms_irq_enabled = false; 560 561 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0) 562 disable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]); 563 else 564 idr |= ATMEL_US_CTSIC; 565 566 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0) 567 disable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]); 568 else 569 idr |= ATMEL_US_DSRIC; 570 571 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0) 572 disable_irq(atmel_port->gpio_irq[UART_GPIO_RI]); 573 else 574 idr |= ATMEL_US_RIIC; 575 576 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0) 577 disable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]); 578 else 579 idr |= ATMEL_US_DCDIC; 580 581 UART_PUT_IDR(port, idr); 582 } 583 584 /* 585 * Control the transmission of a break signal 586 */ 587 static void atmel_break_ctl(struct uart_port *port, int break_state) 588 { 589 if (break_state != 0) 590 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ 591 else 592 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ 593 } 594 595 /* 596 * Stores the incoming character in the ring buffer 597 */ 598 static void 599 atmel_buffer_rx_char(struct uart_port *port, unsigned int status, 600 unsigned int ch) 601 { 602 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 603 struct circ_buf *ring = &atmel_port->rx_ring; 604 struct atmel_uart_char *c; 605 606 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) 607 /* Buffer overflow, ignore char */ 608 return; 609 610 c = &((struct atmel_uart_char *)ring->buf)[ring->head]; 611 c->status = status; 612 c->ch = ch; 613 614 /* Make sure the character is stored before we update head. */ 615 smp_wmb(); 616 617 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 618 } 619 620 /* 621 * Deal with parity, framing and overrun errors. 622 */ 623 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) 624 { 625 /* clear error */ 626 UART_PUT_CR(port, ATMEL_US_RSTSTA); 627 628 if (status & ATMEL_US_RXBRK) { 629 /* ignore side-effect */ 630 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 631 port->icount.brk++; 632 } 633 if (status & ATMEL_US_PARE) 634 port->icount.parity++; 635 if (status & ATMEL_US_FRAME) 636 port->icount.frame++; 637 if (status & ATMEL_US_OVRE) 638 port->icount.overrun++; 639 } 640 641 /* 642 * Characters received (called from interrupt handler) 643 */ 644 static void atmel_rx_chars(struct uart_port *port) 645 { 646 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 647 unsigned int status, ch; 648 649 status = UART_GET_CSR(port); 650 while (status & ATMEL_US_RXRDY) { 651 ch = UART_GET_CHAR(port); 652 653 /* 654 * note that the error handling code is 655 * out of the main execution path 656 */ 657 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 658 | ATMEL_US_OVRE | ATMEL_US_RXBRK) 659 || atmel_port->break_active)) { 660 661 /* clear error */ 662 UART_PUT_CR(port, ATMEL_US_RSTSTA); 663 664 if (status & ATMEL_US_RXBRK 665 && !atmel_port->break_active) { 666 atmel_port->break_active = 1; 667 UART_PUT_IER(port, ATMEL_US_RXBRK); 668 } else { 669 /* 670 * This is either the end-of-break 671 * condition or we've received at 672 * least one character without RXBRK 673 * being set. In both cases, the next 674 * RXBRK will indicate start-of-break. 675 */ 676 UART_PUT_IDR(port, ATMEL_US_RXBRK); 677 status &= ~ATMEL_US_RXBRK; 678 atmel_port->break_active = 0; 679 } 680 } 681 682 atmel_buffer_rx_char(port, status, ch); 683 status = UART_GET_CSR(port); 684 } 685 686 tasklet_schedule(&atmel_port->tasklet); 687 } 688 689 /* 690 * Transmit characters (called from tasklet with TXRDY interrupt 691 * disabled) 692 */ 693 static void atmel_tx_chars(struct uart_port *port) 694 { 695 struct circ_buf *xmit = &port->state->xmit; 696 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 697 698 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) { 699 UART_PUT_CHAR(port, port->x_char); 700 port->icount.tx++; 701 port->x_char = 0; 702 } 703 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 704 return; 705 706 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) { 707 UART_PUT_CHAR(port, xmit->buf[xmit->tail]); 708 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 709 port->icount.tx++; 710 if (uart_circ_empty(xmit)) 711 break; 712 } 713 714 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 715 uart_write_wakeup(port); 716 717 if (!uart_circ_empty(xmit)) 718 /* Enable interrupts */ 719 UART_PUT_IER(port, atmel_port->tx_done_mask); 720 } 721 722 static void atmel_complete_tx_dma(void *arg) 723 { 724 struct atmel_uart_port *atmel_port = arg; 725 struct uart_port *port = &atmel_port->uart; 726 struct circ_buf *xmit = &port->state->xmit; 727 struct dma_chan *chan = atmel_port->chan_tx; 728 unsigned long flags; 729 730 spin_lock_irqsave(&port->lock, flags); 731 732 if (chan) 733 dmaengine_terminate_all(chan); 734 xmit->tail += sg_dma_len(&atmel_port->sg_tx); 735 xmit->tail &= UART_XMIT_SIZE - 1; 736 737 port->icount.tx += sg_dma_len(&atmel_port->sg_tx); 738 739 spin_lock_irq(&atmel_port->lock_tx); 740 async_tx_ack(atmel_port->desc_tx); 741 atmel_port->cookie_tx = -EINVAL; 742 atmel_port->desc_tx = NULL; 743 spin_unlock_irq(&atmel_port->lock_tx); 744 745 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 746 uart_write_wakeup(port); 747 748 /* 749 * xmit is a circular buffer so, if we have just send data from 750 * xmit->tail to the end of xmit->buf, now we have to transmit the 751 * remaining data from the beginning of xmit->buf to xmit->head. 752 */ 753 if (!uart_circ_empty(xmit)) 754 tasklet_schedule(&atmel_port->tasklet); 755 756 spin_unlock_irqrestore(&port->lock, flags); 757 } 758 759 static void atmel_release_tx_dma(struct uart_port *port) 760 { 761 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 762 struct dma_chan *chan = atmel_port->chan_tx; 763 764 if (chan) { 765 dmaengine_terminate_all(chan); 766 dma_release_channel(chan); 767 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, 768 DMA_TO_DEVICE); 769 } 770 771 atmel_port->desc_tx = NULL; 772 atmel_port->chan_tx = NULL; 773 atmel_port->cookie_tx = -EINVAL; 774 } 775 776 /* 777 * Called from tasklet with TXRDY interrupt is disabled. 778 */ 779 static void atmel_tx_dma(struct uart_port *port) 780 { 781 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 782 struct circ_buf *xmit = &port->state->xmit; 783 struct dma_chan *chan = atmel_port->chan_tx; 784 struct dma_async_tx_descriptor *desc; 785 struct scatterlist *sg = &atmel_port->sg_tx; 786 787 /* Make sure we have an idle channel */ 788 if (atmel_port->desc_tx != NULL) 789 return; 790 791 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 792 /* 793 * DMA is idle now. 794 * Port xmit buffer is already mapped, 795 * and it is one page... Just adjust 796 * offsets and lengths. Since it is a circular buffer, 797 * we have to transmit till the end, and then the rest. 798 * Take the port lock to get a 799 * consistent xmit buffer state. 800 */ 801 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 802 sg_dma_address(sg) = (sg_dma_address(sg) & 803 ~(UART_XMIT_SIZE - 1)) 804 + sg->offset; 805 sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head, 806 xmit->tail, 807 UART_XMIT_SIZE); 808 BUG_ON(!sg_dma_len(sg)); 809 810 desc = dmaengine_prep_slave_sg(chan, 811 sg, 812 1, 813 DMA_MEM_TO_DEV, 814 DMA_PREP_INTERRUPT | 815 DMA_CTRL_ACK); 816 if (!desc) { 817 dev_err(port->dev, "Failed to send via dma!\n"); 818 return; 819 } 820 821 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); 822 823 atmel_port->desc_tx = desc; 824 desc->callback = atmel_complete_tx_dma; 825 desc->callback_param = atmel_port; 826 atmel_port->cookie_tx = dmaengine_submit(desc); 827 828 } else { 829 if (port->rs485.flags & SER_RS485_ENABLED) { 830 /* DMA done, stop TX, start RX for RS485 */ 831 atmel_start_rx(port); 832 } 833 } 834 835 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 836 uart_write_wakeup(port); 837 } 838 839 static int atmel_prepare_tx_dma(struct uart_port *port) 840 { 841 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 842 dma_cap_mask_t mask; 843 struct dma_slave_config config; 844 int ret, nent; 845 846 dma_cap_zero(mask); 847 dma_cap_set(DMA_SLAVE, mask); 848 849 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx"); 850 if (atmel_port->chan_tx == NULL) 851 goto chan_err; 852 dev_info(port->dev, "using %s for tx DMA transfers\n", 853 dma_chan_name(atmel_port->chan_tx)); 854 855 spin_lock_init(&atmel_port->lock_tx); 856 sg_init_table(&atmel_port->sg_tx, 1); 857 /* UART circular tx buffer is an aligned page. */ 858 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); 859 sg_set_page(&atmel_port->sg_tx, 860 virt_to_page(port->state->xmit.buf), 861 UART_XMIT_SIZE, 862 (int)port->state->xmit.buf & ~PAGE_MASK); 863 nent = dma_map_sg(port->dev, 864 &atmel_port->sg_tx, 865 1, 866 DMA_TO_DEVICE); 867 868 if (!nent) { 869 dev_dbg(port->dev, "need to release resource of dma\n"); 870 goto chan_err; 871 } else { 872 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 873 sg_dma_len(&atmel_port->sg_tx), 874 port->state->xmit.buf, 875 sg_dma_address(&atmel_port->sg_tx)); 876 } 877 878 /* Configure the slave DMA */ 879 memset(&config, 0, sizeof(config)); 880 config.direction = DMA_MEM_TO_DEV; 881 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 882 config.dst_addr = port->mapbase + ATMEL_US_THR; 883 884 ret = dmaengine_slave_config(atmel_port->chan_tx, 885 &config); 886 if (ret) { 887 dev_err(port->dev, "DMA tx slave configuration failed\n"); 888 goto chan_err; 889 } 890 891 return 0; 892 893 chan_err: 894 dev_err(port->dev, "TX channel not available, switch to pio\n"); 895 atmel_port->use_dma_tx = 0; 896 if (atmel_port->chan_tx) 897 atmel_release_tx_dma(port); 898 return -EINVAL; 899 } 900 901 static void atmel_complete_rx_dma(void *arg) 902 { 903 struct uart_port *port = arg; 904 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 905 906 tasklet_schedule(&atmel_port->tasklet); 907 } 908 909 static void atmel_release_rx_dma(struct uart_port *port) 910 { 911 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 912 struct dma_chan *chan = atmel_port->chan_rx; 913 914 if (chan) { 915 dmaengine_terminate_all(chan); 916 dma_release_channel(chan); 917 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, 918 DMA_FROM_DEVICE); 919 } 920 921 atmel_port->desc_rx = NULL; 922 atmel_port->chan_rx = NULL; 923 atmel_port->cookie_rx = -EINVAL; 924 } 925 926 static void atmel_rx_from_dma(struct uart_port *port) 927 { 928 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 929 struct tty_port *tport = &port->state->port; 930 struct circ_buf *ring = &atmel_port->rx_ring; 931 struct dma_chan *chan = atmel_port->chan_rx; 932 struct dma_tx_state state; 933 enum dma_status dmastat; 934 size_t count; 935 936 937 /* Reset the UART timeout early so that we don't miss one */ 938 UART_PUT_CR(port, ATMEL_US_STTTO); 939 dmastat = dmaengine_tx_status(chan, 940 atmel_port->cookie_rx, 941 &state); 942 /* Restart a new tasklet if DMA status is error */ 943 if (dmastat == DMA_ERROR) { 944 dev_dbg(port->dev, "Get residue error, restart tasklet\n"); 945 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 946 tasklet_schedule(&atmel_port->tasklet); 947 return; 948 } 949 950 /* CPU claims ownership of RX DMA buffer */ 951 dma_sync_sg_for_cpu(port->dev, 952 &atmel_port->sg_rx, 953 1, 954 DMA_FROM_DEVICE); 955 956 /* 957 * ring->head points to the end of data already written by the DMA. 958 * ring->tail points to the beginning of data to be read by the 959 * framework. 960 * The current transfer size should not be larger than the dma buffer 961 * length. 962 */ 963 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue; 964 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx)); 965 /* 966 * At this point ring->head may point to the first byte right after the 967 * last byte of the dma buffer: 968 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx) 969 * 970 * However ring->tail must always points inside the dma buffer: 971 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1 972 * 973 * Since we use a ring buffer, we have to handle the case 974 * where head is lower than tail. In such a case, we first read from 975 * tail to the end of the buffer then reset tail. 976 */ 977 if (ring->head < ring->tail) { 978 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail; 979 980 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 981 ring->tail = 0; 982 port->icount.rx += count; 983 } 984 985 /* Finally we read data from tail to head */ 986 if (ring->tail < ring->head) { 987 count = ring->head - ring->tail; 988 989 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 990 /* Wrap ring->head if needed */ 991 if (ring->head >= sg_dma_len(&atmel_port->sg_rx)) 992 ring->head = 0; 993 ring->tail = ring->head; 994 port->icount.rx += count; 995 } 996 997 /* USART retreives ownership of RX DMA buffer */ 998 dma_sync_sg_for_device(port->dev, 999 &atmel_port->sg_rx, 1000 1, 1001 DMA_FROM_DEVICE); 1002 1003 /* 1004 * Drop the lock here since it might end up calling 1005 * uart_start(), which takes the lock. 1006 */ 1007 spin_unlock(&port->lock); 1008 tty_flip_buffer_push(tport); 1009 spin_lock(&port->lock); 1010 1011 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 1012 } 1013 1014 static int atmel_prepare_rx_dma(struct uart_port *port) 1015 { 1016 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1017 struct dma_async_tx_descriptor *desc; 1018 dma_cap_mask_t mask; 1019 struct dma_slave_config config; 1020 struct circ_buf *ring; 1021 int ret, nent; 1022 1023 ring = &atmel_port->rx_ring; 1024 1025 dma_cap_zero(mask); 1026 dma_cap_set(DMA_CYCLIC, mask); 1027 1028 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx"); 1029 if (atmel_port->chan_rx == NULL) 1030 goto chan_err; 1031 dev_info(port->dev, "using %s for rx DMA transfers\n", 1032 dma_chan_name(atmel_port->chan_rx)); 1033 1034 spin_lock_init(&atmel_port->lock_rx); 1035 sg_init_table(&atmel_port->sg_rx, 1); 1036 /* UART circular rx buffer is an aligned page. */ 1037 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); 1038 sg_set_page(&atmel_port->sg_rx, 1039 virt_to_page(ring->buf), 1040 ATMEL_SERIAL_RINGSIZE, 1041 (int)ring->buf & ~PAGE_MASK); 1042 nent = dma_map_sg(port->dev, 1043 &atmel_port->sg_rx, 1044 1, 1045 DMA_FROM_DEVICE); 1046 1047 if (!nent) { 1048 dev_dbg(port->dev, "need to release resource of dma\n"); 1049 goto chan_err; 1050 } else { 1051 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 1052 sg_dma_len(&atmel_port->sg_rx), 1053 ring->buf, 1054 sg_dma_address(&atmel_port->sg_rx)); 1055 } 1056 1057 /* Configure the slave DMA */ 1058 memset(&config, 0, sizeof(config)); 1059 config.direction = DMA_DEV_TO_MEM; 1060 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1061 config.src_addr = port->mapbase + ATMEL_US_RHR; 1062 1063 ret = dmaengine_slave_config(atmel_port->chan_rx, 1064 &config); 1065 if (ret) { 1066 dev_err(port->dev, "DMA rx slave configuration failed\n"); 1067 goto chan_err; 1068 } 1069 /* 1070 * Prepare a cyclic dma transfer, assign 2 descriptors, 1071 * each one is half ring buffer size 1072 */ 1073 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, 1074 sg_dma_address(&atmel_port->sg_rx), 1075 sg_dma_len(&atmel_port->sg_rx), 1076 sg_dma_len(&atmel_port->sg_rx)/2, 1077 DMA_DEV_TO_MEM, 1078 DMA_PREP_INTERRUPT); 1079 desc->callback = atmel_complete_rx_dma; 1080 desc->callback_param = port; 1081 atmel_port->desc_rx = desc; 1082 atmel_port->cookie_rx = dmaengine_submit(desc); 1083 1084 return 0; 1085 1086 chan_err: 1087 dev_err(port->dev, "RX channel not available, switch to pio\n"); 1088 atmel_port->use_dma_rx = 0; 1089 if (atmel_port->chan_rx) 1090 atmel_release_rx_dma(port); 1091 return -EINVAL; 1092 } 1093 1094 static void atmel_uart_timer_callback(unsigned long data) 1095 { 1096 struct uart_port *port = (void *)data; 1097 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1098 1099 tasklet_schedule(&atmel_port->tasklet); 1100 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port)); 1101 } 1102 1103 /* 1104 * receive interrupt handler. 1105 */ 1106 static void 1107 atmel_handle_receive(struct uart_port *port, unsigned int pending) 1108 { 1109 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1110 1111 if (atmel_use_pdc_rx(port)) { 1112 /* 1113 * PDC receive. Just schedule the tasklet and let it 1114 * figure out the details. 1115 * 1116 * TODO: We're not handling error flags correctly at 1117 * the moment. 1118 */ 1119 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { 1120 UART_PUT_IDR(port, (ATMEL_US_ENDRX 1121 | ATMEL_US_TIMEOUT)); 1122 tasklet_schedule(&atmel_port->tasklet); 1123 } 1124 1125 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | 1126 ATMEL_US_FRAME | ATMEL_US_PARE)) 1127 atmel_pdc_rxerr(port, pending); 1128 } 1129 1130 if (atmel_use_dma_rx(port)) { 1131 if (pending & ATMEL_US_TIMEOUT) { 1132 UART_PUT_IDR(port, ATMEL_US_TIMEOUT); 1133 tasklet_schedule(&atmel_port->tasklet); 1134 } 1135 } 1136 1137 /* Interrupt receive */ 1138 if (pending & ATMEL_US_RXRDY) 1139 atmel_rx_chars(port); 1140 else if (pending & ATMEL_US_RXBRK) { 1141 /* 1142 * End of break detected. If it came along with a 1143 * character, atmel_rx_chars will handle it. 1144 */ 1145 UART_PUT_CR(port, ATMEL_US_RSTSTA); 1146 UART_PUT_IDR(port, ATMEL_US_RXBRK); 1147 atmel_port->break_active = 0; 1148 } 1149 } 1150 1151 /* 1152 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) 1153 */ 1154 static void 1155 atmel_handle_transmit(struct uart_port *port, unsigned int pending) 1156 { 1157 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1158 1159 if (pending & atmel_port->tx_done_mask) { 1160 /* Either PDC or interrupt transmission */ 1161 UART_PUT_IDR(port, atmel_port->tx_done_mask); 1162 tasklet_schedule(&atmel_port->tasklet); 1163 } 1164 } 1165 1166 /* 1167 * status flags interrupt handler. 1168 */ 1169 static void 1170 atmel_handle_status(struct uart_port *port, unsigned int pending, 1171 unsigned int status) 1172 { 1173 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1174 1175 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC 1176 | ATMEL_US_CTSIC)) { 1177 atmel_port->irq_status = status; 1178 tasklet_schedule(&atmel_port->tasklet); 1179 } 1180 } 1181 1182 /* 1183 * Interrupt handler 1184 */ 1185 static irqreturn_t atmel_interrupt(int irq, void *dev_id) 1186 { 1187 struct uart_port *port = dev_id; 1188 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1189 unsigned int status, pending, mask, pass_counter = 0; 1190 bool gpio_handled = false; 1191 1192 spin_lock(&atmel_port->lock_suspended); 1193 1194 do { 1195 status = atmel_get_lines_status(port); 1196 mask = UART_GET_IMR(port); 1197 pending = status & mask; 1198 if (!gpio_handled) { 1199 /* 1200 * Dealing with GPIO interrupt 1201 */ 1202 if (irq == atmel_port->gpio_irq[UART_GPIO_CTS]) 1203 pending |= ATMEL_US_CTSIC; 1204 1205 if (irq == atmel_port->gpio_irq[UART_GPIO_DSR]) 1206 pending |= ATMEL_US_DSRIC; 1207 1208 if (irq == atmel_port->gpio_irq[UART_GPIO_RI]) 1209 pending |= ATMEL_US_RIIC; 1210 1211 if (irq == atmel_port->gpio_irq[UART_GPIO_DCD]) 1212 pending |= ATMEL_US_DCDIC; 1213 1214 gpio_handled = true; 1215 } 1216 if (!pending) 1217 break; 1218 1219 if (atmel_port->suspended) { 1220 atmel_port->pending |= pending; 1221 atmel_port->pending_status = status; 1222 UART_PUT_IDR(port, mask); 1223 pm_system_wakeup(); 1224 break; 1225 } 1226 1227 atmel_handle_receive(port, pending); 1228 atmel_handle_status(port, pending, status); 1229 atmel_handle_transmit(port, pending); 1230 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); 1231 1232 spin_unlock(&atmel_port->lock_suspended); 1233 1234 return pass_counter ? IRQ_HANDLED : IRQ_NONE; 1235 } 1236 1237 static void atmel_release_tx_pdc(struct uart_port *port) 1238 { 1239 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1240 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1241 1242 dma_unmap_single(port->dev, 1243 pdc->dma_addr, 1244 pdc->dma_size, 1245 DMA_TO_DEVICE); 1246 } 1247 1248 /* 1249 * Called from tasklet with ENDTX and TXBUFE interrupts disabled. 1250 */ 1251 static void atmel_tx_pdc(struct uart_port *port) 1252 { 1253 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1254 struct circ_buf *xmit = &port->state->xmit; 1255 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1256 int count; 1257 1258 /* nothing left to transmit? */ 1259 if (UART_GET_TCR(port)) 1260 return; 1261 1262 xmit->tail += pdc->ofs; 1263 xmit->tail &= UART_XMIT_SIZE - 1; 1264 1265 port->icount.tx += pdc->ofs; 1266 pdc->ofs = 0; 1267 1268 /* more to transmit - setup next transfer */ 1269 1270 /* disable PDC transmit */ 1271 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 1272 1273 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 1274 dma_sync_single_for_device(port->dev, 1275 pdc->dma_addr, 1276 pdc->dma_size, 1277 DMA_TO_DEVICE); 1278 1279 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1280 pdc->ofs = count; 1281 1282 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); 1283 UART_PUT_TCR(port, count); 1284 /* re-enable PDC transmit */ 1285 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 1286 /* Enable interrupts */ 1287 UART_PUT_IER(port, atmel_port->tx_done_mask); 1288 } else { 1289 if ((port->rs485.flags & SER_RS485_ENABLED) && 1290 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) { 1291 /* DMA done, stop TX, start RX for RS485 */ 1292 atmel_start_rx(port); 1293 } 1294 } 1295 1296 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1297 uart_write_wakeup(port); 1298 } 1299 1300 static int atmel_prepare_tx_pdc(struct uart_port *port) 1301 { 1302 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1303 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1304 struct circ_buf *xmit = &port->state->xmit; 1305 1306 pdc->buf = xmit->buf; 1307 pdc->dma_addr = dma_map_single(port->dev, 1308 pdc->buf, 1309 UART_XMIT_SIZE, 1310 DMA_TO_DEVICE); 1311 pdc->dma_size = UART_XMIT_SIZE; 1312 pdc->ofs = 0; 1313 1314 return 0; 1315 } 1316 1317 static void atmel_rx_from_ring(struct uart_port *port) 1318 { 1319 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1320 struct circ_buf *ring = &atmel_port->rx_ring; 1321 unsigned int flg; 1322 unsigned int status; 1323 1324 while (ring->head != ring->tail) { 1325 struct atmel_uart_char c; 1326 1327 /* Make sure c is loaded after head. */ 1328 smp_rmb(); 1329 1330 c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; 1331 1332 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 1333 1334 port->icount.rx++; 1335 status = c.status; 1336 flg = TTY_NORMAL; 1337 1338 /* 1339 * note that the error handling code is 1340 * out of the main execution path 1341 */ 1342 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 1343 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { 1344 if (status & ATMEL_US_RXBRK) { 1345 /* ignore side-effect */ 1346 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 1347 1348 port->icount.brk++; 1349 if (uart_handle_break(port)) 1350 continue; 1351 } 1352 if (status & ATMEL_US_PARE) 1353 port->icount.parity++; 1354 if (status & ATMEL_US_FRAME) 1355 port->icount.frame++; 1356 if (status & ATMEL_US_OVRE) 1357 port->icount.overrun++; 1358 1359 status &= port->read_status_mask; 1360 1361 if (status & ATMEL_US_RXBRK) 1362 flg = TTY_BREAK; 1363 else if (status & ATMEL_US_PARE) 1364 flg = TTY_PARITY; 1365 else if (status & ATMEL_US_FRAME) 1366 flg = TTY_FRAME; 1367 } 1368 1369 1370 if (uart_handle_sysrq_char(port, c.ch)) 1371 continue; 1372 1373 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); 1374 } 1375 1376 /* 1377 * Drop the lock here since it might end up calling 1378 * uart_start(), which takes the lock. 1379 */ 1380 spin_unlock(&port->lock); 1381 tty_flip_buffer_push(&port->state->port); 1382 spin_lock(&port->lock); 1383 } 1384 1385 static void atmel_release_rx_pdc(struct uart_port *port) 1386 { 1387 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1388 int i; 1389 1390 for (i = 0; i < 2; i++) { 1391 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1392 1393 dma_unmap_single(port->dev, 1394 pdc->dma_addr, 1395 pdc->dma_size, 1396 DMA_FROM_DEVICE); 1397 kfree(pdc->buf); 1398 } 1399 } 1400 1401 static void atmel_rx_from_pdc(struct uart_port *port) 1402 { 1403 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1404 struct tty_port *tport = &port->state->port; 1405 struct atmel_dma_buffer *pdc; 1406 int rx_idx = atmel_port->pdc_rx_idx; 1407 unsigned int head; 1408 unsigned int tail; 1409 unsigned int count; 1410 1411 do { 1412 /* Reset the UART timeout early so that we don't miss one */ 1413 UART_PUT_CR(port, ATMEL_US_STTTO); 1414 1415 pdc = &atmel_port->pdc_rx[rx_idx]; 1416 head = UART_GET_RPR(port) - pdc->dma_addr; 1417 tail = pdc->ofs; 1418 1419 /* If the PDC has switched buffers, RPR won't contain 1420 * any address within the current buffer. Since head 1421 * is unsigned, we just need a one-way comparison to 1422 * find out. 1423 * 1424 * In this case, we just need to consume the entire 1425 * buffer and resubmit it for DMA. This will clear the 1426 * ENDRX bit as well, so that we can safely re-enable 1427 * all interrupts below. 1428 */ 1429 head = min(head, pdc->dma_size); 1430 1431 if (likely(head != tail)) { 1432 dma_sync_single_for_cpu(port->dev, pdc->dma_addr, 1433 pdc->dma_size, DMA_FROM_DEVICE); 1434 1435 /* 1436 * head will only wrap around when we recycle 1437 * the DMA buffer, and when that happens, we 1438 * explicitly set tail to 0. So head will 1439 * always be greater than tail. 1440 */ 1441 count = head - tail; 1442 1443 tty_insert_flip_string(tport, pdc->buf + pdc->ofs, 1444 count); 1445 1446 dma_sync_single_for_device(port->dev, pdc->dma_addr, 1447 pdc->dma_size, DMA_FROM_DEVICE); 1448 1449 port->icount.rx += count; 1450 pdc->ofs = head; 1451 } 1452 1453 /* 1454 * If the current buffer is full, we need to check if 1455 * the next one contains any additional data. 1456 */ 1457 if (head >= pdc->dma_size) { 1458 pdc->ofs = 0; 1459 UART_PUT_RNPR(port, pdc->dma_addr); 1460 UART_PUT_RNCR(port, pdc->dma_size); 1461 1462 rx_idx = !rx_idx; 1463 atmel_port->pdc_rx_idx = rx_idx; 1464 } 1465 } while (head >= pdc->dma_size); 1466 1467 /* 1468 * Drop the lock here since it might end up calling 1469 * uart_start(), which takes the lock. 1470 */ 1471 spin_unlock(&port->lock); 1472 tty_flip_buffer_push(tport); 1473 spin_lock(&port->lock); 1474 1475 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1476 } 1477 1478 static int atmel_prepare_rx_pdc(struct uart_port *port) 1479 { 1480 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1481 int i; 1482 1483 for (i = 0; i < 2; i++) { 1484 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1485 1486 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); 1487 if (pdc->buf == NULL) { 1488 if (i != 0) { 1489 dma_unmap_single(port->dev, 1490 atmel_port->pdc_rx[0].dma_addr, 1491 PDC_BUFFER_SIZE, 1492 DMA_FROM_DEVICE); 1493 kfree(atmel_port->pdc_rx[0].buf); 1494 } 1495 atmel_port->use_pdc_rx = 0; 1496 return -ENOMEM; 1497 } 1498 pdc->dma_addr = dma_map_single(port->dev, 1499 pdc->buf, 1500 PDC_BUFFER_SIZE, 1501 DMA_FROM_DEVICE); 1502 pdc->dma_size = PDC_BUFFER_SIZE; 1503 pdc->ofs = 0; 1504 } 1505 1506 atmel_port->pdc_rx_idx = 0; 1507 1508 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); 1509 UART_PUT_RCR(port, PDC_BUFFER_SIZE); 1510 1511 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); 1512 UART_PUT_RNCR(port, PDC_BUFFER_SIZE); 1513 1514 return 0; 1515 } 1516 1517 /* 1518 * tasklet handling tty stuff outside the interrupt handler. 1519 */ 1520 static void atmel_tasklet_func(unsigned long data) 1521 { 1522 struct uart_port *port = (struct uart_port *)data; 1523 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1524 unsigned int status; 1525 unsigned int status_change; 1526 1527 /* The interrupt handler does not take the lock */ 1528 spin_lock(&port->lock); 1529 1530 atmel_port->schedule_tx(port); 1531 1532 status = atmel_port->irq_status; 1533 status_change = status ^ atmel_port->irq_status_prev; 1534 1535 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR 1536 | ATMEL_US_DCD | ATMEL_US_CTS)) { 1537 /* TODO: All reads to CSR will clear these interrupts! */ 1538 if (status_change & ATMEL_US_RI) 1539 port->icount.rng++; 1540 if (status_change & ATMEL_US_DSR) 1541 port->icount.dsr++; 1542 if (status_change & ATMEL_US_DCD) 1543 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); 1544 if (status_change & ATMEL_US_CTS) 1545 uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); 1546 1547 wake_up_interruptible(&port->state->port.delta_msr_wait); 1548 1549 atmel_port->irq_status_prev = status; 1550 } 1551 1552 atmel_port->schedule_rx(port); 1553 1554 spin_unlock(&port->lock); 1555 } 1556 1557 static int atmel_init_property(struct atmel_uart_port *atmel_port, 1558 struct platform_device *pdev) 1559 { 1560 struct device_node *np = pdev->dev.of_node; 1561 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1562 1563 if (np) { 1564 /* DMA/PDC usage specification */ 1565 if (of_get_property(np, "atmel,use-dma-rx", NULL)) { 1566 if (of_get_property(np, "dmas", NULL)) { 1567 atmel_port->use_dma_rx = true; 1568 atmel_port->use_pdc_rx = false; 1569 } else { 1570 atmel_port->use_dma_rx = false; 1571 atmel_port->use_pdc_rx = true; 1572 } 1573 } else { 1574 atmel_port->use_dma_rx = false; 1575 atmel_port->use_pdc_rx = false; 1576 } 1577 1578 if (of_get_property(np, "atmel,use-dma-tx", NULL)) { 1579 if (of_get_property(np, "dmas", NULL)) { 1580 atmel_port->use_dma_tx = true; 1581 atmel_port->use_pdc_tx = false; 1582 } else { 1583 atmel_port->use_dma_tx = false; 1584 atmel_port->use_pdc_tx = true; 1585 } 1586 } else { 1587 atmel_port->use_dma_tx = false; 1588 atmel_port->use_pdc_tx = false; 1589 } 1590 1591 } else { 1592 atmel_port->use_pdc_rx = pdata->use_dma_rx; 1593 atmel_port->use_pdc_tx = pdata->use_dma_tx; 1594 atmel_port->use_dma_rx = false; 1595 atmel_port->use_dma_tx = false; 1596 } 1597 1598 return 0; 1599 } 1600 1601 static void atmel_init_rs485(struct uart_port *port, 1602 struct platform_device *pdev) 1603 { 1604 struct device_node *np = pdev->dev.of_node; 1605 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1606 1607 if (np) { 1608 u32 rs485_delay[2]; 1609 /* rs485 properties */ 1610 if (of_property_read_u32_array(np, "rs485-rts-delay", 1611 rs485_delay, 2) == 0) { 1612 struct serial_rs485 *rs485conf = &port->rs485; 1613 1614 rs485conf->delay_rts_before_send = rs485_delay[0]; 1615 rs485conf->delay_rts_after_send = rs485_delay[1]; 1616 rs485conf->flags = 0; 1617 1618 if (of_get_property(np, "rs485-rx-during-tx", NULL)) 1619 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1620 1621 if (of_get_property(np, "linux,rs485-enabled-at-boot-time", 1622 NULL)) 1623 rs485conf->flags |= SER_RS485_ENABLED; 1624 } 1625 } else { 1626 port->rs485 = pdata->rs485; 1627 } 1628 1629 } 1630 1631 static void atmel_set_ops(struct uart_port *port) 1632 { 1633 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1634 1635 if (atmel_use_dma_rx(port)) { 1636 atmel_port->prepare_rx = &atmel_prepare_rx_dma; 1637 atmel_port->schedule_rx = &atmel_rx_from_dma; 1638 atmel_port->release_rx = &atmel_release_rx_dma; 1639 } else if (atmel_use_pdc_rx(port)) { 1640 atmel_port->prepare_rx = &atmel_prepare_rx_pdc; 1641 atmel_port->schedule_rx = &atmel_rx_from_pdc; 1642 atmel_port->release_rx = &atmel_release_rx_pdc; 1643 } else { 1644 atmel_port->prepare_rx = NULL; 1645 atmel_port->schedule_rx = &atmel_rx_from_ring; 1646 atmel_port->release_rx = NULL; 1647 } 1648 1649 if (atmel_use_dma_tx(port)) { 1650 atmel_port->prepare_tx = &atmel_prepare_tx_dma; 1651 atmel_port->schedule_tx = &atmel_tx_dma; 1652 atmel_port->release_tx = &atmel_release_tx_dma; 1653 } else if (atmel_use_pdc_tx(port)) { 1654 atmel_port->prepare_tx = &atmel_prepare_tx_pdc; 1655 atmel_port->schedule_tx = &atmel_tx_pdc; 1656 atmel_port->release_tx = &atmel_release_tx_pdc; 1657 } else { 1658 atmel_port->prepare_tx = NULL; 1659 atmel_port->schedule_tx = &atmel_tx_chars; 1660 atmel_port->release_tx = NULL; 1661 } 1662 } 1663 1664 /* 1665 * Get ip name usart or uart 1666 */ 1667 static void atmel_get_ip_name(struct uart_port *port) 1668 { 1669 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1670 int name = UART_GET_IP_NAME(port); 1671 u32 version; 1672 int usart, uart; 1673 /* usart and uart ascii */ 1674 usart = 0x55534152; 1675 uart = 0x44424755; 1676 1677 atmel_port->is_usart = false; 1678 1679 if (name == usart) { 1680 dev_dbg(port->dev, "This is usart\n"); 1681 atmel_port->is_usart = true; 1682 } else if (name == uart) { 1683 dev_dbg(port->dev, "This is uart\n"); 1684 atmel_port->is_usart = false; 1685 } else { 1686 /* fallback for older SoCs: use version field */ 1687 version = UART_GET_IP_VERSION(port); 1688 switch (version) { 1689 case 0x302: 1690 case 0x10213: 1691 dev_dbg(port->dev, "This version is usart\n"); 1692 atmel_port->is_usart = true; 1693 break; 1694 case 0x203: 1695 case 0x10202: 1696 dev_dbg(port->dev, "This version is uart\n"); 1697 atmel_port->is_usart = false; 1698 break; 1699 default: 1700 dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); 1701 } 1702 } 1703 } 1704 1705 static void atmel_free_gpio_irq(struct uart_port *port) 1706 { 1707 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1708 enum mctrl_gpio_idx i; 1709 1710 for (i = 0; i < UART_GPIO_MAX; i++) 1711 if (atmel_port->gpio_irq[i] >= 0) 1712 free_irq(atmel_port->gpio_irq[i], port); 1713 } 1714 1715 static int atmel_request_gpio_irq(struct uart_port *port) 1716 { 1717 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1718 int *irq = atmel_port->gpio_irq; 1719 enum mctrl_gpio_idx i; 1720 int err = 0; 1721 1722 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) { 1723 if (irq[i] < 0) 1724 continue; 1725 1726 irq_set_status_flags(irq[i], IRQ_NOAUTOEN); 1727 err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH, 1728 "atmel_serial", port); 1729 if (err) 1730 dev_err(port->dev, "atmel_startup - Can't get %d irq\n", 1731 irq[i]); 1732 } 1733 1734 /* 1735 * If something went wrong, rollback. 1736 */ 1737 while (err && (--i >= 0)) 1738 if (irq[i] >= 0) 1739 free_irq(irq[i], port); 1740 1741 return err; 1742 } 1743 1744 /* 1745 * Perform initialization and enable port for reception 1746 */ 1747 static int atmel_startup(struct uart_port *port) 1748 { 1749 struct platform_device *pdev = to_platform_device(port->dev); 1750 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1751 struct tty_struct *tty = port->state->port.tty; 1752 int retval; 1753 1754 /* 1755 * Ensure that no interrupts are enabled otherwise when 1756 * request_irq() is called we could get stuck trying to 1757 * handle an unexpected interrupt 1758 */ 1759 UART_PUT_IDR(port, -1); 1760 atmel_port->ms_irq_enabled = false; 1761 1762 /* 1763 * Allocate the IRQ 1764 */ 1765 retval = request_irq(port->irq, atmel_interrupt, 1766 IRQF_SHARED | IRQF_COND_SUSPEND, 1767 tty ? tty->name : "atmel_serial", port); 1768 if (retval) { 1769 dev_err(port->dev, "atmel_startup - Can't get irq\n"); 1770 return retval; 1771 } 1772 1773 /* 1774 * Get the GPIO lines IRQ 1775 */ 1776 retval = atmel_request_gpio_irq(port); 1777 if (retval) 1778 goto free_irq; 1779 1780 /* 1781 * Initialize DMA (if necessary) 1782 */ 1783 atmel_init_property(atmel_port, pdev); 1784 1785 if (atmel_port->prepare_rx) { 1786 retval = atmel_port->prepare_rx(port); 1787 if (retval < 0) 1788 atmel_set_ops(port); 1789 } 1790 1791 if (atmel_port->prepare_tx) { 1792 retval = atmel_port->prepare_tx(port); 1793 if (retval < 0) 1794 atmel_set_ops(port); 1795 } 1796 1797 /* Save current CSR for comparison in atmel_tasklet_func() */ 1798 atmel_port->irq_status_prev = atmel_get_lines_status(port); 1799 atmel_port->irq_status = atmel_port->irq_status_prev; 1800 1801 /* 1802 * Finally, enable the serial port 1803 */ 1804 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1805 /* enable xmit & rcvr */ 1806 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 1807 1808 setup_timer(&atmel_port->uart_timer, 1809 atmel_uart_timer_callback, 1810 (unsigned long)port); 1811 1812 if (atmel_use_pdc_rx(port)) { 1813 /* set UART timeout */ 1814 if (!atmel_port->is_usart) { 1815 mod_timer(&atmel_port->uart_timer, 1816 jiffies + uart_poll_timeout(port)); 1817 /* set USART timeout */ 1818 } else { 1819 UART_PUT_RTOR(port, PDC_RX_TIMEOUT); 1820 UART_PUT_CR(port, ATMEL_US_STTTO); 1821 1822 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1823 } 1824 /* enable PDC controller */ 1825 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); 1826 } else if (atmel_use_dma_rx(port)) { 1827 /* set UART timeout */ 1828 if (!atmel_port->is_usart) { 1829 mod_timer(&atmel_port->uart_timer, 1830 jiffies + uart_poll_timeout(port)); 1831 /* set USART timeout */ 1832 } else { 1833 UART_PUT_RTOR(port, PDC_RX_TIMEOUT); 1834 UART_PUT_CR(port, ATMEL_US_STTTO); 1835 1836 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 1837 } 1838 } else { 1839 /* enable receive only */ 1840 UART_PUT_IER(port, ATMEL_US_RXRDY); 1841 } 1842 1843 return 0; 1844 1845 free_irq: 1846 free_irq(port->irq, port); 1847 1848 return retval; 1849 } 1850 1851 /* 1852 * Flush any TX data submitted for DMA. Called when the TX circular 1853 * buffer is reset. 1854 */ 1855 static void atmel_flush_buffer(struct uart_port *port) 1856 { 1857 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1858 1859 if (atmel_use_pdc_tx(port)) { 1860 UART_PUT_TCR(port, 0); 1861 atmel_port->pdc_tx.ofs = 0; 1862 } 1863 } 1864 1865 /* 1866 * Disable the port 1867 */ 1868 static void atmel_shutdown(struct uart_port *port) 1869 { 1870 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1871 1872 /* 1873 * Prevent any tasklets being scheduled during 1874 * cleanup 1875 */ 1876 del_timer_sync(&atmel_port->uart_timer); 1877 1878 /* 1879 * Clear out any scheduled tasklets before 1880 * we destroy the buffers 1881 */ 1882 tasklet_kill(&atmel_port->tasklet); 1883 1884 /* 1885 * Ensure everything is stopped and 1886 * disable all interrupts, port and break condition. 1887 */ 1888 atmel_stop_rx(port); 1889 atmel_stop_tx(port); 1890 1891 UART_PUT_CR(port, ATMEL_US_RSTSTA); 1892 UART_PUT_IDR(port, -1); 1893 1894 1895 /* 1896 * Shut-down the DMA. 1897 */ 1898 if (atmel_port->release_rx) 1899 atmel_port->release_rx(port); 1900 if (atmel_port->release_tx) 1901 atmel_port->release_tx(port); 1902 1903 /* 1904 * Reset ring buffer pointers 1905 */ 1906 atmel_port->rx_ring.head = 0; 1907 atmel_port->rx_ring.tail = 0; 1908 1909 /* 1910 * Free the interrupts 1911 */ 1912 free_irq(port->irq, port); 1913 atmel_free_gpio_irq(port); 1914 1915 atmel_port->ms_irq_enabled = false; 1916 1917 atmel_flush_buffer(port); 1918 } 1919 1920 /* 1921 * Power / Clock management. 1922 */ 1923 static void atmel_serial_pm(struct uart_port *port, unsigned int state, 1924 unsigned int oldstate) 1925 { 1926 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1927 1928 switch (state) { 1929 case 0: 1930 /* 1931 * Enable the peripheral clock for this serial port. 1932 * This is called on uart_open() or a resume event. 1933 */ 1934 clk_prepare_enable(atmel_port->clk); 1935 1936 /* re-enable interrupts if we disabled some on suspend */ 1937 UART_PUT_IER(port, atmel_port->backup_imr); 1938 break; 1939 case 3: 1940 /* Back up the interrupt mask and disable all interrupts */ 1941 atmel_port->backup_imr = UART_GET_IMR(port); 1942 UART_PUT_IDR(port, -1); 1943 1944 /* 1945 * Disable the peripheral clock for this serial port. 1946 * This is called on uart_close() or a suspend event. 1947 */ 1948 clk_disable_unprepare(atmel_port->clk); 1949 break; 1950 default: 1951 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); 1952 } 1953 } 1954 1955 /* 1956 * Change the port parameters 1957 */ 1958 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, 1959 struct ktermios *old) 1960 { 1961 unsigned long flags; 1962 unsigned int old_mode, mode, imr, quot, baud; 1963 1964 /* save the current mode register */ 1965 mode = old_mode = UART_GET_MR(port); 1966 1967 /* reset the mode, clock divisor, parity, stop bits and data size */ 1968 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | 1969 ATMEL_US_PAR | ATMEL_US_USMODE); 1970 1971 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1972 quot = uart_get_divisor(port, baud); 1973 1974 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ 1975 quot /= 8; 1976 mode |= ATMEL_US_USCLKS_MCK_DIV8; 1977 } 1978 1979 /* byte size */ 1980 switch (termios->c_cflag & CSIZE) { 1981 case CS5: 1982 mode |= ATMEL_US_CHRL_5; 1983 break; 1984 case CS6: 1985 mode |= ATMEL_US_CHRL_6; 1986 break; 1987 case CS7: 1988 mode |= ATMEL_US_CHRL_7; 1989 break; 1990 default: 1991 mode |= ATMEL_US_CHRL_8; 1992 break; 1993 } 1994 1995 /* stop bits */ 1996 if (termios->c_cflag & CSTOPB) 1997 mode |= ATMEL_US_NBSTOP_2; 1998 1999 /* parity */ 2000 if (termios->c_cflag & PARENB) { 2001 /* Mark or Space parity */ 2002 if (termios->c_cflag & CMSPAR) { 2003 if (termios->c_cflag & PARODD) 2004 mode |= ATMEL_US_PAR_MARK; 2005 else 2006 mode |= ATMEL_US_PAR_SPACE; 2007 } else if (termios->c_cflag & PARODD) 2008 mode |= ATMEL_US_PAR_ODD; 2009 else 2010 mode |= ATMEL_US_PAR_EVEN; 2011 } else 2012 mode |= ATMEL_US_PAR_NONE; 2013 2014 spin_lock_irqsave(&port->lock, flags); 2015 2016 port->read_status_mask = ATMEL_US_OVRE; 2017 if (termios->c_iflag & INPCK) 2018 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2019 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2020 port->read_status_mask |= ATMEL_US_RXBRK; 2021 2022 if (atmel_use_pdc_rx(port)) 2023 /* need to enable error interrupts */ 2024 UART_PUT_IER(port, port->read_status_mask); 2025 2026 /* 2027 * Characters to ignore 2028 */ 2029 port->ignore_status_mask = 0; 2030 if (termios->c_iflag & IGNPAR) 2031 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2032 if (termios->c_iflag & IGNBRK) { 2033 port->ignore_status_mask |= ATMEL_US_RXBRK; 2034 /* 2035 * If we're ignoring parity and break indicators, 2036 * ignore overruns too (for real raw support). 2037 */ 2038 if (termios->c_iflag & IGNPAR) 2039 port->ignore_status_mask |= ATMEL_US_OVRE; 2040 } 2041 /* TODO: Ignore all characters if CREAD is set.*/ 2042 2043 /* update the per-port timeout */ 2044 uart_update_timeout(port, termios->c_cflag, baud); 2045 2046 /* 2047 * save/disable interrupts. The tty layer will ensure that the 2048 * transmitter is empty if requested by the caller, so there's 2049 * no need to wait for it here. 2050 */ 2051 imr = UART_GET_IMR(port); 2052 UART_PUT_IDR(port, -1); 2053 2054 /* disable receiver and transmitter */ 2055 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); 2056 2057 /* mode */ 2058 if (port->rs485.flags & SER_RS485_ENABLED) { 2059 if ((port->rs485.delay_rts_after_send) > 0) 2060 UART_PUT_TTGR(port, port->rs485.delay_rts_after_send); 2061 mode |= ATMEL_US_USMODE_RS485; 2062 } else if (termios->c_cflag & CRTSCTS) { 2063 /* RS232 with hardware handshake (RTS/CTS) */ 2064 mode |= ATMEL_US_USMODE_HWHS; 2065 } else { 2066 /* RS232 without hadware handshake */ 2067 mode |= ATMEL_US_USMODE_NORMAL; 2068 } 2069 2070 /* set the mode, clock divisor, parity, stop bits and data size */ 2071 UART_PUT_MR(port, mode); 2072 2073 /* 2074 * when switching the mode, set the RTS line state according to the 2075 * new mode, otherwise keep the former state 2076 */ 2077 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) { 2078 unsigned int rts_state; 2079 2080 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 2081 /* let the hardware control the RTS line */ 2082 rts_state = ATMEL_US_RTSDIS; 2083 } else { 2084 /* force RTS line to low level */ 2085 rts_state = ATMEL_US_RTSEN; 2086 } 2087 2088 UART_PUT_CR(port, rts_state); 2089 } 2090 2091 /* set the baud rate */ 2092 UART_PUT_BRGR(port, quot); 2093 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2094 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 2095 2096 /* restore interrupts */ 2097 UART_PUT_IER(port, imr); 2098 2099 /* CTS flow-control and modem-status interrupts */ 2100 if (UART_ENABLE_MS(port, termios->c_cflag)) 2101 atmel_enable_ms(port); 2102 else 2103 atmel_disable_ms(port); 2104 2105 spin_unlock_irqrestore(&port->lock, flags); 2106 } 2107 2108 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios) 2109 { 2110 if (termios->c_line == N_PPS) { 2111 port->flags |= UPF_HARDPPS_CD; 2112 spin_lock_irq(&port->lock); 2113 atmel_enable_ms(port); 2114 spin_unlock_irq(&port->lock); 2115 } else { 2116 port->flags &= ~UPF_HARDPPS_CD; 2117 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 2118 spin_lock_irq(&port->lock); 2119 atmel_disable_ms(port); 2120 spin_unlock_irq(&port->lock); 2121 } 2122 } 2123 } 2124 2125 /* 2126 * Return string describing the specified port 2127 */ 2128 static const char *atmel_type(struct uart_port *port) 2129 { 2130 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; 2131 } 2132 2133 /* 2134 * Release the memory region(s) being used by 'port'. 2135 */ 2136 static void atmel_release_port(struct uart_port *port) 2137 { 2138 struct platform_device *pdev = to_platform_device(port->dev); 2139 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 2140 2141 release_mem_region(port->mapbase, size); 2142 2143 if (port->flags & UPF_IOREMAP) { 2144 iounmap(port->membase); 2145 port->membase = NULL; 2146 } 2147 } 2148 2149 /* 2150 * Request the memory region(s) being used by 'port'. 2151 */ 2152 static int atmel_request_port(struct uart_port *port) 2153 { 2154 struct platform_device *pdev = to_platform_device(port->dev); 2155 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 2156 2157 if (!request_mem_region(port->mapbase, size, "atmel_serial")) 2158 return -EBUSY; 2159 2160 if (port->flags & UPF_IOREMAP) { 2161 port->membase = ioremap(port->mapbase, size); 2162 if (port->membase == NULL) { 2163 release_mem_region(port->mapbase, size); 2164 return -ENOMEM; 2165 } 2166 } 2167 2168 return 0; 2169 } 2170 2171 /* 2172 * Configure/autoconfigure the port. 2173 */ 2174 static void atmel_config_port(struct uart_port *port, int flags) 2175 { 2176 if (flags & UART_CONFIG_TYPE) { 2177 port->type = PORT_ATMEL; 2178 atmel_request_port(port); 2179 } 2180 } 2181 2182 /* 2183 * Verify the new serial_struct (for TIOCSSERIAL). 2184 */ 2185 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) 2186 { 2187 int ret = 0; 2188 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) 2189 ret = -EINVAL; 2190 if (port->irq != ser->irq) 2191 ret = -EINVAL; 2192 if (ser->io_type != SERIAL_IO_MEM) 2193 ret = -EINVAL; 2194 if (port->uartclk / 16 != ser->baud_base) 2195 ret = -EINVAL; 2196 if ((void *)port->mapbase != ser->iomem_base) 2197 ret = -EINVAL; 2198 if (port->iobase != ser->port) 2199 ret = -EINVAL; 2200 if (ser->hub6 != 0) 2201 ret = -EINVAL; 2202 return ret; 2203 } 2204 2205 #ifdef CONFIG_CONSOLE_POLL 2206 static int atmel_poll_get_char(struct uart_port *port) 2207 { 2208 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY)) 2209 cpu_relax(); 2210 2211 return UART_GET_CHAR(port); 2212 } 2213 2214 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) 2215 { 2216 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) 2217 cpu_relax(); 2218 2219 UART_PUT_CHAR(port, ch); 2220 } 2221 #endif 2222 2223 static struct uart_ops atmel_pops = { 2224 .tx_empty = atmel_tx_empty, 2225 .set_mctrl = atmel_set_mctrl, 2226 .get_mctrl = atmel_get_mctrl, 2227 .stop_tx = atmel_stop_tx, 2228 .start_tx = atmel_start_tx, 2229 .stop_rx = atmel_stop_rx, 2230 .enable_ms = atmel_enable_ms, 2231 .break_ctl = atmel_break_ctl, 2232 .startup = atmel_startup, 2233 .shutdown = atmel_shutdown, 2234 .flush_buffer = atmel_flush_buffer, 2235 .set_termios = atmel_set_termios, 2236 .set_ldisc = atmel_set_ldisc, 2237 .type = atmel_type, 2238 .release_port = atmel_release_port, 2239 .request_port = atmel_request_port, 2240 .config_port = atmel_config_port, 2241 .verify_port = atmel_verify_port, 2242 .pm = atmel_serial_pm, 2243 #ifdef CONFIG_CONSOLE_POLL 2244 .poll_get_char = atmel_poll_get_char, 2245 .poll_put_char = atmel_poll_put_char, 2246 #endif 2247 }; 2248 2249 /* 2250 * Configure the port from the platform device resource info. 2251 */ 2252 static int atmel_init_port(struct atmel_uart_port *atmel_port, 2253 struct platform_device *pdev) 2254 { 2255 int ret; 2256 struct uart_port *port = &atmel_port->uart; 2257 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2258 2259 if (!atmel_init_property(atmel_port, pdev)) 2260 atmel_set_ops(port); 2261 2262 atmel_init_rs485(port, pdev); 2263 2264 port->iotype = UPIO_MEM; 2265 port->flags = UPF_BOOT_AUTOCONF; 2266 port->ops = &atmel_pops; 2267 port->fifosize = 1; 2268 port->dev = &pdev->dev; 2269 port->mapbase = pdev->resource[0].start; 2270 port->irq = pdev->resource[1].start; 2271 port->rs485_config = atmel_config_rs485; 2272 2273 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, 2274 (unsigned long)port); 2275 2276 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); 2277 2278 if (pdata && pdata->regs) { 2279 /* Already mapped by setup code */ 2280 port->membase = pdata->regs; 2281 } else { 2282 port->flags |= UPF_IOREMAP; 2283 port->membase = NULL; 2284 } 2285 2286 /* for console, the clock could already be configured */ 2287 if (!atmel_port->clk) { 2288 atmel_port->clk = clk_get(&pdev->dev, "usart"); 2289 if (IS_ERR(atmel_port->clk)) { 2290 ret = PTR_ERR(atmel_port->clk); 2291 atmel_port->clk = NULL; 2292 return ret; 2293 } 2294 ret = clk_prepare_enable(atmel_port->clk); 2295 if (ret) { 2296 clk_put(atmel_port->clk); 2297 atmel_port->clk = NULL; 2298 return ret; 2299 } 2300 port->uartclk = clk_get_rate(atmel_port->clk); 2301 clk_disable_unprepare(atmel_port->clk); 2302 /* only enable clock when USART is in use */ 2303 } 2304 2305 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ 2306 if (port->rs485.flags & SER_RS485_ENABLED) 2307 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 2308 else if (atmel_use_pdc_tx(port)) { 2309 port->fifosize = PDC_BUFFER_SIZE; 2310 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; 2311 } else { 2312 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 2313 } 2314 2315 return 0; 2316 } 2317 2318 struct platform_device *atmel_default_console_device; /* the serial console device */ 2319 2320 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2321 static void atmel_console_putchar(struct uart_port *port, int ch) 2322 { 2323 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) 2324 cpu_relax(); 2325 UART_PUT_CHAR(port, ch); 2326 } 2327 2328 /* 2329 * Interrupts are disabled on entering 2330 */ 2331 static void atmel_console_write(struct console *co, const char *s, u_int count) 2332 { 2333 struct uart_port *port = &atmel_ports[co->index].uart; 2334 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2335 unsigned int status, imr; 2336 unsigned int pdc_tx; 2337 2338 /* 2339 * First, save IMR and then disable interrupts 2340 */ 2341 imr = UART_GET_IMR(port); 2342 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask); 2343 2344 /* Store PDC transmit status and disable it */ 2345 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN; 2346 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 2347 2348 uart_console_write(port, s, count, atmel_console_putchar); 2349 2350 /* 2351 * Finally, wait for transmitter to become empty 2352 * and restore IMR 2353 */ 2354 do { 2355 status = UART_GET_CSR(port); 2356 } while (!(status & ATMEL_US_TXRDY)); 2357 2358 /* Restore PDC transmit status */ 2359 if (pdc_tx) 2360 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 2361 2362 /* set interrupts back the way they were */ 2363 UART_PUT_IER(port, imr); 2364 } 2365 2366 /* 2367 * If the port was already initialised (eg, by a boot loader), 2368 * try to determine the current setup. 2369 */ 2370 static void __init atmel_console_get_options(struct uart_port *port, int *baud, 2371 int *parity, int *bits) 2372 { 2373 unsigned int mr, quot; 2374 2375 /* 2376 * If the baud rate generator isn't running, the port wasn't 2377 * initialized by the boot loader. 2378 */ 2379 quot = UART_GET_BRGR(port) & ATMEL_US_CD; 2380 if (!quot) 2381 return; 2382 2383 mr = UART_GET_MR(port) & ATMEL_US_CHRL; 2384 if (mr == ATMEL_US_CHRL_8) 2385 *bits = 8; 2386 else 2387 *bits = 7; 2388 2389 mr = UART_GET_MR(port) & ATMEL_US_PAR; 2390 if (mr == ATMEL_US_PAR_EVEN) 2391 *parity = 'e'; 2392 else if (mr == ATMEL_US_PAR_ODD) 2393 *parity = 'o'; 2394 2395 /* 2396 * The serial core only rounds down when matching this to a 2397 * supported baud rate. Make sure we don't end up slightly 2398 * lower than one of those, as it would make us fall through 2399 * to a much lower baud rate than we really want. 2400 */ 2401 *baud = port->uartclk / (16 * (quot - 1)); 2402 } 2403 2404 static int __init atmel_console_setup(struct console *co, char *options) 2405 { 2406 int ret; 2407 struct uart_port *port = &atmel_ports[co->index].uart; 2408 int baud = 115200; 2409 int bits = 8; 2410 int parity = 'n'; 2411 int flow = 'n'; 2412 2413 if (port->membase == NULL) { 2414 /* Port not initialized yet - delay setup */ 2415 return -ENODEV; 2416 } 2417 2418 ret = clk_prepare_enable(atmel_ports[co->index].clk); 2419 if (ret) 2420 return ret; 2421 2422 UART_PUT_IDR(port, -1); 2423 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2424 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 2425 2426 if (options) 2427 uart_parse_options(options, &baud, &parity, &bits, &flow); 2428 else 2429 atmel_console_get_options(port, &baud, &parity, &bits); 2430 2431 return uart_set_options(port, co, baud, parity, bits, flow); 2432 } 2433 2434 static struct uart_driver atmel_uart; 2435 2436 static struct console atmel_console = { 2437 .name = ATMEL_DEVICENAME, 2438 .write = atmel_console_write, 2439 .device = uart_console_device, 2440 .setup = atmel_console_setup, 2441 .flags = CON_PRINTBUFFER, 2442 .index = -1, 2443 .data = &atmel_uart, 2444 }; 2445 2446 #define ATMEL_CONSOLE_DEVICE (&atmel_console) 2447 2448 /* 2449 * Early console initialization (before VM subsystem initialized). 2450 */ 2451 static int __init atmel_console_init(void) 2452 { 2453 int ret; 2454 if (atmel_default_console_device) { 2455 struct atmel_uart_data *pdata = 2456 dev_get_platdata(&atmel_default_console_device->dev); 2457 int id = pdata->num; 2458 struct atmel_uart_port *port = &atmel_ports[id]; 2459 2460 port->backup_imr = 0; 2461 port->uart.line = id; 2462 2463 add_preferred_console(ATMEL_DEVICENAME, id, NULL); 2464 ret = atmel_init_port(port, atmel_default_console_device); 2465 if (ret) 2466 return ret; 2467 register_console(&atmel_console); 2468 } 2469 2470 return 0; 2471 } 2472 2473 console_initcall(atmel_console_init); 2474 2475 /* 2476 * Late console initialization. 2477 */ 2478 static int __init atmel_late_console_init(void) 2479 { 2480 if (atmel_default_console_device 2481 && !(atmel_console.flags & CON_ENABLED)) 2482 register_console(&atmel_console); 2483 2484 return 0; 2485 } 2486 2487 core_initcall(atmel_late_console_init); 2488 2489 static inline bool atmel_is_console_port(struct uart_port *port) 2490 { 2491 return port->cons && port->cons->index == port->line; 2492 } 2493 2494 #else 2495 #define ATMEL_CONSOLE_DEVICE NULL 2496 2497 static inline bool atmel_is_console_port(struct uart_port *port) 2498 { 2499 return false; 2500 } 2501 #endif 2502 2503 static struct uart_driver atmel_uart = { 2504 .owner = THIS_MODULE, 2505 .driver_name = "atmel_serial", 2506 .dev_name = ATMEL_DEVICENAME, 2507 .major = SERIAL_ATMEL_MAJOR, 2508 .minor = MINOR_START, 2509 .nr = ATMEL_MAX_UART, 2510 .cons = ATMEL_CONSOLE_DEVICE, 2511 }; 2512 2513 #ifdef CONFIG_PM 2514 static bool atmel_serial_clk_will_stop(void) 2515 { 2516 #ifdef CONFIG_ARCH_AT91 2517 return at91_suspend_entering_slow_clock(); 2518 #else 2519 return false; 2520 #endif 2521 } 2522 2523 static int atmel_serial_suspend(struct platform_device *pdev, 2524 pm_message_t state) 2525 { 2526 struct uart_port *port = platform_get_drvdata(pdev); 2527 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2528 2529 if (atmel_is_console_port(port) && console_suspend_enabled) { 2530 /* Drain the TX shifter */ 2531 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) 2532 cpu_relax(); 2533 } 2534 2535 /* we can not wake up if we're running on slow clock */ 2536 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); 2537 if (atmel_serial_clk_will_stop()) { 2538 unsigned long flags; 2539 2540 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2541 atmel_port->suspended = true; 2542 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2543 device_set_wakeup_enable(&pdev->dev, 0); 2544 } 2545 2546 uart_suspend_port(&atmel_uart, port); 2547 2548 return 0; 2549 } 2550 2551 static int atmel_serial_resume(struct platform_device *pdev) 2552 { 2553 struct uart_port *port = platform_get_drvdata(pdev); 2554 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2555 unsigned long flags; 2556 2557 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2558 if (atmel_port->pending) { 2559 atmel_handle_receive(port, atmel_port->pending); 2560 atmel_handle_status(port, atmel_port->pending, 2561 atmel_port->pending_status); 2562 atmel_handle_transmit(port, atmel_port->pending); 2563 atmel_port->pending = 0; 2564 } 2565 atmel_port->suspended = false; 2566 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2567 2568 uart_resume_port(&atmel_uart, port); 2569 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); 2570 2571 return 0; 2572 } 2573 #else 2574 #define atmel_serial_suspend NULL 2575 #define atmel_serial_resume NULL 2576 #endif 2577 2578 static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev) 2579 { 2580 enum mctrl_gpio_idx i; 2581 struct gpio_desc *gpiod; 2582 2583 p->gpios = mctrl_gpio_init(dev, 0); 2584 if (IS_ERR_OR_NULL(p->gpios)) 2585 return -1; 2586 2587 for (i = 0; i < UART_GPIO_MAX; i++) { 2588 gpiod = mctrl_gpio_to_gpiod(p->gpios, i); 2589 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN)) 2590 p->gpio_irq[i] = gpiod_to_irq(gpiod); 2591 else 2592 p->gpio_irq[i] = -EINVAL; 2593 } 2594 2595 return 0; 2596 } 2597 2598 static int atmel_serial_probe(struct platform_device *pdev) 2599 { 2600 struct atmel_uart_port *port; 2601 struct device_node *np = pdev->dev.of_node; 2602 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2603 void *data; 2604 int ret = -ENODEV; 2605 bool rs485_enabled; 2606 2607 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); 2608 2609 if (np) 2610 ret = of_alias_get_id(np, "serial"); 2611 else 2612 if (pdata) 2613 ret = pdata->num; 2614 2615 if (ret < 0) 2616 /* port id not found in platform data nor device-tree aliases: 2617 * auto-enumerate it */ 2618 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); 2619 2620 if (ret >= ATMEL_MAX_UART) { 2621 ret = -ENODEV; 2622 goto err; 2623 } 2624 2625 if (test_and_set_bit(ret, atmel_ports_in_use)) { 2626 /* port already in use */ 2627 ret = -EBUSY; 2628 goto err; 2629 } 2630 2631 port = &atmel_ports[ret]; 2632 port->backup_imr = 0; 2633 port->uart.line = ret; 2634 2635 spin_lock_init(&port->lock_suspended); 2636 2637 ret = atmel_init_gpios(port, &pdev->dev); 2638 if (ret < 0) 2639 dev_err(&pdev->dev, "%s", 2640 "Failed to initialize GPIOs. The serial port may not work as expected"); 2641 2642 ret = atmel_init_port(port, pdev); 2643 if (ret) 2644 goto err_clear_bit; 2645 2646 if (!atmel_use_pdc_rx(&port->uart)) { 2647 ret = -ENOMEM; 2648 data = kmalloc(sizeof(struct atmel_uart_char) 2649 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); 2650 if (!data) 2651 goto err_alloc_ring; 2652 port->rx_ring.buf = data; 2653 } 2654 2655 rs485_enabled = port->uart.rs485.flags & SER_RS485_ENABLED; 2656 2657 ret = uart_add_one_port(&atmel_uart, &port->uart); 2658 if (ret) 2659 goto err_add_port; 2660 2661 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2662 if (atmel_is_console_port(&port->uart) 2663 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { 2664 /* 2665 * The serial core enabled the clock for us, so undo 2666 * the clk_prepare_enable() in atmel_console_setup() 2667 */ 2668 clk_disable_unprepare(port->clk); 2669 } 2670 #endif 2671 2672 device_init_wakeup(&pdev->dev, 1); 2673 platform_set_drvdata(pdev, port); 2674 2675 /* 2676 * The peripheral clock has been disabled by atmel_init_port(): 2677 * enable it before accessing I/O registers 2678 */ 2679 clk_prepare_enable(port->clk); 2680 2681 if (rs485_enabled) { 2682 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL); 2683 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN); 2684 } 2685 2686 /* 2687 * Get port name of usart or uart 2688 */ 2689 atmel_get_ip_name(&port->uart); 2690 2691 /* 2692 * The peripheral clock can now safely be disabled till the port 2693 * is used 2694 */ 2695 clk_disable_unprepare(port->clk); 2696 2697 return 0; 2698 2699 err_add_port: 2700 kfree(port->rx_ring.buf); 2701 port->rx_ring.buf = NULL; 2702 err_alloc_ring: 2703 if (!atmel_is_console_port(&port->uart)) { 2704 clk_put(port->clk); 2705 port->clk = NULL; 2706 } 2707 err_clear_bit: 2708 clear_bit(port->uart.line, atmel_ports_in_use); 2709 err: 2710 return ret; 2711 } 2712 2713 static int atmel_serial_remove(struct platform_device *pdev) 2714 { 2715 struct uart_port *port = platform_get_drvdata(pdev); 2716 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2717 int ret = 0; 2718 2719 tasklet_kill(&atmel_port->tasklet); 2720 2721 device_init_wakeup(&pdev->dev, 0); 2722 2723 ret = uart_remove_one_port(&atmel_uart, port); 2724 2725 kfree(atmel_port->rx_ring.buf); 2726 2727 /* "port" is allocated statically, so we shouldn't free it */ 2728 2729 clear_bit(port->line, atmel_ports_in_use); 2730 2731 clk_put(atmel_port->clk); 2732 2733 return ret; 2734 } 2735 2736 static struct platform_driver atmel_serial_driver = { 2737 .probe = atmel_serial_probe, 2738 .remove = atmel_serial_remove, 2739 .suspend = atmel_serial_suspend, 2740 .resume = atmel_serial_resume, 2741 .driver = { 2742 .name = "atmel_usart", 2743 .of_match_table = of_match_ptr(atmel_serial_dt_ids), 2744 }, 2745 }; 2746 2747 static int __init atmel_serial_init(void) 2748 { 2749 int ret; 2750 2751 ret = uart_register_driver(&atmel_uart); 2752 if (ret) 2753 return ret; 2754 2755 ret = platform_driver_register(&atmel_serial_driver); 2756 if (ret) 2757 uart_unregister_driver(&atmel_uart); 2758 2759 return ret; 2760 } 2761 2762 static void __exit atmel_serial_exit(void) 2763 { 2764 platform_driver_unregister(&atmel_serial_driver); 2765 uart_unregister_driver(&atmel_uart); 2766 } 2767 2768 module_init(atmel_serial_init); 2769 module_exit(atmel_serial_exit); 2770 2771 MODULE_AUTHOR("Rick Bronson"); 2772 MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); 2773 MODULE_LICENSE("GPL"); 2774 MODULE_ALIAS("platform:atmel_usart"); 2775