1 /* 2 * Driver for Atmel AT91 / AT32 Serial ports 3 * Copyright (C) 2003 Rick Bronson 4 * 5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. 6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 7 * 8 * DMA support added by Chip Coldwell. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 #include <linux/module.h> 26 #include <linux/tty.h> 27 #include <linux/ioport.h> 28 #include <linux/slab.h> 29 #include <linux/init.h> 30 #include <linux/serial.h> 31 #include <linux/clk.h> 32 #include <linux/console.h> 33 #include <linux/sysrq.h> 34 #include <linux/tty_flip.h> 35 #include <linux/platform_device.h> 36 #include <linux/of.h> 37 #include <linux/of_device.h> 38 #include <linux/of_gpio.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/atmel_pdc.h> 41 #include <linux/atmel_serial.h> 42 #include <linux/uaccess.h> 43 #include <linux/platform_data/atmel.h> 44 #include <linux/timer.h> 45 #include <linux/gpio.h> 46 47 #include <asm/io.h> 48 #include <asm/ioctls.h> 49 50 #define PDC_BUFFER_SIZE 512 51 /* Revisit: We should calculate this based on the actual port settings */ 52 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ 53 54 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 55 #define SUPPORT_SYSRQ 56 #endif 57 58 #include <linux/serial_core.h> 59 60 static void atmel_start_rx(struct uart_port *port); 61 static void atmel_stop_rx(struct uart_port *port); 62 63 #ifdef CONFIG_SERIAL_ATMEL_TTYAT 64 65 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we 66 * should coexist with the 8250 driver, such as if we have an external 16C550 67 * UART. */ 68 #define SERIAL_ATMEL_MAJOR 204 69 #define MINOR_START 154 70 #define ATMEL_DEVICENAME "ttyAT" 71 72 #else 73 74 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port 75 * name, but it is legally reserved for the 8250 driver. */ 76 #define SERIAL_ATMEL_MAJOR TTY_MAJOR 77 #define MINOR_START 64 78 #define ATMEL_DEVICENAME "ttyS" 79 80 #endif 81 82 #define ATMEL_ISR_PASS_LIMIT 256 83 84 /* UART registers. CR is write-only, hence no GET macro */ 85 #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) 86 #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) 87 #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) 88 #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) 89 #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) 90 #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) 91 #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) 92 #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) 93 #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) 94 #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) 95 #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) 96 #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) 97 #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR) 98 #define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME) 99 #define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION) 100 101 /* PDC registers */ 102 #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) 103 #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) 104 105 #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) 106 #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) 107 #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) 108 #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) 109 #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) 110 111 #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) 112 #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) 113 #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR) 114 115 struct atmel_dma_buffer { 116 unsigned char *buf; 117 dma_addr_t dma_addr; 118 unsigned int dma_size; 119 unsigned int ofs; 120 }; 121 122 struct atmel_uart_char { 123 u16 status; 124 u16 ch; 125 }; 126 127 #define ATMEL_SERIAL_RINGSIZE 1024 128 129 /* 130 * We wrap our port structure around the generic uart_port. 131 */ 132 struct atmel_uart_port { 133 struct uart_port uart; /* uart */ 134 struct clk *clk; /* uart clock */ 135 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ 136 u32 backup_imr; /* IMR saved during suspend */ 137 int break_active; /* break being received */ 138 139 bool use_dma_rx; /* enable DMA receiver */ 140 bool use_pdc_rx; /* enable PDC receiver */ 141 short pdc_rx_idx; /* current PDC RX buffer */ 142 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ 143 144 bool use_dma_tx; /* enable DMA transmitter */ 145 bool use_pdc_tx; /* enable PDC transmitter */ 146 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ 147 148 spinlock_t lock_tx; /* port lock */ 149 spinlock_t lock_rx; /* port lock */ 150 struct dma_chan *chan_tx; 151 struct dma_chan *chan_rx; 152 struct dma_async_tx_descriptor *desc_tx; 153 struct dma_async_tx_descriptor *desc_rx; 154 dma_cookie_t cookie_tx; 155 dma_cookie_t cookie_rx; 156 struct scatterlist sg_tx; 157 struct scatterlist sg_rx; 158 struct tasklet_struct tasklet; 159 unsigned int irq_status; 160 unsigned int irq_status_prev; 161 162 struct circ_buf rx_ring; 163 164 struct serial_rs485 rs485; /* rs485 settings */ 165 int rts_gpio; /* optional RTS GPIO */ 166 unsigned int tx_done_mask; 167 bool is_usart; /* usart or uart */ 168 struct timer_list uart_timer; /* uart timer */ 169 int (*prepare_rx)(struct uart_port *port); 170 int (*prepare_tx)(struct uart_port *port); 171 void (*schedule_rx)(struct uart_port *port); 172 void (*schedule_tx)(struct uart_port *port); 173 void (*release_rx)(struct uart_port *port); 174 void (*release_tx)(struct uart_port *port); 175 }; 176 177 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; 178 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); 179 180 #ifdef SUPPORT_SYSRQ 181 static struct console atmel_console; 182 #endif 183 184 #if defined(CONFIG_OF) 185 static const struct of_device_id atmel_serial_dt_ids[] = { 186 { .compatible = "atmel,at91rm9200-usart" }, 187 { .compatible = "atmel,at91sam9260-usart" }, 188 { /* sentinel */ } 189 }; 190 191 MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids); 192 #endif 193 194 static inline struct atmel_uart_port * 195 to_atmel_uart_port(struct uart_port *uart) 196 { 197 return container_of(uart, struct atmel_uart_port, uart); 198 } 199 200 #ifdef CONFIG_SERIAL_ATMEL_PDC 201 static bool atmel_use_pdc_rx(struct uart_port *port) 202 { 203 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 204 205 return atmel_port->use_pdc_rx; 206 } 207 208 static bool atmel_use_pdc_tx(struct uart_port *port) 209 { 210 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 211 212 return atmel_port->use_pdc_tx; 213 } 214 #else 215 static bool atmel_use_pdc_rx(struct uart_port *port) 216 { 217 return false; 218 } 219 220 static bool atmel_use_pdc_tx(struct uart_port *port) 221 { 222 return false; 223 } 224 #endif 225 226 static bool atmel_use_dma_tx(struct uart_port *port) 227 { 228 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 229 230 return atmel_port->use_dma_tx; 231 } 232 233 static bool atmel_use_dma_rx(struct uart_port *port) 234 { 235 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 236 237 return atmel_port->use_dma_rx; 238 } 239 240 /* Enable or disable the rs485 support */ 241 void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf) 242 { 243 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 244 unsigned int mode; 245 unsigned long flags; 246 247 spin_lock_irqsave(&port->lock, flags); 248 249 /* Disable interrupts */ 250 UART_PUT_IDR(port, atmel_port->tx_done_mask); 251 252 mode = UART_GET_MR(port); 253 254 /* Resetting serial mode to RS232 (0x0) */ 255 mode &= ~ATMEL_US_USMODE; 256 257 atmel_port->rs485 = *rs485conf; 258 259 if (rs485conf->flags & SER_RS485_ENABLED) { 260 dev_dbg(port->dev, "Setting UART to RS485\n"); 261 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 262 if ((rs485conf->delay_rts_after_send) > 0) 263 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send); 264 mode |= ATMEL_US_USMODE_RS485; 265 } else { 266 dev_dbg(port->dev, "Setting UART to RS232\n"); 267 if (atmel_use_pdc_tx(port)) 268 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 269 ATMEL_US_TXBUFE; 270 else 271 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 272 } 273 UART_PUT_MR(port, mode); 274 275 /* Enable interrupts */ 276 UART_PUT_IER(port, atmel_port->tx_done_mask); 277 278 spin_unlock_irqrestore(&port->lock, flags); 279 280 } 281 282 /* 283 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. 284 */ 285 static u_int atmel_tx_empty(struct uart_port *port) 286 { 287 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; 288 } 289 290 /* 291 * Set state of the modem control output lines 292 */ 293 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) 294 { 295 unsigned int control = 0; 296 unsigned int mode; 297 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 298 299 /* 300 * AT91RM9200 Errata #39: RTS0 is not internally connected 301 * to PA21. We need to drive the pin as a GPIO. 302 */ 303 if (gpio_is_valid(atmel_port->rts_gpio)) { 304 if (mctrl & TIOCM_RTS) 305 gpio_set_value(atmel_port->rts_gpio, 0); 306 else 307 gpio_set_value(atmel_port->rts_gpio, 1); 308 } 309 310 if (mctrl & TIOCM_RTS) 311 control |= ATMEL_US_RTSEN; 312 else 313 control |= ATMEL_US_RTSDIS; 314 315 if (mctrl & TIOCM_DTR) 316 control |= ATMEL_US_DTREN; 317 else 318 control |= ATMEL_US_DTRDIS; 319 320 UART_PUT_CR(port, control); 321 322 /* Local loopback mode? */ 323 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE; 324 if (mctrl & TIOCM_LOOP) 325 mode |= ATMEL_US_CHMODE_LOC_LOOP; 326 else 327 mode |= ATMEL_US_CHMODE_NORMAL; 328 329 /* Resetting serial mode to RS232 (0x0) */ 330 mode &= ~ATMEL_US_USMODE; 331 332 if (atmel_port->rs485.flags & SER_RS485_ENABLED) { 333 dev_dbg(port->dev, "Setting UART to RS485\n"); 334 if ((atmel_port->rs485.delay_rts_after_send) > 0) 335 UART_PUT_TTGR(port, 336 atmel_port->rs485.delay_rts_after_send); 337 mode |= ATMEL_US_USMODE_RS485; 338 } else { 339 dev_dbg(port->dev, "Setting UART to RS232\n"); 340 } 341 UART_PUT_MR(port, mode); 342 } 343 344 /* 345 * Get state of the modem control input lines 346 */ 347 static u_int atmel_get_mctrl(struct uart_port *port) 348 { 349 unsigned int status, ret = 0; 350 351 status = UART_GET_CSR(port); 352 353 /* 354 * The control signals are active low. 355 */ 356 if (!(status & ATMEL_US_DCD)) 357 ret |= TIOCM_CD; 358 if (!(status & ATMEL_US_CTS)) 359 ret |= TIOCM_CTS; 360 if (!(status & ATMEL_US_DSR)) 361 ret |= TIOCM_DSR; 362 if (!(status & ATMEL_US_RI)) 363 ret |= TIOCM_RI; 364 365 return ret; 366 } 367 368 /* 369 * Stop transmitting. 370 */ 371 static void atmel_stop_tx(struct uart_port *port) 372 { 373 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 374 375 if (atmel_use_pdc_tx(port)) { 376 /* disable PDC transmit */ 377 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 378 } 379 /* Disable interrupts */ 380 UART_PUT_IDR(port, atmel_port->tx_done_mask); 381 382 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && 383 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) 384 atmel_start_rx(port); 385 } 386 387 /* 388 * Start transmitting. 389 */ 390 static void atmel_start_tx(struct uart_port *port) 391 { 392 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 393 394 if (atmel_use_pdc_tx(port)) { 395 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) 396 /* The transmitter is already running. Yes, we 397 really need this.*/ 398 return; 399 400 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && 401 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) 402 atmel_stop_rx(port); 403 404 /* re-enable PDC transmit */ 405 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 406 } 407 /* Enable interrupts */ 408 UART_PUT_IER(port, atmel_port->tx_done_mask); 409 } 410 411 /* 412 * start receiving - port is in process of being opened. 413 */ 414 static void atmel_start_rx(struct uart_port *port) 415 { 416 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */ 417 418 UART_PUT_CR(port, ATMEL_US_RXEN); 419 420 if (atmel_use_pdc_rx(port)) { 421 /* enable PDC controller */ 422 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 423 port->read_status_mask); 424 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); 425 } else { 426 UART_PUT_IER(port, ATMEL_US_RXRDY); 427 } 428 } 429 430 /* 431 * Stop receiving - port is in process of being closed. 432 */ 433 static void atmel_stop_rx(struct uart_port *port) 434 { 435 UART_PUT_CR(port, ATMEL_US_RXDIS); 436 437 if (atmel_use_pdc_rx(port)) { 438 /* disable PDC receive */ 439 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); 440 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 441 port->read_status_mask); 442 } else { 443 UART_PUT_IDR(port, ATMEL_US_RXRDY); 444 } 445 } 446 447 /* 448 * Enable modem status interrupts 449 */ 450 static void atmel_enable_ms(struct uart_port *port) 451 { 452 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC 453 | ATMEL_US_DCDIC | ATMEL_US_CTSIC); 454 } 455 456 /* 457 * Control the transmission of a break signal 458 */ 459 static void atmel_break_ctl(struct uart_port *port, int break_state) 460 { 461 if (break_state != 0) 462 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ 463 else 464 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ 465 } 466 467 /* 468 * Stores the incoming character in the ring buffer 469 */ 470 static void 471 atmel_buffer_rx_char(struct uart_port *port, unsigned int status, 472 unsigned int ch) 473 { 474 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 475 struct circ_buf *ring = &atmel_port->rx_ring; 476 struct atmel_uart_char *c; 477 478 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) 479 /* Buffer overflow, ignore char */ 480 return; 481 482 c = &((struct atmel_uart_char *)ring->buf)[ring->head]; 483 c->status = status; 484 c->ch = ch; 485 486 /* Make sure the character is stored before we update head. */ 487 smp_wmb(); 488 489 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 490 } 491 492 /* 493 * Deal with parity, framing and overrun errors. 494 */ 495 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) 496 { 497 /* clear error */ 498 UART_PUT_CR(port, ATMEL_US_RSTSTA); 499 500 if (status & ATMEL_US_RXBRK) { 501 /* ignore side-effect */ 502 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 503 port->icount.brk++; 504 } 505 if (status & ATMEL_US_PARE) 506 port->icount.parity++; 507 if (status & ATMEL_US_FRAME) 508 port->icount.frame++; 509 if (status & ATMEL_US_OVRE) 510 port->icount.overrun++; 511 } 512 513 /* 514 * Characters received (called from interrupt handler) 515 */ 516 static void atmel_rx_chars(struct uart_port *port) 517 { 518 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 519 unsigned int status, ch; 520 521 status = UART_GET_CSR(port); 522 while (status & ATMEL_US_RXRDY) { 523 ch = UART_GET_CHAR(port); 524 525 /* 526 * note that the error handling code is 527 * out of the main execution path 528 */ 529 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 530 | ATMEL_US_OVRE | ATMEL_US_RXBRK) 531 || atmel_port->break_active)) { 532 533 /* clear error */ 534 UART_PUT_CR(port, ATMEL_US_RSTSTA); 535 536 if (status & ATMEL_US_RXBRK 537 && !atmel_port->break_active) { 538 atmel_port->break_active = 1; 539 UART_PUT_IER(port, ATMEL_US_RXBRK); 540 } else { 541 /* 542 * This is either the end-of-break 543 * condition or we've received at 544 * least one character without RXBRK 545 * being set. In both cases, the next 546 * RXBRK will indicate start-of-break. 547 */ 548 UART_PUT_IDR(port, ATMEL_US_RXBRK); 549 status &= ~ATMEL_US_RXBRK; 550 atmel_port->break_active = 0; 551 } 552 } 553 554 atmel_buffer_rx_char(port, status, ch); 555 status = UART_GET_CSR(port); 556 } 557 558 tasklet_schedule(&atmel_port->tasklet); 559 } 560 561 /* 562 * Transmit characters (called from tasklet with TXRDY interrupt 563 * disabled) 564 */ 565 static void atmel_tx_chars(struct uart_port *port) 566 { 567 struct circ_buf *xmit = &port->state->xmit; 568 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 569 570 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) { 571 UART_PUT_CHAR(port, port->x_char); 572 port->icount.tx++; 573 port->x_char = 0; 574 } 575 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 576 return; 577 578 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) { 579 UART_PUT_CHAR(port, xmit->buf[xmit->tail]); 580 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 581 port->icount.tx++; 582 if (uart_circ_empty(xmit)) 583 break; 584 } 585 586 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 587 uart_write_wakeup(port); 588 589 if (!uart_circ_empty(xmit)) 590 /* Enable interrupts */ 591 UART_PUT_IER(port, atmel_port->tx_done_mask); 592 } 593 594 static void atmel_complete_tx_dma(void *arg) 595 { 596 struct atmel_uart_port *atmel_port = arg; 597 struct uart_port *port = &atmel_port->uart; 598 struct circ_buf *xmit = &port->state->xmit; 599 struct dma_chan *chan = atmel_port->chan_tx; 600 unsigned long flags; 601 602 spin_lock_irqsave(&port->lock, flags); 603 604 if (chan) 605 dmaengine_terminate_all(chan); 606 xmit->tail += sg_dma_len(&atmel_port->sg_tx); 607 xmit->tail &= UART_XMIT_SIZE - 1; 608 609 port->icount.tx += sg_dma_len(&atmel_port->sg_tx); 610 611 spin_lock_irq(&atmel_port->lock_tx); 612 async_tx_ack(atmel_port->desc_tx); 613 atmel_port->cookie_tx = -EINVAL; 614 atmel_port->desc_tx = NULL; 615 spin_unlock_irq(&atmel_port->lock_tx); 616 617 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 618 uart_write_wakeup(port); 619 620 /* Do we really need this? */ 621 if (!uart_circ_empty(xmit)) 622 tasklet_schedule(&atmel_port->tasklet); 623 624 spin_unlock_irqrestore(&port->lock, flags); 625 } 626 627 static void atmel_release_tx_dma(struct uart_port *port) 628 { 629 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 630 struct dma_chan *chan = atmel_port->chan_tx; 631 632 if (chan) { 633 dmaengine_terminate_all(chan); 634 dma_release_channel(chan); 635 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, 636 DMA_MEM_TO_DEV); 637 } 638 639 atmel_port->desc_tx = NULL; 640 atmel_port->chan_tx = NULL; 641 atmel_port->cookie_tx = -EINVAL; 642 } 643 644 /* 645 * Called from tasklet with TXRDY interrupt is disabled. 646 */ 647 static void atmel_tx_dma(struct uart_port *port) 648 { 649 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 650 struct circ_buf *xmit = &port->state->xmit; 651 struct dma_chan *chan = atmel_port->chan_tx; 652 struct dma_async_tx_descriptor *desc; 653 struct scatterlist *sg = &atmel_port->sg_tx; 654 655 /* Make sure we have an idle channel */ 656 if (atmel_port->desc_tx != NULL) 657 return; 658 659 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 660 /* 661 * DMA is idle now. 662 * Port xmit buffer is already mapped, 663 * and it is one page... Just adjust 664 * offsets and lengths. Since it is a circular buffer, 665 * we have to transmit till the end, and then the rest. 666 * Take the port lock to get a 667 * consistent xmit buffer state. 668 */ 669 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 670 sg_dma_address(sg) = (sg_dma_address(sg) & 671 ~(UART_XMIT_SIZE - 1)) 672 + sg->offset; 673 sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head, 674 xmit->tail, 675 UART_XMIT_SIZE); 676 BUG_ON(!sg_dma_len(sg)); 677 678 desc = dmaengine_prep_slave_sg(chan, 679 sg, 680 1, 681 DMA_MEM_TO_DEV, 682 DMA_PREP_INTERRUPT | 683 DMA_CTRL_ACK); 684 if (!desc) { 685 dev_err(port->dev, "Failed to send via dma!\n"); 686 return; 687 } 688 689 dma_sync_sg_for_device(port->dev, sg, 1, DMA_MEM_TO_DEV); 690 691 atmel_port->desc_tx = desc; 692 desc->callback = atmel_complete_tx_dma; 693 desc->callback_param = atmel_port; 694 atmel_port->cookie_tx = dmaengine_submit(desc); 695 696 } else { 697 if (atmel_port->rs485.flags & SER_RS485_ENABLED) { 698 /* DMA done, stop TX, start RX for RS485 */ 699 atmel_start_rx(port); 700 } 701 } 702 703 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 704 uart_write_wakeup(port); 705 } 706 707 static int atmel_prepare_tx_dma(struct uart_port *port) 708 { 709 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 710 dma_cap_mask_t mask; 711 struct dma_slave_config config; 712 int ret, nent; 713 714 dma_cap_zero(mask); 715 dma_cap_set(DMA_SLAVE, mask); 716 717 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx"); 718 if (atmel_port->chan_tx == NULL) 719 goto chan_err; 720 dev_info(port->dev, "using %s for tx DMA transfers\n", 721 dma_chan_name(atmel_port->chan_tx)); 722 723 spin_lock_init(&atmel_port->lock_tx); 724 sg_init_table(&atmel_port->sg_tx, 1); 725 /* UART circular tx buffer is an aligned page. */ 726 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); 727 sg_set_page(&atmel_port->sg_tx, 728 virt_to_page(port->state->xmit.buf), 729 UART_XMIT_SIZE, 730 (int)port->state->xmit.buf & ~PAGE_MASK); 731 nent = dma_map_sg(port->dev, 732 &atmel_port->sg_tx, 733 1, 734 DMA_MEM_TO_DEV); 735 736 if (!nent) { 737 dev_dbg(port->dev, "need to release resource of dma\n"); 738 goto chan_err; 739 } else { 740 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 741 sg_dma_len(&atmel_port->sg_tx), 742 port->state->xmit.buf, 743 sg_dma_address(&atmel_port->sg_tx)); 744 } 745 746 /* Configure the slave DMA */ 747 memset(&config, 0, sizeof(config)); 748 config.direction = DMA_MEM_TO_DEV; 749 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 750 config.dst_addr = port->mapbase + ATMEL_US_THR; 751 752 ret = dmaengine_device_control(atmel_port->chan_tx, 753 DMA_SLAVE_CONFIG, 754 (unsigned long)&config); 755 if (ret) { 756 dev_err(port->dev, "DMA tx slave configuration failed\n"); 757 goto chan_err; 758 } 759 760 return 0; 761 762 chan_err: 763 dev_err(port->dev, "TX channel not available, switch to pio\n"); 764 atmel_port->use_dma_tx = 0; 765 if (atmel_port->chan_tx) 766 atmel_release_tx_dma(port); 767 return -EINVAL; 768 } 769 770 static void atmel_flip_buffer_rx_dma(struct uart_port *port, 771 char *buf, size_t count) 772 { 773 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 774 struct tty_port *tport = &port->state->port; 775 776 dma_sync_sg_for_cpu(port->dev, 777 &atmel_port->sg_rx, 778 1, 779 DMA_DEV_TO_MEM); 780 781 tty_insert_flip_string(tport, buf, count); 782 783 dma_sync_sg_for_device(port->dev, 784 &atmel_port->sg_rx, 785 1, 786 DMA_DEV_TO_MEM); 787 /* 788 * Drop the lock here since it might end up calling 789 * uart_start(), which takes the lock. 790 */ 791 spin_unlock(&port->lock); 792 tty_flip_buffer_push(tport); 793 spin_lock(&port->lock); 794 } 795 796 static void atmel_complete_rx_dma(void *arg) 797 { 798 struct uart_port *port = arg; 799 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 800 801 tasklet_schedule(&atmel_port->tasklet); 802 } 803 804 static void atmel_release_rx_dma(struct uart_port *port) 805 { 806 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 807 struct dma_chan *chan = atmel_port->chan_rx; 808 809 if (chan) { 810 dmaengine_terminate_all(chan); 811 dma_release_channel(chan); 812 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, 813 DMA_DEV_TO_MEM); 814 } 815 816 atmel_port->desc_rx = NULL; 817 atmel_port->chan_rx = NULL; 818 atmel_port->cookie_rx = -EINVAL; 819 } 820 821 static void atmel_rx_from_dma(struct uart_port *port) 822 { 823 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 824 struct circ_buf *ring = &atmel_port->rx_ring; 825 struct dma_chan *chan = atmel_port->chan_rx; 826 struct dma_tx_state state; 827 enum dma_status dmastat; 828 size_t pending, count; 829 830 831 /* Reset the UART timeout early so that we don't miss one */ 832 UART_PUT_CR(port, ATMEL_US_STTTO); 833 dmastat = dmaengine_tx_status(chan, 834 atmel_port->cookie_rx, 835 &state); 836 /* Restart a new tasklet if DMA status is error */ 837 if (dmastat == DMA_ERROR) { 838 dev_dbg(port->dev, "Get residue error, restart tasklet\n"); 839 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 840 tasklet_schedule(&atmel_port->tasklet); 841 return; 842 } 843 /* current transfer size should no larger than dma buffer */ 844 pending = sg_dma_len(&atmel_port->sg_rx) - state.residue; 845 BUG_ON(pending > sg_dma_len(&atmel_port->sg_rx)); 846 847 /* 848 * This will take the chars we have so far, 849 * ring->head will record the transfer size, only new bytes come 850 * will insert into the framework. 851 */ 852 if (pending > ring->head) { 853 count = pending - ring->head; 854 855 atmel_flip_buffer_rx_dma(port, ring->buf + ring->head, count); 856 857 ring->head += count; 858 if (ring->head == sg_dma_len(&atmel_port->sg_rx)) 859 ring->head = 0; 860 861 port->icount.rx += count; 862 } 863 864 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 865 } 866 867 static int atmel_prepare_rx_dma(struct uart_port *port) 868 { 869 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 870 struct dma_async_tx_descriptor *desc; 871 dma_cap_mask_t mask; 872 struct dma_slave_config config; 873 struct circ_buf *ring; 874 int ret, nent; 875 876 ring = &atmel_port->rx_ring; 877 878 dma_cap_zero(mask); 879 dma_cap_set(DMA_CYCLIC, mask); 880 881 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx"); 882 if (atmel_port->chan_rx == NULL) 883 goto chan_err; 884 dev_info(port->dev, "using %s for rx DMA transfers\n", 885 dma_chan_name(atmel_port->chan_rx)); 886 887 spin_lock_init(&atmel_port->lock_rx); 888 sg_init_table(&atmel_port->sg_rx, 1); 889 /* UART circular rx buffer is an aligned page. */ 890 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); 891 sg_set_page(&atmel_port->sg_rx, 892 virt_to_page(ring->buf), 893 ATMEL_SERIAL_RINGSIZE, 894 (int)ring->buf & ~PAGE_MASK); 895 nent = dma_map_sg(port->dev, 896 &atmel_port->sg_rx, 897 1, 898 DMA_DEV_TO_MEM); 899 900 if (!nent) { 901 dev_dbg(port->dev, "need to release resource of dma\n"); 902 goto chan_err; 903 } else { 904 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 905 sg_dma_len(&atmel_port->sg_rx), 906 ring->buf, 907 sg_dma_address(&atmel_port->sg_rx)); 908 } 909 910 /* Configure the slave DMA */ 911 memset(&config, 0, sizeof(config)); 912 config.direction = DMA_DEV_TO_MEM; 913 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 914 config.src_addr = port->mapbase + ATMEL_US_RHR; 915 916 ret = dmaengine_device_control(atmel_port->chan_rx, 917 DMA_SLAVE_CONFIG, 918 (unsigned long)&config); 919 if (ret) { 920 dev_err(port->dev, "DMA rx slave configuration failed\n"); 921 goto chan_err; 922 } 923 /* 924 * Prepare a cyclic dma transfer, assign 2 descriptors, 925 * each one is half ring buffer size 926 */ 927 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, 928 sg_dma_address(&atmel_port->sg_rx), 929 sg_dma_len(&atmel_port->sg_rx), 930 sg_dma_len(&atmel_port->sg_rx)/2, 931 DMA_DEV_TO_MEM, 932 DMA_PREP_INTERRUPT); 933 desc->callback = atmel_complete_rx_dma; 934 desc->callback_param = port; 935 atmel_port->desc_rx = desc; 936 atmel_port->cookie_rx = dmaengine_submit(desc); 937 938 return 0; 939 940 chan_err: 941 dev_err(port->dev, "RX channel not available, switch to pio\n"); 942 atmel_port->use_dma_rx = 0; 943 if (atmel_port->chan_rx) 944 atmel_release_rx_dma(port); 945 return -EINVAL; 946 } 947 948 static void atmel_uart_timer_callback(unsigned long data) 949 { 950 struct uart_port *port = (void *)data; 951 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 952 953 tasklet_schedule(&atmel_port->tasklet); 954 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port)); 955 } 956 957 /* 958 * receive interrupt handler. 959 */ 960 static void 961 atmel_handle_receive(struct uart_port *port, unsigned int pending) 962 { 963 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 964 965 if (atmel_use_pdc_rx(port)) { 966 /* 967 * PDC receive. Just schedule the tasklet and let it 968 * figure out the details. 969 * 970 * TODO: We're not handling error flags correctly at 971 * the moment. 972 */ 973 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { 974 UART_PUT_IDR(port, (ATMEL_US_ENDRX 975 | ATMEL_US_TIMEOUT)); 976 tasklet_schedule(&atmel_port->tasklet); 977 } 978 979 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | 980 ATMEL_US_FRAME | ATMEL_US_PARE)) 981 atmel_pdc_rxerr(port, pending); 982 } 983 984 if (atmel_use_dma_rx(port)) { 985 if (pending & ATMEL_US_TIMEOUT) { 986 UART_PUT_IDR(port, ATMEL_US_TIMEOUT); 987 tasklet_schedule(&atmel_port->tasklet); 988 } 989 } 990 991 /* Interrupt receive */ 992 if (pending & ATMEL_US_RXRDY) 993 atmel_rx_chars(port); 994 else if (pending & ATMEL_US_RXBRK) { 995 /* 996 * End of break detected. If it came along with a 997 * character, atmel_rx_chars will handle it. 998 */ 999 UART_PUT_CR(port, ATMEL_US_RSTSTA); 1000 UART_PUT_IDR(port, ATMEL_US_RXBRK); 1001 atmel_port->break_active = 0; 1002 } 1003 } 1004 1005 /* 1006 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) 1007 */ 1008 static void 1009 atmel_handle_transmit(struct uart_port *port, unsigned int pending) 1010 { 1011 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1012 1013 if (pending & atmel_port->tx_done_mask) { 1014 /* Either PDC or interrupt transmission */ 1015 UART_PUT_IDR(port, atmel_port->tx_done_mask); 1016 tasklet_schedule(&atmel_port->tasklet); 1017 } 1018 } 1019 1020 /* 1021 * status flags interrupt handler. 1022 */ 1023 static void 1024 atmel_handle_status(struct uart_port *port, unsigned int pending, 1025 unsigned int status) 1026 { 1027 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1028 1029 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC 1030 | ATMEL_US_CTSIC)) { 1031 atmel_port->irq_status = status; 1032 tasklet_schedule(&atmel_port->tasklet); 1033 } 1034 } 1035 1036 /* 1037 * Interrupt handler 1038 */ 1039 static irqreturn_t atmel_interrupt(int irq, void *dev_id) 1040 { 1041 struct uart_port *port = dev_id; 1042 unsigned int status, pending, pass_counter = 0; 1043 1044 do { 1045 status = UART_GET_CSR(port); 1046 pending = status & UART_GET_IMR(port); 1047 if (!pending) 1048 break; 1049 1050 atmel_handle_receive(port, pending); 1051 atmel_handle_status(port, pending, status); 1052 atmel_handle_transmit(port, pending); 1053 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); 1054 1055 return pass_counter ? IRQ_HANDLED : IRQ_NONE; 1056 } 1057 1058 static void atmel_release_tx_pdc(struct uart_port *port) 1059 { 1060 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1061 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1062 1063 dma_unmap_single(port->dev, 1064 pdc->dma_addr, 1065 pdc->dma_size, 1066 DMA_TO_DEVICE); 1067 } 1068 1069 /* 1070 * Called from tasklet with ENDTX and TXBUFE interrupts disabled. 1071 */ 1072 static void atmel_tx_pdc(struct uart_port *port) 1073 { 1074 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1075 struct circ_buf *xmit = &port->state->xmit; 1076 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1077 int count; 1078 1079 /* nothing left to transmit? */ 1080 if (UART_GET_TCR(port)) 1081 return; 1082 1083 xmit->tail += pdc->ofs; 1084 xmit->tail &= UART_XMIT_SIZE - 1; 1085 1086 port->icount.tx += pdc->ofs; 1087 pdc->ofs = 0; 1088 1089 /* more to transmit - setup next transfer */ 1090 1091 /* disable PDC transmit */ 1092 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 1093 1094 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 1095 dma_sync_single_for_device(port->dev, 1096 pdc->dma_addr, 1097 pdc->dma_size, 1098 DMA_TO_DEVICE); 1099 1100 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1101 pdc->ofs = count; 1102 1103 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); 1104 UART_PUT_TCR(port, count); 1105 /* re-enable PDC transmit */ 1106 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 1107 /* Enable interrupts */ 1108 UART_PUT_IER(port, atmel_port->tx_done_mask); 1109 } else { 1110 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && 1111 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) { 1112 /* DMA done, stop TX, start RX for RS485 */ 1113 atmel_start_rx(port); 1114 } 1115 } 1116 1117 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1118 uart_write_wakeup(port); 1119 } 1120 1121 static int atmel_prepare_tx_pdc(struct uart_port *port) 1122 { 1123 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1124 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1125 struct circ_buf *xmit = &port->state->xmit; 1126 1127 pdc->buf = xmit->buf; 1128 pdc->dma_addr = dma_map_single(port->dev, 1129 pdc->buf, 1130 UART_XMIT_SIZE, 1131 DMA_TO_DEVICE); 1132 pdc->dma_size = UART_XMIT_SIZE; 1133 pdc->ofs = 0; 1134 1135 return 0; 1136 } 1137 1138 static void atmel_rx_from_ring(struct uart_port *port) 1139 { 1140 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1141 struct circ_buf *ring = &atmel_port->rx_ring; 1142 unsigned int flg; 1143 unsigned int status; 1144 1145 while (ring->head != ring->tail) { 1146 struct atmel_uart_char c; 1147 1148 /* Make sure c is loaded after head. */ 1149 smp_rmb(); 1150 1151 c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; 1152 1153 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 1154 1155 port->icount.rx++; 1156 status = c.status; 1157 flg = TTY_NORMAL; 1158 1159 /* 1160 * note that the error handling code is 1161 * out of the main execution path 1162 */ 1163 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 1164 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { 1165 if (status & ATMEL_US_RXBRK) { 1166 /* ignore side-effect */ 1167 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 1168 1169 port->icount.brk++; 1170 if (uart_handle_break(port)) 1171 continue; 1172 } 1173 if (status & ATMEL_US_PARE) 1174 port->icount.parity++; 1175 if (status & ATMEL_US_FRAME) 1176 port->icount.frame++; 1177 if (status & ATMEL_US_OVRE) 1178 port->icount.overrun++; 1179 1180 status &= port->read_status_mask; 1181 1182 if (status & ATMEL_US_RXBRK) 1183 flg = TTY_BREAK; 1184 else if (status & ATMEL_US_PARE) 1185 flg = TTY_PARITY; 1186 else if (status & ATMEL_US_FRAME) 1187 flg = TTY_FRAME; 1188 } 1189 1190 1191 if (uart_handle_sysrq_char(port, c.ch)) 1192 continue; 1193 1194 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); 1195 } 1196 1197 /* 1198 * Drop the lock here since it might end up calling 1199 * uart_start(), which takes the lock. 1200 */ 1201 spin_unlock(&port->lock); 1202 tty_flip_buffer_push(&port->state->port); 1203 spin_lock(&port->lock); 1204 } 1205 1206 static void atmel_release_rx_pdc(struct uart_port *port) 1207 { 1208 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1209 int i; 1210 1211 for (i = 0; i < 2; i++) { 1212 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1213 1214 dma_unmap_single(port->dev, 1215 pdc->dma_addr, 1216 pdc->dma_size, 1217 DMA_FROM_DEVICE); 1218 kfree(pdc->buf); 1219 } 1220 } 1221 1222 static void atmel_rx_from_pdc(struct uart_port *port) 1223 { 1224 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1225 struct tty_port *tport = &port->state->port; 1226 struct atmel_dma_buffer *pdc; 1227 int rx_idx = atmel_port->pdc_rx_idx; 1228 unsigned int head; 1229 unsigned int tail; 1230 unsigned int count; 1231 1232 do { 1233 /* Reset the UART timeout early so that we don't miss one */ 1234 UART_PUT_CR(port, ATMEL_US_STTTO); 1235 1236 pdc = &atmel_port->pdc_rx[rx_idx]; 1237 head = UART_GET_RPR(port) - pdc->dma_addr; 1238 tail = pdc->ofs; 1239 1240 /* If the PDC has switched buffers, RPR won't contain 1241 * any address within the current buffer. Since head 1242 * is unsigned, we just need a one-way comparison to 1243 * find out. 1244 * 1245 * In this case, we just need to consume the entire 1246 * buffer and resubmit it for DMA. This will clear the 1247 * ENDRX bit as well, so that we can safely re-enable 1248 * all interrupts below. 1249 */ 1250 head = min(head, pdc->dma_size); 1251 1252 if (likely(head != tail)) { 1253 dma_sync_single_for_cpu(port->dev, pdc->dma_addr, 1254 pdc->dma_size, DMA_FROM_DEVICE); 1255 1256 /* 1257 * head will only wrap around when we recycle 1258 * the DMA buffer, and when that happens, we 1259 * explicitly set tail to 0. So head will 1260 * always be greater than tail. 1261 */ 1262 count = head - tail; 1263 1264 tty_insert_flip_string(tport, pdc->buf + pdc->ofs, 1265 count); 1266 1267 dma_sync_single_for_device(port->dev, pdc->dma_addr, 1268 pdc->dma_size, DMA_FROM_DEVICE); 1269 1270 port->icount.rx += count; 1271 pdc->ofs = head; 1272 } 1273 1274 /* 1275 * If the current buffer is full, we need to check if 1276 * the next one contains any additional data. 1277 */ 1278 if (head >= pdc->dma_size) { 1279 pdc->ofs = 0; 1280 UART_PUT_RNPR(port, pdc->dma_addr); 1281 UART_PUT_RNCR(port, pdc->dma_size); 1282 1283 rx_idx = !rx_idx; 1284 atmel_port->pdc_rx_idx = rx_idx; 1285 } 1286 } while (head >= pdc->dma_size); 1287 1288 /* 1289 * Drop the lock here since it might end up calling 1290 * uart_start(), which takes the lock. 1291 */ 1292 spin_unlock(&port->lock); 1293 tty_flip_buffer_push(tport); 1294 spin_lock(&port->lock); 1295 1296 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1297 } 1298 1299 static int atmel_prepare_rx_pdc(struct uart_port *port) 1300 { 1301 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1302 int i; 1303 1304 for (i = 0; i < 2; i++) { 1305 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1306 1307 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); 1308 if (pdc->buf == NULL) { 1309 if (i != 0) { 1310 dma_unmap_single(port->dev, 1311 atmel_port->pdc_rx[0].dma_addr, 1312 PDC_BUFFER_SIZE, 1313 DMA_FROM_DEVICE); 1314 kfree(atmel_port->pdc_rx[0].buf); 1315 } 1316 atmel_port->use_pdc_rx = 0; 1317 return -ENOMEM; 1318 } 1319 pdc->dma_addr = dma_map_single(port->dev, 1320 pdc->buf, 1321 PDC_BUFFER_SIZE, 1322 DMA_FROM_DEVICE); 1323 pdc->dma_size = PDC_BUFFER_SIZE; 1324 pdc->ofs = 0; 1325 } 1326 1327 atmel_port->pdc_rx_idx = 0; 1328 1329 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); 1330 UART_PUT_RCR(port, PDC_BUFFER_SIZE); 1331 1332 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); 1333 UART_PUT_RNCR(port, PDC_BUFFER_SIZE); 1334 1335 return 0; 1336 } 1337 1338 /* 1339 * tasklet handling tty stuff outside the interrupt handler. 1340 */ 1341 static void atmel_tasklet_func(unsigned long data) 1342 { 1343 struct uart_port *port = (struct uart_port *)data; 1344 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1345 unsigned int status; 1346 unsigned int status_change; 1347 1348 /* The interrupt handler does not take the lock */ 1349 spin_lock(&port->lock); 1350 1351 atmel_port->schedule_tx(port); 1352 1353 status = atmel_port->irq_status; 1354 status_change = status ^ atmel_port->irq_status_prev; 1355 1356 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR 1357 | ATMEL_US_DCD | ATMEL_US_CTS)) { 1358 /* TODO: All reads to CSR will clear these interrupts! */ 1359 if (status_change & ATMEL_US_RI) 1360 port->icount.rng++; 1361 if (status_change & ATMEL_US_DSR) 1362 port->icount.dsr++; 1363 if (status_change & ATMEL_US_DCD) 1364 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); 1365 if (status_change & ATMEL_US_CTS) 1366 uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); 1367 1368 wake_up_interruptible(&port->state->port.delta_msr_wait); 1369 1370 atmel_port->irq_status_prev = status; 1371 } 1372 1373 atmel_port->schedule_rx(port); 1374 1375 spin_unlock(&port->lock); 1376 } 1377 1378 static int atmel_init_property(struct atmel_uart_port *atmel_port, 1379 struct platform_device *pdev) 1380 { 1381 struct device_node *np = pdev->dev.of_node; 1382 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1383 1384 if (np) { 1385 /* DMA/PDC usage specification */ 1386 if (of_get_property(np, "atmel,use-dma-rx", NULL)) { 1387 if (of_get_property(np, "dmas", NULL)) { 1388 atmel_port->use_dma_rx = true; 1389 atmel_port->use_pdc_rx = false; 1390 } else { 1391 atmel_port->use_dma_rx = false; 1392 atmel_port->use_pdc_rx = true; 1393 } 1394 } else { 1395 atmel_port->use_dma_rx = false; 1396 atmel_port->use_pdc_rx = false; 1397 } 1398 1399 if (of_get_property(np, "atmel,use-dma-tx", NULL)) { 1400 if (of_get_property(np, "dmas", NULL)) { 1401 atmel_port->use_dma_tx = true; 1402 atmel_port->use_pdc_tx = false; 1403 } else { 1404 atmel_port->use_dma_tx = false; 1405 atmel_port->use_pdc_tx = true; 1406 } 1407 } else { 1408 atmel_port->use_dma_tx = false; 1409 atmel_port->use_pdc_tx = false; 1410 } 1411 1412 } else { 1413 atmel_port->use_pdc_rx = pdata->use_dma_rx; 1414 atmel_port->use_pdc_tx = pdata->use_dma_tx; 1415 atmel_port->use_dma_rx = false; 1416 atmel_port->use_dma_tx = false; 1417 } 1418 1419 return 0; 1420 } 1421 1422 static void atmel_init_rs485(struct atmel_uart_port *atmel_port, 1423 struct platform_device *pdev) 1424 { 1425 struct device_node *np = pdev->dev.of_node; 1426 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1427 1428 if (np) { 1429 u32 rs485_delay[2]; 1430 /* rs485 properties */ 1431 if (of_property_read_u32_array(np, "rs485-rts-delay", 1432 rs485_delay, 2) == 0) { 1433 struct serial_rs485 *rs485conf = &atmel_port->rs485; 1434 1435 rs485conf->delay_rts_before_send = rs485_delay[0]; 1436 rs485conf->delay_rts_after_send = rs485_delay[1]; 1437 rs485conf->flags = 0; 1438 1439 if (of_get_property(np, "rs485-rx-during-tx", NULL)) 1440 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1441 1442 if (of_get_property(np, "linux,rs485-enabled-at-boot-time", 1443 NULL)) 1444 rs485conf->flags |= SER_RS485_ENABLED; 1445 } 1446 } else { 1447 atmel_port->rs485 = pdata->rs485; 1448 } 1449 1450 } 1451 1452 static void atmel_set_ops(struct uart_port *port) 1453 { 1454 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1455 1456 if (atmel_use_dma_rx(port)) { 1457 atmel_port->prepare_rx = &atmel_prepare_rx_dma; 1458 atmel_port->schedule_rx = &atmel_rx_from_dma; 1459 atmel_port->release_rx = &atmel_release_rx_dma; 1460 } else if (atmel_use_pdc_rx(port)) { 1461 atmel_port->prepare_rx = &atmel_prepare_rx_pdc; 1462 atmel_port->schedule_rx = &atmel_rx_from_pdc; 1463 atmel_port->release_rx = &atmel_release_rx_pdc; 1464 } else { 1465 atmel_port->prepare_rx = NULL; 1466 atmel_port->schedule_rx = &atmel_rx_from_ring; 1467 atmel_port->release_rx = NULL; 1468 } 1469 1470 if (atmel_use_dma_tx(port)) { 1471 atmel_port->prepare_tx = &atmel_prepare_tx_dma; 1472 atmel_port->schedule_tx = &atmel_tx_dma; 1473 atmel_port->release_tx = &atmel_release_tx_dma; 1474 } else if (atmel_use_pdc_tx(port)) { 1475 atmel_port->prepare_tx = &atmel_prepare_tx_pdc; 1476 atmel_port->schedule_tx = &atmel_tx_pdc; 1477 atmel_port->release_tx = &atmel_release_tx_pdc; 1478 } else { 1479 atmel_port->prepare_tx = NULL; 1480 atmel_port->schedule_tx = &atmel_tx_chars; 1481 atmel_port->release_tx = NULL; 1482 } 1483 } 1484 1485 /* 1486 * Get ip name usart or uart 1487 */ 1488 static void atmel_get_ip_name(struct uart_port *port) 1489 { 1490 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1491 int name = UART_GET_IP_NAME(port); 1492 u32 version; 1493 int usart, uart; 1494 /* usart and uart ascii */ 1495 usart = 0x55534152; 1496 uart = 0x44424755; 1497 1498 atmel_port->is_usart = false; 1499 1500 if (name == usart) { 1501 dev_dbg(port->dev, "This is usart\n"); 1502 atmel_port->is_usart = true; 1503 } else if (name == uart) { 1504 dev_dbg(port->dev, "This is uart\n"); 1505 atmel_port->is_usart = false; 1506 } else { 1507 /* fallback for older SoCs: use version field */ 1508 version = UART_GET_IP_VERSION(port); 1509 switch (version) { 1510 case 0x302: 1511 case 0x10213: 1512 dev_dbg(port->dev, "This version is usart\n"); 1513 atmel_port->is_usart = true; 1514 break; 1515 case 0x203: 1516 case 0x10202: 1517 dev_dbg(port->dev, "This version is uart\n"); 1518 atmel_port->is_usart = false; 1519 break; 1520 default: 1521 dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); 1522 } 1523 } 1524 } 1525 1526 /* 1527 * Perform initialization and enable port for reception 1528 */ 1529 static int atmel_startup(struct uart_port *port) 1530 { 1531 struct platform_device *pdev = to_platform_device(port->dev); 1532 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1533 struct tty_struct *tty = port->state->port.tty; 1534 int retval; 1535 1536 /* 1537 * Ensure that no interrupts are enabled otherwise when 1538 * request_irq() is called we could get stuck trying to 1539 * handle an unexpected interrupt 1540 */ 1541 UART_PUT_IDR(port, -1); 1542 1543 /* 1544 * Allocate the IRQ 1545 */ 1546 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, 1547 tty ? tty->name : "atmel_serial", port); 1548 if (retval) { 1549 dev_err(port->dev, "atmel_startup - Can't get irq\n"); 1550 return retval; 1551 } 1552 1553 /* 1554 * Initialize DMA (if necessary) 1555 */ 1556 atmel_init_property(atmel_port, pdev); 1557 1558 if (atmel_port->prepare_rx) { 1559 retval = atmel_port->prepare_rx(port); 1560 if (retval < 0) 1561 atmel_set_ops(port); 1562 } 1563 1564 if (atmel_port->prepare_tx) { 1565 retval = atmel_port->prepare_tx(port); 1566 if (retval < 0) 1567 atmel_set_ops(port); 1568 } 1569 1570 /* Save current CSR for comparison in atmel_tasklet_func() */ 1571 atmel_port->irq_status_prev = UART_GET_CSR(port); 1572 atmel_port->irq_status = atmel_port->irq_status_prev; 1573 1574 /* 1575 * Finally, enable the serial port 1576 */ 1577 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1578 /* enable xmit & rcvr */ 1579 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 1580 1581 setup_timer(&atmel_port->uart_timer, 1582 atmel_uart_timer_callback, 1583 (unsigned long)port); 1584 1585 if (atmel_use_pdc_rx(port)) { 1586 /* set UART timeout */ 1587 if (!atmel_port->is_usart) { 1588 mod_timer(&atmel_port->uart_timer, 1589 jiffies + uart_poll_timeout(port)); 1590 /* set USART timeout */ 1591 } else { 1592 UART_PUT_RTOR(port, PDC_RX_TIMEOUT); 1593 UART_PUT_CR(port, ATMEL_US_STTTO); 1594 1595 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1596 } 1597 /* enable PDC controller */ 1598 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); 1599 } else if (atmel_use_dma_rx(port)) { 1600 /* set UART timeout */ 1601 if (!atmel_port->is_usart) { 1602 mod_timer(&atmel_port->uart_timer, 1603 jiffies + uart_poll_timeout(port)); 1604 /* set USART timeout */ 1605 } else { 1606 UART_PUT_RTOR(port, PDC_RX_TIMEOUT); 1607 UART_PUT_CR(port, ATMEL_US_STTTO); 1608 1609 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 1610 } 1611 } else { 1612 /* enable receive only */ 1613 UART_PUT_IER(port, ATMEL_US_RXRDY); 1614 } 1615 1616 return 0; 1617 } 1618 1619 /* 1620 * Disable the port 1621 */ 1622 static void atmel_shutdown(struct uart_port *port) 1623 { 1624 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1625 1626 /* 1627 * Prevent any tasklets being scheduled during 1628 * cleanup 1629 */ 1630 del_timer_sync(&atmel_port->uart_timer); 1631 1632 /* 1633 * Clear out any scheduled tasklets before 1634 * we destroy the buffers 1635 */ 1636 tasklet_kill(&atmel_port->tasklet); 1637 1638 /* 1639 * Ensure everything is stopped and 1640 * disable all interrupts, port and break condition. 1641 */ 1642 atmel_stop_rx(port); 1643 atmel_stop_tx(port); 1644 1645 UART_PUT_CR(port, ATMEL_US_RSTSTA); 1646 UART_PUT_IDR(port, -1); 1647 1648 1649 /* 1650 * Shut-down the DMA. 1651 */ 1652 if (atmel_port->release_rx) 1653 atmel_port->release_rx(port); 1654 if (atmel_port->release_tx) 1655 atmel_port->release_tx(port); 1656 1657 /* 1658 * Reset ring buffer pointers 1659 */ 1660 atmel_port->rx_ring.head = 0; 1661 atmel_port->rx_ring.tail = 0; 1662 1663 /* 1664 * Free the interrupt 1665 */ 1666 free_irq(port->irq, port); 1667 } 1668 1669 /* 1670 * Flush any TX data submitted for DMA. Called when the TX circular 1671 * buffer is reset. 1672 */ 1673 static void atmel_flush_buffer(struct uart_port *port) 1674 { 1675 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1676 1677 if (atmel_use_pdc_tx(port)) { 1678 UART_PUT_TCR(port, 0); 1679 atmel_port->pdc_tx.ofs = 0; 1680 } 1681 } 1682 1683 /* 1684 * Power / Clock management. 1685 */ 1686 static void atmel_serial_pm(struct uart_port *port, unsigned int state, 1687 unsigned int oldstate) 1688 { 1689 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1690 1691 switch (state) { 1692 case 0: 1693 /* 1694 * Enable the peripheral clock for this serial port. 1695 * This is called on uart_open() or a resume event. 1696 */ 1697 clk_prepare_enable(atmel_port->clk); 1698 1699 /* re-enable interrupts if we disabled some on suspend */ 1700 UART_PUT_IER(port, atmel_port->backup_imr); 1701 break; 1702 case 3: 1703 /* Back up the interrupt mask and disable all interrupts */ 1704 atmel_port->backup_imr = UART_GET_IMR(port); 1705 UART_PUT_IDR(port, -1); 1706 1707 /* 1708 * Disable the peripheral clock for this serial port. 1709 * This is called on uart_close() or a suspend event. 1710 */ 1711 clk_disable_unprepare(atmel_port->clk); 1712 break; 1713 default: 1714 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); 1715 } 1716 } 1717 1718 /* 1719 * Change the port parameters 1720 */ 1721 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, 1722 struct ktermios *old) 1723 { 1724 unsigned long flags; 1725 unsigned int mode, imr, quot, baud; 1726 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1727 1728 /* Get current mode register */ 1729 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL 1730 | ATMEL_US_NBSTOP | ATMEL_US_PAR 1731 | ATMEL_US_USMODE); 1732 1733 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1734 quot = uart_get_divisor(port, baud); 1735 1736 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ 1737 quot /= 8; 1738 mode |= ATMEL_US_USCLKS_MCK_DIV8; 1739 } 1740 1741 /* byte size */ 1742 switch (termios->c_cflag & CSIZE) { 1743 case CS5: 1744 mode |= ATMEL_US_CHRL_5; 1745 break; 1746 case CS6: 1747 mode |= ATMEL_US_CHRL_6; 1748 break; 1749 case CS7: 1750 mode |= ATMEL_US_CHRL_7; 1751 break; 1752 default: 1753 mode |= ATMEL_US_CHRL_8; 1754 break; 1755 } 1756 1757 /* stop bits */ 1758 if (termios->c_cflag & CSTOPB) 1759 mode |= ATMEL_US_NBSTOP_2; 1760 1761 /* parity */ 1762 if (termios->c_cflag & PARENB) { 1763 /* Mark or Space parity */ 1764 if (termios->c_cflag & CMSPAR) { 1765 if (termios->c_cflag & PARODD) 1766 mode |= ATMEL_US_PAR_MARK; 1767 else 1768 mode |= ATMEL_US_PAR_SPACE; 1769 } else if (termios->c_cflag & PARODD) 1770 mode |= ATMEL_US_PAR_ODD; 1771 else 1772 mode |= ATMEL_US_PAR_EVEN; 1773 } else 1774 mode |= ATMEL_US_PAR_NONE; 1775 1776 /* hardware handshake (RTS/CTS) */ 1777 if (termios->c_cflag & CRTSCTS) 1778 mode |= ATMEL_US_USMODE_HWHS; 1779 else 1780 mode |= ATMEL_US_USMODE_NORMAL; 1781 1782 spin_lock_irqsave(&port->lock, flags); 1783 1784 port->read_status_mask = ATMEL_US_OVRE; 1785 if (termios->c_iflag & INPCK) 1786 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 1787 if (termios->c_iflag & (BRKINT | PARMRK)) 1788 port->read_status_mask |= ATMEL_US_RXBRK; 1789 1790 if (atmel_use_pdc_rx(port)) 1791 /* need to enable error interrupts */ 1792 UART_PUT_IER(port, port->read_status_mask); 1793 1794 /* 1795 * Characters to ignore 1796 */ 1797 port->ignore_status_mask = 0; 1798 if (termios->c_iflag & IGNPAR) 1799 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 1800 if (termios->c_iflag & IGNBRK) { 1801 port->ignore_status_mask |= ATMEL_US_RXBRK; 1802 /* 1803 * If we're ignoring parity and break indicators, 1804 * ignore overruns too (for real raw support). 1805 */ 1806 if (termios->c_iflag & IGNPAR) 1807 port->ignore_status_mask |= ATMEL_US_OVRE; 1808 } 1809 /* TODO: Ignore all characters if CREAD is set.*/ 1810 1811 /* update the per-port timeout */ 1812 uart_update_timeout(port, termios->c_cflag, baud); 1813 1814 /* 1815 * save/disable interrupts. The tty layer will ensure that the 1816 * transmitter is empty if requested by the caller, so there's 1817 * no need to wait for it here. 1818 */ 1819 imr = UART_GET_IMR(port); 1820 UART_PUT_IDR(port, -1); 1821 1822 /* disable receiver and transmitter */ 1823 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); 1824 1825 /* Resetting serial mode to RS232 (0x0) */ 1826 mode &= ~ATMEL_US_USMODE; 1827 1828 if (atmel_port->rs485.flags & SER_RS485_ENABLED) { 1829 if ((atmel_port->rs485.delay_rts_after_send) > 0) 1830 UART_PUT_TTGR(port, 1831 atmel_port->rs485.delay_rts_after_send); 1832 mode |= ATMEL_US_USMODE_RS485; 1833 } 1834 1835 /* set the parity, stop bits and data size */ 1836 UART_PUT_MR(port, mode); 1837 1838 /* set the baud rate */ 1839 UART_PUT_BRGR(port, quot); 1840 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1841 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 1842 1843 /* restore interrupts */ 1844 UART_PUT_IER(port, imr); 1845 1846 /* CTS flow-control and modem-status interrupts */ 1847 if (UART_ENABLE_MS(port, termios->c_cflag)) 1848 port->ops->enable_ms(port); 1849 1850 spin_unlock_irqrestore(&port->lock, flags); 1851 } 1852 1853 static void atmel_set_ldisc(struct uart_port *port, int new) 1854 { 1855 if (new == N_PPS) { 1856 port->flags |= UPF_HARDPPS_CD; 1857 atmel_enable_ms(port); 1858 } else { 1859 port->flags &= ~UPF_HARDPPS_CD; 1860 } 1861 } 1862 1863 /* 1864 * Return string describing the specified port 1865 */ 1866 static const char *atmel_type(struct uart_port *port) 1867 { 1868 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; 1869 } 1870 1871 /* 1872 * Release the memory region(s) being used by 'port'. 1873 */ 1874 static void atmel_release_port(struct uart_port *port) 1875 { 1876 struct platform_device *pdev = to_platform_device(port->dev); 1877 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 1878 1879 release_mem_region(port->mapbase, size); 1880 1881 if (port->flags & UPF_IOREMAP) { 1882 iounmap(port->membase); 1883 port->membase = NULL; 1884 } 1885 } 1886 1887 /* 1888 * Request the memory region(s) being used by 'port'. 1889 */ 1890 static int atmel_request_port(struct uart_port *port) 1891 { 1892 struct platform_device *pdev = to_platform_device(port->dev); 1893 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 1894 1895 if (!request_mem_region(port->mapbase, size, "atmel_serial")) 1896 return -EBUSY; 1897 1898 if (port->flags & UPF_IOREMAP) { 1899 port->membase = ioremap(port->mapbase, size); 1900 if (port->membase == NULL) { 1901 release_mem_region(port->mapbase, size); 1902 return -ENOMEM; 1903 } 1904 } 1905 1906 return 0; 1907 } 1908 1909 /* 1910 * Configure/autoconfigure the port. 1911 */ 1912 static void atmel_config_port(struct uart_port *port, int flags) 1913 { 1914 if (flags & UART_CONFIG_TYPE) { 1915 port->type = PORT_ATMEL; 1916 atmel_request_port(port); 1917 } 1918 } 1919 1920 /* 1921 * Verify the new serial_struct (for TIOCSSERIAL). 1922 */ 1923 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) 1924 { 1925 int ret = 0; 1926 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) 1927 ret = -EINVAL; 1928 if (port->irq != ser->irq) 1929 ret = -EINVAL; 1930 if (ser->io_type != SERIAL_IO_MEM) 1931 ret = -EINVAL; 1932 if (port->uartclk / 16 != ser->baud_base) 1933 ret = -EINVAL; 1934 if ((void *)port->mapbase != ser->iomem_base) 1935 ret = -EINVAL; 1936 if (port->iobase != ser->port) 1937 ret = -EINVAL; 1938 if (ser->hub6 != 0) 1939 ret = -EINVAL; 1940 return ret; 1941 } 1942 1943 #ifdef CONFIG_CONSOLE_POLL 1944 static int atmel_poll_get_char(struct uart_port *port) 1945 { 1946 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY)) 1947 cpu_relax(); 1948 1949 return UART_GET_CHAR(port); 1950 } 1951 1952 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) 1953 { 1954 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) 1955 cpu_relax(); 1956 1957 UART_PUT_CHAR(port, ch); 1958 } 1959 #endif 1960 1961 static int 1962 atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg) 1963 { 1964 struct serial_rs485 rs485conf; 1965 1966 switch (cmd) { 1967 case TIOCSRS485: 1968 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg, 1969 sizeof(rs485conf))) 1970 return -EFAULT; 1971 1972 atmel_config_rs485(port, &rs485conf); 1973 break; 1974 1975 case TIOCGRS485: 1976 if (copy_to_user((struct serial_rs485 *) arg, 1977 &(to_atmel_uart_port(port)->rs485), 1978 sizeof(rs485conf))) 1979 return -EFAULT; 1980 break; 1981 1982 default: 1983 return -ENOIOCTLCMD; 1984 } 1985 return 0; 1986 } 1987 1988 1989 1990 static struct uart_ops atmel_pops = { 1991 .tx_empty = atmel_tx_empty, 1992 .set_mctrl = atmel_set_mctrl, 1993 .get_mctrl = atmel_get_mctrl, 1994 .stop_tx = atmel_stop_tx, 1995 .start_tx = atmel_start_tx, 1996 .stop_rx = atmel_stop_rx, 1997 .enable_ms = atmel_enable_ms, 1998 .break_ctl = atmel_break_ctl, 1999 .startup = atmel_startup, 2000 .shutdown = atmel_shutdown, 2001 .flush_buffer = atmel_flush_buffer, 2002 .set_termios = atmel_set_termios, 2003 .set_ldisc = atmel_set_ldisc, 2004 .type = atmel_type, 2005 .release_port = atmel_release_port, 2006 .request_port = atmel_request_port, 2007 .config_port = atmel_config_port, 2008 .verify_port = atmel_verify_port, 2009 .pm = atmel_serial_pm, 2010 .ioctl = atmel_ioctl, 2011 #ifdef CONFIG_CONSOLE_POLL 2012 .poll_get_char = atmel_poll_get_char, 2013 .poll_put_char = atmel_poll_put_char, 2014 #endif 2015 }; 2016 2017 /* 2018 * Configure the port from the platform device resource info. 2019 */ 2020 static int atmel_init_port(struct atmel_uart_port *atmel_port, 2021 struct platform_device *pdev) 2022 { 2023 int ret; 2024 struct uart_port *port = &atmel_port->uart; 2025 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2026 2027 if (!atmel_init_property(atmel_port, pdev)) 2028 atmel_set_ops(port); 2029 2030 atmel_init_rs485(atmel_port, pdev); 2031 2032 port->iotype = UPIO_MEM; 2033 port->flags = UPF_BOOT_AUTOCONF; 2034 port->ops = &atmel_pops; 2035 port->fifosize = 1; 2036 port->dev = &pdev->dev; 2037 port->mapbase = pdev->resource[0].start; 2038 port->irq = pdev->resource[1].start; 2039 2040 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, 2041 (unsigned long)port); 2042 2043 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); 2044 2045 if (pdata && pdata->regs) { 2046 /* Already mapped by setup code */ 2047 port->membase = pdata->regs; 2048 } else { 2049 port->flags |= UPF_IOREMAP; 2050 port->membase = NULL; 2051 } 2052 2053 /* for console, the clock could already be configured */ 2054 if (!atmel_port->clk) { 2055 atmel_port->clk = clk_get(&pdev->dev, "usart"); 2056 if (IS_ERR(atmel_port->clk)) { 2057 ret = PTR_ERR(atmel_port->clk); 2058 atmel_port->clk = NULL; 2059 return ret; 2060 } 2061 ret = clk_prepare_enable(atmel_port->clk); 2062 if (ret) { 2063 clk_put(atmel_port->clk); 2064 atmel_port->clk = NULL; 2065 return ret; 2066 } 2067 port->uartclk = clk_get_rate(atmel_port->clk); 2068 clk_disable_unprepare(atmel_port->clk); 2069 /* only enable clock when USART is in use */ 2070 } 2071 2072 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ 2073 if (atmel_port->rs485.flags & SER_RS485_ENABLED) 2074 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 2075 else if (atmel_use_pdc_tx(port)) { 2076 port->fifosize = PDC_BUFFER_SIZE; 2077 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; 2078 } else { 2079 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 2080 } 2081 2082 return 0; 2083 } 2084 2085 struct platform_device *atmel_default_console_device; /* the serial console device */ 2086 2087 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2088 static void atmel_console_putchar(struct uart_port *port, int ch) 2089 { 2090 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) 2091 cpu_relax(); 2092 UART_PUT_CHAR(port, ch); 2093 } 2094 2095 /* 2096 * Interrupts are disabled on entering 2097 */ 2098 static void atmel_console_write(struct console *co, const char *s, u_int count) 2099 { 2100 struct uart_port *port = &atmel_ports[co->index].uart; 2101 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2102 unsigned int status, imr; 2103 unsigned int pdc_tx; 2104 2105 /* 2106 * First, save IMR and then disable interrupts 2107 */ 2108 imr = UART_GET_IMR(port); 2109 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask); 2110 2111 /* Store PDC transmit status and disable it */ 2112 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN; 2113 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 2114 2115 uart_console_write(port, s, count, atmel_console_putchar); 2116 2117 /* 2118 * Finally, wait for transmitter to become empty 2119 * and restore IMR 2120 */ 2121 do { 2122 status = UART_GET_CSR(port); 2123 } while (!(status & ATMEL_US_TXRDY)); 2124 2125 /* Restore PDC transmit status */ 2126 if (pdc_tx) 2127 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 2128 2129 /* set interrupts back the way they were */ 2130 UART_PUT_IER(port, imr); 2131 } 2132 2133 /* 2134 * If the port was already initialised (eg, by a boot loader), 2135 * try to determine the current setup. 2136 */ 2137 static void __init atmel_console_get_options(struct uart_port *port, int *baud, 2138 int *parity, int *bits) 2139 { 2140 unsigned int mr, quot; 2141 2142 /* 2143 * If the baud rate generator isn't running, the port wasn't 2144 * initialized by the boot loader. 2145 */ 2146 quot = UART_GET_BRGR(port) & ATMEL_US_CD; 2147 if (!quot) 2148 return; 2149 2150 mr = UART_GET_MR(port) & ATMEL_US_CHRL; 2151 if (mr == ATMEL_US_CHRL_8) 2152 *bits = 8; 2153 else 2154 *bits = 7; 2155 2156 mr = UART_GET_MR(port) & ATMEL_US_PAR; 2157 if (mr == ATMEL_US_PAR_EVEN) 2158 *parity = 'e'; 2159 else if (mr == ATMEL_US_PAR_ODD) 2160 *parity = 'o'; 2161 2162 /* 2163 * The serial core only rounds down when matching this to a 2164 * supported baud rate. Make sure we don't end up slightly 2165 * lower than one of those, as it would make us fall through 2166 * to a much lower baud rate than we really want. 2167 */ 2168 *baud = port->uartclk / (16 * (quot - 1)); 2169 } 2170 2171 static int __init atmel_console_setup(struct console *co, char *options) 2172 { 2173 int ret; 2174 struct uart_port *port = &atmel_ports[co->index].uart; 2175 int baud = 115200; 2176 int bits = 8; 2177 int parity = 'n'; 2178 int flow = 'n'; 2179 2180 if (port->membase == NULL) { 2181 /* Port not initialized yet - delay setup */ 2182 return -ENODEV; 2183 } 2184 2185 ret = clk_prepare_enable(atmel_ports[co->index].clk); 2186 if (ret) 2187 return ret; 2188 2189 UART_PUT_IDR(port, -1); 2190 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2191 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 2192 2193 if (options) 2194 uart_parse_options(options, &baud, &parity, &bits, &flow); 2195 else 2196 atmel_console_get_options(port, &baud, &parity, &bits); 2197 2198 return uart_set_options(port, co, baud, parity, bits, flow); 2199 } 2200 2201 static struct uart_driver atmel_uart; 2202 2203 static struct console atmel_console = { 2204 .name = ATMEL_DEVICENAME, 2205 .write = atmel_console_write, 2206 .device = uart_console_device, 2207 .setup = atmel_console_setup, 2208 .flags = CON_PRINTBUFFER, 2209 .index = -1, 2210 .data = &atmel_uart, 2211 }; 2212 2213 #define ATMEL_CONSOLE_DEVICE (&atmel_console) 2214 2215 /* 2216 * Early console initialization (before VM subsystem initialized). 2217 */ 2218 static int __init atmel_console_init(void) 2219 { 2220 int ret; 2221 if (atmel_default_console_device) { 2222 struct atmel_uart_data *pdata = 2223 dev_get_platdata(&atmel_default_console_device->dev); 2224 int id = pdata->num; 2225 struct atmel_uart_port *port = &atmel_ports[id]; 2226 2227 port->backup_imr = 0; 2228 port->uart.line = id; 2229 2230 add_preferred_console(ATMEL_DEVICENAME, id, NULL); 2231 ret = atmel_init_port(port, atmel_default_console_device); 2232 if (ret) 2233 return ret; 2234 register_console(&atmel_console); 2235 } 2236 2237 return 0; 2238 } 2239 2240 console_initcall(atmel_console_init); 2241 2242 /* 2243 * Late console initialization. 2244 */ 2245 static int __init atmel_late_console_init(void) 2246 { 2247 if (atmel_default_console_device 2248 && !(atmel_console.flags & CON_ENABLED)) 2249 register_console(&atmel_console); 2250 2251 return 0; 2252 } 2253 2254 core_initcall(atmel_late_console_init); 2255 2256 static inline bool atmel_is_console_port(struct uart_port *port) 2257 { 2258 return port->cons && port->cons->index == port->line; 2259 } 2260 2261 #else 2262 #define ATMEL_CONSOLE_DEVICE NULL 2263 2264 static inline bool atmel_is_console_port(struct uart_port *port) 2265 { 2266 return false; 2267 } 2268 #endif 2269 2270 static struct uart_driver atmel_uart = { 2271 .owner = THIS_MODULE, 2272 .driver_name = "atmel_serial", 2273 .dev_name = ATMEL_DEVICENAME, 2274 .major = SERIAL_ATMEL_MAJOR, 2275 .minor = MINOR_START, 2276 .nr = ATMEL_MAX_UART, 2277 .cons = ATMEL_CONSOLE_DEVICE, 2278 }; 2279 2280 #ifdef CONFIG_PM 2281 static bool atmel_serial_clk_will_stop(void) 2282 { 2283 #ifdef CONFIG_ARCH_AT91 2284 return at91_suspend_entering_slow_clock(); 2285 #else 2286 return false; 2287 #endif 2288 } 2289 2290 static int atmel_serial_suspend(struct platform_device *pdev, 2291 pm_message_t state) 2292 { 2293 struct uart_port *port = platform_get_drvdata(pdev); 2294 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2295 2296 if (atmel_is_console_port(port) && console_suspend_enabled) { 2297 /* Drain the TX shifter */ 2298 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) 2299 cpu_relax(); 2300 } 2301 2302 /* we can not wake up if we're running on slow clock */ 2303 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); 2304 if (atmel_serial_clk_will_stop()) 2305 device_set_wakeup_enable(&pdev->dev, 0); 2306 2307 uart_suspend_port(&atmel_uart, port); 2308 2309 return 0; 2310 } 2311 2312 static int atmel_serial_resume(struct platform_device *pdev) 2313 { 2314 struct uart_port *port = platform_get_drvdata(pdev); 2315 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2316 2317 uart_resume_port(&atmel_uart, port); 2318 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); 2319 2320 return 0; 2321 } 2322 #else 2323 #define atmel_serial_suspend NULL 2324 #define atmel_serial_resume NULL 2325 #endif 2326 2327 static int atmel_serial_probe(struct platform_device *pdev) 2328 { 2329 struct atmel_uart_port *port; 2330 struct device_node *np = pdev->dev.of_node; 2331 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2332 void *data; 2333 int ret = -ENODEV; 2334 2335 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); 2336 2337 if (np) 2338 ret = of_alias_get_id(np, "serial"); 2339 else 2340 if (pdata) 2341 ret = pdata->num; 2342 2343 if (ret < 0) 2344 /* port id not found in platform data nor device-tree aliases: 2345 * auto-enumerate it */ 2346 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); 2347 2348 if (ret >= ATMEL_MAX_UART) { 2349 ret = -ENODEV; 2350 goto err; 2351 } 2352 2353 if (test_and_set_bit(ret, atmel_ports_in_use)) { 2354 /* port already in use */ 2355 ret = -EBUSY; 2356 goto err; 2357 } 2358 2359 port = &atmel_ports[ret]; 2360 port->backup_imr = 0; 2361 port->uart.line = ret; 2362 port->rts_gpio = -EINVAL; /* Invalid, zero could be valid */ 2363 if (pdata) 2364 port->rts_gpio = pdata->rts_gpio; 2365 else if (np) 2366 port->rts_gpio = of_get_named_gpio(np, "rts-gpios", 0); 2367 2368 if (gpio_is_valid(port->rts_gpio)) { 2369 ret = devm_gpio_request(&pdev->dev, port->rts_gpio, "RTS"); 2370 if (ret) { 2371 dev_err(&pdev->dev, "error requesting RTS GPIO\n"); 2372 goto err; 2373 } 2374 /* Default to 1 as RTS is active low */ 2375 ret = gpio_direction_output(port->rts_gpio, 1); 2376 if (ret) { 2377 dev_err(&pdev->dev, "error setting up RTS GPIO\n"); 2378 goto err; 2379 } 2380 } 2381 2382 ret = atmel_init_port(port, pdev); 2383 if (ret) 2384 goto err; 2385 2386 if (!atmel_use_pdc_rx(&port->uart)) { 2387 ret = -ENOMEM; 2388 data = kmalloc(sizeof(struct atmel_uart_char) 2389 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); 2390 if (!data) 2391 goto err_alloc_ring; 2392 port->rx_ring.buf = data; 2393 } 2394 2395 ret = uart_add_one_port(&atmel_uart, &port->uart); 2396 if (ret) 2397 goto err_add_port; 2398 2399 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2400 if (atmel_is_console_port(&port->uart) 2401 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { 2402 /* 2403 * The serial core enabled the clock for us, so undo 2404 * the clk_prepare_enable() in atmel_console_setup() 2405 */ 2406 clk_disable_unprepare(port->clk); 2407 } 2408 #endif 2409 2410 device_init_wakeup(&pdev->dev, 1); 2411 platform_set_drvdata(pdev, port); 2412 2413 if (port->rs485.flags & SER_RS485_ENABLED) { 2414 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL); 2415 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN); 2416 } 2417 2418 /* 2419 * Get port name of usart or uart 2420 */ 2421 atmel_get_ip_name(&port->uart); 2422 2423 return 0; 2424 2425 err_add_port: 2426 kfree(port->rx_ring.buf); 2427 port->rx_ring.buf = NULL; 2428 err_alloc_ring: 2429 if (!atmel_is_console_port(&port->uart)) { 2430 clk_put(port->clk); 2431 port->clk = NULL; 2432 } 2433 err: 2434 return ret; 2435 } 2436 2437 static int atmel_serial_remove(struct platform_device *pdev) 2438 { 2439 struct uart_port *port = platform_get_drvdata(pdev); 2440 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2441 int ret = 0; 2442 2443 tasklet_kill(&atmel_port->tasklet); 2444 2445 device_init_wakeup(&pdev->dev, 0); 2446 2447 ret = uart_remove_one_port(&atmel_uart, port); 2448 2449 kfree(atmel_port->rx_ring.buf); 2450 2451 /* "port" is allocated statically, so we shouldn't free it */ 2452 2453 clear_bit(port->line, atmel_ports_in_use); 2454 2455 clk_put(atmel_port->clk); 2456 2457 return ret; 2458 } 2459 2460 static struct platform_driver atmel_serial_driver = { 2461 .probe = atmel_serial_probe, 2462 .remove = atmel_serial_remove, 2463 .suspend = atmel_serial_suspend, 2464 .resume = atmel_serial_resume, 2465 .driver = { 2466 .name = "atmel_usart", 2467 .owner = THIS_MODULE, 2468 .of_match_table = of_match_ptr(atmel_serial_dt_ids), 2469 }, 2470 }; 2471 2472 static int __init atmel_serial_init(void) 2473 { 2474 int ret; 2475 2476 ret = uart_register_driver(&atmel_uart); 2477 if (ret) 2478 return ret; 2479 2480 ret = platform_driver_register(&atmel_serial_driver); 2481 if (ret) 2482 uart_unregister_driver(&atmel_uart); 2483 2484 return ret; 2485 } 2486 2487 static void __exit atmel_serial_exit(void) 2488 { 2489 platform_driver_unregister(&atmel_serial_driver); 2490 uart_unregister_driver(&atmel_uart); 2491 } 2492 2493 module_init(atmel_serial_init); 2494 module_exit(atmel_serial_exit); 2495 2496 MODULE_AUTHOR("Rick Bronson"); 2497 MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); 2498 MODULE_LICENSE("GPL"); 2499 MODULE_ALIAS("platform:atmel_usart"); 2500