1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Atmel AT91 Serial ports 4 * Copyright (C) 2003 Rick Bronson 5 * 6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. 7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 8 * 9 * DMA support added by Chip Coldwell. 10 */ 11 #include <linux/tty.h> 12 #include <linux/ioport.h> 13 #include <linux/slab.h> 14 #include <linux/init.h> 15 #include <linux/serial.h> 16 #include <linux/clk.h> 17 #include <linux/console.h> 18 #include <linux/sysrq.h> 19 #include <linux/tty_flip.h> 20 #include <linux/platform_device.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/dmaengine.h> 25 #include <linux/atmel_pdc.h> 26 #include <linux/uaccess.h> 27 #include <linux/platform_data/atmel.h> 28 #include <linux/timer.h> 29 #include <linux/err.h> 30 #include <linux/irq.h> 31 #include <linux/suspend.h> 32 #include <linux/mm.h> 33 #include <linux/io.h> 34 35 #include <asm/div64.h> 36 #include <asm/ioctls.h> 37 38 #define PDC_BUFFER_SIZE 512 39 /* Revisit: We should calculate this based on the actual port settings */ 40 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ 41 42 /* The minium number of data FIFOs should be able to contain */ 43 #define ATMEL_MIN_FIFO_SIZE 8 44 /* 45 * These two offsets are substracted from the RX FIFO size to define the RTS 46 * high and low thresholds 47 */ 48 #define ATMEL_RTS_HIGH_OFFSET 16 49 #define ATMEL_RTS_LOW_OFFSET 20 50 51 #include <linux/serial_core.h> 52 53 #include "serial_mctrl_gpio.h" 54 #include "atmel_serial.h" 55 56 static void atmel_start_rx(struct uart_port *port); 57 static void atmel_stop_rx(struct uart_port *port); 58 59 #ifdef CONFIG_SERIAL_ATMEL_TTYAT 60 61 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we 62 * should coexist with the 8250 driver, such as if we have an external 16C550 63 * UART. */ 64 #define SERIAL_ATMEL_MAJOR 204 65 #define MINOR_START 154 66 #define ATMEL_DEVICENAME "ttyAT" 67 68 #else 69 70 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port 71 * name, but it is legally reserved for the 8250 driver. */ 72 #define SERIAL_ATMEL_MAJOR TTY_MAJOR 73 #define MINOR_START 64 74 #define ATMEL_DEVICENAME "ttyS" 75 76 #endif 77 78 #define ATMEL_ISR_PASS_LIMIT 256 79 80 struct atmel_dma_buffer { 81 unsigned char *buf; 82 dma_addr_t dma_addr; 83 unsigned int dma_size; 84 unsigned int ofs; 85 }; 86 87 struct atmel_uart_char { 88 u16 status; 89 u16 ch; 90 }; 91 92 /* 93 * Be careful, the real size of the ring buffer is 94 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer 95 * can contain up to 1024 characters in PIO mode and up to 4096 characters in 96 * DMA mode. 97 */ 98 #define ATMEL_SERIAL_RINGSIZE 1024 99 100 /* 101 * at91: 6 USARTs and one DBGU port (SAM9260) 102 * samx7: 3 USARTs and 5 UARTs 103 */ 104 #define ATMEL_MAX_UART 8 105 106 /* 107 * We wrap our port structure around the generic uart_port. 108 */ 109 struct atmel_uart_port { 110 struct uart_port uart; /* uart */ 111 struct clk *clk; /* uart clock */ 112 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ 113 u32 backup_imr; /* IMR saved during suspend */ 114 int break_active; /* break being received */ 115 116 bool use_dma_rx; /* enable DMA receiver */ 117 bool use_pdc_rx; /* enable PDC receiver */ 118 short pdc_rx_idx; /* current PDC RX buffer */ 119 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ 120 121 bool use_dma_tx; /* enable DMA transmitter */ 122 bool use_pdc_tx; /* enable PDC transmitter */ 123 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ 124 125 spinlock_t lock_tx; /* port lock */ 126 spinlock_t lock_rx; /* port lock */ 127 struct dma_chan *chan_tx; 128 struct dma_chan *chan_rx; 129 struct dma_async_tx_descriptor *desc_tx; 130 struct dma_async_tx_descriptor *desc_rx; 131 dma_cookie_t cookie_tx; 132 dma_cookie_t cookie_rx; 133 struct scatterlist sg_tx; 134 struct scatterlist sg_rx; 135 struct tasklet_struct tasklet_rx; 136 struct tasklet_struct tasklet_tx; 137 atomic_t tasklet_shutdown; 138 unsigned int irq_status_prev; 139 unsigned int tx_len; 140 141 struct circ_buf rx_ring; 142 143 struct mctrl_gpios *gpios; 144 u32 backup_mode; /* MR saved during iso7816 operations */ 145 u32 backup_brgr; /* BRGR saved during iso7816 operations */ 146 unsigned int tx_done_mask; 147 u32 fifo_size; 148 u32 rts_high; 149 u32 rts_low; 150 bool ms_irq_enabled; 151 u32 rtor; /* address of receiver timeout register if it exists */ 152 bool has_frac_baudrate; 153 bool has_hw_timer; 154 struct timer_list uart_timer; 155 156 bool tx_stopped; 157 bool suspended; 158 unsigned int pending; 159 unsigned int pending_status; 160 spinlock_t lock_suspended; 161 162 bool hd_start_rx; /* can start RX during half-duplex operation */ 163 164 /* ISO7816 */ 165 unsigned int fidi_min; 166 unsigned int fidi_max; 167 168 #ifdef CONFIG_PM 169 struct { 170 u32 cr; 171 u32 mr; 172 u32 imr; 173 u32 brgr; 174 u32 rtor; 175 u32 ttgr; 176 u32 fmr; 177 u32 fimr; 178 } cache; 179 #endif 180 181 int (*prepare_rx)(struct uart_port *port); 182 int (*prepare_tx)(struct uart_port *port); 183 void (*schedule_rx)(struct uart_port *port); 184 void (*schedule_tx)(struct uart_port *port); 185 void (*release_rx)(struct uart_port *port); 186 void (*release_tx)(struct uart_port *port); 187 }; 188 189 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; 190 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); 191 192 #if defined(CONFIG_OF) 193 static const struct of_device_id atmel_serial_dt_ids[] = { 194 { .compatible = "atmel,at91rm9200-usart-serial" }, 195 { /* sentinel */ } 196 }; 197 #endif 198 199 static inline struct atmel_uart_port * 200 to_atmel_uart_port(struct uart_port *uart) 201 { 202 return container_of(uart, struct atmel_uart_port, uart); 203 } 204 205 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg) 206 { 207 return __raw_readl(port->membase + reg); 208 } 209 210 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value) 211 { 212 __raw_writel(value, port->membase + reg); 213 } 214 215 static inline u8 atmel_uart_read_char(struct uart_port *port) 216 { 217 return __raw_readb(port->membase + ATMEL_US_RHR); 218 } 219 220 static inline void atmel_uart_write_char(struct uart_port *port, u8 value) 221 { 222 __raw_writeb(value, port->membase + ATMEL_US_THR); 223 } 224 225 static inline int atmel_uart_is_half_duplex(struct uart_port *port) 226 { 227 return ((port->rs485.flags & SER_RS485_ENABLED) && 228 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) || 229 (port->iso7816.flags & SER_ISO7816_ENABLED); 230 } 231 232 #ifdef CONFIG_SERIAL_ATMEL_PDC 233 static bool atmel_use_pdc_rx(struct uart_port *port) 234 { 235 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 236 237 return atmel_port->use_pdc_rx; 238 } 239 240 static bool atmel_use_pdc_tx(struct uart_port *port) 241 { 242 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 243 244 return atmel_port->use_pdc_tx; 245 } 246 #else 247 static bool atmel_use_pdc_rx(struct uart_port *port) 248 { 249 return false; 250 } 251 252 static bool atmel_use_pdc_tx(struct uart_port *port) 253 { 254 return false; 255 } 256 #endif 257 258 static bool atmel_use_dma_tx(struct uart_port *port) 259 { 260 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 261 262 return atmel_port->use_dma_tx; 263 } 264 265 static bool atmel_use_dma_rx(struct uart_port *port) 266 { 267 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 268 269 return atmel_port->use_dma_rx; 270 } 271 272 static bool atmel_use_fifo(struct uart_port *port) 273 { 274 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 275 276 return atmel_port->fifo_size; 277 } 278 279 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port, 280 struct tasklet_struct *t) 281 { 282 if (!atomic_read(&atmel_port->tasklet_shutdown)) 283 tasklet_schedule(t); 284 } 285 286 /* Enable or disable the rs485 support */ 287 static int atmel_config_rs485(struct uart_port *port, 288 struct serial_rs485 *rs485conf) 289 { 290 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 291 unsigned int mode; 292 293 /* Disable interrupts */ 294 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); 295 296 mode = atmel_uart_readl(port, ATMEL_US_MR); 297 298 /* Resetting serial mode to RS232 (0x0) */ 299 mode &= ~ATMEL_US_USMODE; 300 301 port->rs485 = *rs485conf; 302 303 if (rs485conf->flags & SER_RS485_ENABLED) { 304 dev_dbg(port->dev, "Setting UART to RS485\n"); 305 if (port->rs485.flags & SER_RS485_RX_DURING_TX) 306 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 307 else 308 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 309 310 atmel_uart_writel(port, ATMEL_US_TTGR, 311 rs485conf->delay_rts_after_send); 312 mode |= ATMEL_US_USMODE_RS485; 313 } else { 314 dev_dbg(port->dev, "Setting UART to RS232\n"); 315 if (atmel_use_pdc_tx(port)) 316 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 317 ATMEL_US_TXBUFE; 318 else 319 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 320 } 321 atmel_uart_writel(port, ATMEL_US_MR, mode); 322 323 /* Enable interrupts */ 324 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 325 326 return 0; 327 } 328 329 static unsigned int atmel_calc_cd(struct uart_port *port, 330 struct serial_iso7816 *iso7816conf) 331 { 332 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 333 unsigned int cd; 334 u64 mck_rate; 335 336 mck_rate = (u64)clk_get_rate(atmel_port->clk); 337 do_div(mck_rate, iso7816conf->clk); 338 cd = mck_rate; 339 return cd; 340 } 341 342 static unsigned int atmel_calc_fidi(struct uart_port *port, 343 struct serial_iso7816 *iso7816conf) 344 { 345 u64 fidi = 0; 346 347 if (iso7816conf->sc_fi && iso7816conf->sc_di) { 348 fidi = (u64)iso7816conf->sc_fi; 349 do_div(fidi, iso7816conf->sc_di); 350 } 351 return (u32)fidi; 352 } 353 354 /* Enable or disable the iso7816 support */ 355 /* Called with interrupts disabled */ 356 static int atmel_config_iso7816(struct uart_port *port, 357 struct serial_iso7816 *iso7816conf) 358 { 359 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 360 unsigned int mode; 361 unsigned int cd, fidi; 362 int ret = 0; 363 364 /* Disable interrupts */ 365 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); 366 367 mode = atmel_uart_readl(port, ATMEL_US_MR); 368 369 if (iso7816conf->flags & SER_ISO7816_ENABLED) { 370 mode &= ~ATMEL_US_USMODE; 371 372 if (iso7816conf->tg > 255) { 373 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n"); 374 memset(iso7816conf, 0, sizeof(struct serial_iso7816)); 375 ret = -EINVAL; 376 goto err_out; 377 } 378 379 if ((iso7816conf->flags & SER_ISO7816_T_PARAM) 380 == SER_ISO7816_T(0)) { 381 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK; 382 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM) 383 == SER_ISO7816_T(1)) { 384 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK; 385 } else { 386 dev_err(port->dev, "ISO7816: Type not supported\n"); 387 memset(iso7816conf, 0, sizeof(struct serial_iso7816)); 388 ret = -EINVAL; 389 goto err_out; 390 } 391 392 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR); 393 394 /* select mck clock, and output */ 395 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO; 396 /* set parity for normal/inverse mode + max iterations */ 397 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3); 398 399 cd = atmel_calc_cd(port, iso7816conf); 400 fidi = atmel_calc_fidi(port, iso7816conf); 401 if (fidi == 0) { 402 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n"); 403 } else if (fidi < atmel_port->fidi_min 404 || fidi > atmel_port->fidi_max) { 405 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi); 406 memset(iso7816conf, 0, sizeof(struct serial_iso7816)); 407 ret = -EINVAL; 408 goto err_out; 409 } 410 411 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) { 412 /* port not yet in iso7816 mode: store configuration */ 413 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR); 414 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR); 415 } 416 417 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg); 418 atmel_uart_writel(port, ATMEL_US_BRGR, cd); 419 atmel_uart_writel(port, ATMEL_US_FIDI, fidi); 420 421 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN); 422 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION; 423 } else { 424 dev_dbg(port->dev, "Setting UART back to RS232\n"); 425 /* back to last RS232 settings */ 426 mode = atmel_port->backup_mode; 427 memset(iso7816conf, 0, sizeof(struct serial_iso7816)); 428 atmel_uart_writel(port, ATMEL_US_TTGR, 0); 429 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr); 430 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174); 431 432 if (atmel_use_pdc_tx(port)) 433 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 434 ATMEL_US_TXBUFE; 435 else 436 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 437 } 438 439 port->iso7816 = *iso7816conf; 440 441 atmel_uart_writel(port, ATMEL_US_MR, mode); 442 443 err_out: 444 /* Enable interrupts */ 445 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 446 447 return ret; 448 } 449 450 /* 451 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. 452 */ 453 static u_int atmel_tx_empty(struct uart_port *port) 454 { 455 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 456 457 if (atmel_port->tx_stopped) 458 return TIOCSER_TEMT; 459 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ? 460 TIOCSER_TEMT : 461 0; 462 } 463 464 /* 465 * Set state of the modem control output lines 466 */ 467 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) 468 { 469 unsigned int control = 0; 470 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR); 471 unsigned int rts_paused, rts_ready; 472 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 473 474 /* override mode to RS485 if needed, otherwise keep the current mode */ 475 if (port->rs485.flags & SER_RS485_ENABLED) { 476 atmel_uart_writel(port, ATMEL_US_TTGR, 477 port->rs485.delay_rts_after_send); 478 mode &= ~ATMEL_US_USMODE; 479 mode |= ATMEL_US_USMODE_RS485; 480 } 481 482 /* set the RTS line state according to the mode */ 483 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 484 /* force RTS line to high level */ 485 rts_paused = ATMEL_US_RTSEN; 486 487 /* give the control of the RTS line back to the hardware */ 488 rts_ready = ATMEL_US_RTSDIS; 489 } else { 490 /* force RTS line to high level */ 491 rts_paused = ATMEL_US_RTSDIS; 492 493 /* force RTS line to low level */ 494 rts_ready = ATMEL_US_RTSEN; 495 } 496 497 if (mctrl & TIOCM_RTS) 498 control |= rts_ready; 499 else 500 control |= rts_paused; 501 502 if (mctrl & TIOCM_DTR) 503 control |= ATMEL_US_DTREN; 504 else 505 control |= ATMEL_US_DTRDIS; 506 507 atmel_uart_writel(port, ATMEL_US_CR, control); 508 509 mctrl_gpio_set(atmel_port->gpios, mctrl); 510 511 /* Local loopback mode? */ 512 mode &= ~ATMEL_US_CHMODE; 513 if (mctrl & TIOCM_LOOP) 514 mode |= ATMEL_US_CHMODE_LOC_LOOP; 515 else 516 mode |= ATMEL_US_CHMODE_NORMAL; 517 518 atmel_uart_writel(port, ATMEL_US_MR, mode); 519 } 520 521 /* 522 * Get state of the modem control input lines 523 */ 524 static u_int atmel_get_mctrl(struct uart_port *port) 525 { 526 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 527 unsigned int ret = 0, status; 528 529 status = atmel_uart_readl(port, ATMEL_US_CSR); 530 531 /* 532 * The control signals are active low. 533 */ 534 if (!(status & ATMEL_US_DCD)) 535 ret |= TIOCM_CD; 536 if (!(status & ATMEL_US_CTS)) 537 ret |= TIOCM_CTS; 538 if (!(status & ATMEL_US_DSR)) 539 ret |= TIOCM_DSR; 540 if (!(status & ATMEL_US_RI)) 541 ret |= TIOCM_RI; 542 543 return mctrl_gpio_get(atmel_port->gpios, &ret); 544 } 545 546 /* 547 * Stop transmitting. 548 */ 549 static void atmel_stop_tx(struct uart_port *port) 550 { 551 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 552 553 if (atmel_use_pdc_tx(port)) { 554 /* disable PDC transmit */ 555 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 556 } 557 558 /* 559 * Disable the transmitter. 560 * This is mandatory when DMA is used, otherwise the DMA buffer 561 * is fully transmitted. 562 */ 563 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS); 564 atmel_port->tx_stopped = true; 565 566 /* Disable interrupts */ 567 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); 568 569 if (atmel_uart_is_half_duplex(port)) 570 if (!atomic_read(&atmel_port->tasklet_shutdown)) 571 atmel_start_rx(port); 572 573 } 574 575 /* 576 * Start transmitting. 577 */ 578 static void atmel_start_tx(struct uart_port *port) 579 { 580 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 581 582 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR) 583 & ATMEL_PDC_TXTEN)) 584 /* The transmitter is already running. Yes, we 585 really need this.*/ 586 return; 587 588 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port)) 589 if (atmel_uart_is_half_duplex(port)) 590 atmel_stop_rx(port); 591 592 if (atmel_use_pdc_tx(port)) 593 /* re-enable PDC transmit */ 594 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 595 596 /* Enable interrupts */ 597 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 598 599 /* re-enable the transmitter */ 600 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN); 601 atmel_port->tx_stopped = false; 602 } 603 604 /* 605 * start receiving - port is in process of being opened. 606 */ 607 static void atmel_start_rx(struct uart_port *port) 608 { 609 /* reset status and receiver */ 610 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 611 612 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN); 613 614 if (atmel_use_pdc_rx(port)) { 615 /* enable PDC controller */ 616 atmel_uart_writel(port, ATMEL_US_IER, 617 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 618 port->read_status_mask); 619 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 620 } else { 621 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY); 622 } 623 } 624 625 /* 626 * Stop receiving - port is in process of being closed. 627 */ 628 static void atmel_stop_rx(struct uart_port *port) 629 { 630 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS); 631 632 if (atmel_use_pdc_rx(port)) { 633 /* disable PDC receive */ 634 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS); 635 atmel_uart_writel(port, ATMEL_US_IDR, 636 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 637 port->read_status_mask); 638 } else { 639 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY); 640 } 641 } 642 643 /* 644 * Enable modem status interrupts 645 */ 646 static void atmel_enable_ms(struct uart_port *port) 647 { 648 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 649 uint32_t ier = 0; 650 651 /* 652 * Interrupt should not be enabled twice 653 */ 654 if (atmel_port->ms_irq_enabled) 655 return; 656 657 atmel_port->ms_irq_enabled = true; 658 659 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) 660 ier |= ATMEL_US_CTSIC; 661 662 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR)) 663 ier |= ATMEL_US_DSRIC; 664 665 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI)) 666 ier |= ATMEL_US_RIIC; 667 668 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD)) 669 ier |= ATMEL_US_DCDIC; 670 671 atmel_uart_writel(port, ATMEL_US_IER, ier); 672 673 mctrl_gpio_enable_ms(atmel_port->gpios); 674 } 675 676 /* 677 * Disable modem status interrupts 678 */ 679 static void atmel_disable_ms(struct uart_port *port) 680 { 681 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 682 uint32_t idr = 0; 683 684 /* 685 * Interrupt should not be disabled twice 686 */ 687 if (!atmel_port->ms_irq_enabled) 688 return; 689 690 atmel_port->ms_irq_enabled = false; 691 692 mctrl_gpio_disable_ms(atmel_port->gpios); 693 694 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) 695 idr |= ATMEL_US_CTSIC; 696 697 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR)) 698 idr |= ATMEL_US_DSRIC; 699 700 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI)) 701 idr |= ATMEL_US_RIIC; 702 703 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD)) 704 idr |= ATMEL_US_DCDIC; 705 706 atmel_uart_writel(port, ATMEL_US_IDR, idr); 707 } 708 709 /* 710 * Control the transmission of a break signal 711 */ 712 static void atmel_break_ctl(struct uart_port *port, int break_state) 713 { 714 if (break_state != 0) 715 /* start break */ 716 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK); 717 else 718 /* stop break */ 719 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK); 720 } 721 722 /* 723 * Stores the incoming character in the ring buffer 724 */ 725 static void 726 atmel_buffer_rx_char(struct uart_port *port, unsigned int status, 727 unsigned int ch) 728 { 729 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 730 struct circ_buf *ring = &atmel_port->rx_ring; 731 struct atmel_uart_char *c; 732 733 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) 734 /* Buffer overflow, ignore char */ 735 return; 736 737 c = &((struct atmel_uart_char *)ring->buf)[ring->head]; 738 c->status = status; 739 c->ch = ch; 740 741 /* Make sure the character is stored before we update head. */ 742 smp_wmb(); 743 744 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 745 } 746 747 /* 748 * Deal with parity, framing and overrun errors. 749 */ 750 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) 751 { 752 /* clear error */ 753 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 754 755 if (status & ATMEL_US_RXBRK) { 756 /* ignore side-effect */ 757 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 758 port->icount.brk++; 759 } 760 if (status & ATMEL_US_PARE) 761 port->icount.parity++; 762 if (status & ATMEL_US_FRAME) 763 port->icount.frame++; 764 if (status & ATMEL_US_OVRE) 765 port->icount.overrun++; 766 } 767 768 /* 769 * Characters received (called from interrupt handler) 770 */ 771 static void atmel_rx_chars(struct uart_port *port) 772 { 773 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 774 unsigned int status, ch; 775 776 status = atmel_uart_readl(port, ATMEL_US_CSR); 777 while (status & ATMEL_US_RXRDY) { 778 ch = atmel_uart_read_char(port); 779 780 /* 781 * note that the error handling code is 782 * out of the main execution path 783 */ 784 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 785 | ATMEL_US_OVRE | ATMEL_US_RXBRK) 786 || atmel_port->break_active)) { 787 788 /* clear error */ 789 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 790 791 if (status & ATMEL_US_RXBRK 792 && !atmel_port->break_active) { 793 atmel_port->break_active = 1; 794 atmel_uart_writel(port, ATMEL_US_IER, 795 ATMEL_US_RXBRK); 796 } else { 797 /* 798 * This is either the end-of-break 799 * condition or we've received at 800 * least one character without RXBRK 801 * being set. In both cases, the next 802 * RXBRK will indicate start-of-break. 803 */ 804 atmel_uart_writel(port, ATMEL_US_IDR, 805 ATMEL_US_RXBRK); 806 status &= ~ATMEL_US_RXBRK; 807 atmel_port->break_active = 0; 808 } 809 } 810 811 atmel_buffer_rx_char(port, status, ch); 812 status = atmel_uart_readl(port, ATMEL_US_CSR); 813 } 814 815 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx); 816 } 817 818 /* 819 * Transmit characters (called from tasklet with TXRDY interrupt 820 * disabled) 821 */ 822 static void atmel_tx_chars(struct uart_port *port) 823 { 824 struct circ_buf *xmit = &port->state->xmit; 825 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 826 827 if (port->x_char && 828 (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) { 829 atmel_uart_write_char(port, port->x_char); 830 port->icount.tx++; 831 port->x_char = 0; 832 } 833 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 834 return; 835 836 while (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY) { 837 atmel_uart_write_char(port, xmit->buf[xmit->tail]); 838 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 839 port->icount.tx++; 840 if (uart_circ_empty(xmit)) 841 break; 842 } 843 844 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 845 uart_write_wakeup(port); 846 847 if (!uart_circ_empty(xmit)) { 848 /* we still have characters to transmit, so we should continue 849 * transmitting them when TX is ready, regardless of 850 * mode or duplexity 851 */ 852 atmel_port->tx_done_mask |= ATMEL_US_TXRDY; 853 854 /* Enable interrupts */ 855 atmel_uart_writel(port, ATMEL_US_IER, 856 atmel_port->tx_done_mask); 857 } else { 858 if (atmel_uart_is_half_duplex(port)) 859 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY; 860 } 861 } 862 863 static void atmel_complete_tx_dma(void *arg) 864 { 865 struct atmel_uart_port *atmel_port = arg; 866 struct uart_port *port = &atmel_port->uart; 867 struct circ_buf *xmit = &port->state->xmit; 868 struct dma_chan *chan = atmel_port->chan_tx; 869 unsigned long flags; 870 871 spin_lock_irqsave(&port->lock, flags); 872 873 if (chan) 874 dmaengine_terminate_all(chan); 875 xmit->tail += atmel_port->tx_len; 876 xmit->tail &= UART_XMIT_SIZE - 1; 877 878 port->icount.tx += atmel_port->tx_len; 879 880 spin_lock_irq(&atmel_port->lock_tx); 881 async_tx_ack(atmel_port->desc_tx); 882 atmel_port->cookie_tx = -EINVAL; 883 atmel_port->desc_tx = NULL; 884 spin_unlock_irq(&atmel_port->lock_tx); 885 886 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 887 uart_write_wakeup(port); 888 889 /* 890 * xmit is a circular buffer so, if we have just send data from 891 * xmit->tail to the end of xmit->buf, now we have to transmit the 892 * remaining data from the beginning of xmit->buf to xmit->head. 893 */ 894 if (!uart_circ_empty(xmit)) 895 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx); 896 else if (atmel_uart_is_half_duplex(port)) { 897 /* 898 * DMA done, re-enable TXEMPTY and signal that we can stop 899 * TX and start RX for RS485 900 */ 901 atmel_port->hd_start_rx = true; 902 atmel_uart_writel(port, ATMEL_US_IER, 903 atmel_port->tx_done_mask); 904 } 905 906 spin_unlock_irqrestore(&port->lock, flags); 907 } 908 909 static void atmel_release_tx_dma(struct uart_port *port) 910 { 911 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 912 struct dma_chan *chan = atmel_port->chan_tx; 913 914 if (chan) { 915 dmaengine_terminate_all(chan); 916 dma_release_channel(chan); 917 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, 918 DMA_TO_DEVICE); 919 } 920 921 atmel_port->desc_tx = NULL; 922 atmel_port->chan_tx = NULL; 923 atmel_port->cookie_tx = -EINVAL; 924 } 925 926 /* 927 * Called from tasklet with TXRDY interrupt is disabled. 928 */ 929 static void atmel_tx_dma(struct uart_port *port) 930 { 931 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 932 struct circ_buf *xmit = &port->state->xmit; 933 struct dma_chan *chan = atmel_port->chan_tx; 934 struct dma_async_tx_descriptor *desc; 935 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx; 936 unsigned int tx_len, part1_len, part2_len, sg_len; 937 dma_addr_t phys_addr; 938 939 /* Make sure we have an idle channel */ 940 if (atmel_port->desc_tx != NULL) 941 return; 942 943 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 944 /* 945 * DMA is idle now. 946 * Port xmit buffer is already mapped, 947 * and it is one page... Just adjust 948 * offsets and lengths. Since it is a circular buffer, 949 * we have to transmit till the end, and then the rest. 950 * Take the port lock to get a 951 * consistent xmit buffer state. 952 */ 953 tx_len = CIRC_CNT_TO_END(xmit->head, 954 xmit->tail, 955 UART_XMIT_SIZE); 956 957 if (atmel_port->fifo_size) { 958 /* multi data mode */ 959 part1_len = (tx_len & ~0x3); /* DWORD access */ 960 part2_len = (tx_len & 0x3); /* BYTE access */ 961 } else { 962 /* single data (legacy) mode */ 963 part1_len = 0; 964 part2_len = tx_len; /* BYTE access only */ 965 } 966 967 sg_init_table(sgl, 2); 968 sg_len = 0; 969 phys_addr = sg_dma_address(sg_tx) + xmit->tail; 970 if (part1_len) { 971 sg = &sgl[sg_len++]; 972 sg_dma_address(sg) = phys_addr; 973 sg_dma_len(sg) = part1_len; 974 975 phys_addr += part1_len; 976 } 977 978 if (part2_len) { 979 sg = &sgl[sg_len++]; 980 sg_dma_address(sg) = phys_addr; 981 sg_dma_len(sg) = part2_len; 982 } 983 984 /* 985 * save tx_len so atmel_complete_tx_dma() will increase 986 * xmit->tail correctly 987 */ 988 atmel_port->tx_len = tx_len; 989 990 desc = dmaengine_prep_slave_sg(chan, 991 sgl, 992 sg_len, 993 DMA_MEM_TO_DEV, 994 DMA_PREP_INTERRUPT | 995 DMA_CTRL_ACK); 996 if (!desc) { 997 dev_err(port->dev, "Failed to send via dma!\n"); 998 return; 999 } 1000 1001 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE); 1002 1003 atmel_port->desc_tx = desc; 1004 desc->callback = atmel_complete_tx_dma; 1005 desc->callback_param = atmel_port; 1006 atmel_port->cookie_tx = dmaengine_submit(desc); 1007 if (dma_submit_error(atmel_port->cookie_tx)) { 1008 dev_err(port->dev, "dma_submit_error %d\n", 1009 atmel_port->cookie_tx); 1010 return; 1011 } 1012 1013 dma_async_issue_pending(chan); 1014 } 1015 1016 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1017 uart_write_wakeup(port); 1018 } 1019 1020 static int atmel_prepare_tx_dma(struct uart_port *port) 1021 { 1022 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1023 struct device *mfd_dev = port->dev->parent; 1024 dma_cap_mask_t mask; 1025 struct dma_slave_config config; 1026 int ret, nent; 1027 1028 dma_cap_zero(mask); 1029 dma_cap_set(DMA_SLAVE, mask); 1030 1031 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx"); 1032 if (atmel_port->chan_tx == NULL) 1033 goto chan_err; 1034 dev_info(port->dev, "using %s for tx DMA transfers\n", 1035 dma_chan_name(atmel_port->chan_tx)); 1036 1037 spin_lock_init(&atmel_port->lock_tx); 1038 sg_init_table(&atmel_port->sg_tx, 1); 1039 /* UART circular tx buffer is an aligned page. */ 1040 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf)); 1041 sg_set_page(&atmel_port->sg_tx, 1042 virt_to_page(port->state->xmit.buf), 1043 UART_XMIT_SIZE, 1044 offset_in_page(port->state->xmit.buf)); 1045 nent = dma_map_sg(port->dev, 1046 &atmel_port->sg_tx, 1047 1, 1048 DMA_TO_DEVICE); 1049 1050 if (!nent) { 1051 dev_dbg(port->dev, "need to release resource of dma\n"); 1052 goto chan_err; 1053 } else { 1054 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, 1055 sg_dma_len(&atmel_port->sg_tx), 1056 port->state->xmit.buf, 1057 &sg_dma_address(&atmel_port->sg_tx)); 1058 } 1059 1060 /* Configure the slave DMA */ 1061 memset(&config, 0, sizeof(config)); 1062 config.direction = DMA_MEM_TO_DEV; 1063 config.dst_addr_width = (atmel_port->fifo_size) ? 1064 DMA_SLAVE_BUSWIDTH_4_BYTES : 1065 DMA_SLAVE_BUSWIDTH_1_BYTE; 1066 config.dst_addr = port->mapbase + ATMEL_US_THR; 1067 config.dst_maxburst = 1; 1068 1069 ret = dmaengine_slave_config(atmel_port->chan_tx, 1070 &config); 1071 if (ret) { 1072 dev_err(port->dev, "DMA tx slave configuration failed\n"); 1073 goto chan_err; 1074 } 1075 1076 return 0; 1077 1078 chan_err: 1079 dev_err(port->dev, "TX channel not available, switch to pio\n"); 1080 atmel_port->use_dma_tx = false; 1081 if (atmel_port->chan_tx) 1082 atmel_release_tx_dma(port); 1083 return -EINVAL; 1084 } 1085 1086 static void atmel_complete_rx_dma(void *arg) 1087 { 1088 struct uart_port *port = arg; 1089 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1090 1091 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx); 1092 } 1093 1094 static void atmel_release_rx_dma(struct uart_port *port) 1095 { 1096 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1097 struct dma_chan *chan = atmel_port->chan_rx; 1098 1099 if (chan) { 1100 dmaengine_terminate_all(chan); 1101 dma_release_channel(chan); 1102 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, 1103 DMA_FROM_DEVICE); 1104 } 1105 1106 atmel_port->desc_rx = NULL; 1107 atmel_port->chan_rx = NULL; 1108 atmel_port->cookie_rx = -EINVAL; 1109 } 1110 1111 static void atmel_rx_from_dma(struct uart_port *port) 1112 { 1113 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1114 struct tty_port *tport = &port->state->port; 1115 struct circ_buf *ring = &atmel_port->rx_ring; 1116 struct dma_chan *chan = atmel_port->chan_rx; 1117 struct dma_tx_state state; 1118 enum dma_status dmastat; 1119 size_t count; 1120 1121 1122 /* Reset the UART timeout early so that we don't miss one */ 1123 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1124 dmastat = dmaengine_tx_status(chan, 1125 atmel_port->cookie_rx, 1126 &state); 1127 /* Restart a new tasklet if DMA status is error */ 1128 if (dmastat == DMA_ERROR) { 1129 dev_dbg(port->dev, "Get residue error, restart tasklet\n"); 1130 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT); 1131 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx); 1132 return; 1133 } 1134 1135 /* CPU claims ownership of RX DMA buffer */ 1136 dma_sync_sg_for_cpu(port->dev, 1137 &atmel_port->sg_rx, 1138 1, 1139 DMA_FROM_DEVICE); 1140 1141 /* 1142 * ring->head points to the end of data already written by the DMA. 1143 * ring->tail points to the beginning of data to be read by the 1144 * framework. 1145 * The current transfer size should not be larger than the dma buffer 1146 * length. 1147 */ 1148 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue; 1149 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx)); 1150 /* 1151 * At this point ring->head may point to the first byte right after the 1152 * last byte of the dma buffer: 1153 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx) 1154 * 1155 * However ring->tail must always points inside the dma buffer: 1156 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1 1157 * 1158 * Since we use a ring buffer, we have to handle the case 1159 * where head is lower than tail. In such a case, we first read from 1160 * tail to the end of the buffer then reset tail. 1161 */ 1162 if (ring->head < ring->tail) { 1163 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail; 1164 1165 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 1166 ring->tail = 0; 1167 port->icount.rx += count; 1168 } 1169 1170 /* Finally we read data from tail to head */ 1171 if (ring->tail < ring->head) { 1172 count = ring->head - ring->tail; 1173 1174 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 1175 /* Wrap ring->head if needed */ 1176 if (ring->head >= sg_dma_len(&atmel_port->sg_rx)) 1177 ring->head = 0; 1178 ring->tail = ring->head; 1179 port->icount.rx += count; 1180 } 1181 1182 /* USART retreives ownership of RX DMA buffer */ 1183 dma_sync_sg_for_device(port->dev, 1184 &atmel_port->sg_rx, 1185 1, 1186 DMA_FROM_DEVICE); 1187 1188 tty_flip_buffer_push(tport); 1189 1190 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT); 1191 } 1192 1193 static int atmel_prepare_rx_dma(struct uart_port *port) 1194 { 1195 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1196 struct device *mfd_dev = port->dev->parent; 1197 struct dma_async_tx_descriptor *desc; 1198 dma_cap_mask_t mask; 1199 struct dma_slave_config config; 1200 struct circ_buf *ring; 1201 int ret, nent; 1202 1203 ring = &atmel_port->rx_ring; 1204 1205 dma_cap_zero(mask); 1206 dma_cap_set(DMA_CYCLIC, mask); 1207 1208 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx"); 1209 if (atmel_port->chan_rx == NULL) 1210 goto chan_err; 1211 dev_info(port->dev, "using %s for rx DMA transfers\n", 1212 dma_chan_name(atmel_port->chan_rx)); 1213 1214 spin_lock_init(&atmel_port->lock_rx); 1215 sg_init_table(&atmel_port->sg_rx, 1); 1216 /* UART circular rx buffer is an aligned page. */ 1217 BUG_ON(!PAGE_ALIGNED(ring->buf)); 1218 sg_set_page(&atmel_port->sg_rx, 1219 virt_to_page(ring->buf), 1220 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE, 1221 offset_in_page(ring->buf)); 1222 nent = dma_map_sg(port->dev, 1223 &atmel_port->sg_rx, 1224 1, 1225 DMA_FROM_DEVICE); 1226 1227 if (!nent) { 1228 dev_dbg(port->dev, "need to release resource of dma\n"); 1229 goto chan_err; 1230 } else { 1231 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, 1232 sg_dma_len(&atmel_port->sg_rx), 1233 ring->buf, 1234 &sg_dma_address(&atmel_port->sg_rx)); 1235 } 1236 1237 /* Configure the slave DMA */ 1238 memset(&config, 0, sizeof(config)); 1239 config.direction = DMA_DEV_TO_MEM; 1240 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1241 config.src_addr = port->mapbase + ATMEL_US_RHR; 1242 config.src_maxburst = 1; 1243 1244 ret = dmaengine_slave_config(atmel_port->chan_rx, 1245 &config); 1246 if (ret) { 1247 dev_err(port->dev, "DMA rx slave configuration failed\n"); 1248 goto chan_err; 1249 } 1250 /* 1251 * Prepare a cyclic dma transfer, assign 2 descriptors, 1252 * each one is half ring buffer size 1253 */ 1254 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, 1255 sg_dma_address(&atmel_port->sg_rx), 1256 sg_dma_len(&atmel_port->sg_rx), 1257 sg_dma_len(&atmel_port->sg_rx)/2, 1258 DMA_DEV_TO_MEM, 1259 DMA_PREP_INTERRUPT); 1260 if (!desc) { 1261 dev_err(port->dev, "Preparing DMA cyclic failed\n"); 1262 goto chan_err; 1263 } 1264 desc->callback = atmel_complete_rx_dma; 1265 desc->callback_param = port; 1266 atmel_port->desc_rx = desc; 1267 atmel_port->cookie_rx = dmaengine_submit(desc); 1268 if (dma_submit_error(atmel_port->cookie_rx)) { 1269 dev_err(port->dev, "dma_submit_error %d\n", 1270 atmel_port->cookie_rx); 1271 goto chan_err; 1272 } 1273 1274 dma_async_issue_pending(atmel_port->chan_rx); 1275 1276 return 0; 1277 1278 chan_err: 1279 dev_err(port->dev, "RX channel not available, switch to pio\n"); 1280 atmel_port->use_dma_rx = false; 1281 if (atmel_port->chan_rx) 1282 atmel_release_rx_dma(port); 1283 return -EINVAL; 1284 } 1285 1286 static void atmel_uart_timer_callback(struct timer_list *t) 1287 { 1288 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t, 1289 uart_timer); 1290 struct uart_port *port = &atmel_port->uart; 1291 1292 if (!atomic_read(&atmel_port->tasklet_shutdown)) { 1293 tasklet_schedule(&atmel_port->tasklet_rx); 1294 mod_timer(&atmel_port->uart_timer, 1295 jiffies + uart_poll_timeout(port)); 1296 } 1297 } 1298 1299 /* 1300 * receive interrupt handler. 1301 */ 1302 static void 1303 atmel_handle_receive(struct uart_port *port, unsigned int pending) 1304 { 1305 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1306 1307 if (atmel_use_pdc_rx(port)) { 1308 /* 1309 * PDC receive. Just schedule the tasklet and let it 1310 * figure out the details. 1311 * 1312 * TODO: We're not handling error flags correctly at 1313 * the moment. 1314 */ 1315 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { 1316 atmel_uart_writel(port, ATMEL_US_IDR, 1317 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)); 1318 atmel_tasklet_schedule(atmel_port, 1319 &atmel_port->tasklet_rx); 1320 } 1321 1322 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | 1323 ATMEL_US_FRAME | ATMEL_US_PARE)) 1324 atmel_pdc_rxerr(port, pending); 1325 } 1326 1327 if (atmel_use_dma_rx(port)) { 1328 if (pending & ATMEL_US_TIMEOUT) { 1329 atmel_uart_writel(port, ATMEL_US_IDR, 1330 ATMEL_US_TIMEOUT); 1331 atmel_tasklet_schedule(atmel_port, 1332 &atmel_port->tasklet_rx); 1333 } 1334 } 1335 1336 /* Interrupt receive */ 1337 if (pending & ATMEL_US_RXRDY) 1338 atmel_rx_chars(port); 1339 else if (pending & ATMEL_US_RXBRK) { 1340 /* 1341 * End of break detected. If it came along with a 1342 * character, atmel_rx_chars will handle it. 1343 */ 1344 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 1345 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK); 1346 atmel_port->break_active = 0; 1347 } 1348 } 1349 1350 /* 1351 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) 1352 */ 1353 static void 1354 atmel_handle_transmit(struct uart_port *port, unsigned int pending) 1355 { 1356 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1357 1358 if (pending & atmel_port->tx_done_mask) { 1359 atmel_uart_writel(port, ATMEL_US_IDR, 1360 atmel_port->tx_done_mask); 1361 1362 /* Start RX if flag was set and FIFO is empty */ 1363 if (atmel_port->hd_start_rx) { 1364 if (!(atmel_uart_readl(port, ATMEL_US_CSR) 1365 & ATMEL_US_TXEMPTY)) 1366 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n"); 1367 1368 atmel_port->hd_start_rx = false; 1369 atmel_start_rx(port); 1370 } 1371 1372 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx); 1373 } 1374 } 1375 1376 /* 1377 * status flags interrupt handler. 1378 */ 1379 static void 1380 atmel_handle_status(struct uart_port *port, unsigned int pending, 1381 unsigned int status) 1382 { 1383 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1384 unsigned int status_change; 1385 1386 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC 1387 | ATMEL_US_CTSIC)) { 1388 status_change = status ^ atmel_port->irq_status_prev; 1389 atmel_port->irq_status_prev = status; 1390 1391 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR 1392 | ATMEL_US_DCD | ATMEL_US_CTS)) { 1393 /* TODO: All reads to CSR will clear these interrupts! */ 1394 if (status_change & ATMEL_US_RI) 1395 port->icount.rng++; 1396 if (status_change & ATMEL_US_DSR) 1397 port->icount.dsr++; 1398 if (status_change & ATMEL_US_DCD) 1399 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); 1400 if (status_change & ATMEL_US_CTS) 1401 uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); 1402 1403 wake_up_interruptible(&port->state->port.delta_msr_wait); 1404 } 1405 } 1406 1407 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION)) 1408 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending); 1409 } 1410 1411 /* 1412 * Interrupt handler 1413 */ 1414 static irqreturn_t atmel_interrupt(int irq, void *dev_id) 1415 { 1416 struct uart_port *port = dev_id; 1417 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1418 unsigned int status, pending, mask, pass_counter = 0; 1419 1420 spin_lock(&atmel_port->lock_suspended); 1421 1422 do { 1423 status = atmel_uart_readl(port, ATMEL_US_CSR); 1424 mask = atmel_uart_readl(port, ATMEL_US_IMR); 1425 pending = status & mask; 1426 if (!pending) 1427 break; 1428 1429 if (atmel_port->suspended) { 1430 atmel_port->pending |= pending; 1431 atmel_port->pending_status = status; 1432 atmel_uart_writel(port, ATMEL_US_IDR, mask); 1433 pm_system_wakeup(); 1434 break; 1435 } 1436 1437 atmel_handle_receive(port, pending); 1438 atmel_handle_status(port, pending, status); 1439 atmel_handle_transmit(port, pending); 1440 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); 1441 1442 spin_unlock(&atmel_port->lock_suspended); 1443 1444 return pass_counter ? IRQ_HANDLED : IRQ_NONE; 1445 } 1446 1447 static void atmel_release_tx_pdc(struct uart_port *port) 1448 { 1449 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1450 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1451 1452 dma_unmap_single(port->dev, 1453 pdc->dma_addr, 1454 pdc->dma_size, 1455 DMA_TO_DEVICE); 1456 } 1457 1458 /* 1459 * Called from tasklet with ENDTX and TXBUFE interrupts disabled. 1460 */ 1461 static void atmel_tx_pdc(struct uart_port *port) 1462 { 1463 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1464 struct circ_buf *xmit = &port->state->xmit; 1465 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1466 int count; 1467 1468 /* nothing left to transmit? */ 1469 if (atmel_uart_readl(port, ATMEL_PDC_TCR)) 1470 return; 1471 1472 xmit->tail += pdc->ofs; 1473 xmit->tail &= UART_XMIT_SIZE - 1; 1474 1475 port->icount.tx += pdc->ofs; 1476 pdc->ofs = 0; 1477 1478 /* more to transmit - setup next transfer */ 1479 1480 /* disable PDC transmit */ 1481 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 1482 1483 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 1484 dma_sync_single_for_device(port->dev, 1485 pdc->dma_addr, 1486 pdc->dma_size, 1487 DMA_TO_DEVICE); 1488 1489 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1490 pdc->ofs = count; 1491 1492 atmel_uart_writel(port, ATMEL_PDC_TPR, 1493 pdc->dma_addr + xmit->tail); 1494 atmel_uart_writel(port, ATMEL_PDC_TCR, count); 1495 /* re-enable PDC transmit */ 1496 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 1497 /* Enable interrupts */ 1498 atmel_uart_writel(port, ATMEL_US_IER, 1499 atmel_port->tx_done_mask); 1500 } else { 1501 if (atmel_uart_is_half_duplex(port)) { 1502 /* DMA done, stop TX, start RX for RS485 */ 1503 atmel_start_rx(port); 1504 } 1505 } 1506 1507 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1508 uart_write_wakeup(port); 1509 } 1510 1511 static int atmel_prepare_tx_pdc(struct uart_port *port) 1512 { 1513 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1514 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1515 struct circ_buf *xmit = &port->state->xmit; 1516 1517 pdc->buf = xmit->buf; 1518 pdc->dma_addr = dma_map_single(port->dev, 1519 pdc->buf, 1520 UART_XMIT_SIZE, 1521 DMA_TO_DEVICE); 1522 pdc->dma_size = UART_XMIT_SIZE; 1523 pdc->ofs = 0; 1524 1525 return 0; 1526 } 1527 1528 static void atmel_rx_from_ring(struct uart_port *port) 1529 { 1530 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1531 struct circ_buf *ring = &atmel_port->rx_ring; 1532 unsigned int flg; 1533 unsigned int status; 1534 1535 while (ring->head != ring->tail) { 1536 struct atmel_uart_char c; 1537 1538 /* Make sure c is loaded after head. */ 1539 smp_rmb(); 1540 1541 c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; 1542 1543 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 1544 1545 port->icount.rx++; 1546 status = c.status; 1547 flg = TTY_NORMAL; 1548 1549 /* 1550 * note that the error handling code is 1551 * out of the main execution path 1552 */ 1553 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 1554 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { 1555 if (status & ATMEL_US_RXBRK) { 1556 /* ignore side-effect */ 1557 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 1558 1559 port->icount.brk++; 1560 if (uart_handle_break(port)) 1561 continue; 1562 } 1563 if (status & ATMEL_US_PARE) 1564 port->icount.parity++; 1565 if (status & ATMEL_US_FRAME) 1566 port->icount.frame++; 1567 if (status & ATMEL_US_OVRE) 1568 port->icount.overrun++; 1569 1570 status &= port->read_status_mask; 1571 1572 if (status & ATMEL_US_RXBRK) 1573 flg = TTY_BREAK; 1574 else if (status & ATMEL_US_PARE) 1575 flg = TTY_PARITY; 1576 else if (status & ATMEL_US_FRAME) 1577 flg = TTY_FRAME; 1578 } 1579 1580 1581 if (uart_handle_sysrq_char(port, c.ch)) 1582 continue; 1583 1584 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); 1585 } 1586 1587 tty_flip_buffer_push(&port->state->port); 1588 } 1589 1590 static void atmel_release_rx_pdc(struct uart_port *port) 1591 { 1592 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1593 int i; 1594 1595 for (i = 0; i < 2; i++) { 1596 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1597 1598 dma_unmap_single(port->dev, 1599 pdc->dma_addr, 1600 pdc->dma_size, 1601 DMA_FROM_DEVICE); 1602 kfree(pdc->buf); 1603 } 1604 } 1605 1606 static void atmel_rx_from_pdc(struct uart_port *port) 1607 { 1608 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1609 struct tty_port *tport = &port->state->port; 1610 struct atmel_dma_buffer *pdc; 1611 int rx_idx = atmel_port->pdc_rx_idx; 1612 unsigned int head; 1613 unsigned int tail; 1614 unsigned int count; 1615 1616 do { 1617 /* Reset the UART timeout early so that we don't miss one */ 1618 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1619 1620 pdc = &atmel_port->pdc_rx[rx_idx]; 1621 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr; 1622 tail = pdc->ofs; 1623 1624 /* If the PDC has switched buffers, RPR won't contain 1625 * any address within the current buffer. Since head 1626 * is unsigned, we just need a one-way comparison to 1627 * find out. 1628 * 1629 * In this case, we just need to consume the entire 1630 * buffer and resubmit it for DMA. This will clear the 1631 * ENDRX bit as well, so that we can safely re-enable 1632 * all interrupts below. 1633 */ 1634 head = min(head, pdc->dma_size); 1635 1636 if (likely(head != tail)) { 1637 dma_sync_single_for_cpu(port->dev, pdc->dma_addr, 1638 pdc->dma_size, DMA_FROM_DEVICE); 1639 1640 /* 1641 * head will only wrap around when we recycle 1642 * the DMA buffer, and when that happens, we 1643 * explicitly set tail to 0. So head will 1644 * always be greater than tail. 1645 */ 1646 count = head - tail; 1647 1648 tty_insert_flip_string(tport, pdc->buf + pdc->ofs, 1649 count); 1650 1651 dma_sync_single_for_device(port->dev, pdc->dma_addr, 1652 pdc->dma_size, DMA_FROM_DEVICE); 1653 1654 port->icount.rx += count; 1655 pdc->ofs = head; 1656 } 1657 1658 /* 1659 * If the current buffer is full, we need to check if 1660 * the next one contains any additional data. 1661 */ 1662 if (head >= pdc->dma_size) { 1663 pdc->ofs = 0; 1664 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr); 1665 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size); 1666 1667 rx_idx = !rx_idx; 1668 atmel_port->pdc_rx_idx = rx_idx; 1669 } 1670 } while (head >= pdc->dma_size); 1671 1672 tty_flip_buffer_push(tport); 1673 1674 atmel_uart_writel(port, ATMEL_US_IER, 1675 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1676 } 1677 1678 static int atmel_prepare_rx_pdc(struct uart_port *port) 1679 { 1680 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1681 int i; 1682 1683 for (i = 0; i < 2; i++) { 1684 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1685 1686 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); 1687 if (pdc->buf == NULL) { 1688 if (i != 0) { 1689 dma_unmap_single(port->dev, 1690 atmel_port->pdc_rx[0].dma_addr, 1691 PDC_BUFFER_SIZE, 1692 DMA_FROM_DEVICE); 1693 kfree(atmel_port->pdc_rx[0].buf); 1694 } 1695 atmel_port->use_pdc_rx = false; 1696 return -ENOMEM; 1697 } 1698 pdc->dma_addr = dma_map_single(port->dev, 1699 pdc->buf, 1700 PDC_BUFFER_SIZE, 1701 DMA_FROM_DEVICE); 1702 pdc->dma_size = PDC_BUFFER_SIZE; 1703 pdc->ofs = 0; 1704 } 1705 1706 atmel_port->pdc_rx_idx = 0; 1707 1708 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr); 1709 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE); 1710 1711 atmel_uart_writel(port, ATMEL_PDC_RNPR, 1712 atmel_port->pdc_rx[1].dma_addr); 1713 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE); 1714 1715 return 0; 1716 } 1717 1718 /* 1719 * tasklet handling tty stuff outside the interrupt handler. 1720 */ 1721 static void atmel_tasklet_rx_func(struct tasklet_struct *t) 1722 { 1723 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t, 1724 tasklet_rx); 1725 struct uart_port *port = &atmel_port->uart; 1726 1727 /* The interrupt handler does not take the lock */ 1728 spin_lock(&port->lock); 1729 atmel_port->schedule_rx(port); 1730 spin_unlock(&port->lock); 1731 } 1732 1733 static void atmel_tasklet_tx_func(struct tasklet_struct *t) 1734 { 1735 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t, 1736 tasklet_tx); 1737 struct uart_port *port = &atmel_port->uart; 1738 1739 /* The interrupt handler does not take the lock */ 1740 spin_lock(&port->lock); 1741 atmel_port->schedule_tx(port); 1742 spin_unlock(&port->lock); 1743 } 1744 1745 static void atmel_init_property(struct atmel_uart_port *atmel_port, 1746 struct platform_device *pdev) 1747 { 1748 struct device_node *np = pdev->dev.of_node; 1749 1750 /* DMA/PDC usage specification */ 1751 if (of_property_read_bool(np, "atmel,use-dma-rx")) { 1752 if (of_property_read_bool(np, "dmas")) { 1753 atmel_port->use_dma_rx = true; 1754 atmel_port->use_pdc_rx = false; 1755 } else { 1756 atmel_port->use_dma_rx = false; 1757 atmel_port->use_pdc_rx = true; 1758 } 1759 } else { 1760 atmel_port->use_dma_rx = false; 1761 atmel_port->use_pdc_rx = false; 1762 } 1763 1764 if (of_property_read_bool(np, "atmel,use-dma-tx")) { 1765 if (of_property_read_bool(np, "dmas")) { 1766 atmel_port->use_dma_tx = true; 1767 atmel_port->use_pdc_tx = false; 1768 } else { 1769 atmel_port->use_dma_tx = false; 1770 atmel_port->use_pdc_tx = true; 1771 } 1772 } else { 1773 atmel_port->use_dma_tx = false; 1774 atmel_port->use_pdc_tx = false; 1775 } 1776 } 1777 1778 static void atmel_set_ops(struct uart_port *port) 1779 { 1780 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1781 1782 if (atmel_use_dma_rx(port)) { 1783 atmel_port->prepare_rx = &atmel_prepare_rx_dma; 1784 atmel_port->schedule_rx = &atmel_rx_from_dma; 1785 atmel_port->release_rx = &atmel_release_rx_dma; 1786 } else if (atmel_use_pdc_rx(port)) { 1787 atmel_port->prepare_rx = &atmel_prepare_rx_pdc; 1788 atmel_port->schedule_rx = &atmel_rx_from_pdc; 1789 atmel_port->release_rx = &atmel_release_rx_pdc; 1790 } else { 1791 atmel_port->prepare_rx = NULL; 1792 atmel_port->schedule_rx = &atmel_rx_from_ring; 1793 atmel_port->release_rx = NULL; 1794 } 1795 1796 if (atmel_use_dma_tx(port)) { 1797 atmel_port->prepare_tx = &atmel_prepare_tx_dma; 1798 atmel_port->schedule_tx = &atmel_tx_dma; 1799 atmel_port->release_tx = &atmel_release_tx_dma; 1800 } else if (atmel_use_pdc_tx(port)) { 1801 atmel_port->prepare_tx = &atmel_prepare_tx_pdc; 1802 atmel_port->schedule_tx = &atmel_tx_pdc; 1803 atmel_port->release_tx = &atmel_release_tx_pdc; 1804 } else { 1805 atmel_port->prepare_tx = NULL; 1806 atmel_port->schedule_tx = &atmel_tx_chars; 1807 atmel_port->release_tx = NULL; 1808 } 1809 } 1810 1811 /* 1812 * Get ip name usart or uart 1813 */ 1814 static void atmel_get_ip_name(struct uart_port *port) 1815 { 1816 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1817 int name = atmel_uart_readl(port, ATMEL_US_NAME); 1818 u32 version; 1819 u32 usart, dbgu_uart, new_uart; 1820 /* ASCII decoding for IP version */ 1821 usart = 0x55534152; /* USAR(T) */ 1822 dbgu_uart = 0x44424755; /* DBGU */ 1823 new_uart = 0x55415254; /* UART */ 1824 1825 /* 1826 * Only USART devices from at91sam9260 SOC implement fractional 1827 * baudrate. It is available for all asynchronous modes, with the 1828 * following restriction: the sampling clock's duty cycle is not 1829 * constant. 1830 */ 1831 atmel_port->has_frac_baudrate = false; 1832 atmel_port->has_hw_timer = false; 1833 1834 if (name == new_uart) { 1835 dev_dbg(port->dev, "Uart with hw timer"); 1836 atmel_port->has_hw_timer = true; 1837 atmel_port->rtor = ATMEL_UA_RTOR; 1838 } else if (name == usart) { 1839 dev_dbg(port->dev, "Usart\n"); 1840 atmel_port->has_frac_baudrate = true; 1841 atmel_port->has_hw_timer = true; 1842 atmel_port->rtor = ATMEL_US_RTOR; 1843 version = atmel_uart_readl(port, ATMEL_US_VERSION); 1844 switch (version) { 1845 case 0x814: /* sama5d2 */ 1846 fallthrough; 1847 case 0x701: /* sama5d4 */ 1848 atmel_port->fidi_min = 3; 1849 atmel_port->fidi_max = 65535; 1850 break; 1851 case 0x502: /* sam9x5, sama5d3 */ 1852 atmel_port->fidi_min = 3; 1853 atmel_port->fidi_max = 2047; 1854 break; 1855 default: 1856 atmel_port->fidi_min = 1; 1857 atmel_port->fidi_max = 2047; 1858 } 1859 } else if (name == dbgu_uart) { 1860 dev_dbg(port->dev, "Dbgu or uart without hw timer\n"); 1861 } else { 1862 /* fallback for older SoCs: use version field */ 1863 version = atmel_uart_readl(port, ATMEL_US_VERSION); 1864 switch (version) { 1865 case 0x302: 1866 case 0x10213: 1867 case 0x10302: 1868 dev_dbg(port->dev, "This version is usart\n"); 1869 atmel_port->has_frac_baudrate = true; 1870 atmel_port->has_hw_timer = true; 1871 atmel_port->rtor = ATMEL_US_RTOR; 1872 break; 1873 case 0x203: 1874 case 0x10202: 1875 dev_dbg(port->dev, "This version is uart\n"); 1876 break; 1877 default: 1878 dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); 1879 } 1880 } 1881 } 1882 1883 /* 1884 * Perform initialization and enable port for reception 1885 */ 1886 static int atmel_startup(struct uart_port *port) 1887 { 1888 struct platform_device *pdev = to_platform_device(port->dev); 1889 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1890 int retval; 1891 1892 /* 1893 * Ensure that no interrupts are enabled otherwise when 1894 * request_irq() is called we could get stuck trying to 1895 * handle an unexpected interrupt 1896 */ 1897 atmel_uart_writel(port, ATMEL_US_IDR, -1); 1898 atmel_port->ms_irq_enabled = false; 1899 1900 /* 1901 * Allocate the IRQ 1902 */ 1903 retval = request_irq(port->irq, atmel_interrupt, 1904 IRQF_SHARED | IRQF_COND_SUSPEND, 1905 dev_name(&pdev->dev), port); 1906 if (retval) { 1907 dev_err(port->dev, "atmel_startup - Can't get irq\n"); 1908 return retval; 1909 } 1910 1911 atomic_set(&atmel_port->tasklet_shutdown, 0); 1912 tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func); 1913 tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func); 1914 1915 /* 1916 * Initialize DMA (if necessary) 1917 */ 1918 atmel_init_property(atmel_port, pdev); 1919 atmel_set_ops(port); 1920 1921 if (atmel_port->prepare_rx) { 1922 retval = atmel_port->prepare_rx(port); 1923 if (retval < 0) 1924 atmel_set_ops(port); 1925 } 1926 1927 if (atmel_port->prepare_tx) { 1928 retval = atmel_port->prepare_tx(port); 1929 if (retval < 0) 1930 atmel_set_ops(port); 1931 } 1932 1933 /* 1934 * Enable FIFO when available 1935 */ 1936 if (atmel_port->fifo_size) { 1937 unsigned int txrdym = ATMEL_US_ONE_DATA; 1938 unsigned int rxrdym = ATMEL_US_ONE_DATA; 1939 unsigned int fmr; 1940 1941 atmel_uart_writel(port, ATMEL_US_CR, 1942 ATMEL_US_FIFOEN | 1943 ATMEL_US_RXFCLR | 1944 ATMEL_US_TXFLCLR); 1945 1946 if (atmel_use_dma_tx(port)) 1947 txrdym = ATMEL_US_FOUR_DATA; 1948 1949 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym); 1950 if (atmel_port->rts_high && 1951 atmel_port->rts_low) 1952 fmr |= ATMEL_US_FRTSC | 1953 ATMEL_US_RXFTHRES(atmel_port->rts_high) | 1954 ATMEL_US_RXFTHRES2(atmel_port->rts_low); 1955 1956 atmel_uart_writel(port, ATMEL_US_FMR, fmr); 1957 } 1958 1959 /* Save current CSR for comparison in atmel_tasklet_func() */ 1960 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR); 1961 1962 /* 1963 * Finally, enable the serial port 1964 */ 1965 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1966 /* enable xmit & rcvr */ 1967 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 1968 atmel_port->tx_stopped = false; 1969 1970 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0); 1971 1972 if (atmel_use_pdc_rx(port)) { 1973 /* set UART timeout */ 1974 if (!atmel_port->has_hw_timer) { 1975 mod_timer(&atmel_port->uart_timer, 1976 jiffies + uart_poll_timeout(port)); 1977 /* set USART timeout */ 1978 } else { 1979 atmel_uart_writel(port, atmel_port->rtor, 1980 PDC_RX_TIMEOUT); 1981 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1982 1983 atmel_uart_writel(port, ATMEL_US_IER, 1984 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1985 } 1986 /* enable PDC controller */ 1987 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 1988 } else if (atmel_use_dma_rx(port)) { 1989 /* set UART timeout */ 1990 if (!atmel_port->has_hw_timer) { 1991 mod_timer(&atmel_port->uart_timer, 1992 jiffies + uart_poll_timeout(port)); 1993 /* set USART timeout */ 1994 } else { 1995 atmel_uart_writel(port, atmel_port->rtor, 1996 PDC_RX_TIMEOUT); 1997 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1998 1999 atmel_uart_writel(port, ATMEL_US_IER, 2000 ATMEL_US_TIMEOUT); 2001 } 2002 } else { 2003 /* enable receive only */ 2004 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY); 2005 } 2006 2007 return 0; 2008 } 2009 2010 /* 2011 * Flush any TX data submitted for DMA. Called when the TX circular 2012 * buffer is reset. 2013 */ 2014 static void atmel_flush_buffer(struct uart_port *port) 2015 { 2016 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2017 2018 if (atmel_use_pdc_tx(port)) { 2019 atmel_uart_writel(port, ATMEL_PDC_TCR, 0); 2020 atmel_port->pdc_tx.ofs = 0; 2021 } 2022 /* 2023 * in uart_flush_buffer(), the xmit circular buffer has just 2024 * been cleared, so we have to reset tx_len accordingly. 2025 */ 2026 atmel_port->tx_len = 0; 2027 } 2028 2029 /* 2030 * Disable the port 2031 */ 2032 static void atmel_shutdown(struct uart_port *port) 2033 { 2034 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2035 2036 /* Disable modem control lines interrupts */ 2037 atmel_disable_ms(port); 2038 2039 /* Disable interrupts at device level */ 2040 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2041 2042 /* Prevent spurious interrupts from scheduling the tasklet */ 2043 atomic_inc(&atmel_port->tasklet_shutdown); 2044 2045 /* 2046 * Prevent any tasklets being scheduled during 2047 * cleanup 2048 */ 2049 del_timer_sync(&atmel_port->uart_timer); 2050 2051 /* Make sure that no interrupt is on the fly */ 2052 synchronize_irq(port->irq); 2053 2054 /* 2055 * Clear out any scheduled tasklets before 2056 * we destroy the buffers 2057 */ 2058 tasklet_kill(&atmel_port->tasklet_rx); 2059 tasklet_kill(&atmel_port->tasklet_tx); 2060 2061 /* 2062 * Ensure everything is stopped and 2063 * disable port and break condition. 2064 */ 2065 atmel_stop_rx(port); 2066 atmel_stop_tx(port); 2067 2068 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 2069 2070 /* 2071 * Shut-down the DMA. 2072 */ 2073 if (atmel_port->release_rx) 2074 atmel_port->release_rx(port); 2075 if (atmel_port->release_tx) 2076 atmel_port->release_tx(port); 2077 2078 /* 2079 * Reset ring buffer pointers 2080 */ 2081 atmel_port->rx_ring.head = 0; 2082 atmel_port->rx_ring.tail = 0; 2083 2084 /* 2085 * Free the interrupts 2086 */ 2087 free_irq(port->irq, port); 2088 2089 atmel_flush_buffer(port); 2090 } 2091 2092 /* 2093 * Power / Clock management. 2094 */ 2095 static void atmel_serial_pm(struct uart_port *port, unsigned int state, 2096 unsigned int oldstate) 2097 { 2098 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2099 2100 switch (state) { 2101 case UART_PM_STATE_ON: 2102 /* 2103 * Enable the peripheral clock for this serial port. 2104 * This is called on uart_open() or a resume event. 2105 */ 2106 clk_prepare_enable(atmel_port->clk); 2107 2108 /* re-enable interrupts if we disabled some on suspend */ 2109 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr); 2110 break; 2111 case UART_PM_STATE_OFF: 2112 /* Back up the interrupt mask and disable all interrupts */ 2113 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR); 2114 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2115 2116 /* 2117 * Disable the peripheral clock for this serial port. 2118 * This is called on uart_close() or a suspend event. 2119 */ 2120 clk_disable_unprepare(atmel_port->clk); 2121 break; 2122 default: 2123 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); 2124 } 2125 } 2126 2127 /* 2128 * Change the port parameters 2129 */ 2130 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, 2131 struct ktermios *old) 2132 { 2133 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2134 unsigned long flags; 2135 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0; 2136 2137 /* save the current mode register */ 2138 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR); 2139 2140 /* reset the mode, clock divisor, parity, stop bits and data size */ 2141 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | 2142 ATMEL_US_PAR | ATMEL_US_USMODE); 2143 2144 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 2145 2146 /* byte size */ 2147 switch (termios->c_cflag & CSIZE) { 2148 case CS5: 2149 mode |= ATMEL_US_CHRL_5; 2150 break; 2151 case CS6: 2152 mode |= ATMEL_US_CHRL_6; 2153 break; 2154 case CS7: 2155 mode |= ATMEL_US_CHRL_7; 2156 break; 2157 default: 2158 mode |= ATMEL_US_CHRL_8; 2159 break; 2160 } 2161 2162 /* stop bits */ 2163 if (termios->c_cflag & CSTOPB) 2164 mode |= ATMEL_US_NBSTOP_2; 2165 2166 /* parity */ 2167 if (termios->c_cflag & PARENB) { 2168 /* Mark or Space parity */ 2169 if (termios->c_cflag & CMSPAR) { 2170 if (termios->c_cflag & PARODD) 2171 mode |= ATMEL_US_PAR_MARK; 2172 else 2173 mode |= ATMEL_US_PAR_SPACE; 2174 } else if (termios->c_cflag & PARODD) 2175 mode |= ATMEL_US_PAR_ODD; 2176 else 2177 mode |= ATMEL_US_PAR_EVEN; 2178 } else 2179 mode |= ATMEL_US_PAR_NONE; 2180 2181 spin_lock_irqsave(&port->lock, flags); 2182 2183 port->read_status_mask = ATMEL_US_OVRE; 2184 if (termios->c_iflag & INPCK) 2185 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2186 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2187 port->read_status_mask |= ATMEL_US_RXBRK; 2188 2189 if (atmel_use_pdc_rx(port)) 2190 /* need to enable error interrupts */ 2191 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask); 2192 2193 /* 2194 * Characters to ignore 2195 */ 2196 port->ignore_status_mask = 0; 2197 if (termios->c_iflag & IGNPAR) 2198 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2199 if (termios->c_iflag & IGNBRK) { 2200 port->ignore_status_mask |= ATMEL_US_RXBRK; 2201 /* 2202 * If we're ignoring parity and break indicators, 2203 * ignore overruns too (for real raw support). 2204 */ 2205 if (termios->c_iflag & IGNPAR) 2206 port->ignore_status_mask |= ATMEL_US_OVRE; 2207 } 2208 /* TODO: Ignore all characters if CREAD is set.*/ 2209 2210 /* update the per-port timeout */ 2211 uart_update_timeout(port, termios->c_cflag, baud); 2212 2213 /* 2214 * save/disable interrupts. The tty layer will ensure that the 2215 * transmitter is empty if requested by the caller, so there's 2216 * no need to wait for it here. 2217 */ 2218 imr = atmel_uart_readl(port, ATMEL_US_IMR); 2219 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2220 2221 /* disable receiver and transmitter */ 2222 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS); 2223 atmel_port->tx_stopped = true; 2224 2225 /* mode */ 2226 if (port->rs485.flags & SER_RS485_ENABLED) { 2227 atmel_uart_writel(port, ATMEL_US_TTGR, 2228 port->rs485.delay_rts_after_send); 2229 mode |= ATMEL_US_USMODE_RS485; 2230 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) { 2231 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg); 2232 /* select mck clock, and output */ 2233 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO; 2234 /* set max iterations */ 2235 mode |= ATMEL_US_MAX_ITER(3); 2236 if ((port->iso7816.flags & SER_ISO7816_T_PARAM) 2237 == SER_ISO7816_T(0)) 2238 mode |= ATMEL_US_USMODE_ISO7816_T0; 2239 else 2240 mode |= ATMEL_US_USMODE_ISO7816_T1; 2241 } else if (termios->c_cflag & CRTSCTS) { 2242 /* RS232 with hardware handshake (RTS/CTS) */ 2243 if (atmel_use_fifo(port) && 2244 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) { 2245 /* 2246 * with ATMEL_US_USMODE_HWHS set, the controller will 2247 * be able to drive the RTS pin high/low when the RX 2248 * FIFO is above RXFTHRES/below RXFTHRES2. 2249 * It will also disable the transmitter when the CTS 2250 * pin is high. 2251 * This mode is not activated if CTS pin is a GPIO 2252 * because in this case, the transmitter is always 2253 * disabled (there must be an internal pull-up 2254 * responsible for this behaviour). 2255 * If the RTS pin is a GPIO, the controller won't be 2256 * able to drive it according to the FIFO thresholds, 2257 * but it will be handled by the driver. 2258 */ 2259 mode |= ATMEL_US_USMODE_HWHS; 2260 } else { 2261 /* 2262 * For platforms without FIFO, the flow control is 2263 * handled by the driver. 2264 */ 2265 mode |= ATMEL_US_USMODE_NORMAL; 2266 } 2267 } else { 2268 /* RS232 without hadware handshake */ 2269 mode |= ATMEL_US_USMODE_NORMAL; 2270 } 2271 2272 /* 2273 * Set the baud rate: 2274 * Fractional baudrate allows to setup output frequency more 2275 * accurately. This feature is enabled only when using normal mode. 2276 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8)) 2277 * Currently, OVER is always set to 0 so we get 2278 * baudrate = selected clock / (16 * (CD + FP / 8)) 2279 * then 2280 * 8 CD + FP = selected clock / (2 * baudrate) 2281 */ 2282 if (atmel_port->has_frac_baudrate) { 2283 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2); 2284 cd = div >> 3; 2285 fp = div & ATMEL_US_FP_MASK; 2286 } else { 2287 cd = uart_get_divisor(port, baud); 2288 } 2289 2290 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */ 2291 cd /= 8; 2292 mode |= ATMEL_US_USCLKS_MCK_DIV8; 2293 } 2294 quot = cd | fp << ATMEL_US_FP_OFFSET; 2295 2296 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) 2297 atmel_uart_writel(port, ATMEL_US_BRGR, quot); 2298 2299 /* set the mode, clock divisor, parity, stop bits and data size */ 2300 atmel_uart_writel(port, ATMEL_US_MR, mode); 2301 2302 /* 2303 * when switching the mode, set the RTS line state according to the 2304 * new mode, otherwise keep the former state 2305 */ 2306 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) { 2307 unsigned int rts_state; 2308 2309 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 2310 /* let the hardware control the RTS line */ 2311 rts_state = ATMEL_US_RTSDIS; 2312 } else { 2313 /* force RTS line to low level */ 2314 rts_state = ATMEL_US_RTSEN; 2315 } 2316 2317 atmel_uart_writel(port, ATMEL_US_CR, rts_state); 2318 } 2319 2320 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2321 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 2322 atmel_port->tx_stopped = false; 2323 2324 /* restore interrupts */ 2325 atmel_uart_writel(port, ATMEL_US_IER, imr); 2326 2327 /* CTS flow-control and modem-status interrupts */ 2328 if (UART_ENABLE_MS(port, termios->c_cflag)) 2329 atmel_enable_ms(port); 2330 else 2331 atmel_disable_ms(port); 2332 2333 spin_unlock_irqrestore(&port->lock, flags); 2334 } 2335 2336 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios) 2337 { 2338 if (termios->c_line == N_PPS) { 2339 port->flags |= UPF_HARDPPS_CD; 2340 spin_lock_irq(&port->lock); 2341 atmel_enable_ms(port); 2342 spin_unlock_irq(&port->lock); 2343 } else { 2344 port->flags &= ~UPF_HARDPPS_CD; 2345 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 2346 spin_lock_irq(&port->lock); 2347 atmel_disable_ms(port); 2348 spin_unlock_irq(&port->lock); 2349 } 2350 } 2351 } 2352 2353 /* 2354 * Return string describing the specified port 2355 */ 2356 static const char *atmel_type(struct uart_port *port) 2357 { 2358 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; 2359 } 2360 2361 /* 2362 * Release the memory region(s) being used by 'port'. 2363 */ 2364 static void atmel_release_port(struct uart_port *port) 2365 { 2366 struct platform_device *mpdev = to_platform_device(port->dev->parent); 2367 int size = resource_size(mpdev->resource); 2368 2369 release_mem_region(port->mapbase, size); 2370 2371 if (port->flags & UPF_IOREMAP) { 2372 iounmap(port->membase); 2373 port->membase = NULL; 2374 } 2375 } 2376 2377 /* 2378 * Request the memory region(s) being used by 'port'. 2379 */ 2380 static int atmel_request_port(struct uart_port *port) 2381 { 2382 struct platform_device *mpdev = to_platform_device(port->dev->parent); 2383 int size = resource_size(mpdev->resource); 2384 2385 if (!request_mem_region(port->mapbase, size, "atmel_serial")) 2386 return -EBUSY; 2387 2388 if (port->flags & UPF_IOREMAP) { 2389 port->membase = ioremap(port->mapbase, size); 2390 if (port->membase == NULL) { 2391 release_mem_region(port->mapbase, size); 2392 return -ENOMEM; 2393 } 2394 } 2395 2396 return 0; 2397 } 2398 2399 /* 2400 * Configure/autoconfigure the port. 2401 */ 2402 static void atmel_config_port(struct uart_port *port, int flags) 2403 { 2404 if (flags & UART_CONFIG_TYPE) { 2405 port->type = PORT_ATMEL; 2406 atmel_request_port(port); 2407 } 2408 } 2409 2410 /* 2411 * Verify the new serial_struct (for TIOCSSERIAL). 2412 */ 2413 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) 2414 { 2415 int ret = 0; 2416 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) 2417 ret = -EINVAL; 2418 if (port->irq != ser->irq) 2419 ret = -EINVAL; 2420 if (ser->io_type != SERIAL_IO_MEM) 2421 ret = -EINVAL; 2422 if (port->uartclk / 16 != ser->baud_base) 2423 ret = -EINVAL; 2424 if (port->mapbase != (unsigned long)ser->iomem_base) 2425 ret = -EINVAL; 2426 if (port->iobase != ser->port) 2427 ret = -EINVAL; 2428 if (ser->hub6 != 0) 2429 ret = -EINVAL; 2430 return ret; 2431 } 2432 2433 #ifdef CONFIG_CONSOLE_POLL 2434 static int atmel_poll_get_char(struct uart_port *port) 2435 { 2436 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY)) 2437 cpu_relax(); 2438 2439 return atmel_uart_read_char(port); 2440 } 2441 2442 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) 2443 { 2444 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) 2445 cpu_relax(); 2446 2447 atmel_uart_write_char(port, ch); 2448 } 2449 #endif 2450 2451 static const struct uart_ops atmel_pops = { 2452 .tx_empty = atmel_tx_empty, 2453 .set_mctrl = atmel_set_mctrl, 2454 .get_mctrl = atmel_get_mctrl, 2455 .stop_tx = atmel_stop_tx, 2456 .start_tx = atmel_start_tx, 2457 .stop_rx = atmel_stop_rx, 2458 .enable_ms = atmel_enable_ms, 2459 .break_ctl = atmel_break_ctl, 2460 .startup = atmel_startup, 2461 .shutdown = atmel_shutdown, 2462 .flush_buffer = atmel_flush_buffer, 2463 .set_termios = atmel_set_termios, 2464 .set_ldisc = atmel_set_ldisc, 2465 .type = atmel_type, 2466 .release_port = atmel_release_port, 2467 .request_port = atmel_request_port, 2468 .config_port = atmel_config_port, 2469 .verify_port = atmel_verify_port, 2470 .pm = atmel_serial_pm, 2471 #ifdef CONFIG_CONSOLE_POLL 2472 .poll_get_char = atmel_poll_get_char, 2473 .poll_put_char = atmel_poll_put_char, 2474 #endif 2475 }; 2476 2477 /* 2478 * Configure the port from the platform device resource info. 2479 */ 2480 static int atmel_init_port(struct atmel_uart_port *atmel_port, 2481 struct platform_device *pdev) 2482 { 2483 int ret; 2484 struct uart_port *port = &atmel_port->uart; 2485 struct platform_device *mpdev = to_platform_device(pdev->dev.parent); 2486 2487 atmel_init_property(atmel_port, pdev); 2488 atmel_set_ops(port); 2489 2490 port->iotype = UPIO_MEM; 2491 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; 2492 port->ops = &atmel_pops; 2493 port->fifosize = 1; 2494 port->dev = &pdev->dev; 2495 port->mapbase = mpdev->resource[0].start; 2496 port->irq = platform_get_irq(mpdev, 0); 2497 port->rs485_config = atmel_config_rs485; 2498 port->iso7816_config = atmel_config_iso7816; 2499 port->membase = NULL; 2500 2501 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); 2502 2503 ret = uart_get_rs485_mode(port); 2504 if (ret) 2505 return ret; 2506 2507 /* for console, the clock could already be configured */ 2508 if (!atmel_port->clk) { 2509 atmel_port->clk = clk_get(&mpdev->dev, "usart"); 2510 if (IS_ERR(atmel_port->clk)) { 2511 ret = PTR_ERR(atmel_port->clk); 2512 atmel_port->clk = NULL; 2513 return ret; 2514 } 2515 ret = clk_prepare_enable(atmel_port->clk); 2516 if (ret) { 2517 clk_put(atmel_port->clk); 2518 atmel_port->clk = NULL; 2519 return ret; 2520 } 2521 port->uartclk = clk_get_rate(atmel_port->clk); 2522 clk_disable_unprepare(atmel_port->clk); 2523 /* only enable clock when USART is in use */ 2524 } 2525 2526 /* 2527 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or 2528 * ENDTX|TXBUFE 2529 */ 2530 if (atmel_uart_is_half_duplex(port)) 2531 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 2532 else if (atmel_use_pdc_tx(port)) { 2533 port->fifosize = PDC_BUFFER_SIZE; 2534 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; 2535 } else { 2536 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 2537 } 2538 2539 return 0; 2540 } 2541 2542 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2543 static void atmel_console_putchar(struct uart_port *port, int ch) 2544 { 2545 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) 2546 cpu_relax(); 2547 atmel_uart_write_char(port, ch); 2548 } 2549 2550 /* 2551 * Interrupts are disabled on entering 2552 */ 2553 static void atmel_console_write(struct console *co, const char *s, u_int count) 2554 { 2555 struct uart_port *port = &atmel_ports[co->index].uart; 2556 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2557 unsigned int status, imr; 2558 unsigned int pdc_tx; 2559 2560 /* 2561 * First, save IMR and then disable interrupts 2562 */ 2563 imr = atmel_uart_readl(port, ATMEL_US_IMR); 2564 atmel_uart_writel(port, ATMEL_US_IDR, 2565 ATMEL_US_RXRDY | atmel_port->tx_done_mask); 2566 2567 /* Store PDC transmit status and disable it */ 2568 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN; 2569 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 2570 2571 /* Make sure that tx path is actually able to send characters */ 2572 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN); 2573 atmel_port->tx_stopped = false; 2574 2575 uart_console_write(port, s, count, atmel_console_putchar); 2576 2577 /* 2578 * Finally, wait for transmitter to become empty 2579 * and restore IMR 2580 */ 2581 do { 2582 status = atmel_uart_readl(port, ATMEL_US_CSR); 2583 } while (!(status & ATMEL_US_TXRDY)); 2584 2585 /* Restore PDC transmit status */ 2586 if (pdc_tx) 2587 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 2588 2589 /* set interrupts back the way they were */ 2590 atmel_uart_writel(port, ATMEL_US_IER, imr); 2591 } 2592 2593 /* 2594 * If the port was already initialised (eg, by a boot loader), 2595 * try to determine the current setup. 2596 */ 2597 static void __init atmel_console_get_options(struct uart_port *port, int *baud, 2598 int *parity, int *bits) 2599 { 2600 unsigned int mr, quot; 2601 2602 /* 2603 * If the baud rate generator isn't running, the port wasn't 2604 * initialized by the boot loader. 2605 */ 2606 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD; 2607 if (!quot) 2608 return; 2609 2610 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL; 2611 if (mr == ATMEL_US_CHRL_8) 2612 *bits = 8; 2613 else 2614 *bits = 7; 2615 2616 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR; 2617 if (mr == ATMEL_US_PAR_EVEN) 2618 *parity = 'e'; 2619 else if (mr == ATMEL_US_PAR_ODD) 2620 *parity = 'o'; 2621 2622 /* 2623 * The serial core only rounds down when matching this to a 2624 * supported baud rate. Make sure we don't end up slightly 2625 * lower than one of those, as it would make us fall through 2626 * to a much lower baud rate than we really want. 2627 */ 2628 *baud = port->uartclk / (16 * (quot - 1)); 2629 } 2630 2631 static int __init atmel_console_setup(struct console *co, char *options) 2632 { 2633 int ret; 2634 struct uart_port *port = &atmel_ports[co->index].uart; 2635 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2636 int baud = 115200; 2637 int bits = 8; 2638 int parity = 'n'; 2639 int flow = 'n'; 2640 2641 if (port->membase == NULL) { 2642 /* Port not initialized yet - delay setup */ 2643 return -ENODEV; 2644 } 2645 2646 ret = clk_prepare_enable(atmel_ports[co->index].clk); 2647 if (ret) 2648 return ret; 2649 2650 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2651 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2652 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 2653 atmel_port->tx_stopped = false; 2654 2655 if (options) 2656 uart_parse_options(options, &baud, &parity, &bits, &flow); 2657 else 2658 atmel_console_get_options(port, &baud, &parity, &bits); 2659 2660 return uart_set_options(port, co, baud, parity, bits, flow); 2661 } 2662 2663 static struct uart_driver atmel_uart; 2664 2665 static struct console atmel_console = { 2666 .name = ATMEL_DEVICENAME, 2667 .write = atmel_console_write, 2668 .device = uart_console_device, 2669 .setup = atmel_console_setup, 2670 .flags = CON_PRINTBUFFER, 2671 .index = -1, 2672 .data = &atmel_uart, 2673 }; 2674 2675 #define ATMEL_CONSOLE_DEVICE (&atmel_console) 2676 2677 #else 2678 #define ATMEL_CONSOLE_DEVICE NULL 2679 #endif 2680 2681 static struct uart_driver atmel_uart = { 2682 .owner = THIS_MODULE, 2683 .driver_name = "atmel_serial", 2684 .dev_name = ATMEL_DEVICENAME, 2685 .major = SERIAL_ATMEL_MAJOR, 2686 .minor = MINOR_START, 2687 .nr = ATMEL_MAX_UART, 2688 .cons = ATMEL_CONSOLE_DEVICE, 2689 }; 2690 2691 #ifdef CONFIG_PM 2692 static bool atmel_serial_clk_will_stop(void) 2693 { 2694 #ifdef CONFIG_ARCH_AT91 2695 return at91_suspend_entering_slow_clock(); 2696 #else 2697 return false; 2698 #endif 2699 } 2700 2701 static int atmel_serial_suspend(struct platform_device *pdev, 2702 pm_message_t state) 2703 { 2704 struct uart_port *port = platform_get_drvdata(pdev); 2705 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2706 2707 if (uart_console(port) && console_suspend_enabled) { 2708 /* Drain the TX shifter */ 2709 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & 2710 ATMEL_US_TXEMPTY)) 2711 cpu_relax(); 2712 } 2713 2714 if (uart_console(port) && !console_suspend_enabled) { 2715 /* Cache register values as we won't get a full shutdown/startup 2716 * cycle 2717 */ 2718 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR); 2719 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR); 2720 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR); 2721 atmel_port->cache.rtor = atmel_uart_readl(port, 2722 atmel_port->rtor); 2723 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR); 2724 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR); 2725 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR); 2726 } 2727 2728 /* we can not wake up if we're running on slow clock */ 2729 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); 2730 if (atmel_serial_clk_will_stop()) { 2731 unsigned long flags; 2732 2733 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2734 atmel_port->suspended = true; 2735 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2736 device_set_wakeup_enable(&pdev->dev, 0); 2737 } 2738 2739 uart_suspend_port(&atmel_uart, port); 2740 2741 return 0; 2742 } 2743 2744 static int atmel_serial_resume(struct platform_device *pdev) 2745 { 2746 struct uart_port *port = platform_get_drvdata(pdev); 2747 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2748 unsigned long flags; 2749 2750 if (uart_console(port) && !console_suspend_enabled) { 2751 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr); 2752 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr); 2753 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr); 2754 atmel_uart_writel(port, atmel_port->rtor, 2755 atmel_port->cache.rtor); 2756 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr); 2757 2758 if (atmel_port->fifo_size) { 2759 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN | 2760 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR); 2761 atmel_uart_writel(port, ATMEL_US_FMR, 2762 atmel_port->cache.fmr); 2763 atmel_uart_writel(port, ATMEL_US_FIER, 2764 atmel_port->cache.fimr); 2765 } 2766 atmel_start_rx(port); 2767 } 2768 2769 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2770 if (atmel_port->pending) { 2771 atmel_handle_receive(port, atmel_port->pending); 2772 atmel_handle_status(port, atmel_port->pending, 2773 atmel_port->pending_status); 2774 atmel_handle_transmit(port, atmel_port->pending); 2775 atmel_port->pending = 0; 2776 } 2777 atmel_port->suspended = false; 2778 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2779 2780 uart_resume_port(&atmel_uart, port); 2781 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); 2782 2783 return 0; 2784 } 2785 #else 2786 #define atmel_serial_suspend NULL 2787 #define atmel_serial_resume NULL 2788 #endif 2789 2790 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port, 2791 struct platform_device *pdev) 2792 { 2793 atmel_port->fifo_size = 0; 2794 atmel_port->rts_low = 0; 2795 atmel_port->rts_high = 0; 2796 2797 if (of_property_read_u32(pdev->dev.of_node, 2798 "atmel,fifo-size", 2799 &atmel_port->fifo_size)) 2800 return; 2801 2802 if (!atmel_port->fifo_size) 2803 return; 2804 2805 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) { 2806 atmel_port->fifo_size = 0; 2807 dev_err(&pdev->dev, "Invalid FIFO size\n"); 2808 return; 2809 } 2810 2811 /* 2812 * 0 <= rts_low <= rts_high <= fifo_size 2813 * Once their CTS line asserted by the remote peer, some x86 UARTs tend 2814 * to flush their internal TX FIFO, commonly up to 16 data, before 2815 * actually stopping to send new data. So we try to set the RTS High 2816 * Threshold to a reasonably high value respecting this 16 data 2817 * empirical rule when possible. 2818 */ 2819 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1, 2820 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET); 2821 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2, 2822 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET); 2823 2824 dev_info(&pdev->dev, "Using FIFO (%u data)\n", 2825 atmel_port->fifo_size); 2826 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n", 2827 atmel_port->rts_high); 2828 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n", 2829 atmel_port->rts_low); 2830 } 2831 2832 static int atmel_serial_probe(struct platform_device *pdev) 2833 { 2834 struct atmel_uart_port *atmel_port; 2835 struct device_node *np = pdev->dev.parent->of_node; 2836 void *data; 2837 int ret; 2838 bool rs485_enabled; 2839 2840 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); 2841 2842 /* 2843 * In device tree there is no node with "atmel,at91rm9200-usart-serial" 2844 * as compatible string. This driver is probed by at91-usart mfd driver 2845 * which is just a wrapper over the atmel_serial driver and 2846 * spi-at91-usart driver. All attributes needed by this driver are 2847 * found in of_node of parent. 2848 */ 2849 pdev->dev.of_node = np; 2850 2851 ret = of_alias_get_id(np, "serial"); 2852 if (ret < 0) 2853 /* port id not found in platform data nor device-tree aliases: 2854 * auto-enumerate it */ 2855 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); 2856 2857 if (ret >= ATMEL_MAX_UART) { 2858 ret = -ENODEV; 2859 goto err; 2860 } 2861 2862 if (test_and_set_bit(ret, atmel_ports_in_use)) { 2863 /* port already in use */ 2864 ret = -EBUSY; 2865 goto err; 2866 } 2867 2868 atmel_port = &atmel_ports[ret]; 2869 atmel_port->backup_imr = 0; 2870 atmel_port->uart.line = ret; 2871 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE); 2872 atmel_serial_probe_fifos(atmel_port, pdev); 2873 2874 atomic_set(&atmel_port->tasklet_shutdown, 0); 2875 spin_lock_init(&atmel_port->lock_suspended); 2876 2877 ret = atmel_init_port(atmel_port, pdev); 2878 if (ret) 2879 goto err_clear_bit; 2880 2881 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0); 2882 if (IS_ERR(atmel_port->gpios)) { 2883 ret = PTR_ERR(atmel_port->gpios); 2884 goto err_clear_bit; 2885 } 2886 2887 if (!atmel_use_pdc_rx(&atmel_port->uart)) { 2888 ret = -ENOMEM; 2889 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE, 2890 sizeof(struct atmel_uart_char), 2891 GFP_KERNEL); 2892 if (!data) 2893 goto err_alloc_ring; 2894 atmel_port->rx_ring.buf = data; 2895 } 2896 2897 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED; 2898 2899 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart); 2900 if (ret) 2901 goto err_add_port; 2902 2903 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2904 if (uart_console(&atmel_port->uart) 2905 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { 2906 /* 2907 * The serial core enabled the clock for us, so undo 2908 * the clk_prepare_enable() in atmel_console_setup() 2909 */ 2910 clk_disable_unprepare(atmel_port->clk); 2911 } 2912 #endif 2913 2914 device_init_wakeup(&pdev->dev, 1); 2915 platform_set_drvdata(pdev, atmel_port); 2916 2917 /* 2918 * The peripheral clock has been disabled by atmel_init_port(): 2919 * enable it before accessing I/O registers 2920 */ 2921 clk_prepare_enable(atmel_port->clk); 2922 2923 if (rs485_enabled) { 2924 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR, 2925 ATMEL_US_USMODE_NORMAL); 2926 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR, 2927 ATMEL_US_RTSEN); 2928 } 2929 2930 /* 2931 * Get port name of usart or uart 2932 */ 2933 atmel_get_ip_name(&atmel_port->uart); 2934 2935 /* 2936 * The peripheral clock can now safely be disabled till the port 2937 * is used 2938 */ 2939 clk_disable_unprepare(atmel_port->clk); 2940 2941 return 0; 2942 2943 err_add_port: 2944 kfree(atmel_port->rx_ring.buf); 2945 atmel_port->rx_ring.buf = NULL; 2946 err_alloc_ring: 2947 if (!uart_console(&atmel_port->uart)) { 2948 clk_put(atmel_port->clk); 2949 atmel_port->clk = NULL; 2950 } 2951 err_clear_bit: 2952 clear_bit(atmel_port->uart.line, atmel_ports_in_use); 2953 err: 2954 return ret; 2955 } 2956 2957 /* 2958 * Even if the driver is not modular, it makes sense to be able to 2959 * unbind a device: there can be many bound devices, and there are 2960 * situations where dynamic binding and unbinding can be useful. 2961 * 2962 * For example, a connected device can require a specific firmware update 2963 * protocol that needs bitbanging on IO lines, but use the regular serial 2964 * port in the normal case. 2965 */ 2966 static int atmel_serial_remove(struct platform_device *pdev) 2967 { 2968 struct uart_port *port = platform_get_drvdata(pdev); 2969 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2970 int ret = 0; 2971 2972 tasklet_kill(&atmel_port->tasklet_rx); 2973 tasklet_kill(&atmel_port->tasklet_tx); 2974 2975 device_init_wakeup(&pdev->dev, 0); 2976 2977 ret = uart_remove_one_port(&atmel_uart, port); 2978 2979 kfree(atmel_port->rx_ring.buf); 2980 2981 /* "port" is allocated statically, so we shouldn't free it */ 2982 2983 clear_bit(port->line, atmel_ports_in_use); 2984 2985 clk_put(atmel_port->clk); 2986 atmel_port->clk = NULL; 2987 pdev->dev.of_node = NULL; 2988 2989 return ret; 2990 } 2991 2992 static struct platform_driver atmel_serial_driver = { 2993 .probe = atmel_serial_probe, 2994 .remove = atmel_serial_remove, 2995 .suspend = atmel_serial_suspend, 2996 .resume = atmel_serial_resume, 2997 .driver = { 2998 .name = "atmel_usart_serial", 2999 .of_match_table = of_match_ptr(atmel_serial_dt_ids), 3000 }, 3001 }; 3002 3003 static int __init atmel_serial_init(void) 3004 { 3005 int ret; 3006 3007 ret = uart_register_driver(&atmel_uart); 3008 if (ret) 3009 return ret; 3010 3011 ret = platform_driver_register(&atmel_serial_driver); 3012 if (ret) 3013 uart_unregister_driver(&atmel_uart); 3014 3015 return ret; 3016 } 3017 device_initcall(atmel_serial_init); 3018