1 /* 2 * Driver for Atmel AT91 / AT32 Serial ports 3 * Copyright (C) 2003 Rick Bronson 4 * 5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. 6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 7 * 8 * DMA support added by Chip Coldwell. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 #include <linux/module.h> 26 #include <linux/tty.h> 27 #include <linux/ioport.h> 28 #include <linux/slab.h> 29 #include <linux/init.h> 30 #include <linux/serial.h> 31 #include <linux/clk.h> 32 #include <linux/console.h> 33 #include <linux/sysrq.h> 34 #include <linux/tty_flip.h> 35 #include <linux/platform_device.h> 36 #include <linux/of.h> 37 #include <linux/of_device.h> 38 #include <linux/of_gpio.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/dmaengine.h> 41 #include <linux/atmel_pdc.h> 42 #include <linux/atmel_serial.h> 43 #include <linux/uaccess.h> 44 #include <linux/platform_data/atmel.h> 45 #include <linux/timer.h> 46 #include <linux/gpio.h> 47 #include <linux/gpio/consumer.h> 48 #include <linux/err.h> 49 #include <linux/irq.h> 50 #include <linux/suspend.h> 51 52 #include <asm/io.h> 53 #include <asm/ioctls.h> 54 55 #define PDC_BUFFER_SIZE 512 56 /* Revisit: We should calculate this based on the actual port settings */ 57 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ 58 59 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 60 #define SUPPORT_SYSRQ 61 #endif 62 63 #include <linux/serial_core.h> 64 65 #include "serial_mctrl_gpio.h" 66 67 static void atmel_start_rx(struct uart_port *port); 68 static void atmel_stop_rx(struct uart_port *port); 69 70 #ifdef CONFIG_SERIAL_ATMEL_TTYAT 71 72 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we 73 * should coexist with the 8250 driver, such as if we have an external 16C550 74 * UART. */ 75 #define SERIAL_ATMEL_MAJOR 204 76 #define MINOR_START 154 77 #define ATMEL_DEVICENAME "ttyAT" 78 79 #else 80 81 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port 82 * name, but it is legally reserved for the 8250 driver. */ 83 #define SERIAL_ATMEL_MAJOR TTY_MAJOR 84 #define MINOR_START 64 85 #define ATMEL_DEVICENAME "ttyS" 86 87 #endif 88 89 #define ATMEL_ISR_PASS_LIMIT 256 90 91 /* UART registers. CR is write-only, hence no GET macro */ 92 #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) 93 #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) 94 #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) 95 #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) 96 #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) 97 #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) 98 #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) 99 #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) 100 #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) 101 #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) 102 #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) 103 #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) 104 #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR) 105 #define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME) 106 #define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION) 107 108 /* PDC registers */ 109 #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) 110 #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) 111 112 #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) 113 #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) 114 #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) 115 #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) 116 #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) 117 118 #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) 119 #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) 120 #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR) 121 122 struct atmel_dma_buffer { 123 unsigned char *buf; 124 dma_addr_t dma_addr; 125 unsigned int dma_size; 126 unsigned int ofs; 127 }; 128 129 struct atmel_uart_char { 130 u16 status; 131 u16 ch; 132 }; 133 134 #define ATMEL_SERIAL_RINGSIZE 1024 135 136 /* 137 * We wrap our port structure around the generic uart_port. 138 */ 139 struct atmel_uart_port { 140 struct uart_port uart; /* uart */ 141 struct clk *clk; /* uart clock */ 142 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ 143 u32 backup_imr; /* IMR saved during suspend */ 144 int break_active; /* break being received */ 145 146 bool use_dma_rx; /* enable DMA receiver */ 147 bool use_pdc_rx; /* enable PDC receiver */ 148 short pdc_rx_idx; /* current PDC RX buffer */ 149 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ 150 151 bool use_dma_tx; /* enable DMA transmitter */ 152 bool use_pdc_tx; /* enable PDC transmitter */ 153 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ 154 155 spinlock_t lock_tx; /* port lock */ 156 spinlock_t lock_rx; /* port lock */ 157 struct dma_chan *chan_tx; 158 struct dma_chan *chan_rx; 159 struct dma_async_tx_descriptor *desc_tx; 160 struct dma_async_tx_descriptor *desc_rx; 161 dma_cookie_t cookie_tx; 162 dma_cookie_t cookie_rx; 163 struct scatterlist sg_tx; 164 struct scatterlist sg_rx; 165 struct tasklet_struct tasklet; 166 unsigned int irq_status; 167 unsigned int irq_status_prev; 168 unsigned int status_change; 169 170 struct circ_buf rx_ring; 171 172 struct mctrl_gpios *gpios; 173 int gpio_irq[UART_GPIO_MAX]; 174 unsigned int tx_done_mask; 175 bool ms_irq_enabled; 176 bool is_usart; /* usart or uart */ 177 struct timer_list uart_timer; /* uart timer */ 178 179 bool suspended; 180 unsigned int pending; 181 unsigned int pending_status; 182 spinlock_t lock_suspended; 183 184 int (*prepare_rx)(struct uart_port *port); 185 int (*prepare_tx)(struct uart_port *port); 186 void (*schedule_rx)(struct uart_port *port); 187 void (*schedule_tx)(struct uart_port *port); 188 void (*release_rx)(struct uart_port *port); 189 void (*release_tx)(struct uart_port *port); 190 }; 191 192 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; 193 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); 194 195 #ifdef SUPPORT_SYSRQ 196 static struct console atmel_console; 197 #endif 198 199 #if defined(CONFIG_OF) 200 static const struct of_device_id atmel_serial_dt_ids[] = { 201 { .compatible = "atmel,at91rm9200-usart" }, 202 { .compatible = "atmel,at91sam9260-usart" }, 203 { /* sentinel */ } 204 }; 205 206 MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids); 207 #endif 208 209 static inline struct atmel_uart_port * 210 to_atmel_uart_port(struct uart_port *uart) 211 { 212 return container_of(uart, struct atmel_uart_port, uart); 213 } 214 215 #ifdef CONFIG_SERIAL_ATMEL_PDC 216 static bool atmel_use_pdc_rx(struct uart_port *port) 217 { 218 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 219 220 return atmel_port->use_pdc_rx; 221 } 222 223 static bool atmel_use_pdc_tx(struct uart_port *port) 224 { 225 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 226 227 return atmel_port->use_pdc_tx; 228 } 229 #else 230 static bool atmel_use_pdc_rx(struct uart_port *port) 231 { 232 return false; 233 } 234 235 static bool atmel_use_pdc_tx(struct uart_port *port) 236 { 237 return false; 238 } 239 #endif 240 241 static bool atmel_use_dma_tx(struct uart_port *port) 242 { 243 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 244 245 return atmel_port->use_dma_tx; 246 } 247 248 static bool atmel_use_dma_rx(struct uart_port *port) 249 { 250 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 251 252 return atmel_port->use_dma_rx; 253 } 254 255 static unsigned int atmel_get_lines_status(struct uart_port *port) 256 { 257 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 258 unsigned int status, ret = 0; 259 260 status = UART_GET_CSR(port); 261 262 mctrl_gpio_get(atmel_port->gpios, &ret); 263 264 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 265 UART_GPIO_CTS))) { 266 if (ret & TIOCM_CTS) 267 status &= ~ATMEL_US_CTS; 268 else 269 status |= ATMEL_US_CTS; 270 } 271 272 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 273 UART_GPIO_DSR))) { 274 if (ret & TIOCM_DSR) 275 status &= ~ATMEL_US_DSR; 276 else 277 status |= ATMEL_US_DSR; 278 } 279 280 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 281 UART_GPIO_RI))) { 282 if (ret & TIOCM_RI) 283 status &= ~ATMEL_US_RI; 284 else 285 status |= ATMEL_US_RI; 286 } 287 288 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 289 UART_GPIO_DCD))) { 290 if (ret & TIOCM_CD) 291 status &= ~ATMEL_US_DCD; 292 else 293 status |= ATMEL_US_DCD; 294 } 295 296 return status; 297 } 298 299 /* Enable or disable the rs485 support */ 300 static int atmel_config_rs485(struct uart_port *port, 301 struct serial_rs485 *rs485conf) 302 { 303 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 304 unsigned int mode; 305 306 /* Disable interrupts */ 307 UART_PUT_IDR(port, atmel_port->tx_done_mask); 308 309 mode = UART_GET_MR(port); 310 311 /* Resetting serial mode to RS232 (0x0) */ 312 mode &= ~ATMEL_US_USMODE; 313 314 port->rs485 = *rs485conf; 315 316 if (rs485conf->flags & SER_RS485_ENABLED) { 317 dev_dbg(port->dev, "Setting UART to RS485\n"); 318 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 319 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send); 320 mode |= ATMEL_US_USMODE_RS485; 321 } else { 322 dev_dbg(port->dev, "Setting UART to RS232\n"); 323 if (atmel_use_pdc_tx(port)) 324 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 325 ATMEL_US_TXBUFE; 326 else 327 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 328 } 329 UART_PUT_MR(port, mode); 330 331 /* Enable interrupts */ 332 UART_PUT_IER(port, atmel_port->tx_done_mask); 333 334 return 0; 335 } 336 337 /* 338 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. 339 */ 340 static u_int atmel_tx_empty(struct uart_port *port) 341 { 342 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; 343 } 344 345 /* 346 * Set state of the modem control output lines 347 */ 348 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) 349 { 350 unsigned int control = 0; 351 unsigned int mode = UART_GET_MR(port); 352 unsigned int rts_paused, rts_ready; 353 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 354 355 /* override mode to RS485 if needed, otherwise keep the current mode */ 356 if (port->rs485.flags & SER_RS485_ENABLED) { 357 UART_PUT_TTGR(port, port->rs485.delay_rts_after_send); 358 mode &= ~ATMEL_US_USMODE; 359 mode |= ATMEL_US_USMODE_RS485; 360 } 361 362 /* set the RTS line state according to the mode */ 363 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 364 /* force RTS line to high level */ 365 rts_paused = ATMEL_US_RTSEN; 366 367 /* give the control of the RTS line back to the hardware */ 368 rts_ready = ATMEL_US_RTSDIS; 369 } else { 370 /* force RTS line to high level */ 371 rts_paused = ATMEL_US_RTSDIS; 372 373 /* force RTS line to low level */ 374 rts_ready = ATMEL_US_RTSEN; 375 } 376 377 if (mctrl & TIOCM_RTS) 378 control |= rts_ready; 379 else 380 control |= rts_paused; 381 382 if (mctrl & TIOCM_DTR) 383 control |= ATMEL_US_DTREN; 384 else 385 control |= ATMEL_US_DTRDIS; 386 387 UART_PUT_CR(port, control); 388 389 mctrl_gpio_set(atmel_port->gpios, mctrl); 390 391 /* Local loopback mode? */ 392 mode &= ~ATMEL_US_CHMODE; 393 if (mctrl & TIOCM_LOOP) 394 mode |= ATMEL_US_CHMODE_LOC_LOOP; 395 else 396 mode |= ATMEL_US_CHMODE_NORMAL; 397 398 UART_PUT_MR(port, mode); 399 } 400 401 /* 402 * Get state of the modem control input lines 403 */ 404 static u_int atmel_get_mctrl(struct uart_port *port) 405 { 406 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 407 unsigned int ret = 0, status; 408 409 status = UART_GET_CSR(port); 410 411 /* 412 * The control signals are active low. 413 */ 414 if (!(status & ATMEL_US_DCD)) 415 ret |= TIOCM_CD; 416 if (!(status & ATMEL_US_CTS)) 417 ret |= TIOCM_CTS; 418 if (!(status & ATMEL_US_DSR)) 419 ret |= TIOCM_DSR; 420 if (!(status & ATMEL_US_RI)) 421 ret |= TIOCM_RI; 422 423 return mctrl_gpio_get(atmel_port->gpios, &ret); 424 } 425 426 /* 427 * Stop transmitting. 428 */ 429 static void atmel_stop_tx(struct uart_port *port) 430 { 431 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 432 433 if (atmel_use_pdc_tx(port)) { 434 /* disable PDC transmit */ 435 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 436 } 437 /* Disable interrupts */ 438 UART_PUT_IDR(port, atmel_port->tx_done_mask); 439 440 if ((port->rs485.flags & SER_RS485_ENABLED) && 441 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 442 atmel_start_rx(port); 443 } 444 445 /* 446 * Start transmitting. 447 */ 448 static void atmel_start_tx(struct uart_port *port) 449 { 450 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 451 452 if (atmel_use_pdc_tx(port)) { 453 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) 454 /* The transmitter is already running. Yes, we 455 really need this.*/ 456 return; 457 458 if ((port->rs485.flags & SER_RS485_ENABLED) && 459 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 460 atmel_stop_rx(port); 461 462 /* re-enable PDC transmit */ 463 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 464 } 465 /* Enable interrupts */ 466 UART_PUT_IER(port, atmel_port->tx_done_mask); 467 } 468 469 /* 470 * start receiving - port is in process of being opened. 471 */ 472 static void atmel_start_rx(struct uart_port *port) 473 { 474 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */ 475 476 UART_PUT_CR(port, ATMEL_US_RXEN); 477 478 if (atmel_use_pdc_rx(port)) { 479 /* enable PDC controller */ 480 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 481 port->read_status_mask); 482 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); 483 } else { 484 UART_PUT_IER(port, ATMEL_US_RXRDY); 485 } 486 } 487 488 /* 489 * Stop receiving - port is in process of being closed. 490 */ 491 static void atmel_stop_rx(struct uart_port *port) 492 { 493 UART_PUT_CR(port, ATMEL_US_RXDIS); 494 495 if (atmel_use_pdc_rx(port)) { 496 /* disable PDC receive */ 497 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); 498 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 499 port->read_status_mask); 500 } else { 501 UART_PUT_IDR(port, ATMEL_US_RXRDY); 502 } 503 } 504 505 /* 506 * Enable modem status interrupts 507 */ 508 static void atmel_enable_ms(struct uart_port *port) 509 { 510 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 511 uint32_t ier = 0; 512 513 /* 514 * Interrupt should not be enabled twice 515 */ 516 if (atmel_port->ms_irq_enabled) 517 return; 518 519 atmel_port->ms_irq_enabled = true; 520 521 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0) 522 enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]); 523 else 524 ier |= ATMEL_US_CTSIC; 525 526 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0) 527 enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]); 528 else 529 ier |= ATMEL_US_DSRIC; 530 531 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0) 532 enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]); 533 else 534 ier |= ATMEL_US_RIIC; 535 536 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0) 537 enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]); 538 else 539 ier |= ATMEL_US_DCDIC; 540 541 UART_PUT_IER(port, ier); 542 } 543 544 /* 545 * Disable modem status interrupts 546 */ 547 static void atmel_disable_ms(struct uart_port *port) 548 { 549 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 550 uint32_t idr = 0; 551 552 /* 553 * Interrupt should not be disabled twice 554 */ 555 if (!atmel_port->ms_irq_enabled) 556 return; 557 558 atmel_port->ms_irq_enabled = false; 559 560 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0) 561 disable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]); 562 else 563 idr |= ATMEL_US_CTSIC; 564 565 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0) 566 disable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]); 567 else 568 idr |= ATMEL_US_DSRIC; 569 570 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0) 571 disable_irq(atmel_port->gpio_irq[UART_GPIO_RI]); 572 else 573 idr |= ATMEL_US_RIIC; 574 575 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0) 576 disable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]); 577 else 578 idr |= ATMEL_US_DCDIC; 579 580 UART_PUT_IDR(port, idr); 581 } 582 583 /* 584 * Control the transmission of a break signal 585 */ 586 static void atmel_break_ctl(struct uart_port *port, int break_state) 587 { 588 if (break_state != 0) 589 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ 590 else 591 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ 592 } 593 594 /* 595 * Stores the incoming character in the ring buffer 596 */ 597 static void 598 atmel_buffer_rx_char(struct uart_port *port, unsigned int status, 599 unsigned int ch) 600 { 601 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 602 struct circ_buf *ring = &atmel_port->rx_ring; 603 struct atmel_uart_char *c; 604 605 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) 606 /* Buffer overflow, ignore char */ 607 return; 608 609 c = &((struct atmel_uart_char *)ring->buf)[ring->head]; 610 c->status = status; 611 c->ch = ch; 612 613 /* Make sure the character is stored before we update head. */ 614 smp_wmb(); 615 616 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 617 } 618 619 /* 620 * Deal with parity, framing and overrun errors. 621 */ 622 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) 623 { 624 /* clear error */ 625 UART_PUT_CR(port, ATMEL_US_RSTSTA); 626 627 if (status & ATMEL_US_RXBRK) { 628 /* ignore side-effect */ 629 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 630 port->icount.brk++; 631 } 632 if (status & ATMEL_US_PARE) 633 port->icount.parity++; 634 if (status & ATMEL_US_FRAME) 635 port->icount.frame++; 636 if (status & ATMEL_US_OVRE) 637 port->icount.overrun++; 638 } 639 640 /* 641 * Characters received (called from interrupt handler) 642 */ 643 static void atmel_rx_chars(struct uart_port *port) 644 { 645 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 646 unsigned int status, ch; 647 648 status = UART_GET_CSR(port); 649 while (status & ATMEL_US_RXRDY) { 650 ch = UART_GET_CHAR(port); 651 652 /* 653 * note that the error handling code is 654 * out of the main execution path 655 */ 656 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 657 | ATMEL_US_OVRE | ATMEL_US_RXBRK) 658 || atmel_port->break_active)) { 659 660 /* clear error */ 661 UART_PUT_CR(port, ATMEL_US_RSTSTA); 662 663 if (status & ATMEL_US_RXBRK 664 && !atmel_port->break_active) { 665 atmel_port->break_active = 1; 666 UART_PUT_IER(port, ATMEL_US_RXBRK); 667 } else { 668 /* 669 * This is either the end-of-break 670 * condition or we've received at 671 * least one character without RXBRK 672 * being set. In both cases, the next 673 * RXBRK will indicate start-of-break. 674 */ 675 UART_PUT_IDR(port, ATMEL_US_RXBRK); 676 status &= ~ATMEL_US_RXBRK; 677 atmel_port->break_active = 0; 678 } 679 } 680 681 atmel_buffer_rx_char(port, status, ch); 682 status = UART_GET_CSR(port); 683 } 684 685 tasklet_schedule(&atmel_port->tasklet); 686 } 687 688 /* 689 * Transmit characters (called from tasklet with TXRDY interrupt 690 * disabled) 691 */ 692 static void atmel_tx_chars(struct uart_port *port) 693 { 694 struct circ_buf *xmit = &port->state->xmit; 695 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 696 697 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) { 698 UART_PUT_CHAR(port, port->x_char); 699 port->icount.tx++; 700 port->x_char = 0; 701 } 702 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 703 return; 704 705 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) { 706 UART_PUT_CHAR(port, xmit->buf[xmit->tail]); 707 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 708 port->icount.tx++; 709 if (uart_circ_empty(xmit)) 710 break; 711 } 712 713 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 714 uart_write_wakeup(port); 715 716 if (!uart_circ_empty(xmit)) 717 /* Enable interrupts */ 718 UART_PUT_IER(port, atmel_port->tx_done_mask); 719 } 720 721 static void atmel_complete_tx_dma(void *arg) 722 { 723 struct atmel_uart_port *atmel_port = arg; 724 struct uart_port *port = &atmel_port->uart; 725 struct circ_buf *xmit = &port->state->xmit; 726 struct dma_chan *chan = atmel_port->chan_tx; 727 unsigned long flags; 728 729 spin_lock_irqsave(&port->lock, flags); 730 731 if (chan) 732 dmaengine_terminate_all(chan); 733 xmit->tail += sg_dma_len(&atmel_port->sg_tx); 734 xmit->tail &= UART_XMIT_SIZE - 1; 735 736 port->icount.tx += sg_dma_len(&atmel_port->sg_tx); 737 738 spin_lock_irq(&atmel_port->lock_tx); 739 async_tx_ack(atmel_port->desc_tx); 740 atmel_port->cookie_tx = -EINVAL; 741 atmel_port->desc_tx = NULL; 742 spin_unlock_irq(&atmel_port->lock_tx); 743 744 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 745 uart_write_wakeup(port); 746 747 /* 748 * xmit is a circular buffer so, if we have just send data from 749 * xmit->tail to the end of xmit->buf, now we have to transmit the 750 * remaining data from the beginning of xmit->buf to xmit->head. 751 */ 752 if (!uart_circ_empty(xmit)) 753 tasklet_schedule(&atmel_port->tasklet); 754 755 spin_unlock_irqrestore(&port->lock, flags); 756 } 757 758 static void atmel_release_tx_dma(struct uart_port *port) 759 { 760 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 761 struct dma_chan *chan = atmel_port->chan_tx; 762 763 if (chan) { 764 dmaengine_terminate_all(chan); 765 dma_release_channel(chan); 766 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, 767 DMA_TO_DEVICE); 768 } 769 770 atmel_port->desc_tx = NULL; 771 atmel_port->chan_tx = NULL; 772 atmel_port->cookie_tx = -EINVAL; 773 } 774 775 /* 776 * Called from tasklet with TXRDY interrupt is disabled. 777 */ 778 static void atmel_tx_dma(struct uart_port *port) 779 { 780 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 781 struct circ_buf *xmit = &port->state->xmit; 782 struct dma_chan *chan = atmel_port->chan_tx; 783 struct dma_async_tx_descriptor *desc; 784 struct scatterlist *sg = &atmel_port->sg_tx; 785 786 /* Make sure we have an idle channel */ 787 if (atmel_port->desc_tx != NULL) 788 return; 789 790 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 791 /* 792 * DMA is idle now. 793 * Port xmit buffer is already mapped, 794 * and it is one page... Just adjust 795 * offsets and lengths. Since it is a circular buffer, 796 * we have to transmit till the end, and then the rest. 797 * Take the port lock to get a 798 * consistent xmit buffer state. 799 */ 800 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 801 sg_dma_address(sg) = (sg_dma_address(sg) & 802 ~(UART_XMIT_SIZE - 1)) 803 + sg->offset; 804 sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head, 805 xmit->tail, 806 UART_XMIT_SIZE); 807 BUG_ON(!sg_dma_len(sg)); 808 809 desc = dmaengine_prep_slave_sg(chan, 810 sg, 811 1, 812 DMA_MEM_TO_DEV, 813 DMA_PREP_INTERRUPT | 814 DMA_CTRL_ACK); 815 if (!desc) { 816 dev_err(port->dev, "Failed to send via dma!\n"); 817 return; 818 } 819 820 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); 821 822 atmel_port->desc_tx = desc; 823 desc->callback = atmel_complete_tx_dma; 824 desc->callback_param = atmel_port; 825 atmel_port->cookie_tx = dmaengine_submit(desc); 826 827 } else { 828 if (port->rs485.flags & SER_RS485_ENABLED) { 829 /* DMA done, stop TX, start RX for RS485 */ 830 atmel_start_rx(port); 831 } 832 } 833 834 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 835 uart_write_wakeup(port); 836 } 837 838 static int atmel_prepare_tx_dma(struct uart_port *port) 839 { 840 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 841 dma_cap_mask_t mask; 842 struct dma_slave_config config; 843 int ret, nent; 844 845 dma_cap_zero(mask); 846 dma_cap_set(DMA_SLAVE, mask); 847 848 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx"); 849 if (atmel_port->chan_tx == NULL) 850 goto chan_err; 851 dev_info(port->dev, "using %s for tx DMA transfers\n", 852 dma_chan_name(atmel_port->chan_tx)); 853 854 spin_lock_init(&atmel_port->lock_tx); 855 sg_init_table(&atmel_port->sg_tx, 1); 856 /* UART circular tx buffer is an aligned page. */ 857 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf)); 858 sg_set_page(&atmel_port->sg_tx, 859 virt_to_page(port->state->xmit.buf), 860 UART_XMIT_SIZE, 861 (int)port->state->xmit.buf & ~PAGE_MASK); 862 nent = dma_map_sg(port->dev, 863 &atmel_port->sg_tx, 864 1, 865 DMA_TO_DEVICE); 866 867 if (!nent) { 868 dev_dbg(port->dev, "need to release resource of dma\n"); 869 goto chan_err; 870 } else { 871 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 872 sg_dma_len(&atmel_port->sg_tx), 873 port->state->xmit.buf, 874 sg_dma_address(&atmel_port->sg_tx)); 875 } 876 877 /* Configure the slave DMA */ 878 memset(&config, 0, sizeof(config)); 879 config.direction = DMA_MEM_TO_DEV; 880 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 881 config.dst_addr = port->mapbase + ATMEL_US_THR; 882 config.dst_maxburst = 1; 883 884 ret = dmaengine_slave_config(atmel_port->chan_tx, 885 &config); 886 if (ret) { 887 dev_err(port->dev, "DMA tx slave configuration failed\n"); 888 goto chan_err; 889 } 890 891 return 0; 892 893 chan_err: 894 dev_err(port->dev, "TX channel not available, switch to pio\n"); 895 atmel_port->use_dma_tx = 0; 896 if (atmel_port->chan_tx) 897 atmel_release_tx_dma(port); 898 return -EINVAL; 899 } 900 901 static void atmel_complete_rx_dma(void *arg) 902 { 903 struct uart_port *port = arg; 904 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 905 906 tasklet_schedule(&atmel_port->tasklet); 907 } 908 909 static void atmel_release_rx_dma(struct uart_port *port) 910 { 911 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 912 struct dma_chan *chan = atmel_port->chan_rx; 913 914 if (chan) { 915 dmaengine_terminate_all(chan); 916 dma_release_channel(chan); 917 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, 918 DMA_FROM_DEVICE); 919 } 920 921 atmel_port->desc_rx = NULL; 922 atmel_port->chan_rx = NULL; 923 atmel_port->cookie_rx = -EINVAL; 924 } 925 926 static void atmel_rx_from_dma(struct uart_port *port) 927 { 928 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 929 struct tty_port *tport = &port->state->port; 930 struct circ_buf *ring = &atmel_port->rx_ring; 931 struct dma_chan *chan = atmel_port->chan_rx; 932 struct dma_tx_state state; 933 enum dma_status dmastat; 934 size_t count; 935 936 937 /* Reset the UART timeout early so that we don't miss one */ 938 UART_PUT_CR(port, ATMEL_US_STTTO); 939 dmastat = dmaengine_tx_status(chan, 940 atmel_port->cookie_rx, 941 &state); 942 /* Restart a new tasklet if DMA status is error */ 943 if (dmastat == DMA_ERROR) { 944 dev_dbg(port->dev, "Get residue error, restart tasklet\n"); 945 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 946 tasklet_schedule(&atmel_port->tasklet); 947 return; 948 } 949 950 /* CPU claims ownership of RX DMA buffer */ 951 dma_sync_sg_for_cpu(port->dev, 952 &atmel_port->sg_rx, 953 1, 954 DMA_FROM_DEVICE); 955 956 /* 957 * ring->head points to the end of data already written by the DMA. 958 * ring->tail points to the beginning of data to be read by the 959 * framework. 960 * The current transfer size should not be larger than the dma buffer 961 * length. 962 */ 963 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue; 964 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx)); 965 /* 966 * At this point ring->head may point to the first byte right after the 967 * last byte of the dma buffer: 968 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx) 969 * 970 * However ring->tail must always points inside the dma buffer: 971 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1 972 * 973 * Since we use a ring buffer, we have to handle the case 974 * where head is lower than tail. In such a case, we first read from 975 * tail to the end of the buffer then reset tail. 976 */ 977 if (ring->head < ring->tail) { 978 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail; 979 980 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 981 ring->tail = 0; 982 port->icount.rx += count; 983 } 984 985 /* Finally we read data from tail to head */ 986 if (ring->tail < ring->head) { 987 count = ring->head - ring->tail; 988 989 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 990 /* Wrap ring->head if needed */ 991 if (ring->head >= sg_dma_len(&atmel_port->sg_rx)) 992 ring->head = 0; 993 ring->tail = ring->head; 994 port->icount.rx += count; 995 } 996 997 /* USART retreives ownership of RX DMA buffer */ 998 dma_sync_sg_for_device(port->dev, 999 &atmel_port->sg_rx, 1000 1, 1001 DMA_FROM_DEVICE); 1002 1003 /* 1004 * Drop the lock here since it might end up calling 1005 * uart_start(), which takes the lock. 1006 */ 1007 spin_unlock(&port->lock); 1008 tty_flip_buffer_push(tport); 1009 spin_lock(&port->lock); 1010 1011 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 1012 } 1013 1014 static int atmel_prepare_rx_dma(struct uart_port *port) 1015 { 1016 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1017 struct dma_async_tx_descriptor *desc; 1018 dma_cap_mask_t mask; 1019 struct dma_slave_config config; 1020 struct circ_buf *ring; 1021 int ret, nent; 1022 1023 ring = &atmel_port->rx_ring; 1024 1025 dma_cap_zero(mask); 1026 dma_cap_set(DMA_CYCLIC, mask); 1027 1028 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx"); 1029 if (atmel_port->chan_rx == NULL) 1030 goto chan_err; 1031 dev_info(port->dev, "using %s for rx DMA transfers\n", 1032 dma_chan_name(atmel_port->chan_rx)); 1033 1034 spin_lock_init(&atmel_port->lock_rx); 1035 sg_init_table(&atmel_port->sg_rx, 1); 1036 /* UART circular rx buffer is an aligned page. */ 1037 BUG_ON(!PAGE_ALIGNED(ring->buf)); 1038 sg_set_page(&atmel_port->sg_rx, 1039 virt_to_page(ring->buf), 1040 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE, 1041 (int)ring->buf & ~PAGE_MASK); 1042 nent = dma_map_sg(port->dev, 1043 &atmel_port->sg_rx, 1044 1, 1045 DMA_FROM_DEVICE); 1046 1047 if (!nent) { 1048 dev_dbg(port->dev, "need to release resource of dma\n"); 1049 goto chan_err; 1050 } else { 1051 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 1052 sg_dma_len(&atmel_port->sg_rx), 1053 ring->buf, 1054 sg_dma_address(&atmel_port->sg_rx)); 1055 } 1056 1057 /* Configure the slave DMA */ 1058 memset(&config, 0, sizeof(config)); 1059 config.direction = DMA_DEV_TO_MEM; 1060 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1061 config.src_addr = port->mapbase + ATMEL_US_RHR; 1062 config.src_maxburst = 1; 1063 1064 ret = dmaengine_slave_config(atmel_port->chan_rx, 1065 &config); 1066 if (ret) { 1067 dev_err(port->dev, "DMA rx slave configuration failed\n"); 1068 goto chan_err; 1069 } 1070 /* 1071 * Prepare a cyclic dma transfer, assign 2 descriptors, 1072 * each one is half ring buffer size 1073 */ 1074 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, 1075 sg_dma_address(&atmel_port->sg_rx), 1076 sg_dma_len(&atmel_port->sg_rx), 1077 sg_dma_len(&atmel_port->sg_rx)/2, 1078 DMA_DEV_TO_MEM, 1079 DMA_PREP_INTERRUPT); 1080 desc->callback = atmel_complete_rx_dma; 1081 desc->callback_param = port; 1082 atmel_port->desc_rx = desc; 1083 atmel_port->cookie_rx = dmaengine_submit(desc); 1084 1085 return 0; 1086 1087 chan_err: 1088 dev_err(port->dev, "RX channel not available, switch to pio\n"); 1089 atmel_port->use_dma_rx = 0; 1090 if (atmel_port->chan_rx) 1091 atmel_release_rx_dma(port); 1092 return -EINVAL; 1093 } 1094 1095 static void atmel_uart_timer_callback(unsigned long data) 1096 { 1097 struct uart_port *port = (void *)data; 1098 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1099 1100 tasklet_schedule(&atmel_port->tasklet); 1101 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port)); 1102 } 1103 1104 /* 1105 * receive interrupt handler. 1106 */ 1107 static void 1108 atmel_handle_receive(struct uart_port *port, unsigned int pending) 1109 { 1110 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1111 1112 if (atmel_use_pdc_rx(port)) { 1113 /* 1114 * PDC receive. Just schedule the tasklet and let it 1115 * figure out the details. 1116 * 1117 * TODO: We're not handling error flags correctly at 1118 * the moment. 1119 */ 1120 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { 1121 UART_PUT_IDR(port, (ATMEL_US_ENDRX 1122 | ATMEL_US_TIMEOUT)); 1123 tasklet_schedule(&atmel_port->tasklet); 1124 } 1125 1126 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | 1127 ATMEL_US_FRAME | ATMEL_US_PARE)) 1128 atmel_pdc_rxerr(port, pending); 1129 } 1130 1131 if (atmel_use_dma_rx(port)) { 1132 if (pending & ATMEL_US_TIMEOUT) { 1133 UART_PUT_IDR(port, ATMEL_US_TIMEOUT); 1134 tasklet_schedule(&atmel_port->tasklet); 1135 } 1136 } 1137 1138 /* Interrupt receive */ 1139 if (pending & ATMEL_US_RXRDY) 1140 atmel_rx_chars(port); 1141 else if (pending & ATMEL_US_RXBRK) { 1142 /* 1143 * End of break detected. If it came along with a 1144 * character, atmel_rx_chars will handle it. 1145 */ 1146 UART_PUT_CR(port, ATMEL_US_RSTSTA); 1147 UART_PUT_IDR(port, ATMEL_US_RXBRK); 1148 atmel_port->break_active = 0; 1149 } 1150 } 1151 1152 /* 1153 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) 1154 */ 1155 static void 1156 atmel_handle_transmit(struct uart_port *port, unsigned int pending) 1157 { 1158 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1159 1160 if (pending & atmel_port->tx_done_mask) { 1161 /* Either PDC or interrupt transmission */ 1162 UART_PUT_IDR(port, atmel_port->tx_done_mask); 1163 tasklet_schedule(&atmel_port->tasklet); 1164 } 1165 } 1166 1167 /* 1168 * status flags interrupt handler. 1169 */ 1170 static void 1171 atmel_handle_status(struct uart_port *port, unsigned int pending, 1172 unsigned int status) 1173 { 1174 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1175 1176 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC 1177 | ATMEL_US_CTSIC)) { 1178 atmel_port->irq_status = status; 1179 atmel_port->status_change = atmel_port->irq_status ^ 1180 atmel_port->irq_status_prev; 1181 atmel_port->irq_status_prev = status; 1182 tasklet_schedule(&atmel_port->tasklet); 1183 } 1184 } 1185 1186 /* 1187 * Interrupt handler 1188 */ 1189 static irqreturn_t atmel_interrupt(int irq, void *dev_id) 1190 { 1191 struct uart_port *port = dev_id; 1192 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1193 unsigned int status, pending, mask, pass_counter = 0; 1194 bool gpio_handled = false; 1195 1196 spin_lock(&atmel_port->lock_suspended); 1197 1198 do { 1199 status = atmel_get_lines_status(port); 1200 mask = UART_GET_IMR(port); 1201 pending = status & mask; 1202 if (!gpio_handled) { 1203 /* 1204 * Dealing with GPIO interrupt 1205 */ 1206 if (irq == atmel_port->gpio_irq[UART_GPIO_CTS]) 1207 pending |= ATMEL_US_CTSIC; 1208 1209 if (irq == atmel_port->gpio_irq[UART_GPIO_DSR]) 1210 pending |= ATMEL_US_DSRIC; 1211 1212 if (irq == atmel_port->gpio_irq[UART_GPIO_RI]) 1213 pending |= ATMEL_US_RIIC; 1214 1215 if (irq == atmel_port->gpio_irq[UART_GPIO_DCD]) 1216 pending |= ATMEL_US_DCDIC; 1217 1218 gpio_handled = true; 1219 } 1220 if (!pending) 1221 break; 1222 1223 if (atmel_port->suspended) { 1224 atmel_port->pending |= pending; 1225 atmel_port->pending_status = status; 1226 UART_PUT_IDR(port, mask); 1227 pm_system_wakeup(); 1228 break; 1229 } 1230 1231 atmel_handle_receive(port, pending); 1232 atmel_handle_status(port, pending, status); 1233 atmel_handle_transmit(port, pending); 1234 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); 1235 1236 spin_unlock(&atmel_port->lock_suspended); 1237 1238 return pass_counter ? IRQ_HANDLED : IRQ_NONE; 1239 } 1240 1241 static void atmel_release_tx_pdc(struct uart_port *port) 1242 { 1243 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1244 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1245 1246 dma_unmap_single(port->dev, 1247 pdc->dma_addr, 1248 pdc->dma_size, 1249 DMA_TO_DEVICE); 1250 } 1251 1252 /* 1253 * Called from tasklet with ENDTX and TXBUFE interrupts disabled. 1254 */ 1255 static void atmel_tx_pdc(struct uart_port *port) 1256 { 1257 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1258 struct circ_buf *xmit = &port->state->xmit; 1259 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1260 int count; 1261 1262 /* nothing left to transmit? */ 1263 if (UART_GET_TCR(port)) 1264 return; 1265 1266 xmit->tail += pdc->ofs; 1267 xmit->tail &= UART_XMIT_SIZE - 1; 1268 1269 port->icount.tx += pdc->ofs; 1270 pdc->ofs = 0; 1271 1272 /* more to transmit - setup next transfer */ 1273 1274 /* disable PDC transmit */ 1275 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 1276 1277 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 1278 dma_sync_single_for_device(port->dev, 1279 pdc->dma_addr, 1280 pdc->dma_size, 1281 DMA_TO_DEVICE); 1282 1283 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1284 pdc->ofs = count; 1285 1286 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); 1287 UART_PUT_TCR(port, count); 1288 /* re-enable PDC transmit */ 1289 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 1290 /* Enable interrupts */ 1291 UART_PUT_IER(port, atmel_port->tx_done_mask); 1292 } else { 1293 if ((port->rs485.flags & SER_RS485_ENABLED) && 1294 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) { 1295 /* DMA done, stop TX, start RX for RS485 */ 1296 atmel_start_rx(port); 1297 } 1298 } 1299 1300 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1301 uart_write_wakeup(port); 1302 } 1303 1304 static int atmel_prepare_tx_pdc(struct uart_port *port) 1305 { 1306 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1307 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1308 struct circ_buf *xmit = &port->state->xmit; 1309 1310 pdc->buf = xmit->buf; 1311 pdc->dma_addr = dma_map_single(port->dev, 1312 pdc->buf, 1313 UART_XMIT_SIZE, 1314 DMA_TO_DEVICE); 1315 pdc->dma_size = UART_XMIT_SIZE; 1316 pdc->ofs = 0; 1317 1318 return 0; 1319 } 1320 1321 static void atmel_rx_from_ring(struct uart_port *port) 1322 { 1323 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1324 struct circ_buf *ring = &atmel_port->rx_ring; 1325 unsigned int flg; 1326 unsigned int status; 1327 1328 while (ring->head != ring->tail) { 1329 struct atmel_uart_char c; 1330 1331 /* Make sure c is loaded after head. */ 1332 smp_rmb(); 1333 1334 c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; 1335 1336 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 1337 1338 port->icount.rx++; 1339 status = c.status; 1340 flg = TTY_NORMAL; 1341 1342 /* 1343 * note that the error handling code is 1344 * out of the main execution path 1345 */ 1346 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 1347 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { 1348 if (status & ATMEL_US_RXBRK) { 1349 /* ignore side-effect */ 1350 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 1351 1352 port->icount.brk++; 1353 if (uart_handle_break(port)) 1354 continue; 1355 } 1356 if (status & ATMEL_US_PARE) 1357 port->icount.parity++; 1358 if (status & ATMEL_US_FRAME) 1359 port->icount.frame++; 1360 if (status & ATMEL_US_OVRE) 1361 port->icount.overrun++; 1362 1363 status &= port->read_status_mask; 1364 1365 if (status & ATMEL_US_RXBRK) 1366 flg = TTY_BREAK; 1367 else if (status & ATMEL_US_PARE) 1368 flg = TTY_PARITY; 1369 else if (status & ATMEL_US_FRAME) 1370 flg = TTY_FRAME; 1371 } 1372 1373 1374 if (uart_handle_sysrq_char(port, c.ch)) 1375 continue; 1376 1377 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); 1378 } 1379 1380 /* 1381 * Drop the lock here since it might end up calling 1382 * uart_start(), which takes the lock. 1383 */ 1384 spin_unlock(&port->lock); 1385 tty_flip_buffer_push(&port->state->port); 1386 spin_lock(&port->lock); 1387 } 1388 1389 static void atmel_release_rx_pdc(struct uart_port *port) 1390 { 1391 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1392 int i; 1393 1394 for (i = 0; i < 2; i++) { 1395 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1396 1397 dma_unmap_single(port->dev, 1398 pdc->dma_addr, 1399 pdc->dma_size, 1400 DMA_FROM_DEVICE); 1401 kfree(pdc->buf); 1402 } 1403 } 1404 1405 static void atmel_rx_from_pdc(struct uart_port *port) 1406 { 1407 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1408 struct tty_port *tport = &port->state->port; 1409 struct atmel_dma_buffer *pdc; 1410 int rx_idx = atmel_port->pdc_rx_idx; 1411 unsigned int head; 1412 unsigned int tail; 1413 unsigned int count; 1414 1415 do { 1416 /* Reset the UART timeout early so that we don't miss one */ 1417 UART_PUT_CR(port, ATMEL_US_STTTO); 1418 1419 pdc = &atmel_port->pdc_rx[rx_idx]; 1420 head = UART_GET_RPR(port) - pdc->dma_addr; 1421 tail = pdc->ofs; 1422 1423 /* If the PDC has switched buffers, RPR won't contain 1424 * any address within the current buffer. Since head 1425 * is unsigned, we just need a one-way comparison to 1426 * find out. 1427 * 1428 * In this case, we just need to consume the entire 1429 * buffer and resubmit it for DMA. This will clear the 1430 * ENDRX bit as well, so that we can safely re-enable 1431 * all interrupts below. 1432 */ 1433 head = min(head, pdc->dma_size); 1434 1435 if (likely(head != tail)) { 1436 dma_sync_single_for_cpu(port->dev, pdc->dma_addr, 1437 pdc->dma_size, DMA_FROM_DEVICE); 1438 1439 /* 1440 * head will only wrap around when we recycle 1441 * the DMA buffer, and when that happens, we 1442 * explicitly set tail to 0. So head will 1443 * always be greater than tail. 1444 */ 1445 count = head - tail; 1446 1447 tty_insert_flip_string(tport, pdc->buf + pdc->ofs, 1448 count); 1449 1450 dma_sync_single_for_device(port->dev, pdc->dma_addr, 1451 pdc->dma_size, DMA_FROM_DEVICE); 1452 1453 port->icount.rx += count; 1454 pdc->ofs = head; 1455 } 1456 1457 /* 1458 * If the current buffer is full, we need to check if 1459 * the next one contains any additional data. 1460 */ 1461 if (head >= pdc->dma_size) { 1462 pdc->ofs = 0; 1463 UART_PUT_RNPR(port, pdc->dma_addr); 1464 UART_PUT_RNCR(port, pdc->dma_size); 1465 1466 rx_idx = !rx_idx; 1467 atmel_port->pdc_rx_idx = rx_idx; 1468 } 1469 } while (head >= pdc->dma_size); 1470 1471 /* 1472 * Drop the lock here since it might end up calling 1473 * uart_start(), which takes the lock. 1474 */ 1475 spin_unlock(&port->lock); 1476 tty_flip_buffer_push(tport); 1477 spin_lock(&port->lock); 1478 1479 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1480 } 1481 1482 static int atmel_prepare_rx_pdc(struct uart_port *port) 1483 { 1484 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1485 int i; 1486 1487 for (i = 0; i < 2; i++) { 1488 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1489 1490 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); 1491 if (pdc->buf == NULL) { 1492 if (i != 0) { 1493 dma_unmap_single(port->dev, 1494 atmel_port->pdc_rx[0].dma_addr, 1495 PDC_BUFFER_SIZE, 1496 DMA_FROM_DEVICE); 1497 kfree(atmel_port->pdc_rx[0].buf); 1498 } 1499 atmel_port->use_pdc_rx = 0; 1500 return -ENOMEM; 1501 } 1502 pdc->dma_addr = dma_map_single(port->dev, 1503 pdc->buf, 1504 PDC_BUFFER_SIZE, 1505 DMA_FROM_DEVICE); 1506 pdc->dma_size = PDC_BUFFER_SIZE; 1507 pdc->ofs = 0; 1508 } 1509 1510 atmel_port->pdc_rx_idx = 0; 1511 1512 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); 1513 UART_PUT_RCR(port, PDC_BUFFER_SIZE); 1514 1515 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); 1516 UART_PUT_RNCR(port, PDC_BUFFER_SIZE); 1517 1518 return 0; 1519 } 1520 1521 /* 1522 * tasklet handling tty stuff outside the interrupt handler. 1523 */ 1524 static void atmel_tasklet_func(unsigned long data) 1525 { 1526 struct uart_port *port = (struct uart_port *)data; 1527 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1528 unsigned int status = atmel_port->irq_status; 1529 unsigned int status_change = atmel_port->status_change; 1530 1531 /* The interrupt handler does not take the lock */ 1532 spin_lock(&port->lock); 1533 1534 atmel_port->schedule_tx(port); 1535 1536 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR 1537 | ATMEL_US_DCD | ATMEL_US_CTS)) { 1538 /* TODO: All reads to CSR will clear these interrupts! */ 1539 if (status_change & ATMEL_US_RI) 1540 port->icount.rng++; 1541 if (status_change & ATMEL_US_DSR) 1542 port->icount.dsr++; 1543 if (status_change & ATMEL_US_DCD) 1544 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); 1545 if (status_change & ATMEL_US_CTS) 1546 uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); 1547 1548 wake_up_interruptible(&port->state->port.delta_msr_wait); 1549 1550 atmel_port->status_change = 0; 1551 } 1552 1553 atmel_port->schedule_rx(port); 1554 1555 spin_unlock(&port->lock); 1556 } 1557 1558 static void atmel_init_property(struct atmel_uart_port *atmel_port, 1559 struct platform_device *pdev) 1560 { 1561 struct device_node *np = pdev->dev.of_node; 1562 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1563 1564 if (np) { 1565 /* DMA/PDC usage specification */ 1566 if (of_get_property(np, "atmel,use-dma-rx", NULL)) { 1567 if (of_get_property(np, "dmas", NULL)) { 1568 atmel_port->use_dma_rx = true; 1569 atmel_port->use_pdc_rx = false; 1570 } else { 1571 atmel_port->use_dma_rx = false; 1572 atmel_port->use_pdc_rx = true; 1573 } 1574 } else { 1575 atmel_port->use_dma_rx = false; 1576 atmel_port->use_pdc_rx = false; 1577 } 1578 1579 if (of_get_property(np, "atmel,use-dma-tx", NULL)) { 1580 if (of_get_property(np, "dmas", NULL)) { 1581 atmel_port->use_dma_tx = true; 1582 atmel_port->use_pdc_tx = false; 1583 } else { 1584 atmel_port->use_dma_tx = false; 1585 atmel_port->use_pdc_tx = true; 1586 } 1587 } else { 1588 atmel_port->use_dma_tx = false; 1589 atmel_port->use_pdc_tx = false; 1590 } 1591 1592 } else { 1593 atmel_port->use_pdc_rx = pdata->use_dma_rx; 1594 atmel_port->use_pdc_tx = pdata->use_dma_tx; 1595 atmel_port->use_dma_rx = false; 1596 atmel_port->use_dma_tx = false; 1597 } 1598 1599 } 1600 1601 static void atmel_init_rs485(struct uart_port *port, 1602 struct platform_device *pdev) 1603 { 1604 struct device_node *np = pdev->dev.of_node; 1605 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1606 1607 if (np) { 1608 u32 rs485_delay[2]; 1609 /* rs485 properties */ 1610 if (of_property_read_u32_array(np, "rs485-rts-delay", 1611 rs485_delay, 2) == 0) { 1612 struct serial_rs485 *rs485conf = &port->rs485; 1613 1614 rs485conf->delay_rts_before_send = rs485_delay[0]; 1615 rs485conf->delay_rts_after_send = rs485_delay[1]; 1616 rs485conf->flags = 0; 1617 1618 if (of_get_property(np, "rs485-rx-during-tx", NULL)) 1619 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1620 1621 if (of_get_property(np, "linux,rs485-enabled-at-boot-time", 1622 NULL)) 1623 rs485conf->flags |= SER_RS485_ENABLED; 1624 } 1625 } else { 1626 port->rs485 = pdata->rs485; 1627 } 1628 1629 } 1630 1631 static void atmel_set_ops(struct uart_port *port) 1632 { 1633 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1634 1635 if (atmel_use_dma_rx(port)) { 1636 atmel_port->prepare_rx = &atmel_prepare_rx_dma; 1637 atmel_port->schedule_rx = &atmel_rx_from_dma; 1638 atmel_port->release_rx = &atmel_release_rx_dma; 1639 } else if (atmel_use_pdc_rx(port)) { 1640 atmel_port->prepare_rx = &atmel_prepare_rx_pdc; 1641 atmel_port->schedule_rx = &atmel_rx_from_pdc; 1642 atmel_port->release_rx = &atmel_release_rx_pdc; 1643 } else { 1644 atmel_port->prepare_rx = NULL; 1645 atmel_port->schedule_rx = &atmel_rx_from_ring; 1646 atmel_port->release_rx = NULL; 1647 } 1648 1649 if (atmel_use_dma_tx(port)) { 1650 atmel_port->prepare_tx = &atmel_prepare_tx_dma; 1651 atmel_port->schedule_tx = &atmel_tx_dma; 1652 atmel_port->release_tx = &atmel_release_tx_dma; 1653 } else if (atmel_use_pdc_tx(port)) { 1654 atmel_port->prepare_tx = &atmel_prepare_tx_pdc; 1655 atmel_port->schedule_tx = &atmel_tx_pdc; 1656 atmel_port->release_tx = &atmel_release_tx_pdc; 1657 } else { 1658 atmel_port->prepare_tx = NULL; 1659 atmel_port->schedule_tx = &atmel_tx_chars; 1660 atmel_port->release_tx = NULL; 1661 } 1662 } 1663 1664 /* 1665 * Get ip name usart or uart 1666 */ 1667 static void atmel_get_ip_name(struct uart_port *port) 1668 { 1669 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1670 int name = UART_GET_IP_NAME(port); 1671 u32 version; 1672 int usart, uart; 1673 /* usart and uart ascii */ 1674 usart = 0x55534152; 1675 uart = 0x44424755; 1676 1677 atmel_port->is_usart = false; 1678 1679 if (name == usart) { 1680 dev_dbg(port->dev, "This is usart\n"); 1681 atmel_port->is_usart = true; 1682 } else if (name == uart) { 1683 dev_dbg(port->dev, "This is uart\n"); 1684 atmel_port->is_usart = false; 1685 } else { 1686 /* fallback for older SoCs: use version field */ 1687 version = UART_GET_IP_VERSION(port); 1688 switch (version) { 1689 case 0x302: 1690 case 0x10213: 1691 dev_dbg(port->dev, "This version is usart\n"); 1692 atmel_port->is_usart = true; 1693 break; 1694 case 0x203: 1695 case 0x10202: 1696 dev_dbg(port->dev, "This version is uart\n"); 1697 atmel_port->is_usart = false; 1698 break; 1699 default: 1700 dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); 1701 } 1702 } 1703 } 1704 1705 static void atmel_free_gpio_irq(struct uart_port *port) 1706 { 1707 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1708 enum mctrl_gpio_idx i; 1709 1710 for (i = 0; i < UART_GPIO_MAX; i++) 1711 if (atmel_port->gpio_irq[i] >= 0) 1712 free_irq(atmel_port->gpio_irq[i], port); 1713 } 1714 1715 static int atmel_request_gpio_irq(struct uart_port *port) 1716 { 1717 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1718 int *irq = atmel_port->gpio_irq; 1719 enum mctrl_gpio_idx i; 1720 int err = 0; 1721 1722 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) { 1723 if (irq[i] < 0) 1724 continue; 1725 1726 irq_set_status_flags(irq[i], IRQ_NOAUTOEN); 1727 err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH, 1728 "atmel_serial", port); 1729 if (err) 1730 dev_err(port->dev, "atmel_startup - Can't get %d irq\n", 1731 irq[i]); 1732 } 1733 1734 /* 1735 * If something went wrong, rollback. 1736 */ 1737 while (err && (--i >= 0)) 1738 if (irq[i] >= 0) 1739 free_irq(irq[i], port); 1740 1741 return err; 1742 } 1743 1744 /* 1745 * Perform initialization and enable port for reception 1746 */ 1747 static int atmel_startup(struct uart_port *port) 1748 { 1749 struct platform_device *pdev = to_platform_device(port->dev); 1750 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1751 struct tty_struct *tty = port->state->port.tty; 1752 int retval; 1753 1754 /* 1755 * Ensure that no interrupts are enabled otherwise when 1756 * request_irq() is called we could get stuck trying to 1757 * handle an unexpected interrupt 1758 */ 1759 UART_PUT_IDR(port, -1); 1760 atmel_port->ms_irq_enabled = false; 1761 1762 /* 1763 * Allocate the IRQ 1764 */ 1765 retval = request_irq(port->irq, atmel_interrupt, 1766 IRQF_SHARED | IRQF_COND_SUSPEND, 1767 tty ? tty->name : "atmel_serial", port); 1768 if (retval) { 1769 dev_err(port->dev, "atmel_startup - Can't get irq\n"); 1770 return retval; 1771 } 1772 1773 /* 1774 * Get the GPIO lines IRQ 1775 */ 1776 retval = atmel_request_gpio_irq(port); 1777 if (retval) 1778 goto free_irq; 1779 1780 tasklet_enable(&atmel_port->tasklet); 1781 1782 /* 1783 * Initialize DMA (if necessary) 1784 */ 1785 atmel_init_property(atmel_port, pdev); 1786 atmel_set_ops(port); 1787 1788 if (atmel_port->prepare_rx) { 1789 retval = atmel_port->prepare_rx(port); 1790 if (retval < 0) 1791 atmel_set_ops(port); 1792 } 1793 1794 if (atmel_port->prepare_tx) { 1795 retval = atmel_port->prepare_tx(port); 1796 if (retval < 0) 1797 atmel_set_ops(port); 1798 } 1799 1800 /* Save current CSR for comparison in atmel_tasklet_func() */ 1801 atmel_port->irq_status_prev = atmel_get_lines_status(port); 1802 atmel_port->irq_status = atmel_port->irq_status_prev; 1803 1804 /* 1805 * Finally, enable the serial port 1806 */ 1807 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1808 /* enable xmit & rcvr */ 1809 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 1810 1811 setup_timer(&atmel_port->uart_timer, 1812 atmel_uart_timer_callback, 1813 (unsigned long)port); 1814 1815 if (atmel_use_pdc_rx(port)) { 1816 /* set UART timeout */ 1817 if (!atmel_port->is_usart) { 1818 mod_timer(&atmel_port->uart_timer, 1819 jiffies + uart_poll_timeout(port)); 1820 /* set USART timeout */ 1821 } else { 1822 UART_PUT_RTOR(port, PDC_RX_TIMEOUT); 1823 UART_PUT_CR(port, ATMEL_US_STTTO); 1824 1825 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1826 } 1827 /* enable PDC controller */ 1828 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); 1829 } else if (atmel_use_dma_rx(port)) { 1830 /* set UART timeout */ 1831 if (!atmel_port->is_usart) { 1832 mod_timer(&atmel_port->uart_timer, 1833 jiffies + uart_poll_timeout(port)); 1834 /* set USART timeout */ 1835 } else { 1836 UART_PUT_RTOR(port, PDC_RX_TIMEOUT); 1837 UART_PUT_CR(port, ATMEL_US_STTTO); 1838 1839 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 1840 } 1841 } else { 1842 /* enable receive only */ 1843 UART_PUT_IER(port, ATMEL_US_RXRDY); 1844 } 1845 1846 return 0; 1847 1848 free_irq: 1849 free_irq(port->irq, port); 1850 1851 return retval; 1852 } 1853 1854 /* 1855 * Flush any TX data submitted for DMA. Called when the TX circular 1856 * buffer is reset. 1857 */ 1858 static void atmel_flush_buffer(struct uart_port *port) 1859 { 1860 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1861 1862 if (atmel_use_pdc_tx(port)) { 1863 UART_PUT_TCR(port, 0); 1864 atmel_port->pdc_tx.ofs = 0; 1865 } 1866 } 1867 1868 /* 1869 * Disable the port 1870 */ 1871 static void atmel_shutdown(struct uart_port *port) 1872 { 1873 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1874 1875 /* 1876 * Prevent any tasklets being scheduled during 1877 * cleanup 1878 */ 1879 del_timer_sync(&atmel_port->uart_timer); 1880 1881 /* 1882 * Clear out any scheduled tasklets before 1883 * we destroy the buffers 1884 */ 1885 tasklet_disable(&atmel_port->tasklet); 1886 tasklet_kill(&atmel_port->tasklet); 1887 1888 /* 1889 * Ensure everything is stopped and 1890 * disable all interrupts, port and break condition. 1891 */ 1892 atmel_stop_rx(port); 1893 atmel_stop_tx(port); 1894 1895 UART_PUT_CR(port, ATMEL_US_RSTSTA); 1896 UART_PUT_IDR(port, -1); 1897 1898 1899 /* 1900 * Shut-down the DMA. 1901 */ 1902 if (atmel_port->release_rx) 1903 atmel_port->release_rx(port); 1904 if (atmel_port->release_tx) 1905 atmel_port->release_tx(port); 1906 1907 /* 1908 * Reset ring buffer pointers 1909 */ 1910 atmel_port->rx_ring.head = 0; 1911 atmel_port->rx_ring.tail = 0; 1912 1913 /* 1914 * Free the interrupts 1915 */ 1916 free_irq(port->irq, port); 1917 atmel_free_gpio_irq(port); 1918 1919 atmel_port->ms_irq_enabled = false; 1920 1921 atmel_flush_buffer(port); 1922 } 1923 1924 /* 1925 * Power / Clock management. 1926 */ 1927 static void atmel_serial_pm(struct uart_port *port, unsigned int state, 1928 unsigned int oldstate) 1929 { 1930 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1931 1932 switch (state) { 1933 case 0: 1934 /* 1935 * Enable the peripheral clock for this serial port. 1936 * This is called on uart_open() or a resume event. 1937 */ 1938 clk_prepare_enable(atmel_port->clk); 1939 1940 /* re-enable interrupts if we disabled some on suspend */ 1941 UART_PUT_IER(port, atmel_port->backup_imr); 1942 break; 1943 case 3: 1944 /* Back up the interrupt mask and disable all interrupts */ 1945 atmel_port->backup_imr = UART_GET_IMR(port); 1946 UART_PUT_IDR(port, -1); 1947 1948 /* 1949 * Disable the peripheral clock for this serial port. 1950 * This is called on uart_close() or a suspend event. 1951 */ 1952 clk_disable_unprepare(atmel_port->clk); 1953 break; 1954 default: 1955 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); 1956 } 1957 } 1958 1959 /* 1960 * Change the port parameters 1961 */ 1962 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, 1963 struct ktermios *old) 1964 { 1965 unsigned long flags; 1966 unsigned int old_mode, mode, imr, quot, baud; 1967 1968 /* save the current mode register */ 1969 mode = old_mode = UART_GET_MR(port); 1970 1971 /* reset the mode, clock divisor, parity, stop bits and data size */ 1972 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | 1973 ATMEL_US_PAR | ATMEL_US_USMODE); 1974 1975 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1976 quot = uart_get_divisor(port, baud); 1977 1978 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ 1979 quot /= 8; 1980 mode |= ATMEL_US_USCLKS_MCK_DIV8; 1981 } 1982 1983 /* byte size */ 1984 switch (termios->c_cflag & CSIZE) { 1985 case CS5: 1986 mode |= ATMEL_US_CHRL_5; 1987 break; 1988 case CS6: 1989 mode |= ATMEL_US_CHRL_6; 1990 break; 1991 case CS7: 1992 mode |= ATMEL_US_CHRL_7; 1993 break; 1994 default: 1995 mode |= ATMEL_US_CHRL_8; 1996 break; 1997 } 1998 1999 /* stop bits */ 2000 if (termios->c_cflag & CSTOPB) 2001 mode |= ATMEL_US_NBSTOP_2; 2002 2003 /* parity */ 2004 if (termios->c_cflag & PARENB) { 2005 /* Mark or Space parity */ 2006 if (termios->c_cflag & CMSPAR) { 2007 if (termios->c_cflag & PARODD) 2008 mode |= ATMEL_US_PAR_MARK; 2009 else 2010 mode |= ATMEL_US_PAR_SPACE; 2011 } else if (termios->c_cflag & PARODD) 2012 mode |= ATMEL_US_PAR_ODD; 2013 else 2014 mode |= ATMEL_US_PAR_EVEN; 2015 } else 2016 mode |= ATMEL_US_PAR_NONE; 2017 2018 spin_lock_irqsave(&port->lock, flags); 2019 2020 port->read_status_mask = ATMEL_US_OVRE; 2021 if (termios->c_iflag & INPCK) 2022 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2023 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2024 port->read_status_mask |= ATMEL_US_RXBRK; 2025 2026 if (atmel_use_pdc_rx(port)) 2027 /* need to enable error interrupts */ 2028 UART_PUT_IER(port, port->read_status_mask); 2029 2030 /* 2031 * Characters to ignore 2032 */ 2033 port->ignore_status_mask = 0; 2034 if (termios->c_iflag & IGNPAR) 2035 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2036 if (termios->c_iflag & IGNBRK) { 2037 port->ignore_status_mask |= ATMEL_US_RXBRK; 2038 /* 2039 * If we're ignoring parity and break indicators, 2040 * ignore overruns too (for real raw support). 2041 */ 2042 if (termios->c_iflag & IGNPAR) 2043 port->ignore_status_mask |= ATMEL_US_OVRE; 2044 } 2045 /* TODO: Ignore all characters if CREAD is set.*/ 2046 2047 /* update the per-port timeout */ 2048 uart_update_timeout(port, termios->c_cflag, baud); 2049 2050 /* 2051 * save/disable interrupts. The tty layer will ensure that the 2052 * transmitter is empty if requested by the caller, so there's 2053 * no need to wait for it here. 2054 */ 2055 imr = UART_GET_IMR(port); 2056 UART_PUT_IDR(port, -1); 2057 2058 /* disable receiver and transmitter */ 2059 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); 2060 2061 /* mode */ 2062 if (port->rs485.flags & SER_RS485_ENABLED) { 2063 UART_PUT_TTGR(port, port->rs485.delay_rts_after_send); 2064 mode |= ATMEL_US_USMODE_RS485; 2065 } else if (termios->c_cflag & CRTSCTS) { 2066 /* RS232 with hardware handshake (RTS/CTS) */ 2067 mode |= ATMEL_US_USMODE_HWHS; 2068 } else { 2069 /* RS232 without hadware handshake */ 2070 mode |= ATMEL_US_USMODE_NORMAL; 2071 } 2072 2073 /* set the mode, clock divisor, parity, stop bits and data size */ 2074 UART_PUT_MR(port, mode); 2075 2076 /* 2077 * when switching the mode, set the RTS line state according to the 2078 * new mode, otherwise keep the former state 2079 */ 2080 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) { 2081 unsigned int rts_state; 2082 2083 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 2084 /* let the hardware control the RTS line */ 2085 rts_state = ATMEL_US_RTSDIS; 2086 } else { 2087 /* force RTS line to low level */ 2088 rts_state = ATMEL_US_RTSEN; 2089 } 2090 2091 UART_PUT_CR(port, rts_state); 2092 } 2093 2094 /* set the baud rate */ 2095 UART_PUT_BRGR(port, quot); 2096 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2097 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 2098 2099 /* restore interrupts */ 2100 UART_PUT_IER(port, imr); 2101 2102 /* CTS flow-control and modem-status interrupts */ 2103 if (UART_ENABLE_MS(port, termios->c_cflag)) 2104 atmel_enable_ms(port); 2105 else 2106 atmel_disable_ms(port); 2107 2108 spin_unlock_irqrestore(&port->lock, flags); 2109 } 2110 2111 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios) 2112 { 2113 if (termios->c_line == N_PPS) { 2114 port->flags |= UPF_HARDPPS_CD; 2115 spin_lock_irq(&port->lock); 2116 atmel_enable_ms(port); 2117 spin_unlock_irq(&port->lock); 2118 } else { 2119 port->flags &= ~UPF_HARDPPS_CD; 2120 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 2121 spin_lock_irq(&port->lock); 2122 atmel_disable_ms(port); 2123 spin_unlock_irq(&port->lock); 2124 } 2125 } 2126 } 2127 2128 /* 2129 * Return string describing the specified port 2130 */ 2131 static const char *atmel_type(struct uart_port *port) 2132 { 2133 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; 2134 } 2135 2136 /* 2137 * Release the memory region(s) being used by 'port'. 2138 */ 2139 static void atmel_release_port(struct uart_port *port) 2140 { 2141 struct platform_device *pdev = to_platform_device(port->dev); 2142 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 2143 2144 release_mem_region(port->mapbase, size); 2145 2146 if (port->flags & UPF_IOREMAP) { 2147 iounmap(port->membase); 2148 port->membase = NULL; 2149 } 2150 } 2151 2152 /* 2153 * Request the memory region(s) being used by 'port'. 2154 */ 2155 static int atmel_request_port(struct uart_port *port) 2156 { 2157 struct platform_device *pdev = to_platform_device(port->dev); 2158 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 2159 2160 if (!request_mem_region(port->mapbase, size, "atmel_serial")) 2161 return -EBUSY; 2162 2163 if (port->flags & UPF_IOREMAP) { 2164 port->membase = ioremap(port->mapbase, size); 2165 if (port->membase == NULL) { 2166 release_mem_region(port->mapbase, size); 2167 return -ENOMEM; 2168 } 2169 } 2170 2171 return 0; 2172 } 2173 2174 /* 2175 * Configure/autoconfigure the port. 2176 */ 2177 static void atmel_config_port(struct uart_port *port, int flags) 2178 { 2179 if (flags & UART_CONFIG_TYPE) { 2180 port->type = PORT_ATMEL; 2181 atmel_request_port(port); 2182 } 2183 } 2184 2185 /* 2186 * Verify the new serial_struct (for TIOCSSERIAL). 2187 */ 2188 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) 2189 { 2190 int ret = 0; 2191 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) 2192 ret = -EINVAL; 2193 if (port->irq != ser->irq) 2194 ret = -EINVAL; 2195 if (ser->io_type != SERIAL_IO_MEM) 2196 ret = -EINVAL; 2197 if (port->uartclk / 16 != ser->baud_base) 2198 ret = -EINVAL; 2199 if ((void *)port->mapbase != ser->iomem_base) 2200 ret = -EINVAL; 2201 if (port->iobase != ser->port) 2202 ret = -EINVAL; 2203 if (ser->hub6 != 0) 2204 ret = -EINVAL; 2205 return ret; 2206 } 2207 2208 #ifdef CONFIG_CONSOLE_POLL 2209 static int atmel_poll_get_char(struct uart_port *port) 2210 { 2211 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY)) 2212 cpu_relax(); 2213 2214 return UART_GET_CHAR(port); 2215 } 2216 2217 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) 2218 { 2219 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) 2220 cpu_relax(); 2221 2222 UART_PUT_CHAR(port, ch); 2223 } 2224 #endif 2225 2226 static struct uart_ops atmel_pops = { 2227 .tx_empty = atmel_tx_empty, 2228 .set_mctrl = atmel_set_mctrl, 2229 .get_mctrl = atmel_get_mctrl, 2230 .stop_tx = atmel_stop_tx, 2231 .start_tx = atmel_start_tx, 2232 .stop_rx = atmel_stop_rx, 2233 .enable_ms = atmel_enable_ms, 2234 .break_ctl = atmel_break_ctl, 2235 .startup = atmel_startup, 2236 .shutdown = atmel_shutdown, 2237 .flush_buffer = atmel_flush_buffer, 2238 .set_termios = atmel_set_termios, 2239 .set_ldisc = atmel_set_ldisc, 2240 .type = atmel_type, 2241 .release_port = atmel_release_port, 2242 .request_port = atmel_request_port, 2243 .config_port = atmel_config_port, 2244 .verify_port = atmel_verify_port, 2245 .pm = atmel_serial_pm, 2246 #ifdef CONFIG_CONSOLE_POLL 2247 .poll_get_char = atmel_poll_get_char, 2248 .poll_put_char = atmel_poll_put_char, 2249 #endif 2250 }; 2251 2252 /* 2253 * Configure the port from the platform device resource info. 2254 */ 2255 static int atmel_init_port(struct atmel_uart_port *atmel_port, 2256 struct platform_device *pdev) 2257 { 2258 int ret; 2259 struct uart_port *port = &atmel_port->uart; 2260 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2261 2262 atmel_init_property(atmel_port, pdev); 2263 atmel_set_ops(port); 2264 2265 atmel_init_rs485(port, pdev); 2266 2267 port->iotype = UPIO_MEM; 2268 port->flags = UPF_BOOT_AUTOCONF; 2269 port->ops = &atmel_pops; 2270 port->fifosize = 1; 2271 port->dev = &pdev->dev; 2272 port->mapbase = pdev->resource[0].start; 2273 port->irq = pdev->resource[1].start; 2274 port->rs485_config = atmel_config_rs485; 2275 2276 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, 2277 (unsigned long)port); 2278 tasklet_disable(&atmel_port->tasklet); 2279 2280 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); 2281 2282 if (pdata && pdata->regs) { 2283 /* Already mapped by setup code */ 2284 port->membase = pdata->regs; 2285 } else { 2286 port->flags |= UPF_IOREMAP; 2287 port->membase = NULL; 2288 } 2289 2290 /* for console, the clock could already be configured */ 2291 if (!atmel_port->clk) { 2292 atmel_port->clk = clk_get(&pdev->dev, "usart"); 2293 if (IS_ERR(atmel_port->clk)) { 2294 ret = PTR_ERR(atmel_port->clk); 2295 atmel_port->clk = NULL; 2296 return ret; 2297 } 2298 ret = clk_prepare_enable(atmel_port->clk); 2299 if (ret) { 2300 clk_put(atmel_port->clk); 2301 atmel_port->clk = NULL; 2302 return ret; 2303 } 2304 port->uartclk = clk_get_rate(atmel_port->clk); 2305 clk_disable_unprepare(atmel_port->clk); 2306 /* only enable clock when USART is in use */ 2307 } 2308 2309 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ 2310 if (port->rs485.flags & SER_RS485_ENABLED) 2311 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 2312 else if (atmel_use_pdc_tx(port)) { 2313 port->fifosize = PDC_BUFFER_SIZE; 2314 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; 2315 } else { 2316 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 2317 } 2318 2319 return 0; 2320 } 2321 2322 struct platform_device *atmel_default_console_device; /* the serial console device */ 2323 2324 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2325 static void atmel_console_putchar(struct uart_port *port, int ch) 2326 { 2327 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) 2328 cpu_relax(); 2329 UART_PUT_CHAR(port, ch); 2330 } 2331 2332 /* 2333 * Interrupts are disabled on entering 2334 */ 2335 static void atmel_console_write(struct console *co, const char *s, u_int count) 2336 { 2337 struct uart_port *port = &atmel_ports[co->index].uart; 2338 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2339 unsigned int status, imr; 2340 unsigned int pdc_tx; 2341 2342 /* 2343 * First, save IMR and then disable interrupts 2344 */ 2345 imr = UART_GET_IMR(port); 2346 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask); 2347 2348 /* Store PDC transmit status and disable it */ 2349 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN; 2350 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 2351 2352 uart_console_write(port, s, count, atmel_console_putchar); 2353 2354 /* 2355 * Finally, wait for transmitter to become empty 2356 * and restore IMR 2357 */ 2358 do { 2359 status = UART_GET_CSR(port); 2360 } while (!(status & ATMEL_US_TXRDY)); 2361 2362 /* Restore PDC transmit status */ 2363 if (pdc_tx) 2364 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 2365 2366 /* set interrupts back the way they were */ 2367 UART_PUT_IER(port, imr); 2368 } 2369 2370 /* 2371 * If the port was already initialised (eg, by a boot loader), 2372 * try to determine the current setup. 2373 */ 2374 static void __init atmel_console_get_options(struct uart_port *port, int *baud, 2375 int *parity, int *bits) 2376 { 2377 unsigned int mr, quot; 2378 2379 /* 2380 * If the baud rate generator isn't running, the port wasn't 2381 * initialized by the boot loader. 2382 */ 2383 quot = UART_GET_BRGR(port) & ATMEL_US_CD; 2384 if (!quot) 2385 return; 2386 2387 mr = UART_GET_MR(port) & ATMEL_US_CHRL; 2388 if (mr == ATMEL_US_CHRL_8) 2389 *bits = 8; 2390 else 2391 *bits = 7; 2392 2393 mr = UART_GET_MR(port) & ATMEL_US_PAR; 2394 if (mr == ATMEL_US_PAR_EVEN) 2395 *parity = 'e'; 2396 else if (mr == ATMEL_US_PAR_ODD) 2397 *parity = 'o'; 2398 2399 /* 2400 * The serial core only rounds down when matching this to a 2401 * supported baud rate. Make sure we don't end up slightly 2402 * lower than one of those, as it would make us fall through 2403 * to a much lower baud rate than we really want. 2404 */ 2405 *baud = port->uartclk / (16 * (quot - 1)); 2406 } 2407 2408 static int __init atmel_console_setup(struct console *co, char *options) 2409 { 2410 int ret; 2411 struct uart_port *port = &atmel_ports[co->index].uart; 2412 int baud = 115200; 2413 int bits = 8; 2414 int parity = 'n'; 2415 int flow = 'n'; 2416 2417 if (port->membase == NULL) { 2418 /* Port not initialized yet - delay setup */ 2419 return -ENODEV; 2420 } 2421 2422 ret = clk_prepare_enable(atmel_ports[co->index].clk); 2423 if (ret) 2424 return ret; 2425 2426 UART_PUT_IDR(port, -1); 2427 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2428 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 2429 2430 if (options) 2431 uart_parse_options(options, &baud, &parity, &bits, &flow); 2432 else 2433 atmel_console_get_options(port, &baud, &parity, &bits); 2434 2435 return uart_set_options(port, co, baud, parity, bits, flow); 2436 } 2437 2438 static struct uart_driver atmel_uart; 2439 2440 static struct console atmel_console = { 2441 .name = ATMEL_DEVICENAME, 2442 .write = atmel_console_write, 2443 .device = uart_console_device, 2444 .setup = atmel_console_setup, 2445 .flags = CON_PRINTBUFFER, 2446 .index = -1, 2447 .data = &atmel_uart, 2448 }; 2449 2450 #define ATMEL_CONSOLE_DEVICE (&atmel_console) 2451 2452 /* 2453 * Early console initialization (before VM subsystem initialized). 2454 */ 2455 static int __init atmel_console_init(void) 2456 { 2457 int ret; 2458 if (atmel_default_console_device) { 2459 struct atmel_uart_data *pdata = 2460 dev_get_platdata(&atmel_default_console_device->dev); 2461 int id = pdata->num; 2462 struct atmel_uart_port *port = &atmel_ports[id]; 2463 2464 port->backup_imr = 0; 2465 port->uart.line = id; 2466 2467 add_preferred_console(ATMEL_DEVICENAME, id, NULL); 2468 ret = atmel_init_port(port, atmel_default_console_device); 2469 if (ret) 2470 return ret; 2471 register_console(&atmel_console); 2472 } 2473 2474 return 0; 2475 } 2476 2477 console_initcall(atmel_console_init); 2478 2479 /* 2480 * Late console initialization. 2481 */ 2482 static int __init atmel_late_console_init(void) 2483 { 2484 if (atmel_default_console_device 2485 && !(atmel_console.flags & CON_ENABLED)) 2486 register_console(&atmel_console); 2487 2488 return 0; 2489 } 2490 2491 core_initcall(atmel_late_console_init); 2492 2493 static inline bool atmel_is_console_port(struct uart_port *port) 2494 { 2495 return port->cons && port->cons->index == port->line; 2496 } 2497 2498 #else 2499 #define ATMEL_CONSOLE_DEVICE NULL 2500 2501 static inline bool atmel_is_console_port(struct uart_port *port) 2502 { 2503 return false; 2504 } 2505 #endif 2506 2507 static struct uart_driver atmel_uart = { 2508 .owner = THIS_MODULE, 2509 .driver_name = "atmel_serial", 2510 .dev_name = ATMEL_DEVICENAME, 2511 .major = SERIAL_ATMEL_MAJOR, 2512 .minor = MINOR_START, 2513 .nr = ATMEL_MAX_UART, 2514 .cons = ATMEL_CONSOLE_DEVICE, 2515 }; 2516 2517 #ifdef CONFIG_PM 2518 static bool atmel_serial_clk_will_stop(void) 2519 { 2520 #ifdef CONFIG_ARCH_AT91 2521 return at91_suspend_entering_slow_clock(); 2522 #else 2523 return false; 2524 #endif 2525 } 2526 2527 static int atmel_serial_suspend(struct platform_device *pdev, 2528 pm_message_t state) 2529 { 2530 struct uart_port *port = platform_get_drvdata(pdev); 2531 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2532 2533 if (atmel_is_console_port(port) && console_suspend_enabled) { 2534 /* Drain the TX shifter */ 2535 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) 2536 cpu_relax(); 2537 } 2538 2539 /* we can not wake up if we're running on slow clock */ 2540 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); 2541 if (atmel_serial_clk_will_stop()) { 2542 unsigned long flags; 2543 2544 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2545 atmel_port->suspended = true; 2546 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2547 device_set_wakeup_enable(&pdev->dev, 0); 2548 } 2549 2550 uart_suspend_port(&atmel_uart, port); 2551 2552 return 0; 2553 } 2554 2555 static int atmel_serial_resume(struct platform_device *pdev) 2556 { 2557 struct uart_port *port = platform_get_drvdata(pdev); 2558 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2559 unsigned long flags; 2560 2561 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2562 if (atmel_port->pending) { 2563 atmel_handle_receive(port, atmel_port->pending); 2564 atmel_handle_status(port, atmel_port->pending, 2565 atmel_port->pending_status); 2566 atmel_handle_transmit(port, atmel_port->pending); 2567 atmel_port->pending = 0; 2568 } 2569 atmel_port->suspended = false; 2570 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2571 2572 uart_resume_port(&atmel_uart, port); 2573 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); 2574 2575 return 0; 2576 } 2577 #else 2578 #define atmel_serial_suspend NULL 2579 #define atmel_serial_resume NULL 2580 #endif 2581 2582 static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev) 2583 { 2584 enum mctrl_gpio_idx i; 2585 struct gpio_desc *gpiod; 2586 2587 p->gpios = mctrl_gpio_init(dev, 0); 2588 if (IS_ERR(p->gpios)) 2589 return PTR_ERR(p->gpios); 2590 2591 for (i = 0; i < UART_GPIO_MAX; i++) { 2592 gpiod = mctrl_gpio_to_gpiod(p->gpios, i); 2593 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN)) 2594 p->gpio_irq[i] = gpiod_to_irq(gpiod); 2595 else 2596 p->gpio_irq[i] = -EINVAL; 2597 } 2598 2599 return 0; 2600 } 2601 2602 static int atmel_serial_probe(struct platform_device *pdev) 2603 { 2604 struct atmel_uart_port *port; 2605 struct device_node *np = pdev->dev.of_node; 2606 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2607 void *data; 2608 int ret = -ENODEV; 2609 bool rs485_enabled; 2610 2611 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); 2612 2613 if (np) 2614 ret = of_alias_get_id(np, "serial"); 2615 else 2616 if (pdata) 2617 ret = pdata->num; 2618 2619 if (ret < 0) 2620 /* port id not found in platform data nor device-tree aliases: 2621 * auto-enumerate it */ 2622 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); 2623 2624 if (ret >= ATMEL_MAX_UART) { 2625 ret = -ENODEV; 2626 goto err; 2627 } 2628 2629 if (test_and_set_bit(ret, atmel_ports_in_use)) { 2630 /* port already in use */ 2631 ret = -EBUSY; 2632 goto err; 2633 } 2634 2635 port = &atmel_ports[ret]; 2636 port->backup_imr = 0; 2637 port->uart.line = ret; 2638 2639 spin_lock_init(&port->lock_suspended); 2640 2641 ret = atmel_init_gpios(port, &pdev->dev); 2642 if (ret < 0) { 2643 dev_err(&pdev->dev, "Failed to initialize GPIOs."); 2644 goto err; 2645 } 2646 2647 ret = atmel_init_port(port, pdev); 2648 if (ret) 2649 goto err_clear_bit; 2650 2651 if (!atmel_use_pdc_rx(&port->uart)) { 2652 ret = -ENOMEM; 2653 data = kmalloc(sizeof(struct atmel_uart_char) 2654 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); 2655 if (!data) 2656 goto err_alloc_ring; 2657 port->rx_ring.buf = data; 2658 } 2659 2660 rs485_enabled = port->uart.rs485.flags & SER_RS485_ENABLED; 2661 2662 ret = uart_add_one_port(&atmel_uart, &port->uart); 2663 if (ret) 2664 goto err_add_port; 2665 2666 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2667 if (atmel_is_console_port(&port->uart) 2668 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { 2669 /* 2670 * The serial core enabled the clock for us, so undo 2671 * the clk_prepare_enable() in atmel_console_setup() 2672 */ 2673 clk_disable_unprepare(port->clk); 2674 } 2675 #endif 2676 2677 device_init_wakeup(&pdev->dev, 1); 2678 platform_set_drvdata(pdev, port); 2679 2680 /* 2681 * The peripheral clock has been disabled by atmel_init_port(): 2682 * enable it before accessing I/O registers 2683 */ 2684 clk_prepare_enable(port->clk); 2685 2686 if (rs485_enabled) { 2687 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL); 2688 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN); 2689 } 2690 2691 /* 2692 * Get port name of usart or uart 2693 */ 2694 atmel_get_ip_name(&port->uart); 2695 2696 /* 2697 * The peripheral clock can now safely be disabled till the port 2698 * is used 2699 */ 2700 clk_disable_unprepare(port->clk); 2701 2702 return 0; 2703 2704 err_add_port: 2705 kfree(port->rx_ring.buf); 2706 port->rx_ring.buf = NULL; 2707 err_alloc_ring: 2708 if (!atmel_is_console_port(&port->uart)) { 2709 clk_put(port->clk); 2710 port->clk = NULL; 2711 } 2712 err_clear_bit: 2713 clear_bit(port->uart.line, atmel_ports_in_use); 2714 err: 2715 return ret; 2716 } 2717 2718 static int atmel_serial_remove(struct platform_device *pdev) 2719 { 2720 struct uart_port *port = platform_get_drvdata(pdev); 2721 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2722 int ret = 0; 2723 2724 tasklet_kill(&atmel_port->tasklet); 2725 2726 device_init_wakeup(&pdev->dev, 0); 2727 2728 ret = uart_remove_one_port(&atmel_uart, port); 2729 2730 kfree(atmel_port->rx_ring.buf); 2731 2732 /* "port" is allocated statically, so we shouldn't free it */ 2733 2734 clear_bit(port->line, atmel_ports_in_use); 2735 2736 clk_put(atmel_port->clk); 2737 2738 return ret; 2739 } 2740 2741 static struct platform_driver atmel_serial_driver = { 2742 .probe = atmel_serial_probe, 2743 .remove = atmel_serial_remove, 2744 .suspend = atmel_serial_suspend, 2745 .resume = atmel_serial_resume, 2746 .driver = { 2747 .name = "atmel_usart", 2748 .of_match_table = of_match_ptr(atmel_serial_dt_ids), 2749 }, 2750 }; 2751 2752 static int __init atmel_serial_init(void) 2753 { 2754 int ret; 2755 2756 ret = uart_register_driver(&atmel_uart); 2757 if (ret) 2758 return ret; 2759 2760 ret = platform_driver_register(&atmel_serial_driver); 2761 if (ret) 2762 uart_unregister_driver(&atmel_uart); 2763 2764 return ret; 2765 } 2766 2767 static void __exit atmel_serial_exit(void) 2768 { 2769 platform_driver_unregister(&atmel_serial_driver); 2770 uart_unregister_driver(&atmel_uart); 2771 } 2772 2773 module_init(atmel_serial_init); 2774 module_exit(atmel_serial_exit); 2775 2776 MODULE_AUTHOR("Rick Bronson"); 2777 MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); 2778 MODULE_LICENSE("GPL"); 2779 MODULE_ALIAS("platform:atmel_usart"); 2780