1 /*
2  *  Driver for Atmel AT91 / AT32 Serial ports
3  *  Copyright (C) 2003 Rick Bronson
4  *
5  *  Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7  *
8  *  DMA support added by Chip Coldwell.
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
23  *
24  */
25 #include <linux/tty.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/serial.h>
30 #include <linux/clk.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/tty_flip.h>
34 #include <linux/platform_device.h>
35 #include <linux/of.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmaengine.h>
40 #include <linux/atmel_pdc.h>
41 #include <linux/atmel_serial.h>
42 #include <linux/uaccess.h>
43 #include <linux/platform_data/atmel.h>
44 #include <linux/timer.h>
45 #include <linux/gpio.h>
46 #include <linux/gpio/consumer.h>
47 #include <linux/err.h>
48 #include <linux/irq.h>
49 #include <linux/suspend.h>
50 
51 #include <asm/io.h>
52 #include <asm/ioctls.h>
53 
54 #define PDC_BUFFER_SIZE		512
55 /* Revisit: We should calculate this based on the actual port settings */
56 #define PDC_RX_TIMEOUT		(3 * 10)		/* 3 bytes */
57 
58 /* The minium number of data FIFOs should be able to contain */
59 #define ATMEL_MIN_FIFO_SIZE	8
60 /*
61  * These two offsets are substracted from the RX FIFO size to define the RTS
62  * high and low thresholds
63  */
64 #define ATMEL_RTS_HIGH_OFFSET	16
65 #define ATMEL_RTS_LOW_OFFSET	20
66 
67 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
68 #define SUPPORT_SYSRQ
69 #endif
70 
71 #include <linux/serial_core.h>
72 
73 #include "serial_mctrl_gpio.h"
74 
75 static void atmel_start_rx(struct uart_port *port);
76 static void atmel_stop_rx(struct uart_port *port);
77 
78 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
79 
80 /* Use device name ttyAT, major 204 and minor 154-169.  This is necessary if we
81  * should coexist with the 8250 driver, such as if we have an external 16C550
82  * UART. */
83 #define SERIAL_ATMEL_MAJOR	204
84 #define MINOR_START		154
85 #define ATMEL_DEVICENAME	"ttyAT"
86 
87 #else
88 
89 /* Use device name ttyS, major 4, minor 64-68.  This is the usual serial port
90  * name, but it is legally reserved for the 8250 driver. */
91 #define SERIAL_ATMEL_MAJOR	TTY_MAJOR
92 #define MINOR_START		64
93 #define ATMEL_DEVICENAME	"ttyS"
94 
95 #endif
96 
97 #define ATMEL_ISR_PASS_LIMIT	256
98 
99 struct atmel_dma_buffer {
100 	unsigned char	*buf;
101 	dma_addr_t	dma_addr;
102 	unsigned int	dma_size;
103 	unsigned int	ofs;
104 };
105 
106 struct atmel_uart_char {
107 	u16		status;
108 	u16		ch;
109 };
110 
111 /*
112  * Be careful, the real size of the ring buffer is
113  * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
114  * can contain up to 1024 characters in PIO mode and up to 4096 characters in
115  * DMA mode.
116  */
117 #define ATMEL_SERIAL_RINGSIZE 1024
118 
119 /*
120  * at91: 6 USARTs and one DBGU port (SAM9260)
121  * avr32: 4
122  */
123 #define ATMEL_MAX_UART		7
124 
125 /*
126  * We wrap our port structure around the generic uart_port.
127  */
128 struct atmel_uart_port {
129 	struct uart_port	uart;		/* uart */
130 	struct clk		*clk;		/* uart clock */
131 	int			may_wakeup;	/* cached value of device_may_wakeup for times we need to disable it */
132 	u32			backup_imr;	/* IMR saved during suspend */
133 	int			break_active;	/* break being received */
134 
135 	bool			use_dma_rx;	/* enable DMA receiver */
136 	bool			use_pdc_rx;	/* enable PDC receiver */
137 	short			pdc_rx_idx;	/* current PDC RX buffer */
138 	struct atmel_dma_buffer	pdc_rx[2];	/* PDC receier */
139 
140 	bool			use_dma_tx;     /* enable DMA transmitter */
141 	bool			use_pdc_tx;	/* enable PDC transmitter */
142 	struct atmel_dma_buffer	pdc_tx;		/* PDC transmitter */
143 
144 	spinlock_t			lock_tx;	/* port lock */
145 	spinlock_t			lock_rx;	/* port lock */
146 	struct dma_chan			*chan_tx;
147 	struct dma_chan			*chan_rx;
148 	struct dma_async_tx_descriptor	*desc_tx;
149 	struct dma_async_tx_descriptor	*desc_rx;
150 	dma_cookie_t			cookie_tx;
151 	dma_cookie_t			cookie_rx;
152 	struct scatterlist		sg_tx;
153 	struct scatterlist		sg_rx;
154 	struct tasklet_struct	tasklet_rx;
155 	struct tasklet_struct	tasklet_tx;
156 	atomic_t		tasklet_shutdown;
157 	unsigned int		irq_status_prev;
158 	unsigned int		tx_len;
159 
160 	struct circ_buf		rx_ring;
161 
162 	struct mctrl_gpios	*gpios;
163 	unsigned int		tx_done_mask;
164 	u32			fifo_size;
165 	u32			rts_high;
166 	u32			rts_low;
167 	bool			ms_irq_enabled;
168 	u32			rtor;	/* address of receiver timeout register if it exists */
169 	bool			has_frac_baudrate;
170 	bool			has_hw_timer;
171 	struct timer_list	uart_timer;
172 
173 	bool			suspended;
174 	unsigned int		pending;
175 	unsigned int		pending_status;
176 	spinlock_t		lock_suspended;
177 
178 	int (*prepare_rx)(struct uart_port *port);
179 	int (*prepare_tx)(struct uart_port *port);
180 	void (*schedule_rx)(struct uart_port *port);
181 	void (*schedule_tx)(struct uart_port *port);
182 	void (*release_rx)(struct uart_port *port);
183 	void (*release_tx)(struct uart_port *port);
184 };
185 
186 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
187 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
188 
189 #ifdef SUPPORT_SYSRQ
190 static struct console atmel_console;
191 #endif
192 
193 #if defined(CONFIG_OF)
194 static const struct of_device_id atmel_serial_dt_ids[] = {
195 	{ .compatible = "atmel,at91rm9200-usart" },
196 	{ .compatible = "atmel,at91sam9260-usart" },
197 	{ /* sentinel */ }
198 };
199 #endif
200 
201 static inline struct atmel_uart_port *
202 to_atmel_uart_port(struct uart_port *uart)
203 {
204 	return container_of(uart, struct atmel_uart_port, uart);
205 }
206 
207 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
208 {
209 	return __raw_readl(port->membase + reg);
210 }
211 
212 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
213 {
214 	__raw_writel(value, port->membase + reg);
215 }
216 
217 #ifdef CONFIG_AVR32
218 
219 /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
220 static inline u8 atmel_uart_read_char(struct uart_port *port)
221 {
222 	return __raw_readl(port->membase + ATMEL_US_RHR);
223 }
224 
225 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
226 {
227 	__raw_writel(value, port->membase + ATMEL_US_THR);
228 }
229 
230 #else
231 
232 static inline u8 atmel_uart_read_char(struct uart_port *port)
233 {
234 	return __raw_readb(port->membase + ATMEL_US_RHR);
235 }
236 
237 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
238 {
239 	__raw_writeb(value, port->membase + ATMEL_US_THR);
240 }
241 
242 #endif
243 
244 #ifdef CONFIG_SERIAL_ATMEL_PDC
245 static bool atmel_use_pdc_rx(struct uart_port *port)
246 {
247 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
248 
249 	return atmel_port->use_pdc_rx;
250 }
251 
252 static bool atmel_use_pdc_tx(struct uart_port *port)
253 {
254 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
255 
256 	return atmel_port->use_pdc_tx;
257 }
258 #else
259 static bool atmel_use_pdc_rx(struct uart_port *port)
260 {
261 	return false;
262 }
263 
264 static bool atmel_use_pdc_tx(struct uart_port *port)
265 {
266 	return false;
267 }
268 #endif
269 
270 static bool atmel_use_dma_tx(struct uart_port *port)
271 {
272 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
273 
274 	return atmel_port->use_dma_tx;
275 }
276 
277 static bool atmel_use_dma_rx(struct uart_port *port)
278 {
279 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
280 
281 	return atmel_port->use_dma_rx;
282 }
283 
284 static bool atmel_use_fifo(struct uart_port *port)
285 {
286 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
287 
288 	return atmel_port->fifo_size;
289 }
290 
291 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
292 				   struct tasklet_struct *t)
293 {
294 	if (!atomic_read(&atmel_port->tasklet_shutdown))
295 		tasklet_schedule(t);
296 }
297 
298 static unsigned int atmel_get_lines_status(struct uart_port *port)
299 {
300 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
301 	unsigned int status, ret = 0;
302 
303 	status = atmel_uart_readl(port, ATMEL_US_CSR);
304 
305 	mctrl_gpio_get(atmel_port->gpios, &ret);
306 
307 	if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
308 						UART_GPIO_CTS))) {
309 		if (ret & TIOCM_CTS)
310 			status &= ~ATMEL_US_CTS;
311 		else
312 			status |= ATMEL_US_CTS;
313 	}
314 
315 	if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
316 						UART_GPIO_DSR))) {
317 		if (ret & TIOCM_DSR)
318 			status &= ~ATMEL_US_DSR;
319 		else
320 			status |= ATMEL_US_DSR;
321 	}
322 
323 	if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
324 						UART_GPIO_RI))) {
325 		if (ret & TIOCM_RI)
326 			status &= ~ATMEL_US_RI;
327 		else
328 			status |= ATMEL_US_RI;
329 	}
330 
331 	if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
332 						UART_GPIO_DCD))) {
333 		if (ret & TIOCM_CD)
334 			status &= ~ATMEL_US_DCD;
335 		else
336 			status |= ATMEL_US_DCD;
337 	}
338 
339 	return status;
340 }
341 
342 /* Enable or disable the rs485 support */
343 static int atmel_config_rs485(struct uart_port *port,
344 			      struct serial_rs485 *rs485conf)
345 {
346 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
347 	unsigned int mode;
348 
349 	/* Disable interrupts */
350 	atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
351 
352 	mode = atmel_uart_readl(port, ATMEL_US_MR);
353 
354 	/* Resetting serial mode to RS232 (0x0) */
355 	mode &= ~ATMEL_US_USMODE;
356 
357 	port->rs485 = *rs485conf;
358 
359 	if (rs485conf->flags & SER_RS485_ENABLED) {
360 		dev_dbg(port->dev, "Setting UART to RS485\n");
361 		atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
362 		atmel_uart_writel(port, ATMEL_US_TTGR,
363 				  rs485conf->delay_rts_after_send);
364 		mode |= ATMEL_US_USMODE_RS485;
365 	} else {
366 		dev_dbg(port->dev, "Setting UART to RS232\n");
367 		if (atmel_use_pdc_tx(port))
368 			atmel_port->tx_done_mask = ATMEL_US_ENDTX |
369 				ATMEL_US_TXBUFE;
370 		else
371 			atmel_port->tx_done_mask = ATMEL_US_TXRDY;
372 	}
373 	atmel_uart_writel(port, ATMEL_US_MR, mode);
374 
375 	/* Enable interrupts */
376 	atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
377 
378 	return 0;
379 }
380 
381 /*
382  * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
383  */
384 static u_int atmel_tx_empty(struct uart_port *port)
385 {
386 	return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
387 		TIOCSER_TEMT :
388 		0;
389 }
390 
391 /*
392  * Set state of the modem control output lines
393  */
394 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
395 {
396 	unsigned int control = 0;
397 	unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
398 	unsigned int rts_paused, rts_ready;
399 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
400 
401 	/* override mode to RS485 if needed, otherwise keep the current mode */
402 	if (port->rs485.flags & SER_RS485_ENABLED) {
403 		atmel_uart_writel(port, ATMEL_US_TTGR,
404 				  port->rs485.delay_rts_after_send);
405 		mode &= ~ATMEL_US_USMODE;
406 		mode |= ATMEL_US_USMODE_RS485;
407 	}
408 
409 	/* set the RTS line state according to the mode */
410 	if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
411 		/* force RTS line to high level */
412 		rts_paused = ATMEL_US_RTSEN;
413 
414 		/* give the control of the RTS line back to the hardware */
415 		rts_ready = ATMEL_US_RTSDIS;
416 	} else {
417 		/* force RTS line to high level */
418 		rts_paused = ATMEL_US_RTSDIS;
419 
420 		/* force RTS line to low level */
421 		rts_ready = ATMEL_US_RTSEN;
422 	}
423 
424 	if (mctrl & TIOCM_RTS)
425 		control |= rts_ready;
426 	else
427 		control |= rts_paused;
428 
429 	if (mctrl & TIOCM_DTR)
430 		control |= ATMEL_US_DTREN;
431 	else
432 		control |= ATMEL_US_DTRDIS;
433 
434 	atmel_uart_writel(port, ATMEL_US_CR, control);
435 
436 	mctrl_gpio_set(atmel_port->gpios, mctrl);
437 
438 	/* Local loopback mode? */
439 	mode &= ~ATMEL_US_CHMODE;
440 	if (mctrl & TIOCM_LOOP)
441 		mode |= ATMEL_US_CHMODE_LOC_LOOP;
442 	else
443 		mode |= ATMEL_US_CHMODE_NORMAL;
444 
445 	atmel_uart_writel(port, ATMEL_US_MR, mode);
446 }
447 
448 /*
449  * Get state of the modem control input lines
450  */
451 static u_int atmel_get_mctrl(struct uart_port *port)
452 {
453 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
454 	unsigned int ret = 0, status;
455 
456 	status = atmel_uart_readl(port, ATMEL_US_CSR);
457 
458 	/*
459 	 * The control signals are active low.
460 	 */
461 	if (!(status & ATMEL_US_DCD))
462 		ret |= TIOCM_CD;
463 	if (!(status & ATMEL_US_CTS))
464 		ret |= TIOCM_CTS;
465 	if (!(status & ATMEL_US_DSR))
466 		ret |= TIOCM_DSR;
467 	if (!(status & ATMEL_US_RI))
468 		ret |= TIOCM_RI;
469 
470 	return mctrl_gpio_get(atmel_port->gpios, &ret);
471 }
472 
473 /*
474  * Stop transmitting.
475  */
476 static void atmel_stop_tx(struct uart_port *port)
477 {
478 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
479 
480 	if (atmel_use_pdc_tx(port)) {
481 		/* disable PDC transmit */
482 		atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
483 	}
484 	/* Disable interrupts */
485 	atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
486 
487 	if ((port->rs485.flags & SER_RS485_ENABLED) &&
488 	    !(port->rs485.flags & SER_RS485_RX_DURING_TX))
489 		atmel_start_rx(port);
490 }
491 
492 /*
493  * Start transmitting.
494  */
495 static void atmel_start_tx(struct uart_port *port)
496 {
497 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
498 
499 	if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
500 				       & ATMEL_PDC_TXTEN))
501 		/* The transmitter is already running.  Yes, we
502 		   really need this.*/
503 		return;
504 
505 	if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
506 		if ((port->rs485.flags & SER_RS485_ENABLED) &&
507 		    !(port->rs485.flags & SER_RS485_RX_DURING_TX))
508 			atmel_stop_rx(port);
509 
510 	if (atmel_use_pdc_tx(port))
511 		/* re-enable PDC transmit */
512 		atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
513 
514 	/* Enable interrupts */
515 	atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
516 }
517 
518 /*
519  * start receiving - port is in process of being opened.
520  */
521 static void atmel_start_rx(struct uart_port *port)
522 {
523 	/* reset status and receiver */
524 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
525 
526 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
527 
528 	if (atmel_use_pdc_rx(port)) {
529 		/* enable PDC controller */
530 		atmel_uart_writel(port, ATMEL_US_IER,
531 				  ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
532 				  port->read_status_mask);
533 		atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
534 	} else {
535 		atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
536 	}
537 }
538 
539 /*
540  * Stop receiving - port is in process of being closed.
541  */
542 static void atmel_stop_rx(struct uart_port *port)
543 {
544 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
545 
546 	if (atmel_use_pdc_rx(port)) {
547 		/* disable PDC receive */
548 		atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
549 		atmel_uart_writel(port, ATMEL_US_IDR,
550 				  ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
551 				  port->read_status_mask);
552 	} else {
553 		atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
554 	}
555 }
556 
557 /*
558  * Enable modem status interrupts
559  */
560 static void atmel_enable_ms(struct uart_port *port)
561 {
562 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
563 	uint32_t ier = 0;
564 
565 	/*
566 	 * Interrupt should not be enabled twice
567 	 */
568 	if (atmel_port->ms_irq_enabled)
569 		return;
570 
571 	atmel_port->ms_irq_enabled = true;
572 
573 	if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
574 		ier |= ATMEL_US_CTSIC;
575 
576 	if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
577 		ier |= ATMEL_US_DSRIC;
578 
579 	if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
580 		ier |= ATMEL_US_RIIC;
581 
582 	if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
583 		ier |= ATMEL_US_DCDIC;
584 
585 	atmel_uart_writel(port, ATMEL_US_IER, ier);
586 
587 	mctrl_gpio_enable_ms(atmel_port->gpios);
588 }
589 
590 /*
591  * Disable modem status interrupts
592  */
593 static void atmel_disable_ms(struct uart_port *port)
594 {
595 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
596 	uint32_t idr = 0;
597 
598 	/*
599 	 * Interrupt should not be disabled twice
600 	 */
601 	if (!atmel_port->ms_irq_enabled)
602 		return;
603 
604 	atmel_port->ms_irq_enabled = false;
605 
606 	mctrl_gpio_disable_ms(atmel_port->gpios);
607 
608 	if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
609 		idr |= ATMEL_US_CTSIC;
610 
611 	if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
612 		idr |= ATMEL_US_DSRIC;
613 
614 	if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
615 		idr |= ATMEL_US_RIIC;
616 
617 	if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
618 		idr |= ATMEL_US_DCDIC;
619 
620 	atmel_uart_writel(port, ATMEL_US_IDR, idr);
621 }
622 
623 /*
624  * Control the transmission of a break signal
625  */
626 static void atmel_break_ctl(struct uart_port *port, int break_state)
627 {
628 	if (break_state != 0)
629 		/* start break */
630 		atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
631 	else
632 		/* stop break */
633 		atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
634 }
635 
636 /*
637  * Stores the incoming character in the ring buffer
638  */
639 static void
640 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
641 		     unsigned int ch)
642 {
643 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
644 	struct circ_buf *ring = &atmel_port->rx_ring;
645 	struct atmel_uart_char *c;
646 
647 	if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
648 		/* Buffer overflow, ignore char */
649 		return;
650 
651 	c = &((struct atmel_uart_char *)ring->buf)[ring->head];
652 	c->status	= status;
653 	c->ch		= ch;
654 
655 	/* Make sure the character is stored before we update head. */
656 	smp_wmb();
657 
658 	ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
659 }
660 
661 /*
662  * Deal with parity, framing and overrun errors.
663  */
664 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
665 {
666 	/* clear error */
667 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
668 
669 	if (status & ATMEL_US_RXBRK) {
670 		/* ignore side-effect */
671 		status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
672 		port->icount.brk++;
673 	}
674 	if (status & ATMEL_US_PARE)
675 		port->icount.parity++;
676 	if (status & ATMEL_US_FRAME)
677 		port->icount.frame++;
678 	if (status & ATMEL_US_OVRE)
679 		port->icount.overrun++;
680 }
681 
682 /*
683  * Characters received (called from interrupt handler)
684  */
685 static void atmel_rx_chars(struct uart_port *port)
686 {
687 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
688 	unsigned int status, ch;
689 
690 	status = atmel_uart_readl(port, ATMEL_US_CSR);
691 	while (status & ATMEL_US_RXRDY) {
692 		ch = atmel_uart_read_char(port);
693 
694 		/*
695 		 * note that the error handling code is
696 		 * out of the main execution path
697 		 */
698 		if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
699 				       | ATMEL_US_OVRE | ATMEL_US_RXBRK)
700 			     || atmel_port->break_active)) {
701 
702 			/* clear error */
703 			atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
704 
705 			if (status & ATMEL_US_RXBRK
706 			    && !atmel_port->break_active) {
707 				atmel_port->break_active = 1;
708 				atmel_uart_writel(port, ATMEL_US_IER,
709 						  ATMEL_US_RXBRK);
710 			} else {
711 				/*
712 				 * This is either the end-of-break
713 				 * condition or we've received at
714 				 * least one character without RXBRK
715 				 * being set. In both cases, the next
716 				 * RXBRK will indicate start-of-break.
717 				 */
718 				atmel_uart_writel(port, ATMEL_US_IDR,
719 						  ATMEL_US_RXBRK);
720 				status &= ~ATMEL_US_RXBRK;
721 				atmel_port->break_active = 0;
722 			}
723 		}
724 
725 		atmel_buffer_rx_char(port, status, ch);
726 		status = atmel_uart_readl(port, ATMEL_US_CSR);
727 	}
728 
729 	atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
730 }
731 
732 /*
733  * Transmit characters (called from tasklet with TXRDY interrupt
734  * disabled)
735  */
736 static void atmel_tx_chars(struct uart_port *port)
737 {
738 	struct circ_buf *xmit = &port->state->xmit;
739 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
740 
741 	if (port->x_char &&
742 	    (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
743 		atmel_uart_write_char(port, port->x_char);
744 		port->icount.tx++;
745 		port->x_char = 0;
746 	}
747 	if (uart_circ_empty(xmit) || uart_tx_stopped(port))
748 		return;
749 
750 	while (atmel_uart_readl(port, ATMEL_US_CSR) &
751 	       atmel_port->tx_done_mask) {
752 		atmel_uart_write_char(port, xmit->buf[xmit->tail]);
753 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
754 		port->icount.tx++;
755 		if (uart_circ_empty(xmit))
756 			break;
757 	}
758 
759 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
760 		uart_write_wakeup(port);
761 
762 	if (!uart_circ_empty(xmit))
763 		/* Enable interrupts */
764 		atmel_uart_writel(port, ATMEL_US_IER,
765 				  atmel_port->tx_done_mask);
766 }
767 
768 static void atmel_complete_tx_dma(void *arg)
769 {
770 	struct atmel_uart_port *atmel_port = arg;
771 	struct uart_port *port = &atmel_port->uart;
772 	struct circ_buf *xmit = &port->state->xmit;
773 	struct dma_chan *chan = atmel_port->chan_tx;
774 	unsigned long flags;
775 
776 	spin_lock_irqsave(&port->lock, flags);
777 
778 	if (chan)
779 		dmaengine_terminate_all(chan);
780 	xmit->tail += atmel_port->tx_len;
781 	xmit->tail &= UART_XMIT_SIZE - 1;
782 
783 	port->icount.tx += atmel_port->tx_len;
784 
785 	spin_lock_irq(&atmel_port->lock_tx);
786 	async_tx_ack(atmel_port->desc_tx);
787 	atmel_port->cookie_tx = -EINVAL;
788 	atmel_port->desc_tx = NULL;
789 	spin_unlock_irq(&atmel_port->lock_tx);
790 
791 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
792 		uart_write_wakeup(port);
793 
794 	/*
795 	 * xmit is a circular buffer so, if we have just send data from
796 	 * xmit->tail to the end of xmit->buf, now we have to transmit the
797 	 * remaining data from the beginning of xmit->buf to xmit->head.
798 	 */
799 	if (!uart_circ_empty(xmit))
800 		atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
801 
802 	spin_unlock_irqrestore(&port->lock, flags);
803 }
804 
805 static void atmel_release_tx_dma(struct uart_port *port)
806 {
807 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
808 	struct dma_chan *chan = atmel_port->chan_tx;
809 
810 	if (chan) {
811 		dmaengine_terminate_all(chan);
812 		dma_release_channel(chan);
813 		dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
814 				DMA_TO_DEVICE);
815 	}
816 
817 	atmel_port->desc_tx = NULL;
818 	atmel_port->chan_tx = NULL;
819 	atmel_port->cookie_tx = -EINVAL;
820 }
821 
822 /*
823  * Called from tasklet with TXRDY interrupt is disabled.
824  */
825 static void atmel_tx_dma(struct uart_port *port)
826 {
827 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
828 	struct circ_buf *xmit = &port->state->xmit;
829 	struct dma_chan *chan = atmel_port->chan_tx;
830 	struct dma_async_tx_descriptor *desc;
831 	struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
832 	unsigned int tx_len, part1_len, part2_len, sg_len;
833 	dma_addr_t phys_addr;
834 
835 	/* Make sure we have an idle channel */
836 	if (atmel_port->desc_tx != NULL)
837 		return;
838 
839 	if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
840 		/*
841 		 * DMA is idle now.
842 		 * Port xmit buffer is already mapped,
843 		 * and it is one page... Just adjust
844 		 * offsets and lengths. Since it is a circular buffer,
845 		 * we have to transmit till the end, and then the rest.
846 		 * Take the port lock to get a
847 		 * consistent xmit buffer state.
848 		 */
849 		tx_len = CIRC_CNT_TO_END(xmit->head,
850 					 xmit->tail,
851 					 UART_XMIT_SIZE);
852 
853 		if (atmel_port->fifo_size) {
854 			/* multi data mode */
855 			part1_len = (tx_len & ~0x3); /* DWORD access */
856 			part2_len = (tx_len & 0x3); /* BYTE access */
857 		} else {
858 			/* single data (legacy) mode */
859 			part1_len = 0;
860 			part2_len = tx_len; /* BYTE access only */
861 		}
862 
863 		sg_init_table(sgl, 2);
864 		sg_len = 0;
865 		phys_addr = sg_dma_address(sg_tx) + xmit->tail;
866 		if (part1_len) {
867 			sg = &sgl[sg_len++];
868 			sg_dma_address(sg) = phys_addr;
869 			sg_dma_len(sg) = part1_len;
870 
871 			phys_addr += part1_len;
872 		}
873 
874 		if (part2_len) {
875 			sg = &sgl[sg_len++];
876 			sg_dma_address(sg) = phys_addr;
877 			sg_dma_len(sg) = part2_len;
878 		}
879 
880 		/*
881 		 * save tx_len so atmel_complete_tx_dma() will increase
882 		 * xmit->tail correctly
883 		 */
884 		atmel_port->tx_len = tx_len;
885 
886 		desc = dmaengine_prep_slave_sg(chan,
887 					       sgl,
888 					       sg_len,
889 					       DMA_MEM_TO_DEV,
890 					       DMA_PREP_INTERRUPT |
891 					       DMA_CTRL_ACK);
892 		if (!desc) {
893 			dev_err(port->dev, "Failed to send via dma!\n");
894 			return;
895 		}
896 
897 		dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
898 
899 		atmel_port->desc_tx = desc;
900 		desc->callback = atmel_complete_tx_dma;
901 		desc->callback_param = atmel_port;
902 		atmel_port->cookie_tx = dmaengine_submit(desc);
903 
904 	} else {
905 		if (port->rs485.flags & SER_RS485_ENABLED) {
906 			/* DMA done, stop TX, start RX for RS485 */
907 			atmel_start_rx(port);
908 		}
909 	}
910 
911 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
912 		uart_write_wakeup(port);
913 }
914 
915 static int atmel_prepare_tx_dma(struct uart_port *port)
916 {
917 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
918 	dma_cap_mask_t		mask;
919 	struct dma_slave_config config;
920 	int ret, nent;
921 
922 	dma_cap_zero(mask);
923 	dma_cap_set(DMA_SLAVE, mask);
924 
925 	atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
926 	if (atmel_port->chan_tx == NULL)
927 		goto chan_err;
928 	dev_info(port->dev, "using %s for tx DMA transfers\n",
929 		dma_chan_name(atmel_port->chan_tx));
930 
931 	spin_lock_init(&atmel_port->lock_tx);
932 	sg_init_table(&atmel_port->sg_tx, 1);
933 	/* UART circular tx buffer is an aligned page. */
934 	BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
935 	sg_set_page(&atmel_port->sg_tx,
936 			virt_to_page(port->state->xmit.buf),
937 			UART_XMIT_SIZE,
938 			(unsigned long)port->state->xmit.buf & ~PAGE_MASK);
939 	nent = dma_map_sg(port->dev,
940 				&atmel_port->sg_tx,
941 				1,
942 				DMA_TO_DEVICE);
943 
944 	if (!nent) {
945 		dev_dbg(port->dev, "need to release resource of dma\n");
946 		goto chan_err;
947 	} else {
948 		dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
949 			sg_dma_len(&atmel_port->sg_tx),
950 			port->state->xmit.buf,
951 			&sg_dma_address(&atmel_port->sg_tx));
952 	}
953 
954 	/* Configure the slave DMA */
955 	memset(&config, 0, sizeof(config));
956 	config.direction = DMA_MEM_TO_DEV;
957 	config.dst_addr_width = (atmel_port->fifo_size) ?
958 				DMA_SLAVE_BUSWIDTH_4_BYTES :
959 				DMA_SLAVE_BUSWIDTH_1_BYTE;
960 	config.dst_addr = port->mapbase + ATMEL_US_THR;
961 	config.dst_maxburst = 1;
962 
963 	ret = dmaengine_slave_config(atmel_port->chan_tx,
964 				     &config);
965 	if (ret) {
966 		dev_err(port->dev, "DMA tx slave configuration failed\n");
967 		goto chan_err;
968 	}
969 
970 	return 0;
971 
972 chan_err:
973 	dev_err(port->dev, "TX channel not available, switch to pio\n");
974 	atmel_port->use_dma_tx = 0;
975 	if (atmel_port->chan_tx)
976 		atmel_release_tx_dma(port);
977 	return -EINVAL;
978 }
979 
980 static void atmel_complete_rx_dma(void *arg)
981 {
982 	struct uart_port *port = arg;
983 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
984 
985 	atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
986 }
987 
988 static void atmel_release_rx_dma(struct uart_port *port)
989 {
990 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
991 	struct dma_chan *chan = atmel_port->chan_rx;
992 
993 	if (chan) {
994 		dmaengine_terminate_all(chan);
995 		dma_release_channel(chan);
996 		dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
997 				DMA_FROM_DEVICE);
998 	}
999 
1000 	atmel_port->desc_rx = NULL;
1001 	atmel_port->chan_rx = NULL;
1002 	atmel_port->cookie_rx = -EINVAL;
1003 }
1004 
1005 static void atmel_rx_from_dma(struct uart_port *port)
1006 {
1007 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1008 	struct tty_port *tport = &port->state->port;
1009 	struct circ_buf *ring = &atmel_port->rx_ring;
1010 	struct dma_chan *chan = atmel_port->chan_rx;
1011 	struct dma_tx_state state;
1012 	enum dma_status dmastat;
1013 	size_t count;
1014 
1015 
1016 	/* Reset the UART timeout early so that we don't miss one */
1017 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1018 	dmastat = dmaengine_tx_status(chan,
1019 				atmel_port->cookie_rx,
1020 				&state);
1021 	/* Restart a new tasklet if DMA status is error */
1022 	if (dmastat == DMA_ERROR) {
1023 		dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1024 		atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1025 		atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1026 		return;
1027 	}
1028 
1029 	/* CPU claims ownership of RX DMA buffer */
1030 	dma_sync_sg_for_cpu(port->dev,
1031 			    &atmel_port->sg_rx,
1032 			    1,
1033 			    DMA_FROM_DEVICE);
1034 
1035 	/*
1036 	 * ring->head points to the end of data already written by the DMA.
1037 	 * ring->tail points to the beginning of data to be read by the
1038 	 * framework.
1039 	 * The current transfer size should not be larger than the dma buffer
1040 	 * length.
1041 	 */
1042 	ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1043 	BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1044 	/*
1045 	 * At this point ring->head may point to the first byte right after the
1046 	 * last byte of the dma buffer:
1047 	 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1048 	 *
1049 	 * However ring->tail must always points inside the dma buffer:
1050 	 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1051 	 *
1052 	 * Since we use a ring buffer, we have to handle the case
1053 	 * where head is lower than tail. In such a case, we first read from
1054 	 * tail to the end of the buffer then reset tail.
1055 	 */
1056 	if (ring->head < ring->tail) {
1057 		count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1058 
1059 		tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1060 		ring->tail = 0;
1061 		port->icount.rx += count;
1062 	}
1063 
1064 	/* Finally we read data from tail to head */
1065 	if (ring->tail < ring->head) {
1066 		count = ring->head - ring->tail;
1067 
1068 		tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1069 		/* Wrap ring->head if needed */
1070 		if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1071 			ring->head = 0;
1072 		ring->tail = ring->head;
1073 		port->icount.rx += count;
1074 	}
1075 
1076 	/* USART retreives ownership of RX DMA buffer */
1077 	dma_sync_sg_for_device(port->dev,
1078 			       &atmel_port->sg_rx,
1079 			       1,
1080 			       DMA_FROM_DEVICE);
1081 
1082 	/*
1083 	 * Drop the lock here since it might end up calling
1084 	 * uart_start(), which takes the lock.
1085 	 */
1086 	spin_unlock(&port->lock);
1087 	tty_flip_buffer_push(tport);
1088 	spin_lock(&port->lock);
1089 
1090 	atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1091 }
1092 
1093 static int atmel_prepare_rx_dma(struct uart_port *port)
1094 {
1095 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1096 	struct dma_async_tx_descriptor *desc;
1097 	dma_cap_mask_t		mask;
1098 	struct dma_slave_config config;
1099 	struct circ_buf		*ring;
1100 	int ret, nent;
1101 
1102 	ring = &atmel_port->rx_ring;
1103 
1104 	dma_cap_zero(mask);
1105 	dma_cap_set(DMA_CYCLIC, mask);
1106 
1107 	atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1108 	if (atmel_port->chan_rx == NULL)
1109 		goto chan_err;
1110 	dev_info(port->dev, "using %s for rx DMA transfers\n",
1111 		dma_chan_name(atmel_port->chan_rx));
1112 
1113 	spin_lock_init(&atmel_port->lock_rx);
1114 	sg_init_table(&atmel_port->sg_rx, 1);
1115 	/* UART circular rx buffer is an aligned page. */
1116 	BUG_ON(!PAGE_ALIGNED(ring->buf));
1117 	sg_set_page(&atmel_port->sg_rx,
1118 		    virt_to_page(ring->buf),
1119 		    sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1120 		    (unsigned long)ring->buf & ~PAGE_MASK);
1121 	nent = dma_map_sg(port->dev,
1122 			  &atmel_port->sg_rx,
1123 			  1,
1124 			  DMA_FROM_DEVICE);
1125 
1126 	if (!nent) {
1127 		dev_dbg(port->dev, "need to release resource of dma\n");
1128 		goto chan_err;
1129 	} else {
1130 		dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1131 			sg_dma_len(&atmel_port->sg_rx),
1132 			ring->buf,
1133 			&sg_dma_address(&atmel_port->sg_rx));
1134 	}
1135 
1136 	/* Configure the slave DMA */
1137 	memset(&config, 0, sizeof(config));
1138 	config.direction = DMA_DEV_TO_MEM;
1139 	config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1140 	config.src_addr = port->mapbase + ATMEL_US_RHR;
1141 	config.src_maxburst = 1;
1142 
1143 	ret = dmaengine_slave_config(atmel_port->chan_rx,
1144 				     &config);
1145 	if (ret) {
1146 		dev_err(port->dev, "DMA rx slave configuration failed\n");
1147 		goto chan_err;
1148 	}
1149 	/*
1150 	 * Prepare a cyclic dma transfer, assign 2 descriptors,
1151 	 * each one is half ring buffer size
1152 	 */
1153 	desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1154 					 sg_dma_address(&atmel_port->sg_rx),
1155 					 sg_dma_len(&atmel_port->sg_rx),
1156 					 sg_dma_len(&atmel_port->sg_rx)/2,
1157 					 DMA_DEV_TO_MEM,
1158 					 DMA_PREP_INTERRUPT);
1159 	desc->callback = atmel_complete_rx_dma;
1160 	desc->callback_param = port;
1161 	atmel_port->desc_rx = desc;
1162 	atmel_port->cookie_rx = dmaengine_submit(desc);
1163 
1164 	return 0;
1165 
1166 chan_err:
1167 	dev_err(port->dev, "RX channel not available, switch to pio\n");
1168 	atmel_port->use_dma_rx = 0;
1169 	if (atmel_port->chan_rx)
1170 		atmel_release_rx_dma(port);
1171 	return -EINVAL;
1172 }
1173 
1174 static void atmel_uart_timer_callback(unsigned long data)
1175 {
1176 	struct uart_port *port = (void *)data;
1177 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1178 
1179 	if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1180 		tasklet_schedule(&atmel_port->tasklet_rx);
1181 		mod_timer(&atmel_port->uart_timer,
1182 			  jiffies + uart_poll_timeout(port));
1183 	}
1184 }
1185 
1186 /*
1187  * receive interrupt handler.
1188  */
1189 static void
1190 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1191 {
1192 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1193 
1194 	if (atmel_use_pdc_rx(port)) {
1195 		/*
1196 		 * PDC receive. Just schedule the tasklet and let it
1197 		 * figure out the details.
1198 		 *
1199 		 * TODO: We're not handling error flags correctly at
1200 		 * the moment.
1201 		 */
1202 		if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1203 			atmel_uart_writel(port, ATMEL_US_IDR,
1204 					  (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1205 			atmel_tasklet_schedule(atmel_port,
1206 					       &atmel_port->tasklet_rx);
1207 		}
1208 
1209 		if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1210 				ATMEL_US_FRAME | ATMEL_US_PARE))
1211 			atmel_pdc_rxerr(port, pending);
1212 	}
1213 
1214 	if (atmel_use_dma_rx(port)) {
1215 		if (pending & ATMEL_US_TIMEOUT) {
1216 			atmel_uart_writel(port, ATMEL_US_IDR,
1217 					  ATMEL_US_TIMEOUT);
1218 			atmel_tasklet_schedule(atmel_port,
1219 					       &atmel_port->tasklet_rx);
1220 		}
1221 	}
1222 
1223 	/* Interrupt receive */
1224 	if (pending & ATMEL_US_RXRDY)
1225 		atmel_rx_chars(port);
1226 	else if (pending & ATMEL_US_RXBRK) {
1227 		/*
1228 		 * End of break detected. If it came along with a
1229 		 * character, atmel_rx_chars will handle it.
1230 		 */
1231 		atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1232 		atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1233 		atmel_port->break_active = 0;
1234 	}
1235 }
1236 
1237 /*
1238  * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1239  */
1240 static void
1241 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1242 {
1243 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1244 
1245 	if (pending & atmel_port->tx_done_mask) {
1246 		/* Either PDC or interrupt transmission */
1247 		atmel_uart_writel(port, ATMEL_US_IDR,
1248 				  atmel_port->tx_done_mask);
1249 		atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1250 	}
1251 }
1252 
1253 /*
1254  * status flags interrupt handler.
1255  */
1256 static void
1257 atmel_handle_status(struct uart_port *port, unsigned int pending,
1258 		    unsigned int status)
1259 {
1260 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1261 	unsigned int status_change;
1262 
1263 	if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1264 				| ATMEL_US_CTSIC)) {
1265 		status_change = status ^ atmel_port->irq_status_prev;
1266 		atmel_port->irq_status_prev = status;
1267 
1268 		if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1269 					| ATMEL_US_DCD | ATMEL_US_CTS)) {
1270 			/* TODO: All reads to CSR will clear these interrupts! */
1271 			if (status_change & ATMEL_US_RI)
1272 				port->icount.rng++;
1273 			if (status_change & ATMEL_US_DSR)
1274 				port->icount.dsr++;
1275 			if (status_change & ATMEL_US_DCD)
1276 				uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1277 			if (status_change & ATMEL_US_CTS)
1278 				uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1279 
1280 			wake_up_interruptible(&port->state->port.delta_msr_wait);
1281 		}
1282 	}
1283 }
1284 
1285 /*
1286  * Interrupt handler
1287  */
1288 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1289 {
1290 	struct uart_port *port = dev_id;
1291 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1292 	unsigned int status, pending, mask, pass_counter = 0;
1293 
1294 	spin_lock(&atmel_port->lock_suspended);
1295 
1296 	do {
1297 		status = atmel_get_lines_status(port);
1298 		mask = atmel_uart_readl(port, ATMEL_US_IMR);
1299 		pending = status & mask;
1300 		if (!pending)
1301 			break;
1302 
1303 		if (atmel_port->suspended) {
1304 			atmel_port->pending |= pending;
1305 			atmel_port->pending_status = status;
1306 			atmel_uart_writel(port, ATMEL_US_IDR, mask);
1307 			pm_system_wakeup();
1308 			break;
1309 		}
1310 
1311 		atmel_handle_receive(port, pending);
1312 		atmel_handle_status(port, pending, status);
1313 		atmel_handle_transmit(port, pending);
1314 	} while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1315 
1316 	spin_unlock(&atmel_port->lock_suspended);
1317 
1318 	return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1319 }
1320 
1321 static void atmel_release_tx_pdc(struct uart_port *port)
1322 {
1323 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1324 	struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1325 
1326 	dma_unmap_single(port->dev,
1327 			 pdc->dma_addr,
1328 			 pdc->dma_size,
1329 			 DMA_TO_DEVICE);
1330 }
1331 
1332 /*
1333  * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1334  */
1335 static void atmel_tx_pdc(struct uart_port *port)
1336 {
1337 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1338 	struct circ_buf *xmit = &port->state->xmit;
1339 	struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1340 	int count;
1341 
1342 	/* nothing left to transmit? */
1343 	if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1344 		return;
1345 
1346 	xmit->tail += pdc->ofs;
1347 	xmit->tail &= UART_XMIT_SIZE - 1;
1348 
1349 	port->icount.tx += pdc->ofs;
1350 	pdc->ofs = 0;
1351 
1352 	/* more to transmit - setup next transfer */
1353 
1354 	/* disable PDC transmit */
1355 	atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1356 
1357 	if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1358 		dma_sync_single_for_device(port->dev,
1359 					   pdc->dma_addr,
1360 					   pdc->dma_size,
1361 					   DMA_TO_DEVICE);
1362 
1363 		count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1364 		pdc->ofs = count;
1365 
1366 		atmel_uart_writel(port, ATMEL_PDC_TPR,
1367 				  pdc->dma_addr + xmit->tail);
1368 		atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1369 		/* re-enable PDC transmit */
1370 		atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1371 		/* Enable interrupts */
1372 		atmel_uart_writel(port, ATMEL_US_IER,
1373 				  atmel_port->tx_done_mask);
1374 	} else {
1375 		if ((port->rs485.flags & SER_RS485_ENABLED) &&
1376 		    !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1377 			/* DMA done, stop TX, start RX for RS485 */
1378 			atmel_start_rx(port);
1379 		}
1380 	}
1381 
1382 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1383 		uart_write_wakeup(port);
1384 }
1385 
1386 static int atmel_prepare_tx_pdc(struct uart_port *port)
1387 {
1388 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1389 	struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1390 	struct circ_buf *xmit = &port->state->xmit;
1391 
1392 	pdc->buf = xmit->buf;
1393 	pdc->dma_addr = dma_map_single(port->dev,
1394 					pdc->buf,
1395 					UART_XMIT_SIZE,
1396 					DMA_TO_DEVICE);
1397 	pdc->dma_size = UART_XMIT_SIZE;
1398 	pdc->ofs = 0;
1399 
1400 	return 0;
1401 }
1402 
1403 static void atmel_rx_from_ring(struct uart_port *port)
1404 {
1405 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1406 	struct circ_buf *ring = &atmel_port->rx_ring;
1407 	unsigned int flg;
1408 	unsigned int status;
1409 
1410 	while (ring->head != ring->tail) {
1411 		struct atmel_uart_char c;
1412 
1413 		/* Make sure c is loaded after head. */
1414 		smp_rmb();
1415 
1416 		c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1417 
1418 		ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1419 
1420 		port->icount.rx++;
1421 		status = c.status;
1422 		flg = TTY_NORMAL;
1423 
1424 		/*
1425 		 * note that the error handling code is
1426 		 * out of the main execution path
1427 		 */
1428 		if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1429 				       | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1430 			if (status & ATMEL_US_RXBRK) {
1431 				/* ignore side-effect */
1432 				status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1433 
1434 				port->icount.brk++;
1435 				if (uart_handle_break(port))
1436 					continue;
1437 			}
1438 			if (status & ATMEL_US_PARE)
1439 				port->icount.parity++;
1440 			if (status & ATMEL_US_FRAME)
1441 				port->icount.frame++;
1442 			if (status & ATMEL_US_OVRE)
1443 				port->icount.overrun++;
1444 
1445 			status &= port->read_status_mask;
1446 
1447 			if (status & ATMEL_US_RXBRK)
1448 				flg = TTY_BREAK;
1449 			else if (status & ATMEL_US_PARE)
1450 				flg = TTY_PARITY;
1451 			else if (status & ATMEL_US_FRAME)
1452 				flg = TTY_FRAME;
1453 		}
1454 
1455 
1456 		if (uart_handle_sysrq_char(port, c.ch))
1457 			continue;
1458 
1459 		uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1460 	}
1461 
1462 	/*
1463 	 * Drop the lock here since it might end up calling
1464 	 * uart_start(), which takes the lock.
1465 	 */
1466 	spin_unlock(&port->lock);
1467 	tty_flip_buffer_push(&port->state->port);
1468 	spin_lock(&port->lock);
1469 }
1470 
1471 static void atmel_release_rx_pdc(struct uart_port *port)
1472 {
1473 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1474 	int i;
1475 
1476 	for (i = 0; i < 2; i++) {
1477 		struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1478 
1479 		dma_unmap_single(port->dev,
1480 				 pdc->dma_addr,
1481 				 pdc->dma_size,
1482 				 DMA_FROM_DEVICE);
1483 		kfree(pdc->buf);
1484 	}
1485 }
1486 
1487 static void atmel_rx_from_pdc(struct uart_port *port)
1488 {
1489 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1490 	struct tty_port *tport = &port->state->port;
1491 	struct atmel_dma_buffer *pdc;
1492 	int rx_idx = atmel_port->pdc_rx_idx;
1493 	unsigned int head;
1494 	unsigned int tail;
1495 	unsigned int count;
1496 
1497 	do {
1498 		/* Reset the UART timeout early so that we don't miss one */
1499 		atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1500 
1501 		pdc = &atmel_port->pdc_rx[rx_idx];
1502 		head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1503 		tail = pdc->ofs;
1504 
1505 		/* If the PDC has switched buffers, RPR won't contain
1506 		 * any address within the current buffer. Since head
1507 		 * is unsigned, we just need a one-way comparison to
1508 		 * find out.
1509 		 *
1510 		 * In this case, we just need to consume the entire
1511 		 * buffer and resubmit it for DMA. This will clear the
1512 		 * ENDRX bit as well, so that we can safely re-enable
1513 		 * all interrupts below.
1514 		 */
1515 		head = min(head, pdc->dma_size);
1516 
1517 		if (likely(head != tail)) {
1518 			dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1519 					pdc->dma_size, DMA_FROM_DEVICE);
1520 
1521 			/*
1522 			 * head will only wrap around when we recycle
1523 			 * the DMA buffer, and when that happens, we
1524 			 * explicitly set tail to 0. So head will
1525 			 * always be greater than tail.
1526 			 */
1527 			count = head - tail;
1528 
1529 			tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1530 						count);
1531 
1532 			dma_sync_single_for_device(port->dev, pdc->dma_addr,
1533 					pdc->dma_size, DMA_FROM_DEVICE);
1534 
1535 			port->icount.rx += count;
1536 			pdc->ofs = head;
1537 		}
1538 
1539 		/*
1540 		 * If the current buffer is full, we need to check if
1541 		 * the next one contains any additional data.
1542 		 */
1543 		if (head >= pdc->dma_size) {
1544 			pdc->ofs = 0;
1545 			atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1546 			atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1547 
1548 			rx_idx = !rx_idx;
1549 			atmel_port->pdc_rx_idx = rx_idx;
1550 		}
1551 	} while (head >= pdc->dma_size);
1552 
1553 	/*
1554 	 * Drop the lock here since it might end up calling
1555 	 * uart_start(), which takes the lock.
1556 	 */
1557 	spin_unlock(&port->lock);
1558 	tty_flip_buffer_push(tport);
1559 	spin_lock(&port->lock);
1560 
1561 	atmel_uart_writel(port, ATMEL_US_IER,
1562 			  ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1563 }
1564 
1565 static int atmel_prepare_rx_pdc(struct uart_port *port)
1566 {
1567 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1568 	int i;
1569 
1570 	for (i = 0; i < 2; i++) {
1571 		struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1572 
1573 		pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1574 		if (pdc->buf == NULL) {
1575 			if (i != 0) {
1576 				dma_unmap_single(port->dev,
1577 					atmel_port->pdc_rx[0].dma_addr,
1578 					PDC_BUFFER_SIZE,
1579 					DMA_FROM_DEVICE);
1580 				kfree(atmel_port->pdc_rx[0].buf);
1581 			}
1582 			atmel_port->use_pdc_rx = 0;
1583 			return -ENOMEM;
1584 		}
1585 		pdc->dma_addr = dma_map_single(port->dev,
1586 						pdc->buf,
1587 						PDC_BUFFER_SIZE,
1588 						DMA_FROM_DEVICE);
1589 		pdc->dma_size = PDC_BUFFER_SIZE;
1590 		pdc->ofs = 0;
1591 	}
1592 
1593 	atmel_port->pdc_rx_idx = 0;
1594 
1595 	atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1596 	atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1597 
1598 	atmel_uart_writel(port, ATMEL_PDC_RNPR,
1599 			  atmel_port->pdc_rx[1].dma_addr);
1600 	atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1601 
1602 	return 0;
1603 }
1604 
1605 /*
1606  * tasklet handling tty stuff outside the interrupt handler.
1607  */
1608 static void atmel_tasklet_rx_func(unsigned long data)
1609 {
1610 	struct uart_port *port = (struct uart_port *)data;
1611 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1612 
1613 	/* The interrupt handler does not take the lock */
1614 	spin_lock(&port->lock);
1615 	atmel_port->schedule_rx(port);
1616 	spin_unlock(&port->lock);
1617 }
1618 
1619 static void atmel_tasklet_tx_func(unsigned long data)
1620 {
1621 	struct uart_port *port = (struct uart_port *)data;
1622 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1623 
1624 	/* The interrupt handler does not take the lock */
1625 	spin_lock(&port->lock);
1626 	atmel_port->schedule_tx(port);
1627 	spin_unlock(&port->lock);
1628 }
1629 
1630 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1631 				struct platform_device *pdev)
1632 {
1633 	struct device_node *np = pdev->dev.of_node;
1634 	struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1635 
1636 	if (np) {
1637 		/* DMA/PDC usage specification */
1638 		if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1639 			if (of_property_read_bool(np, "dmas")) {
1640 				atmel_port->use_dma_rx  = true;
1641 				atmel_port->use_pdc_rx  = false;
1642 			} else {
1643 				atmel_port->use_dma_rx  = false;
1644 				atmel_port->use_pdc_rx  = true;
1645 			}
1646 		} else {
1647 			atmel_port->use_dma_rx  = false;
1648 			atmel_port->use_pdc_rx  = false;
1649 		}
1650 
1651 		if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1652 			if (of_property_read_bool(np, "dmas")) {
1653 				atmel_port->use_dma_tx  = true;
1654 				atmel_port->use_pdc_tx  = false;
1655 			} else {
1656 				atmel_port->use_dma_tx  = false;
1657 				atmel_port->use_pdc_tx  = true;
1658 			}
1659 		} else {
1660 			atmel_port->use_dma_tx  = false;
1661 			atmel_port->use_pdc_tx  = false;
1662 		}
1663 
1664 	} else {
1665 		atmel_port->use_pdc_rx  = pdata->use_dma_rx;
1666 		atmel_port->use_pdc_tx  = pdata->use_dma_tx;
1667 		atmel_port->use_dma_rx  = false;
1668 		atmel_port->use_dma_tx  = false;
1669 	}
1670 
1671 }
1672 
1673 static void atmel_init_rs485(struct uart_port *port,
1674 				struct platform_device *pdev)
1675 {
1676 	struct device_node *np = pdev->dev.of_node;
1677 	struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1678 
1679 	if (np) {
1680 		struct serial_rs485 *rs485conf = &port->rs485;
1681 		u32 rs485_delay[2];
1682 		/* rs485 properties */
1683 		if (of_property_read_u32_array(np, "rs485-rts-delay",
1684 					rs485_delay, 2) == 0) {
1685 			rs485conf->delay_rts_before_send = rs485_delay[0];
1686 			rs485conf->delay_rts_after_send = rs485_delay[1];
1687 			rs485conf->flags = 0;
1688 		}
1689 
1690 		if (of_get_property(np, "rs485-rx-during-tx", NULL))
1691 			rs485conf->flags |= SER_RS485_RX_DURING_TX;
1692 
1693 		if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1694 								NULL))
1695 			rs485conf->flags |= SER_RS485_ENABLED;
1696 	} else {
1697 		port->rs485       = pdata->rs485;
1698 	}
1699 
1700 }
1701 
1702 static void atmel_set_ops(struct uart_port *port)
1703 {
1704 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1705 
1706 	if (atmel_use_dma_rx(port)) {
1707 		atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1708 		atmel_port->schedule_rx = &atmel_rx_from_dma;
1709 		atmel_port->release_rx = &atmel_release_rx_dma;
1710 	} else if (atmel_use_pdc_rx(port)) {
1711 		atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1712 		atmel_port->schedule_rx = &atmel_rx_from_pdc;
1713 		atmel_port->release_rx = &atmel_release_rx_pdc;
1714 	} else {
1715 		atmel_port->prepare_rx = NULL;
1716 		atmel_port->schedule_rx = &atmel_rx_from_ring;
1717 		atmel_port->release_rx = NULL;
1718 	}
1719 
1720 	if (atmel_use_dma_tx(port)) {
1721 		atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1722 		atmel_port->schedule_tx = &atmel_tx_dma;
1723 		atmel_port->release_tx = &atmel_release_tx_dma;
1724 	} else if (atmel_use_pdc_tx(port)) {
1725 		atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1726 		atmel_port->schedule_tx = &atmel_tx_pdc;
1727 		atmel_port->release_tx = &atmel_release_tx_pdc;
1728 	} else {
1729 		atmel_port->prepare_tx = NULL;
1730 		atmel_port->schedule_tx = &atmel_tx_chars;
1731 		atmel_port->release_tx = NULL;
1732 	}
1733 }
1734 
1735 /*
1736  * Get ip name usart or uart
1737  */
1738 static void atmel_get_ip_name(struct uart_port *port)
1739 {
1740 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1741 	int name = atmel_uart_readl(port, ATMEL_US_NAME);
1742 	u32 version;
1743 	u32 usart, dbgu_uart, new_uart;
1744 	/* ASCII decoding for IP version */
1745 	usart = 0x55534152;	/* USAR(T) */
1746 	dbgu_uart = 0x44424755;	/* DBGU */
1747 	new_uart = 0x55415254;	/* UART */
1748 
1749 	/*
1750 	 * Only USART devices from at91sam9260 SOC implement fractional
1751 	 * baudrate.
1752 	 */
1753 	atmel_port->has_frac_baudrate = false;
1754 	atmel_port->has_hw_timer = false;
1755 
1756 	if (name == new_uart) {
1757 		dev_dbg(port->dev, "Uart with hw timer");
1758 		atmel_port->has_hw_timer = true;
1759 		atmel_port->rtor = ATMEL_UA_RTOR;
1760 	} else if (name == usart) {
1761 		dev_dbg(port->dev, "Usart\n");
1762 		atmel_port->has_frac_baudrate = true;
1763 		atmel_port->has_hw_timer = true;
1764 		atmel_port->rtor = ATMEL_US_RTOR;
1765 	} else if (name == dbgu_uart) {
1766 		dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1767 	} else {
1768 		/* fallback for older SoCs: use version field */
1769 		version = atmel_uart_readl(port, ATMEL_US_VERSION);
1770 		switch (version) {
1771 		case 0x302:
1772 		case 0x10213:
1773 			dev_dbg(port->dev, "This version is usart\n");
1774 			atmel_port->has_frac_baudrate = true;
1775 			atmel_port->has_hw_timer = true;
1776 			atmel_port->rtor = ATMEL_US_RTOR;
1777 			break;
1778 		case 0x203:
1779 		case 0x10202:
1780 			dev_dbg(port->dev, "This version is uart\n");
1781 			break;
1782 		default:
1783 			dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1784 		}
1785 	}
1786 }
1787 
1788 /*
1789  * Perform initialization and enable port for reception
1790  */
1791 static int atmel_startup(struct uart_port *port)
1792 {
1793 	struct platform_device *pdev = to_platform_device(port->dev);
1794 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1795 	struct tty_struct *tty = port->state->port.tty;
1796 	int retval;
1797 
1798 	/*
1799 	 * Ensure that no interrupts are enabled otherwise when
1800 	 * request_irq() is called we could get stuck trying to
1801 	 * handle an unexpected interrupt
1802 	 */
1803 	atmel_uart_writel(port, ATMEL_US_IDR, -1);
1804 	atmel_port->ms_irq_enabled = false;
1805 
1806 	/*
1807 	 * Allocate the IRQ
1808 	 */
1809 	retval = request_irq(port->irq, atmel_interrupt,
1810 			IRQF_SHARED | IRQF_COND_SUSPEND,
1811 			tty ? tty->name : "atmel_serial", port);
1812 	if (retval) {
1813 		dev_err(port->dev, "atmel_startup - Can't get irq\n");
1814 		return retval;
1815 	}
1816 
1817 	atomic_set(&atmel_port->tasklet_shutdown, 0);
1818 	tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1819 			(unsigned long)port);
1820 	tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1821 			(unsigned long)port);
1822 
1823 	/*
1824 	 * Initialize DMA (if necessary)
1825 	 */
1826 	atmel_init_property(atmel_port, pdev);
1827 	atmel_set_ops(port);
1828 
1829 	if (atmel_port->prepare_rx) {
1830 		retval = atmel_port->prepare_rx(port);
1831 		if (retval < 0)
1832 			atmel_set_ops(port);
1833 	}
1834 
1835 	if (atmel_port->prepare_tx) {
1836 		retval = atmel_port->prepare_tx(port);
1837 		if (retval < 0)
1838 			atmel_set_ops(port);
1839 	}
1840 
1841 	/*
1842 	 * Enable FIFO when available
1843 	 */
1844 	if (atmel_port->fifo_size) {
1845 		unsigned int txrdym = ATMEL_US_ONE_DATA;
1846 		unsigned int rxrdym = ATMEL_US_ONE_DATA;
1847 		unsigned int fmr;
1848 
1849 		atmel_uart_writel(port, ATMEL_US_CR,
1850 				  ATMEL_US_FIFOEN |
1851 				  ATMEL_US_RXFCLR |
1852 				  ATMEL_US_TXFLCLR);
1853 
1854 		if (atmel_use_dma_tx(port))
1855 			txrdym = ATMEL_US_FOUR_DATA;
1856 
1857 		fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1858 		if (atmel_port->rts_high &&
1859 		    atmel_port->rts_low)
1860 			fmr |=	ATMEL_US_FRTSC |
1861 				ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1862 				ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1863 
1864 		atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1865 	}
1866 
1867 	/* Save current CSR for comparison in atmel_tasklet_func() */
1868 	atmel_port->irq_status_prev = atmel_get_lines_status(port);
1869 
1870 	/*
1871 	 * Finally, enable the serial port
1872 	 */
1873 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1874 	/* enable xmit & rcvr */
1875 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1876 
1877 	setup_timer(&atmel_port->uart_timer,
1878 			atmel_uart_timer_callback,
1879 			(unsigned long)port);
1880 
1881 	if (atmel_use_pdc_rx(port)) {
1882 		/* set UART timeout */
1883 		if (!atmel_port->has_hw_timer) {
1884 			mod_timer(&atmel_port->uart_timer,
1885 					jiffies + uart_poll_timeout(port));
1886 		/* set USART timeout */
1887 		} else {
1888 			atmel_uart_writel(port, atmel_port->rtor,
1889 					  PDC_RX_TIMEOUT);
1890 			atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1891 
1892 			atmel_uart_writel(port, ATMEL_US_IER,
1893 					  ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1894 		}
1895 		/* enable PDC controller */
1896 		atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1897 	} else if (atmel_use_dma_rx(port)) {
1898 		/* set UART timeout */
1899 		if (!atmel_port->has_hw_timer) {
1900 			mod_timer(&atmel_port->uart_timer,
1901 					jiffies + uart_poll_timeout(port));
1902 		/* set USART timeout */
1903 		} else {
1904 			atmel_uart_writel(port, atmel_port->rtor,
1905 					  PDC_RX_TIMEOUT);
1906 			atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1907 
1908 			atmel_uart_writel(port, ATMEL_US_IER,
1909 					  ATMEL_US_TIMEOUT);
1910 		}
1911 	} else {
1912 		/* enable receive only */
1913 		atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1914 	}
1915 
1916 	return 0;
1917 }
1918 
1919 /*
1920  * Flush any TX data submitted for DMA. Called when the TX circular
1921  * buffer is reset.
1922  */
1923 static void atmel_flush_buffer(struct uart_port *port)
1924 {
1925 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1926 
1927 	if (atmel_use_pdc_tx(port)) {
1928 		atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1929 		atmel_port->pdc_tx.ofs = 0;
1930 	}
1931 }
1932 
1933 /*
1934  * Disable the port
1935  */
1936 static void atmel_shutdown(struct uart_port *port)
1937 {
1938 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1939 
1940 	/* Disable modem control lines interrupts */
1941 	atmel_disable_ms(port);
1942 
1943 	/* Disable interrupts at device level */
1944 	atmel_uart_writel(port, ATMEL_US_IDR, -1);
1945 
1946 	/* Prevent spurious interrupts from scheduling the tasklet */
1947 	atomic_inc(&atmel_port->tasklet_shutdown);
1948 
1949 	/*
1950 	 * Prevent any tasklets being scheduled during
1951 	 * cleanup
1952 	 */
1953 	del_timer_sync(&atmel_port->uart_timer);
1954 
1955 	/* Make sure that no interrupt is on the fly */
1956 	synchronize_irq(port->irq);
1957 
1958 	/*
1959 	 * Clear out any scheduled tasklets before
1960 	 * we destroy the buffers
1961 	 */
1962 	tasklet_kill(&atmel_port->tasklet_rx);
1963 	tasklet_kill(&atmel_port->tasklet_tx);
1964 
1965 	/*
1966 	 * Ensure everything is stopped and
1967 	 * disable port and break condition.
1968 	 */
1969 	atmel_stop_rx(port);
1970 	atmel_stop_tx(port);
1971 
1972 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1973 
1974 	/*
1975 	 * Shut-down the DMA.
1976 	 */
1977 	if (atmel_port->release_rx)
1978 		atmel_port->release_rx(port);
1979 	if (atmel_port->release_tx)
1980 		atmel_port->release_tx(port);
1981 
1982 	/*
1983 	 * Reset ring buffer pointers
1984 	 */
1985 	atmel_port->rx_ring.head = 0;
1986 	atmel_port->rx_ring.tail = 0;
1987 
1988 	/*
1989 	 * Free the interrupts
1990 	 */
1991 	free_irq(port->irq, port);
1992 
1993 	atmel_flush_buffer(port);
1994 }
1995 
1996 /*
1997  * Power / Clock management.
1998  */
1999 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2000 			    unsigned int oldstate)
2001 {
2002 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2003 
2004 	switch (state) {
2005 	case 0:
2006 		/*
2007 		 * Enable the peripheral clock for this serial port.
2008 		 * This is called on uart_open() or a resume event.
2009 		 */
2010 		clk_prepare_enable(atmel_port->clk);
2011 
2012 		/* re-enable interrupts if we disabled some on suspend */
2013 		atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2014 		break;
2015 	case 3:
2016 		/* Back up the interrupt mask and disable all interrupts */
2017 		atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2018 		atmel_uart_writel(port, ATMEL_US_IDR, -1);
2019 
2020 		/*
2021 		 * Disable the peripheral clock for this serial port.
2022 		 * This is called on uart_close() or a suspend event.
2023 		 */
2024 		clk_disable_unprepare(atmel_port->clk);
2025 		break;
2026 	default:
2027 		dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2028 	}
2029 }
2030 
2031 /*
2032  * Change the port parameters
2033  */
2034 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2035 			      struct ktermios *old)
2036 {
2037 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2038 	unsigned long flags;
2039 	unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2040 
2041 	/* save the current mode register */
2042 	mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2043 
2044 	/* reset the mode, clock divisor, parity, stop bits and data size */
2045 	mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2046 		  ATMEL_US_PAR | ATMEL_US_USMODE);
2047 
2048 	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2049 
2050 	/* byte size */
2051 	switch (termios->c_cflag & CSIZE) {
2052 	case CS5:
2053 		mode |= ATMEL_US_CHRL_5;
2054 		break;
2055 	case CS6:
2056 		mode |= ATMEL_US_CHRL_6;
2057 		break;
2058 	case CS7:
2059 		mode |= ATMEL_US_CHRL_7;
2060 		break;
2061 	default:
2062 		mode |= ATMEL_US_CHRL_8;
2063 		break;
2064 	}
2065 
2066 	/* stop bits */
2067 	if (termios->c_cflag & CSTOPB)
2068 		mode |= ATMEL_US_NBSTOP_2;
2069 
2070 	/* parity */
2071 	if (termios->c_cflag & PARENB) {
2072 		/* Mark or Space parity */
2073 		if (termios->c_cflag & CMSPAR) {
2074 			if (termios->c_cflag & PARODD)
2075 				mode |= ATMEL_US_PAR_MARK;
2076 			else
2077 				mode |= ATMEL_US_PAR_SPACE;
2078 		} else if (termios->c_cflag & PARODD)
2079 			mode |= ATMEL_US_PAR_ODD;
2080 		else
2081 			mode |= ATMEL_US_PAR_EVEN;
2082 	} else
2083 		mode |= ATMEL_US_PAR_NONE;
2084 
2085 	spin_lock_irqsave(&port->lock, flags);
2086 
2087 	port->read_status_mask = ATMEL_US_OVRE;
2088 	if (termios->c_iflag & INPCK)
2089 		port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2090 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2091 		port->read_status_mask |= ATMEL_US_RXBRK;
2092 
2093 	if (atmel_use_pdc_rx(port))
2094 		/* need to enable error interrupts */
2095 		atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2096 
2097 	/*
2098 	 * Characters to ignore
2099 	 */
2100 	port->ignore_status_mask = 0;
2101 	if (termios->c_iflag & IGNPAR)
2102 		port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2103 	if (termios->c_iflag & IGNBRK) {
2104 		port->ignore_status_mask |= ATMEL_US_RXBRK;
2105 		/*
2106 		 * If we're ignoring parity and break indicators,
2107 		 * ignore overruns too (for real raw support).
2108 		 */
2109 		if (termios->c_iflag & IGNPAR)
2110 			port->ignore_status_mask |= ATMEL_US_OVRE;
2111 	}
2112 	/* TODO: Ignore all characters if CREAD is set.*/
2113 
2114 	/* update the per-port timeout */
2115 	uart_update_timeout(port, termios->c_cflag, baud);
2116 
2117 	/*
2118 	 * save/disable interrupts. The tty layer will ensure that the
2119 	 * transmitter is empty if requested by the caller, so there's
2120 	 * no need to wait for it here.
2121 	 */
2122 	imr = atmel_uart_readl(port, ATMEL_US_IMR);
2123 	atmel_uart_writel(port, ATMEL_US_IDR, -1);
2124 
2125 	/* disable receiver and transmitter */
2126 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2127 
2128 	/* mode */
2129 	if (port->rs485.flags & SER_RS485_ENABLED) {
2130 		atmel_uart_writel(port, ATMEL_US_TTGR,
2131 				  port->rs485.delay_rts_after_send);
2132 		mode |= ATMEL_US_USMODE_RS485;
2133 	} else if (termios->c_cflag & CRTSCTS) {
2134 		/* RS232 with hardware handshake (RTS/CTS) */
2135 		if (atmel_use_fifo(port) &&
2136 		    !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2137 			/*
2138 			 * with ATMEL_US_USMODE_HWHS set, the controller will
2139 			 * be able to drive the RTS pin high/low when the RX
2140 			 * FIFO is above RXFTHRES/below RXFTHRES2.
2141 			 * It will also disable the transmitter when the CTS
2142 			 * pin is high.
2143 			 * This mode is not activated if CTS pin is a GPIO
2144 			 * because in this case, the transmitter is always
2145 			 * disabled (there must be an internal pull-up
2146 			 * responsible for this behaviour).
2147 			 * If the RTS pin is a GPIO, the controller won't be
2148 			 * able to drive it according to the FIFO thresholds,
2149 			 * but it will be handled by the driver.
2150 			 */
2151 			mode |= ATMEL_US_USMODE_HWHS;
2152 		} else {
2153 			/*
2154 			 * For platforms without FIFO, the flow control is
2155 			 * handled by the driver.
2156 			 */
2157 			mode |= ATMEL_US_USMODE_NORMAL;
2158 		}
2159 	} else {
2160 		/* RS232 without hadware handshake */
2161 		mode |= ATMEL_US_USMODE_NORMAL;
2162 	}
2163 
2164 	/* set the mode, clock divisor, parity, stop bits and data size */
2165 	atmel_uart_writel(port, ATMEL_US_MR, mode);
2166 
2167 	/*
2168 	 * when switching the mode, set the RTS line state according to the
2169 	 * new mode, otherwise keep the former state
2170 	 */
2171 	if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2172 		unsigned int rts_state;
2173 
2174 		if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2175 			/* let the hardware control the RTS line */
2176 			rts_state = ATMEL_US_RTSDIS;
2177 		} else {
2178 			/* force RTS line to low level */
2179 			rts_state = ATMEL_US_RTSEN;
2180 		}
2181 
2182 		atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2183 	}
2184 
2185 	/*
2186 	 * Set the baud rate:
2187 	 * Fractional baudrate allows to setup output frequency more
2188 	 * accurately. This feature is enabled only when using normal mode.
2189 	 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2190 	 * Currently, OVER is always set to 0 so we get
2191 	 * baudrate = selected clock / (16 * (CD + FP / 8))
2192 	 * then
2193 	 * 8 CD + FP = selected clock / (2 * baudrate)
2194 	 */
2195 	if (atmel_port->has_frac_baudrate &&
2196 	    (mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_NORMAL) {
2197 		div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2198 		cd = div >> 3;
2199 		fp = div & ATMEL_US_FP_MASK;
2200 	} else {
2201 		cd = uart_get_divisor(port, baud);
2202 	}
2203 
2204 	if (cd > 65535) {	/* BRGR is 16-bit, so switch to slower clock */
2205 		cd /= 8;
2206 		mode |= ATMEL_US_USCLKS_MCK_DIV8;
2207 	}
2208 	quot = cd | fp << ATMEL_US_FP_OFFSET;
2209 
2210 	atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2211 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2212 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2213 
2214 	/* restore interrupts */
2215 	atmel_uart_writel(port, ATMEL_US_IER, imr);
2216 
2217 	/* CTS flow-control and modem-status interrupts */
2218 	if (UART_ENABLE_MS(port, termios->c_cflag))
2219 		atmel_enable_ms(port);
2220 	else
2221 		atmel_disable_ms(port);
2222 
2223 	spin_unlock_irqrestore(&port->lock, flags);
2224 }
2225 
2226 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2227 {
2228 	if (termios->c_line == N_PPS) {
2229 		port->flags |= UPF_HARDPPS_CD;
2230 		spin_lock_irq(&port->lock);
2231 		atmel_enable_ms(port);
2232 		spin_unlock_irq(&port->lock);
2233 	} else {
2234 		port->flags &= ~UPF_HARDPPS_CD;
2235 		if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2236 			spin_lock_irq(&port->lock);
2237 			atmel_disable_ms(port);
2238 			spin_unlock_irq(&port->lock);
2239 		}
2240 	}
2241 }
2242 
2243 /*
2244  * Return string describing the specified port
2245  */
2246 static const char *atmel_type(struct uart_port *port)
2247 {
2248 	return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2249 }
2250 
2251 /*
2252  * Release the memory region(s) being used by 'port'.
2253  */
2254 static void atmel_release_port(struct uart_port *port)
2255 {
2256 	struct platform_device *pdev = to_platform_device(port->dev);
2257 	int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2258 
2259 	release_mem_region(port->mapbase, size);
2260 
2261 	if (port->flags & UPF_IOREMAP) {
2262 		iounmap(port->membase);
2263 		port->membase = NULL;
2264 	}
2265 }
2266 
2267 /*
2268  * Request the memory region(s) being used by 'port'.
2269  */
2270 static int atmel_request_port(struct uart_port *port)
2271 {
2272 	struct platform_device *pdev = to_platform_device(port->dev);
2273 	int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2274 
2275 	if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2276 		return -EBUSY;
2277 
2278 	if (port->flags & UPF_IOREMAP) {
2279 		port->membase = ioremap(port->mapbase, size);
2280 		if (port->membase == NULL) {
2281 			release_mem_region(port->mapbase, size);
2282 			return -ENOMEM;
2283 		}
2284 	}
2285 
2286 	return 0;
2287 }
2288 
2289 /*
2290  * Configure/autoconfigure the port.
2291  */
2292 static void atmel_config_port(struct uart_port *port, int flags)
2293 {
2294 	if (flags & UART_CONFIG_TYPE) {
2295 		port->type = PORT_ATMEL;
2296 		atmel_request_port(port);
2297 	}
2298 }
2299 
2300 /*
2301  * Verify the new serial_struct (for TIOCSSERIAL).
2302  */
2303 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2304 {
2305 	int ret = 0;
2306 	if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2307 		ret = -EINVAL;
2308 	if (port->irq != ser->irq)
2309 		ret = -EINVAL;
2310 	if (ser->io_type != SERIAL_IO_MEM)
2311 		ret = -EINVAL;
2312 	if (port->uartclk / 16 != ser->baud_base)
2313 		ret = -EINVAL;
2314 	if (port->mapbase != (unsigned long)ser->iomem_base)
2315 		ret = -EINVAL;
2316 	if (port->iobase != ser->port)
2317 		ret = -EINVAL;
2318 	if (ser->hub6 != 0)
2319 		ret = -EINVAL;
2320 	return ret;
2321 }
2322 
2323 #ifdef CONFIG_CONSOLE_POLL
2324 static int atmel_poll_get_char(struct uart_port *port)
2325 {
2326 	while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2327 		cpu_relax();
2328 
2329 	return atmel_uart_read_char(port);
2330 }
2331 
2332 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2333 {
2334 	while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2335 		cpu_relax();
2336 
2337 	atmel_uart_write_char(port, ch);
2338 }
2339 #endif
2340 
2341 static const struct uart_ops atmel_pops = {
2342 	.tx_empty	= atmel_tx_empty,
2343 	.set_mctrl	= atmel_set_mctrl,
2344 	.get_mctrl	= atmel_get_mctrl,
2345 	.stop_tx	= atmel_stop_tx,
2346 	.start_tx	= atmel_start_tx,
2347 	.stop_rx	= atmel_stop_rx,
2348 	.enable_ms	= atmel_enable_ms,
2349 	.break_ctl	= atmel_break_ctl,
2350 	.startup	= atmel_startup,
2351 	.shutdown	= atmel_shutdown,
2352 	.flush_buffer	= atmel_flush_buffer,
2353 	.set_termios	= atmel_set_termios,
2354 	.set_ldisc	= atmel_set_ldisc,
2355 	.type		= atmel_type,
2356 	.release_port	= atmel_release_port,
2357 	.request_port	= atmel_request_port,
2358 	.config_port	= atmel_config_port,
2359 	.verify_port	= atmel_verify_port,
2360 	.pm		= atmel_serial_pm,
2361 #ifdef CONFIG_CONSOLE_POLL
2362 	.poll_get_char	= atmel_poll_get_char,
2363 	.poll_put_char	= atmel_poll_put_char,
2364 #endif
2365 };
2366 
2367 /*
2368  * Configure the port from the platform device resource info.
2369  */
2370 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2371 				      struct platform_device *pdev)
2372 {
2373 	int ret;
2374 	struct uart_port *port = &atmel_port->uart;
2375 	struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2376 
2377 	atmel_init_property(atmel_port, pdev);
2378 	atmel_set_ops(port);
2379 
2380 	atmel_init_rs485(port, pdev);
2381 
2382 	port->iotype		= UPIO_MEM;
2383 	port->flags		= UPF_BOOT_AUTOCONF;
2384 	port->ops		= &atmel_pops;
2385 	port->fifosize		= 1;
2386 	port->dev		= &pdev->dev;
2387 	port->mapbase	= pdev->resource[0].start;
2388 	port->irq	= pdev->resource[1].start;
2389 	port->rs485_config	= atmel_config_rs485;
2390 
2391 	memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2392 
2393 	if (pdata && pdata->regs) {
2394 		/* Already mapped by setup code */
2395 		port->membase = pdata->regs;
2396 	} else {
2397 		port->flags	|= UPF_IOREMAP;
2398 		port->membase	= NULL;
2399 	}
2400 
2401 	/* for console, the clock could already be configured */
2402 	if (!atmel_port->clk) {
2403 		atmel_port->clk = clk_get(&pdev->dev, "usart");
2404 		if (IS_ERR(atmel_port->clk)) {
2405 			ret = PTR_ERR(atmel_port->clk);
2406 			atmel_port->clk = NULL;
2407 			return ret;
2408 		}
2409 		ret = clk_prepare_enable(atmel_port->clk);
2410 		if (ret) {
2411 			clk_put(atmel_port->clk);
2412 			atmel_port->clk = NULL;
2413 			return ret;
2414 		}
2415 		port->uartclk = clk_get_rate(atmel_port->clk);
2416 		clk_disable_unprepare(atmel_port->clk);
2417 		/* only enable clock when USART is in use */
2418 	}
2419 
2420 	/* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2421 	if (port->rs485.flags & SER_RS485_ENABLED)
2422 		atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2423 	else if (atmel_use_pdc_tx(port)) {
2424 		port->fifosize = PDC_BUFFER_SIZE;
2425 		atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2426 	} else {
2427 		atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2428 	}
2429 
2430 	return 0;
2431 }
2432 
2433 struct platform_device *atmel_default_console_device;	/* the serial console device */
2434 
2435 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2436 static void atmel_console_putchar(struct uart_port *port, int ch)
2437 {
2438 	while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2439 		cpu_relax();
2440 	atmel_uart_write_char(port, ch);
2441 }
2442 
2443 /*
2444  * Interrupts are disabled on entering
2445  */
2446 static void atmel_console_write(struct console *co, const char *s, u_int count)
2447 {
2448 	struct uart_port *port = &atmel_ports[co->index].uart;
2449 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2450 	unsigned int status, imr;
2451 	unsigned int pdc_tx;
2452 
2453 	/*
2454 	 * First, save IMR and then disable interrupts
2455 	 */
2456 	imr = atmel_uart_readl(port, ATMEL_US_IMR);
2457 	atmel_uart_writel(port, ATMEL_US_IDR,
2458 			  ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2459 
2460 	/* Store PDC transmit status and disable it */
2461 	pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2462 	atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2463 
2464 	uart_console_write(port, s, count, atmel_console_putchar);
2465 
2466 	/*
2467 	 * Finally, wait for transmitter to become empty
2468 	 * and restore IMR
2469 	 */
2470 	do {
2471 		status = atmel_uart_readl(port, ATMEL_US_CSR);
2472 	} while (!(status & ATMEL_US_TXRDY));
2473 
2474 	/* Restore PDC transmit status */
2475 	if (pdc_tx)
2476 		atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2477 
2478 	/* set interrupts back the way they were */
2479 	atmel_uart_writel(port, ATMEL_US_IER, imr);
2480 }
2481 
2482 /*
2483  * If the port was already initialised (eg, by a boot loader),
2484  * try to determine the current setup.
2485  */
2486 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2487 					     int *parity, int *bits)
2488 {
2489 	unsigned int mr, quot;
2490 
2491 	/*
2492 	 * If the baud rate generator isn't running, the port wasn't
2493 	 * initialized by the boot loader.
2494 	 */
2495 	quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2496 	if (!quot)
2497 		return;
2498 
2499 	mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2500 	if (mr == ATMEL_US_CHRL_8)
2501 		*bits = 8;
2502 	else
2503 		*bits = 7;
2504 
2505 	mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2506 	if (mr == ATMEL_US_PAR_EVEN)
2507 		*parity = 'e';
2508 	else if (mr == ATMEL_US_PAR_ODD)
2509 		*parity = 'o';
2510 
2511 	/*
2512 	 * The serial core only rounds down when matching this to a
2513 	 * supported baud rate. Make sure we don't end up slightly
2514 	 * lower than one of those, as it would make us fall through
2515 	 * to a much lower baud rate than we really want.
2516 	 */
2517 	*baud = port->uartclk / (16 * (quot - 1));
2518 }
2519 
2520 static int __init atmel_console_setup(struct console *co, char *options)
2521 {
2522 	int ret;
2523 	struct uart_port *port = &atmel_ports[co->index].uart;
2524 	int baud = 115200;
2525 	int bits = 8;
2526 	int parity = 'n';
2527 	int flow = 'n';
2528 
2529 	if (port->membase == NULL) {
2530 		/* Port not initialized yet - delay setup */
2531 		return -ENODEV;
2532 	}
2533 
2534 	ret = clk_prepare_enable(atmel_ports[co->index].clk);
2535 	if (ret)
2536 		return ret;
2537 
2538 	atmel_uart_writel(port, ATMEL_US_IDR, -1);
2539 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2540 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2541 
2542 	if (options)
2543 		uart_parse_options(options, &baud, &parity, &bits, &flow);
2544 	else
2545 		atmel_console_get_options(port, &baud, &parity, &bits);
2546 
2547 	return uart_set_options(port, co, baud, parity, bits, flow);
2548 }
2549 
2550 static struct uart_driver atmel_uart;
2551 
2552 static struct console atmel_console = {
2553 	.name		= ATMEL_DEVICENAME,
2554 	.write		= atmel_console_write,
2555 	.device		= uart_console_device,
2556 	.setup		= atmel_console_setup,
2557 	.flags		= CON_PRINTBUFFER,
2558 	.index		= -1,
2559 	.data		= &atmel_uart,
2560 };
2561 
2562 #define ATMEL_CONSOLE_DEVICE	(&atmel_console)
2563 
2564 /*
2565  * Early console initialization (before VM subsystem initialized).
2566  */
2567 static int __init atmel_console_init(void)
2568 {
2569 	int ret;
2570 	if (atmel_default_console_device) {
2571 		struct atmel_uart_data *pdata =
2572 			dev_get_platdata(&atmel_default_console_device->dev);
2573 		int id = pdata->num;
2574 		struct atmel_uart_port *atmel_port = &atmel_ports[id];
2575 
2576 		atmel_port->backup_imr = 0;
2577 		atmel_port->uart.line = id;
2578 
2579 		add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2580 		ret = atmel_init_port(atmel_port, atmel_default_console_device);
2581 		if (ret)
2582 			return ret;
2583 		register_console(&atmel_console);
2584 	}
2585 
2586 	return 0;
2587 }
2588 
2589 console_initcall(atmel_console_init);
2590 
2591 /*
2592  * Late console initialization.
2593  */
2594 static int __init atmel_late_console_init(void)
2595 {
2596 	if (atmel_default_console_device
2597 	    && !(atmel_console.flags & CON_ENABLED))
2598 		register_console(&atmel_console);
2599 
2600 	return 0;
2601 }
2602 
2603 core_initcall(atmel_late_console_init);
2604 
2605 static inline bool atmel_is_console_port(struct uart_port *port)
2606 {
2607 	return port->cons && port->cons->index == port->line;
2608 }
2609 
2610 #else
2611 #define ATMEL_CONSOLE_DEVICE	NULL
2612 
2613 static inline bool atmel_is_console_port(struct uart_port *port)
2614 {
2615 	return false;
2616 }
2617 #endif
2618 
2619 static struct uart_driver atmel_uart = {
2620 	.owner		= THIS_MODULE,
2621 	.driver_name	= "atmel_serial",
2622 	.dev_name	= ATMEL_DEVICENAME,
2623 	.major		= SERIAL_ATMEL_MAJOR,
2624 	.minor		= MINOR_START,
2625 	.nr		= ATMEL_MAX_UART,
2626 	.cons		= ATMEL_CONSOLE_DEVICE,
2627 };
2628 
2629 #ifdef CONFIG_PM
2630 static bool atmel_serial_clk_will_stop(void)
2631 {
2632 #ifdef CONFIG_ARCH_AT91
2633 	return at91_suspend_entering_slow_clock();
2634 #else
2635 	return false;
2636 #endif
2637 }
2638 
2639 static int atmel_serial_suspend(struct platform_device *pdev,
2640 				pm_message_t state)
2641 {
2642 	struct uart_port *port = platform_get_drvdata(pdev);
2643 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2644 
2645 	if (atmel_is_console_port(port) && console_suspend_enabled) {
2646 		/* Drain the TX shifter */
2647 		while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2648 			 ATMEL_US_TXEMPTY))
2649 			cpu_relax();
2650 	}
2651 
2652 	/* we can not wake up if we're running on slow clock */
2653 	atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2654 	if (atmel_serial_clk_will_stop()) {
2655 		unsigned long flags;
2656 
2657 		spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2658 		atmel_port->suspended = true;
2659 		spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2660 		device_set_wakeup_enable(&pdev->dev, 0);
2661 	}
2662 
2663 	uart_suspend_port(&atmel_uart, port);
2664 
2665 	return 0;
2666 }
2667 
2668 static int atmel_serial_resume(struct platform_device *pdev)
2669 {
2670 	struct uart_port *port = platform_get_drvdata(pdev);
2671 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2672 	unsigned long flags;
2673 
2674 	spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2675 	if (atmel_port->pending) {
2676 		atmel_handle_receive(port, atmel_port->pending);
2677 		atmel_handle_status(port, atmel_port->pending,
2678 				    atmel_port->pending_status);
2679 		atmel_handle_transmit(port, atmel_port->pending);
2680 		atmel_port->pending = 0;
2681 	}
2682 	atmel_port->suspended = false;
2683 	spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2684 
2685 	uart_resume_port(&atmel_uart, port);
2686 	device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2687 
2688 	return 0;
2689 }
2690 #else
2691 #define atmel_serial_suspend NULL
2692 #define atmel_serial_resume NULL
2693 #endif
2694 
2695 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2696 				     struct platform_device *pdev)
2697 {
2698 	atmel_port->fifo_size = 0;
2699 	atmel_port->rts_low = 0;
2700 	atmel_port->rts_high = 0;
2701 
2702 	if (of_property_read_u32(pdev->dev.of_node,
2703 				 "atmel,fifo-size",
2704 				 &atmel_port->fifo_size))
2705 		return;
2706 
2707 	if (!atmel_port->fifo_size)
2708 		return;
2709 
2710 	if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2711 		atmel_port->fifo_size = 0;
2712 		dev_err(&pdev->dev, "Invalid FIFO size\n");
2713 		return;
2714 	}
2715 
2716 	/*
2717 	 * 0 <= rts_low <= rts_high <= fifo_size
2718 	 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2719 	 * to flush their internal TX FIFO, commonly up to 16 data, before
2720 	 * actually stopping to send new data. So we try to set the RTS High
2721 	 * Threshold to a reasonably high value respecting this 16 data
2722 	 * empirical rule when possible.
2723 	 */
2724 	atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2725 			       atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2726 	atmel_port->rts_low  = max_t(int, atmel_port->fifo_size >> 2,
2727 			       atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2728 
2729 	dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2730 		 atmel_port->fifo_size);
2731 	dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2732 		atmel_port->rts_high);
2733 	dev_dbg(&pdev->dev, "RTS Low Threshold  : %2u data\n",
2734 		atmel_port->rts_low);
2735 }
2736 
2737 static int atmel_serial_probe(struct platform_device *pdev)
2738 {
2739 	struct atmel_uart_port *atmel_port;
2740 	struct device_node *np = pdev->dev.of_node;
2741 	struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2742 	void *data;
2743 	int ret = -ENODEV;
2744 	bool rs485_enabled;
2745 
2746 	BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2747 
2748 	if (np)
2749 		ret = of_alias_get_id(np, "serial");
2750 	else
2751 		if (pdata)
2752 			ret = pdata->num;
2753 
2754 	if (ret < 0)
2755 		/* port id not found in platform data nor device-tree aliases:
2756 		 * auto-enumerate it */
2757 		ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2758 
2759 	if (ret >= ATMEL_MAX_UART) {
2760 		ret = -ENODEV;
2761 		goto err;
2762 	}
2763 
2764 	if (test_and_set_bit(ret, atmel_ports_in_use)) {
2765 		/* port already in use */
2766 		ret = -EBUSY;
2767 		goto err;
2768 	}
2769 
2770 	atmel_port = &atmel_ports[ret];
2771 	atmel_port->backup_imr = 0;
2772 	atmel_port->uart.line = ret;
2773 	atmel_serial_probe_fifos(atmel_port, pdev);
2774 
2775 	atomic_set(&atmel_port->tasklet_shutdown, 0);
2776 	spin_lock_init(&atmel_port->lock_suspended);
2777 
2778 	ret = atmel_init_port(atmel_port, pdev);
2779 	if (ret)
2780 		goto err_clear_bit;
2781 
2782 	atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2783 	if (IS_ERR(atmel_port->gpios)) {
2784 		ret = PTR_ERR(atmel_port->gpios);
2785 		goto err_clear_bit;
2786 	}
2787 
2788 	if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2789 		ret = -ENOMEM;
2790 		data = kmalloc(sizeof(struct atmel_uart_char)
2791 				* ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2792 		if (!data)
2793 			goto err_alloc_ring;
2794 		atmel_port->rx_ring.buf = data;
2795 	}
2796 
2797 	rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2798 
2799 	ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2800 	if (ret)
2801 		goto err_add_port;
2802 
2803 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2804 	if (atmel_is_console_port(&atmel_port->uart)
2805 			&& ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2806 		/*
2807 		 * The serial core enabled the clock for us, so undo
2808 		 * the clk_prepare_enable() in atmel_console_setup()
2809 		 */
2810 		clk_disable_unprepare(atmel_port->clk);
2811 	}
2812 #endif
2813 
2814 	device_init_wakeup(&pdev->dev, 1);
2815 	platform_set_drvdata(pdev, atmel_port);
2816 
2817 	/*
2818 	 * The peripheral clock has been disabled by atmel_init_port():
2819 	 * enable it before accessing I/O registers
2820 	 */
2821 	clk_prepare_enable(atmel_port->clk);
2822 
2823 	if (rs485_enabled) {
2824 		atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2825 				  ATMEL_US_USMODE_NORMAL);
2826 		atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2827 				  ATMEL_US_RTSEN);
2828 	}
2829 
2830 	/*
2831 	 * Get port name of usart or uart
2832 	 */
2833 	atmel_get_ip_name(&atmel_port->uart);
2834 
2835 	/*
2836 	 * The peripheral clock can now safely be disabled till the port
2837 	 * is used
2838 	 */
2839 	clk_disable_unprepare(atmel_port->clk);
2840 
2841 	return 0;
2842 
2843 err_add_port:
2844 	kfree(atmel_port->rx_ring.buf);
2845 	atmel_port->rx_ring.buf = NULL;
2846 err_alloc_ring:
2847 	if (!atmel_is_console_port(&atmel_port->uart)) {
2848 		clk_put(atmel_port->clk);
2849 		atmel_port->clk = NULL;
2850 	}
2851 err_clear_bit:
2852 	clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2853 err:
2854 	return ret;
2855 }
2856 
2857 /*
2858  * Even if the driver is not modular, it makes sense to be able to
2859  * unbind a device: there can be many bound devices, and there are
2860  * situations where dynamic binding and unbinding can be useful.
2861  *
2862  * For example, a connected device can require a specific firmware update
2863  * protocol that needs bitbanging on IO lines, but use the regular serial
2864  * port in the normal case.
2865  */
2866 static int atmel_serial_remove(struct platform_device *pdev)
2867 {
2868 	struct uart_port *port = platform_get_drvdata(pdev);
2869 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2870 	int ret = 0;
2871 
2872 	tasklet_kill(&atmel_port->tasklet_rx);
2873 	tasklet_kill(&atmel_port->tasklet_tx);
2874 
2875 	device_init_wakeup(&pdev->dev, 0);
2876 
2877 	ret = uart_remove_one_port(&atmel_uart, port);
2878 
2879 	kfree(atmel_port->rx_ring.buf);
2880 
2881 	/* "port" is allocated statically, so we shouldn't free it */
2882 
2883 	clear_bit(port->line, atmel_ports_in_use);
2884 
2885 	clk_put(atmel_port->clk);
2886 	atmel_port->clk = NULL;
2887 
2888 	return ret;
2889 }
2890 
2891 static struct platform_driver atmel_serial_driver = {
2892 	.probe		= atmel_serial_probe,
2893 	.remove		= atmel_serial_remove,
2894 	.suspend	= atmel_serial_suspend,
2895 	.resume		= atmel_serial_resume,
2896 	.driver		= {
2897 		.name			= "atmel_usart",
2898 		.of_match_table		= of_match_ptr(atmel_serial_dt_ids),
2899 	},
2900 };
2901 
2902 static int __init atmel_serial_init(void)
2903 {
2904 	int ret;
2905 
2906 	ret = uart_register_driver(&atmel_uart);
2907 	if (ret)
2908 		return ret;
2909 
2910 	ret = platform_driver_register(&atmel_serial_driver);
2911 	if (ret)
2912 		uart_unregister_driver(&atmel_uart);
2913 
2914 	return ret;
2915 }
2916 device_initcall(atmel_serial_init);
2917