1 /* 2 * Driver for Atmel AT91 / AT32 Serial ports 3 * Copyright (C) 2003 Rick Bronson 4 * 5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. 6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 7 * 8 * DMA support added by Chip Coldwell. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 #include <linux/tty.h> 26 #include <linux/ioport.h> 27 #include <linux/slab.h> 28 #include <linux/init.h> 29 #include <linux/serial.h> 30 #include <linux/clk.h> 31 #include <linux/console.h> 32 #include <linux/sysrq.h> 33 #include <linux/tty_flip.h> 34 #include <linux/platform_device.h> 35 #include <linux/of.h> 36 #include <linux/of_device.h> 37 #include <linux/of_gpio.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/dmaengine.h> 40 #include <linux/atmel_pdc.h> 41 #include <linux/atmel_serial.h> 42 #include <linux/uaccess.h> 43 #include <linux/platform_data/atmel.h> 44 #include <linux/timer.h> 45 #include <linux/gpio.h> 46 #include <linux/gpio/consumer.h> 47 #include <linux/err.h> 48 #include <linux/irq.h> 49 #include <linux/suspend.h> 50 51 #include <asm/io.h> 52 #include <asm/ioctls.h> 53 54 #define PDC_BUFFER_SIZE 512 55 /* Revisit: We should calculate this based on the actual port settings */ 56 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ 57 58 /* The minium number of data FIFOs should be able to contain */ 59 #define ATMEL_MIN_FIFO_SIZE 8 60 /* 61 * These two offsets are substracted from the RX FIFO size to define the RTS 62 * high and low thresholds 63 */ 64 #define ATMEL_RTS_HIGH_OFFSET 16 65 #define ATMEL_RTS_LOW_OFFSET 20 66 67 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 68 #define SUPPORT_SYSRQ 69 #endif 70 71 #include <linux/serial_core.h> 72 73 #include "serial_mctrl_gpio.h" 74 75 static void atmel_start_rx(struct uart_port *port); 76 static void atmel_stop_rx(struct uart_port *port); 77 78 #ifdef CONFIG_SERIAL_ATMEL_TTYAT 79 80 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we 81 * should coexist with the 8250 driver, such as if we have an external 16C550 82 * UART. */ 83 #define SERIAL_ATMEL_MAJOR 204 84 #define MINOR_START 154 85 #define ATMEL_DEVICENAME "ttyAT" 86 87 #else 88 89 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port 90 * name, but it is legally reserved for the 8250 driver. */ 91 #define SERIAL_ATMEL_MAJOR TTY_MAJOR 92 #define MINOR_START 64 93 #define ATMEL_DEVICENAME "ttyS" 94 95 #endif 96 97 #define ATMEL_ISR_PASS_LIMIT 256 98 99 struct atmel_dma_buffer { 100 unsigned char *buf; 101 dma_addr_t dma_addr; 102 unsigned int dma_size; 103 unsigned int ofs; 104 }; 105 106 struct atmel_uart_char { 107 u16 status; 108 u16 ch; 109 }; 110 111 #define ATMEL_SERIAL_RINGSIZE 1024 112 113 /* 114 * at91: 6 USARTs and one DBGU port (SAM9260) 115 * avr32: 4 116 */ 117 #define ATMEL_MAX_UART 7 118 119 /* 120 * We wrap our port structure around the generic uart_port. 121 */ 122 struct atmel_uart_port { 123 struct uart_port uart; /* uart */ 124 struct clk *clk; /* uart clock */ 125 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ 126 u32 backup_imr; /* IMR saved during suspend */ 127 int break_active; /* break being received */ 128 129 bool use_dma_rx; /* enable DMA receiver */ 130 bool use_pdc_rx; /* enable PDC receiver */ 131 short pdc_rx_idx; /* current PDC RX buffer */ 132 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ 133 134 bool use_dma_tx; /* enable DMA transmitter */ 135 bool use_pdc_tx; /* enable PDC transmitter */ 136 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ 137 138 spinlock_t lock_tx; /* port lock */ 139 spinlock_t lock_rx; /* port lock */ 140 struct dma_chan *chan_tx; 141 struct dma_chan *chan_rx; 142 struct dma_async_tx_descriptor *desc_tx; 143 struct dma_async_tx_descriptor *desc_rx; 144 dma_cookie_t cookie_tx; 145 dma_cookie_t cookie_rx; 146 struct scatterlist sg_tx; 147 struct scatterlist sg_rx; 148 struct tasklet_struct tasklet; 149 unsigned int irq_status; 150 unsigned int irq_status_prev; 151 unsigned int status_change; 152 unsigned int tx_len; 153 154 struct circ_buf rx_ring; 155 156 struct mctrl_gpios *gpios; 157 unsigned int tx_done_mask; 158 u32 fifo_size; 159 u32 rts_high; 160 u32 rts_low; 161 bool ms_irq_enabled; 162 u32 rtor; /* address of receiver timeout register if it exists */ 163 bool has_hw_timer; 164 struct timer_list uart_timer; 165 166 bool suspended; 167 unsigned int pending; 168 unsigned int pending_status; 169 spinlock_t lock_suspended; 170 171 int (*prepare_rx)(struct uart_port *port); 172 int (*prepare_tx)(struct uart_port *port); 173 void (*schedule_rx)(struct uart_port *port); 174 void (*schedule_tx)(struct uart_port *port); 175 void (*release_rx)(struct uart_port *port); 176 void (*release_tx)(struct uart_port *port); 177 }; 178 179 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; 180 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); 181 182 #ifdef SUPPORT_SYSRQ 183 static struct console atmel_console; 184 #endif 185 186 #if defined(CONFIG_OF) 187 static const struct of_device_id atmel_serial_dt_ids[] = { 188 { .compatible = "atmel,at91rm9200-usart" }, 189 { .compatible = "atmel,at91sam9260-usart" }, 190 { /* sentinel */ } 191 }; 192 #endif 193 194 static inline struct atmel_uart_port * 195 to_atmel_uart_port(struct uart_port *uart) 196 { 197 return container_of(uart, struct atmel_uart_port, uart); 198 } 199 200 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg) 201 { 202 return __raw_readl(port->membase + reg); 203 } 204 205 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value) 206 { 207 __raw_writel(value, port->membase + reg); 208 } 209 210 #ifdef CONFIG_AVR32 211 212 /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */ 213 static inline u8 atmel_uart_read_char(struct uart_port *port) 214 { 215 return __raw_readl(port->membase + ATMEL_US_RHR); 216 } 217 218 static inline void atmel_uart_write_char(struct uart_port *port, u8 value) 219 { 220 __raw_writel(value, port->membase + ATMEL_US_THR); 221 } 222 223 #else 224 225 static inline u8 atmel_uart_read_char(struct uart_port *port) 226 { 227 return __raw_readb(port->membase + ATMEL_US_RHR); 228 } 229 230 static inline void atmel_uart_write_char(struct uart_port *port, u8 value) 231 { 232 __raw_writeb(value, port->membase + ATMEL_US_THR); 233 } 234 235 #endif 236 237 #ifdef CONFIG_SERIAL_ATMEL_PDC 238 static bool atmel_use_pdc_rx(struct uart_port *port) 239 { 240 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 241 242 return atmel_port->use_pdc_rx; 243 } 244 245 static bool atmel_use_pdc_tx(struct uart_port *port) 246 { 247 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 248 249 return atmel_port->use_pdc_tx; 250 } 251 #else 252 static bool atmel_use_pdc_rx(struct uart_port *port) 253 { 254 return false; 255 } 256 257 static bool atmel_use_pdc_tx(struct uart_port *port) 258 { 259 return false; 260 } 261 #endif 262 263 static bool atmel_use_dma_tx(struct uart_port *port) 264 { 265 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 266 267 return atmel_port->use_dma_tx; 268 } 269 270 static bool atmel_use_dma_rx(struct uart_port *port) 271 { 272 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 273 274 return atmel_port->use_dma_rx; 275 } 276 277 static bool atmel_use_fifo(struct uart_port *port) 278 { 279 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 280 281 return atmel_port->fifo_size; 282 } 283 284 static unsigned int atmel_get_lines_status(struct uart_port *port) 285 { 286 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 287 unsigned int status, ret = 0; 288 289 status = atmel_uart_readl(port, ATMEL_US_CSR); 290 291 mctrl_gpio_get(atmel_port->gpios, &ret); 292 293 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 294 UART_GPIO_CTS))) { 295 if (ret & TIOCM_CTS) 296 status &= ~ATMEL_US_CTS; 297 else 298 status |= ATMEL_US_CTS; 299 } 300 301 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 302 UART_GPIO_DSR))) { 303 if (ret & TIOCM_DSR) 304 status &= ~ATMEL_US_DSR; 305 else 306 status |= ATMEL_US_DSR; 307 } 308 309 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 310 UART_GPIO_RI))) { 311 if (ret & TIOCM_RI) 312 status &= ~ATMEL_US_RI; 313 else 314 status |= ATMEL_US_RI; 315 } 316 317 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 318 UART_GPIO_DCD))) { 319 if (ret & TIOCM_CD) 320 status &= ~ATMEL_US_DCD; 321 else 322 status |= ATMEL_US_DCD; 323 } 324 325 return status; 326 } 327 328 /* Enable or disable the rs485 support */ 329 static int atmel_config_rs485(struct uart_port *port, 330 struct serial_rs485 *rs485conf) 331 { 332 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 333 unsigned int mode; 334 335 /* Disable interrupts */ 336 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); 337 338 mode = atmel_uart_readl(port, ATMEL_US_MR); 339 340 /* Resetting serial mode to RS232 (0x0) */ 341 mode &= ~ATMEL_US_USMODE; 342 343 port->rs485 = *rs485conf; 344 345 if (rs485conf->flags & SER_RS485_ENABLED) { 346 dev_dbg(port->dev, "Setting UART to RS485\n"); 347 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 348 atmel_uart_writel(port, ATMEL_US_TTGR, 349 rs485conf->delay_rts_after_send); 350 mode |= ATMEL_US_USMODE_RS485; 351 } else { 352 dev_dbg(port->dev, "Setting UART to RS232\n"); 353 if (atmel_use_pdc_tx(port)) 354 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 355 ATMEL_US_TXBUFE; 356 else 357 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 358 } 359 atmel_uart_writel(port, ATMEL_US_MR, mode); 360 361 /* Enable interrupts */ 362 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 363 364 return 0; 365 } 366 367 /* 368 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. 369 */ 370 static u_int atmel_tx_empty(struct uart_port *port) 371 { 372 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ? 373 TIOCSER_TEMT : 374 0; 375 } 376 377 /* 378 * Set state of the modem control output lines 379 */ 380 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) 381 { 382 unsigned int control = 0; 383 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR); 384 unsigned int rts_paused, rts_ready; 385 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 386 387 /* override mode to RS485 if needed, otherwise keep the current mode */ 388 if (port->rs485.flags & SER_RS485_ENABLED) { 389 atmel_uart_writel(port, ATMEL_US_TTGR, 390 port->rs485.delay_rts_after_send); 391 mode &= ~ATMEL_US_USMODE; 392 mode |= ATMEL_US_USMODE_RS485; 393 } 394 395 /* set the RTS line state according to the mode */ 396 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 397 /* force RTS line to high level */ 398 rts_paused = ATMEL_US_RTSEN; 399 400 /* give the control of the RTS line back to the hardware */ 401 rts_ready = ATMEL_US_RTSDIS; 402 } else { 403 /* force RTS line to high level */ 404 rts_paused = ATMEL_US_RTSDIS; 405 406 /* force RTS line to low level */ 407 rts_ready = ATMEL_US_RTSEN; 408 } 409 410 if (mctrl & TIOCM_RTS) 411 control |= rts_ready; 412 else 413 control |= rts_paused; 414 415 if (mctrl & TIOCM_DTR) 416 control |= ATMEL_US_DTREN; 417 else 418 control |= ATMEL_US_DTRDIS; 419 420 atmel_uart_writel(port, ATMEL_US_CR, control); 421 422 mctrl_gpio_set(atmel_port->gpios, mctrl); 423 424 /* Local loopback mode? */ 425 mode &= ~ATMEL_US_CHMODE; 426 if (mctrl & TIOCM_LOOP) 427 mode |= ATMEL_US_CHMODE_LOC_LOOP; 428 else 429 mode |= ATMEL_US_CHMODE_NORMAL; 430 431 atmel_uart_writel(port, ATMEL_US_MR, mode); 432 } 433 434 /* 435 * Get state of the modem control input lines 436 */ 437 static u_int atmel_get_mctrl(struct uart_port *port) 438 { 439 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 440 unsigned int ret = 0, status; 441 442 status = atmel_uart_readl(port, ATMEL_US_CSR); 443 444 /* 445 * The control signals are active low. 446 */ 447 if (!(status & ATMEL_US_DCD)) 448 ret |= TIOCM_CD; 449 if (!(status & ATMEL_US_CTS)) 450 ret |= TIOCM_CTS; 451 if (!(status & ATMEL_US_DSR)) 452 ret |= TIOCM_DSR; 453 if (!(status & ATMEL_US_RI)) 454 ret |= TIOCM_RI; 455 456 return mctrl_gpio_get(atmel_port->gpios, &ret); 457 } 458 459 /* 460 * Stop transmitting. 461 */ 462 static void atmel_stop_tx(struct uart_port *port) 463 { 464 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 465 466 if (atmel_use_pdc_tx(port)) { 467 /* disable PDC transmit */ 468 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 469 } 470 /* Disable interrupts */ 471 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); 472 473 if ((port->rs485.flags & SER_RS485_ENABLED) && 474 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 475 atmel_start_rx(port); 476 } 477 478 /* 479 * Start transmitting. 480 */ 481 static void atmel_start_tx(struct uart_port *port) 482 { 483 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 484 485 if (atmel_use_pdc_tx(port)) { 486 if (atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN) 487 /* The transmitter is already running. Yes, we 488 really need this.*/ 489 return; 490 491 if ((port->rs485.flags & SER_RS485_ENABLED) && 492 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 493 atmel_stop_rx(port); 494 495 /* re-enable PDC transmit */ 496 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 497 } 498 /* Enable interrupts */ 499 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 500 } 501 502 /* 503 * start receiving - port is in process of being opened. 504 */ 505 static void atmel_start_rx(struct uart_port *port) 506 { 507 /* reset status and receiver */ 508 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 509 510 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN); 511 512 if (atmel_use_pdc_rx(port)) { 513 /* enable PDC controller */ 514 atmel_uart_writel(port, ATMEL_US_IER, 515 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 516 port->read_status_mask); 517 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 518 } else { 519 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY); 520 } 521 } 522 523 /* 524 * Stop receiving - port is in process of being closed. 525 */ 526 static void atmel_stop_rx(struct uart_port *port) 527 { 528 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS); 529 530 if (atmel_use_pdc_rx(port)) { 531 /* disable PDC receive */ 532 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS); 533 atmel_uart_writel(port, ATMEL_US_IDR, 534 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 535 port->read_status_mask); 536 } else { 537 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY); 538 } 539 } 540 541 /* 542 * Enable modem status interrupts 543 */ 544 static void atmel_enable_ms(struct uart_port *port) 545 { 546 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 547 uint32_t ier = 0; 548 549 /* 550 * Interrupt should not be enabled twice 551 */ 552 if (atmel_port->ms_irq_enabled) 553 return; 554 555 atmel_port->ms_irq_enabled = true; 556 557 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) 558 ier |= ATMEL_US_CTSIC; 559 560 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR)) 561 ier |= ATMEL_US_DSRIC; 562 563 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI)) 564 ier |= ATMEL_US_RIIC; 565 566 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD)) 567 ier |= ATMEL_US_DCDIC; 568 569 atmel_uart_writel(port, ATMEL_US_IER, ier); 570 571 mctrl_gpio_enable_ms(atmel_port->gpios); 572 } 573 574 /* 575 * Disable modem status interrupts 576 */ 577 static void atmel_disable_ms(struct uart_port *port) 578 { 579 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 580 uint32_t idr = 0; 581 582 /* 583 * Interrupt should not be disabled twice 584 */ 585 if (!atmel_port->ms_irq_enabled) 586 return; 587 588 atmel_port->ms_irq_enabled = false; 589 590 mctrl_gpio_disable_ms(atmel_port->gpios); 591 592 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) 593 idr |= ATMEL_US_CTSIC; 594 595 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR)) 596 idr |= ATMEL_US_DSRIC; 597 598 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI)) 599 idr |= ATMEL_US_RIIC; 600 601 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD)) 602 idr |= ATMEL_US_DCDIC; 603 604 atmel_uart_writel(port, ATMEL_US_IDR, idr); 605 } 606 607 /* 608 * Control the transmission of a break signal 609 */ 610 static void atmel_break_ctl(struct uart_port *port, int break_state) 611 { 612 if (break_state != 0) 613 /* start break */ 614 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK); 615 else 616 /* stop break */ 617 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK); 618 } 619 620 /* 621 * Stores the incoming character in the ring buffer 622 */ 623 static void 624 atmel_buffer_rx_char(struct uart_port *port, unsigned int status, 625 unsigned int ch) 626 { 627 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 628 struct circ_buf *ring = &atmel_port->rx_ring; 629 struct atmel_uart_char *c; 630 631 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) 632 /* Buffer overflow, ignore char */ 633 return; 634 635 c = &((struct atmel_uart_char *)ring->buf)[ring->head]; 636 c->status = status; 637 c->ch = ch; 638 639 /* Make sure the character is stored before we update head. */ 640 smp_wmb(); 641 642 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 643 } 644 645 /* 646 * Deal with parity, framing and overrun errors. 647 */ 648 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) 649 { 650 /* clear error */ 651 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 652 653 if (status & ATMEL_US_RXBRK) { 654 /* ignore side-effect */ 655 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 656 port->icount.brk++; 657 } 658 if (status & ATMEL_US_PARE) 659 port->icount.parity++; 660 if (status & ATMEL_US_FRAME) 661 port->icount.frame++; 662 if (status & ATMEL_US_OVRE) 663 port->icount.overrun++; 664 } 665 666 /* 667 * Characters received (called from interrupt handler) 668 */ 669 static void atmel_rx_chars(struct uart_port *port) 670 { 671 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 672 unsigned int status, ch; 673 674 status = atmel_uart_readl(port, ATMEL_US_CSR); 675 while (status & ATMEL_US_RXRDY) { 676 ch = atmel_uart_read_char(port); 677 678 /* 679 * note that the error handling code is 680 * out of the main execution path 681 */ 682 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 683 | ATMEL_US_OVRE | ATMEL_US_RXBRK) 684 || atmel_port->break_active)) { 685 686 /* clear error */ 687 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 688 689 if (status & ATMEL_US_RXBRK 690 && !atmel_port->break_active) { 691 atmel_port->break_active = 1; 692 atmel_uart_writel(port, ATMEL_US_IER, 693 ATMEL_US_RXBRK); 694 } else { 695 /* 696 * This is either the end-of-break 697 * condition or we've received at 698 * least one character without RXBRK 699 * being set. In both cases, the next 700 * RXBRK will indicate start-of-break. 701 */ 702 atmel_uart_writel(port, ATMEL_US_IDR, 703 ATMEL_US_RXBRK); 704 status &= ~ATMEL_US_RXBRK; 705 atmel_port->break_active = 0; 706 } 707 } 708 709 atmel_buffer_rx_char(port, status, ch); 710 status = atmel_uart_readl(port, ATMEL_US_CSR); 711 } 712 713 tasklet_schedule(&atmel_port->tasklet); 714 } 715 716 /* 717 * Transmit characters (called from tasklet with TXRDY interrupt 718 * disabled) 719 */ 720 static void atmel_tx_chars(struct uart_port *port) 721 { 722 struct circ_buf *xmit = &port->state->xmit; 723 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 724 725 if (port->x_char && 726 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) { 727 atmel_uart_write_char(port, port->x_char); 728 port->icount.tx++; 729 port->x_char = 0; 730 } 731 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 732 return; 733 734 while (atmel_uart_readl(port, ATMEL_US_CSR) & 735 atmel_port->tx_done_mask) { 736 atmel_uart_write_char(port, xmit->buf[xmit->tail]); 737 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 738 port->icount.tx++; 739 if (uart_circ_empty(xmit)) 740 break; 741 } 742 743 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 744 uart_write_wakeup(port); 745 746 if (!uart_circ_empty(xmit)) 747 /* Enable interrupts */ 748 atmel_uart_writel(port, ATMEL_US_IER, 749 atmel_port->tx_done_mask); 750 } 751 752 static void atmel_complete_tx_dma(void *arg) 753 { 754 struct atmel_uart_port *atmel_port = arg; 755 struct uart_port *port = &atmel_port->uart; 756 struct circ_buf *xmit = &port->state->xmit; 757 struct dma_chan *chan = atmel_port->chan_tx; 758 unsigned long flags; 759 760 spin_lock_irqsave(&port->lock, flags); 761 762 if (chan) 763 dmaengine_terminate_all(chan); 764 xmit->tail += atmel_port->tx_len; 765 xmit->tail &= UART_XMIT_SIZE - 1; 766 767 port->icount.tx += atmel_port->tx_len; 768 769 spin_lock_irq(&atmel_port->lock_tx); 770 async_tx_ack(atmel_port->desc_tx); 771 atmel_port->cookie_tx = -EINVAL; 772 atmel_port->desc_tx = NULL; 773 spin_unlock_irq(&atmel_port->lock_tx); 774 775 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 776 uart_write_wakeup(port); 777 778 /* 779 * xmit is a circular buffer so, if we have just send data from 780 * xmit->tail to the end of xmit->buf, now we have to transmit the 781 * remaining data from the beginning of xmit->buf to xmit->head. 782 */ 783 if (!uart_circ_empty(xmit)) 784 tasklet_schedule(&atmel_port->tasklet); 785 786 spin_unlock_irqrestore(&port->lock, flags); 787 } 788 789 static void atmel_release_tx_dma(struct uart_port *port) 790 { 791 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 792 struct dma_chan *chan = atmel_port->chan_tx; 793 794 if (chan) { 795 dmaengine_terminate_all(chan); 796 dma_release_channel(chan); 797 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, 798 DMA_TO_DEVICE); 799 } 800 801 atmel_port->desc_tx = NULL; 802 atmel_port->chan_tx = NULL; 803 atmel_port->cookie_tx = -EINVAL; 804 } 805 806 /* 807 * Called from tasklet with TXRDY interrupt is disabled. 808 */ 809 static void atmel_tx_dma(struct uart_port *port) 810 { 811 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 812 struct circ_buf *xmit = &port->state->xmit; 813 struct dma_chan *chan = atmel_port->chan_tx; 814 struct dma_async_tx_descriptor *desc; 815 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx; 816 unsigned int tx_len, part1_len, part2_len, sg_len; 817 dma_addr_t phys_addr; 818 819 /* Make sure we have an idle channel */ 820 if (atmel_port->desc_tx != NULL) 821 return; 822 823 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 824 /* 825 * DMA is idle now. 826 * Port xmit buffer is already mapped, 827 * and it is one page... Just adjust 828 * offsets and lengths. Since it is a circular buffer, 829 * we have to transmit till the end, and then the rest. 830 * Take the port lock to get a 831 * consistent xmit buffer state. 832 */ 833 tx_len = CIRC_CNT_TO_END(xmit->head, 834 xmit->tail, 835 UART_XMIT_SIZE); 836 837 if (atmel_port->fifo_size) { 838 /* multi data mode */ 839 part1_len = (tx_len & ~0x3); /* DWORD access */ 840 part2_len = (tx_len & 0x3); /* BYTE access */ 841 } else { 842 /* single data (legacy) mode */ 843 part1_len = 0; 844 part2_len = tx_len; /* BYTE access only */ 845 } 846 847 sg_init_table(sgl, 2); 848 sg_len = 0; 849 phys_addr = sg_dma_address(sg_tx) + xmit->tail; 850 if (part1_len) { 851 sg = &sgl[sg_len++]; 852 sg_dma_address(sg) = phys_addr; 853 sg_dma_len(sg) = part1_len; 854 855 phys_addr += part1_len; 856 } 857 858 if (part2_len) { 859 sg = &sgl[sg_len++]; 860 sg_dma_address(sg) = phys_addr; 861 sg_dma_len(sg) = part2_len; 862 } 863 864 /* 865 * save tx_len so atmel_complete_tx_dma() will increase 866 * xmit->tail correctly 867 */ 868 atmel_port->tx_len = tx_len; 869 870 desc = dmaengine_prep_slave_sg(chan, 871 sgl, 872 sg_len, 873 DMA_MEM_TO_DEV, 874 DMA_PREP_INTERRUPT | 875 DMA_CTRL_ACK); 876 if (!desc) { 877 dev_err(port->dev, "Failed to send via dma!\n"); 878 return; 879 } 880 881 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE); 882 883 atmel_port->desc_tx = desc; 884 desc->callback = atmel_complete_tx_dma; 885 desc->callback_param = atmel_port; 886 atmel_port->cookie_tx = dmaengine_submit(desc); 887 888 } else { 889 if (port->rs485.flags & SER_RS485_ENABLED) { 890 /* DMA done, stop TX, start RX for RS485 */ 891 atmel_start_rx(port); 892 } 893 } 894 895 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 896 uart_write_wakeup(port); 897 } 898 899 static int atmel_prepare_tx_dma(struct uart_port *port) 900 { 901 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 902 dma_cap_mask_t mask; 903 struct dma_slave_config config; 904 int ret, nent; 905 906 dma_cap_zero(mask); 907 dma_cap_set(DMA_SLAVE, mask); 908 909 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx"); 910 if (atmel_port->chan_tx == NULL) 911 goto chan_err; 912 dev_info(port->dev, "using %s for tx DMA transfers\n", 913 dma_chan_name(atmel_port->chan_tx)); 914 915 spin_lock_init(&atmel_port->lock_tx); 916 sg_init_table(&atmel_port->sg_tx, 1); 917 /* UART circular tx buffer is an aligned page. */ 918 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf)); 919 sg_set_page(&atmel_port->sg_tx, 920 virt_to_page(port->state->xmit.buf), 921 UART_XMIT_SIZE, 922 (unsigned long)port->state->xmit.buf & ~PAGE_MASK); 923 nent = dma_map_sg(port->dev, 924 &atmel_port->sg_tx, 925 1, 926 DMA_TO_DEVICE); 927 928 if (!nent) { 929 dev_dbg(port->dev, "need to release resource of dma\n"); 930 goto chan_err; 931 } else { 932 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, 933 sg_dma_len(&atmel_port->sg_tx), 934 port->state->xmit.buf, 935 &sg_dma_address(&atmel_port->sg_tx)); 936 } 937 938 /* Configure the slave DMA */ 939 memset(&config, 0, sizeof(config)); 940 config.direction = DMA_MEM_TO_DEV; 941 config.dst_addr_width = (atmel_port->fifo_size) ? 942 DMA_SLAVE_BUSWIDTH_4_BYTES : 943 DMA_SLAVE_BUSWIDTH_1_BYTE; 944 config.dst_addr = port->mapbase + ATMEL_US_THR; 945 config.dst_maxburst = 1; 946 947 ret = dmaengine_slave_config(atmel_port->chan_tx, 948 &config); 949 if (ret) { 950 dev_err(port->dev, "DMA tx slave configuration failed\n"); 951 goto chan_err; 952 } 953 954 return 0; 955 956 chan_err: 957 dev_err(port->dev, "TX channel not available, switch to pio\n"); 958 atmel_port->use_dma_tx = 0; 959 if (atmel_port->chan_tx) 960 atmel_release_tx_dma(port); 961 return -EINVAL; 962 } 963 964 static void atmel_complete_rx_dma(void *arg) 965 { 966 struct uart_port *port = arg; 967 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 968 969 tasklet_schedule(&atmel_port->tasklet); 970 } 971 972 static void atmel_release_rx_dma(struct uart_port *port) 973 { 974 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 975 struct dma_chan *chan = atmel_port->chan_rx; 976 977 if (chan) { 978 dmaengine_terminate_all(chan); 979 dma_release_channel(chan); 980 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, 981 DMA_FROM_DEVICE); 982 } 983 984 atmel_port->desc_rx = NULL; 985 atmel_port->chan_rx = NULL; 986 atmel_port->cookie_rx = -EINVAL; 987 } 988 989 static void atmel_rx_from_dma(struct uart_port *port) 990 { 991 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 992 struct tty_port *tport = &port->state->port; 993 struct circ_buf *ring = &atmel_port->rx_ring; 994 struct dma_chan *chan = atmel_port->chan_rx; 995 struct dma_tx_state state; 996 enum dma_status dmastat; 997 size_t count; 998 999 1000 /* Reset the UART timeout early so that we don't miss one */ 1001 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1002 dmastat = dmaengine_tx_status(chan, 1003 atmel_port->cookie_rx, 1004 &state); 1005 /* Restart a new tasklet if DMA status is error */ 1006 if (dmastat == DMA_ERROR) { 1007 dev_dbg(port->dev, "Get residue error, restart tasklet\n"); 1008 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT); 1009 tasklet_schedule(&atmel_port->tasklet); 1010 return; 1011 } 1012 1013 /* CPU claims ownership of RX DMA buffer */ 1014 dma_sync_sg_for_cpu(port->dev, 1015 &atmel_port->sg_rx, 1016 1, 1017 DMA_FROM_DEVICE); 1018 1019 /* 1020 * ring->head points to the end of data already written by the DMA. 1021 * ring->tail points to the beginning of data to be read by the 1022 * framework. 1023 * The current transfer size should not be larger than the dma buffer 1024 * length. 1025 */ 1026 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue; 1027 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx)); 1028 /* 1029 * At this point ring->head may point to the first byte right after the 1030 * last byte of the dma buffer: 1031 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx) 1032 * 1033 * However ring->tail must always points inside the dma buffer: 1034 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1 1035 * 1036 * Since we use a ring buffer, we have to handle the case 1037 * where head is lower than tail. In such a case, we first read from 1038 * tail to the end of the buffer then reset tail. 1039 */ 1040 if (ring->head < ring->tail) { 1041 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail; 1042 1043 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 1044 ring->tail = 0; 1045 port->icount.rx += count; 1046 } 1047 1048 /* Finally we read data from tail to head */ 1049 if (ring->tail < ring->head) { 1050 count = ring->head - ring->tail; 1051 1052 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 1053 /* Wrap ring->head if needed */ 1054 if (ring->head >= sg_dma_len(&atmel_port->sg_rx)) 1055 ring->head = 0; 1056 ring->tail = ring->head; 1057 port->icount.rx += count; 1058 } 1059 1060 /* USART retreives ownership of RX DMA buffer */ 1061 dma_sync_sg_for_device(port->dev, 1062 &atmel_port->sg_rx, 1063 1, 1064 DMA_FROM_DEVICE); 1065 1066 /* 1067 * Drop the lock here since it might end up calling 1068 * uart_start(), which takes the lock. 1069 */ 1070 spin_unlock(&port->lock); 1071 tty_flip_buffer_push(tport); 1072 spin_lock(&port->lock); 1073 1074 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT); 1075 } 1076 1077 static int atmel_prepare_rx_dma(struct uart_port *port) 1078 { 1079 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1080 struct dma_async_tx_descriptor *desc; 1081 dma_cap_mask_t mask; 1082 struct dma_slave_config config; 1083 struct circ_buf *ring; 1084 int ret, nent; 1085 1086 ring = &atmel_port->rx_ring; 1087 1088 dma_cap_zero(mask); 1089 dma_cap_set(DMA_CYCLIC, mask); 1090 1091 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx"); 1092 if (atmel_port->chan_rx == NULL) 1093 goto chan_err; 1094 dev_info(port->dev, "using %s for rx DMA transfers\n", 1095 dma_chan_name(atmel_port->chan_rx)); 1096 1097 spin_lock_init(&atmel_port->lock_rx); 1098 sg_init_table(&atmel_port->sg_rx, 1); 1099 /* UART circular rx buffer is an aligned page. */ 1100 BUG_ON(!PAGE_ALIGNED(ring->buf)); 1101 sg_set_page(&atmel_port->sg_rx, 1102 virt_to_page(ring->buf), 1103 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE, 1104 (unsigned long)ring->buf & ~PAGE_MASK); 1105 nent = dma_map_sg(port->dev, 1106 &atmel_port->sg_rx, 1107 1, 1108 DMA_FROM_DEVICE); 1109 1110 if (!nent) { 1111 dev_dbg(port->dev, "need to release resource of dma\n"); 1112 goto chan_err; 1113 } else { 1114 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, 1115 sg_dma_len(&atmel_port->sg_rx), 1116 ring->buf, 1117 &sg_dma_address(&atmel_port->sg_rx)); 1118 } 1119 1120 /* Configure the slave DMA */ 1121 memset(&config, 0, sizeof(config)); 1122 config.direction = DMA_DEV_TO_MEM; 1123 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1124 config.src_addr = port->mapbase + ATMEL_US_RHR; 1125 config.src_maxburst = 1; 1126 1127 ret = dmaengine_slave_config(atmel_port->chan_rx, 1128 &config); 1129 if (ret) { 1130 dev_err(port->dev, "DMA rx slave configuration failed\n"); 1131 goto chan_err; 1132 } 1133 /* 1134 * Prepare a cyclic dma transfer, assign 2 descriptors, 1135 * each one is half ring buffer size 1136 */ 1137 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, 1138 sg_dma_address(&atmel_port->sg_rx), 1139 sg_dma_len(&atmel_port->sg_rx), 1140 sg_dma_len(&atmel_port->sg_rx)/2, 1141 DMA_DEV_TO_MEM, 1142 DMA_PREP_INTERRUPT); 1143 desc->callback = atmel_complete_rx_dma; 1144 desc->callback_param = port; 1145 atmel_port->desc_rx = desc; 1146 atmel_port->cookie_rx = dmaengine_submit(desc); 1147 1148 return 0; 1149 1150 chan_err: 1151 dev_err(port->dev, "RX channel not available, switch to pio\n"); 1152 atmel_port->use_dma_rx = 0; 1153 if (atmel_port->chan_rx) 1154 atmel_release_rx_dma(port); 1155 return -EINVAL; 1156 } 1157 1158 static void atmel_uart_timer_callback(unsigned long data) 1159 { 1160 struct uart_port *port = (void *)data; 1161 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1162 1163 tasklet_schedule(&atmel_port->tasklet); 1164 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port)); 1165 } 1166 1167 /* 1168 * receive interrupt handler. 1169 */ 1170 static void 1171 atmel_handle_receive(struct uart_port *port, unsigned int pending) 1172 { 1173 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1174 1175 if (atmel_use_pdc_rx(port)) { 1176 /* 1177 * PDC receive. Just schedule the tasklet and let it 1178 * figure out the details. 1179 * 1180 * TODO: We're not handling error flags correctly at 1181 * the moment. 1182 */ 1183 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { 1184 atmel_uart_writel(port, ATMEL_US_IDR, 1185 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)); 1186 tasklet_schedule(&atmel_port->tasklet); 1187 } 1188 1189 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | 1190 ATMEL_US_FRAME | ATMEL_US_PARE)) 1191 atmel_pdc_rxerr(port, pending); 1192 } 1193 1194 if (atmel_use_dma_rx(port)) { 1195 if (pending & ATMEL_US_TIMEOUT) { 1196 atmel_uart_writel(port, ATMEL_US_IDR, 1197 ATMEL_US_TIMEOUT); 1198 tasklet_schedule(&atmel_port->tasklet); 1199 } 1200 } 1201 1202 /* Interrupt receive */ 1203 if (pending & ATMEL_US_RXRDY) 1204 atmel_rx_chars(port); 1205 else if (pending & ATMEL_US_RXBRK) { 1206 /* 1207 * End of break detected. If it came along with a 1208 * character, atmel_rx_chars will handle it. 1209 */ 1210 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 1211 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK); 1212 atmel_port->break_active = 0; 1213 } 1214 } 1215 1216 /* 1217 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) 1218 */ 1219 static void 1220 atmel_handle_transmit(struct uart_port *port, unsigned int pending) 1221 { 1222 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1223 1224 if (pending & atmel_port->tx_done_mask) { 1225 /* Either PDC or interrupt transmission */ 1226 atmel_uart_writel(port, ATMEL_US_IDR, 1227 atmel_port->tx_done_mask); 1228 tasklet_schedule(&atmel_port->tasklet); 1229 } 1230 } 1231 1232 /* 1233 * status flags interrupt handler. 1234 */ 1235 static void 1236 atmel_handle_status(struct uart_port *port, unsigned int pending, 1237 unsigned int status) 1238 { 1239 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1240 1241 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC 1242 | ATMEL_US_CTSIC)) { 1243 atmel_port->irq_status = status; 1244 atmel_port->status_change = atmel_port->irq_status ^ 1245 atmel_port->irq_status_prev; 1246 atmel_port->irq_status_prev = status; 1247 tasklet_schedule(&atmel_port->tasklet); 1248 } 1249 } 1250 1251 /* 1252 * Interrupt handler 1253 */ 1254 static irqreturn_t atmel_interrupt(int irq, void *dev_id) 1255 { 1256 struct uart_port *port = dev_id; 1257 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1258 unsigned int status, pending, mask, pass_counter = 0; 1259 1260 spin_lock(&atmel_port->lock_suspended); 1261 1262 do { 1263 status = atmel_get_lines_status(port); 1264 mask = atmel_uart_readl(port, ATMEL_US_IMR); 1265 pending = status & mask; 1266 if (!pending) 1267 break; 1268 1269 if (atmel_port->suspended) { 1270 atmel_port->pending |= pending; 1271 atmel_port->pending_status = status; 1272 atmel_uart_writel(port, ATMEL_US_IDR, mask); 1273 pm_system_wakeup(); 1274 break; 1275 } 1276 1277 atmel_handle_receive(port, pending); 1278 atmel_handle_status(port, pending, status); 1279 atmel_handle_transmit(port, pending); 1280 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); 1281 1282 spin_unlock(&atmel_port->lock_suspended); 1283 1284 return pass_counter ? IRQ_HANDLED : IRQ_NONE; 1285 } 1286 1287 static void atmel_release_tx_pdc(struct uart_port *port) 1288 { 1289 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1290 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1291 1292 dma_unmap_single(port->dev, 1293 pdc->dma_addr, 1294 pdc->dma_size, 1295 DMA_TO_DEVICE); 1296 } 1297 1298 /* 1299 * Called from tasklet with ENDTX and TXBUFE interrupts disabled. 1300 */ 1301 static void atmel_tx_pdc(struct uart_port *port) 1302 { 1303 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1304 struct circ_buf *xmit = &port->state->xmit; 1305 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1306 int count; 1307 1308 /* nothing left to transmit? */ 1309 if (atmel_uart_readl(port, ATMEL_PDC_TCR)) 1310 return; 1311 1312 xmit->tail += pdc->ofs; 1313 xmit->tail &= UART_XMIT_SIZE - 1; 1314 1315 port->icount.tx += pdc->ofs; 1316 pdc->ofs = 0; 1317 1318 /* more to transmit - setup next transfer */ 1319 1320 /* disable PDC transmit */ 1321 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 1322 1323 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 1324 dma_sync_single_for_device(port->dev, 1325 pdc->dma_addr, 1326 pdc->dma_size, 1327 DMA_TO_DEVICE); 1328 1329 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1330 pdc->ofs = count; 1331 1332 atmel_uart_writel(port, ATMEL_PDC_TPR, 1333 pdc->dma_addr + xmit->tail); 1334 atmel_uart_writel(port, ATMEL_PDC_TCR, count); 1335 /* re-enable PDC transmit */ 1336 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 1337 /* Enable interrupts */ 1338 atmel_uart_writel(port, ATMEL_US_IER, 1339 atmel_port->tx_done_mask); 1340 } else { 1341 if ((port->rs485.flags & SER_RS485_ENABLED) && 1342 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) { 1343 /* DMA done, stop TX, start RX for RS485 */ 1344 atmel_start_rx(port); 1345 } 1346 } 1347 1348 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1349 uart_write_wakeup(port); 1350 } 1351 1352 static int atmel_prepare_tx_pdc(struct uart_port *port) 1353 { 1354 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1355 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1356 struct circ_buf *xmit = &port->state->xmit; 1357 1358 pdc->buf = xmit->buf; 1359 pdc->dma_addr = dma_map_single(port->dev, 1360 pdc->buf, 1361 UART_XMIT_SIZE, 1362 DMA_TO_DEVICE); 1363 pdc->dma_size = UART_XMIT_SIZE; 1364 pdc->ofs = 0; 1365 1366 return 0; 1367 } 1368 1369 static void atmel_rx_from_ring(struct uart_port *port) 1370 { 1371 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1372 struct circ_buf *ring = &atmel_port->rx_ring; 1373 unsigned int flg; 1374 unsigned int status; 1375 1376 while (ring->head != ring->tail) { 1377 struct atmel_uart_char c; 1378 1379 /* Make sure c is loaded after head. */ 1380 smp_rmb(); 1381 1382 c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; 1383 1384 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 1385 1386 port->icount.rx++; 1387 status = c.status; 1388 flg = TTY_NORMAL; 1389 1390 /* 1391 * note that the error handling code is 1392 * out of the main execution path 1393 */ 1394 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 1395 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { 1396 if (status & ATMEL_US_RXBRK) { 1397 /* ignore side-effect */ 1398 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 1399 1400 port->icount.brk++; 1401 if (uart_handle_break(port)) 1402 continue; 1403 } 1404 if (status & ATMEL_US_PARE) 1405 port->icount.parity++; 1406 if (status & ATMEL_US_FRAME) 1407 port->icount.frame++; 1408 if (status & ATMEL_US_OVRE) 1409 port->icount.overrun++; 1410 1411 status &= port->read_status_mask; 1412 1413 if (status & ATMEL_US_RXBRK) 1414 flg = TTY_BREAK; 1415 else if (status & ATMEL_US_PARE) 1416 flg = TTY_PARITY; 1417 else if (status & ATMEL_US_FRAME) 1418 flg = TTY_FRAME; 1419 } 1420 1421 1422 if (uart_handle_sysrq_char(port, c.ch)) 1423 continue; 1424 1425 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); 1426 } 1427 1428 /* 1429 * Drop the lock here since it might end up calling 1430 * uart_start(), which takes the lock. 1431 */ 1432 spin_unlock(&port->lock); 1433 tty_flip_buffer_push(&port->state->port); 1434 spin_lock(&port->lock); 1435 } 1436 1437 static void atmel_release_rx_pdc(struct uart_port *port) 1438 { 1439 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1440 int i; 1441 1442 for (i = 0; i < 2; i++) { 1443 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1444 1445 dma_unmap_single(port->dev, 1446 pdc->dma_addr, 1447 pdc->dma_size, 1448 DMA_FROM_DEVICE); 1449 kfree(pdc->buf); 1450 } 1451 } 1452 1453 static void atmel_rx_from_pdc(struct uart_port *port) 1454 { 1455 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1456 struct tty_port *tport = &port->state->port; 1457 struct atmel_dma_buffer *pdc; 1458 int rx_idx = atmel_port->pdc_rx_idx; 1459 unsigned int head; 1460 unsigned int tail; 1461 unsigned int count; 1462 1463 do { 1464 /* Reset the UART timeout early so that we don't miss one */ 1465 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1466 1467 pdc = &atmel_port->pdc_rx[rx_idx]; 1468 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr; 1469 tail = pdc->ofs; 1470 1471 /* If the PDC has switched buffers, RPR won't contain 1472 * any address within the current buffer. Since head 1473 * is unsigned, we just need a one-way comparison to 1474 * find out. 1475 * 1476 * In this case, we just need to consume the entire 1477 * buffer and resubmit it for DMA. This will clear the 1478 * ENDRX bit as well, so that we can safely re-enable 1479 * all interrupts below. 1480 */ 1481 head = min(head, pdc->dma_size); 1482 1483 if (likely(head != tail)) { 1484 dma_sync_single_for_cpu(port->dev, pdc->dma_addr, 1485 pdc->dma_size, DMA_FROM_DEVICE); 1486 1487 /* 1488 * head will only wrap around when we recycle 1489 * the DMA buffer, and when that happens, we 1490 * explicitly set tail to 0. So head will 1491 * always be greater than tail. 1492 */ 1493 count = head - tail; 1494 1495 tty_insert_flip_string(tport, pdc->buf + pdc->ofs, 1496 count); 1497 1498 dma_sync_single_for_device(port->dev, pdc->dma_addr, 1499 pdc->dma_size, DMA_FROM_DEVICE); 1500 1501 port->icount.rx += count; 1502 pdc->ofs = head; 1503 } 1504 1505 /* 1506 * If the current buffer is full, we need to check if 1507 * the next one contains any additional data. 1508 */ 1509 if (head >= pdc->dma_size) { 1510 pdc->ofs = 0; 1511 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr); 1512 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size); 1513 1514 rx_idx = !rx_idx; 1515 atmel_port->pdc_rx_idx = rx_idx; 1516 } 1517 } while (head >= pdc->dma_size); 1518 1519 /* 1520 * Drop the lock here since it might end up calling 1521 * uart_start(), which takes the lock. 1522 */ 1523 spin_unlock(&port->lock); 1524 tty_flip_buffer_push(tport); 1525 spin_lock(&port->lock); 1526 1527 atmel_uart_writel(port, ATMEL_US_IER, 1528 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1529 } 1530 1531 static int atmel_prepare_rx_pdc(struct uart_port *port) 1532 { 1533 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1534 int i; 1535 1536 for (i = 0; i < 2; i++) { 1537 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1538 1539 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); 1540 if (pdc->buf == NULL) { 1541 if (i != 0) { 1542 dma_unmap_single(port->dev, 1543 atmel_port->pdc_rx[0].dma_addr, 1544 PDC_BUFFER_SIZE, 1545 DMA_FROM_DEVICE); 1546 kfree(atmel_port->pdc_rx[0].buf); 1547 } 1548 atmel_port->use_pdc_rx = 0; 1549 return -ENOMEM; 1550 } 1551 pdc->dma_addr = dma_map_single(port->dev, 1552 pdc->buf, 1553 PDC_BUFFER_SIZE, 1554 DMA_FROM_DEVICE); 1555 pdc->dma_size = PDC_BUFFER_SIZE; 1556 pdc->ofs = 0; 1557 } 1558 1559 atmel_port->pdc_rx_idx = 0; 1560 1561 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr); 1562 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE); 1563 1564 atmel_uart_writel(port, ATMEL_PDC_RNPR, 1565 atmel_port->pdc_rx[1].dma_addr); 1566 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE); 1567 1568 return 0; 1569 } 1570 1571 /* 1572 * tasklet handling tty stuff outside the interrupt handler. 1573 */ 1574 static void atmel_tasklet_func(unsigned long data) 1575 { 1576 struct uart_port *port = (struct uart_port *)data; 1577 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1578 unsigned int status = atmel_port->irq_status; 1579 unsigned int status_change = atmel_port->status_change; 1580 1581 /* The interrupt handler does not take the lock */ 1582 spin_lock(&port->lock); 1583 1584 atmel_port->schedule_tx(port); 1585 1586 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR 1587 | ATMEL_US_DCD | ATMEL_US_CTS)) { 1588 /* TODO: All reads to CSR will clear these interrupts! */ 1589 if (status_change & ATMEL_US_RI) 1590 port->icount.rng++; 1591 if (status_change & ATMEL_US_DSR) 1592 port->icount.dsr++; 1593 if (status_change & ATMEL_US_DCD) 1594 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); 1595 if (status_change & ATMEL_US_CTS) 1596 uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); 1597 1598 wake_up_interruptible(&port->state->port.delta_msr_wait); 1599 1600 atmel_port->status_change = 0; 1601 } 1602 1603 atmel_port->schedule_rx(port); 1604 1605 spin_unlock(&port->lock); 1606 } 1607 1608 static void atmel_init_property(struct atmel_uart_port *atmel_port, 1609 struct platform_device *pdev) 1610 { 1611 struct device_node *np = pdev->dev.of_node; 1612 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1613 1614 if (np) { 1615 /* DMA/PDC usage specification */ 1616 if (of_get_property(np, "atmel,use-dma-rx", NULL)) { 1617 if (of_get_property(np, "dmas", NULL)) { 1618 atmel_port->use_dma_rx = true; 1619 atmel_port->use_pdc_rx = false; 1620 } else { 1621 atmel_port->use_dma_rx = false; 1622 atmel_port->use_pdc_rx = true; 1623 } 1624 } else { 1625 atmel_port->use_dma_rx = false; 1626 atmel_port->use_pdc_rx = false; 1627 } 1628 1629 if (of_get_property(np, "atmel,use-dma-tx", NULL)) { 1630 if (of_get_property(np, "dmas", NULL)) { 1631 atmel_port->use_dma_tx = true; 1632 atmel_port->use_pdc_tx = false; 1633 } else { 1634 atmel_port->use_dma_tx = false; 1635 atmel_port->use_pdc_tx = true; 1636 } 1637 } else { 1638 atmel_port->use_dma_tx = false; 1639 atmel_port->use_pdc_tx = false; 1640 } 1641 1642 } else { 1643 atmel_port->use_pdc_rx = pdata->use_dma_rx; 1644 atmel_port->use_pdc_tx = pdata->use_dma_tx; 1645 atmel_port->use_dma_rx = false; 1646 atmel_port->use_dma_tx = false; 1647 } 1648 1649 } 1650 1651 static void atmel_init_rs485(struct uart_port *port, 1652 struct platform_device *pdev) 1653 { 1654 struct device_node *np = pdev->dev.of_node; 1655 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1656 1657 if (np) { 1658 struct serial_rs485 *rs485conf = &port->rs485; 1659 u32 rs485_delay[2]; 1660 /* rs485 properties */ 1661 if (of_property_read_u32_array(np, "rs485-rts-delay", 1662 rs485_delay, 2) == 0) { 1663 rs485conf->delay_rts_before_send = rs485_delay[0]; 1664 rs485conf->delay_rts_after_send = rs485_delay[1]; 1665 rs485conf->flags = 0; 1666 } 1667 1668 if (of_get_property(np, "rs485-rx-during-tx", NULL)) 1669 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1670 1671 if (of_get_property(np, "linux,rs485-enabled-at-boot-time", 1672 NULL)) 1673 rs485conf->flags |= SER_RS485_ENABLED; 1674 } else { 1675 port->rs485 = pdata->rs485; 1676 } 1677 1678 } 1679 1680 static void atmel_set_ops(struct uart_port *port) 1681 { 1682 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1683 1684 if (atmel_use_dma_rx(port)) { 1685 atmel_port->prepare_rx = &atmel_prepare_rx_dma; 1686 atmel_port->schedule_rx = &atmel_rx_from_dma; 1687 atmel_port->release_rx = &atmel_release_rx_dma; 1688 } else if (atmel_use_pdc_rx(port)) { 1689 atmel_port->prepare_rx = &atmel_prepare_rx_pdc; 1690 atmel_port->schedule_rx = &atmel_rx_from_pdc; 1691 atmel_port->release_rx = &atmel_release_rx_pdc; 1692 } else { 1693 atmel_port->prepare_rx = NULL; 1694 atmel_port->schedule_rx = &atmel_rx_from_ring; 1695 atmel_port->release_rx = NULL; 1696 } 1697 1698 if (atmel_use_dma_tx(port)) { 1699 atmel_port->prepare_tx = &atmel_prepare_tx_dma; 1700 atmel_port->schedule_tx = &atmel_tx_dma; 1701 atmel_port->release_tx = &atmel_release_tx_dma; 1702 } else if (atmel_use_pdc_tx(port)) { 1703 atmel_port->prepare_tx = &atmel_prepare_tx_pdc; 1704 atmel_port->schedule_tx = &atmel_tx_pdc; 1705 atmel_port->release_tx = &atmel_release_tx_pdc; 1706 } else { 1707 atmel_port->prepare_tx = NULL; 1708 atmel_port->schedule_tx = &atmel_tx_chars; 1709 atmel_port->release_tx = NULL; 1710 } 1711 } 1712 1713 /* 1714 * Get ip name usart or uart 1715 */ 1716 static void atmel_get_ip_name(struct uart_port *port) 1717 { 1718 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1719 int name = atmel_uart_readl(port, ATMEL_US_NAME); 1720 u32 version; 1721 u32 usart, dbgu_uart, new_uart; 1722 /* ASCII decoding for IP version */ 1723 usart = 0x55534152; /* USAR(T) */ 1724 dbgu_uart = 0x44424755; /* DBGU */ 1725 new_uart = 0x55415254; /* UART */ 1726 1727 atmel_port->has_hw_timer = false; 1728 1729 if (name == new_uart) { 1730 dev_dbg(port->dev, "Uart with hw timer"); 1731 atmel_port->has_hw_timer = true; 1732 atmel_port->rtor = ATMEL_UA_RTOR; 1733 } else if (name == usart) { 1734 dev_dbg(port->dev, "Usart\n"); 1735 atmel_port->has_hw_timer = true; 1736 atmel_port->rtor = ATMEL_US_RTOR; 1737 } else if (name == dbgu_uart) { 1738 dev_dbg(port->dev, "Dbgu or uart without hw timer\n"); 1739 } else { 1740 /* fallback for older SoCs: use version field */ 1741 version = atmel_uart_readl(port, ATMEL_US_VERSION); 1742 switch (version) { 1743 case 0x302: 1744 case 0x10213: 1745 dev_dbg(port->dev, "This version is usart\n"); 1746 atmel_port->has_hw_timer = true; 1747 atmel_port->rtor = ATMEL_US_RTOR; 1748 break; 1749 case 0x203: 1750 case 0x10202: 1751 dev_dbg(port->dev, "This version is uart\n"); 1752 break; 1753 default: 1754 dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); 1755 } 1756 } 1757 } 1758 1759 /* 1760 * Perform initialization and enable port for reception 1761 */ 1762 static int atmel_startup(struct uart_port *port) 1763 { 1764 struct platform_device *pdev = to_platform_device(port->dev); 1765 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1766 struct tty_struct *tty = port->state->port.tty; 1767 int retval; 1768 1769 /* 1770 * Ensure that no interrupts are enabled otherwise when 1771 * request_irq() is called we could get stuck trying to 1772 * handle an unexpected interrupt 1773 */ 1774 atmel_uart_writel(port, ATMEL_US_IDR, -1); 1775 atmel_port->ms_irq_enabled = false; 1776 1777 /* 1778 * Allocate the IRQ 1779 */ 1780 retval = request_irq(port->irq, atmel_interrupt, 1781 IRQF_SHARED | IRQF_COND_SUSPEND, 1782 tty ? tty->name : "atmel_serial", port); 1783 if (retval) { 1784 dev_err(port->dev, "atmel_startup - Can't get irq\n"); 1785 return retval; 1786 } 1787 1788 tasklet_enable(&atmel_port->tasklet); 1789 1790 /* 1791 * Initialize DMA (if necessary) 1792 */ 1793 atmel_init_property(atmel_port, pdev); 1794 atmel_set_ops(port); 1795 1796 if (atmel_port->prepare_rx) { 1797 retval = atmel_port->prepare_rx(port); 1798 if (retval < 0) 1799 atmel_set_ops(port); 1800 } 1801 1802 if (atmel_port->prepare_tx) { 1803 retval = atmel_port->prepare_tx(port); 1804 if (retval < 0) 1805 atmel_set_ops(port); 1806 } 1807 1808 /* 1809 * Enable FIFO when available 1810 */ 1811 if (atmel_port->fifo_size) { 1812 unsigned int txrdym = ATMEL_US_ONE_DATA; 1813 unsigned int rxrdym = ATMEL_US_ONE_DATA; 1814 unsigned int fmr; 1815 1816 atmel_uart_writel(port, ATMEL_US_CR, 1817 ATMEL_US_FIFOEN | 1818 ATMEL_US_RXFCLR | 1819 ATMEL_US_TXFLCLR); 1820 1821 if (atmel_use_dma_tx(port)) 1822 txrdym = ATMEL_US_FOUR_DATA; 1823 1824 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym); 1825 if (atmel_port->rts_high && 1826 atmel_port->rts_low) 1827 fmr |= ATMEL_US_FRTSC | 1828 ATMEL_US_RXFTHRES(atmel_port->rts_high) | 1829 ATMEL_US_RXFTHRES2(atmel_port->rts_low); 1830 1831 atmel_uart_writel(port, ATMEL_US_FMR, fmr); 1832 } 1833 1834 /* Save current CSR for comparison in atmel_tasklet_func() */ 1835 atmel_port->irq_status_prev = atmel_get_lines_status(port); 1836 atmel_port->irq_status = atmel_port->irq_status_prev; 1837 1838 /* 1839 * Finally, enable the serial port 1840 */ 1841 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1842 /* enable xmit & rcvr */ 1843 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 1844 1845 setup_timer(&atmel_port->uart_timer, 1846 atmel_uart_timer_callback, 1847 (unsigned long)port); 1848 1849 if (atmel_use_pdc_rx(port)) { 1850 /* set UART timeout */ 1851 if (!atmel_port->has_hw_timer) { 1852 mod_timer(&atmel_port->uart_timer, 1853 jiffies + uart_poll_timeout(port)); 1854 /* set USART timeout */ 1855 } else { 1856 atmel_uart_writel(port, atmel_port->rtor, 1857 PDC_RX_TIMEOUT); 1858 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1859 1860 atmel_uart_writel(port, ATMEL_US_IER, 1861 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1862 } 1863 /* enable PDC controller */ 1864 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 1865 } else if (atmel_use_dma_rx(port)) { 1866 /* set UART timeout */ 1867 if (!atmel_port->has_hw_timer) { 1868 mod_timer(&atmel_port->uart_timer, 1869 jiffies + uart_poll_timeout(port)); 1870 /* set USART timeout */ 1871 } else { 1872 atmel_uart_writel(port, atmel_port->rtor, 1873 PDC_RX_TIMEOUT); 1874 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1875 1876 atmel_uart_writel(port, ATMEL_US_IER, 1877 ATMEL_US_TIMEOUT); 1878 } 1879 } else { 1880 /* enable receive only */ 1881 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY); 1882 } 1883 1884 return 0; 1885 } 1886 1887 /* 1888 * Flush any TX data submitted for DMA. Called when the TX circular 1889 * buffer is reset. 1890 */ 1891 static void atmel_flush_buffer(struct uart_port *port) 1892 { 1893 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1894 1895 if (atmel_use_pdc_tx(port)) { 1896 atmel_uart_writel(port, ATMEL_PDC_TCR, 0); 1897 atmel_port->pdc_tx.ofs = 0; 1898 } 1899 } 1900 1901 /* 1902 * Disable the port 1903 */ 1904 static void atmel_shutdown(struct uart_port *port) 1905 { 1906 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1907 1908 /* 1909 * Prevent any tasklets being scheduled during 1910 * cleanup 1911 */ 1912 del_timer_sync(&atmel_port->uart_timer); 1913 1914 /* 1915 * Clear out any scheduled tasklets before 1916 * we destroy the buffers 1917 */ 1918 tasklet_disable(&atmel_port->tasklet); 1919 tasklet_kill(&atmel_port->tasklet); 1920 1921 /* 1922 * Ensure everything is stopped and 1923 * disable all interrupts, port and break condition. 1924 */ 1925 atmel_stop_rx(port); 1926 atmel_stop_tx(port); 1927 1928 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 1929 atmel_uart_writel(port, ATMEL_US_IDR, -1); 1930 1931 1932 /* 1933 * Shut-down the DMA. 1934 */ 1935 if (atmel_port->release_rx) 1936 atmel_port->release_rx(port); 1937 if (atmel_port->release_tx) 1938 atmel_port->release_tx(port); 1939 1940 /* 1941 * Reset ring buffer pointers 1942 */ 1943 atmel_port->rx_ring.head = 0; 1944 atmel_port->rx_ring.tail = 0; 1945 1946 /* 1947 * Free the interrupts 1948 */ 1949 free_irq(port->irq, port); 1950 1951 atmel_port->ms_irq_enabled = false; 1952 1953 atmel_flush_buffer(port); 1954 } 1955 1956 /* 1957 * Power / Clock management. 1958 */ 1959 static void atmel_serial_pm(struct uart_port *port, unsigned int state, 1960 unsigned int oldstate) 1961 { 1962 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1963 1964 switch (state) { 1965 case 0: 1966 /* 1967 * Enable the peripheral clock for this serial port. 1968 * This is called on uart_open() or a resume event. 1969 */ 1970 clk_prepare_enable(atmel_port->clk); 1971 1972 /* re-enable interrupts if we disabled some on suspend */ 1973 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr); 1974 break; 1975 case 3: 1976 /* Back up the interrupt mask and disable all interrupts */ 1977 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR); 1978 atmel_uart_writel(port, ATMEL_US_IDR, -1); 1979 1980 /* 1981 * Disable the peripheral clock for this serial port. 1982 * This is called on uart_close() or a suspend event. 1983 */ 1984 clk_disable_unprepare(atmel_port->clk); 1985 break; 1986 default: 1987 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); 1988 } 1989 } 1990 1991 /* 1992 * Change the port parameters 1993 */ 1994 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, 1995 struct ktermios *old) 1996 { 1997 unsigned long flags; 1998 unsigned int old_mode, mode, imr, quot, baud; 1999 2000 /* save the current mode register */ 2001 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR); 2002 2003 /* reset the mode, clock divisor, parity, stop bits and data size */ 2004 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | 2005 ATMEL_US_PAR | ATMEL_US_USMODE); 2006 2007 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 2008 quot = uart_get_divisor(port, baud); 2009 2010 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ 2011 quot /= 8; 2012 mode |= ATMEL_US_USCLKS_MCK_DIV8; 2013 } 2014 2015 /* byte size */ 2016 switch (termios->c_cflag & CSIZE) { 2017 case CS5: 2018 mode |= ATMEL_US_CHRL_5; 2019 break; 2020 case CS6: 2021 mode |= ATMEL_US_CHRL_6; 2022 break; 2023 case CS7: 2024 mode |= ATMEL_US_CHRL_7; 2025 break; 2026 default: 2027 mode |= ATMEL_US_CHRL_8; 2028 break; 2029 } 2030 2031 /* stop bits */ 2032 if (termios->c_cflag & CSTOPB) 2033 mode |= ATMEL_US_NBSTOP_2; 2034 2035 /* parity */ 2036 if (termios->c_cflag & PARENB) { 2037 /* Mark or Space parity */ 2038 if (termios->c_cflag & CMSPAR) { 2039 if (termios->c_cflag & PARODD) 2040 mode |= ATMEL_US_PAR_MARK; 2041 else 2042 mode |= ATMEL_US_PAR_SPACE; 2043 } else if (termios->c_cflag & PARODD) 2044 mode |= ATMEL_US_PAR_ODD; 2045 else 2046 mode |= ATMEL_US_PAR_EVEN; 2047 } else 2048 mode |= ATMEL_US_PAR_NONE; 2049 2050 spin_lock_irqsave(&port->lock, flags); 2051 2052 port->read_status_mask = ATMEL_US_OVRE; 2053 if (termios->c_iflag & INPCK) 2054 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2055 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2056 port->read_status_mask |= ATMEL_US_RXBRK; 2057 2058 if (atmel_use_pdc_rx(port)) 2059 /* need to enable error interrupts */ 2060 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask); 2061 2062 /* 2063 * Characters to ignore 2064 */ 2065 port->ignore_status_mask = 0; 2066 if (termios->c_iflag & IGNPAR) 2067 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2068 if (termios->c_iflag & IGNBRK) { 2069 port->ignore_status_mask |= ATMEL_US_RXBRK; 2070 /* 2071 * If we're ignoring parity and break indicators, 2072 * ignore overruns too (for real raw support). 2073 */ 2074 if (termios->c_iflag & IGNPAR) 2075 port->ignore_status_mask |= ATMEL_US_OVRE; 2076 } 2077 /* TODO: Ignore all characters if CREAD is set.*/ 2078 2079 /* update the per-port timeout */ 2080 uart_update_timeout(port, termios->c_cflag, baud); 2081 2082 /* 2083 * save/disable interrupts. The tty layer will ensure that the 2084 * transmitter is empty if requested by the caller, so there's 2085 * no need to wait for it here. 2086 */ 2087 imr = atmel_uart_readl(port, ATMEL_US_IMR); 2088 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2089 2090 /* disable receiver and transmitter */ 2091 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS); 2092 2093 /* mode */ 2094 if (port->rs485.flags & SER_RS485_ENABLED) { 2095 atmel_uart_writel(port, ATMEL_US_TTGR, 2096 port->rs485.delay_rts_after_send); 2097 mode |= ATMEL_US_USMODE_RS485; 2098 } else if (termios->c_cflag & CRTSCTS) { 2099 /* RS232 with hardware handshake (RTS/CTS) */ 2100 if (atmel_use_dma_rx(port) && !atmel_use_fifo(port)) { 2101 dev_info(port->dev, "not enabling hardware flow control because DMA is used"); 2102 termios->c_cflag &= ~CRTSCTS; 2103 } else { 2104 mode |= ATMEL_US_USMODE_HWHS; 2105 } 2106 } else { 2107 /* RS232 without hadware handshake */ 2108 mode |= ATMEL_US_USMODE_NORMAL; 2109 } 2110 2111 /* set the mode, clock divisor, parity, stop bits and data size */ 2112 atmel_uart_writel(port, ATMEL_US_MR, mode); 2113 2114 /* 2115 * when switching the mode, set the RTS line state according to the 2116 * new mode, otherwise keep the former state 2117 */ 2118 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) { 2119 unsigned int rts_state; 2120 2121 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 2122 /* let the hardware control the RTS line */ 2123 rts_state = ATMEL_US_RTSDIS; 2124 } else { 2125 /* force RTS line to low level */ 2126 rts_state = ATMEL_US_RTSEN; 2127 } 2128 2129 atmel_uart_writel(port, ATMEL_US_CR, rts_state); 2130 } 2131 2132 /* set the baud rate */ 2133 atmel_uart_writel(port, ATMEL_US_BRGR, quot); 2134 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2135 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 2136 2137 /* restore interrupts */ 2138 atmel_uart_writel(port, ATMEL_US_IER, imr); 2139 2140 /* CTS flow-control and modem-status interrupts */ 2141 if (UART_ENABLE_MS(port, termios->c_cflag)) 2142 atmel_enable_ms(port); 2143 else 2144 atmel_disable_ms(port); 2145 2146 spin_unlock_irqrestore(&port->lock, flags); 2147 } 2148 2149 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios) 2150 { 2151 if (termios->c_line == N_PPS) { 2152 port->flags |= UPF_HARDPPS_CD; 2153 spin_lock_irq(&port->lock); 2154 atmel_enable_ms(port); 2155 spin_unlock_irq(&port->lock); 2156 } else { 2157 port->flags &= ~UPF_HARDPPS_CD; 2158 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 2159 spin_lock_irq(&port->lock); 2160 atmel_disable_ms(port); 2161 spin_unlock_irq(&port->lock); 2162 } 2163 } 2164 } 2165 2166 /* 2167 * Return string describing the specified port 2168 */ 2169 static const char *atmel_type(struct uart_port *port) 2170 { 2171 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; 2172 } 2173 2174 /* 2175 * Release the memory region(s) being used by 'port'. 2176 */ 2177 static void atmel_release_port(struct uart_port *port) 2178 { 2179 struct platform_device *pdev = to_platform_device(port->dev); 2180 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 2181 2182 release_mem_region(port->mapbase, size); 2183 2184 if (port->flags & UPF_IOREMAP) { 2185 iounmap(port->membase); 2186 port->membase = NULL; 2187 } 2188 } 2189 2190 /* 2191 * Request the memory region(s) being used by 'port'. 2192 */ 2193 static int atmel_request_port(struct uart_port *port) 2194 { 2195 struct platform_device *pdev = to_platform_device(port->dev); 2196 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 2197 2198 if (!request_mem_region(port->mapbase, size, "atmel_serial")) 2199 return -EBUSY; 2200 2201 if (port->flags & UPF_IOREMAP) { 2202 port->membase = ioremap(port->mapbase, size); 2203 if (port->membase == NULL) { 2204 release_mem_region(port->mapbase, size); 2205 return -ENOMEM; 2206 } 2207 } 2208 2209 return 0; 2210 } 2211 2212 /* 2213 * Configure/autoconfigure the port. 2214 */ 2215 static void atmel_config_port(struct uart_port *port, int flags) 2216 { 2217 if (flags & UART_CONFIG_TYPE) { 2218 port->type = PORT_ATMEL; 2219 atmel_request_port(port); 2220 } 2221 } 2222 2223 /* 2224 * Verify the new serial_struct (for TIOCSSERIAL). 2225 */ 2226 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) 2227 { 2228 int ret = 0; 2229 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) 2230 ret = -EINVAL; 2231 if (port->irq != ser->irq) 2232 ret = -EINVAL; 2233 if (ser->io_type != SERIAL_IO_MEM) 2234 ret = -EINVAL; 2235 if (port->uartclk / 16 != ser->baud_base) 2236 ret = -EINVAL; 2237 if (port->mapbase != (unsigned long)ser->iomem_base) 2238 ret = -EINVAL; 2239 if (port->iobase != ser->port) 2240 ret = -EINVAL; 2241 if (ser->hub6 != 0) 2242 ret = -EINVAL; 2243 return ret; 2244 } 2245 2246 #ifdef CONFIG_CONSOLE_POLL 2247 static int atmel_poll_get_char(struct uart_port *port) 2248 { 2249 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY)) 2250 cpu_relax(); 2251 2252 return atmel_uart_read_char(port); 2253 } 2254 2255 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) 2256 { 2257 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) 2258 cpu_relax(); 2259 2260 atmel_uart_write_char(port, ch); 2261 } 2262 #endif 2263 2264 static struct uart_ops atmel_pops = { 2265 .tx_empty = atmel_tx_empty, 2266 .set_mctrl = atmel_set_mctrl, 2267 .get_mctrl = atmel_get_mctrl, 2268 .stop_tx = atmel_stop_tx, 2269 .start_tx = atmel_start_tx, 2270 .stop_rx = atmel_stop_rx, 2271 .enable_ms = atmel_enable_ms, 2272 .break_ctl = atmel_break_ctl, 2273 .startup = atmel_startup, 2274 .shutdown = atmel_shutdown, 2275 .flush_buffer = atmel_flush_buffer, 2276 .set_termios = atmel_set_termios, 2277 .set_ldisc = atmel_set_ldisc, 2278 .type = atmel_type, 2279 .release_port = atmel_release_port, 2280 .request_port = atmel_request_port, 2281 .config_port = atmel_config_port, 2282 .verify_port = atmel_verify_port, 2283 .pm = atmel_serial_pm, 2284 #ifdef CONFIG_CONSOLE_POLL 2285 .poll_get_char = atmel_poll_get_char, 2286 .poll_put_char = atmel_poll_put_char, 2287 #endif 2288 }; 2289 2290 /* 2291 * Configure the port from the platform device resource info. 2292 */ 2293 static int atmel_init_port(struct atmel_uart_port *atmel_port, 2294 struct platform_device *pdev) 2295 { 2296 int ret; 2297 struct uart_port *port = &atmel_port->uart; 2298 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2299 2300 atmel_init_property(atmel_port, pdev); 2301 atmel_set_ops(port); 2302 2303 atmel_init_rs485(port, pdev); 2304 2305 port->iotype = UPIO_MEM; 2306 port->flags = UPF_BOOT_AUTOCONF; 2307 port->ops = &atmel_pops; 2308 port->fifosize = 1; 2309 port->dev = &pdev->dev; 2310 port->mapbase = pdev->resource[0].start; 2311 port->irq = pdev->resource[1].start; 2312 port->rs485_config = atmel_config_rs485; 2313 2314 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, 2315 (unsigned long)port); 2316 tasklet_disable(&atmel_port->tasklet); 2317 2318 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); 2319 2320 if (pdata && pdata->regs) { 2321 /* Already mapped by setup code */ 2322 port->membase = pdata->regs; 2323 } else { 2324 port->flags |= UPF_IOREMAP; 2325 port->membase = NULL; 2326 } 2327 2328 /* for console, the clock could already be configured */ 2329 if (!atmel_port->clk) { 2330 atmel_port->clk = clk_get(&pdev->dev, "usart"); 2331 if (IS_ERR(atmel_port->clk)) { 2332 ret = PTR_ERR(atmel_port->clk); 2333 atmel_port->clk = NULL; 2334 return ret; 2335 } 2336 ret = clk_prepare_enable(atmel_port->clk); 2337 if (ret) { 2338 clk_put(atmel_port->clk); 2339 atmel_port->clk = NULL; 2340 return ret; 2341 } 2342 port->uartclk = clk_get_rate(atmel_port->clk); 2343 clk_disable_unprepare(atmel_port->clk); 2344 /* only enable clock when USART is in use */ 2345 } 2346 2347 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ 2348 if (port->rs485.flags & SER_RS485_ENABLED) 2349 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 2350 else if (atmel_use_pdc_tx(port)) { 2351 port->fifosize = PDC_BUFFER_SIZE; 2352 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; 2353 } else { 2354 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 2355 } 2356 2357 return 0; 2358 } 2359 2360 struct platform_device *atmel_default_console_device; /* the serial console device */ 2361 2362 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2363 static void atmel_console_putchar(struct uart_port *port, int ch) 2364 { 2365 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) 2366 cpu_relax(); 2367 atmel_uart_write_char(port, ch); 2368 } 2369 2370 /* 2371 * Interrupts are disabled on entering 2372 */ 2373 static void atmel_console_write(struct console *co, const char *s, u_int count) 2374 { 2375 struct uart_port *port = &atmel_ports[co->index].uart; 2376 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2377 unsigned int status, imr; 2378 unsigned int pdc_tx; 2379 2380 /* 2381 * First, save IMR and then disable interrupts 2382 */ 2383 imr = atmel_uart_readl(port, ATMEL_US_IMR); 2384 atmel_uart_writel(port, ATMEL_US_IDR, 2385 ATMEL_US_RXRDY | atmel_port->tx_done_mask); 2386 2387 /* Store PDC transmit status and disable it */ 2388 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN; 2389 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 2390 2391 uart_console_write(port, s, count, atmel_console_putchar); 2392 2393 /* 2394 * Finally, wait for transmitter to become empty 2395 * and restore IMR 2396 */ 2397 do { 2398 status = atmel_uart_readl(port, ATMEL_US_CSR); 2399 } while (!(status & ATMEL_US_TXRDY)); 2400 2401 /* Restore PDC transmit status */ 2402 if (pdc_tx) 2403 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 2404 2405 /* set interrupts back the way they were */ 2406 atmel_uart_writel(port, ATMEL_US_IER, imr); 2407 } 2408 2409 /* 2410 * If the port was already initialised (eg, by a boot loader), 2411 * try to determine the current setup. 2412 */ 2413 static void __init atmel_console_get_options(struct uart_port *port, int *baud, 2414 int *parity, int *bits) 2415 { 2416 unsigned int mr, quot; 2417 2418 /* 2419 * If the baud rate generator isn't running, the port wasn't 2420 * initialized by the boot loader. 2421 */ 2422 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD; 2423 if (!quot) 2424 return; 2425 2426 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL; 2427 if (mr == ATMEL_US_CHRL_8) 2428 *bits = 8; 2429 else 2430 *bits = 7; 2431 2432 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR; 2433 if (mr == ATMEL_US_PAR_EVEN) 2434 *parity = 'e'; 2435 else if (mr == ATMEL_US_PAR_ODD) 2436 *parity = 'o'; 2437 2438 /* 2439 * The serial core only rounds down when matching this to a 2440 * supported baud rate. Make sure we don't end up slightly 2441 * lower than one of those, as it would make us fall through 2442 * to a much lower baud rate than we really want. 2443 */ 2444 *baud = port->uartclk / (16 * (quot - 1)); 2445 } 2446 2447 static int __init atmel_console_setup(struct console *co, char *options) 2448 { 2449 int ret; 2450 struct uart_port *port = &atmel_ports[co->index].uart; 2451 int baud = 115200; 2452 int bits = 8; 2453 int parity = 'n'; 2454 int flow = 'n'; 2455 2456 if (port->membase == NULL) { 2457 /* Port not initialized yet - delay setup */ 2458 return -ENODEV; 2459 } 2460 2461 ret = clk_prepare_enable(atmel_ports[co->index].clk); 2462 if (ret) 2463 return ret; 2464 2465 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2466 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2467 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 2468 2469 if (options) 2470 uart_parse_options(options, &baud, &parity, &bits, &flow); 2471 else 2472 atmel_console_get_options(port, &baud, &parity, &bits); 2473 2474 return uart_set_options(port, co, baud, parity, bits, flow); 2475 } 2476 2477 static struct uart_driver atmel_uart; 2478 2479 static struct console atmel_console = { 2480 .name = ATMEL_DEVICENAME, 2481 .write = atmel_console_write, 2482 .device = uart_console_device, 2483 .setup = atmel_console_setup, 2484 .flags = CON_PRINTBUFFER, 2485 .index = -1, 2486 .data = &atmel_uart, 2487 }; 2488 2489 #define ATMEL_CONSOLE_DEVICE (&atmel_console) 2490 2491 /* 2492 * Early console initialization (before VM subsystem initialized). 2493 */ 2494 static int __init atmel_console_init(void) 2495 { 2496 int ret; 2497 if (atmel_default_console_device) { 2498 struct atmel_uart_data *pdata = 2499 dev_get_platdata(&atmel_default_console_device->dev); 2500 int id = pdata->num; 2501 struct atmel_uart_port *atmel_port = &atmel_ports[id]; 2502 2503 atmel_port->backup_imr = 0; 2504 atmel_port->uart.line = id; 2505 2506 add_preferred_console(ATMEL_DEVICENAME, id, NULL); 2507 ret = atmel_init_port(atmel_port, atmel_default_console_device); 2508 if (ret) 2509 return ret; 2510 register_console(&atmel_console); 2511 } 2512 2513 return 0; 2514 } 2515 2516 console_initcall(atmel_console_init); 2517 2518 /* 2519 * Late console initialization. 2520 */ 2521 static int __init atmel_late_console_init(void) 2522 { 2523 if (atmel_default_console_device 2524 && !(atmel_console.flags & CON_ENABLED)) 2525 register_console(&atmel_console); 2526 2527 return 0; 2528 } 2529 2530 core_initcall(atmel_late_console_init); 2531 2532 static inline bool atmel_is_console_port(struct uart_port *port) 2533 { 2534 return port->cons && port->cons->index == port->line; 2535 } 2536 2537 #else 2538 #define ATMEL_CONSOLE_DEVICE NULL 2539 2540 static inline bool atmel_is_console_port(struct uart_port *port) 2541 { 2542 return false; 2543 } 2544 #endif 2545 2546 static struct uart_driver atmel_uart = { 2547 .owner = THIS_MODULE, 2548 .driver_name = "atmel_serial", 2549 .dev_name = ATMEL_DEVICENAME, 2550 .major = SERIAL_ATMEL_MAJOR, 2551 .minor = MINOR_START, 2552 .nr = ATMEL_MAX_UART, 2553 .cons = ATMEL_CONSOLE_DEVICE, 2554 }; 2555 2556 #ifdef CONFIG_PM 2557 static bool atmel_serial_clk_will_stop(void) 2558 { 2559 #ifdef CONFIG_ARCH_AT91 2560 return at91_suspend_entering_slow_clock(); 2561 #else 2562 return false; 2563 #endif 2564 } 2565 2566 static int atmel_serial_suspend(struct platform_device *pdev, 2567 pm_message_t state) 2568 { 2569 struct uart_port *port = platform_get_drvdata(pdev); 2570 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2571 2572 if (atmel_is_console_port(port) && console_suspend_enabled) { 2573 /* Drain the TX shifter */ 2574 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & 2575 ATMEL_US_TXEMPTY)) 2576 cpu_relax(); 2577 } 2578 2579 /* we can not wake up if we're running on slow clock */ 2580 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); 2581 if (atmel_serial_clk_will_stop()) { 2582 unsigned long flags; 2583 2584 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2585 atmel_port->suspended = true; 2586 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2587 device_set_wakeup_enable(&pdev->dev, 0); 2588 } 2589 2590 uart_suspend_port(&atmel_uart, port); 2591 2592 return 0; 2593 } 2594 2595 static int atmel_serial_resume(struct platform_device *pdev) 2596 { 2597 struct uart_port *port = platform_get_drvdata(pdev); 2598 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2599 unsigned long flags; 2600 2601 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2602 if (atmel_port->pending) { 2603 atmel_handle_receive(port, atmel_port->pending); 2604 atmel_handle_status(port, atmel_port->pending, 2605 atmel_port->pending_status); 2606 atmel_handle_transmit(port, atmel_port->pending); 2607 atmel_port->pending = 0; 2608 } 2609 atmel_port->suspended = false; 2610 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2611 2612 uart_resume_port(&atmel_uart, port); 2613 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); 2614 2615 return 0; 2616 } 2617 #else 2618 #define atmel_serial_suspend NULL 2619 #define atmel_serial_resume NULL 2620 #endif 2621 2622 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port, 2623 struct platform_device *pdev) 2624 { 2625 atmel_port->fifo_size = 0; 2626 atmel_port->rts_low = 0; 2627 atmel_port->rts_high = 0; 2628 2629 if (of_property_read_u32(pdev->dev.of_node, 2630 "atmel,fifo-size", 2631 &atmel_port->fifo_size)) 2632 return; 2633 2634 if (!atmel_port->fifo_size) 2635 return; 2636 2637 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) { 2638 atmel_port->fifo_size = 0; 2639 dev_err(&pdev->dev, "Invalid FIFO size\n"); 2640 return; 2641 } 2642 2643 /* 2644 * 0 <= rts_low <= rts_high <= fifo_size 2645 * Once their CTS line asserted by the remote peer, some x86 UARTs tend 2646 * to flush their internal TX FIFO, commonly up to 16 data, before 2647 * actually stopping to send new data. So we try to set the RTS High 2648 * Threshold to a reasonably high value respecting this 16 data 2649 * empirical rule when possible. 2650 */ 2651 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1, 2652 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET); 2653 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2, 2654 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET); 2655 2656 dev_info(&pdev->dev, "Using FIFO (%u data)\n", 2657 atmel_port->fifo_size); 2658 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n", 2659 atmel_port->rts_high); 2660 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n", 2661 atmel_port->rts_low); 2662 } 2663 2664 static int atmel_serial_probe(struct platform_device *pdev) 2665 { 2666 struct atmel_uart_port *atmel_port; 2667 struct device_node *np = pdev->dev.of_node; 2668 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2669 void *data; 2670 int ret = -ENODEV; 2671 bool rs485_enabled; 2672 2673 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); 2674 2675 if (np) 2676 ret = of_alias_get_id(np, "serial"); 2677 else 2678 if (pdata) 2679 ret = pdata->num; 2680 2681 if (ret < 0) 2682 /* port id not found in platform data nor device-tree aliases: 2683 * auto-enumerate it */ 2684 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); 2685 2686 if (ret >= ATMEL_MAX_UART) { 2687 ret = -ENODEV; 2688 goto err; 2689 } 2690 2691 if (test_and_set_bit(ret, atmel_ports_in_use)) { 2692 /* port already in use */ 2693 ret = -EBUSY; 2694 goto err; 2695 } 2696 2697 atmel_port = &atmel_ports[ret]; 2698 atmel_port->backup_imr = 0; 2699 atmel_port->uart.line = ret; 2700 atmel_serial_probe_fifos(atmel_port, pdev); 2701 2702 spin_lock_init(&atmel_port->lock_suspended); 2703 2704 ret = atmel_init_port(atmel_port, pdev); 2705 if (ret) 2706 goto err_clear_bit; 2707 2708 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0); 2709 if (IS_ERR(atmel_port->gpios)) { 2710 ret = PTR_ERR(atmel_port->gpios); 2711 goto err_clear_bit; 2712 } 2713 2714 if (!atmel_use_pdc_rx(&atmel_port->uart)) { 2715 ret = -ENOMEM; 2716 data = kmalloc(sizeof(struct atmel_uart_char) 2717 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); 2718 if (!data) 2719 goto err_alloc_ring; 2720 atmel_port->rx_ring.buf = data; 2721 } 2722 2723 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED; 2724 2725 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart); 2726 if (ret) 2727 goto err_add_port; 2728 2729 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2730 if (atmel_is_console_port(&atmel_port->uart) 2731 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { 2732 /* 2733 * The serial core enabled the clock for us, so undo 2734 * the clk_prepare_enable() in atmel_console_setup() 2735 */ 2736 clk_disable_unprepare(atmel_port->clk); 2737 } 2738 #endif 2739 2740 device_init_wakeup(&pdev->dev, 1); 2741 platform_set_drvdata(pdev, atmel_port); 2742 2743 /* 2744 * The peripheral clock has been disabled by atmel_init_port(): 2745 * enable it before accessing I/O registers 2746 */ 2747 clk_prepare_enable(atmel_port->clk); 2748 2749 if (rs485_enabled) { 2750 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR, 2751 ATMEL_US_USMODE_NORMAL); 2752 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR, 2753 ATMEL_US_RTSEN); 2754 } 2755 2756 /* 2757 * Get port name of usart or uart 2758 */ 2759 atmel_get_ip_name(&atmel_port->uart); 2760 2761 /* 2762 * The peripheral clock can now safely be disabled till the port 2763 * is used 2764 */ 2765 clk_disable_unprepare(atmel_port->clk); 2766 2767 return 0; 2768 2769 err_add_port: 2770 kfree(atmel_port->rx_ring.buf); 2771 atmel_port->rx_ring.buf = NULL; 2772 err_alloc_ring: 2773 if (!atmel_is_console_port(&atmel_port->uart)) { 2774 clk_put(atmel_port->clk); 2775 atmel_port->clk = NULL; 2776 } 2777 err_clear_bit: 2778 clear_bit(atmel_port->uart.line, atmel_ports_in_use); 2779 err: 2780 return ret; 2781 } 2782 2783 /* 2784 * Even if the driver is not modular, it makes sense to be able to 2785 * unbind a device: there can be many bound devices, and there are 2786 * situations where dynamic binding and unbinding can be useful. 2787 * 2788 * For example, a connected device can require a specific firmware update 2789 * protocol that needs bitbanging on IO lines, but use the regular serial 2790 * port in the normal case. 2791 */ 2792 static int atmel_serial_remove(struct platform_device *pdev) 2793 { 2794 struct uart_port *port = platform_get_drvdata(pdev); 2795 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2796 int ret = 0; 2797 2798 tasklet_kill(&atmel_port->tasklet); 2799 2800 device_init_wakeup(&pdev->dev, 0); 2801 2802 ret = uart_remove_one_port(&atmel_uart, port); 2803 2804 kfree(atmel_port->rx_ring.buf); 2805 2806 /* "port" is allocated statically, so we shouldn't free it */ 2807 2808 clear_bit(port->line, atmel_ports_in_use); 2809 2810 clk_put(atmel_port->clk); 2811 atmel_port->clk = NULL; 2812 2813 return ret; 2814 } 2815 2816 static struct platform_driver atmel_serial_driver = { 2817 .probe = atmel_serial_probe, 2818 .remove = atmel_serial_remove, 2819 .suspend = atmel_serial_suspend, 2820 .resume = atmel_serial_resume, 2821 .driver = { 2822 .name = "atmel_usart", 2823 .of_match_table = of_match_ptr(atmel_serial_dt_ids), 2824 }, 2825 }; 2826 2827 static int __init atmel_serial_init(void) 2828 { 2829 int ret; 2830 2831 ret = uart_register_driver(&atmel_uart); 2832 if (ret) 2833 return ret; 2834 2835 ret = platform_driver_register(&atmel_serial_driver); 2836 if (ret) 2837 uart_unregister_driver(&atmel_uart); 2838 2839 return ret; 2840 } 2841 device_initcall(atmel_serial_init); 2842