1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Atmel AT91 Serial ports 4 * Copyright (C) 2003 Rick Bronson 5 * 6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. 7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 8 * 9 * DMA support added by Chip Coldwell. 10 */ 11 #include <linux/tty.h> 12 #include <linux/ioport.h> 13 #include <linux/slab.h> 14 #include <linux/init.h> 15 #include <linux/serial.h> 16 #include <linux/clk.h> 17 #include <linux/console.h> 18 #include <linux/sysrq.h> 19 #include <linux/tty_flip.h> 20 #include <linux/platform_device.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/of_gpio.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/dmaengine.h> 26 #include <linux/atmel_pdc.h> 27 #include <linux/uaccess.h> 28 #include <linux/platform_data/atmel.h> 29 #include <linux/timer.h> 30 #include <linux/gpio.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/err.h> 33 #include <linux/irq.h> 34 #include <linux/suspend.h> 35 #include <linux/mm.h> 36 37 #include <asm/div64.h> 38 #include <asm/io.h> 39 #include <asm/ioctls.h> 40 41 #define PDC_BUFFER_SIZE 512 42 /* Revisit: We should calculate this based on the actual port settings */ 43 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ 44 45 /* The minium number of data FIFOs should be able to contain */ 46 #define ATMEL_MIN_FIFO_SIZE 8 47 /* 48 * These two offsets are substracted from the RX FIFO size to define the RTS 49 * high and low thresholds 50 */ 51 #define ATMEL_RTS_HIGH_OFFSET 16 52 #define ATMEL_RTS_LOW_OFFSET 20 53 54 #include <linux/serial_core.h> 55 56 #include "serial_mctrl_gpio.h" 57 #include "atmel_serial.h" 58 59 static void atmel_start_rx(struct uart_port *port); 60 static void atmel_stop_rx(struct uart_port *port); 61 62 #ifdef CONFIG_SERIAL_ATMEL_TTYAT 63 64 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we 65 * should coexist with the 8250 driver, such as if we have an external 16C550 66 * UART. */ 67 #define SERIAL_ATMEL_MAJOR 204 68 #define MINOR_START 154 69 #define ATMEL_DEVICENAME "ttyAT" 70 71 #else 72 73 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port 74 * name, but it is legally reserved for the 8250 driver. */ 75 #define SERIAL_ATMEL_MAJOR TTY_MAJOR 76 #define MINOR_START 64 77 #define ATMEL_DEVICENAME "ttyS" 78 79 #endif 80 81 #define ATMEL_ISR_PASS_LIMIT 256 82 83 struct atmel_dma_buffer { 84 unsigned char *buf; 85 dma_addr_t dma_addr; 86 unsigned int dma_size; 87 unsigned int ofs; 88 }; 89 90 struct atmel_uart_char { 91 u16 status; 92 u16 ch; 93 }; 94 95 /* 96 * Be careful, the real size of the ring buffer is 97 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer 98 * can contain up to 1024 characters in PIO mode and up to 4096 characters in 99 * DMA mode. 100 */ 101 #define ATMEL_SERIAL_RINGSIZE 1024 102 103 /* 104 * at91: 6 USARTs and one DBGU port (SAM9260) 105 * samx7: 3 USARTs and 5 UARTs 106 */ 107 #define ATMEL_MAX_UART 8 108 109 /* 110 * We wrap our port structure around the generic uart_port. 111 */ 112 struct atmel_uart_port { 113 struct uart_port uart; /* uart */ 114 struct clk *clk; /* uart clock */ 115 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ 116 u32 backup_imr; /* IMR saved during suspend */ 117 int break_active; /* break being received */ 118 119 bool use_dma_rx; /* enable DMA receiver */ 120 bool use_pdc_rx; /* enable PDC receiver */ 121 short pdc_rx_idx; /* current PDC RX buffer */ 122 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ 123 124 bool use_dma_tx; /* enable DMA transmitter */ 125 bool use_pdc_tx; /* enable PDC transmitter */ 126 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ 127 128 spinlock_t lock_tx; /* port lock */ 129 spinlock_t lock_rx; /* port lock */ 130 struct dma_chan *chan_tx; 131 struct dma_chan *chan_rx; 132 struct dma_async_tx_descriptor *desc_tx; 133 struct dma_async_tx_descriptor *desc_rx; 134 dma_cookie_t cookie_tx; 135 dma_cookie_t cookie_rx; 136 struct scatterlist sg_tx; 137 struct scatterlist sg_rx; 138 struct tasklet_struct tasklet_rx; 139 struct tasklet_struct tasklet_tx; 140 atomic_t tasklet_shutdown; 141 unsigned int irq_status_prev; 142 unsigned int tx_len; 143 144 struct circ_buf rx_ring; 145 146 struct mctrl_gpios *gpios; 147 u32 backup_mode; /* MR saved during iso7816 operations */ 148 u32 backup_brgr; /* BRGR saved during iso7816 operations */ 149 unsigned int tx_done_mask; 150 u32 fifo_size; 151 u32 rts_high; 152 u32 rts_low; 153 bool ms_irq_enabled; 154 u32 rtor; /* address of receiver timeout register if it exists */ 155 bool has_frac_baudrate; 156 bool has_hw_timer; 157 struct timer_list uart_timer; 158 159 bool tx_stopped; 160 bool suspended; 161 unsigned int pending; 162 unsigned int pending_status; 163 spinlock_t lock_suspended; 164 165 bool hd_start_rx; /* can start RX during half-duplex operation */ 166 167 /* ISO7816 */ 168 unsigned int fidi_min; 169 unsigned int fidi_max; 170 171 #ifdef CONFIG_PM 172 struct { 173 u32 cr; 174 u32 mr; 175 u32 imr; 176 u32 brgr; 177 u32 rtor; 178 u32 ttgr; 179 u32 fmr; 180 u32 fimr; 181 } cache; 182 #endif 183 184 int (*prepare_rx)(struct uart_port *port); 185 int (*prepare_tx)(struct uart_port *port); 186 void (*schedule_rx)(struct uart_port *port); 187 void (*schedule_tx)(struct uart_port *port); 188 void (*release_rx)(struct uart_port *port); 189 void (*release_tx)(struct uart_port *port); 190 }; 191 192 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; 193 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); 194 195 #if defined(CONFIG_OF) 196 static const struct of_device_id atmel_serial_dt_ids[] = { 197 { .compatible = "atmel,at91rm9200-usart-serial" }, 198 { /* sentinel */ } 199 }; 200 #endif 201 202 static inline struct atmel_uart_port * 203 to_atmel_uart_port(struct uart_port *uart) 204 { 205 return container_of(uart, struct atmel_uart_port, uart); 206 } 207 208 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg) 209 { 210 return __raw_readl(port->membase + reg); 211 } 212 213 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value) 214 { 215 __raw_writel(value, port->membase + reg); 216 } 217 218 static inline u8 atmel_uart_read_char(struct uart_port *port) 219 { 220 return __raw_readb(port->membase + ATMEL_US_RHR); 221 } 222 223 static inline void atmel_uart_write_char(struct uart_port *port, u8 value) 224 { 225 __raw_writeb(value, port->membase + ATMEL_US_THR); 226 } 227 228 static inline int atmel_uart_is_half_duplex(struct uart_port *port) 229 { 230 return ((port->rs485.flags & SER_RS485_ENABLED) && 231 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) || 232 (port->iso7816.flags & SER_ISO7816_ENABLED); 233 } 234 235 #ifdef CONFIG_SERIAL_ATMEL_PDC 236 static bool atmel_use_pdc_rx(struct uart_port *port) 237 { 238 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 239 240 return atmel_port->use_pdc_rx; 241 } 242 243 static bool atmel_use_pdc_tx(struct uart_port *port) 244 { 245 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 246 247 return atmel_port->use_pdc_tx; 248 } 249 #else 250 static bool atmel_use_pdc_rx(struct uart_port *port) 251 { 252 return false; 253 } 254 255 static bool atmel_use_pdc_tx(struct uart_port *port) 256 { 257 return false; 258 } 259 #endif 260 261 static bool atmel_use_dma_tx(struct uart_port *port) 262 { 263 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 264 265 return atmel_port->use_dma_tx; 266 } 267 268 static bool atmel_use_dma_rx(struct uart_port *port) 269 { 270 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 271 272 return atmel_port->use_dma_rx; 273 } 274 275 static bool atmel_use_fifo(struct uart_port *port) 276 { 277 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 278 279 return atmel_port->fifo_size; 280 } 281 282 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port, 283 struct tasklet_struct *t) 284 { 285 if (!atomic_read(&atmel_port->tasklet_shutdown)) 286 tasklet_schedule(t); 287 } 288 289 /* Enable or disable the rs485 support */ 290 static int atmel_config_rs485(struct uart_port *port, 291 struct serial_rs485 *rs485conf) 292 { 293 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 294 unsigned int mode; 295 296 /* Disable interrupts */ 297 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); 298 299 mode = atmel_uart_readl(port, ATMEL_US_MR); 300 301 /* Resetting serial mode to RS232 (0x0) */ 302 mode &= ~ATMEL_US_USMODE; 303 304 port->rs485 = *rs485conf; 305 306 if (rs485conf->flags & SER_RS485_ENABLED) { 307 dev_dbg(port->dev, "Setting UART to RS485\n"); 308 if (port->rs485.flags & SER_RS485_RX_DURING_TX) 309 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 310 else 311 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 312 313 atmel_uart_writel(port, ATMEL_US_TTGR, 314 rs485conf->delay_rts_after_send); 315 mode |= ATMEL_US_USMODE_RS485; 316 } else { 317 dev_dbg(port->dev, "Setting UART to RS232\n"); 318 if (atmel_use_pdc_tx(port)) 319 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 320 ATMEL_US_TXBUFE; 321 else 322 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 323 } 324 atmel_uart_writel(port, ATMEL_US_MR, mode); 325 326 /* Enable interrupts */ 327 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 328 329 return 0; 330 } 331 332 static unsigned int atmel_calc_cd(struct uart_port *port, 333 struct serial_iso7816 *iso7816conf) 334 { 335 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 336 unsigned int cd; 337 u64 mck_rate; 338 339 mck_rate = (u64)clk_get_rate(atmel_port->clk); 340 do_div(mck_rate, iso7816conf->clk); 341 cd = mck_rate; 342 return cd; 343 } 344 345 static unsigned int atmel_calc_fidi(struct uart_port *port, 346 struct serial_iso7816 *iso7816conf) 347 { 348 u64 fidi = 0; 349 350 if (iso7816conf->sc_fi && iso7816conf->sc_di) { 351 fidi = (u64)iso7816conf->sc_fi; 352 do_div(fidi, iso7816conf->sc_di); 353 } 354 return (u32)fidi; 355 } 356 357 /* Enable or disable the iso7816 support */ 358 /* Called with interrupts disabled */ 359 static int atmel_config_iso7816(struct uart_port *port, 360 struct serial_iso7816 *iso7816conf) 361 { 362 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 363 unsigned int mode; 364 unsigned int cd, fidi; 365 int ret = 0; 366 367 /* Disable interrupts */ 368 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); 369 370 mode = atmel_uart_readl(port, ATMEL_US_MR); 371 372 if (iso7816conf->flags & SER_ISO7816_ENABLED) { 373 mode &= ~ATMEL_US_USMODE; 374 375 if (iso7816conf->tg > 255) { 376 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n"); 377 memset(iso7816conf, 0, sizeof(struct serial_iso7816)); 378 ret = -EINVAL; 379 goto err_out; 380 } 381 382 if ((iso7816conf->flags & SER_ISO7816_T_PARAM) 383 == SER_ISO7816_T(0)) { 384 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK; 385 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM) 386 == SER_ISO7816_T(1)) { 387 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK; 388 } else { 389 dev_err(port->dev, "ISO7816: Type not supported\n"); 390 memset(iso7816conf, 0, sizeof(struct serial_iso7816)); 391 ret = -EINVAL; 392 goto err_out; 393 } 394 395 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR); 396 397 /* select mck clock, and output */ 398 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO; 399 /* set parity for normal/inverse mode + max iterations */ 400 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3); 401 402 cd = atmel_calc_cd(port, iso7816conf); 403 fidi = atmel_calc_fidi(port, iso7816conf); 404 if (fidi == 0) { 405 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n"); 406 } else if (fidi < atmel_port->fidi_min 407 || fidi > atmel_port->fidi_max) { 408 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi); 409 memset(iso7816conf, 0, sizeof(struct serial_iso7816)); 410 ret = -EINVAL; 411 goto err_out; 412 } 413 414 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) { 415 /* port not yet in iso7816 mode: store configuration */ 416 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR); 417 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR); 418 } 419 420 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg); 421 atmel_uart_writel(port, ATMEL_US_BRGR, cd); 422 atmel_uart_writel(port, ATMEL_US_FIDI, fidi); 423 424 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN); 425 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION; 426 } else { 427 dev_dbg(port->dev, "Setting UART back to RS232\n"); 428 /* back to last RS232 settings */ 429 mode = atmel_port->backup_mode; 430 memset(iso7816conf, 0, sizeof(struct serial_iso7816)); 431 atmel_uart_writel(port, ATMEL_US_TTGR, 0); 432 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr); 433 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174); 434 435 if (atmel_use_pdc_tx(port)) 436 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 437 ATMEL_US_TXBUFE; 438 else 439 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 440 } 441 442 port->iso7816 = *iso7816conf; 443 444 atmel_uart_writel(port, ATMEL_US_MR, mode); 445 446 err_out: 447 /* Enable interrupts */ 448 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 449 450 return ret; 451 } 452 453 /* 454 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. 455 */ 456 static u_int atmel_tx_empty(struct uart_port *port) 457 { 458 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 459 460 if (atmel_port->tx_stopped) 461 return TIOCSER_TEMT; 462 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ? 463 TIOCSER_TEMT : 464 0; 465 } 466 467 /* 468 * Set state of the modem control output lines 469 */ 470 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) 471 { 472 unsigned int control = 0; 473 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR); 474 unsigned int rts_paused, rts_ready; 475 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 476 477 /* override mode to RS485 if needed, otherwise keep the current mode */ 478 if (port->rs485.flags & SER_RS485_ENABLED) { 479 atmel_uart_writel(port, ATMEL_US_TTGR, 480 port->rs485.delay_rts_after_send); 481 mode &= ~ATMEL_US_USMODE; 482 mode |= ATMEL_US_USMODE_RS485; 483 } 484 485 /* set the RTS line state according to the mode */ 486 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 487 /* force RTS line to high level */ 488 rts_paused = ATMEL_US_RTSEN; 489 490 /* give the control of the RTS line back to the hardware */ 491 rts_ready = ATMEL_US_RTSDIS; 492 } else { 493 /* force RTS line to high level */ 494 rts_paused = ATMEL_US_RTSDIS; 495 496 /* force RTS line to low level */ 497 rts_ready = ATMEL_US_RTSEN; 498 } 499 500 if (mctrl & TIOCM_RTS) 501 control |= rts_ready; 502 else 503 control |= rts_paused; 504 505 if (mctrl & TIOCM_DTR) 506 control |= ATMEL_US_DTREN; 507 else 508 control |= ATMEL_US_DTRDIS; 509 510 atmel_uart_writel(port, ATMEL_US_CR, control); 511 512 mctrl_gpio_set(atmel_port->gpios, mctrl); 513 514 /* Local loopback mode? */ 515 mode &= ~ATMEL_US_CHMODE; 516 if (mctrl & TIOCM_LOOP) 517 mode |= ATMEL_US_CHMODE_LOC_LOOP; 518 else 519 mode |= ATMEL_US_CHMODE_NORMAL; 520 521 atmel_uart_writel(port, ATMEL_US_MR, mode); 522 } 523 524 /* 525 * Get state of the modem control input lines 526 */ 527 static u_int atmel_get_mctrl(struct uart_port *port) 528 { 529 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 530 unsigned int ret = 0, status; 531 532 status = atmel_uart_readl(port, ATMEL_US_CSR); 533 534 /* 535 * The control signals are active low. 536 */ 537 if (!(status & ATMEL_US_DCD)) 538 ret |= TIOCM_CD; 539 if (!(status & ATMEL_US_CTS)) 540 ret |= TIOCM_CTS; 541 if (!(status & ATMEL_US_DSR)) 542 ret |= TIOCM_DSR; 543 if (!(status & ATMEL_US_RI)) 544 ret |= TIOCM_RI; 545 546 return mctrl_gpio_get(atmel_port->gpios, &ret); 547 } 548 549 /* 550 * Stop transmitting. 551 */ 552 static void atmel_stop_tx(struct uart_port *port) 553 { 554 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 555 556 if (atmel_use_pdc_tx(port)) { 557 /* disable PDC transmit */ 558 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 559 } 560 561 /* 562 * Disable the transmitter. 563 * This is mandatory when DMA is used, otherwise the DMA buffer 564 * is fully transmitted. 565 */ 566 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS); 567 atmel_port->tx_stopped = true; 568 569 /* Disable interrupts */ 570 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); 571 572 if (atmel_uart_is_half_duplex(port)) 573 if (!atomic_read(&atmel_port->tasklet_shutdown)) 574 atmel_start_rx(port); 575 576 } 577 578 /* 579 * Start transmitting. 580 */ 581 static void atmel_start_tx(struct uart_port *port) 582 { 583 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 584 585 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR) 586 & ATMEL_PDC_TXTEN)) 587 /* The transmitter is already running. Yes, we 588 really need this.*/ 589 return; 590 591 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port)) 592 if (atmel_uart_is_half_duplex(port)) 593 atmel_stop_rx(port); 594 595 if (atmel_use_pdc_tx(port)) 596 /* re-enable PDC transmit */ 597 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 598 599 /* Enable interrupts */ 600 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 601 602 /* re-enable the transmitter */ 603 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN); 604 atmel_port->tx_stopped = false; 605 } 606 607 /* 608 * start receiving - port is in process of being opened. 609 */ 610 static void atmel_start_rx(struct uart_port *port) 611 { 612 /* reset status and receiver */ 613 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 614 615 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN); 616 617 if (atmel_use_pdc_rx(port)) { 618 /* enable PDC controller */ 619 atmel_uart_writel(port, ATMEL_US_IER, 620 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 621 port->read_status_mask); 622 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 623 } else { 624 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY); 625 } 626 } 627 628 /* 629 * Stop receiving - port is in process of being closed. 630 */ 631 static void atmel_stop_rx(struct uart_port *port) 632 { 633 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS); 634 635 if (atmel_use_pdc_rx(port)) { 636 /* disable PDC receive */ 637 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS); 638 atmel_uart_writel(port, ATMEL_US_IDR, 639 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 640 port->read_status_mask); 641 } else { 642 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY); 643 } 644 } 645 646 /* 647 * Enable modem status interrupts 648 */ 649 static void atmel_enable_ms(struct uart_port *port) 650 { 651 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 652 uint32_t ier = 0; 653 654 /* 655 * Interrupt should not be enabled twice 656 */ 657 if (atmel_port->ms_irq_enabled) 658 return; 659 660 atmel_port->ms_irq_enabled = true; 661 662 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) 663 ier |= ATMEL_US_CTSIC; 664 665 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR)) 666 ier |= ATMEL_US_DSRIC; 667 668 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI)) 669 ier |= ATMEL_US_RIIC; 670 671 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD)) 672 ier |= ATMEL_US_DCDIC; 673 674 atmel_uart_writel(port, ATMEL_US_IER, ier); 675 676 mctrl_gpio_enable_ms(atmel_port->gpios); 677 } 678 679 /* 680 * Disable modem status interrupts 681 */ 682 static void atmel_disable_ms(struct uart_port *port) 683 { 684 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 685 uint32_t idr = 0; 686 687 /* 688 * Interrupt should not be disabled twice 689 */ 690 if (!atmel_port->ms_irq_enabled) 691 return; 692 693 atmel_port->ms_irq_enabled = false; 694 695 mctrl_gpio_disable_ms(atmel_port->gpios); 696 697 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) 698 idr |= ATMEL_US_CTSIC; 699 700 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR)) 701 idr |= ATMEL_US_DSRIC; 702 703 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI)) 704 idr |= ATMEL_US_RIIC; 705 706 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD)) 707 idr |= ATMEL_US_DCDIC; 708 709 atmel_uart_writel(port, ATMEL_US_IDR, idr); 710 } 711 712 /* 713 * Control the transmission of a break signal 714 */ 715 static void atmel_break_ctl(struct uart_port *port, int break_state) 716 { 717 if (break_state != 0) 718 /* start break */ 719 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK); 720 else 721 /* stop break */ 722 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK); 723 } 724 725 /* 726 * Stores the incoming character in the ring buffer 727 */ 728 static void 729 atmel_buffer_rx_char(struct uart_port *port, unsigned int status, 730 unsigned int ch) 731 { 732 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 733 struct circ_buf *ring = &atmel_port->rx_ring; 734 struct atmel_uart_char *c; 735 736 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) 737 /* Buffer overflow, ignore char */ 738 return; 739 740 c = &((struct atmel_uart_char *)ring->buf)[ring->head]; 741 c->status = status; 742 c->ch = ch; 743 744 /* Make sure the character is stored before we update head. */ 745 smp_wmb(); 746 747 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 748 } 749 750 /* 751 * Deal with parity, framing and overrun errors. 752 */ 753 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) 754 { 755 /* clear error */ 756 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 757 758 if (status & ATMEL_US_RXBRK) { 759 /* ignore side-effect */ 760 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 761 port->icount.brk++; 762 } 763 if (status & ATMEL_US_PARE) 764 port->icount.parity++; 765 if (status & ATMEL_US_FRAME) 766 port->icount.frame++; 767 if (status & ATMEL_US_OVRE) 768 port->icount.overrun++; 769 } 770 771 /* 772 * Characters received (called from interrupt handler) 773 */ 774 static void atmel_rx_chars(struct uart_port *port) 775 { 776 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 777 unsigned int status, ch; 778 779 status = atmel_uart_readl(port, ATMEL_US_CSR); 780 while (status & ATMEL_US_RXRDY) { 781 ch = atmel_uart_read_char(port); 782 783 /* 784 * note that the error handling code is 785 * out of the main execution path 786 */ 787 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 788 | ATMEL_US_OVRE | ATMEL_US_RXBRK) 789 || atmel_port->break_active)) { 790 791 /* clear error */ 792 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 793 794 if (status & ATMEL_US_RXBRK 795 && !atmel_port->break_active) { 796 atmel_port->break_active = 1; 797 atmel_uart_writel(port, ATMEL_US_IER, 798 ATMEL_US_RXBRK); 799 } else { 800 /* 801 * This is either the end-of-break 802 * condition or we've received at 803 * least one character without RXBRK 804 * being set. In both cases, the next 805 * RXBRK will indicate start-of-break. 806 */ 807 atmel_uart_writel(port, ATMEL_US_IDR, 808 ATMEL_US_RXBRK); 809 status &= ~ATMEL_US_RXBRK; 810 atmel_port->break_active = 0; 811 } 812 } 813 814 atmel_buffer_rx_char(port, status, ch); 815 status = atmel_uart_readl(port, ATMEL_US_CSR); 816 } 817 818 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx); 819 } 820 821 /* 822 * Transmit characters (called from tasklet with TXRDY interrupt 823 * disabled) 824 */ 825 static void atmel_tx_chars(struct uart_port *port) 826 { 827 struct circ_buf *xmit = &port->state->xmit; 828 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 829 830 if (port->x_char && 831 (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) { 832 atmel_uart_write_char(port, port->x_char); 833 port->icount.tx++; 834 port->x_char = 0; 835 } 836 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 837 return; 838 839 while (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY) { 840 atmel_uart_write_char(port, xmit->buf[xmit->tail]); 841 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 842 port->icount.tx++; 843 if (uart_circ_empty(xmit)) 844 break; 845 } 846 847 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 848 uart_write_wakeup(port); 849 850 if (!uart_circ_empty(xmit)) { 851 /* we still have characters to transmit, so we should continue 852 * transmitting them when TX is ready, regardless of 853 * mode or duplexity 854 */ 855 atmel_port->tx_done_mask |= ATMEL_US_TXRDY; 856 857 /* Enable interrupts */ 858 atmel_uart_writel(port, ATMEL_US_IER, 859 atmel_port->tx_done_mask); 860 } else { 861 if (atmel_uart_is_half_duplex(port)) 862 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY; 863 } 864 } 865 866 static void atmel_complete_tx_dma(void *arg) 867 { 868 struct atmel_uart_port *atmel_port = arg; 869 struct uart_port *port = &atmel_port->uart; 870 struct circ_buf *xmit = &port->state->xmit; 871 struct dma_chan *chan = atmel_port->chan_tx; 872 unsigned long flags; 873 874 spin_lock_irqsave(&port->lock, flags); 875 876 if (chan) 877 dmaengine_terminate_all(chan); 878 xmit->tail += atmel_port->tx_len; 879 xmit->tail &= UART_XMIT_SIZE - 1; 880 881 port->icount.tx += atmel_port->tx_len; 882 883 spin_lock_irq(&atmel_port->lock_tx); 884 async_tx_ack(atmel_port->desc_tx); 885 atmel_port->cookie_tx = -EINVAL; 886 atmel_port->desc_tx = NULL; 887 spin_unlock_irq(&atmel_port->lock_tx); 888 889 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 890 uart_write_wakeup(port); 891 892 /* 893 * xmit is a circular buffer so, if we have just send data from 894 * xmit->tail to the end of xmit->buf, now we have to transmit the 895 * remaining data from the beginning of xmit->buf to xmit->head. 896 */ 897 if (!uart_circ_empty(xmit)) 898 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx); 899 else if (atmel_uart_is_half_duplex(port)) { 900 /* 901 * DMA done, re-enable TXEMPTY and signal that we can stop 902 * TX and start RX for RS485 903 */ 904 atmel_port->hd_start_rx = true; 905 atmel_uart_writel(port, ATMEL_US_IER, 906 atmel_port->tx_done_mask); 907 } 908 909 spin_unlock_irqrestore(&port->lock, flags); 910 } 911 912 static void atmel_release_tx_dma(struct uart_port *port) 913 { 914 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 915 struct dma_chan *chan = atmel_port->chan_tx; 916 917 if (chan) { 918 dmaengine_terminate_all(chan); 919 dma_release_channel(chan); 920 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, 921 DMA_TO_DEVICE); 922 } 923 924 atmel_port->desc_tx = NULL; 925 atmel_port->chan_tx = NULL; 926 atmel_port->cookie_tx = -EINVAL; 927 } 928 929 /* 930 * Called from tasklet with TXRDY interrupt is disabled. 931 */ 932 static void atmel_tx_dma(struct uart_port *port) 933 { 934 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 935 struct circ_buf *xmit = &port->state->xmit; 936 struct dma_chan *chan = atmel_port->chan_tx; 937 struct dma_async_tx_descriptor *desc; 938 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx; 939 unsigned int tx_len, part1_len, part2_len, sg_len; 940 dma_addr_t phys_addr; 941 942 /* Make sure we have an idle channel */ 943 if (atmel_port->desc_tx != NULL) 944 return; 945 946 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 947 /* 948 * DMA is idle now. 949 * Port xmit buffer is already mapped, 950 * and it is one page... Just adjust 951 * offsets and lengths. Since it is a circular buffer, 952 * we have to transmit till the end, and then the rest. 953 * Take the port lock to get a 954 * consistent xmit buffer state. 955 */ 956 tx_len = CIRC_CNT_TO_END(xmit->head, 957 xmit->tail, 958 UART_XMIT_SIZE); 959 960 if (atmel_port->fifo_size) { 961 /* multi data mode */ 962 part1_len = (tx_len & ~0x3); /* DWORD access */ 963 part2_len = (tx_len & 0x3); /* BYTE access */ 964 } else { 965 /* single data (legacy) mode */ 966 part1_len = 0; 967 part2_len = tx_len; /* BYTE access only */ 968 } 969 970 sg_init_table(sgl, 2); 971 sg_len = 0; 972 phys_addr = sg_dma_address(sg_tx) + xmit->tail; 973 if (part1_len) { 974 sg = &sgl[sg_len++]; 975 sg_dma_address(sg) = phys_addr; 976 sg_dma_len(sg) = part1_len; 977 978 phys_addr += part1_len; 979 } 980 981 if (part2_len) { 982 sg = &sgl[sg_len++]; 983 sg_dma_address(sg) = phys_addr; 984 sg_dma_len(sg) = part2_len; 985 } 986 987 /* 988 * save tx_len so atmel_complete_tx_dma() will increase 989 * xmit->tail correctly 990 */ 991 atmel_port->tx_len = tx_len; 992 993 desc = dmaengine_prep_slave_sg(chan, 994 sgl, 995 sg_len, 996 DMA_MEM_TO_DEV, 997 DMA_PREP_INTERRUPT | 998 DMA_CTRL_ACK); 999 if (!desc) { 1000 dev_err(port->dev, "Failed to send via dma!\n"); 1001 return; 1002 } 1003 1004 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE); 1005 1006 atmel_port->desc_tx = desc; 1007 desc->callback = atmel_complete_tx_dma; 1008 desc->callback_param = atmel_port; 1009 atmel_port->cookie_tx = dmaengine_submit(desc); 1010 } 1011 1012 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1013 uart_write_wakeup(port); 1014 } 1015 1016 static int atmel_prepare_tx_dma(struct uart_port *port) 1017 { 1018 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1019 struct device *mfd_dev = port->dev->parent; 1020 dma_cap_mask_t mask; 1021 struct dma_slave_config config; 1022 int ret, nent; 1023 1024 dma_cap_zero(mask); 1025 dma_cap_set(DMA_SLAVE, mask); 1026 1027 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx"); 1028 if (atmel_port->chan_tx == NULL) 1029 goto chan_err; 1030 dev_info(port->dev, "using %s for tx DMA transfers\n", 1031 dma_chan_name(atmel_port->chan_tx)); 1032 1033 spin_lock_init(&atmel_port->lock_tx); 1034 sg_init_table(&atmel_port->sg_tx, 1); 1035 /* UART circular tx buffer is an aligned page. */ 1036 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf)); 1037 sg_set_page(&atmel_port->sg_tx, 1038 virt_to_page(port->state->xmit.buf), 1039 UART_XMIT_SIZE, 1040 offset_in_page(port->state->xmit.buf)); 1041 nent = dma_map_sg(port->dev, 1042 &atmel_port->sg_tx, 1043 1, 1044 DMA_TO_DEVICE); 1045 1046 if (!nent) { 1047 dev_dbg(port->dev, "need to release resource of dma\n"); 1048 goto chan_err; 1049 } else { 1050 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, 1051 sg_dma_len(&atmel_port->sg_tx), 1052 port->state->xmit.buf, 1053 &sg_dma_address(&atmel_port->sg_tx)); 1054 } 1055 1056 /* Configure the slave DMA */ 1057 memset(&config, 0, sizeof(config)); 1058 config.direction = DMA_MEM_TO_DEV; 1059 config.dst_addr_width = (atmel_port->fifo_size) ? 1060 DMA_SLAVE_BUSWIDTH_4_BYTES : 1061 DMA_SLAVE_BUSWIDTH_1_BYTE; 1062 config.dst_addr = port->mapbase + ATMEL_US_THR; 1063 config.dst_maxburst = 1; 1064 1065 ret = dmaengine_slave_config(atmel_port->chan_tx, 1066 &config); 1067 if (ret) { 1068 dev_err(port->dev, "DMA tx slave configuration failed\n"); 1069 goto chan_err; 1070 } 1071 1072 return 0; 1073 1074 chan_err: 1075 dev_err(port->dev, "TX channel not available, switch to pio\n"); 1076 atmel_port->use_dma_tx = false; 1077 if (atmel_port->chan_tx) 1078 atmel_release_tx_dma(port); 1079 return -EINVAL; 1080 } 1081 1082 static void atmel_complete_rx_dma(void *arg) 1083 { 1084 struct uart_port *port = arg; 1085 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1086 1087 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx); 1088 } 1089 1090 static void atmel_release_rx_dma(struct uart_port *port) 1091 { 1092 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1093 struct dma_chan *chan = atmel_port->chan_rx; 1094 1095 if (chan) { 1096 dmaengine_terminate_all(chan); 1097 dma_release_channel(chan); 1098 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, 1099 DMA_FROM_DEVICE); 1100 } 1101 1102 atmel_port->desc_rx = NULL; 1103 atmel_port->chan_rx = NULL; 1104 atmel_port->cookie_rx = -EINVAL; 1105 } 1106 1107 static void atmel_rx_from_dma(struct uart_port *port) 1108 { 1109 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1110 struct tty_port *tport = &port->state->port; 1111 struct circ_buf *ring = &atmel_port->rx_ring; 1112 struct dma_chan *chan = atmel_port->chan_rx; 1113 struct dma_tx_state state; 1114 enum dma_status dmastat; 1115 size_t count; 1116 1117 1118 /* Reset the UART timeout early so that we don't miss one */ 1119 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1120 dmastat = dmaengine_tx_status(chan, 1121 atmel_port->cookie_rx, 1122 &state); 1123 /* Restart a new tasklet if DMA status is error */ 1124 if (dmastat == DMA_ERROR) { 1125 dev_dbg(port->dev, "Get residue error, restart tasklet\n"); 1126 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT); 1127 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx); 1128 return; 1129 } 1130 1131 /* CPU claims ownership of RX DMA buffer */ 1132 dma_sync_sg_for_cpu(port->dev, 1133 &atmel_port->sg_rx, 1134 1, 1135 DMA_FROM_DEVICE); 1136 1137 /* 1138 * ring->head points to the end of data already written by the DMA. 1139 * ring->tail points to the beginning of data to be read by the 1140 * framework. 1141 * The current transfer size should not be larger than the dma buffer 1142 * length. 1143 */ 1144 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue; 1145 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx)); 1146 /* 1147 * At this point ring->head may point to the first byte right after the 1148 * last byte of the dma buffer: 1149 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx) 1150 * 1151 * However ring->tail must always points inside the dma buffer: 1152 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1 1153 * 1154 * Since we use a ring buffer, we have to handle the case 1155 * where head is lower than tail. In such a case, we first read from 1156 * tail to the end of the buffer then reset tail. 1157 */ 1158 if (ring->head < ring->tail) { 1159 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail; 1160 1161 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 1162 ring->tail = 0; 1163 port->icount.rx += count; 1164 } 1165 1166 /* Finally we read data from tail to head */ 1167 if (ring->tail < ring->head) { 1168 count = ring->head - ring->tail; 1169 1170 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 1171 /* Wrap ring->head if needed */ 1172 if (ring->head >= sg_dma_len(&atmel_port->sg_rx)) 1173 ring->head = 0; 1174 ring->tail = ring->head; 1175 port->icount.rx += count; 1176 } 1177 1178 /* USART retreives ownership of RX DMA buffer */ 1179 dma_sync_sg_for_device(port->dev, 1180 &atmel_port->sg_rx, 1181 1, 1182 DMA_FROM_DEVICE); 1183 1184 /* 1185 * Drop the lock here since it might end up calling 1186 * uart_start(), which takes the lock. 1187 */ 1188 spin_unlock(&port->lock); 1189 tty_flip_buffer_push(tport); 1190 spin_lock(&port->lock); 1191 1192 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT); 1193 } 1194 1195 static int atmel_prepare_rx_dma(struct uart_port *port) 1196 { 1197 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1198 struct device *mfd_dev = port->dev->parent; 1199 struct dma_async_tx_descriptor *desc; 1200 dma_cap_mask_t mask; 1201 struct dma_slave_config config; 1202 struct circ_buf *ring; 1203 int ret, nent; 1204 1205 ring = &atmel_port->rx_ring; 1206 1207 dma_cap_zero(mask); 1208 dma_cap_set(DMA_CYCLIC, mask); 1209 1210 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx"); 1211 if (atmel_port->chan_rx == NULL) 1212 goto chan_err; 1213 dev_info(port->dev, "using %s for rx DMA transfers\n", 1214 dma_chan_name(atmel_port->chan_rx)); 1215 1216 spin_lock_init(&atmel_port->lock_rx); 1217 sg_init_table(&atmel_port->sg_rx, 1); 1218 /* UART circular rx buffer is an aligned page. */ 1219 BUG_ON(!PAGE_ALIGNED(ring->buf)); 1220 sg_set_page(&atmel_port->sg_rx, 1221 virt_to_page(ring->buf), 1222 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE, 1223 offset_in_page(ring->buf)); 1224 nent = dma_map_sg(port->dev, 1225 &atmel_port->sg_rx, 1226 1, 1227 DMA_FROM_DEVICE); 1228 1229 if (!nent) { 1230 dev_dbg(port->dev, "need to release resource of dma\n"); 1231 goto chan_err; 1232 } else { 1233 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, 1234 sg_dma_len(&atmel_port->sg_rx), 1235 ring->buf, 1236 &sg_dma_address(&atmel_port->sg_rx)); 1237 } 1238 1239 /* Configure the slave DMA */ 1240 memset(&config, 0, sizeof(config)); 1241 config.direction = DMA_DEV_TO_MEM; 1242 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1243 config.src_addr = port->mapbase + ATMEL_US_RHR; 1244 config.src_maxburst = 1; 1245 1246 ret = dmaengine_slave_config(atmel_port->chan_rx, 1247 &config); 1248 if (ret) { 1249 dev_err(port->dev, "DMA rx slave configuration failed\n"); 1250 goto chan_err; 1251 } 1252 /* 1253 * Prepare a cyclic dma transfer, assign 2 descriptors, 1254 * each one is half ring buffer size 1255 */ 1256 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, 1257 sg_dma_address(&atmel_port->sg_rx), 1258 sg_dma_len(&atmel_port->sg_rx), 1259 sg_dma_len(&atmel_port->sg_rx)/2, 1260 DMA_DEV_TO_MEM, 1261 DMA_PREP_INTERRUPT); 1262 if (!desc) { 1263 dev_err(port->dev, "Preparing DMA cyclic failed\n"); 1264 goto chan_err; 1265 } 1266 desc->callback = atmel_complete_rx_dma; 1267 desc->callback_param = port; 1268 atmel_port->desc_rx = desc; 1269 atmel_port->cookie_rx = dmaengine_submit(desc); 1270 1271 return 0; 1272 1273 chan_err: 1274 dev_err(port->dev, "RX channel not available, switch to pio\n"); 1275 atmel_port->use_dma_rx = false; 1276 if (atmel_port->chan_rx) 1277 atmel_release_rx_dma(port); 1278 return -EINVAL; 1279 } 1280 1281 static void atmel_uart_timer_callback(struct timer_list *t) 1282 { 1283 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t, 1284 uart_timer); 1285 struct uart_port *port = &atmel_port->uart; 1286 1287 if (!atomic_read(&atmel_port->tasklet_shutdown)) { 1288 tasklet_schedule(&atmel_port->tasklet_rx); 1289 mod_timer(&atmel_port->uart_timer, 1290 jiffies + uart_poll_timeout(port)); 1291 } 1292 } 1293 1294 /* 1295 * receive interrupt handler. 1296 */ 1297 static void 1298 atmel_handle_receive(struct uart_port *port, unsigned int pending) 1299 { 1300 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1301 1302 if (atmel_use_pdc_rx(port)) { 1303 /* 1304 * PDC receive. Just schedule the tasklet and let it 1305 * figure out the details. 1306 * 1307 * TODO: We're not handling error flags correctly at 1308 * the moment. 1309 */ 1310 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { 1311 atmel_uart_writel(port, ATMEL_US_IDR, 1312 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)); 1313 atmel_tasklet_schedule(atmel_port, 1314 &atmel_port->tasklet_rx); 1315 } 1316 1317 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | 1318 ATMEL_US_FRAME | ATMEL_US_PARE)) 1319 atmel_pdc_rxerr(port, pending); 1320 } 1321 1322 if (atmel_use_dma_rx(port)) { 1323 if (pending & ATMEL_US_TIMEOUT) { 1324 atmel_uart_writel(port, ATMEL_US_IDR, 1325 ATMEL_US_TIMEOUT); 1326 atmel_tasklet_schedule(atmel_port, 1327 &atmel_port->tasklet_rx); 1328 } 1329 } 1330 1331 /* Interrupt receive */ 1332 if (pending & ATMEL_US_RXRDY) 1333 atmel_rx_chars(port); 1334 else if (pending & ATMEL_US_RXBRK) { 1335 /* 1336 * End of break detected. If it came along with a 1337 * character, atmel_rx_chars will handle it. 1338 */ 1339 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 1340 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK); 1341 atmel_port->break_active = 0; 1342 } 1343 } 1344 1345 /* 1346 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) 1347 */ 1348 static void 1349 atmel_handle_transmit(struct uart_port *port, unsigned int pending) 1350 { 1351 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1352 1353 if (pending & atmel_port->tx_done_mask) { 1354 atmel_uart_writel(port, ATMEL_US_IDR, 1355 atmel_port->tx_done_mask); 1356 1357 /* Start RX if flag was set and FIFO is empty */ 1358 if (atmel_port->hd_start_rx) { 1359 if (!(atmel_uart_readl(port, ATMEL_US_CSR) 1360 & ATMEL_US_TXEMPTY)) 1361 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n"); 1362 1363 atmel_port->hd_start_rx = false; 1364 atmel_start_rx(port); 1365 } 1366 1367 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx); 1368 } 1369 } 1370 1371 /* 1372 * status flags interrupt handler. 1373 */ 1374 static void 1375 atmel_handle_status(struct uart_port *port, unsigned int pending, 1376 unsigned int status) 1377 { 1378 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1379 unsigned int status_change; 1380 1381 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC 1382 | ATMEL_US_CTSIC)) { 1383 status_change = status ^ atmel_port->irq_status_prev; 1384 atmel_port->irq_status_prev = status; 1385 1386 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR 1387 | ATMEL_US_DCD | ATMEL_US_CTS)) { 1388 /* TODO: All reads to CSR will clear these interrupts! */ 1389 if (status_change & ATMEL_US_RI) 1390 port->icount.rng++; 1391 if (status_change & ATMEL_US_DSR) 1392 port->icount.dsr++; 1393 if (status_change & ATMEL_US_DCD) 1394 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); 1395 if (status_change & ATMEL_US_CTS) 1396 uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); 1397 1398 wake_up_interruptible(&port->state->port.delta_msr_wait); 1399 } 1400 } 1401 1402 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION)) 1403 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending); 1404 } 1405 1406 /* 1407 * Interrupt handler 1408 */ 1409 static irqreturn_t atmel_interrupt(int irq, void *dev_id) 1410 { 1411 struct uart_port *port = dev_id; 1412 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1413 unsigned int status, pending, mask, pass_counter = 0; 1414 1415 spin_lock(&atmel_port->lock_suspended); 1416 1417 do { 1418 status = atmel_uart_readl(port, ATMEL_US_CSR); 1419 mask = atmel_uart_readl(port, ATMEL_US_IMR); 1420 pending = status & mask; 1421 if (!pending) 1422 break; 1423 1424 if (atmel_port->suspended) { 1425 atmel_port->pending |= pending; 1426 atmel_port->pending_status = status; 1427 atmel_uart_writel(port, ATMEL_US_IDR, mask); 1428 pm_system_wakeup(); 1429 break; 1430 } 1431 1432 atmel_handle_receive(port, pending); 1433 atmel_handle_status(port, pending, status); 1434 atmel_handle_transmit(port, pending); 1435 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); 1436 1437 spin_unlock(&atmel_port->lock_suspended); 1438 1439 return pass_counter ? IRQ_HANDLED : IRQ_NONE; 1440 } 1441 1442 static void atmel_release_tx_pdc(struct uart_port *port) 1443 { 1444 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1445 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1446 1447 dma_unmap_single(port->dev, 1448 pdc->dma_addr, 1449 pdc->dma_size, 1450 DMA_TO_DEVICE); 1451 } 1452 1453 /* 1454 * Called from tasklet with ENDTX and TXBUFE interrupts disabled. 1455 */ 1456 static void atmel_tx_pdc(struct uart_port *port) 1457 { 1458 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1459 struct circ_buf *xmit = &port->state->xmit; 1460 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1461 int count; 1462 1463 /* nothing left to transmit? */ 1464 if (atmel_uart_readl(port, ATMEL_PDC_TCR)) 1465 return; 1466 1467 xmit->tail += pdc->ofs; 1468 xmit->tail &= UART_XMIT_SIZE - 1; 1469 1470 port->icount.tx += pdc->ofs; 1471 pdc->ofs = 0; 1472 1473 /* more to transmit - setup next transfer */ 1474 1475 /* disable PDC transmit */ 1476 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 1477 1478 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 1479 dma_sync_single_for_device(port->dev, 1480 pdc->dma_addr, 1481 pdc->dma_size, 1482 DMA_TO_DEVICE); 1483 1484 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1485 pdc->ofs = count; 1486 1487 atmel_uart_writel(port, ATMEL_PDC_TPR, 1488 pdc->dma_addr + xmit->tail); 1489 atmel_uart_writel(port, ATMEL_PDC_TCR, count); 1490 /* re-enable PDC transmit */ 1491 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 1492 /* Enable interrupts */ 1493 atmel_uart_writel(port, ATMEL_US_IER, 1494 atmel_port->tx_done_mask); 1495 } else { 1496 if (atmel_uart_is_half_duplex(port)) { 1497 /* DMA done, stop TX, start RX for RS485 */ 1498 atmel_start_rx(port); 1499 } 1500 } 1501 1502 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1503 uart_write_wakeup(port); 1504 } 1505 1506 static int atmel_prepare_tx_pdc(struct uart_port *port) 1507 { 1508 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1509 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1510 struct circ_buf *xmit = &port->state->xmit; 1511 1512 pdc->buf = xmit->buf; 1513 pdc->dma_addr = dma_map_single(port->dev, 1514 pdc->buf, 1515 UART_XMIT_SIZE, 1516 DMA_TO_DEVICE); 1517 pdc->dma_size = UART_XMIT_SIZE; 1518 pdc->ofs = 0; 1519 1520 return 0; 1521 } 1522 1523 static void atmel_rx_from_ring(struct uart_port *port) 1524 { 1525 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1526 struct circ_buf *ring = &atmel_port->rx_ring; 1527 unsigned int flg; 1528 unsigned int status; 1529 1530 while (ring->head != ring->tail) { 1531 struct atmel_uart_char c; 1532 1533 /* Make sure c is loaded after head. */ 1534 smp_rmb(); 1535 1536 c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; 1537 1538 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 1539 1540 port->icount.rx++; 1541 status = c.status; 1542 flg = TTY_NORMAL; 1543 1544 /* 1545 * note that the error handling code is 1546 * out of the main execution path 1547 */ 1548 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 1549 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { 1550 if (status & ATMEL_US_RXBRK) { 1551 /* ignore side-effect */ 1552 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 1553 1554 port->icount.brk++; 1555 if (uart_handle_break(port)) 1556 continue; 1557 } 1558 if (status & ATMEL_US_PARE) 1559 port->icount.parity++; 1560 if (status & ATMEL_US_FRAME) 1561 port->icount.frame++; 1562 if (status & ATMEL_US_OVRE) 1563 port->icount.overrun++; 1564 1565 status &= port->read_status_mask; 1566 1567 if (status & ATMEL_US_RXBRK) 1568 flg = TTY_BREAK; 1569 else if (status & ATMEL_US_PARE) 1570 flg = TTY_PARITY; 1571 else if (status & ATMEL_US_FRAME) 1572 flg = TTY_FRAME; 1573 } 1574 1575 1576 if (uart_handle_sysrq_char(port, c.ch)) 1577 continue; 1578 1579 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); 1580 } 1581 1582 /* 1583 * Drop the lock here since it might end up calling 1584 * uart_start(), which takes the lock. 1585 */ 1586 spin_unlock(&port->lock); 1587 tty_flip_buffer_push(&port->state->port); 1588 spin_lock(&port->lock); 1589 } 1590 1591 static void atmel_release_rx_pdc(struct uart_port *port) 1592 { 1593 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1594 int i; 1595 1596 for (i = 0; i < 2; i++) { 1597 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1598 1599 dma_unmap_single(port->dev, 1600 pdc->dma_addr, 1601 pdc->dma_size, 1602 DMA_FROM_DEVICE); 1603 kfree(pdc->buf); 1604 } 1605 } 1606 1607 static void atmel_rx_from_pdc(struct uart_port *port) 1608 { 1609 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1610 struct tty_port *tport = &port->state->port; 1611 struct atmel_dma_buffer *pdc; 1612 int rx_idx = atmel_port->pdc_rx_idx; 1613 unsigned int head; 1614 unsigned int tail; 1615 unsigned int count; 1616 1617 do { 1618 /* Reset the UART timeout early so that we don't miss one */ 1619 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1620 1621 pdc = &atmel_port->pdc_rx[rx_idx]; 1622 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr; 1623 tail = pdc->ofs; 1624 1625 /* If the PDC has switched buffers, RPR won't contain 1626 * any address within the current buffer. Since head 1627 * is unsigned, we just need a one-way comparison to 1628 * find out. 1629 * 1630 * In this case, we just need to consume the entire 1631 * buffer and resubmit it for DMA. This will clear the 1632 * ENDRX bit as well, so that we can safely re-enable 1633 * all interrupts below. 1634 */ 1635 head = min(head, pdc->dma_size); 1636 1637 if (likely(head != tail)) { 1638 dma_sync_single_for_cpu(port->dev, pdc->dma_addr, 1639 pdc->dma_size, DMA_FROM_DEVICE); 1640 1641 /* 1642 * head will only wrap around when we recycle 1643 * the DMA buffer, and when that happens, we 1644 * explicitly set tail to 0. So head will 1645 * always be greater than tail. 1646 */ 1647 count = head - tail; 1648 1649 tty_insert_flip_string(tport, pdc->buf + pdc->ofs, 1650 count); 1651 1652 dma_sync_single_for_device(port->dev, pdc->dma_addr, 1653 pdc->dma_size, DMA_FROM_DEVICE); 1654 1655 port->icount.rx += count; 1656 pdc->ofs = head; 1657 } 1658 1659 /* 1660 * If the current buffer is full, we need to check if 1661 * the next one contains any additional data. 1662 */ 1663 if (head >= pdc->dma_size) { 1664 pdc->ofs = 0; 1665 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr); 1666 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size); 1667 1668 rx_idx = !rx_idx; 1669 atmel_port->pdc_rx_idx = rx_idx; 1670 } 1671 } while (head >= pdc->dma_size); 1672 1673 /* 1674 * Drop the lock here since it might end up calling 1675 * uart_start(), which takes the lock. 1676 */ 1677 spin_unlock(&port->lock); 1678 tty_flip_buffer_push(tport); 1679 spin_lock(&port->lock); 1680 1681 atmel_uart_writel(port, ATMEL_US_IER, 1682 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1683 } 1684 1685 static int atmel_prepare_rx_pdc(struct uart_port *port) 1686 { 1687 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1688 int i; 1689 1690 for (i = 0; i < 2; i++) { 1691 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1692 1693 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); 1694 if (pdc->buf == NULL) { 1695 if (i != 0) { 1696 dma_unmap_single(port->dev, 1697 atmel_port->pdc_rx[0].dma_addr, 1698 PDC_BUFFER_SIZE, 1699 DMA_FROM_DEVICE); 1700 kfree(atmel_port->pdc_rx[0].buf); 1701 } 1702 atmel_port->use_pdc_rx = false; 1703 return -ENOMEM; 1704 } 1705 pdc->dma_addr = dma_map_single(port->dev, 1706 pdc->buf, 1707 PDC_BUFFER_SIZE, 1708 DMA_FROM_DEVICE); 1709 pdc->dma_size = PDC_BUFFER_SIZE; 1710 pdc->ofs = 0; 1711 } 1712 1713 atmel_port->pdc_rx_idx = 0; 1714 1715 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr); 1716 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE); 1717 1718 atmel_uart_writel(port, ATMEL_PDC_RNPR, 1719 atmel_port->pdc_rx[1].dma_addr); 1720 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE); 1721 1722 return 0; 1723 } 1724 1725 /* 1726 * tasklet handling tty stuff outside the interrupt handler. 1727 */ 1728 static void atmel_tasklet_rx_func(unsigned long data) 1729 { 1730 struct uart_port *port = (struct uart_port *)data; 1731 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1732 1733 /* The interrupt handler does not take the lock */ 1734 spin_lock(&port->lock); 1735 atmel_port->schedule_rx(port); 1736 spin_unlock(&port->lock); 1737 } 1738 1739 static void atmel_tasklet_tx_func(unsigned long data) 1740 { 1741 struct uart_port *port = (struct uart_port *)data; 1742 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1743 1744 /* The interrupt handler does not take the lock */ 1745 spin_lock(&port->lock); 1746 atmel_port->schedule_tx(port); 1747 spin_unlock(&port->lock); 1748 } 1749 1750 static void atmel_init_property(struct atmel_uart_port *atmel_port, 1751 struct platform_device *pdev) 1752 { 1753 struct device_node *np = pdev->dev.of_node; 1754 1755 /* DMA/PDC usage specification */ 1756 if (of_property_read_bool(np, "atmel,use-dma-rx")) { 1757 if (of_property_read_bool(np, "dmas")) { 1758 atmel_port->use_dma_rx = true; 1759 atmel_port->use_pdc_rx = false; 1760 } else { 1761 atmel_port->use_dma_rx = false; 1762 atmel_port->use_pdc_rx = true; 1763 } 1764 } else { 1765 atmel_port->use_dma_rx = false; 1766 atmel_port->use_pdc_rx = false; 1767 } 1768 1769 if (of_property_read_bool(np, "atmel,use-dma-tx")) { 1770 if (of_property_read_bool(np, "dmas")) { 1771 atmel_port->use_dma_tx = true; 1772 atmel_port->use_pdc_tx = false; 1773 } else { 1774 atmel_port->use_dma_tx = false; 1775 atmel_port->use_pdc_tx = true; 1776 } 1777 } else { 1778 atmel_port->use_dma_tx = false; 1779 atmel_port->use_pdc_tx = false; 1780 } 1781 } 1782 1783 static void atmel_set_ops(struct uart_port *port) 1784 { 1785 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1786 1787 if (atmel_use_dma_rx(port)) { 1788 atmel_port->prepare_rx = &atmel_prepare_rx_dma; 1789 atmel_port->schedule_rx = &atmel_rx_from_dma; 1790 atmel_port->release_rx = &atmel_release_rx_dma; 1791 } else if (atmel_use_pdc_rx(port)) { 1792 atmel_port->prepare_rx = &atmel_prepare_rx_pdc; 1793 atmel_port->schedule_rx = &atmel_rx_from_pdc; 1794 atmel_port->release_rx = &atmel_release_rx_pdc; 1795 } else { 1796 atmel_port->prepare_rx = NULL; 1797 atmel_port->schedule_rx = &atmel_rx_from_ring; 1798 atmel_port->release_rx = NULL; 1799 } 1800 1801 if (atmel_use_dma_tx(port)) { 1802 atmel_port->prepare_tx = &atmel_prepare_tx_dma; 1803 atmel_port->schedule_tx = &atmel_tx_dma; 1804 atmel_port->release_tx = &atmel_release_tx_dma; 1805 } else if (atmel_use_pdc_tx(port)) { 1806 atmel_port->prepare_tx = &atmel_prepare_tx_pdc; 1807 atmel_port->schedule_tx = &atmel_tx_pdc; 1808 atmel_port->release_tx = &atmel_release_tx_pdc; 1809 } else { 1810 atmel_port->prepare_tx = NULL; 1811 atmel_port->schedule_tx = &atmel_tx_chars; 1812 atmel_port->release_tx = NULL; 1813 } 1814 } 1815 1816 /* 1817 * Get ip name usart or uart 1818 */ 1819 static void atmel_get_ip_name(struct uart_port *port) 1820 { 1821 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1822 int name = atmel_uart_readl(port, ATMEL_US_NAME); 1823 u32 version; 1824 u32 usart, dbgu_uart, new_uart; 1825 /* ASCII decoding for IP version */ 1826 usart = 0x55534152; /* USAR(T) */ 1827 dbgu_uart = 0x44424755; /* DBGU */ 1828 new_uart = 0x55415254; /* UART */ 1829 1830 /* 1831 * Only USART devices from at91sam9260 SOC implement fractional 1832 * baudrate. It is available for all asynchronous modes, with the 1833 * following restriction: the sampling clock's duty cycle is not 1834 * constant. 1835 */ 1836 atmel_port->has_frac_baudrate = false; 1837 atmel_port->has_hw_timer = false; 1838 1839 if (name == new_uart) { 1840 dev_dbg(port->dev, "Uart with hw timer"); 1841 atmel_port->has_hw_timer = true; 1842 atmel_port->rtor = ATMEL_UA_RTOR; 1843 } else if (name == usart) { 1844 dev_dbg(port->dev, "Usart\n"); 1845 atmel_port->has_frac_baudrate = true; 1846 atmel_port->has_hw_timer = true; 1847 atmel_port->rtor = ATMEL_US_RTOR; 1848 version = atmel_uart_readl(port, ATMEL_US_VERSION); 1849 switch (version) { 1850 case 0x814: /* sama5d2 */ 1851 /* fall through */ 1852 case 0x701: /* sama5d4 */ 1853 atmel_port->fidi_min = 3; 1854 atmel_port->fidi_max = 65535; 1855 break; 1856 case 0x502: /* sam9x5, sama5d3 */ 1857 atmel_port->fidi_min = 3; 1858 atmel_port->fidi_max = 2047; 1859 break; 1860 default: 1861 atmel_port->fidi_min = 1; 1862 atmel_port->fidi_max = 2047; 1863 } 1864 } else if (name == dbgu_uart) { 1865 dev_dbg(port->dev, "Dbgu or uart without hw timer\n"); 1866 } else { 1867 /* fallback for older SoCs: use version field */ 1868 version = atmel_uart_readl(port, ATMEL_US_VERSION); 1869 switch (version) { 1870 case 0x302: 1871 case 0x10213: 1872 case 0x10302: 1873 dev_dbg(port->dev, "This version is usart\n"); 1874 atmel_port->has_frac_baudrate = true; 1875 atmel_port->has_hw_timer = true; 1876 atmel_port->rtor = ATMEL_US_RTOR; 1877 break; 1878 case 0x203: 1879 case 0x10202: 1880 dev_dbg(port->dev, "This version is uart\n"); 1881 break; 1882 default: 1883 dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); 1884 } 1885 } 1886 } 1887 1888 /* 1889 * Perform initialization and enable port for reception 1890 */ 1891 static int atmel_startup(struct uart_port *port) 1892 { 1893 struct platform_device *pdev = to_platform_device(port->dev); 1894 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1895 int retval; 1896 1897 /* 1898 * Ensure that no interrupts are enabled otherwise when 1899 * request_irq() is called we could get stuck trying to 1900 * handle an unexpected interrupt 1901 */ 1902 atmel_uart_writel(port, ATMEL_US_IDR, -1); 1903 atmel_port->ms_irq_enabled = false; 1904 1905 /* 1906 * Allocate the IRQ 1907 */ 1908 retval = request_irq(port->irq, atmel_interrupt, 1909 IRQF_SHARED | IRQF_COND_SUSPEND, 1910 dev_name(&pdev->dev), port); 1911 if (retval) { 1912 dev_err(port->dev, "atmel_startup - Can't get irq\n"); 1913 return retval; 1914 } 1915 1916 atomic_set(&atmel_port->tasklet_shutdown, 0); 1917 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func, 1918 (unsigned long)port); 1919 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func, 1920 (unsigned long)port); 1921 1922 /* 1923 * Initialize DMA (if necessary) 1924 */ 1925 atmel_init_property(atmel_port, pdev); 1926 atmel_set_ops(port); 1927 1928 if (atmel_port->prepare_rx) { 1929 retval = atmel_port->prepare_rx(port); 1930 if (retval < 0) 1931 atmel_set_ops(port); 1932 } 1933 1934 if (atmel_port->prepare_tx) { 1935 retval = atmel_port->prepare_tx(port); 1936 if (retval < 0) 1937 atmel_set_ops(port); 1938 } 1939 1940 /* 1941 * Enable FIFO when available 1942 */ 1943 if (atmel_port->fifo_size) { 1944 unsigned int txrdym = ATMEL_US_ONE_DATA; 1945 unsigned int rxrdym = ATMEL_US_ONE_DATA; 1946 unsigned int fmr; 1947 1948 atmel_uart_writel(port, ATMEL_US_CR, 1949 ATMEL_US_FIFOEN | 1950 ATMEL_US_RXFCLR | 1951 ATMEL_US_TXFLCLR); 1952 1953 if (atmel_use_dma_tx(port)) 1954 txrdym = ATMEL_US_FOUR_DATA; 1955 1956 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym); 1957 if (atmel_port->rts_high && 1958 atmel_port->rts_low) 1959 fmr |= ATMEL_US_FRTSC | 1960 ATMEL_US_RXFTHRES(atmel_port->rts_high) | 1961 ATMEL_US_RXFTHRES2(atmel_port->rts_low); 1962 1963 atmel_uart_writel(port, ATMEL_US_FMR, fmr); 1964 } 1965 1966 /* Save current CSR for comparison in atmel_tasklet_func() */ 1967 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR); 1968 1969 /* 1970 * Finally, enable the serial port 1971 */ 1972 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1973 /* enable xmit & rcvr */ 1974 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 1975 atmel_port->tx_stopped = false; 1976 1977 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0); 1978 1979 if (atmel_use_pdc_rx(port)) { 1980 /* set UART timeout */ 1981 if (!atmel_port->has_hw_timer) { 1982 mod_timer(&atmel_port->uart_timer, 1983 jiffies + uart_poll_timeout(port)); 1984 /* set USART timeout */ 1985 } else { 1986 atmel_uart_writel(port, atmel_port->rtor, 1987 PDC_RX_TIMEOUT); 1988 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1989 1990 atmel_uart_writel(port, ATMEL_US_IER, 1991 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1992 } 1993 /* enable PDC controller */ 1994 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 1995 } else if (atmel_use_dma_rx(port)) { 1996 /* set UART timeout */ 1997 if (!atmel_port->has_hw_timer) { 1998 mod_timer(&atmel_port->uart_timer, 1999 jiffies + uart_poll_timeout(port)); 2000 /* set USART timeout */ 2001 } else { 2002 atmel_uart_writel(port, atmel_port->rtor, 2003 PDC_RX_TIMEOUT); 2004 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 2005 2006 atmel_uart_writel(port, ATMEL_US_IER, 2007 ATMEL_US_TIMEOUT); 2008 } 2009 } else { 2010 /* enable receive only */ 2011 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY); 2012 } 2013 2014 return 0; 2015 } 2016 2017 /* 2018 * Flush any TX data submitted for DMA. Called when the TX circular 2019 * buffer is reset. 2020 */ 2021 static void atmel_flush_buffer(struct uart_port *port) 2022 { 2023 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2024 2025 if (atmel_use_pdc_tx(port)) { 2026 atmel_uart_writel(port, ATMEL_PDC_TCR, 0); 2027 atmel_port->pdc_tx.ofs = 0; 2028 } 2029 /* 2030 * in uart_flush_buffer(), the xmit circular buffer has just 2031 * been cleared, so we have to reset tx_len accordingly. 2032 */ 2033 atmel_port->tx_len = 0; 2034 } 2035 2036 /* 2037 * Disable the port 2038 */ 2039 static void atmel_shutdown(struct uart_port *port) 2040 { 2041 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2042 2043 /* Disable modem control lines interrupts */ 2044 atmel_disable_ms(port); 2045 2046 /* Disable interrupts at device level */ 2047 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2048 2049 /* Prevent spurious interrupts from scheduling the tasklet */ 2050 atomic_inc(&atmel_port->tasklet_shutdown); 2051 2052 /* 2053 * Prevent any tasklets being scheduled during 2054 * cleanup 2055 */ 2056 del_timer_sync(&atmel_port->uart_timer); 2057 2058 /* Make sure that no interrupt is on the fly */ 2059 synchronize_irq(port->irq); 2060 2061 /* 2062 * Clear out any scheduled tasklets before 2063 * we destroy the buffers 2064 */ 2065 tasklet_kill(&atmel_port->tasklet_rx); 2066 tasklet_kill(&atmel_port->tasklet_tx); 2067 2068 /* 2069 * Ensure everything is stopped and 2070 * disable port and break condition. 2071 */ 2072 atmel_stop_rx(port); 2073 atmel_stop_tx(port); 2074 2075 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 2076 2077 /* 2078 * Shut-down the DMA. 2079 */ 2080 if (atmel_port->release_rx) 2081 atmel_port->release_rx(port); 2082 if (atmel_port->release_tx) 2083 atmel_port->release_tx(port); 2084 2085 /* 2086 * Reset ring buffer pointers 2087 */ 2088 atmel_port->rx_ring.head = 0; 2089 atmel_port->rx_ring.tail = 0; 2090 2091 /* 2092 * Free the interrupts 2093 */ 2094 free_irq(port->irq, port); 2095 2096 atmel_flush_buffer(port); 2097 } 2098 2099 /* 2100 * Power / Clock management. 2101 */ 2102 static void atmel_serial_pm(struct uart_port *port, unsigned int state, 2103 unsigned int oldstate) 2104 { 2105 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2106 2107 switch (state) { 2108 case 0: 2109 /* 2110 * Enable the peripheral clock for this serial port. 2111 * This is called on uart_open() or a resume event. 2112 */ 2113 clk_prepare_enable(atmel_port->clk); 2114 2115 /* re-enable interrupts if we disabled some on suspend */ 2116 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr); 2117 break; 2118 case 3: 2119 /* Back up the interrupt mask and disable all interrupts */ 2120 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR); 2121 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2122 2123 /* 2124 * Disable the peripheral clock for this serial port. 2125 * This is called on uart_close() or a suspend event. 2126 */ 2127 clk_disable_unprepare(atmel_port->clk); 2128 break; 2129 default: 2130 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); 2131 } 2132 } 2133 2134 /* 2135 * Change the port parameters 2136 */ 2137 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, 2138 struct ktermios *old) 2139 { 2140 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2141 unsigned long flags; 2142 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0; 2143 2144 /* save the current mode register */ 2145 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR); 2146 2147 /* reset the mode, clock divisor, parity, stop bits and data size */ 2148 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | 2149 ATMEL_US_PAR | ATMEL_US_USMODE); 2150 2151 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 2152 2153 /* byte size */ 2154 switch (termios->c_cflag & CSIZE) { 2155 case CS5: 2156 mode |= ATMEL_US_CHRL_5; 2157 break; 2158 case CS6: 2159 mode |= ATMEL_US_CHRL_6; 2160 break; 2161 case CS7: 2162 mode |= ATMEL_US_CHRL_7; 2163 break; 2164 default: 2165 mode |= ATMEL_US_CHRL_8; 2166 break; 2167 } 2168 2169 /* stop bits */ 2170 if (termios->c_cflag & CSTOPB) 2171 mode |= ATMEL_US_NBSTOP_2; 2172 2173 /* parity */ 2174 if (termios->c_cflag & PARENB) { 2175 /* Mark or Space parity */ 2176 if (termios->c_cflag & CMSPAR) { 2177 if (termios->c_cflag & PARODD) 2178 mode |= ATMEL_US_PAR_MARK; 2179 else 2180 mode |= ATMEL_US_PAR_SPACE; 2181 } else if (termios->c_cflag & PARODD) 2182 mode |= ATMEL_US_PAR_ODD; 2183 else 2184 mode |= ATMEL_US_PAR_EVEN; 2185 } else 2186 mode |= ATMEL_US_PAR_NONE; 2187 2188 spin_lock_irqsave(&port->lock, flags); 2189 2190 port->read_status_mask = ATMEL_US_OVRE; 2191 if (termios->c_iflag & INPCK) 2192 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2193 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2194 port->read_status_mask |= ATMEL_US_RXBRK; 2195 2196 if (atmel_use_pdc_rx(port)) 2197 /* need to enable error interrupts */ 2198 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask); 2199 2200 /* 2201 * Characters to ignore 2202 */ 2203 port->ignore_status_mask = 0; 2204 if (termios->c_iflag & IGNPAR) 2205 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2206 if (termios->c_iflag & IGNBRK) { 2207 port->ignore_status_mask |= ATMEL_US_RXBRK; 2208 /* 2209 * If we're ignoring parity and break indicators, 2210 * ignore overruns too (for real raw support). 2211 */ 2212 if (termios->c_iflag & IGNPAR) 2213 port->ignore_status_mask |= ATMEL_US_OVRE; 2214 } 2215 /* TODO: Ignore all characters if CREAD is set.*/ 2216 2217 /* update the per-port timeout */ 2218 uart_update_timeout(port, termios->c_cflag, baud); 2219 2220 /* 2221 * save/disable interrupts. The tty layer will ensure that the 2222 * transmitter is empty if requested by the caller, so there's 2223 * no need to wait for it here. 2224 */ 2225 imr = atmel_uart_readl(port, ATMEL_US_IMR); 2226 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2227 2228 /* disable receiver and transmitter */ 2229 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS); 2230 atmel_port->tx_stopped = true; 2231 2232 /* mode */ 2233 if (port->rs485.flags & SER_RS485_ENABLED) { 2234 atmel_uart_writel(port, ATMEL_US_TTGR, 2235 port->rs485.delay_rts_after_send); 2236 mode |= ATMEL_US_USMODE_RS485; 2237 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) { 2238 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg); 2239 /* select mck clock, and output */ 2240 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO; 2241 /* set max iterations */ 2242 mode |= ATMEL_US_MAX_ITER(3); 2243 if ((port->iso7816.flags & SER_ISO7816_T_PARAM) 2244 == SER_ISO7816_T(0)) 2245 mode |= ATMEL_US_USMODE_ISO7816_T0; 2246 else 2247 mode |= ATMEL_US_USMODE_ISO7816_T1; 2248 } else if (termios->c_cflag & CRTSCTS) { 2249 /* RS232 with hardware handshake (RTS/CTS) */ 2250 if (atmel_use_fifo(port) && 2251 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) { 2252 /* 2253 * with ATMEL_US_USMODE_HWHS set, the controller will 2254 * be able to drive the RTS pin high/low when the RX 2255 * FIFO is above RXFTHRES/below RXFTHRES2. 2256 * It will also disable the transmitter when the CTS 2257 * pin is high. 2258 * This mode is not activated if CTS pin is a GPIO 2259 * because in this case, the transmitter is always 2260 * disabled (there must be an internal pull-up 2261 * responsible for this behaviour). 2262 * If the RTS pin is a GPIO, the controller won't be 2263 * able to drive it according to the FIFO thresholds, 2264 * but it will be handled by the driver. 2265 */ 2266 mode |= ATMEL_US_USMODE_HWHS; 2267 } else { 2268 /* 2269 * For platforms without FIFO, the flow control is 2270 * handled by the driver. 2271 */ 2272 mode |= ATMEL_US_USMODE_NORMAL; 2273 } 2274 } else { 2275 /* RS232 without hadware handshake */ 2276 mode |= ATMEL_US_USMODE_NORMAL; 2277 } 2278 2279 /* 2280 * Set the baud rate: 2281 * Fractional baudrate allows to setup output frequency more 2282 * accurately. This feature is enabled only when using normal mode. 2283 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8)) 2284 * Currently, OVER is always set to 0 so we get 2285 * baudrate = selected clock / (16 * (CD + FP / 8)) 2286 * then 2287 * 8 CD + FP = selected clock / (2 * baudrate) 2288 */ 2289 if (atmel_port->has_frac_baudrate) { 2290 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2); 2291 cd = div >> 3; 2292 fp = div & ATMEL_US_FP_MASK; 2293 } else { 2294 cd = uart_get_divisor(port, baud); 2295 } 2296 2297 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */ 2298 cd /= 8; 2299 mode |= ATMEL_US_USCLKS_MCK_DIV8; 2300 } 2301 quot = cd | fp << ATMEL_US_FP_OFFSET; 2302 2303 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) 2304 atmel_uart_writel(port, ATMEL_US_BRGR, quot); 2305 2306 /* set the mode, clock divisor, parity, stop bits and data size */ 2307 atmel_uart_writel(port, ATMEL_US_MR, mode); 2308 2309 /* 2310 * when switching the mode, set the RTS line state according to the 2311 * new mode, otherwise keep the former state 2312 */ 2313 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) { 2314 unsigned int rts_state; 2315 2316 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 2317 /* let the hardware control the RTS line */ 2318 rts_state = ATMEL_US_RTSDIS; 2319 } else { 2320 /* force RTS line to low level */ 2321 rts_state = ATMEL_US_RTSEN; 2322 } 2323 2324 atmel_uart_writel(port, ATMEL_US_CR, rts_state); 2325 } 2326 2327 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2328 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 2329 atmel_port->tx_stopped = false; 2330 2331 /* restore interrupts */ 2332 atmel_uart_writel(port, ATMEL_US_IER, imr); 2333 2334 /* CTS flow-control and modem-status interrupts */ 2335 if (UART_ENABLE_MS(port, termios->c_cflag)) 2336 atmel_enable_ms(port); 2337 else 2338 atmel_disable_ms(port); 2339 2340 spin_unlock_irqrestore(&port->lock, flags); 2341 } 2342 2343 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios) 2344 { 2345 if (termios->c_line == N_PPS) { 2346 port->flags |= UPF_HARDPPS_CD; 2347 spin_lock_irq(&port->lock); 2348 atmel_enable_ms(port); 2349 spin_unlock_irq(&port->lock); 2350 } else { 2351 port->flags &= ~UPF_HARDPPS_CD; 2352 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 2353 spin_lock_irq(&port->lock); 2354 atmel_disable_ms(port); 2355 spin_unlock_irq(&port->lock); 2356 } 2357 } 2358 } 2359 2360 /* 2361 * Return string describing the specified port 2362 */ 2363 static const char *atmel_type(struct uart_port *port) 2364 { 2365 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; 2366 } 2367 2368 /* 2369 * Release the memory region(s) being used by 'port'. 2370 */ 2371 static void atmel_release_port(struct uart_port *port) 2372 { 2373 struct platform_device *mpdev = to_platform_device(port->dev->parent); 2374 int size = resource_size(mpdev->resource); 2375 2376 release_mem_region(port->mapbase, size); 2377 2378 if (port->flags & UPF_IOREMAP) { 2379 iounmap(port->membase); 2380 port->membase = NULL; 2381 } 2382 } 2383 2384 /* 2385 * Request the memory region(s) being used by 'port'. 2386 */ 2387 static int atmel_request_port(struct uart_port *port) 2388 { 2389 struct platform_device *mpdev = to_platform_device(port->dev->parent); 2390 int size = resource_size(mpdev->resource); 2391 2392 if (!request_mem_region(port->mapbase, size, "atmel_serial")) 2393 return -EBUSY; 2394 2395 if (port->flags & UPF_IOREMAP) { 2396 port->membase = ioremap(port->mapbase, size); 2397 if (port->membase == NULL) { 2398 release_mem_region(port->mapbase, size); 2399 return -ENOMEM; 2400 } 2401 } 2402 2403 return 0; 2404 } 2405 2406 /* 2407 * Configure/autoconfigure the port. 2408 */ 2409 static void atmel_config_port(struct uart_port *port, int flags) 2410 { 2411 if (flags & UART_CONFIG_TYPE) { 2412 port->type = PORT_ATMEL; 2413 atmel_request_port(port); 2414 } 2415 } 2416 2417 /* 2418 * Verify the new serial_struct (for TIOCSSERIAL). 2419 */ 2420 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) 2421 { 2422 int ret = 0; 2423 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) 2424 ret = -EINVAL; 2425 if (port->irq != ser->irq) 2426 ret = -EINVAL; 2427 if (ser->io_type != SERIAL_IO_MEM) 2428 ret = -EINVAL; 2429 if (port->uartclk / 16 != ser->baud_base) 2430 ret = -EINVAL; 2431 if (port->mapbase != (unsigned long)ser->iomem_base) 2432 ret = -EINVAL; 2433 if (port->iobase != ser->port) 2434 ret = -EINVAL; 2435 if (ser->hub6 != 0) 2436 ret = -EINVAL; 2437 return ret; 2438 } 2439 2440 #ifdef CONFIG_CONSOLE_POLL 2441 static int atmel_poll_get_char(struct uart_port *port) 2442 { 2443 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY)) 2444 cpu_relax(); 2445 2446 return atmel_uart_read_char(port); 2447 } 2448 2449 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) 2450 { 2451 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) 2452 cpu_relax(); 2453 2454 atmel_uart_write_char(port, ch); 2455 } 2456 #endif 2457 2458 static const struct uart_ops atmel_pops = { 2459 .tx_empty = atmel_tx_empty, 2460 .set_mctrl = atmel_set_mctrl, 2461 .get_mctrl = atmel_get_mctrl, 2462 .stop_tx = atmel_stop_tx, 2463 .start_tx = atmel_start_tx, 2464 .stop_rx = atmel_stop_rx, 2465 .enable_ms = atmel_enable_ms, 2466 .break_ctl = atmel_break_ctl, 2467 .startup = atmel_startup, 2468 .shutdown = atmel_shutdown, 2469 .flush_buffer = atmel_flush_buffer, 2470 .set_termios = atmel_set_termios, 2471 .set_ldisc = atmel_set_ldisc, 2472 .type = atmel_type, 2473 .release_port = atmel_release_port, 2474 .request_port = atmel_request_port, 2475 .config_port = atmel_config_port, 2476 .verify_port = atmel_verify_port, 2477 .pm = atmel_serial_pm, 2478 #ifdef CONFIG_CONSOLE_POLL 2479 .poll_get_char = atmel_poll_get_char, 2480 .poll_put_char = atmel_poll_put_char, 2481 #endif 2482 }; 2483 2484 /* 2485 * Configure the port from the platform device resource info. 2486 */ 2487 static int atmel_init_port(struct atmel_uart_port *atmel_port, 2488 struct platform_device *pdev) 2489 { 2490 int ret; 2491 struct uart_port *port = &atmel_port->uart; 2492 struct platform_device *mpdev = to_platform_device(pdev->dev.parent); 2493 2494 atmel_init_property(atmel_port, pdev); 2495 atmel_set_ops(port); 2496 2497 uart_get_rs485_mode(&mpdev->dev, &port->rs485); 2498 2499 port->iotype = UPIO_MEM; 2500 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; 2501 port->ops = &atmel_pops; 2502 port->fifosize = 1; 2503 port->dev = &pdev->dev; 2504 port->mapbase = mpdev->resource[0].start; 2505 port->irq = mpdev->resource[1].start; 2506 port->rs485_config = atmel_config_rs485; 2507 port->iso7816_config = atmel_config_iso7816; 2508 port->membase = NULL; 2509 2510 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); 2511 2512 /* for console, the clock could already be configured */ 2513 if (!atmel_port->clk) { 2514 atmel_port->clk = clk_get(&mpdev->dev, "usart"); 2515 if (IS_ERR(atmel_port->clk)) { 2516 ret = PTR_ERR(atmel_port->clk); 2517 atmel_port->clk = NULL; 2518 return ret; 2519 } 2520 ret = clk_prepare_enable(atmel_port->clk); 2521 if (ret) { 2522 clk_put(atmel_port->clk); 2523 atmel_port->clk = NULL; 2524 return ret; 2525 } 2526 port->uartclk = clk_get_rate(atmel_port->clk); 2527 clk_disable_unprepare(atmel_port->clk); 2528 /* only enable clock when USART is in use */ 2529 } 2530 2531 /* 2532 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or 2533 * ENDTX|TXBUFE 2534 */ 2535 if (atmel_uart_is_half_duplex(port)) 2536 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 2537 else if (atmel_use_pdc_tx(port)) { 2538 port->fifosize = PDC_BUFFER_SIZE; 2539 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; 2540 } else { 2541 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 2542 } 2543 2544 return 0; 2545 } 2546 2547 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2548 static void atmel_console_putchar(struct uart_port *port, int ch) 2549 { 2550 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) 2551 cpu_relax(); 2552 atmel_uart_write_char(port, ch); 2553 } 2554 2555 /* 2556 * Interrupts are disabled on entering 2557 */ 2558 static void atmel_console_write(struct console *co, const char *s, u_int count) 2559 { 2560 struct uart_port *port = &atmel_ports[co->index].uart; 2561 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2562 unsigned int status, imr; 2563 unsigned int pdc_tx; 2564 2565 /* 2566 * First, save IMR and then disable interrupts 2567 */ 2568 imr = atmel_uart_readl(port, ATMEL_US_IMR); 2569 atmel_uart_writel(port, ATMEL_US_IDR, 2570 ATMEL_US_RXRDY | atmel_port->tx_done_mask); 2571 2572 /* Store PDC transmit status and disable it */ 2573 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN; 2574 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 2575 2576 /* Make sure that tx path is actually able to send characters */ 2577 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN); 2578 atmel_port->tx_stopped = false; 2579 2580 uart_console_write(port, s, count, atmel_console_putchar); 2581 2582 /* 2583 * Finally, wait for transmitter to become empty 2584 * and restore IMR 2585 */ 2586 do { 2587 status = atmel_uart_readl(port, ATMEL_US_CSR); 2588 } while (!(status & ATMEL_US_TXRDY)); 2589 2590 /* Restore PDC transmit status */ 2591 if (pdc_tx) 2592 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 2593 2594 /* set interrupts back the way they were */ 2595 atmel_uart_writel(port, ATMEL_US_IER, imr); 2596 } 2597 2598 /* 2599 * If the port was already initialised (eg, by a boot loader), 2600 * try to determine the current setup. 2601 */ 2602 static void __init atmel_console_get_options(struct uart_port *port, int *baud, 2603 int *parity, int *bits) 2604 { 2605 unsigned int mr, quot; 2606 2607 /* 2608 * If the baud rate generator isn't running, the port wasn't 2609 * initialized by the boot loader. 2610 */ 2611 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD; 2612 if (!quot) 2613 return; 2614 2615 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL; 2616 if (mr == ATMEL_US_CHRL_8) 2617 *bits = 8; 2618 else 2619 *bits = 7; 2620 2621 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR; 2622 if (mr == ATMEL_US_PAR_EVEN) 2623 *parity = 'e'; 2624 else if (mr == ATMEL_US_PAR_ODD) 2625 *parity = 'o'; 2626 2627 /* 2628 * The serial core only rounds down when matching this to a 2629 * supported baud rate. Make sure we don't end up slightly 2630 * lower than one of those, as it would make us fall through 2631 * to a much lower baud rate than we really want. 2632 */ 2633 *baud = port->uartclk / (16 * (quot - 1)); 2634 } 2635 2636 static int __init atmel_console_setup(struct console *co, char *options) 2637 { 2638 int ret; 2639 struct uart_port *port = &atmel_ports[co->index].uart; 2640 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2641 int baud = 115200; 2642 int bits = 8; 2643 int parity = 'n'; 2644 int flow = 'n'; 2645 2646 if (port->membase == NULL) { 2647 /* Port not initialized yet - delay setup */ 2648 return -ENODEV; 2649 } 2650 2651 ret = clk_prepare_enable(atmel_ports[co->index].clk); 2652 if (ret) 2653 return ret; 2654 2655 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2656 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2657 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 2658 atmel_port->tx_stopped = false; 2659 2660 if (options) 2661 uart_parse_options(options, &baud, &parity, &bits, &flow); 2662 else 2663 atmel_console_get_options(port, &baud, &parity, &bits); 2664 2665 return uart_set_options(port, co, baud, parity, bits, flow); 2666 } 2667 2668 static struct uart_driver atmel_uart; 2669 2670 static struct console atmel_console = { 2671 .name = ATMEL_DEVICENAME, 2672 .write = atmel_console_write, 2673 .device = uart_console_device, 2674 .setup = atmel_console_setup, 2675 .flags = CON_PRINTBUFFER, 2676 .index = -1, 2677 .data = &atmel_uart, 2678 }; 2679 2680 #define ATMEL_CONSOLE_DEVICE (&atmel_console) 2681 2682 static inline bool atmel_is_console_port(struct uart_port *port) 2683 { 2684 return port->cons && port->cons->index == port->line; 2685 } 2686 2687 #else 2688 #define ATMEL_CONSOLE_DEVICE NULL 2689 2690 static inline bool atmel_is_console_port(struct uart_port *port) 2691 { 2692 return false; 2693 } 2694 #endif 2695 2696 static struct uart_driver atmel_uart = { 2697 .owner = THIS_MODULE, 2698 .driver_name = "atmel_serial", 2699 .dev_name = ATMEL_DEVICENAME, 2700 .major = SERIAL_ATMEL_MAJOR, 2701 .minor = MINOR_START, 2702 .nr = ATMEL_MAX_UART, 2703 .cons = ATMEL_CONSOLE_DEVICE, 2704 }; 2705 2706 #ifdef CONFIG_PM 2707 static bool atmel_serial_clk_will_stop(void) 2708 { 2709 #ifdef CONFIG_ARCH_AT91 2710 return at91_suspend_entering_slow_clock(); 2711 #else 2712 return false; 2713 #endif 2714 } 2715 2716 static int atmel_serial_suspend(struct platform_device *pdev, 2717 pm_message_t state) 2718 { 2719 struct uart_port *port = platform_get_drvdata(pdev); 2720 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2721 2722 if (atmel_is_console_port(port) && console_suspend_enabled) { 2723 /* Drain the TX shifter */ 2724 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & 2725 ATMEL_US_TXEMPTY)) 2726 cpu_relax(); 2727 } 2728 2729 if (atmel_is_console_port(port) && !console_suspend_enabled) { 2730 /* Cache register values as we won't get a full shutdown/startup 2731 * cycle 2732 */ 2733 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR); 2734 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR); 2735 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR); 2736 atmel_port->cache.rtor = atmel_uart_readl(port, 2737 atmel_port->rtor); 2738 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR); 2739 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR); 2740 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR); 2741 } 2742 2743 /* we can not wake up if we're running on slow clock */ 2744 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); 2745 if (atmel_serial_clk_will_stop()) { 2746 unsigned long flags; 2747 2748 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2749 atmel_port->suspended = true; 2750 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2751 device_set_wakeup_enable(&pdev->dev, 0); 2752 } 2753 2754 uart_suspend_port(&atmel_uart, port); 2755 2756 return 0; 2757 } 2758 2759 static int atmel_serial_resume(struct platform_device *pdev) 2760 { 2761 struct uart_port *port = platform_get_drvdata(pdev); 2762 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2763 unsigned long flags; 2764 2765 if (atmel_is_console_port(port) && !console_suspend_enabled) { 2766 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr); 2767 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr); 2768 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr); 2769 atmel_uart_writel(port, atmel_port->rtor, 2770 atmel_port->cache.rtor); 2771 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr); 2772 2773 if (atmel_port->fifo_size) { 2774 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN | 2775 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR); 2776 atmel_uart_writel(port, ATMEL_US_FMR, 2777 atmel_port->cache.fmr); 2778 atmel_uart_writel(port, ATMEL_US_FIER, 2779 atmel_port->cache.fimr); 2780 } 2781 atmel_start_rx(port); 2782 } 2783 2784 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2785 if (atmel_port->pending) { 2786 atmel_handle_receive(port, atmel_port->pending); 2787 atmel_handle_status(port, atmel_port->pending, 2788 atmel_port->pending_status); 2789 atmel_handle_transmit(port, atmel_port->pending); 2790 atmel_port->pending = 0; 2791 } 2792 atmel_port->suspended = false; 2793 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2794 2795 uart_resume_port(&atmel_uart, port); 2796 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); 2797 2798 return 0; 2799 } 2800 #else 2801 #define atmel_serial_suspend NULL 2802 #define atmel_serial_resume NULL 2803 #endif 2804 2805 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port, 2806 struct platform_device *pdev) 2807 { 2808 atmel_port->fifo_size = 0; 2809 atmel_port->rts_low = 0; 2810 atmel_port->rts_high = 0; 2811 2812 if (of_property_read_u32(pdev->dev.of_node, 2813 "atmel,fifo-size", 2814 &atmel_port->fifo_size)) 2815 return; 2816 2817 if (!atmel_port->fifo_size) 2818 return; 2819 2820 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) { 2821 atmel_port->fifo_size = 0; 2822 dev_err(&pdev->dev, "Invalid FIFO size\n"); 2823 return; 2824 } 2825 2826 /* 2827 * 0 <= rts_low <= rts_high <= fifo_size 2828 * Once their CTS line asserted by the remote peer, some x86 UARTs tend 2829 * to flush their internal TX FIFO, commonly up to 16 data, before 2830 * actually stopping to send new data. So we try to set the RTS High 2831 * Threshold to a reasonably high value respecting this 16 data 2832 * empirical rule when possible. 2833 */ 2834 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1, 2835 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET); 2836 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2, 2837 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET); 2838 2839 dev_info(&pdev->dev, "Using FIFO (%u data)\n", 2840 atmel_port->fifo_size); 2841 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n", 2842 atmel_port->rts_high); 2843 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n", 2844 atmel_port->rts_low); 2845 } 2846 2847 static int atmel_serial_probe(struct platform_device *pdev) 2848 { 2849 struct atmel_uart_port *atmel_port; 2850 struct device_node *np = pdev->dev.parent->of_node; 2851 void *data; 2852 int ret; 2853 bool rs485_enabled; 2854 2855 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); 2856 2857 /* 2858 * In device tree there is no node with "atmel,at91rm9200-usart-serial" 2859 * as compatible string. This driver is probed by at91-usart mfd driver 2860 * which is just a wrapper over the atmel_serial driver and 2861 * spi-at91-usart driver. All attributes needed by this driver are 2862 * found in of_node of parent. 2863 */ 2864 pdev->dev.of_node = np; 2865 2866 ret = of_alias_get_id(np, "serial"); 2867 if (ret < 0) 2868 /* port id not found in platform data nor device-tree aliases: 2869 * auto-enumerate it */ 2870 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); 2871 2872 if (ret >= ATMEL_MAX_UART) { 2873 ret = -ENODEV; 2874 goto err; 2875 } 2876 2877 if (test_and_set_bit(ret, atmel_ports_in_use)) { 2878 /* port already in use */ 2879 ret = -EBUSY; 2880 goto err; 2881 } 2882 2883 atmel_port = &atmel_ports[ret]; 2884 atmel_port->backup_imr = 0; 2885 atmel_port->uart.line = ret; 2886 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE); 2887 atmel_serial_probe_fifos(atmel_port, pdev); 2888 2889 atomic_set(&atmel_port->tasklet_shutdown, 0); 2890 spin_lock_init(&atmel_port->lock_suspended); 2891 2892 ret = atmel_init_port(atmel_port, pdev); 2893 if (ret) 2894 goto err_clear_bit; 2895 2896 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0); 2897 if (IS_ERR(atmel_port->gpios)) { 2898 ret = PTR_ERR(atmel_port->gpios); 2899 goto err_clear_bit; 2900 } 2901 2902 if (!atmel_use_pdc_rx(&atmel_port->uart)) { 2903 ret = -ENOMEM; 2904 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE, 2905 sizeof(struct atmel_uart_char), 2906 GFP_KERNEL); 2907 if (!data) 2908 goto err_alloc_ring; 2909 atmel_port->rx_ring.buf = data; 2910 } 2911 2912 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED; 2913 2914 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart); 2915 if (ret) 2916 goto err_add_port; 2917 2918 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2919 if (atmel_is_console_port(&atmel_port->uart) 2920 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { 2921 /* 2922 * The serial core enabled the clock for us, so undo 2923 * the clk_prepare_enable() in atmel_console_setup() 2924 */ 2925 clk_disable_unprepare(atmel_port->clk); 2926 } 2927 #endif 2928 2929 device_init_wakeup(&pdev->dev, 1); 2930 platform_set_drvdata(pdev, atmel_port); 2931 2932 /* 2933 * The peripheral clock has been disabled by atmel_init_port(): 2934 * enable it before accessing I/O registers 2935 */ 2936 clk_prepare_enable(atmel_port->clk); 2937 2938 if (rs485_enabled) { 2939 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR, 2940 ATMEL_US_USMODE_NORMAL); 2941 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR, 2942 ATMEL_US_RTSEN); 2943 } 2944 2945 /* 2946 * Get port name of usart or uart 2947 */ 2948 atmel_get_ip_name(&atmel_port->uart); 2949 2950 /* 2951 * The peripheral clock can now safely be disabled till the port 2952 * is used 2953 */ 2954 clk_disable_unprepare(atmel_port->clk); 2955 2956 return 0; 2957 2958 err_add_port: 2959 kfree(atmel_port->rx_ring.buf); 2960 atmel_port->rx_ring.buf = NULL; 2961 err_alloc_ring: 2962 if (!atmel_is_console_port(&atmel_port->uart)) { 2963 clk_put(atmel_port->clk); 2964 atmel_port->clk = NULL; 2965 } 2966 err_clear_bit: 2967 clear_bit(atmel_port->uart.line, atmel_ports_in_use); 2968 err: 2969 return ret; 2970 } 2971 2972 /* 2973 * Even if the driver is not modular, it makes sense to be able to 2974 * unbind a device: there can be many bound devices, and there are 2975 * situations where dynamic binding and unbinding can be useful. 2976 * 2977 * For example, a connected device can require a specific firmware update 2978 * protocol that needs bitbanging on IO lines, but use the regular serial 2979 * port in the normal case. 2980 */ 2981 static int atmel_serial_remove(struct platform_device *pdev) 2982 { 2983 struct uart_port *port = platform_get_drvdata(pdev); 2984 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2985 int ret = 0; 2986 2987 tasklet_kill(&atmel_port->tasklet_rx); 2988 tasklet_kill(&atmel_port->tasklet_tx); 2989 2990 device_init_wakeup(&pdev->dev, 0); 2991 2992 ret = uart_remove_one_port(&atmel_uart, port); 2993 2994 kfree(atmel_port->rx_ring.buf); 2995 2996 /* "port" is allocated statically, so we shouldn't free it */ 2997 2998 clear_bit(port->line, atmel_ports_in_use); 2999 3000 clk_put(atmel_port->clk); 3001 atmel_port->clk = NULL; 3002 pdev->dev.of_node = NULL; 3003 3004 return ret; 3005 } 3006 3007 static struct platform_driver atmel_serial_driver = { 3008 .probe = atmel_serial_probe, 3009 .remove = atmel_serial_remove, 3010 .suspend = atmel_serial_suspend, 3011 .resume = atmel_serial_resume, 3012 .driver = { 3013 .name = "atmel_usart_serial", 3014 .of_match_table = of_match_ptr(atmel_serial_dt_ids), 3015 }, 3016 }; 3017 3018 static int __init atmel_serial_init(void) 3019 { 3020 int ret; 3021 3022 ret = uart_register_driver(&atmel_uart); 3023 if (ret) 3024 return ret; 3025 3026 ret = platform_driver_register(&atmel_serial_driver); 3027 if (ret) 3028 uart_unregister_driver(&atmel_uart); 3029 3030 return ret; 3031 } 3032 device_initcall(atmel_serial_init); 3033