1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Driver for Atmel AT91 Serial ports
4  *  Copyright (C) 2003 Rick Bronson
5  *
6  *  Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8  *
9  *  DMA support added by Chip Coldwell.
10  */
11 #include <linux/circ_buf.h>
12 #include <linux/tty.h>
13 #include <linux/ioport.h>
14 #include <linux/slab.h>
15 #include <linux/init.h>
16 #include <linux/serial.h>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/console.h>
20 #include <linux/sysrq.h>
21 #include <linux/tty_flip.h>
22 #include <linux/platform_device.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/dmaengine.h>
27 #include <linux/atmel_pdc.h>
28 #include <linux/uaccess.h>
29 #include <linux/platform_data/atmel.h>
30 #include <linux/timer.h>
31 #include <linux/err.h>
32 #include <linux/irq.h>
33 #include <linux/suspend.h>
34 #include <linux/mm.h>
35 #include <linux/io.h>
36 
37 #include <asm/div64.h>
38 #include <asm/ioctls.h>
39 
40 #define PDC_BUFFER_SIZE		512
41 /* Revisit: We should calculate this based on the actual port settings */
42 #define PDC_RX_TIMEOUT		(3 * 10)		/* 3 bytes */
43 
44 /* The minium number of data FIFOs should be able to contain */
45 #define ATMEL_MIN_FIFO_SIZE	8
46 /*
47  * These two offsets are substracted from the RX FIFO size to define the RTS
48  * high and low thresholds
49  */
50 #define ATMEL_RTS_HIGH_OFFSET	16
51 #define ATMEL_RTS_LOW_OFFSET	20
52 
53 #include <linux/serial_core.h>
54 
55 #include "serial_mctrl_gpio.h"
56 #include "atmel_serial.h"
57 
58 static void atmel_start_rx(struct uart_port *port);
59 static void atmel_stop_rx(struct uart_port *port);
60 
61 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
62 
63 /* Use device name ttyAT, major 204 and minor 154-169.  This is necessary if we
64  * should coexist with the 8250 driver, such as if we have an external 16C550
65  * UART. */
66 #define SERIAL_ATMEL_MAJOR	204
67 #define MINOR_START		154
68 #define ATMEL_DEVICENAME	"ttyAT"
69 
70 #else
71 
72 /* Use device name ttyS, major 4, minor 64-68.  This is the usual serial port
73  * name, but it is legally reserved for the 8250 driver. */
74 #define SERIAL_ATMEL_MAJOR	TTY_MAJOR
75 #define MINOR_START		64
76 #define ATMEL_DEVICENAME	"ttyS"
77 
78 #endif
79 
80 #define ATMEL_ISR_PASS_LIMIT	256
81 
82 struct atmel_dma_buffer {
83 	unsigned char	*buf;
84 	dma_addr_t	dma_addr;
85 	unsigned int	dma_size;
86 	unsigned int	ofs;
87 };
88 
89 struct atmel_uart_char {
90 	u16		status;
91 	u16		ch;
92 };
93 
94 /*
95  * Be careful, the real size of the ring buffer is
96  * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
97  * can contain up to 1024 characters in PIO mode and up to 4096 characters in
98  * DMA mode.
99  */
100 #define ATMEL_SERIAL_RINGSIZE 1024
101 
102 /*
103  * at91: 6 USARTs and one DBGU port (SAM9260)
104  * samx7: 3 USARTs and 5 UARTs
105  */
106 #define ATMEL_MAX_UART		8
107 
108 /*
109  * We wrap our port structure around the generic uart_port.
110  */
111 struct atmel_uart_port {
112 	struct uart_port	uart;		/* uart */
113 	struct clk		*clk;		/* uart clock */
114 	struct clk		*gclk;		/* uart generic clock */
115 	int			may_wakeup;	/* cached value of device_may_wakeup for times we need to disable it */
116 	u32			backup_imr;	/* IMR saved during suspend */
117 	int			break_active;	/* break being received */
118 
119 	bool			use_dma_rx;	/* enable DMA receiver */
120 	bool			use_pdc_rx;	/* enable PDC receiver */
121 	short			pdc_rx_idx;	/* current PDC RX buffer */
122 	struct atmel_dma_buffer	pdc_rx[2];	/* PDC receier */
123 
124 	bool			use_dma_tx;     /* enable DMA transmitter */
125 	bool			use_pdc_tx;	/* enable PDC transmitter */
126 	struct atmel_dma_buffer	pdc_tx;		/* PDC transmitter */
127 
128 	spinlock_t			lock_tx;	/* port lock */
129 	spinlock_t			lock_rx;	/* port lock */
130 	struct dma_chan			*chan_tx;
131 	struct dma_chan			*chan_rx;
132 	struct dma_async_tx_descriptor	*desc_tx;
133 	struct dma_async_tx_descriptor	*desc_rx;
134 	dma_cookie_t			cookie_tx;
135 	dma_cookie_t			cookie_rx;
136 	struct scatterlist		sg_tx;
137 	struct scatterlist		sg_rx;
138 	struct tasklet_struct	tasklet_rx;
139 	struct tasklet_struct	tasklet_tx;
140 	atomic_t		tasklet_shutdown;
141 	unsigned int		irq_status_prev;
142 	unsigned int		tx_len;
143 
144 	struct circ_buf		rx_ring;
145 
146 	struct mctrl_gpios	*gpios;
147 	u32			backup_mode;	/* MR saved during iso7816 operations */
148 	u32			backup_brgr;	/* BRGR saved during iso7816 operations */
149 	unsigned int		tx_done_mask;
150 	u32			fifo_size;
151 	u32			rts_high;
152 	u32			rts_low;
153 	bool			ms_irq_enabled;
154 	u32			rtor;	/* address of receiver timeout register if it exists */
155 	bool			is_usart;
156 	bool			has_frac_baudrate;
157 	bool			has_hw_timer;
158 	struct timer_list	uart_timer;
159 
160 	bool			tx_stopped;
161 	bool			suspended;
162 	unsigned int		pending;
163 	unsigned int		pending_status;
164 	spinlock_t		lock_suspended;
165 
166 	bool			hd_start_rx;	/* can start RX during half-duplex operation */
167 
168 	/* ISO7816 */
169 	unsigned int		fidi_min;
170 	unsigned int		fidi_max;
171 
172 	struct {
173 		u32		cr;
174 		u32		mr;
175 		u32		imr;
176 		u32		brgr;
177 		u32		rtor;
178 		u32		ttgr;
179 		u32		fmr;
180 		u32		fimr;
181 	} cache;
182 
183 	int (*prepare_rx)(struct uart_port *port);
184 	int (*prepare_tx)(struct uart_port *port);
185 	void (*schedule_rx)(struct uart_port *port);
186 	void (*schedule_tx)(struct uart_port *port);
187 	void (*release_rx)(struct uart_port *port);
188 	void (*release_tx)(struct uart_port *port);
189 };
190 
191 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
192 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
193 
194 #if defined(CONFIG_OF)
195 static const struct of_device_id atmel_serial_dt_ids[] = {
196 	{ .compatible = "atmel,at91rm9200-usart-serial" },
197 	{ /* sentinel */ }
198 };
199 #endif
200 
201 static inline struct atmel_uart_port *
202 to_atmel_uart_port(struct uart_port *uart)
203 {
204 	return container_of(uart, struct atmel_uart_port, uart);
205 }
206 
207 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
208 {
209 	return __raw_readl(port->membase + reg);
210 }
211 
212 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
213 {
214 	__raw_writel(value, port->membase + reg);
215 }
216 
217 static inline u8 atmel_uart_read_char(struct uart_port *port)
218 {
219 	return __raw_readb(port->membase + ATMEL_US_RHR);
220 }
221 
222 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
223 {
224 	__raw_writeb(value, port->membase + ATMEL_US_THR);
225 }
226 
227 static inline int atmel_uart_is_half_duplex(struct uart_port *port)
228 {
229 	return ((port->rs485.flags & SER_RS485_ENABLED) &&
230 		!(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
231 		(port->iso7816.flags & SER_ISO7816_ENABLED);
232 }
233 
234 static inline int atmel_error_rate(int desired_value, int actual_value)
235 {
236 	return 100 - (desired_value * 100) / actual_value;
237 }
238 
239 #ifdef CONFIG_SERIAL_ATMEL_PDC
240 static bool atmel_use_pdc_rx(struct uart_port *port)
241 {
242 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
243 
244 	return atmel_port->use_pdc_rx;
245 }
246 
247 static bool atmel_use_pdc_tx(struct uart_port *port)
248 {
249 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
250 
251 	return atmel_port->use_pdc_tx;
252 }
253 #else
254 static bool atmel_use_pdc_rx(struct uart_port *port)
255 {
256 	return false;
257 }
258 
259 static bool atmel_use_pdc_tx(struct uart_port *port)
260 {
261 	return false;
262 }
263 #endif
264 
265 static bool atmel_use_dma_tx(struct uart_port *port)
266 {
267 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
268 
269 	return atmel_port->use_dma_tx;
270 }
271 
272 static bool atmel_use_dma_rx(struct uart_port *port)
273 {
274 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
275 
276 	return atmel_port->use_dma_rx;
277 }
278 
279 static bool atmel_use_fifo(struct uart_port *port)
280 {
281 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
282 
283 	return atmel_port->fifo_size;
284 }
285 
286 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
287 				   struct tasklet_struct *t)
288 {
289 	if (!atomic_read(&atmel_port->tasklet_shutdown))
290 		tasklet_schedule(t);
291 }
292 
293 /* Enable or disable the rs485 support */
294 static int atmel_config_rs485(struct uart_port *port, struct ktermios *termios,
295 			      struct serial_rs485 *rs485conf)
296 {
297 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
298 	unsigned int mode;
299 
300 	/* Disable interrupts */
301 	atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
302 
303 	mode = atmel_uart_readl(port, ATMEL_US_MR);
304 
305 	if (rs485conf->flags & SER_RS485_ENABLED) {
306 		dev_dbg(port->dev, "Setting UART to RS485\n");
307 		if (rs485conf->flags & SER_RS485_RX_DURING_TX)
308 			atmel_port->tx_done_mask = ATMEL_US_TXRDY;
309 		else
310 			atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
311 
312 		atmel_uart_writel(port, ATMEL_US_TTGR,
313 				  rs485conf->delay_rts_after_send);
314 		mode &= ~ATMEL_US_USMODE;
315 		mode |= ATMEL_US_USMODE_RS485;
316 	} else {
317 		dev_dbg(port->dev, "Setting UART to RS232\n");
318 		if (atmel_use_pdc_tx(port))
319 			atmel_port->tx_done_mask = ATMEL_US_ENDTX |
320 				ATMEL_US_TXBUFE;
321 		else
322 			atmel_port->tx_done_mask = ATMEL_US_TXRDY;
323 	}
324 	atmel_uart_writel(port, ATMEL_US_MR, mode);
325 
326 	/* Enable interrupts */
327 	atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
328 
329 	return 0;
330 }
331 
332 static unsigned int atmel_calc_cd(struct uart_port *port,
333 				  struct serial_iso7816 *iso7816conf)
334 {
335 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
336 	unsigned int cd;
337 	u64 mck_rate;
338 
339 	mck_rate = (u64)clk_get_rate(atmel_port->clk);
340 	do_div(mck_rate, iso7816conf->clk);
341 	cd = mck_rate;
342 	return cd;
343 }
344 
345 static unsigned int atmel_calc_fidi(struct uart_port *port,
346 				    struct serial_iso7816 *iso7816conf)
347 {
348 	u64 fidi = 0;
349 
350 	if (iso7816conf->sc_fi && iso7816conf->sc_di) {
351 		fidi = (u64)iso7816conf->sc_fi;
352 		do_div(fidi, iso7816conf->sc_di);
353 	}
354 	return (u32)fidi;
355 }
356 
357 /* Enable or disable the iso7816 support */
358 /* Called with interrupts disabled */
359 static int atmel_config_iso7816(struct uart_port *port,
360 				struct serial_iso7816 *iso7816conf)
361 {
362 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
363 	unsigned int mode;
364 	unsigned int cd, fidi;
365 	int ret = 0;
366 
367 	/* Disable interrupts */
368 	atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
369 
370 	mode = atmel_uart_readl(port, ATMEL_US_MR);
371 
372 	if (iso7816conf->flags & SER_ISO7816_ENABLED) {
373 		mode &= ~ATMEL_US_USMODE;
374 
375 		if (iso7816conf->tg > 255) {
376 			dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
377 			memset(iso7816conf, 0, sizeof(struct serial_iso7816));
378 			ret = -EINVAL;
379 			goto err_out;
380 		}
381 
382 		if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
383 		    == SER_ISO7816_T(0)) {
384 			mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
385 		} else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
386 			   == SER_ISO7816_T(1)) {
387 			mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
388 		} else {
389 			dev_err(port->dev, "ISO7816: Type not supported\n");
390 			memset(iso7816conf, 0, sizeof(struct serial_iso7816));
391 			ret = -EINVAL;
392 			goto err_out;
393 		}
394 
395 		mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
396 
397 		/* select mck clock, and output  */
398 		mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
399 		/* set parity for normal/inverse mode + max iterations */
400 		mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
401 
402 		cd = atmel_calc_cd(port, iso7816conf);
403 		fidi = atmel_calc_fidi(port, iso7816conf);
404 		if (fidi == 0) {
405 			dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
406 		} else if (fidi < atmel_port->fidi_min
407 			   || fidi > atmel_port->fidi_max) {
408 			dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
409 			memset(iso7816conf, 0, sizeof(struct serial_iso7816));
410 			ret = -EINVAL;
411 			goto err_out;
412 		}
413 
414 		if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
415 			/* port not yet in iso7816 mode: store configuration */
416 			atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
417 			atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
418 		}
419 
420 		atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
421 		atmel_uart_writel(port, ATMEL_US_BRGR, cd);
422 		atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
423 
424 		atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
425 		atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
426 	} else {
427 		dev_dbg(port->dev, "Setting UART back to RS232\n");
428 		/* back to last RS232 settings */
429 		mode = atmel_port->backup_mode;
430 		memset(iso7816conf, 0, sizeof(struct serial_iso7816));
431 		atmel_uart_writel(port, ATMEL_US_TTGR, 0);
432 		atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
433 		atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
434 
435 		if (atmel_use_pdc_tx(port))
436 			atmel_port->tx_done_mask = ATMEL_US_ENDTX |
437 						   ATMEL_US_TXBUFE;
438 		else
439 			atmel_port->tx_done_mask = ATMEL_US_TXRDY;
440 	}
441 
442 	port->iso7816 = *iso7816conf;
443 
444 	atmel_uart_writel(port, ATMEL_US_MR, mode);
445 
446 err_out:
447 	/* Enable interrupts */
448 	atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
449 
450 	return ret;
451 }
452 
453 /*
454  * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
455  */
456 static u_int atmel_tx_empty(struct uart_port *port)
457 {
458 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
459 
460 	if (atmel_port->tx_stopped)
461 		return TIOCSER_TEMT;
462 	return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
463 		TIOCSER_TEMT :
464 		0;
465 }
466 
467 /*
468  * Set state of the modem control output lines
469  */
470 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
471 {
472 	unsigned int control = 0;
473 	unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
474 	unsigned int rts_paused, rts_ready;
475 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
476 
477 	/* override mode to RS485 if needed, otherwise keep the current mode */
478 	if (port->rs485.flags & SER_RS485_ENABLED) {
479 		atmel_uart_writel(port, ATMEL_US_TTGR,
480 				  port->rs485.delay_rts_after_send);
481 		mode &= ~ATMEL_US_USMODE;
482 		mode |= ATMEL_US_USMODE_RS485;
483 	}
484 
485 	/* set the RTS line state according to the mode */
486 	if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
487 		/* force RTS line to high level */
488 		rts_paused = ATMEL_US_RTSEN;
489 
490 		/* give the control of the RTS line back to the hardware */
491 		rts_ready = ATMEL_US_RTSDIS;
492 	} else {
493 		/* force RTS line to high level */
494 		rts_paused = ATMEL_US_RTSDIS;
495 
496 		/* force RTS line to low level */
497 		rts_ready = ATMEL_US_RTSEN;
498 	}
499 
500 	if (mctrl & TIOCM_RTS)
501 		control |= rts_ready;
502 	else
503 		control |= rts_paused;
504 
505 	if (mctrl & TIOCM_DTR)
506 		control |= ATMEL_US_DTREN;
507 	else
508 		control |= ATMEL_US_DTRDIS;
509 
510 	atmel_uart_writel(port, ATMEL_US_CR, control);
511 
512 	mctrl_gpio_set(atmel_port->gpios, mctrl);
513 
514 	/* Local loopback mode? */
515 	mode &= ~ATMEL_US_CHMODE;
516 	if (mctrl & TIOCM_LOOP)
517 		mode |= ATMEL_US_CHMODE_LOC_LOOP;
518 	else
519 		mode |= ATMEL_US_CHMODE_NORMAL;
520 
521 	atmel_uart_writel(port, ATMEL_US_MR, mode);
522 }
523 
524 /*
525  * Get state of the modem control input lines
526  */
527 static u_int atmel_get_mctrl(struct uart_port *port)
528 {
529 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
530 	unsigned int ret = 0, status;
531 
532 	status = atmel_uart_readl(port, ATMEL_US_CSR);
533 
534 	/*
535 	 * The control signals are active low.
536 	 */
537 	if (!(status & ATMEL_US_DCD))
538 		ret |= TIOCM_CD;
539 	if (!(status & ATMEL_US_CTS))
540 		ret |= TIOCM_CTS;
541 	if (!(status & ATMEL_US_DSR))
542 		ret |= TIOCM_DSR;
543 	if (!(status & ATMEL_US_RI))
544 		ret |= TIOCM_RI;
545 
546 	return mctrl_gpio_get(atmel_port->gpios, &ret);
547 }
548 
549 /*
550  * Stop transmitting.
551  */
552 static void atmel_stop_tx(struct uart_port *port)
553 {
554 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
555 	bool is_pdc = atmel_use_pdc_tx(port);
556 	bool is_dma = is_pdc || atmel_use_dma_tx(port);
557 
558 	if (is_pdc) {
559 		/* disable PDC transmit */
560 		atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
561 	}
562 
563 	if (is_dma) {
564 		/*
565 		 * Disable the transmitter.
566 		 * This is mandatory when DMA is used, otherwise the DMA buffer
567 		 * is fully transmitted.
568 		 */
569 		atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
570 		atmel_port->tx_stopped = true;
571 	}
572 
573 	/* Disable interrupts */
574 	atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
575 
576 	if (atmel_uart_is_half_duplex(port))
577 		if (!atomic_read(&atmel_port->tasklet_shutdown))
578 			atmel_start_rx(port);
579 }
580 
581 /*
582  * Start transmitting.
583  */
584 static void atmel_start_tx(struct uart_port *port)
585 {
586 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
587 	bool is_pdc = atmel_use_pdc_tx(port);
588 	bool is_dma = is_pdc || atmel_use_dma_tx(port);
589 
590 	if (is_pdc && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
591 				       & ATMEL_PDC_TXTEN))
592 		/* The transmitter is already running.  Yes, we
593 		   really need this.*/
594 		return;
595 
596 	if (is_dma && atmel_uart_is_half_duplex(port))
597 		atmel_stop_rx(port);
598 
599 	if (is_pdc) {
600 		/* re-enable PDC transmit */
601 		atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
602 	}
603 
604 	/* Enable interrupts */
605 	atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
606 
607 	if (is_dma) {
608 		/* re-enable the transmitter */
609 		atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
610 		atmel_port->tx_stopped = false;
611 	}
612 }
613 
614 /*
615  * start receiving - port is in process of being opened.
616  */
617 static void atmel_start_rx(struct uart_port *port)
618 {
619 	/* reset status and receiver */
620 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
621 
622 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
623 
624 	if (atmel_use_pdc_rx(port)) {
625 		/* enable PDC controller */
626 		atmel_uart_writel(port, ATMEL_US_IER,
627 				  ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
628 				  port->read_status_mask);
629 		atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
630 	} else {
631 		atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
632 	}
633 }
634 
635 /*
636  * Stop receiving - port is in process of being closed.
637  */
638 static void atmel_stop_rx(struct uart_port *port)
639 {
640 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
641 
642 	if (atmel_use_pdc_rx(port)) {
643 		/* disable PDC receive */
644 		atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
645 		atmel_uart_writel(port, ATMEL_US_IDR,
646 				  ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
647 				  port->read_status_mask);
648 	} else {
649 		atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
650 	}
651 }
652 
653 /*
654  * Enable modem status interrupts
655  */
656 static void atmel_enable_ms(struct uart_port *port)
657 {
658 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
659 	uint32_t ier = 0;
660 
661 	/*
662 	 * Interrupt should not be enabled twice
663 	 */
664 	if (atmel_port->ms_irq_enabled)
665 		return;
666 
667 	atmel_port->ms_irq_enabled = true;
668 
669 	if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
670 		ier |= ATMEL_US_CTSIC;
671 
672 	if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
673 		ier |= ATMEL_US_DSRIC;
674 
675 	if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
676 		ier |= ATMEL_US_RIIC;
677 
678 	if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
679 		ier |= ATMEL_US_DCDIC;
680 
681 	atmel_uart_writel(port, ATMEL_US_IER, ier);
682 
683 	mctrl_gpio_enable_ms(atmel_port->gpios);
684 }
685 
686 /*
687  * Disable modem status interrupts
688  */
689 static void atmel_disable_ms(struct uart_port *port)
690 {
691 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
692 	uint32_t idr = 0;
693 
694 	/*
695 	 * Interrupt should not be disabled twice
696 	 */
697 	if (!atmel_port->ms_irq_enabled)
698 		return;
699 
700 	atmel_port->ms_irq_enabled = false;
701 
702 	mctrl_gpio_disable_ms(atmel_port->gpios);
703 
704 	if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
705 		idr |= ATMEL_US_CTSIC;
706 
707 	if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
708 		idr |= ATMEL_US_DSRIC;
709 
710 	if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
711 		idr |= ATMEL_US_RIIC;
712 
713 	if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
714 		idr |= ATMEL_US_DCDIC;
715 
716 	atmel_uart_writel(port, ATMEL_US_IDR, idr);
717 }
718 
719 /*
720  * Control the transmission of a break signal
721  */
722 static void atmel_break_ctl(struct uart_port *port, int break_state)
723 {
724 	if (break_state != 0)
725 		/* start break */
726 		atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
727 	else
728 		/* stop break */
729 		atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
730 }
731 
732 /*
733  * Stores the incoming character in the ring buffer
734  */
735 static void
736 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
737 		     unsigned int ch)
738 {
739 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
740 	struct circ_buf *ring = &atmel_port->rx_ring;
741 	struct atmel_uart_char *c;
742 
743 	if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
744 		/* Buffer overflow, ignore char */
745 		return;
746 
747 	c = &((struct atmel_uart_char *)ring->buf)[ring->head];
748 	c->status	= status;
749 	c->ch		= ch;
750 
751 	/* Make sure the character is stored before we update head. */
752 	smp_wmb();
753 
754 	ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
755 }
756 
757 /*
758  * Deal with parity, framing and overrun errors.
759  */
760 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
761 {
762 	/* clear error */
763 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
764 
765 	if (status & ATMEL_US_RXBRK) {
766 		/* ignore side-effect */
767 		status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
768 		port->icount.brk++;
769 	}
770 	if (status & ATMEL_US_PARE)
771 		port->icount.parity++;
772 	if (status & ATMEL_US_FRAME)
773 		port->icount.frame++;
774 	if (status & ATMEL_US_OVRE)
775 		port->icount.overrun++;
776 }
777 
778 /*
779  * Characters received (called from interrupt handler)
780  */
781 static void atmel_rx_chars(struct uart_port *port)
782 {
783 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
784 	unsigned int status, ch;
785 
786 	status = atmel_uart_readl(port, ATMEL_US_CSR);
787 	while (status & ATMEL_US_RXRDY) {
788 		ch = atmel_uart_read_char(port);
789 
790 		/*
791 		 * note that the error handling code is
792 		 * out of the main execution path
793 		 */
794 		if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
795 				       | ATMEL_US_OVRE | ATMEL_US_RXBRK)
796 			     || atmel_port->break_active)) {
797 
798 			/* clear error */
799 			atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
800 
801 			if (status & ATMEL_US_RXBRK
802 			    && !atmel_port->break_active) {
803 				atmel_port->break_active = 1;
804 				atmel_uart_writel(port, ATMEL_US_IER,
805 						  ATMEL_US_RXBRK);
806 			} else {
807 				/*
808 				 * This is either the end-of-break
809 				 * condition or we've received at
810 				 * least one character without RXBRK
811 				 * being set. In both cases, the next
812 				 * RXBRK will indicate start-of-break.
813 				 */
814 				atmel_uart_writel(port, ATMEL_US_IDR,
815 						  ATMEL_US_RXBRK);
816 				status &= ~ATMEL_US_RXBRK;
817 				atmel_port->break_active = 0;
818 			}
819 		}
820 
821 		atmel_buffer_rx_char(port, status, ch);
822 		status = atmel_uart_readl(port, ATMEL_US_CSR);
823 	}
824 
825 	atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
826 }
827 
828 /*
829  * Transmit characters (called from tasklet with TXRDY interrupt
830  * disabled)
831  */
832 static void atmel_tx_chars(struct uart_port *port)
833 {
834 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
835 	bool pending;
836 	u8 ch;
837 
838 	pending = uart_port_tx(port, ch,
839 		atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY,
840 		atmel_uart_write_char(port, ch));
841 	if (pending) {
842 		/* we still have characters to transmit, so we should continue
843 		 * transmitting them when TX is ready, regardless of
844 		 * mode or duplexity
845 		 */
846 		atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
847 
848 		/* Enable interrupts */
849 		atmel_uart_writel(port, ATMEL_US_IER,
850 				  atmel_port->tx_done_mask);
851 	} else {
852 		if (atmel_uart_is_half_duplex(port))
853 			atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
854 	}
855 }
856 
857 static void atmel_complete_tx_dma(void *arg)
858 {
859 	struct atmel_uart_port *atmel_port = arg;
860 	struct uart_port *port = &atmel_port->uart;
861 	struct circ_buf *xmit = &port->state->xmit;
862 	struct dma_chan *chan = atmel_port->chan_tx;
863 	unsigned long flags;
864 
865 	spin_lock_irqsave(&port->lock, flags);
866 
867 	if (chan)
868 		dmaengine_terminate_all(chan);
869 	uart_xmit_advance(port, atmel_port->tx_len);
870 
871 	spin_lock(&atmel_port->lock_tx);
872 	async_tx_ack(atmel_port->desc_tx);
873 	atmel_port->cookie_tx = -EINVAL;
874 	atmel_port->desc_tx = NULL;
875 	spin_unlock(&atmel_port->lock_tx);
876 
877 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
878 		uart_write_wakeup(port);
879 
880 	/*
881 	 * xmit is a circular buffer so, if we have just send data from
882 	 * xmit->tail to the end of xmit->buf, now we have to transmit the
883 	 * remaining data from the beginning of xmit->buf to xmit->head.
884 	 */
885 	if (!uart_circ_empty(xmit))
886 		atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
887 	else if (atmel_uart_is_half_duplex(port)) {
888 		/*
889 		 * DMA done, re-enable TXEMPTY and signal that we can stop
890 		 * TX and start RX for RS485
891 		 */
892 		atmel_port->hd_start_rx = true;
893 		atmel_uart_writel(port, ATMEL_US_IER,
894 				  atmel_port->tx_done_mask);
895 	}
896 
897 	spin_unlock_irqrestore(&port->lock, flags);
898 }
899 
900 static void atmel_release_tx_dma(struct uart_port *port)
901 {
902 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
903 	struct dma_chan *chan = atmel_port->chan_tx;
904 
905 	if (chan) {
906 		dmaengine_terminate_all(chan);
907 		dma_release_channel(chan);
908 		dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
909 				DMA_TO_DEVICE);
910 	}
911 
912 	atmel_port->desc_tx = NULL;
913 	atmel_port->chan_tx = NULL;
914 	atmel_port->cookie_tx = -EINVAL;
915 }
916 
917 /*
918  * Called from tasklet with TXRDY interrupt is disabled.
919  */
920 static void atmel_tx_dma(struct uart_port *port)
921 {
922 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
923 	struct circ_buf *xmit = &port->state->xmit;
924 	struct dma_chan *chan = atmel_port->chan_tx;
925 	struct dma_async_tx_descriptor *desc;
926 	struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
927 	unsigned int tx_len, part1_len, part2_len, sg_len;
928 	dma_addr_t phys_addr;
929 
930 	/* Make sure we have an idle channel */
931 	if (atmel_port->desc_tx != NULL)
932 		return;
933 
934 	if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
935 		/*
936 		 * DMA is idle now.
937 		 * Port xmit buffer is already mapped,
938 		 * and it is one page... Just adjust
939 		 * offsets and lengths. Since it is a circular buffer,
940 		 * we have to transmit till the end, and then the rest.
941 		 * Take the port lock to get a
942 		 * consistent xmit buffer state.
943 		 */
944 		tx_len = CIRC_CNT_TO_END(xmit->head,
945 					 xmit->tail,
946 					 UART_XMIT_SIZE);
947 
948 		if (atmel_port->fifo_size) {
949 			/* multi data mode */
950 			part1_len = (tx_len & ~0x3); /* DWORD access */
951 			part2_len = (tx_len & 0x3); /* BYTE access */
952 		} else {
953 			/* single data (legacy) mode */
954 			part1_len = 0;
955 			part2_len = tx_len; /* BYTE access only */
956 		}
957 
958 		sg_init_table(sgl, 2);
959 		sg_len = 0;
960 		phys_addr = sg_dma_address(sg_tx) + xmit->tail;
961 		if (part1_len) {
962 			sg = &sgl[sg_len++];
963 			sg_dma_address(sg) = phys_addr;
964 			sg_dma_len(sg) = part1_len;
965 
966 			phys_addr += part1_len;
967 		}
968 
969 		if (part2_len) {
970 			sg = &sgl[sg_len++];
971 			sg_dma_address(sg) = phys_addr;
972 			sg_dma_len(sg) = part2_len;
973 		}
974 
975 		/*
976 		 * save tx_len so atmel_complete_tx_dma() will increase
977 		 * xmit->tail correctly
978 		 */
979 		atmel_port->tx_len = tx_len;
980 
981 		desc = dmaengine_prep_slave_sg(chan,
982 					       sgl,
983 					       sg_len,
984 					       DMA_MEM_TO_DEV,
985 					       DMA_PREP_INTERRUPT |
986 					       DMA_CTRL_ACK);
987 		if (!desc) {
988 			dev_err(port->dev, "Failed to send via dma!\n");
989 			return;
990 		}
991 
992 		dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
993 
994 		atmel_port->desc_tx = desc;
995 		desc->callback = atmel_complete_tx_dma;
996 		desc->callback_param = atmel_port;
997 		atmel_port->cookie_tx = dmaengine_submit(desc);
998 		if (dma_submit_error(atmel_port->cookie_tx)) {
999 			dev_err(port->dev, "dma_submit_error %d\n",
1000 				atmel_port->cookie_tx);
1001 			return;
1002 		}
1003 
1004 		dma_async_issue_pending(chan);
1005 	}
1006 
1007 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1008 		uart_write_wakeup(port);
1009 }
1010 
1011 static int atmel_prepare_tx_dma(struct uart_port *port)
1012 {
1013 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1014 	struct device *mfd_dev = port->dev->parent;
1015 	dma_cap_mask_t		mask;
1016 	struct dma_slave_config config;
1017 	int ret, nent;
1018 
1019 	dma_cap_zero(mask);
1020 	dma_cap_set(DMA_SLAVE, mask);
1021 
1022 	atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx");
1023 	if (atmel_port->chan_tx == NULL)
1024 		goto chan_err;
1025 	dev_info(port->dev, "using %s for tx DMA transfers\n",
1026 		dma_chan_name(atmel_port->chan_tx));
1027 
1028 	spin_lock_init(&atmel_port->lock_tx);
1029 	sg_init_table(&atmel_port->sg_tx, 1);
1030 	/* UART circular tx buffer is an aligned page. */
1031 	BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
1032 	sg_set_page(&atmel_port->sg_tx,
1033 			virt_to_page(port->state->xmit.buf),
1034 			UART_XMIT_SIZE,
1035 			offset_in_page(port->state->xmit.buf));
1036 	nent = dma_map_sg(port->dev,
1037 				&atmel_port->sg_tx,
1038 				1,
1039 				DMA_TO_DEVICE);
1040 
1041 	if (!nent) {
1042 		dev_dbg(port->dev, "need to release resource of dma\n");
1043 		goto chan_err;
1044 	} else {
1045 		dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1046 			sg_dma_len(&atmel_port->sg_tx),
1047 			port->state->xmit.buf,
1048 			&sg_dma_address(&atmel_port->sg_tx));
1049 	}
1050 
1051 	/* Configure the slave DMA */
1052 	memset(&config, 0, sizeof(config));
1053 	config.direction = DMA_MEM_TO_DEV;
1054 	config.dst_addr_width = (atmel_port->fifo_size) ?
1055 				DMA_SLAVE_BUSWIDTH_4_BYTES :
1056 				DMA_SLAVE_BUSWIDTH_1_BYTE;
1057 	config.dst_addr = port->mapbase + ATMEL_US_THR;
1058 	config.dst_maxburst = 1;
1059 
1060 	ret = dmaengine_slave_config(atmel_port->chan_tx,
1061 				     &config);
1062 	if (ret) {
1063 		dev_err(port->dev, "DMA tx slave configuration failed\n");
1064 		goto chan_err;
1065 	}
1066 
1067 	return 0;
1068 
1069 chan_err:
1070 	dev_err(port->dev, "TX channel not available, switch to pio\n");
1071 	atmel_port->use_dma_tx = false;
1072 	if (atmel_port->chan_tx)
1073 		atmel_release_tx_dma(port);
1074 	return -EINVAL;
1075 }
1076 
1077 static void atmel_complete_rx_dma(void *arg)
1078 {
1079 	struct uart_port *port = arg;
1080 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1081 
1082 	atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1083 }
1084 
1085 static void atmel_release_rx_dma(struct uart_port *port)
1086 {
1087 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1088 	struct dma_chan *chan = atmel_port->chan_rx;
1089 
1090 	if (chan) {
1091 		dmaengine_terminate_all(chan);
1092 		dma_release_channel(chan);
1093 		dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1094 				DMA_FROM_DEVICE);
1095 	}
1096 
1097 	atmel_port->desc_rx = NULL;
1098 	atmel_port->chan_rx = NULL;
1099 	atmel_port->cookie_rx = -EINVAL;
1100 }
1101 
1102 static void atmel_rx_from_dma(struct uart_port *port)
1103 {
1104 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1105 	struct tty_port *tport = &port->state->port;
1106 	struct circ_buf *ring = &atmel_port->rx_ring;
1107 	struct dma_chan *chan = atmel_port->chan_rx;
1108 	struct dma_tx_state state;
1109 	enum dma_status dmastat;
1110 	size_t count;
1111 
1112 
1113 	/* Reset the UART timeout early so that we don't miss one */
1114 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1115 	dmastat = dmaengine_tx_status(chan,
1116 				atmel_port->cookie_rx,
1117 				&state);
1118 	/* Restart a new tasklet if DMA status is error */
1119 	if (dmastat == DMA_ERROR) {
1120 		dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1121 		atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1122 		atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1123 		return;
1124 	}
1125 
1126 	/* CPU claims ownership of RX DMA buffer */
1127 	dma_sync_sg_for_cpu(port->dev,
1128 			    &atmel_port->sg_rx,
1129 			    1,
1130 			    DMA_FROM_DEVICE);
1131 
1132 	/*
1133 	 * ring->head points to the end of data already written by the DMA.
1134 	 * ring->tail points to the beginning of data to be read by the
1135 	 * framework.
1136 	 * The current transfer size should not be larger than the dma buffer
1137 	 * length.
1138 	 */
1139 	ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1140 	BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1141 	/*
1142 	 * At this point ring->head may point to the first byte right after the
1143 	 * last byte of the dma buffer:
1144 	 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1145 	 *
1146 	 * However ring->tail must always points inside the dma buffer:
1147 	 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1148 	 *
1149 	 * Since we use a ring buffer, we have to handle the case
1150 	 * where head is lower than tail. In such a case, we first read from
1151 	 * tail to the end of the buffer then reset tail.
1152 	 */
1153 	if (ring->head < ring->tail) {
1154 		count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1155 
1156 		tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1157 		ring->tail = 0;
1158 		port->icount.rx += count;
1159 	}
1160 
1161 	/* Finally we read data from tail to head */
1162 	if (ring->tail < ring->head) {
1163 		count = ring->head - ring->tail;
1164 
1165 		tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1166 		/* Wrap ring->head if needed */
1167 		if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1168 			ring->head = 0;
1169 		ring->tail = ring->head;
1170 		port->icount.rx += count;
1171 	}
1172 
1173 	/* USART retreives ownership of RX DMA buffer */
1174 	dma_sync_sg_for_device(port->dev,
1175 			       &atmel_port->sg_rx,
1176 			       1,
1177 			       DMA_FROM_DEVICE);
1178 
1179 	tty_flip_buffer_push(tport);
1180 
1181 	atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1182 }
1183 
1184 static int atmel_prepare_rx_dma(struct uart_port *port)
1185 {
1186 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1187 	struct device *mfd_dev = port->dev->parent;
1188 	struct dma_async_tx_descriptor *desc;
1189 	dma_cap_mask_t		mask;
1190 	struct dma_slave_config config;
1191 	struct circ_buf		*ring;
1192 	int ret, nent;
1193 
1194 	ring = &atmel_port->rx_ring;
1195 
1196 	dma_cap_zero(mask);
1197 	dma_cap_set(DMA_CYCLIC, mask);
1198 
1199 	atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx");
1200 	if (atmel_port->chan_rx == NULL)
1201 		goto chan_err;
1202 	dev_info(port->dev, "using %s for rx DMA transfers\n",
1203 		dma_chan_name(atmel_port->chan_rx));
1204 
1205 	spin_lock_init(&atmel_port->lock_rx);
1206 	sg_init_table(&atmel_port->sg_rx, 1);
1207 	/* UART circular rx buffer is an aligned page. */
1208 	BUG_ON(!PAGE_ALIGNED(ring->buf));
1209 	sg_set_page(&atmel_port->sg_rx,
1210 		    virt_to_page(ring->buf),
1211 		    sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1212 		    offset_in_page(ring->buf));
1213 	nent = dma_map_sg(port->dev,
1214 			  &atmel_port->sg_rx,
1215 			  1,
1216 			  DMA_FROM_DEVICE);
1217 
1218 	if (!nent) {
1219 		dev_dbg(port->dev, "need to release resource of dma\n");
1220 		goto chan_err;
1221 	} else {
1222 		dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1223 			sg_dma_len(&atmel_port->sg_rx),
1224 			ring->buf,
1225 			&sg_dma_address(&atmel_port->sg_rx));
1226 	}
1227 
1228 	/* Configure the slave DMA */
1229 	memset(&config, 0, sizeof(config));
1230 	config.direction = DMA_DEV_TO_MEM;
1231 	config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1232 	config.src_addr = port->mapbase + ATMEL_US_RHR;
1233 	config.src_maxburst = 1;
1234 
1235 	ret = dmaengine_slave_config(atmel_port->chan_rx,
1236 				     &config);
1237 	if (ret) {
1238 		dev_err(port->dev, "DMA rx slave configuration failed\n");
1239 		goto chan_err;
1240 	}
1241 	/*
1242 	 * Prepare a cyclic dma transfer, assign 2 descriptors,
1243 	 * each one is half ring buffer size
1244 	 */
1245 	desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1246 					 sg_dma_address(&atmel_port->sg_rx),
1247 					 sg_dma_len(&atmel_port->sg_rx),
1248 					 sg_dma_len(&atmel_port->sg_rx)/2,
1249 					 DMA_DEV_TO_MEM,
1250 					 DMA_PREP_INTERRUPT);
1251 	if (!desc) {
1252 		dev_err(port->dev, "Preparing DMA cyclic failed\n");
1253 		goto chan_err;
1254 	}
1255 	desc->callback = atmel_complete_rx_dma;
1256 	desc->callback_param = port;
1257 	atmel_port->desc_rx = desc;
1258 	atmel_port->cookie_rx = dmaengine_submit(desc);
1259 	if (dma_submit_error(atmel_port->cookie_rx)) {
1260 		dev_err(port->dev, "dma_submit_error %d\n",
1261 			atmel_port->cookie_rx);
1262 		goto chan_err;
1263 	}
1264 
1265 	dma_async_issue_pending(atmel_port->chan_rx);
1266 
1267 	return 0;
1268 
1269 chan_err:
1270 	dev_err(port->dev, "RX channel not available, switch to pio\n");
1271 	atmel_port->use_dma_rx = false;
1272 	if (atmel_port->chan_rx)
1273 		atmel_release_rx_dma(port);
1274 	return -EINVAL;
1275 }
1276 
1277 static void atmel_uart_timer_callback(struct timer_list *t)
1278 {
1279 	struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1280 							uart_timer);
1281 	struct uart_port *port = &atmel_port->uart;
1282 
1283 	if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1284 		tasklet_schedule(&atmel_port->tasklet_rx);
1285 		mod_timer(&atmel_port->uart_timer,
1286 			  jiffies + uart_poll_timeout(port));
1287 	}
1288 }
1289 
1290 /*
1291  * receive interrupt handler.
1292  */
1293 static void
1294 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1295 {
1296 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1297 
1298 	if (atmel_use_pdc_rx(port)) {
1299 		/*
1300 		 * PDC receive. Just schedule the tasklet and let it
1301 		 * figure out the details.
1302 		 *
1303 		 * TODO: We're not handling error flags correctly at
1304 		 * the moment.
1305 		 */
1306 		if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1307 			atmel_uart_writel(port, ATMEL_US_IDR,
1308 					  (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1309 			atmel_tasklet_schedule(atmel_port,
1310 					       &atmel_port->tasklet_rx);
1311 		}
1312 
1313 		if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1314 				ATMEL_US_FRAME | ATMEL_US_PARE))
1315 			atmel_pdc_rxerr(port, pending);
1316 	}
1317 
1318 	if (atmel_use_dma_rx(port)) {
1319 		if (pending & ATMEL_US_TIMEOUT) {
1320 			atmel_uart_writel(port, ATMEL_US_IDR,
1321 					  ATMEL_US_TIMEOUT);
1322 			atmel_tasklet_schedule(atmel_port,
1323 					       &atmel_port->tasklet_rx);
1324 		}
1325 	}
1326 
1327 	/* Interrupt receive */
1328 	if (pending & ATMEL_US_RXRDY)
1329 		atmel_rx_chars(port);
1330 	else if (pending & ATMEL_US_RXBRK) {
1331 		/*
1332 		 * End of break detected. If it came along with a
1333 		 * character, atmel_rx_chars will handle it.
1334 		 */
1335 		atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1336 		atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1337 		atmel_port->break_active = 0;
1338 	}
1339 }
1340 
1341 /*
1342  * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1343  */
1344 static void
1345 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1346 {
1347 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1348 
1349 	if (pending & atmel_port->tx_done_mask) {
1350 		atmel_uart_writel(port, ATMEL_US_IDR,
1351 				  atmel_port->tx_done_mask);
1352 
1353 		/* Start RX if flag was set and FIFO is empty */
1354 		if (atmel_port->hd_start_rx) {
1355 			if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1356 					& ATMEL_US_TXEMPTY))
1357 				dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1358 
1359 			atmel_port->hd_start_rx = false;
1360 			atmel_start_rx(port);
1361 		}
1362 
1363 		atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1364 	}
1365 }
1366 
1367 /*
1368  * status flags interrupt handler.
1369  */
1370 static void
1371 atmel_handle_status(struct uart_port *port, unsigned int pending,
1372 		    unsigned int status)
1373 {
1374 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1375 	unsigned int status_change;
1376 
1377 	if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1378 				| ATMEL_US_CTSIC)) {
1379 		status_change = status ^ atmel_port->irq_status_prev;
1380 		atmel_port->irq_status_prev = status;
1381 
1382 		if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1383 					| ATMEL_US_DCD | ATMEL_US_CTS)) {
1384 			/* TODO: All reads to CSR will clear these interrupts! */
1385 			if (status_change & ATMEL_US_RI)
1386 				port->icount.rng++;
1387 			if (status_change & ATMEL_US_DSR)
1388 				port->icount.dsr++;
1389 			if (status_change & ATMEL_US_DCD)
1390 				uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1391 			if (status_change & ATMEL_US_CTS)
1392 				uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1393 
1394 			wake_up_interruptible(&port->state->port.delta_msr_wait);
1395 		}
1396 	}
1397 
1398 	if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1399 		dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
1400 }
1401 
1402 /*
1403  * Interrupt handler
1404  */
1405 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1406 {
1407 	struct uart_port *port = dev_id;
1408 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1409 	unsigned int status, pending, mask, pass_counter = 0;
1410 
1411 	spin_lock(&atmel_port->lock_suspended);
1412 
1413 	do {
1414 		status = atmel_uart_readl(port, ATMEL_US_CSR);
1415 		mask = atmel_uart_readl(port, ATMEL_US_IMR);
1416 		pending = status & mask;
1417 		if (!pending)
1418 			break;
1419 
1420 		if (atmel_port->suspended) {
1421 			atmel_port->pending |= pending;
1422 			atmel_port->pending_status = status;
1423 			atmel_uart_writel(port, ATMEL_US_IDR, mask);
1424 			pm_system_wakeup();
1425 			break;
1426 		}
1427 
1428 		atmel_handle_receive(port, pending);
1429 		atmel_handle_status(port, pending, status);
1430 		atmel_handle_transmit(port, pending);
1431 	} while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1432 
1433 	spin_unlock(&atmel_port->lock_suspended);
1434 
1435 	return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1436 }
1437 
1438 static void atmel_release_tx_pdc(struct uart_port *port)
1439 {
1440 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1441 	struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1442 
1443 	dma_unmap_single(port->dev,
1444 			 pdc->dma_addr,
1445 			 pdc->dma_size,
1446 			 DMA_TO_DEVICE);
1447 }
1448 
1449 /*
1450  * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1451  */
1452 static void atmel_tx_pdc(struct uart_port *port)
1453 {
1454 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1455 	struct circ_buf *xmit = &port->state->xmit;
1456 	struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1457 	int count;
1458 
1459 	/* nothing left to transmit? */
1460 	if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1461 		return;
1462 	uart_xmit_advance(port, pdc->ofs);
1463 	pdc->ofs = 0;
1464 
1465 	/* more to transmit - setup next transfer */
1466 
1467 	/* disable PDC transmit */
1468 	atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1469 
1470 	if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1471 		dma_sync_single_for_device(port->dev,
1472 					   pdc->dma_addr,
1473 					   pdc->dma_size,
1474 					   DMA_TO_DEVICE);
1475 
1476 		count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1477 		pdc->ofs = count;
1478 
1479 		atmel_uart_writel(port, ATMEL_PDC_TPR,
1480 				  pdc->dma_addr + xmit->tail);
1481 		atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1482 		/* re-enable PDC transmit */
1483 		atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1484 		/* Enable interrupts */
1485 		atmel_uart_writel(port, ATMEL_US_IER,
1486 				  atmel_port->tx_done_mask);
1487 	} else {
1488 		if (atmel_uart_is_half_duplex(port)) {
1489 			/* DMA done, stop TX, start RX for RS485 */
1490 			atmel_start_rx(port);
1491 		}
1492 	}
1493 
1494 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1495 		uart_write_wakeup(port);
1496 }
1497 
1498 static int atmel_prepare_tx_pdc(struct uart_port *port)
1499 {
1500 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1501 	struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1502 	struct circ_buf *xmit = &port->state->xmit;
1503 
1504 	pdc->buf = xmit->buf;
1505 	pdc->dma_addr = dma_map_single(port->dev,
1506 					pdc->buf,
1507 					UART_XMIT_SIZE,
1508 					DMA_TO_DEVICE);
1509 	pdc->dma_size = UART_XMIT_SIZE;
1510 	pdc->ofs = 0;
1511 
1512 	return 0;
1513 }
1514 
1515 static void atmel_rx_from_ring(struct uart_port *port)
1516 {
1517 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1518 	struct circ_buf *ring = &atmel_port->rx_ring;
1519 	unsigned int flg;
1520 	unsigned int status;
1521 
1522 	while (ring->head != ring->tail) {
1523 		struct atmel_uart_char c;
1524 
1525 		/* Make sure c is loaded after head. */
1526 		smp_rmb();
1527 
1528 		c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1529 
1530 		ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1531 
1532 		port->icount.rx++;
1533 		status = c.status;
1534 		flg = TTY_NORMAL;
1535 
1536 		/*
1537 		 * note that the error handling code is
1538 		 * out of the main execution path
1539 		 */
1540 		if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1541 				       | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1542 			if (status & ATMEL_US_RXBRK) {
1543 				/* ignore side-effect */
1544 				status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1545 
1546 				port->icount.brk++;
1547 				if (uart_handle_break(port))
1548 					continue;
1549 			}
1550 			if (status & ATMEL_US_PARE)
1551 				port->icount.parity++;
1552 			if (status & ATMEL_US_FRAME)
1553 				port->icount.frame++;
1554 			if (status & ATMEL_US_OVRE)
1555 				port->icount.overrun++;
1556 
1557 			status &= port->read_status_mask;
1558 
1559 			if (status & ATMEL_US_RXBRK)
1560 				flg = TTY_BREAK;
1561 			else if (status & ATMEL_US_PARE)
1562 				flg = TTY_PARITY;
1563 			else if (status & ATMEL_US_FRAME)
1564 				flg = TTY_FRAME;
1565 		}
1566 
1567 
1568 		if (uart_handle_sysrq_char(port, c.ch))
1569 			continue;
1570 
1571 		uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1572 	}
1573 
1574 	tty_flip_buffer_push(&port->state->port);
1575 }
1576 
1577 static void atmel_release_rx_pdc(struct uart_port *port)
1578 {
1579 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1580 	int i;
1581 
1582 	for (i = 0; i < 2; i++) {
1583 		struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1584 
1585 		dma_unmap_single(port->dev,
1586 				 pdc->dma_addr,
1587 				 pdc->dma_size,
1588 				 DMA_FROM_DEVICE);
1589 		kfree(pdc->buf);
1590 	}
1591 }
1592 
1593 static void atmel_rx_from_pdc(struct uart_port *port)
1594 {
1595 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1596 	struct tty_port *tport = &port->state->port;
1597 	struct atmel_dma_buffer *pdc;
1598 	int rx_idx = atmel_port->pdc_rx_idx;
1599 	unsigned int head;
1600 	unsigned int tail;
1601 	unsigned int count;
1602 
1603 	do {
1604 		/* Reset the UART timeout early so that we don't miss one */
1605 		atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1606 
1607 		pdc = &atmel_port->pdc_rx[rx_idx];
1608 		head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1609 		tail = pdc->ofs;
1610 
1611 		/* If the PDC has switched buffers, RPR won't contain
1612 		 * any address within the current buffer. Since head
1613 		 * is unsigned, we just need a one-way comparison to
1614 		 * find out.
1615 		 *
1616 		 * In this case, we just need to consume the entire
1617 		 * buffer and resubmit it for DMA. This will clear the
1618 		 * ENDRX bit as well, so that we can safely re-enable
1619 		 * all interrupts below.
1620 		 */
1621 		head = min(head, pdc->dma_size);
1622 
1623 		if (likely(head != tail)) {
1624 			dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1625 					pdc->dma_size, DMA_FROM_DEVICE);
1626 
1627 			/*
1628 			 * head will only wrap around when we recycle
1629 			 * the DMA buffer, and when that happens, we
1630 			 * explicitly set tail to 0. So head will
1631 			 * always be greater than tail.
1632 			 */
1633 			count = head - tail;
1634 
1635 			tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1636 						count);
1637 
1638 			dma_sync_single_for_device(port->dev, pdc->dma_addr,
1639 					pdc->dma_size, DMA_FROM_DEVICE);
1640 
1641 			port->icount.rx += count;
1642 			pdc->ofs = head;
1643 		}
1644 
1645 		/*
1646 		 * If the current buffer is full, we need to check if
1647 		 * the next one contains any additional data.
1648 		 */
1649 		if (head >= pdc->dma_size) {
1650 			pdc->ofs = 0;
1651 			atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1652 			atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1653 
1654 			rx_idx = !rx_idx;
1655 			atmel_port->pdc_rx_idx = rx_idx;
1656 		}
1657 	} while (head >= pdc->dma_size);
1658 
1659 	tty_flip_buffer_push(tport);
1660 
1661 	atmel_uart_writel(port, ATMEL_US_IER,
1662 			  ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1663 }
1664 
1665 static int atmel_prepare_rx_pdc(struct uart_port *port)
1666 {
1667 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1668 	int i;
1669 
1670 	for (i = 0; i < 2; i++) {
1671 		struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1672 
1673 		pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1674 		if (pdc->buf == NULL) {
1675 			if (i != 0) {
1676 				dma_unmap_single(port->dev,
1677 					atmel_port->pdc_rx[0].dma_addr,
1678 					PDC_BUFFER_SIZE,
1679 					DMA_FROM_DEVICE);
1680 				kfree(atmel_port->pdc_rx[0].buf);
1681 			}
1682 			atmel_port->use_pdc_rx = false;
1683 			return -ENOMEM;
1684 		}
1685 		pdc->dma_addr = dma_map_single(port->dev,
1686 						pdc->buf,
1687 						PDC_BUFFER_SIZE,
1688 						DMA_FROM_DEVICE);
1689 		pdc->dma_size = PDC_BUFFER_SIZE;
1690 		pdc->ofs = 0;
1691 	}
1692 
1693 	atmel_port->pdc_rx_idx = 0;
1694 
1695 	atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1696 	atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1697 
1698 	atmel_uart_writel(port, ATMEL_PDC_RNPR,
1699 			  atmel_port->pdc_rx[1].dma_addr);
1700 	atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1701 
1702 	return 0;
1703 }
1704 
1705 /*
1706  * tasklet handling tty stuff outside the interrupt handler.
1707  */
1708 static void atmel_tasklet_rx_func(struct tasklet_struct *t)
1709 {
1710 	struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1711 							  tasklet_rx);
1712 	struct uart_port *port = &atmel_port->uart;
1713 
1714 	/* The interrupt handler does not take the lock */
1715 	spin_lock(&port->lock);
1716 	atmel_port->schedule_rx(port);
1717 	spin_unlock(&port->lock);
1718 }
1719 
1720 static void atmel_tasklet_tx_func(struct tasklet_struct *t)
1721 {
1722 	struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1723 							  tasklet_tx);
1724 	struct uart_port *port = &atmel_port->uart;
1725 
1726 	/* The interrupt handler does not take the lock */
1727 	spin_lock(&port->lock);
1728 	atmel_port->schedule_tx(port);
1729 	spin_unlock(&port->lock);
1730 }
1731 
1732 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1733 				struct platform_device *pdev)
1734 {
1735 	struct device_node *np = pdev->dev.of_node;
1736 
1737 	/* DMA/PDC usage specification */
1738 	if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1739 		if (of_property_read_bool(np, "dmas")) {
1740 			atmel_port->use_dma_rx  = true;
1741 			atmel_port->use_pdc_rx  = false;
1742 		} else {
1743 			atmel_port->use_dma_rx  = false;
1744 			atmel_port->use_pdc_rx  = true;
1745 		}
1746 	} else {
1747 		atmel_port->use_dma_rx  = false;
1748 		atmel_port->use_pdc_rx  = false;
1749 	}
1750 
1751 	if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1752 		if (of_property_read_bool(np, "dmas")) {
1753 			atmel_port->use_dma_tx  = true;
1754 			atmel_port->use_pdc_tx  = false;
1755 		} else {
1756 			atmel_port->use_dma_tx  = false;
1757 			atmel_port->use_pdc_tx  = true;
1758 		}
1759 	} else {
1760 		atmel_port->use_dma_tx  = false;
1761 		atmel_port->use_pdc_tx  = false;
1762 	}
1763 }
1764 
1765 static void atmel_set_ops(struct uart_port *port)
1766 {
1767 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1768 
1769 	if (atmel_use_dma_rx(port)) {
1770 		atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1771 		atmel_port->schedule_rx = &atmel_rx_from_dma;
1772 		atmel_port->release_rx = &atmel_release_rx_dma;
1773 	} else if (atmel_use_pdc_rx(port)) {
1774 		atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1775 		atmel_port->schedule_rx = &atmel_rx_from_pdc;
1776 		atmel_port->release_rx = &atmel_release_rx_pdc;
1777 	} else {
1778 		atmel_port->prepare_rx = NULL;
1779 		atmel_port->schedule_rx = &atmel_rx_from_ring;
1780 		atmel_port->release_rx = NULL;
1781 	}
1782 
1783 	if (atmel_use_dma_tx(port)) {
1784 		atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1785 		atmel_port->schedule_tx = &atmel_tx_dma;
1786 		atmel_port->release_tx = &atmel_release_tx_dma;
1787 	} else if (atmel_use_pdc_tx(port)) {
1788 		atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1789 		atmel_port->schedule_tx = &atmel_tx_pdc;
1790 		atmel_port->release_tx = &atmel_release_tx_pdc;
1791 	} else {
1792 		atmel_port->prepare_tx = NULL;
1793 		atmel_port->schedule_tx = &atmel_tx_chars;
1794 		atmel_port->release_tx = NULL;
1795 	}
1796 }
1797 
1798 /*
1799  * Get ip name usart or uart
1800  */
1801 static void atmel_get_ip_name(struct uart_port *port)
1802 {
1803 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1804 	int name = atmel_uart_readl(port, ATMEL_US_NAME);
1805 	u32 version;
1806 	u32 usart, dbgu_uart, new_uart;
1807 	/* ASCII decoding for IP version */
1808 	usart = 0x55534152;	/* USAR(T) */
1809 	dbgu_uart = 0x44424755;	/* DBGU */
1810 	new_uart = 0x55415254;	/* UART */
1811 
1812 	/*
1813 	 * Only USART devices from at91sam9260 SOC implement fractional
1814 	 * baudrate. It is available for all asynchronous modes, with the
1815 	 * following restriction: the sampling clock's duty cycle is not
1816 	 * constant.
1817 	 */
1818 	atmel_port->has_frac_baudrate = false;
1819 	atmel_port->has_hw_timer = false;
1820 	atmel_port->is_usart = false;
1821 
1822 	if (name == new_uart) {
1823 		dev_dbg(port->dev, "Uart with hw timer");
1824 		atmel_port->has_hw_timer = true;
1825 		atmel_port->rtor = ATMEL_UA_RTOR;
1826 	} else if (name == usart) {
1827 		dev_dbg(port->dev, "Usart\n");
1828 		atmel_port->has_frac_baudrate = true;
1829 		atmel_port->has_hw_timer = true;
1830 		atmel_port->is_usart = true;
1831 		atmel_port->rtor = ATMEL_US_RTOR;
1832 		version = atmel_uart_readl(port, ATMEL_US_VERSION);
1833 		switch (version) {
1834 		case 0x814:	/* sama5d2 */
1835 			fallthrough;
1836 		case 0x701:	/* sama5d4 */
1837 			atmel_port->fidi_min = 3;
1838 			atmel_port->fidi_max = 65535;
1839 			break;
1840 		case 0x502:	/* sam9x5, sama5d3 */
1841 			atmel_port->fidi_min = 3;
1842 			atmel_port->fidi_max = 2047;
1843 			break;
1844 		default:
1845 			atmel_port->fidi_min = 1;
1846 			atmel_port->fidi_max = 2047;
1847 		}
1848 	} else if (name == dbgu_uart) {
1849 		dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1850 	} else {
1851 		/* fallback for older SoCs: use version field */
1852 		version = atmel_uart_readl(port, ATMEL_US_VERSION);
1853 		switch (version) {
1854 		case 0x302:
1855 		case 0x10213:
1856 		case 0x10302:
1857 			dev_dbg(port->dev, "This version is usart\n");
1858 			atmel_port->has_frac_baudrate = true;
1859 			atmel_port->has_hw_timer = true;
1860 			atmel_port->is_usart = true;
1861 			atmel_port->rtor = ATMEL_US_RTOR;
1862 			break;
1863 		case 0x203:
1864 		case 0x10202:
1865 			dev_dbg(port->dev, "This version is uart\n");
1866 			break;
1867 		default:
1868 			dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1869 		}
1870 	}
1871 }
1872 
1873 /*
1874  * Perform initialization and enable port for reception
1875  */
1876 static int atmel_startup(struct uart_port *port)
1877 {
1878 	struct platform_device *pdev = to_platform_device(port->dev);
1879 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1880 	int retval;
1881 
1882 	/*
1883 	 * Ensure that no interrupts are enabled otherwise when
1884 	 * request_irq() is called we could get stuck trying to
1885 	 * handle an unexpected interrupt
1886 	 */
1887 	atmel_uart_writel(port, ATMEL_US_IDR, -1);
1888 	atmel_port->ms_irq_enabled = false;
1889 
1890 	/*
1891 	 * Allocate the IRQ
1892 	 */
1893 	retval = request_irq(port->irq, atmel_interrupt,
1894 			     IRQF_SHARED | IRQF_COND_SUSPEND,
1895 			     dev_name(&pdev->dev), port);
1896 	if (retval) {
1897 		dev_err(port->dev, "atmel_startup - Can't get irq\n");
1898 		return retval;
1899 	}
1900 
1901 	atomic_set(&atmel_port->tasklet_shutdown, 0);
1902 	tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func);
1903 	tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func);
1904 
1905 	/*
1906 	 * Initialize DMA (if necessary)
1907 	 */
1908 	atmel_init_property(atmel_port, pdev);
1909 	atmel_set_ops(port);
1910 
1911 	if (atmel_port->prepare_rx) {
1912 		retval = atmel_port->prepare_rx(port);
1913 		if (retval < 0)
1914 			atmel_set_ops(port);
1915 	}
1916 
1917 	if (atmel_port->prepare_tx) {
1918 		retval = atmel_port->prepare_tx(port);
1919 		if (retval < 0)
1920 			atmel_set_ops(port);
1921 	}
1922 
1923 	/*
1924 	 * Enable FIFO when available
1925 	 */
1926 	if (atmel_port->fifo_size) {
1927 		unsigned int txrdym = ATMEL_US_ONE_DATA;
1928 		unsigned int rxrdym = ATMEL_US_ONE_DATA;
1929 		unsigned int fmr;
1930 
1931 		atmel_uart_writel(port, ATMEL_US_CR,
1932 				  ATMEL_US_FIFOEN |
1933 				  ATMEL_US_RXFCLR |
1934 				  ATMEL_US_TXFLCLR);
1935 
1936 		if (atmel_use_dma_tx(port))
1937 			txrdym = ATMEL_US_FOUR_DATA;
1938 
1939 		fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1940 		if (atmel_port->rts_high &&
1941 		    atmel_port->rts_low)
1942 			fmr |=	ATMEL_US_FRTSC |
1943 				ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1944 				ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1945 
1946 		atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1947 	}
1948 
1949 	/* Save current CSR for comparison in atmel_tasklet_func() */
1950 	atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
1951 
1952 	/*
1953 	 * Finally, enable the serial port
1954 	 */
1955 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1956 	/* enable xmit & rcvr */
1957 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1958 	atmel_port->tx_stopped = false;
1959 
1960 	timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1961 
1962 	if (atmel_use_pdc_rx(port)) {
1963 		/* set UART timeout */
1964 		if (!atmel_port->has_hw_timer) {
1965 			mod_timer(&atmel_port->uart_timer,
1966 					jiffies + uart_poll_timeout(port));
1967 		/* set USART timeout */
1968 		} else {
1969 			atmel_uart_writel(port, atmel_port->rtor,
1970 					  PDC_RX_TIMEOUT);
1971 			atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1972 
1973 			atmel_uart_writel(port, ATMEL_US_IER,
1974 					  ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1975 		}
1976 		/* enable PDC controller */
1977 		atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1978 	} else if (atmel_use_dma_rx(port)) {
1979 		/* set UART timeout */
1980 		if (!atmel_port->has_hw_timer) {
1981 			mod_timer(&atmel_port->uart_timer,
1982 					jiffies + uart_poll_timeout(port));
1983 		/* set USART timeout */
1984 		} else {
1985 			atmel_uart_writel(port, atmel_port->rtor,
1986 					  PDC_RX_TIMEOUT);
1987 			atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1988 
1989 			atmel_uart_writel(port, ATMEL_US_IER,
1990 					  ATMEL_US_TIMEOUT);
1991 		}
1992 	} else {
1993 		/* enable receive only */
1994 		atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1995 	}
1996 
1997 	return 0;
1998 }
1999 
2000 /*
2001  * Flush any TX data submitted for DMA. Called when the TX circular
2002  * buffer is reset.
2003  */
2004 static void atmel_flush_buffer(struct uart_port *port)
2005 {
2006 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2007 
2008 	if (atmel_use_pdc_tx(port)) {
2009 		atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
2010 		atmel_port->pdc_tx.ofs = 0;
2011 	}
2012 	/*
2013 	 * in uart_flush_buffer(), the xmit circular buffer has just
2014 	 * been cleared, so we have to reset tx_len accordingly.
2015 	 */
2016 	atmel_port->tx_len = 0;
2017 }
2018 
2019 /*
2020  * Disable the port
2021  */
2022 static void atmel_shutdown(struct uart_port *port)
2023 {
2024 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2025 
2026 	/* Disable modem control lines interrupts */
2027 	atmel_disable_ms(port);
2028 
2029 	/* Disable interrupts at device level */
2030 	atmel_uart_writel(port, ATMEL_US_IDR, -1);
2031 
2032 	/* Prevent spurious interrupts from scheduling the tasklet */
2033 	atomic_inc(&atmel_port->tasklet_shutdown);
2034 
2035 	/*
2036 	 * Prevent any tasklets being scheduled during
2037 	 * cleanup
2038 	 */
2039 	del_timer_sync(&atmel_port->uart_timer);
2040 
2041 	/* Make sure that no interrupt is on the fly */
2042 	synchronize_irq(port->irq);
2043 
2044 	/*
2045 	 * Clear out any scheduled tasklets before
2046 	 * we destroy the buffers
2047 	 */
2048 	tasklet_kill(&atmel_port->tasklet_rx);
2049 	tasklet_kill(&atmel_port->tasklet_tx);
2050 
2051 	/*
2052 	 * Ensure everything is stopped and
2053 	 * disable port and break condition.
2054 	 */
2055 	atmel_stop_rx(port);
2056 	atmel_stop_tx(port);
2057 
2058 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2059 
2060 	/*
2061 	 * Shut-down the DMA.
2062 	 */
2063 	if (atmel_port->release_rx)
2064 		atmel_port->release_rx(port);
2065 	if (atmel_port->release_tx)
2066 		atmel_port->release_tx(port);
2067 
2068 	/*
2069 	 * Reset ring buffer pointers
2070 	 */
2071 	atmel_port->rx_ring.head = 0;
2072 	atmel_port->rx_ring.tail = 0;
2073 
2074 	/*
2075 	 * Free the interrupts
2076 	 */
2077 	free_irq(port->irq, port);
2078 
2079 	atmel_flush_buffer(port);
2080 }
2081 
2082 /*
2083  * Power / Clock management.
2084  */
2085 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2086 			    unsigned int oldstate)
2087 {
2088 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2089 
2090 	switch (state) {
2091 	case UART_PM_STATE_ON:
2092 		/*
2093 		 * Enable the peripheral clock for this serial port.
2094 		 * This is called on uart_open() or a resume event.
2095 		 */
2096 		clk_prepare_enable(atmel_port->clk);
2097 
2098 		/* re-enable interrupts if we disabled some on suspend */
2099 		atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2100 		break;
2101 	case UART_PM_STATE_OFF:
2102 		/* Back up the interrupt mask and disable all interrupts */
2103 		atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2104 		atmel_uart_writel(port, ATMEL_US_IDR, -1);
2105 
2106 		/*
2107 		 * Disable the peripheral clock for this serial port.
2108 		 * This is called on uart_close() or a suspend event.
2109 		 */
2110 		clk_disable_unprepare(atmel_port->clk);
2111 		if (__clk_is_enabled(atmel_port->gclk))
2112 			clk_disable_unprepare(atmel_port->gclk);
2113 		break;
2114 	default:
2115 		dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2116 	}
2117 }
2118 
2119 /*
2120  * Change the port parameters
2121  */
2122 static void atmel_set_termios(struct uart_port *port,
2123 			      struct ktermios *termios,
2124 			      const struct ktermios *old)
2125 {
2126 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2127 	unsigned long flags;
2128 	unsigned int old_mode, mode, imr, quot, div, cd, fp = 0;
2129 	unsigned int baud, actual_baud, gclk_rate;
2130 	int ret;
2131 
2132 	/* save the current mode register */
2133 	mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2134 
2135 	/* reset the mode, clock divisor, parity, stop bits and data size */
2136 	if (atmel_port->is_usart)
2137 		mode &= ~(ATMEL_US_NBSTOP | ATMEL_US_PAR | ATMEL_US_CHRL |
2138 			  ATMEL_US_USCLKS | ATMEL_US_USMODE);
2139 	else
2140 		mode &= ~(ATMEL_UA_BRSRCCK | ATMEL_US_PAR | ATMEL_UA_FILTER);
2141 
2142 	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2143 
2144 	/* byte size */
2145 	switch (termios->c_cflag & CSIZE) {
2146 	case CS5:
2147 		mode |= ATMEL_US_CHRL_5;
2148 		break;
2149 	case CS6:
2150 		mode |= ATMEL_US_CHRL_6;
2151 		break;
2152 	case CS7:
2153 		mode |= ATMEL_US_CHRL_7;
2154 		break;
2155 	default:
2156 		mode |= ATMEL_US_CHRL_8;
2157 		break;
2158 	}
2159 
2160 	/* stop bits */
2161 	if (termios->c_cflag & CSTOPB)
2162 		mode |= ATMEL_US_NBSTOP_2;
2163 
2164 	/* parity */
2165 	if (termios->c_cflag & PARENB) {
2166 		/* Mark or Space parity */
2167 		if (termios->c_cflag & CMSPAR) {
2168 			if (termios->c_cflag & PARODD)
2169 				mode |= ATMEL_US_PAR_MARK;
2170 			else
2171 				mode |= ATMEL_US_PAR_SPACE;
2172 		} else if (termios->c_cflag & PARODD)
2173 			mode |= ATMEL_US_PAR_ODD;
2174 		else
2175 			mode |= ATMEL_US_PAR_EVEN;
2176 	} else
2177 		mode |= ATMEL_US_PAR_NONE;
2178 
2179 	spin_lock_irqsave(&port->lock, flags);
2180 
2181 	port->read_status_mask = ATMEL_US_OVRE;
2182 	if (termios->c_iflag & INPCK)
2183 		port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2184 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2185 		port->read_status_mask |= ATMEL_US_RXBRK;
2186 
2187 	if (atmel_use_pdc_rx(port))
2188 		/* need to enable error interrupts */
2189 		atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2190 
2191 	/*
2192 	 * Characters to ignore
2193 	 */
2194 	port->ignore_status_mask = 0;
2195 	if (termios->c_iflag & IGNPAR)
2196 		port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2197 	if (termios->c_iflag & IGNBRK) {
2198 		port->ignore_status_mask |= ATMEL_US_RXBRK;
2199 		/*
2200 		 * If we're ignoring parity and break indicators,
2201 		 * ignore overruns too (for real raw support).
2202 		 */
2203 		if (termios->c_iflag & IGNPAR)
2204 			port->ignore_status_mask |= ATMEL_US_OVRE;
2205 	}
2206 	/* TODO: Ignore all characters if CREAD is set.*/
2207 
2208 	/* update the per-port timeout */
2209 	uart_update_timeout(port, termios->c_cflag, baud);
2210 
2211 	/*
2212 	 * save/disable interrupts. The tty layer will ensure that the
2213 	 * transmitter is empty if requested by the caller, so there's
2214 	 * no need to wait for it here.
2215 	 */
2216 	imr = atmel_uart_readl(port, ATMEL_US_IMR);
2217 	atmel_uart_writel(port, ATMEL_US_IDR, -1);
2218 
2219 	/* disable receiver and transmitter */
2220 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2221 	atmel_port->tx_stopped = true;
2222 
2223 	/* mode */
2224 	if (port->rs485.flags & SER_RS485_ENABLED) {
2225 		atmel_uart_writel(port, ATMEL_US_TTGR,
2226 				  port->rs485.delay_rts_after_send);
2227 		mode |= ATMEL_US_USMODE_RS485;
2228 	} else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2229 		atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2230 		/* select mck clock, and output  */
2231 		mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2232 		/* set max iterations */
2233 		mode |= ATMEL_US_MAX_ITER(3);
2234 		if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2235 				== SER_ISO7816_T(0))
2236 			mode |= ATMEL_US_USMODE_ISO7816_T0;
2237 		else
2238 			mode |= ATMEL_US_USMODE_ISO7816_T1;
2239 	} else if (termios->c_cflag & CRTSCTS) {
2240 		/* RS232 with hardware handshake (RTS/CTS) */
2241 		if (atmel_use_fifo(port) &&
2242 		    !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2243 			/*
2244 			 * with ATMEL_US_USMODE_HWHS set, the controller will
2245 			 * be able to drive the RTS pin high/low when the RX
2246 			 * FIFO is above RXFTHRES/below RXFTHRES2.
2247 			 * It will also disable the transmitter when the CTS
2248 			 * pin is high.
2249 			 * This mode is not activated if CTS pin is a GPIO
2250 			 * because in this case, the transmitter is always
2251 			 * disabled (there must be an internal pull-up
2252 			 * responsible for this behaviour).
2253 			 * If the RTS pin is a GPIO, the controller won't be
2254 			 * able to drive it according to the FIFO thresholds,
2255 			 * but it will be handled by the driver.
2256 			 */
2257 			mode |= ATMEL_US_USMODE_HWHS;
2258 		} else {
2259 			/*
2260 			 * For platforms without FIFO, the flow control is
2261 			 * handled by the driver.
2262 			 */
2263 			mode |= ATMEL_US_USMODE_NORMAL;
2264 		}
2265 	} else {
2266 		/* RS232 without hadware handshake */
2267 		mode |= ATMEL_US_USMODE_NORMAL;
2268 	}
2269 
2270 	/*
2271 	 * Set the baud rate:
2272 	 * Fractional baudrate allows to setup output frequency more
2273 	 * accurately. This feature is enabled only when using normal mode.
2274 	 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2275 	 * Currently, OVER is always set to 0 so we get
2276 	 * baudrate = selected clock / (16 * (CD + FP / 8))
2277 	 * then
2278 	 * 8 CD + FP = selected clock / (2 * baudrate)
2279 	 */
2280 	if (atmel_port->has_frac_baudrate) {
2281 		div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2282 		cd = div >> 3;
2283 		fp = div & ATMEL_US_FP_MASK;
2284 	} else {
2285 		cd = uart_get_divisor(port, baud);
2286 	}
2287 
2288 	/*
2289 	 * If the current value of the Clock Divisor surpasses the 16 bit
2290 	 * ATMEL_US_CD mask and the IP is USART, switch to the Peripheral
2291 	 * Clock implicitly divided by 8.
2292 	 * If the IP is UART however, keep the highest possible value for
2293 	 * the CD and avoid needless division of CD, since UART IP's do not
2294 	 * support implicit division of the Peripheral Clock.
2295 	 */
2296 	if (atmel_port->is_usart && cd > ATMEL_US_CD) {
2297 		cd /= 8;
2298 		mode |= ATMEL_US_USCLKS_MCK_DIV8;
2299 	} else {
2300 		cd = min_t(unsigned int, cd, ATMEL_US_CD);
2301 	}
2302 
2303 	/*
2304 	 * If there is no Fractional Part, there is a high chance that
2305 	 * we may be able to generate a baudrate closer to the desired one
2306 	 * if we use the GCLK as the clock source driving the baudrate
2307 	 * generator.
2308 	 */
2309 	if (!atmel_port->has_frac_baudrate) {
2310 		if (__clk_is_enabled(atmel_port->gclk))
2311 			clk_disable_unprepare(atmel_port->gclk);
2312 		gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud);
2313 		actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd);
2314 		if (gclk_rate && abs(atmel_error_rate(baud, actual_baud)) >
2315 		    abs(atmel_error_rate(baud, gclk_rate / 16))) {
2316 			clk_set_rate(atmel_port->gclk, 16 * baud);
2317 			ret = clk_prepare_enable(atmel_port->gclk);
2318 			if (ret)
2319 				goto gclk_fail;
2320 
2321 			if (atmel_port->is_usart) {
2322 				mode &= ~ATMEL_US_USCLKS;
2323 				mode |= ATMEL_US_USCLKS_GCLK;
2324 			} else {
2325 				mode |= ATMEL_UA_BRSRCCK;
2326 			}
2327 
2328 			/*
2329 			 * Set the Clock Divisor for GCLK to 1.
2330 			 * Since we were able to generate the smallest
2331 			 * multiple of the desired baudrate times 16,
2332 			 * then we surely can generate a bigger multiple
2333 			 * with the exact error rate for an equally increased
2334 			 * CD. Thus no need to take into account
2335 			 * a higher value for CD.
2336 			 */
2337 			cd = 1;
2338 		}
2339 	}
2340 
2341 gclk_fail:
2342 	quot = cd | fp << ATMEL_US_FP_OFFSET;
2343 
2344 	if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2345 		atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2346 
2347 	/* set the mode, clock divisor, parity, stop bits and data size */
2348 	atmel_uart_writel(port, ATMEL_US_MR, mode);
2349 
2350 	/*
2351 	 * when switching the mode, set the RTS line state according to the
2352 	 * new mode, otherwise keep the former state
2353 	 */
2354 	if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2355 		unsigned int rts_state;
2356 
2357 		if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2358 			/* let the hardware control the RTS line */
2359 			rts_state = ATMEL_US_RTSDIS;
2360 		} else {
2361 			/* force RTS line to low level */
2362 			rts_state = ATMEL_US_RTSEN;
2363 		}
2364 
2365 		atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2366 	}
2367 
2368 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2369 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2370 	atmel_port->tx_stopped = false;
2371 
2372 	/* restore interrupts */
2373 	atmel_uart_writel(port, ATMEL_US_IER, imr);
2374 
2375 	/* CTS flow-control and modem-status interrupts */
2376 	if (UART_ENABLE_MS(port, termios->c_cflag))
2377 		atmel_enable_ms(port);
2378 	else
2379 		atmel_disable_ms(port);
2380 
2381 	spin_unlock_irqrestore(&port->lock, flags);
2382 }
2383 
2384 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2385 {
2386 	if (termios->c_line == N_PPS) {
2387 		port->flags |= UPF_HARDPPS_CD;
2388 		spin_lock_irq(&port->lock);
2389 		atmel_enable_ms(port);
2390 		spin_unlock_irq(&port->lock);
2391 	} else {
2392 		port->flags &= ~UPF_HARDPPS_CD;
2393 		if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2394 			spin_lock_irq(&port->lock);
2395 			atmel_disable_ms(port);
2396 			spin_unlock_irq(&port->lock);
2397 		}
2398 	}
2399 }
2400 
2401 /*
2402  * Return string describing the specified port
2403  */
2404 static const char *atmel_type(struct uart_port *port)
2405 {
2406 	return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2407 }
2408 
2409 /*
2410  * Release the memory region(s) being used by 'port'.
2411  */
2412 static void atmel_release_port(struct uart_port *port)
2413 {
2414 	struct platform_device *mpdev = to_platform_device(port->dev->parent);
2415 	int size = resource_size(mpdev->resource);
2416 
2417 	release_mem_region(port->mapbase, size);
2418 
2419 	if (port->flags & UPF_IOREMAP) {
2420 		iounmap(port->membase);
2421 		port->membase = NULL;
2422 	}
2423 }
2424 
2425 /*
2426  * Request the memory region(s) being used by 'port'.
2427  */
2428 static int atmel_request_port(struct uart_port *port)
2429 {
2430 	struct platform_device *mpdev = to_platform_device(port->dev->parent);
2431 	int size = resource_size(mpdev->resource);
2432 
2433 	if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2434 		return -EBUSY;
2435 
2436 	if (port->flags & UPF_IOREMAP) {
2437 		port->membase = ioremap(port->mapbase, size);
2438 		if (port->membase == NULL) {
2439 			release_mem_region(port->mapbase, size);
2440 			return -ENOMEM;
2441 		}
2442 	}
2443 
2444 	return 0;
2445 }
2446 
2447 /*
2448  * Configure/autoconfigure the port.
2449  */
2450 static void atmel_config_port(struct uart_port *port, int flags)
2451 {
2452 	if (flags & UART_CONFIG_TYPE) {
2453 		port->type = PORT_ATMEL;
2454 		atmel_request_port(port);
2455 	}
2456 }
2457 
2458 /*
2459  * Verify the new serial_struct (for TIOCSSERIAL).
2460  */
2461 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2462 {
2463 	int ret = 0;
2464 	if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2465 		ret = -EINVAL;
2466 	if (port->irq != ser->irq)
2467 		ret = -EINVAL;
2468 	if (ser->io_type != SERIAL_IO_MEM)
2469 		ret = -EINVAL;
2470 	if (port->uartclk / 16 != ser->baud_base)
2471 		ret = -EINVAL;
2472 	if (port->mapbase != (unsigned long)ser->iomem_base)
2473 		ret = -EINVAL;
2474 	if (port->iobase != ser->port)
2475 		ret = -EINVAL;
2476 	if (ser->hub6 != 0)
2477 		ret = -EINVAL;
2478 	return ret;
2479 }
2480 
2481 #ifdef CONFIG_CONSOLE_POLL
2482 static int atmel_poll_get_char(struct uart_port *port)
2483 {
2484 	while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2485 		cpu_relax();
2486 
2487 	return atmel_uart_read_char(port);
2488 }
2489 
2490 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2491 {
2492 	while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2493 		cpu_relax();
2494 
2495 	atmel_uart_write_char(port, ch);
2496 }
2497 #endif
2498 
2499 static const struct uart_ops atmel_pops = {
2500 	.tx_empty	= atmel_tx_empty,
2501 	.set_mctrl	= atmel_set_mctrl,
2502 	.get_mctrl	= atmel_get_mctrl,
2503 	.stop_tx	= atmel_stop_tx,
2504 	.start_tx	= atmel_start_tx,
2505 	.stop_rx	= atmel_stop_rx,
2506 	.enable_ms	= atmel_enable_ms,
2507 	.break_ctl	= atmel_break_ctl,
2508 	.startup	= atmel_startup,
2509 	.shutdown	= atmel_shutdown,
2510 	.flush_buffer	= atmel_flush_buffer,
2511 	.set_termios	= atmel_set_termios,
2512 	.set_ldisc	= atmel_set_ldisc,
2513 	.type		= atmel_type,
2514 	.release_port	= atmel_release_port,
2515 	.request_port	= atmel_request_port,
2516 	.config_port	= atmel_config_port,
2517 	.verify_port	= atmel_verify_port,
2518 	.pm		= atmel_serial_pm,
2519 #ifdef CONFIG_CONSOLE_POLL
2520 	.poll_get_char	= atmel_poll_get_char,
2521 	.poll_put_char	= atmel_poll_put_char,
2522 #endif
2523 };
2524 
2525 static const struct serial_rs485 atmel_rs485_supported = {
2526 	.flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND | SER_RS485_RX_DURING_TX,
2527 	.delay_rts_before_send = 1,
2528 	.delay_rts_after_send = 1,
2529 };
2530 
2531 /*
2532  * Configure the port from the platform device resource info.
2533  */
2534 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2535 				      struct platform_device *pdev)
2536 {
2537 	int ret;
2538 	struct uart_port *port = &atmel_port->uart;
2539 	struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
2540 
2541 	atmel_init_property(atmel_port, pdev);
2542 	atmel_set_ops(port);
2543 
2544 	port->iotype		= UPIO_MEM;
2545 	port->flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2546 	port->ops		= &atmel_pops;
2547 	port->fifosize		= 1;
2548 	port->dev		= &pdev->dev;
2549 	port->mapbase		= mpdev->resource[0].start;
2550 	port->irq		= platform_get_irq(mpdev, 0);
2551 	port->rs485_config	= atmel_config_rs485;
2552 	port->rs485_supported	= atmel_rs485_supported;
2553 	port->iso7816_config	= atmel_config_iso7816;
2554 	port->membase		= NULL;
2555 
2556 	memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2557 
2558 	ret = uart_get_rs485_mode(port);
2559 	if (ret)
2560 		return ret;
2561 
2562 	port->uartclk = clk_get_rate(atmel_port->clk);
2563 
2564 	/*
2565 	 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2566 	 * ENDTX|TXBUFE
2567 	 */
2568 	if (atmel_uart_is_half_duplex(port))
2569 		atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2570 	else if (atmel_use_pdc_tx(port)) {
2571 		port->fifosize = PDC_BUFFER_SIZE;
2572 		atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2573 	} else {
2574 		atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2575 	}
2576 
2577 	return 0;
2578 }
2579 
2580 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2581 static void atmel_console_putchar(struct uart_port *port, unsigned char ch)
2582 {
2583 	while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2584 		cpu_relax();
2585 	atmel_uart_write_char(port, ch);
2586 }
2587 
2588 /*
2589  * Interrupts are disabled on entering
2590  */
2591 static void atmel_console_write(struct console *co, const char *s, u_int count)
2592 {
2593 	struct uart_port *port = &atmel_ports[co->index].uart;
2594 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2595 	unsigned int status, imr;
2596 	unsigned int pdc_tx;
2597 
2598 	/*
2599 	 * First, save IMR and then disable interrupts
2600 	 */
2601 	imr = atmel_uart_readl(port, ATMEL_US_IMR);
2602 	atmel_uart_writel(port, ATMEL_US_IDR,
2603 			  ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2604 
2605 	/* Store PDC transmit status and disable it */
2606 	pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2607 	atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2608 
2609 	/* Make sure that tx path is actually able to send characters */
2610 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2611 	atmel_port->tx_stopped = false;
2612 
2613 	uart_console_write(port, s, count, atmel_console_putchar);
2614 
2615 	/*
2616 	 * Finally, wait for transmitter to become empty
2617 	 * and restore IMR
2618 	 */
2619 	do {
2620 		status = atmel_uart_readl(port, ATMEL_US_CSR);
2621 	} while (!(status & ATMEL_US_TXRDY));
2622 
2623 	/* Restore PDC transmit status */
2624 	if (pdc_tx)
2625 		atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2626 
2627 	/* set interrupts back the way they were */
2628 	atmel_uart_writel(port, ATMEL_US_IER, imr);
2629 }
2630 
2631 /*
2632  * If the port was already initialised (eg, by a boot loader),
2633  * try to determine the current setup.
2634  */
2635 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2636 					     int *parity, int *bits)
2637 {
2638 	unsigned int mr, quot;
2639 
2640 	/*
2641 	 * If the baud rate generator isn't running, the port wasn't
2642 	 * initialized by the boot loader.
2643 	 */
2644 	quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2645 	if (!quot)
2646 		return;
2647 
2648 	mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2649 	if (mr == ATMEL_US_CHRL_8)
2650 		*bits = 8;
2651 	else
2652 		*bits = 7;
2653 
2654 	mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2655 	if (mr == ATMEL_US_PAR_EVEN)
2656 		*parity = 'e';
2657 	else if (mr == ATMEL_US_PAR_ODD)
2658 		*parity = 'o';
2659 
2660 	*baud = port->uartclk / (16 * quot);
2661 }
2662 
2663 static int __init atmel_console_setup(struct console *co, char *options)
2664 {
2665 	struct uart_port *port = &atmel_ports[co->index].uart;
2666 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2667 	int baud = 115200;
2668 	int bits = 8;
2669 	int parity = 'n';
2670 	int flow = 'n';
2671 
2672 	if (port->membase == NULL) {
2673 		/* Port not initialized yet - delay setup */
2674 		return -ENODEV;
2675 	}
2676 
2677 	atmel_uart_writel(port, ATMEL_US_IDR, -1);
2678 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2679 	atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2680 	atmel_port->tx_stopped = false;
2681 
2682 	if (options)
2683 		uart_parse_options(options, &baud, &parity, &bits, &flow);
2684 	else
2685 		atmel_console_get_options(port, &baud, &parity, &bits);
2686 
2687 	return uart_set_options(port, co, baud, parity, bits, flow);
2688 }
2689 
2690 static struct uart_driver atmel_uart;
2691 
2692 static struct console atmel_console = {
2693 	.name		= ATMEL_DEVICENAME,
2694 	.write		= atmel_console_write,
2695 	.device		= uart_console_device,
2696 	.setup		= atmel_console_setup,
2697 	.flags		= CON_PRINTBUFFER,
2698 	.index		= -1,
2699 	.data		= &atmel_uart,
2700 };
2701 
2702 static void atmel_serial_early_write(struct console *con, const char *s,
2703 				     unsigned int n)
2704 {
2705 	struct earlycon_device *dev = con->data;
2706 
2707 	uart_console_write(&dev->port, s, n, atmel_console_putchar);
2708 }
2709 
2710 static int __init atmel_early_console_setup(struct earlycon_device *device,
2711 					    const char *options)
2712 {
2713 	if (!device->port.membase)
2714 		return -ENODEV;
2715 
2716 	device->con->write = atmel_serial_early_write;
2717 
2718 	return 0;
2719 }
2720 
2721 OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91rm9200-usart",
2722 		    atmel_early_console_setup);
2723 OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91sam9260-usart",
2724 		    atmel_early_console_setup);
2725 
2726 #define ATMEL_CONSOLE_DEVICE	(&atmel_console)
2727 
2728 #else
2729 #define ATMEL_CONSOLE_DEVICE	NULL
2730 #endif
2731 
2732 static struct uart_driver atmel_uart = {
2733 	.owner		= THIS_MODULE,
2734 	.driver_name	= "atmel_serial",
2735 	.dev_name	= ATMEL_DEVICENAME,
2736 	.major		= SERIAL_ATMEL_MAJOR,
2737 	.minor		= MINOR_START,
2738 	.nr		= ATMEL_MAX_UART,
2739 	.cons		= ATMEL_CONSOLE_DEVICE,
2740 };
2741 
2742 static bool atmel_serial_clk_will_stop(void)
2743 {
2744 #ifdef CONFIG_ARCH_AT91
2745 	return at91_suspend_entering_slow_clock();
2746 #else
2747 	return false;
2748 #endif
2749 }
2750 
2751 static int __maybe_unused atmel_serial_suspend(struct device *dev)
2752 {
2753 	struct uart_port *port = dev_get_drvdata(dev);
2754 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2755 
2756 	if (uart_console(port) && console_suspend_enabled) {
2757 		/* Drain the TX shifter */
2758 		while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2759 			 ATMEL_US_TXEMPTY))
2760 			cpu_relax();
2761 	}
2762 
2763 	if (uart_console(port) && !console_suspend_enabled) {
2764 		/* Cache register values as we won't get a full shutdown/startup
2765 		 * cycle
2766 		 */
2767 		atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2768 		atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2769 		atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2770 		atmel_port->cache.rtor = atmel_uart_readl(port,
2771 							  atmel_port->rtor);
2772 		atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2773 		atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2774 		atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2775 	}
2776 
2777 	/* we can not wake up if we're running on slow clock */
2778 	atmel_port->may_wakeup = device_may_wakeup(dev);
2779 	if (atmel_serial_clk_will_stop()) {
2780 		unsigned long flags;
2781 
2782 		spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2783 		atmel_port->suspended = true;
2784 		spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2785 		device_set_wakeup_enable(dev, 0);
2786 	}
2787 
2788 	uart_suspend_port(&atmel_uart, port);
2789 
2790 	return 0;
2791 }
2792 
2793 static int __maybe_unused atmel_serial_resume(struct device *dev)
2794 {
2795 	struct uart_port *port = dev_get_drvdata(dev);
2796 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2797 	unsigned long flags;
2798 
2799 	if (uart_console(port) && !console_suspend_enabled) {
2800 		atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2801 		atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2802 		atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2803 		atmel_uart_writel(port, atmel_port->rtor,
2804 				  atmel_port->cache.rtor);
2805 		atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2806 
2807 		if (atmel_port->fifo_size) {
2808 			atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2809 					  ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2810 			atmel_uart_writel(port, ATMEL_US_FMR,
2811 					  atmel_port->cache.fmr);
2812 			atmel_uart_writel(port, ATMEL_US_FIER,
2813 					  atmel_port->cache.fimr);
2814 		}
2815 		atmel_start_rx(port);
2816 	}
2817 
2818 	spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2819 	if (atmel_port->pending) {
2820 		atmel_handle_receive(port, atmel_port->pending);
2821 		atmel_handle_status(port, atmel_port->pending,
2822 				    atmel_port->pending_status);
2823 		atmel_handle_transmit(port, atmel_port->pending);
2824 		atmel_port->pending = 0;
2825 	}
2826 	atmel_port->suspended = false;
2827 	spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2828 
2829 	uart_resume_port(&atmel_uart, port);
2830 	device_set_wakeup_enable(dev, atmel_port->may_wakeup);
2831 
2832 	return 0;
2833 }
2834 
2835 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2836 				     struct platform_device *pdev)
2837 {
2838 	atmel_port->fifo_size = 0;
2839 	atmel_port->rts_low = 0;
2840 	atmel_port->rts_high = 0;
2841 
2842 	if (of_property_read_u32(pdev->dev.of_node,
2843 				 "atmel,fifo-size",
2844 				 &atmel_port->fifo_size))
2845 		return;
2846 
2847 	if (!atmel_port->fifo_size)
2848 		return;
2849 
2850 	if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2851 		atmel_port->fifo_size = 0;
2852 		dev_err(&pdev->dev, "Invalid FIFO size\n");
2853 		return;
2854 	}
2855 
2856 	/*
2857 	 * 0 <= rts_low <= rts_high <= fifo_size
2858 	 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2859 	 * to flush their internal TX FIFO, commonly up to 16 data, before
2860 	 * actually stopping to send new data. So we try to set the RTS High
2861 	 * Threshold to a reasonably high value respecting this 16 data
2862 	 * empirical rule when possible.
2863 	 */
2864 	atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2865 			       atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2866 	atmel_port->rts_low  = max_t(int, atmel_port->fifo_size >> 2,
2867 			       atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2868 
2869 	dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2870 		 atmel_port->fifo_size);
2871 	dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2872 		atmel_port->rts_high);
2873 	dev_dbg(&pdev->dev, "RTS Low Threshold  : %2u data\n",
2874 		atmel_port->rts_low);
2875 }
2876 
2877 static int atmel_serial_probe(struct platform_device *pdev)
2878 {
2879 	struct atmel_uart_port *atmel_port;
2880 	struct device_node *np = pdev->dev.parent->of_node;
2881 	void *data;
2882 	int ret;
2883 	bool rs485_enabled;
2884 
2885 	BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2886 
2887 	/*
2888 	 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2889 	 * as compatible string. This driver is probed by at91-usart mfd driver
2890 	 * which is just a wrapper over the atmel_serial driver and
2891 	 * spi-at91-usart driver. All attributes needed by this driver are
2892 	 * found in of_node of parent.
2893 	 */
2894 	pdev->dev.of_node = np;
2895 
2896 	ret = of_alias_get_id(np, "serial");
2897 	if (ret < 0)
2898 		/* port id not found in platform data nor device-tree aliases:
2899 		 * auto-enumerate it */
2900 		ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2901 
2902 	if (ret >= ATMEL_MAX_UART) {
2903 		ret = -ENODEV;
2904 		goto err;
2905 	}
2906 
2907 	if (test_and_set_bit(ret, atmel_ports_in_use)) {
2908 		/* port already in use */
2909 		ret = -EBUSY;
2910 		goto err;
2911 	}
2912 
2913 	atmel_port = &atmel_ports[ret];
2914 	atmel_port->backup_imr = 0;
2915 	atmel_port->uart.line = ret;
2916 	atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
2917 	atmel_serial_probe_fifos(atmel_port, pdev);
2918 
2919 	atomic_set(&atmel_port->tasklet_shutdown, 0);
2920 	spin_lock_init(&atmel_port->lock_suspended);
2921 
2922 	atmel_port->clk = devm_clk_get(&pdev->dev, "usart");
2923 	if (IS_ERR(atmel_port->clk)) {
2924 		ret = PTR_ERR(atmel_port->clk);
2925 		goto err;
2926 	}
2927 	ret = clk_prepare_enable(atmel_port->clk);
2928 	if (ret)
2929 		goto err;
2930 
2931 	atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk");
2932 	if (IS_ERR(atmel_port->gclk)) {
2933 		ret = PTR_ERR(atmel_port->gclk);
2934 		goto err_clk_disable_unprepare;
2935 	}
2936 
2937 	ret = atmel_init_port(atmel_port, pdev);
2938 	if (ret)
2939 		goto err_clk_disable_unprepare;
2940 
2941 	atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2942 	if (IS_ERR(atmel_port->gpios)) {
2943 		ret = PTR_ERR(atmel_port->gpios);
2944 		goto err_clk_disable_unprepare;
2945 	}
2946 
2947 	if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2948 		ret = -ENOMEM;
2949 		data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2950 				     sizeof(struct atmel_uart_char),
2951 				     GFP_KERNEL);
2952 		if (!data)
2953 			goto err_clk_disable_unprepare;
2954 		atmel_port->rx_ring.buf = data;
2955 	}
2956 
2957 	rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2958 
2959 	ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2960 	if (ret)
2961 		goto err_add_port;
2962 
2963 	device_init_wakeup(&pdev->dev, 1);
2964 	platform_set_drvdata(pdev, atmel_port);
2965 
2966 	if (rs485_enabled) {
2967 		atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2968 				  ATMEL_US_USMODE_NORMAL);
2969 		atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2970 				  ATMEL_US_RTSEN);
2971 	}
2972 
2973 	/*
2974 	 * Get port name of usart or uart
2975 	 */
2976 	atmel_get_ip_name(&atmel_port->uart);
2977 
2978 	/*
2979 	 * The peripheral clock can now safely be disabled till the port
2980 	 * is used
2981 	 */
2982 	clk_disable_unprepare(atmel_port->clk);
2983 
2984 	return 0;
2985 
2986 err_add_port:
2987 	kfree(atmel_port->rx_ring.buf);
2988 	atmel_port->rx_ring.buf = NULL;
2989 err_clk_disable_unprepare:
2990 	clk_disable_unprepare(atmel_port->clk);
2991 	clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2992 err:
2993 	return ret;
2994 }
2995 
2996 /*
2997  * Even if the driver is not modular, it makes sense to be able to
2998  * unbind a device: there can be many bound devices, and there are
2999  * situations where dynamic binding and unbinding can be useful.
3000  *
3001  * For example, a connected device can require a specific firmware update
3002  * protocol that needs bitbanging on IO lines, but use the regular serial
3003  * port in the normal case.
3004  */
3005 static int atmel_serial_remove(struct platform_device *pdev)
3006 {
3007 	struct uart_port *port = platform_get_drvdata(pdev);
3008 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
3009 
3010 	tasklet_kill(&atmel_port->tasklet_rx);
3011 	tasklet_kill(&atmel_port->tasklet_tx);
3012 
3013 	device_init_wakeup(&pdev->dev, 0);
3014 
3015 	uart_remove_one_port(&atmel_uart, port);
3016 
3017 	kfree(atmel_port->rx_ring.buf);
3018 
3019 	/* "port" is allocated statically, so we shouldn't free it */
3020 
3021 	clear_bit(port->line, atmel_ports_in_use);
3022 
3023 	pdev->dev.of_node = NULL;
3024 
3025 	return 0;
3026 }
3027 
3028 static SIMPLE_DEV_PM_OPS(atmel_serial_pm_ops, atmel_serial_suspend,
3029 			 atmel_serial_resume);
3030 
3031 static struct platform_driver atmel_serial_driver = {
3032 	.probe		= atmel_serial_probe,
3033 	.remove		= atmel_serial_remove,
3034 	.driver		= {
3035 		.name			= "atmel_usart_serial",
3036 		.of_match_table		= of_match_ptr(atmel_serial_dt_ids),
3037 		.pm			= pm_ptr(&atmel_serial_pm_ops),
3038 	},
3039 };
3040 
3041 static int __init atmel_serial_init(void)
3042 {
3043 	int ret;
3044 
3045 	ret = uart_register_driver(&atmel_uart);
3046 	if (ret)
3047 		return ret;
3048 
3049 	ret = platform_driver_register(&atmel_serial_driver);
3050 	if (ret)
3051 		uart_unregister_driver(&atmel_uart);
3052 
3053 	return ret;
3054 }
3055 device_initcall(atmel_serial_init);
3056