1 /* 2 * Driver for Atmel AT91 / AT32 Serial ports 3 * Copyright (C) 2003 Rick Bronson 4 * 5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. 6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 7 * 8 * DMA support added by Chip Coldwell. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 #include <linux/module.h> 26 #include <linux/tty.h> 27 #include <linux/ioport.h> 28 #include <linux/slab.h> 29 #include <linux/init.h> 30 #include <linux/serial.h> 31 #include <linux/clk.h> 32 #include <linux/console.h> 33 #include <linux/sysrq.h> 34 #include <linux/tty_flip.h> 35 #include <linux/platform_device.h> 36 #include <linux/of.h> 37 #include <linux/of_device.h> 38 #include <linux/of_gpio.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/dmaengine.h> 41 #include <linux/atmel_pdc.h> 42 #include <linux/atmel_serial.h> 43 #include <linux/uaccess.h> 44 #include <linux/platform_data/atmel.h> 45 #include <linux/timer.h> 46 #include <linux/gpio.h> 47 #include <linux/gpio/consumer.h> 48 #include <linux/err.h> 49 #include <linux/irq.h> 50 #include <linux/suspend.h> 51 52 #include <asm/io.h> 53 #include <asm/ioctls.h> 54 55 #define PDC_BUFFER_SIZE 512 56 /* Revisit: We should calculate this based on the actual port settings */ 57 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ 58 59 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 60 #define SUPPORT_SYSRQ 61 #endif 62 63 #include <linux/serial_core.h> 64 65 #include "serial_mctrl_gpio.h" 66 67 static void atmel_start_rx(struct uart_port *port); 68 static void atmel_stop_rx(struct uart_port *port); 69 70 #ifdef CONFIG_SERIAL_ATMEL_TTYAT 71 72 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we 73 * should coexist with the 8250 driver, such as if we have an external 16C550 74 * UART. */ 75 #define SERIAL_ATMEL_MAJOR 204 76 #define MINOR_START 154 77 #define ATMEL_DEVICENAME "ttyAT" 78 79 #else 80 81 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port 82 * name, but it is legally reserved for the 8250 driver. */ 83 #define SERIAL_ATMEL_MAJOR TTY_MAJOR 84 #define MINOR_START 64 85 #define ATMEL_DEVICENAME "ttyS" 86 87 #endif 88 89 #define ATMEL_ISR_PASS_LIMIT 256 90 91 /* UART registers. CR is write-only, hence no GET macro */ 92 #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) 93 #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) 94 #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) 95 #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) 96 #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) 97 #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) 98 #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) 99 #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) 100 #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) 101 #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) 102 #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) 103 #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) 104 #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR) 105 #define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME) 106 #define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION) 107 108 /* PDC registers */ 109 #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) 110 #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) 111 112 #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) 113 #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) 114 #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) 115 #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) 116 #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) 117 118 #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) 119 #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) 120 #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR) 121 122 struct atmel_dma_buffer { 123 unsigned char *buf; 124 dma_addr_t dma_addr; 125 unsigned int dma_size; 126 unsigned int ofs; 127 }; 128 129 struct atmel_uart_char { 130 u16 status; 131 u16 ch; 132 }; 133 134 #define ATMEL_SERIAL_RINGSIZE 1024 135 136 /* 137 * We wrap our port structure around the generic uart_port. 138 */ 139 struct atmel_uart_port { 140 struct uart_port uart; /* uart */ 141 struct clk *clk; /* uart clock */ 142 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ 143 u32 backup_imr; /* IMR saved during suspend */ 144 int break_active; /* break being received */ 145 146 bool use_dma_rx; /* enable DMA receiver */ 147 bool use_pdc_rx; /* enable PDC receiver */ 148 short pdc_rx_idx; /* current PDC RX buffer */ 149 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ 150 151 bool use_dma_tx; /* enable DMA transmitter */ 152 bool use_pdc_tx; /* enable PDC transmitter */ 153 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ 154 155 spinlock_t lock_tx; /* port lock */ 156 spinlock_t lock_rx; /* port lock */ 157 struct dma_chan *chan_tx; 158 struct dma_chan *chan_rx; 159 struct dma_async_tx_descriptor *desc_tx; 160 struct dma_async_tx_descriptor *desc_rx; 161 dma_cookie_t cookie_tx; 162 dma_cookie_t cookie_rx; 163 struct scatterlist sg_tx; 164 struct scatterlist sg_rx; 165 struct tasklet_struct tasklet; 166 unsigned int irq_status; 167 unsigned int irq_status_prev; 168 169 struct circ_buf rx_ring; 170 171 struct mctrl_gpios *gpios; 172 int gpio_irq[UART_GPIO_MAX]; 173 unsigned int tx_done_mask; 174 bool ms_irq_enabled; 175 bool is_usart; /* usart or uart */ 176 struct timer_list uart_timer; /* uart timer */ 177 178 bool suspended; 179 unsigned int pending; 180 unsigned int pending_status; 181 spinlock_t lock_suspended; 182 183 int (*prepare_rx)(struct uart_port *port); 184 int (*prepare_tx)(struct uart_port *port); 185 void (*schedule_rx)(struct uart_port *port); 186 void (*schedule_tx)(struct uart_port *port); 187 void (*release_rx)(struct uart_port *port); 188 void (*release_tx)(struct uart_port *port); 189 }; 190 191 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; 192 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); 193 194 #ifdef SUPPORT_SYSRQ 195 static struct console atmel_console; 196 #endif 197 198 #if defined(CONFIG_OF) 199 static const struct of_device_id atmel_serial_dt_ids[] = { 200 { .compatible = "atmel,at91rm9200-usart" }, 201 { .compatible = "atmel,at91sam9260-usart" }, 202 { /* sentinel */ } 203 }; 204 205 MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids); 206 #endif 207 208 static inline struct atmel_uart_port * 209 to_atmel_uart_port(struct uart_port *uart) 210 { 211 return container_of(uart, struct atmel_uart_port, uart); 212 } 213 214 #ifdef CONFIG_SERIAL_ATMEL_PDC 215 static bool atmel_use_pdc_rx(struct uart_port *port) 216 { 217 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 218 219 return atmel_port->use_pdc_rx; 220 } 221 222 static bool atmel_use_pdc_tx(struct uart_port *port) 223 { 224 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 225 226 return atmel_port->use_pdc_tx; 227 } 228 #else 229 static bool atmel_use_pdc_rx(struct uart_port *port) 230 { 231 return false; 232 } 233 234 static bool atmel_use_pdc_tx(struct uart_port *port) 235 { 236 return false; 237 } 238 #endif 239 240 static bool atmel_use_dma_tx(struct uart_port *port) 241 { 242 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 243 244 return atmel_port->use_dma_tx; 245 } 246 247 static bool atmel_use_dma_rx(struct uart_port *port) 248 { 249 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 250 251 return atmel_port->use_dma_rx; 252 } 253 254 static unsigned int atmel_get_lines_status(struct uart_port *port) 255 { 256 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 257 unsigned int status, ret = 0; 258 259 status = UART_GET_CSR(port); 260 261 mctrl_gpio_get(atmel_port->gpios, &ret); 262 263 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 264 UART_GPIO_CTS))) { 265 if (ret & TIOCM_CTS) 266 status &= ~ATMEL_US_CTS; 267 else 268 status |= ATMEL_US_CTS; 269 } 270 271 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 272 UART_GPIO_DSR))) { 273 if (ret & TIOCM_DSR) 274 status &= ~ATMEL_US_DSR; 275 else 276 status |= ATMEL_US_DSR; 277 } 278 279 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 280 UART_GPIO_RI))) { 281 if (ret & TIOCM_RI) 282 status &= ~ATMEL_US_RI; 283 else 284 status |= ATMEL_US_RI; 285 } 286 287 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 288 UART_GPIO_DCD))) { 289 if (ret & TIOCM_CD) 290 status &= ~ATMEL_US_DCD; 291 else 292 status |= ATMEL_US_DCD; 293 } 294 295 return status; 296 } 297 298 /* Enable or disable the rs485 support */ 299 static int atmel_config_rs485(struct uart_port *port, 300 struct serial_rs485 *rs485conf) 301 { 302 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 303 unsigned int mode; 304 305 /* Disable interrupts */ 306 UART_PUT_IDR(port, atmel_port->tx_done_mask); 307 308 mode = UART_GET_MR(port); 309 310 /* Resetting serial mode to RS232 (0x0) */ 311 mode &= ~ATMEL_US_USMODE; 312 313 port->rs485 = *rs485conf; 314 315 if (rs485conf->flags & SER_RS485_ENABLED) { 316 dev_dbg(port->dev, "Setting UART to RS485\n"); 317 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 318 if ((rs485conf->delay_rts_after_send) > 0) 319 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send); 320 mode |= ATMEL_US_USMODE_RS485; 321 } else { 322 dev_dbg(port->dev, "Setting UART to RS232\n"); 323 if (atmel_use_pdc_tx(port)) 324 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 325 ATMEL_US_TXBUFE; 326 else 327 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 328 } 329 UART_PUT_MR(port, mode); 330 331 /* Enable interrupts */ 332 UART_PUT_IER(port, atmel_port->tx_done_mask); 333 334 return 0; 335 } 336 337 /* 338 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. 339 */ 340 static u_int atmel_tx_empty(struct uart_port *port) 341 { 342 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; 343 } 344 345 /* 346 * Set state of the modem control output lines 347 */ 348 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) 349 { 350 unsigned int control = 0; 351 unsigned int mode = UART_GET_MR(port); 352 unsigned int rts_paused, rts_ready; 353 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 354 355 /* override mode to RS485 if needed, otherwise keep the current mode */ 356 if (port->rs485.flags & SER_RS485_ENABLED) { 357 if ((port->rs485.delay_rts_after_send) > 0) 358 UART_PUT_TTGR(port, port->rs485.delay_rts_after_send); 359 mode &= ~ATMEL_US_USMODE; 360 mode |= ATMEL_US_USMODE_RS485; 361 } 362 363 /* set the RTS line state according to the mode */ 364 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 365 /* force RTS line to high level */ 366 rts_paused = ATMEL_US_RTSEN; 367 368 /* give the control of the RTS line back to the hardware */ 369 rts_ready = ATMEL_US_RTSDIS; 370 } else { 371 /* force RTS line to high level */ 372 rts_paused = ATMEL_US_RTSDIS; 373 374 /* force RTS line to low level */ 375 rts_ready = ATMEL_US_RTSEN; 376 } 377 378 if (mctrl & TIOCM_RTS) 379 control |= rts_ready; 380 else 381 control |= rts_paused; 382 383 if (mctrl & TIOCM_DTR) 384 control |= ATMEL_US_DTREN; 385 else 386 control |= ATMEL_US_DTRDIS; 387 388 UART_PUT_CR(port, control); 389 390 mctrl_gpio_set(atmel_port->gpios, mctrl); 391 392 /* Local loopback mode? */ 393 mode &= ~ATMEL_US_CHMODE; 394 if (mctrl & TIOCM_LOOP) 395 mode |= ATMEL_US_CHMODE_LOC_LOOP; 396 else 397 mode |= ATMEL_US_CHMODE_NORMAL; 398 399 UART_PUT_MR(port, mode); 400 } 401 402 /* 403 * Get state of the modem control input lines 404 */ 405 static u_int atmel_get_mctrl(struct uart_port *port) 406 { 407 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 408 unsigned int ret = 0, status; 409 410 status = UART_GET_CSR(port); 411 412 /* 413 * The control signals are active low. 414 */ 415 if (!(status & ATMEL_US_DCD)) 416 ret |= TIOCM_CD; 417 if (!(status & ATMEL_US_CTS)) 418 ret |= TIOCM_CTS; 419 if (!(status & ATMEL_US_DSR)) 420 ret |= TIOCM_DSR; 421 if (!(status & ATMEL_US_RI)) 422 ret |= TIOCM_RI; 423 424 return mctrl_gpio_get(atmel_port->gpios, &ret); 425 } 426 427 /* 428 * Stop transmitting. 429 */ 430 static void atmel_stop_tx(struct uart_port *port) 431 { 432 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 433 434 if (atmel_use_pdc_tx(port)) { 435 /* disable PDC transmit */ 436 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 437 } 438 /* Disable interrupts */ 439 UART_PUT_IDR(port, atmel_port->tx_done_mask); 440 441 if ((port->rs485.flags & SER_RS485_ENABLED) && 442 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 443 atmel_start_rx(port); 444 } 445 446 /* 447 * Start transmitting. 448 */ 449 static void atmel_start_tx(struct uart_port *port) 450 { 451 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 452 453 if (atmel_use_pdc_tx(port)) { 454 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) 455 /* The transmitter is already running. Yes, we 456 really need this.*/ 457 return; 458 459 if ((port->rs485.flags & SER_RS485_ENABLED) && 460 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 461 atmel_stop_rx(port); 462 463 /* re-enable PDC transmit */ 464 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 465 } 466 /* Enable interrupts */ 467 UART_PUT_IER(port, atmel_port->tx_done_mask); 468 } 469 470 /* 471 * start receiving - port is in process of being opened. 472 */ 473 static void atmel_start_rx(struct uart_port *port) 474 { 475 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */ 476 477 UART_PUT_CR(port, ATMEL_US_RXEN); 478 479 if (atmel_use_pdc_rx(port)) { 480 /* enable PDC controller */ 481 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 482 port->read_status_mask); 483 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); 484 } else { 485 UART_PUT_IER(port, ATMEL_US_RXRDY); 486 } 487 } 488 489 /* 490 * Stop receiving - port is in process of being closed. 491 */ 492 static void atmel_stop_rx(struct uart_port *port) 493 { 494 UART_PUT_CR(port, ATMEL_US_RXDIS); 495 496 if (atmel_use_pdc_rx(port)) { 497 /* disable PDC receive */ 498 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); 499 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 500 port->read_status_mask); 501 } else { 502 UART_PUT_IDR(port, ATMEL_US_RXRDY); 503 } 504 } 505 506 /* 507 * Enable modem status interrupts 508 */ 509 static void atmel_enable_ms(struct uart_port *port) 510 { 511 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 512 uint32_t ier = 0; 513 514 /* 515 * Interrupt should not be enabled twice 516 */ 517 if (atmel_port->ms_irq_enabled) 518 return; 519 520 atmel_port->ms_irq_enabled = true; 521 522 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0) 523 enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]); 524 else 525 ier |= ATMEL_US_CTSIC; 526 527 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0) 528 enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]); 529 else 530 ier |= ATMEL_US_DSRIC; 531 532 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0) 533 enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]); 534 else 535 ier |= ATMEL_US_RIIC; 536 537 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0) 538 enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]); 539 else 540 ier |= ATMEL_US_DCDIC; 541 542 UART_PUT_IER(port, ier); 543 } 544 545 /* 546 * Disable modem status interrupts 547 */ 548 static void atmel_disable_ms(struct uart_port *port) 549 { 550 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 551 uint32_t idr = 0; 552 553 /* 554 * Interrupt should not be disabled twice 555 */ 556 if (!atmel_port->ms_irq_enabled) 557 return; 558 559 atmel_port->ms_irq_enabled = false; 560 561 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0) 562 disable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]); 563 else 564 idr |= ATMEL_US_CTSIC; 565 566 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0) 567 disable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]); 568 else 569 idr |= ATMEL_US_DSRIC; 570 571 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0) 572 disable_irq(atmel_port->gpio_irq[UART_GPIO_RI]); 573 else 574 idr |= ATMEL_US_RIIC; 575 576 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0) 577 disable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]); 578 else 579 idr |= ATMEL_US_DCDIC; 580 581 UART_PUT_IDR(port, idr); 582 } 583 584 /* 585 * Control the transmission of a break signal 586 */ 587 static void atmel_break_ctl(struct uart_port *port, int break_state) 588 { 589 if (break_state != 0) 590 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ 591 else 592 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ 593 } 594 595 /* 596 * Stores the incoming character in the ring buffer 597 */ 598 static void 599 atmel_buffer_rx_char(struct uart_port *port, unsigned int status, 600 unsigned int ch) 601 { 602 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 603 struct circ_buf *ring = &atmel_port->rx_ring; 604 struct atmel_uart_char *c; 605 606 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) 607 /* Buffer overflow, ignore char */ 608 return; 609 610 c = &((struct atmel_uart_char *)ring->buf)[ring->head]; 611 c->status = status; 612 c->ch = ch; 613 614 /* Make sure the character is stored before we update head. */ 615 smp_wmb(); 616 617 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 618 } 619 620 /* 621 * Deal with parity, framing and overrun errors. 622 */ 623 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) 624 { 625 /* clear error */ 626 UART_PUT_CR(port, ATMEL_US_RSTSTA); 627 628 if (status & ATMEL_US_RXBRK) { 629 /* ignore side-effect */ 630 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 631 port->icount.brk++; 632 } 633 if (status & ATMEL_US_PARE) 634 port->icount.parity++; 635 if (status & ATMEL_US_FRAME) 636 port->icount.frame++; 637 if (status & ATMEL_US_OVRE) 638 port->icount.overrun++; 639 } 640 641 /* 642 * Characters received (called from interrupt handler) 643 */ 644 static void atmel_rx_chars(struct uart_port *port) 645 { 646 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 647 unsigned int status, ch; 648 649 status = UART_GET_CSR(port); 650 while (status & ATMEL_US_RXRDY) { 651 ch = UART_GET_CHAR(port); 652 653 /* 654 * note that the error handling code is 655 * out of the main execution path 656 */ 657 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 658 | ATMEL_US_OVRE | ATMEL_US_RXBRK) 659 || atmel_port->break_active)) { 660 661 /* clear error */ 662 UART_PUT_CR(port, ATMEL_US_RSTSTA); 663 664 if (status & ATMEL_US_RXBRK 665 && !atmel_port->break_active) { 666 atmel_port->break_active = 1; 667 UART_PUT_IER(port, ATMEL_US_RXBRK); 668 } else { 669 /* 670 * This is either the end-of-break 671 * condition or we've received at 672 * least one character without RXBRK 673 * being set. In both cases, the next 674 * RXBRK will indicate start-of-break. 675 */ 676 UART_PUT_IDR(port, ATMEL_US_RXBRK); 677 status &= ~ATMEL_US_RXBRK; 678 atmel_port->break_active = 0; 679 } 680 } 681 682 atmel_buffer_rx_char(port, status, ch); 683 status = UART_GET_CSR(port); 684 } 685 686 tasklet_schedule(&atmel_port->tasklet); 687 } 688 689 /* 690 * Transmit characters (called from tasklet with TXRDY interrupt 691 * disabled) 692 */ 693 static void atmel_tx_chars(struct uart_port *port) 694 { 695 struct circ_buf *xmit = &port->state->xmit; 696 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 697 698 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) { 699 UART_PUT_CHAR(port, port->x_char); 700 port->icount.tx++; 701 port->x_char = 0; 702 } 703 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 704 return; 705 706 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) { 707 UART_PUT_CHAR(port, xmit->buf[xmit->tail]); 708 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 709 port->icount.tx++; 710 if (uart_circ_empty(xmit)) 711 break; 712 } 713 714 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 715 uart_write_wakeup(port); 716 717 if (!uart_circ_empty(xmit)) 718 /* Enable interrupts */ 719 UART_PUT_IER(port, atmel_port->tx_done_mask); 720 } 721 722 static void atmel_complete_tx_dma(void *arg) 723 { 724 struct atmel_uart_port *atmel_port = arg; 725 struct uart_port *port = &atmel_port->uart; 726 struct circ_buf *xmit = &port->state->xmit; 727 struct dma_chan *chan = atmel_port->chan_tx; 728 unsigned long flags; 729 730 spin_lock_irqsave(&port->lock, flags); 731 732 if (chan) 733 dmaengine_terminate_all(chan); 734 xmit->tail += sg_dma_len(&atmel_port->sg_tx); 735 xmit->tail &= UART_XMIT_SIZE - 1; 736 737 port->icount.tx += sg_dma_len(&atmel_port->sg_tx); 738 739 spin_lock_irq(&atmel_port->lock_tx); 740 async_tx_ack(atmel_port->desc_tx); 741 atmel_port->cookie_tx = -EINVAL; 742 atmel_port->desc_tx = NULL; 743 spin_unlock_irq(&atmel_port->lock_tx); 744 745 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 746 uart_write_wakeup(port); 747 748 /* 749 * xmit is a circular buffer so, if we have just send data from 750 * xmit->tail to the end of xmit->buf, now we have to transmit the 751 * remaining data from the beginning of xmit->buf to xmit->head. 752 */ 753 if (!uart_circ_empty(xmit)) 754 tasklet_schedule(&atmel_port->tasklet); 755 756 spin_unlock_irqrestore(&port->lock, flags); 757 } 758 759 static void atmel_release_tx_dma(struct uart_port *port) 760 { 761 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 762 struct dma_chan *chan = atmel_port->chan_tx; 763 764 if (chan) { 765 dmaengine_terminate_all(chan); 766 dma_release_channel(chan); 767 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, 768 DMA_TO_DEVICE); 769 } 770 771 atmel_port->desc_tx = NULL; 772 atmel_port->chan_tx = NULL; 773 atmel_port->cookie_tx = -EINVAL; 774 } 775 776 /* 777 * Called from tasklet with TXRDY interrupt is disabled. 778 */ 779 static void atmel_tx_dma(struct uart_port *port) 780 { 781 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 782 struct circ_buf *xmit = &port->state->xmit; 783 struct dma_chan *chan = atmel_port->chan_tx; 784 struct dma_async_tx_descriptor *desc; 785 struct scatterlist *sg = &atmel_port->sg_tx; 786 787 /* Make sure we have an idle channel */ 788 if (atmel_port->desc_tx != NULL) 789 return; 790 791 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 792 /* 793 * DMA is idle now. 794 * Port xmit buffer is already mapped, 795 * and it is one page... Just adjust 796 * offsets and lengths. Since it is a circular buffer, 797 * we have to transmit till the end, and then the rest. 798 * Take the port lock to get a 799 * consistent xmit buffer state. 800 */ 801 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 802 sg_dma_address(sg) = (sg_dma_address(sg) & 803 ~(UART_XMIT_SIZE - 1)) 804 + sg->offset; 805 sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head, 806 xmit->tail, 807 UART_XMIT_SIZE); 808 BUG_ON(!sg_dma_len(sg)); 809 810 desc = dmaengine_prep_slave_sg(chan, 811 sg, 812 1, 813 DMA_MEM_TO_DEV, 814 DMA_PREP_INTERRUPT | 815 DMA_CTRL_ACK); 816 if (!desc) { 817 dev_err(port->dev, "Failed to send via dma!\n"); 818 return; 819 } 820 821 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); 822 823 atmel_port->desc_tx = desc; 824 desc->callback = atmel_complete_tx_dma; 825 desc->callback_param = atmel_port; 826 atmel_port->cookie_tx = dmaengine_submit(desc); 827 828 } else { 829 if (port->rs485.flags & SER_RS485_ENABLED) { 830 /* DMA done, stop TX, start RX for RS485 */ 831 atmel_start_rx(port); 832 } 833 } 834 835 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 836 uart_write_wakeup(port); 837 } 838 839 static int atmel_prepare_tx_dma(struct uart_port *port) 840 { 841 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 842 dma_cap_mask_t mask; 843 struct dma_slave_config config; 844 int ret, nent; 845 846 dma_cap_zero(mask); 847 dma_cap_set(DMA_SLAVE, mask); 848 849 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx"); 850 if (atmel_port->chan_tx == NULL) 851 goto chan_err; 852 dev_info(port->dev, "using %s for tx DMA transfers\n", 853 dma_chan_name(atmel_port->chan_tx)); 854 855 spin_lock_init(&atmel_port->lock_tx); 856 sg_init_table(&atmel_port->sg_tx, 1); 857 /* UART circular tx buffer is an aligned page. */ 858 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf)); 859 sg_set_page(&atmel_port->sg_tx, 860 virt_to_page(port->state->xmit.buf), 861 UART_XMIT_SIZE, 862 (int)port->state->xmit.buf & ~PAGE_MASK); 863 nent = dma_map_sg(port->dev, 864 &atmel_port->sg_tx, 865 1, 866 DMA_TO_DEVICE); 867 868 if (!nent) { 869 dev_dbg(port->dev, "need to release resource of dma\n"); 870 goto chan_err; 871 } else { 872 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 873 sg_dma_len(&atmel_port->sg_tx), 874 port->state->xmit.buf, 875 sg_dma_address(&atmel_port->sg_tx)); 876 } 877 878 /* Configure the slave DMA */ 879 memset(&config, 0, sizeof(config)); 880 config.direction = DMA_MEM_TO_DEV; 881 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 882 config.dst_addr = port->mapbase + ATMEL_US_THR; 883 config.dst_maxburst = 1; 884 885 ret = dmaengine_slave_config(atmel_port->chan_tx, 886 &config); 887 if (ret) { 888 dev_err(port->dev, "DMA tx slave configuration failed\n"); 889 goto chan_err; 890 } 891 892 return 0; 893 894 chan_err: 895 dev_err(port->dev, "TX channel not available, switch to pio\n"); 896 atmel_port->use_dma_tx = 0; 897 if (atmel_port->chan_tx) 898 atmel_release_tx_dma(port); 899 return -EINVAL; 900 } 901 902 static void atmel_complete_rx_dma(void *arg) 903 { 904 struct uart_port *port = arg; 905 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 906 907 tasklet_schedule(&atmel_port->tasklet); 908 } 909 910 static void atmel_release_rx_dma(struct uart_port *port) 911 { 912 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 913 struct dma_chan *chan = atmel_port->chan_rx; 914 915 if (chan) { 916 dmaengine_terminate_all(chan); 917 dma_release_channel(chan); 918 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, 919 DMA_FROM_DEVICE); 920 } 921 922 atmel_port->desc_rx = NULL; 923 atmel_port->chan_rx = NULL; 924 atmel_port->cookie_rx = -EINVAL; 925 } 926 927 static void atmel_rx_from_dma(struct uart_port *port) 928 { 929 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 930 struct tty_port *tport = &port->state->port; 931 struct circ_buf *ring = &atmel_port->rx_ring; 932 struct dma_chan *chan = atmel_port->chan_rx; 933 struct dma_tx_state state; 934 enum dma_status dmastat; 935 size_t count; 936 937 938 /* Reset the UART timeout early so that we don't miss one */ 939 UART_PUT_CR(port, ATMEL_US_STTTO); 940 dmastat = dmaengine_tx_status(chan, 941 atmel_port->cookie_rx, 942 &state); 943 /* Restart a new tasklet if DMA status is error */ 944 if (dmastat == DMA_ERROR) { 945 dev_dbg(port->dev, "Get residue error, restart tasklet\n"); 946 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 947 tasklet_schedule(&atmel_port->tasklet); 948 return; 949 } 950 951 /* CPU claims ownership of RX DMA buffer */ 952 dma_sync_sg_for_cpu(port->dev, 953 &atmel_port->sg_rx, 954 1, 955 DMA_FROM_DEVICE); 956 957 /* 958 * ring->head points to the end of data already written by the DMA. 959 * ring->tail points to the beginning of data to be read by the 960 * framework. 961 * The current transfer size should not be larger than the dma buffer 962 * length. 963 */ 964 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue; 965 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx)); 966 /* 967 * At this point ring->head may point to the first byte right after the 968 * last byte of the dma buffer: 969 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx) 970 * 971 * However ring->tail must always points inside the dma buffer: 972 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1 973 * 974 * Since we use a ring buffer, we have to handle the case 975 * where head is lower than tail. In such a case, we first read from 976 * tail to the end of the buffer then reset tail. 977 */ 978 if (ring->head < ring->tail) { 979 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail; 980 981 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 982 ring->tail = 0; 983 port->icount.rx += count; 984 } 985 986 /* Finally we read data from tail to head */ 987 if (ring->tail < ring->head) { 988 count = ring->head - ring->tail; 989 990 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 991 /* Wrap ring->head if needed */ 992 if (ring->head >= sg_dma_len(&atmel_port->sg_rx)) 993 ring->head = 0; 994 ring->tail = ring->head; 995 port->icount.rx += count; 996 } 997 998 /* USART retreives ownership of RX DMA buffer */ 999 dma_sync_sg_for_device(port->dev, 1000 &atmel_port->sg_rx, 1001 1, 1002 DMA_FROM_DEVICE); 1003 1004 /* 1005 * Drop the lock here since it might end up calling 1006 * uart_start(), which takes the lock. 1007 */ 1008 spin_unlock(&port->lock); 1009 tty_flip_buffer_push(tport); 1010 spin_lock(&port->lock); 1011 1012 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 1013 } 1014 1015 static int atmel_prepare_rx_dma(struct uart_port *port) 1016 { 1017 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1018 struct dma_async_tx_descriptor *desc; 1019 dma_cap_mask_t mask; 1020 struct dma_slave_config config; 1021 struct circ_buf *ring; 1022 int ret, nent; 1023 1024 ring = &atmel_port->rx_ring; 1025 1026 dma_cap_zero(mask); 1027 dma_cap_set(DMA_CYCLIC, mask); 1028 1029 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx"); 1030 if (atmel_port->chan_rx == NULL) 1031 goto chan_err; 1032 dev_info(port->dev, "using %s for rx DMA transfers\n", 1033 dma_chan_name(atmel_port->chan_rx)); 1034 1035 spin_lock_init(&atmel_port->lock_rx); 1036 sg_init_table(&atmel_port->sg_rx, 1); 1037 /* UART circular rx buffer is an aligned page. */ 1038 BUG_ON(!PAGE_ALIGNED(ring->buf)); 1039 sg_set_page(&atmel_port->sg_rx, 1040 virt_to_page(ring->buf), 1041 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE, 1042 (int)ring->buf & ~PAGE_MASK); 1043 nent = dma_map_sg(port->dev, 1044 &atmel_port->sg_rx, 1045 1, 1046 DMA_FROM_DEVICE); 1047 1048 if (!nent) { 1049 dev_dbg(port->dev, "need to release resource of dma\n"); 1050 goto chan_err; 1051 } else { 1052 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 1053 sg_dma_len(&atmel_port->sg_rx), 1054 ring->buf, 1055 sg_dma_address(&atmel_port->sg_rx)); 1056 } 1057 1058 /* Configure the slave DMA */ 1059 memset(&config, 0, sizeof(config)); 1060 config.direction = DMA_DEV_TO_MEM; 1061 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1062 config.src_addr = port->mapbase + ATMEL_US_RHR; 1063 config.src_maxburst = 1; 1064 1065 ret = dmaengine_slave_config(atmel_port->chan_rx, 1066 &config); 1067 if (ret) { 1068 dev_err(port->dev, "DMA rx slave configuration failed\n"); 1069 goto chan_err; 1070 } 1071 /* 1072 * Prepare a cyclic dma transfer, assign 2 descriptors, 1073 * each one is half ring buffer size 1074 */ 1075 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, 1076 sg_dma_address(&atmel_port->sg_rx), 1077 sg_dma_len(&atmel_port->sg_rx), 1078 sg_dma_len(&atmel_port->sg_rx)/2, 1079 DMA_DEV_TO_MEM, 1080 DMA_PREP_INTERRUPT); 1081 desc->callback = atmel_complete_rx_dma; 1082 desc->callback_param = port; 1083 atmel_port->desc_rx = desc; 1084 atmel_port->cookie_rx = dmaengine_submit(desc); 1085 1086 return 0; 1087 1088 chan_err: 1089 dev_err(port->dev, "RX channel not available, switch to pio\n"); 1090 atmel_port->use_dma_rx = 0; 1091 if (atmel_port->chan_rx) 1092 atmel_release_rx_dma(port); 1093 return -EINVAL; 1094 } 1095 1096 static void atmel_uart_timer_callback(unsigned long data) 1097 { 1098 struct uart_port *port = (void *)data; 1099 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1100 1101 tasklet_schedule(&atmel_port->tasklet); 1102 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port)); 1103 } 1104 1105 /* 1106 * receive interrupt handler. 1107 */ 1108 static void 1109 atmel_handle_receive(struct uart_port *port, unsigned int pending) 1110 { 1111 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1112 1113 if (atmel_use_pdc_rx(port)) { 1114 /* 1115 * PDC receive. Just schedule the tasklet and let it 1116 * figure out the details. 1117 * 1118 * TODO: We're not handling error flags correctly at 1119 * the moment. 1120 */ 1121 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { 1122 UART_PUT_IDR(port, (ATMEL_US_ENDRX 1123 | ATMEL_US_TIMEOUT)); 1124 tasklet_schedule(&atmel_port->tasklet); 1125 } 1126 1127 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | 1128 ATMEL_US_FRAME | ATMEL_US_PARE)) 1129 atmel_pdc_rxerr(port, pending); 1130 } 1131 1132 if (atmel_use_dma_rx(port)) { 1133 if (pending & ATMEL_US_TIMEOUT) { 1134 UART_PUT_IDR(port, ATMEL_US_TIMEOUT); 1135 tasklet_schedule(&atmel_port->tasklet); 1136 } 1137 } 1138 1139 /* Interrupt receive */ 1140 if (pending & ATMEL_US_RXRDY) 1141 atmel_rx_chars(port); 1142 else if (pending & ATMEL_US_RXBRK) { 1143 /* 1144 * End of break detected. If it came along with a 1145 * character, atmel_rx_chars will handle it. 1146 */ 1147 UART_PUT_CR(port, ATMEL_US_RSTSTA); 1148 UART_PUT_IDR(port, ATMEL_US_RXBRK); 1149 atmel_port->break_active = 0; 1150 } 1151 } 1152 1153 /* 1154 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) 1155 */ 1156 static void 1157 atmel_handle_transmit(struct uart_port *port, unsigned int pending) 1158 { 1159 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1160 1161 if (pending & atmel_port->tx_done_mask) { 1162 /* Either PDC or interrupt transmission */ 1163 UART_PUT_IDR(port, atmel_port->tx_done_mask); 1164 tasklet_schedule(&atmel_port->tasklet); 1165 } 1166 } 1167 1168 /* 1169 * status flags interrupt handler. 1170 */ 1171 static void 1172 atmel_handle_status(struct uart_port *port, unsigned int pending, 1173 unsigned int status) 1174 { 1175 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1176 1177 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC 1178 | ATMEL_US_CTSIC)) { 1179 atmel_port->irq_status = status; 1180 tasklet_schedule(&atmel_port->tasklet); 1181 } 1182 } 1183 1184 /* 1185 * Interrupt handler 1186 */ 1187 static irqreturn_t atmel_interrupt(int irq, void *dev_id) 1188 { 1189 struct uart_port *port = dev_id; 1190 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1191 unsigned int status, pending, mask, pass_counter = 0; 1192 bool gpio_handled = false; 1193 1194 spin_lock(&atmel_port->lock_suspended); 1195 1196 do { 1197 status = atmel_get_lines_status(port); 1198 mask = UART_GET_IMR(port); 1199 pending = status & mask; 1200 if (!gpio_handled) { 1201 /* 1202 * Dealing with GPIO interrupt 1203 */ 1204 if (irq == atmel_port->gpio_irq[UART_GPIO_CTS]) 1205 pending |= ATMEL_US_CTSIC; 1206 1207 if (irq == atmel_port->gpio_irq[UART_GPIO_DSR]) 1208 pending |= ATMEL_US_DSRIC; 1209 1210 if (irq == atmel_port->gpio_irq[UART_GPIO_RI]) 1211 pending |= ATMEL_US_RIIC; 1212 1213 if (irq == atmel_port->gpio_irq[UART_GPIO_DCD]) 1214 pending |= ATMEL_US_DCDIC; 1215 1216 gpio_handled = true; 1217 } 1218 if (!pending) 1219 break; 1220 1221 if (atmel_port->suspended) { 1222 atmel_port->pending |= pending; 1223 atmel_port->pending_status = status; 1224 UART_PUT_IDR(port, mask); 1225 pm_system_wakeup(); 1226 break; 1227 } 1228 1229 atmel_handle_receive(port, pending); 1230 atmel_handle_status(port, pending, status); 1231 atmel_handle_transmit(port, pending); 1232 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); 1233 1234 spin_unlock(&atmel_port->lock_suspended); 1235 1236 return pass_counter ? IRQ_HANDLED : IRQ_NONE; 1237 } 1238 1239 static void atmel_release_tx_pdc(struct uart_port *port) 1240 { 1241 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1242 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1243 1244 dma_unmap_single(port->dev, 1245 pdc->dma_addr, 1246 pdc->dma_size, 1247 DMA_TO_DEVICE); 1248 } 1249 1250 /* 1251 * Called from tasklet with ENDTX and TXBUFE interrupts disabled. 1252 */ 1253 static void atmel_tx_pdc(struct uart_port *port) 1254 { 1255 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1256 struct circ_buf *xmit = &port->state->xmit; 1257 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1258 int count; 1259 1260 /* nothing left to transmit? */ 1261 if (UART_GET_TCR(port)) 1262 return; 1263 1264 xmit->tail += pdc->ofs; 1265 xmit->tail &= UART_XMIT_SIZE - 1; 1266 1267 port->icount.tx += pdc->ofs; 1268 pdc->ofs = 0; 1269 1270 /* more to transmit - setup next transfer */ 1271 1272 /* disable PDC transmit */ 1273 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 1274 1275 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 1276 dma_sync_single_for_device(port->dev, 1277 pdc->dma_addr, 1278 pdc->dma_size, 1279 DMA_TO_DEVICE); 1280 1281 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1282 pdc->ofs = count; 1283 1284 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); 1285 UART_PUT_TCR(port, count); 1286 /* re-enable PDC transmit */ 1287 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 1288 /* Enable interrupts */ 1289 UART_PUT_IER(port, atmel_port->tx_done_mask); 1290 } else { 1291 if ((port->rs485.flags & SER_RS485_ENABLED) && 1292 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) { 1293 /* DMA done, stop TX, start RX for RS485 */ 1294 atmel_start_rx(port); 1295 } 1296 } 1297 1298 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1299 uart_write_wakeup(port); 1300 } 1301 1302 static int atmel_prepare_tx_pdc(struct uart_port *port) 1303 { 1304 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1305 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1306 struct circ_buf *xmit = &port->state->xmit; 1307 1308 pdc->buf = xmit->buf; 1309 pdc->dma_addr = dma_map_single(port->dev, 1310 pdc->buf, 1311 UART_XMIT_SIZE, 1312 DMA_TO_DEVICE); 1313 pdc->dma_size = UART_XMIT_SIZE; 1314 pdc->ofs = 0; 1315 1316 return 0; 1317 } 1318 1319 static void atmel_rx_from_ring(struct uart_port *port) 1320 { 1321 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1322 struct circ_buf *ring = &atmel_port->rx_ring; 1323 unsigned int flg; 1324 unsigned int status; 1325 1326 while (ring->head != ring->tail) { 1327 struct atmel_uart_char c; 1328 1329 /* Make sure c is loaded after head. */ 1330 smp_rmb(); 1331 1332 c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; 1333 1334 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 1335 1336 port->icount.rx++; 1337 status = c.status; 1338 flg = TTY_NORMAL; 1339 1340 /* 1341 * note that the error handling code is 1342 * out of the main execution path 1343 */ 1344 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 1345 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { 1346 if (status & ATMEL_US_RXBRK) { 1347 /* ignore side-effect */ 1348 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 1349 1350 port->icount.brk++; 1351 if (uart_handle_break(port)) 1352 continue; 1353 } 1354 if (status & ATMEL_US_PARE) 1355 port->icount.parity++; 1356 if (status & ATMEL_US_FRAME) 1357 port->icount.frame++; 1358 if (status & ATMEL_US_OVRE) 1359 port->icount.overrun++; 1360 1361 status &= port->read_status_mask; 1362 1363 if (status & ATMEL_US_RXBRK) 1364 flg = TTY_BREAK; 1365 else if (status & ATMEL_US_PARE) 1366 flg = TTY_PARITY; 1367 else if (status & ATMEL_US_FRAME) 1368 flg = TTY_FRAME; 1369 } 1370 1371 1372 if (uart_handle_sysrq_char(port, c.ch)) 1373 continue; 1374 1375 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); 1376 } 1377 1378 /* 1379 * Drop the lock here since it might end up calling 1380 * uart_start(), which takes the lock. 1381 */ 1382 spin_unlock(&port->lock); 1383 tty_flip_buffer_push(&port->state->port); 1384 spin_lock(&port->lock); 1385 } 1386 1387 static void atmel_release_rx_pdc(struct uart_port *port) 1388 { 1389 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1390 int i; 1391 1392 for (i = 0; i < 2; i++) { 1393 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1394 1395 dma_unmap_single(port->dev, 1396 pdc->dma_addr, 1397 pdc->dma_size, 1398 DMA_FROM_DEVICE); 1399 kfree(pdc->buf); 1400 } 1401 } 1402 1403 static void atmel_rx_from_pdc(struct uart_port *port) 1404 { 1405 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1406 struct tty_port *tport = &port->state->port; 1407 struct atmel_dma_buffer *pdc; 1408 int rx_idx = atmel_port->pdc_rx_idx; 1409 unsigned int head; 1410 unsigned int tail; 1411 unsigned int count; 1412 1413 do { 1414 /* Reset the UART timeout early so that we don't miss one */ 1415 UART_PUT_CR(port, ATMEL_US_STTTO); 1416 1417 pdc = &atmel_port->pdc_rx[rx_idx]; 1418 head = UART_GET_RPR(port) - pdc->dma_addr; 1419 tail = pdc->ofs; 1420 1421 /* If the PDC has switched buffers, RPR won't contain 1422 * any address within the current buffer. Since head 1423 * is unsigned, we just need a one-way comparison to 1424 * find out. 1425 * 1426 * In this case, we just need to consume the entire 1427 * buffer and resubmit it for DMA. This will clear the 1428 * ENDRX bit as well, so that we can safely re-enable 1429 * all interrupts below. 1430 */ 1431 head = min(head, pdc->dma_size); 1432 1433 if (likely(head != tail)) { 1434 dma_sync_single_for_cpu(port->dev, pdc->dma_addr, 1435 pdc->dma_size, DMA_FROM_DEVICE); 1436 1437 /* 1438 * head will only wrap around when we recycle 1439 * the DMA buffer, and when that happens, we 1440 * explicitly set tail to 0. So head will 1441 * always be greater than tail. 1442 */ 1443 count = head - tail; 1444 1445 tty_insert_flip_string(tport, pdc->buf + pdc->ofs, 1446 count); 1447 1448 dma_sync_single_for_device(port->dev, pdc->dma_addr, 1449 pdc->dma_size, DMA_FROM_DEVICE); 1450 1451 port->icount.rx += count; 1452 pdc->ofs = head; 1453 } 1454 1455 /* 1456 * If the current buffer is full, we need to check if 1457 * the next one contains any additional data. 1458 */ 1459 if (head >= pdc->dma_size) { 1460 pdc->ofs = 0; 1461 UART_PUT_RNPR(port, pdc->dma_addr); 1462 UART_PUT_RNCR(port, pdc->dma_size); 1463 1464 rx_idx = !rx_idx; 1465 atmel_port->pdc_rx_idx = rx_idx; 1466 } 1467 } while (head >= pdc->dma_size); 1468 1469 /* 1470 * Drop the lock here since it might end up calling 1471 * uart_start(), which takes the lock. 1472 */ 1473 spin_unlock(&port->lock); 1474 tty_flip_buffer_push(tport); 1475 spin_lock(&port->lock); 1476 1477 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1478 } 1479 1480 static int atmel_prepare_rx_pdc(struct uart_port *port) 1481 { 1482 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1483 int i; 1484 1485 for (i = 0; i < 2; i++) { 1486 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1487 1488 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); 1489 if (pdc->buf == NULL) { 1490 if (i != 0) { 1491 dma_unmap_single(port->dev, 1492 atmel_port->pdc_rx[0].dma_addr, 1493 PDC_BUFFER_SIZE, 1494 DMA_FROM_DEVICE); 1495 kfree(atmel_port->pdc_rx[0].buf); 1496 } 1497 atmel_port->use_pdc_rx = 0; 1498 return -ENOMEM; 1499 } 1500 pdc->dma_addr = dma_map_single(port->dev, 1501 pdc->buf, 1502 PDC_BUFFER_SIZE, 1503 DMA_FROM_DEVICE); 1504 pdc->dma_size = PDC_BUFFER_SIZE; 1505 pdc->ofs = 0; 1506 } 1507 1508 atmel_port->pdc_rx_idx = 0; 1509 1510 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); 1511 UART_PUT_RCR(port, PDC_BUFFER_SIZE); 1512 1513 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); 1514 UART_PUT_RNCR(port, PDC_BUFFER_SIZE); 1515 1516 return 0; 1517 } 1518 1519 /* 1520 * tasklet handling tty stuff outside the interrupt handler. 1521 */ 1522 static void atmel_tasklet_func(unsigned long data) 1523 { 1524 struct uart_port *port = (struct uart_port *)data; 1525 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1526 unsigned int status; 1527 unsigned int status_change; 1528 1529 /* The interrupt handler does not take the lock */ 1530 spin_lock(&port->lock); 1531 1532 atmel_port->schedule_tx(port); 1533 1534 status = atmel_port->irq_status; 1535 status_change = status ^ atmel_port->irq_status_prev; 1536 1537 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR 1538 | ATMEL_US_DCD | ATMEL_US_CTS)) { 1539 /* TODO: All reads to CSR will clear these interrupts! */ 1540 if (status_change & ATMEL_US_RI) 1541 port->icount.rng++; 1542 if (status_change & ATMEL_US_DSR) 1543 port->icount.dsr++; 1544 if (status_change & ATMEL_US_DCD) 1545 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); 1546 if (status_change & ATMEL_US_CTS) 1547 uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); 1548 1549 wake_up_interruptible(&port->state->port.delta_msr_wait); 1550 1551 atmel_port->irq_status_prev = status; 1552 } 1553 1554 atmel_port->schedule_rx(port); 1555 1556 spin_unlock(&port->lock); 1557 } 1558 1559 static void atmel_init_property(struct atmel_uart_port *atmel_port, 1560 struct platform_device *pdev) 1561 { 1562 struct device_node *np = pdev->dev.of_node; 1563 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1564 1565 if (np) { 1566 /* DMA/PDC usage specification */ 1567 if (of_get_property(np, "atmel,use-dma-rx", NULL)) { 1568 if (of_get_property(np, "dmas", NULL)) { 1569 atmel_port->use_dma_rx = true; 1570 atmel_port->use_pdc_rx = false; 1571 } else { 1572 atmel_port->use_dma_rx = false; 1573 atmel_port->use_pdc_rx = true; 1574 } 1575 } else { 1576 atmel_port->use_dma_rx = false; 1577 atmel_port->use_pdc_rx = false; 1578 } 1579 1580 if (of_get_property(np, "atmel,use-dma-tx", NULL)) { 1581 if (of_get_property(np, "dmas", NULL)) { 1582 atmel_port->use_dma_tx = true; 1583 atmel_port->use_pdc_tx = false; 1584 } else { 1585 atmel_port->use_dma_tx = false; 1586 atmel_port->use_pdc_tx = true; 1587 } 1588 } else { 1589 atmel_port->use_dma_tx = false; 1590 atmel_port->use_pdc_tx = false; 1591 } 1592 1593 } else { 1594 atmel_port->use_pdc_rx = pdata->use_dma_rx; 1595 atmel_port->use_pdc_tx = pdata->use_dma_tx; 1596 atmel_port->use_dma_rx = false; 1597 atmel_port->use_dma_tx = false; 1598 } 1599 1600 } 1601 1602 static void atmel_init_rs485(struct uart_port *port, 1603 struct platform_device *pdev) 1604 { 1605 struct device_node *np = pdev->dev.of_node; 1606 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1607 1608 if (np) { 1609 u32 rs485_delay[2]; 1610 /* rs485 properties */ 1611 if (of_property_read_u32_array(np, "rs485-rts-delay", 1612 rs485_delay, 2) == 0) { 1613 struct serial_rs485 *rs485conf = &port->rs485; 1614 1615 rs485conf->delay_rts_before_send = rs485_delay[0]; 1616 rs485conf->delay_rts_after_send = rs485_delay[1]; 1617 rs485conf->flags = 0; 1618 1619 if (of_get_property(np, "rs485-rx-during-tx", NULL)) 1620 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1621 1622 if (of_get_property(np, "linux,rs485-enabled-at-boot-time", 1623 NULL)) 1624 rs485conf->flags |= SER_RS485_ENABLED; 1625 } 1626 } else { 1627 port->rs485 = pdata->rs485; 1628 } 1629 1630 } 1631 1632 static void atmel_set_ops(struct uart_port *port) 1633 { 1634 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1635 1636 if (atmel_use_dma_rx(port)) { 1637 atmel_port->prepare_rx = &atmel_prepare_rx_dma; 1638 atmel_port->schedule_rx = &atmel_rx_from_dma; 1639 atmel_port->release_rx = &atmel_release_rx_dma; 1640 } else if (atmel_use_pdc_rx(port)) { 1641 atmel_port->prepare_rx = &atmel_prepare_rx_pdc; 1642 atmel_port->schedule_rx = &atmel_rx_from_pdc; 1643 atmel_port->release_rx = &atmel_release_rx_pdc; 1644 } else { 1645 atmel_port->prepare_rx = NULL; 1646 atmel_port->schedule_rx = &atmel_rx_from_ring; 1647 atmel_port->release_rx = NULL; 1648 } 1649 1650 if (atmel_use_dma_tx(port)) { 1651 atmel_port->prepare_tx = &atmel_prepare_tx_dma; 1652 atmel_port->schedule_tx = &atmel_tx_dma; 1653 atmel_port->release_tx = &atmel_release_tx_dma; 1654 } else if (atmel_use_pdc_tx(port)) { 1655 atmel_port->prepare_tx = &atmel_prepare_tx_pdc; 1656 atmel_port->schedule_tx = &atmel_tx_pdc; 1657 atmel_port->release_tx = &atmel_release_tx_pdc; 1658 } else { 1659 atmel_port->prepare_tx = NULL; 1660 atmel_port->schedule_tx = &atmel_tx_chars; 1661 atmel_port->release_tx = NULL; 1662 } 1663 } 1664 1665 /* 1666 * Get ip name usart or uart 1667 */ 1668 static void atmel_get_ip_name(struct uart_port *port) 1669 { 1670 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1671 int name = UART_GET_IP_NAME(port); 1672 u32 version; 1673 int usart, uart; 1674 /* usart and uart ascii */ 1675 usart = 0x55534152; 1676 uart = 0x44424755; 1677 1678 atmel_port->is_usart = false; 1679 1680 if (name == usart) { 1681 dev_dbg(port->dev, "This is usart\n"); 1682 atmel_port->is_usart = true; 1683 } else if (name == uart) { 1684 dev_dbg(port->dev, "This is uart\n"); 1685 atmel_port->is_usart = false; 1686 } else { 1687 /* fallback for older SoCs: use version field */ 1688 version = UART_GET_IP_VERSION(port); 1689 switch (version) { 1690 case 0x302: 1691 case 0x10213: 1692 dev_dbg(port->dev, "This version is usart\n"); 1693 atmel_port->is_usart = true; 1694 break; 1695 case 0x203: 1696 case 0x10202: 1697 dev_dbg(port->dev, "This version is uart\n"); 1698 atmel_port->is_usart = false; 1699 break; 1700 default: 1701 dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); 1702 } 1703 } 1704 } 1705 1706 static void atmel_free_gpio_irq(struct uart_port *port) 1707 { 1708 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1709 enum mctrl_gpio_idx i; 1710 1711 for (i = 0; i < UART_GPIO_MAX; i++) 1712 if (atmel_port->gpio_irq[i] >= 0) 1713 free_irq(atmel_port->gpio_irq[i], port); 1714 } 1715 1716 static int atmel_request_gpio_irq(struct uart_port *port) 1717 { 1718 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1719 int *irq = atmel_port->gpio_irq; 1720 enum mctrl_gpio_idx i; 1721 int err = 0; 1722 1723 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) { 1724 if (irq[i] < 0) 1725 continue; 1726 1727 irq_set_status_flags(irq[i], IRQ_NOAUTOEN); 1728 err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH, 1729 "atmel_serial", port); 1730 if (err) 1731 dev_err(port->dev, "atmel_startup - Can't get %d irq\n", 1732 irq[i]); 1733 } 1734 1735 /* 1736 * If something went wrong, rollback. 1737 */ 1738 while (err && (--i >= 0)) 1739 if (irq[i] >= 0) 1740 free_irq(irq[i], port); 1741 1742 return err; 1743 } 1744 1745 /* 1746 * Perform initialization and enable port for reception 1747 */ 1748 static int atmel_startup(struct uart_port *port) 1749 { 1750 struct platform_device *pdev = to_platform_device(port->dev); 1751 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1752 struct tty_struct *tty = port->state->port.tty; 1753 int retval; 1754 1755 /* 1756 * Ensure that no interrupts are enabled otherwise when 1757 * request_irq() is called we could get stuck trying to 1758 * handle an unexpected interrupt 1759 */ 1760 UART_PUT_IDR(port, -1); 1761 atmel_port->ms_irq_enabled = false; 1762 1763 /* 1764 * Allocate the IRQ 1765 */ 1766 retval = request_irq(port->irq, atmel_interrupt, 1767 IRQF_SHARED | IRQF_COND_SUSPEND, 1768 tty ? tty->name : "atmel_serial", port); 1769 if (retval) { 1770 dev_err(port->dev, "atmel_startup - Can't get irq\n"); 1771 return retval; 1772 } 1773 1774 /* 1775 * Get the GPIO lines IRQ 1776 */ 1777 retval = atmel_request_gpio_irq(port); 1778 if (retval) 1779 goto free_irq; 1780 1781 tasklet_enable(&atmel_port->tasklet); 1782 1783 /* 1784 * Initialize DMA (if necessary) 1785 */ 1786 atmel_init_property(atmel_port, pdev); 1787 atmel_set_ops(port); 1788 1789 if (atmel_port->prepare_rx) { 1790 retval = atmel_port->prepare_rx(port); 1791 if (retval < 0) 1792 atmel_set_ops(port); 1793 } 1794 1795 if (atmel_port->prepare_tx) { 1796 retval = atmel_port->prepare_tx(port); 1797 if (retval < 0) 1798 atmel_set_ops(port); 1799 } 1800 1801 /* Save current CSR for comparison in atmel_tasklet_func() */ 1802 atmel_port->irq_status_prev = atmel_get_lines_status(port); 1803 atmel_port->irq_status = atmel_port->irq_status_prev; 1804 1805 /* 1806 * Finally, enable the serial port 1807 */ 1808 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1809 /* enable xmit & rcvr */ 1810 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 1811 1812 setup_timer(&atmel_port->uart_timer, 1813 atmel_uart_timer_callback, 1814 (unsigned long)port); 1815 1816 if (atmel_use_pdc_rx(port)) { 1817 /* set UART timeout */ 1818 if (!atmel_port->is_usart) { 1819 mod_timer(&atmel_port->uart_timer, 1820 jiffies + uart_poll_timeout(port)); 1821 /* set USART timeout */ 1822 } else { 1823 UART_PUT_RTOR(port, PDC_RX_TIMEOUT); 1824 UART_PUT_CR(port, ATMEL_US_STTTO); 1825 1826 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1827 } 1828 /* enable PDC controller */ 1829 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); 1830 } else if (atmel_use_dma_rx(port)) { 1831 /* set UART timeout */ 1832 if (!atmel_port->is_usart) { 1833 mod_timer(&atmel_port->uart_timer, 1834 jiffies + uart_poll_timeout(port)); 1835 /* set USART timeout */ 1836 } else { 1837 UART_PUT_RTOR(port, PDC_RX_TIMEOUT); 1838 UART_PUT_CR(port, ATMEL_US_STTTO); 1839 1840 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 1841 } 1842 } else { 1843 /* enable receive only */ 1844 UART_PUT_IER(port, ATMEL_US_RXRDY); 1845 } 1846 1847 return 0; 1848 1849 free_irq: 1850 free_irq(port->irq, port); 1851 1852 return retval; 1853 } 1854 1855 /* 1856 * Flush any TX data submitted for DMA. Called when the TX circular 1857 * buffer is reset. 1858 */ 1859 static void atmel_flush_buffer(struct uart_port *port) 1860 { 1861 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1862 1863 if (atmel_use_pdc_tx(port)) { 1864 UART_PUT_TCR(port, 0); 1865 atmel_port->pdc_tx.ofs = 0; 1866 } 1867 } 1868 1869 /* 1870 * Disable the port 1871 */ 1872 static void atmel_shutdown(struct uart_port *port) 1873 { 1874 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1875 1876 /* 1877 * Prevent any tasklets being scheduled during 1878 * cleanup 1879 */ 1880 del_timer_sync(&atmel_port->uart_timer); 1881 1882 /* 1883 * Clear out any scheduled tasklets before 1884 * we destroy the buffers 1885 */ 1886 tasklet_disable(&atmel_port->tasklet); 1887 tasklet_kill(&atmel_port->tasklet); 1888 1889 /* 1890 * Ensure everything is stopped and 1891 * disable all interrupts, port and break condition. 1892 */ 1893 atmel_stop_rx(port); 1894 atmel_stop_tx(port); 1895 1896 UART_PUT_CR(port, ATMEL_US_RSTSTA); 1897 UART_PUT_IDR(port, -1); 1898 1899 1900 /* 1901 * Shut-down the DMA. 1902 */ 1903 if (atmel_port->release_rx) 1904 atmel_port->release_rx(port); 1905 if (atmel_port->release_tx) 1906 atmel_port->release_tx(port); 1907 1908 /* 1909 * Reset ring buffer pointers 1910 */ 1911 atmel_port->rx_ring.head = 0; 1912 atmel_port->rx_ring.tail = 0; 1913 1914 /* 1915 * Free the interrupts 1916 */ 1917 free_irq(port->irq, port); 1918 atmel_free_gpio_irq(port); 1919 1920 atmel_port->ms_irq_enabled = false; 1921 1922 atmel_flush_buffer(port); 1923 } 1924 1925 /* 1926 * Power / Clock management. 1927 */ 1928 static void atmel_serial_pm(struct uart_port *port, unsigned int state, 1929 unsigned int oldstate) 1930 { 1931 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1932 1933 switch (state) { 1934 case 0: 1935 /* 1936 * Enable the peripheral clock for this serial port. 1937 * This is called on uart_open() or a resume event. 1938 */ 1939 clk_prepare_enable(atmel_port->clk); 1940 1941 /* re-enable interrupts if we disabled some on suspend */ 1942 UART_PUT_IER(port, atmel_port->backup_imr); 1943 break; 1944 case 3: 1945 /* Back up the interrupt mask and disable all interrupts */ 1946 atmel_port->backup_imr = UART_GET_IMR(port); 1947 UART_PUT_IDR(port, -1); 1948 1949 /* 1950 * Disable the peripheral clock for this serial port. 1951 * This is called on uart_close() or a suspend event. 1952 */ 1953 clk_disable_unprepare(atmel_port->clk); 1954 break; 1955 default: 1956 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); 1957 } 1958 } 1959 1960 /* 1961 * Change the port parameters 1962 */ 1963 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, 1964 struct ktermios *old) 1965 { 1966 unsigned long flags; 1967 unsigned int old_mode, mode, imr, quot, baud; 1968 1969 /* save the current mode register */ 1970 mode = old_mode = UART_GET_MR(port); 1971 1972 /* reset the mode, clock divisor, parity, stop bits and data size */ 1973 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | 1974 ATMEL_US_PAR | ATMEL_US_USMODE); 1975 1976 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1977 quot = uart_get_divisor(port, baud); 1978 1979 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ 1980 quot /= 8; 1981 mode |= ATMEL_US_USCLKS_MCK_DIV8; 1982 } 1983 1984 /* byte size */ 1985 switch (termios->c_cflag & CSIZE) { 1986 case CS5: 1987 mode |= ATMEL_US_CHRL_5; 1988 break; 1989 case CS6: 1990 mode |= ATMEL_US_CHRL_6; 1991 break; 1992 case CS7: 1993 mode |= ATMEL_US_CHRL_7; 1994 break; 1995 default: 1996 mode |= ATMEL_US_CHRL_8; 1997 break; 1998 } 1999 2000 /* stop bits */ 2001 if (termios->c_cflag & CSTOPB) 2002 mode |= ATMEL_US_NBSTOP_2; 2003 2004 /* parity */ 2005 if (termios->c_cflag & PARENB) { 2006 /* Mark or Space parity */ 2007 if (termios->c_cflag & CMSPAR) { 2008 if (termios->c_cflag & PARODD) 2009 mode |= ATMEL_US_PAR_MARK; 2010 else 2011 mode |= ATMEL_US_PAR_SPACE; 2012 } else if (termios->c_cflag & PARODD) 2013 mode |= ATMEL_US_PAR_ODD; 2014 else 2015 mode |= ATMEL_US_PAR_EVEN; 2016 } else 2017 mode |= ATMEL_US_PAR_NONE; 2018 2019 spin_lock_irqsave(&port->lock, flags); 2020 2021 port->read_status_mask = ATMEL_US_OVRE; 2022 if (termios->c_iflag & INPCK) 2023 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2024 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2025 port->read_status_mask |= ATMEL_US_RXBRK; 2026 2027 if (atmel_use_pdc_rx(port)) 2028 /* need to enable error interrupts */ 2029 UART_PUT_IER(port, port->read_status_mask); 2030 2031 /* 2032 * Characters to ignore 2033 */ 2034 port->ignore_status_mask = 0; 2035 if (termios->c_iflag & IGNPAR) 2036 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2037 if (termios->c_iflag & IGNBRK) { 2038 port->ignore_status_mask |= ATMEL_US_RXBRK; 2039 /* 2040 * If we're ignoring parity and break indicators, 2041 * ignore overruns too (for real raw support). 2042 */ 2043 if (termios->c_iflag & IGNPAR) 2044 port->ignore_status_mask |= ATMEL_US_OVRE; 2045 } 2046 /* TODO: Ignore all characters if CREAD is set.*/ 2047 2048 /* update the per-port timeout */ 2049 uart_update_timeout(port, termios->c_cflag, baud); 2050 2051 /* 2052 * save/disable interrupts. The tty layer will ensure that the 2053 * transmitter is empty if requested by the caller, so there's 2054 * no need to wait for it here. 2055 */ 2056 imr = UART_GET_IMR(port); 2057 UART_PUT_IDR(port, -1); 2058 2059 /* disable receiver and transmitter */ 2060 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); 2061 2062 /* mode */ 2063 if (port->rs485.flags & SER_RS485_ENABLED) { 2064 if ((port->rs485.delay_rts_after_send) > 0) 2065 UART_PUT_TTGR(port, port->rs485.delay_rts_after_send); 2066 mode |= ATMEL_US_USMODE_RS485; 2067 } else if (termios->c_cflag & CRTSCTS) { 2068 /* RS232 with hardware handshake (RTS/CTS) */ 2069 mode |= ATMEL_US_USMODE_HWHS; 2070 } else { 2071 /* RS232 without hadware handshake */ 2072 mode |= ATMEL_US_USMODE_NORMAL; 2073 } 2074 2075 /* set the mode, clock divisor, parity, stop bits and data size */ 2076 UART_PUT_MR(port, mode); 2077 2078 /* 2079 * when switching the mode, set the RTS line state according to the 2080 * new mode, otherwise keep the former state 2081 */ 2082 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) { 2083 unsigned int rts_state; 2084 2085 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 2086 /* let the hardware control the RTS line */ 2087 rts_state = ATMEL_US_RTSDIS; 2088 } else { 2089 /* force RTS line to low level */ 2090 rts_state = ATMEL_US_RTSEN; 2091 } 2092 2093 UART_PUT_CR(port, rts_state); 2094 } 2095 2096 /* set the baud rate */ 2097 UART_PUT_BRGR(port, quot); 2098 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2099 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 2100 2101 /* restore interrupts */ 2102 UART_PUT_IER(port, imr); 2103 2104 /* CTS flow-control and modem-status interrupts */ 2105 if (UART_ENABLE_MS(port, termios->c_cflag)) 2106 atmel_enable_ms(port); 2107 else 2108 atmel_disable_ms(port); 2109 2110 spin_unlock_irqrestore(&port->lock, flags); 2111 } 2112 2113 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios) 2114 { 2115 if (termios->c_line == N_PPS) { 2116 port->flags |= UPF_HARDPPS_CD; 2117 spin_lock_irq(&port->lock); 2118 atmel_enable_ms(port); 2119 spin_unlock_irq(&port->lock); 2120 } else { 2121 port->flags &= ~UPF_HARDPPS_CD; 2122 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 2123 spin_lock_irq(&port->lock); 2124 atmel_disable_ms(port); 2125 spin_unlock_irq(&port->lock); 2126 } 2127 } 2128 } 2129 2130 /* 2131 * Return string describing the specified port 2132 */ 2133 static const char *atmel_type(struct uart_port *port) 2134 { 2135 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; 2136 } 2137 2138 /* 2139 * Release the memory region(s) being used by 'port'. 2140 */ 2141 static void atmel_release_port(struct uart_port *port) 2142 { 2143 struct platform_device *pdev = to_platform_device(port->dev); 2144 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 2145 2146 release_mem_region(port->mapbase, size); 2147 2148 if (port->flags & UPF_IOREMAP) { 2149 iounmap(port->membase); 2150 port->membase = NULL; 2151 } 2152 } 2153 2154 /* 2155 * Request the memory region(s) being used by 'port'. 2156 */ 2157 static int atmel_request_port(struct uart_port *port) 2158 { 2159 struct platform_device *pdev = to_platform_device(port->dev); 2160 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 2161 2162 if (!request_mem_region(port->mapbase, size, "atmel_serial")) 2163 return -EBUSY; 2164 2165 if (port->flags & UPF_IOREMAP) { 2166 port->membase = ioremap(port->mapbase, size); 2167 if (port->membase == NULL) { 2168 release_mem_region(port->mapbase, size); 2169 return -ENOMEM; 2170 } 2171 } 2172 2173 return 0; 2174 } 2175 2176 /* 2177 * Configure/autoconfigure the port. 2178 */ 2179 static void atmel_config_port(struct uart_port *port, int flags) 2180 { 2181 if (flags & UART_CONFIG_TYPE) { 2182 port->type = PORT_ATMEL; 2183 atmel_request_port(port); 2184 } 2185 } 2186 2187 /* 2188 * Verify the new serial_struct (for TIOCSSERIAL). 2189 */ 2190 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) 2191 { 2192 int ret = 0; 2193 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) 2194 ret = -EINVAL; 2195 if (port->irq != ser->irq) 2196 ret = -EINVAL; 2197 if (ser->io_type != SERIAL_IO_MEM) 2198 ret = -EINVAL; 2199 if (port->uartclk / 16 != ser->baud_base) 2200 ret = -EINVAL; 2201 if ((void *)port->mapbase != ser->iomem_base) 2202 ret = -EINVAL; 2203 if (port->iobase != ser->port) 2204 ret = -EINVAL; 2205 if (ser->hub6 != 0) 2206 ret = -EINVAL; 2207 return ret; 2208 } 2209 2210 #ifdef CONFIG_CONSOLE_POLL 2211 static int atmel_poll_get_char(struct uart_port *port) 2212 { 2213 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY)) 2214 cpu_relax(); 2215 2216 return UART_GET_CHAR(port); 2217 } 2218 2219 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) 2220 { 2221 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) 2222 cpu_relax(); 2223 2224 UART_PUT_CHAR(port, ch); 2225 } 2226 #endif 2227 2228 static struct uart_ops atmel_pops = { 2229 .tx_empty = atmel_tx_empty, 2230 .set_mctrl = atmel_set_mctrl, 2231 .get_mctrl = atmel_get_mctrl, 2232 .stop_tx = atmel_stop_tx, 2233 .start_tx = atmel_start_tx, 2234 .stop_rx = atmel_stop_rx, 2235 .enable_ms = atmel_enable_ms, 2236 .break_ctl = atmel_break_ctl, 2237 .startup = atmel_startup, 2238 .shutdown = atmel_shutdown, 2239 .flush_buffer = atmel_flush_buffer, 2240 .set_termios = atmel_set_termios, 2241 .set_ldisc = atmel_set_ldisc, 2242 .type = atmel_type, 2243 .release_port = atmel_release_port, 2244 .request_port = atmel_request_port, 2245 .config_port = atmel_config_port, 2246 .verify_port = atmel_verify_port, 2247 .pm = atmel_serial_pm, 2248 #ifdef CONFIG_CONSOLE_POLL 2249 .poll_get_char = atmel_poll_get_char, 2250 .poll_put_char = atmel_poll_put_char, 2251 #endif 2252 }; 2253 2254 /* 2255 * Configure the port from the platform device resource info. 2256 */ 2257 static int atmel_init_port(struct atmel_uart_port *atmel_port, 2258 struct platform_device *pdev) 2259 { 2260 int ret; 2261 struct uart_port *port = &atmel_port->uart; 2262 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2263 2264 atmel_init_property(atmel_port, pdev); 2265 atmel_set_ops(port); 2266 2267 atmel_init_rs485(port, pdev); 2268 2269 port->iotype = UPIO_MEM; 2270 port->flags = UPF_BOOT_AUTOCONF; 2271 port->ops = &atmel_pops; 2272 port->fifosize = 1; 2273 port->dev = &pdev->dev; 2274 port->mapbase = pdev->resource[0].start; 2275 port->irq = pdev->resource[1].start; 2276 port->rs485_config = atmel_config_rs485; 2277 2278 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, 2279 (unsigned long)port); 2280 tasklet_disable(&atmel_port->tasklet); 2281 2282 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); 2283 2284 if (pdata && pdata->regs) { 2285 /* Already mapped by setup code */ 2286 port->membase = pdata->regs; 2287 } else { 2288 port->flags |= UPF_IOREMAP; 2289 port->membase = NULL; 2290 } 2291 2292 /* for console, the clock could already be configured */ 2293 if (!atmel_port->clk) { 2294 atmel_port->clk = clk_get(&pdev->dev, "usart"); 2295 if (IS_ERR(atmel_port->clk)) { 2296 ret = PTR_ERR(atmel_port->clk); 2297 atmel_port->clk = NULL; 2298 return ret; 2299 } 2300 ret = clk_prepare_enable(atmel_port->clk); 2301 if (ret) { 2302 clk_put(atmel_port->clk); 2303 atmel_port->clk = NULL; 2304 return ret; 2305 } 2306 port->uartclk = clk_get_rate(atmel_port->clk); 2307 clk_disable_unprepare(atmel_port->clk); 2308 /* only enable clock when USART is in use */ 2309 } 2310 2311 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ 2312 if (port->rs485.flags & SER_RS485_ENABLED) 2313 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 2314 else if (atmel_use_pdc_tx(port)) { 2315 port->fifosize = PDC_BUFFER_SIZE; 2316 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; 2317 } else { 2318 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 2319 } 2320 2321 return 0; 2322 } 2323 2324 struct platform_device *atmel_default_console_device; /* the serial console device */ 2325 2326 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2327 static void atmel_console_putchar(struct uart_port *port, int ch) 2328 { 2329 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) 2330 cpu_relax(); 2331 UART_PUT_CHAR(port, ch); 2332 } 2333 2334 /* 2335 * Interrupts are disabled on entering 2336 */ 2337 static void atmel_console_write(struct console *co, const char *s, u_int count) 2338 { 2339 struct uart_port *port = &atmel_ports[co->index].uart; 2340 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2341 unsigned int status, imr; 2342 unsigned int pdc_tx; 2343 2344 /* 2345 * First, save IMR and then disable interrupts 2346 */ 2347 imr = UART_GET_IMR(port); 2348 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask); 2349 2350 /* Store PDC transmit status and disable it */ 2351 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN; 2352 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 2353 2354 uart_console_write(port, s, count, atmel_console_putchar); 2355 2356 /* 2357 * Finally, wait for transmitter to become empty 2358 * and restore IMR 2359 */ 2360 do { 2361 status = UART_GET_CSR(port); 2362 } while (!(status & ATMEL_US_TXRDY)); 2363 2364 /* Restore PDC transmit status */ 2365 if (pdc_tx) 2366 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 2367 2368 /* set interrupts back the way they were */ 2369 UART_PUT_IER(port, imr); 2370 } 2371 2372 /* 2373 * If the port was already initialised (eg, by a boot loader), 2374 * try to determine the current setup. 2375 */ 2376 static void __init atmel_console_get_options(struct uart_port *port, int *baud, 2377 int *parity, int *bits) 2378 { 2379 unsigned int mr, quot; 2380 2381 /* 2382 * If the baud rate generator isn't running, the port wasn't 2383 * initialized by the boot loader. 2384 */ 2385 quot = UART_GET_BRGR(port) & ATMEL_US_CD; 2386 if (!quot) 2387 return; 2388 2389 mr = UART_GET_MR(port) & ATMEL_US_CHRL; 2390 if (mr == ATMEL_US_CHRL_8) 2391 *bits = 8; 2392 else 2393 *bits = 7; 2394 2395 mr = UART_GET_MR(port) & ATMEL_US_PAR; 2396 if (mr == ATMEL_US_PAR_EVEN) 2397 *parity = 'e'; 2398 else if (mr == ATMEL_US_PAR_ODD) 2399 *parity = 'o'; 2400 2401 /* 2402 * The serial core only rounds down when matching this to a 2403 * supported baud rate. Make sure we don't end up slightly 2404 * lower than one of those, as it would make us fall through 2405 * to a much lower baud rate than we really want. 2406 */ 2407 *baud = port->uartclk / (16 * (quot - 1)); 2408 } 2409 2410 static int __init atmel_console_setup(struct console *co, char *options) 2411 { 2412 int ret; 2413 struct uart_port *port = &atmel_ports[co->index].uart; 2414 int baud = 115200; 2415 int bits = 8; 2416 int parity = 'n'; 2417 int flow = 'n'; 2418 2419 if (port->membase == NULL) { 2420 /* Port not initialized yet - delay setup */ 2421 return -ENODEV; 2422 } 2423 2424 ret = clk_prepare_enable(atmel_ports[co->index].clk); 2425 if (ret) 2426 return ret; 2427 2428 UART_PUT_IDR(port, -1); 2429 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2430 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 2431 2432 if (options) 2433 uart_parse_options(options, &baud, &parity, &bits, &flow); 2434 else 2435 atmel_console_get_options(port, &baud, &parity, &bits); 2436 2437 return uart_set_options(port, co, baud, parity, bits, flow); 2438 } 2439 2440 static struct uart_driver atmel_uart; 2441 2442 static struct console atmel_console = { 2443 .name = ATMEL_DEVICENAME, 2444 .write = atmel_console_write, 2445 .device = uart_console_device, 2446 .setup = atmel_console_setup, 2447 .flags = CON_PRINTBUFFER, 2448 .index = -1, 2449 .data = &atmel_uart, 2450 }; 2451 2452 #define ATMEL_CONSOLE_DEVICE (&atmel_console) 2453 2454 /* 2455 * Early console initialization (before VM subsystem initialized). 2456 */ 2457 static int __init atmel_console_init(void) 2458 { 2459 int ret; 2460 if (atmel_default_console_device) { 2461 struct atmel_uart_data *pdata = 2462 dev_get_platdata(&atmel_default_console_device->dev); 2463 int id = pdata->num; 2464 struct atmel_uart_port *port = &atmel_ports[id]; 2465 2466 port->backup_imr = 0; 2467 port->uart.line = id; 2468 2469 add_preferred_console(ATMEL_DEVICENAME, id, NULL); 2470 ret = atmel_init_port(port, atmel_default_console_device); 2471 if (ret) 2472 return ret; 2473 register_console(&atmel_console); 2474 } 2475 2476 return 0; 2477 } 2478 2479 console_initcall(atmel_console_init); 2480 2481 /* 2482 * Late console initialization. 2483 */ 2484 static int __init atmel_late_console_init(void) 2485 { 2486 if (atmel_default_console_device 2487 && !(atmel_console.flags & CON_ENABLED)) 2488 register_console(&atmel_console); 2489 2490 return 0; 2491 } 2492 2493 core_initcall(atmel_late_console_init); 2494 2495 static inline bool atmel_is_console_port(struct uart_port *port) 2496 { 2497 return port->cons && port->cons->index == port->line; 2498 } 2499 2500 #else 2501 #define ATMEL_CONSOLE_DEVICE NULL 2502 2503 static inline bool atmel_is_console_port(struct uart_port *port) 2504 { 2505 return false; 2506 } 2507 #endif 2508 2509 static struct uart_driver atmel_uart = { 2510 .owner = THIS_MODULE, 2511 .driver_name = "atmel_serial", 2512 .dev_name = ATMEL_DEVICENAME, 2513 .major = SERIAL_ATMEL_MAJOR, 2514 .minor = MINOR_START, 2515 .nr = ATMEL_MAX_UART, 2516 .cons = ATMEL_CONSOLE_DEVICE, 2517 }; 2518 2519 #ifdef CONFIG_PM 2520 static bool atmel_serial_clk_will_stop(void) 2521 { 2522 #ifdef CONFIG_ARCH_AT91 2523 return at91_suspend_entering_slow_clock(); 2524 #else 2525 return false; 2526 #endif 2527 } 2528 2529 static int atmel_serial_suspend(struct platform_device *pdev, 2530 pm_message_t state) 2531 { 2532 struct uart_port *port = platform_get_drvdata(pdev); 2533 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2534 2535 if (atmel_is_console_port(port) && console_suspend_enabled) { 2536 /* Drain the TX shifter */ 2537 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) 2538 cpu_relax(); 2539 } 2540 2541 /* we can not wake up if we're running on slow clock */ 2542 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); 2543 if (atmel_serial_clk_will_stop()) { 2544 unsigned long flags; 2545 2546 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2547 atmel_port->suspended = true; 2548 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2549 device_set_wakeup_enable(&pdev->dev, 0); 2550 } 2551 2552 uart_suspend_port(&atmel_uart, port); 2553 2554 return 0; 2555 } 2556 2557 static int atmel_serial_resume(struct platform_device *pdev) 2558 { 2559 struct uart_port *port = platform_get_drvdata(pdev); 2560 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2561 unsigned long flags; 2562 2563 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2564 if (atmel_port->pending) { 2565 atmel_handle_receive(port, atmel_port->pending); 2566 atmel_handle_status(port, atmel_port->pending, 2567 atmel_port->pending_status); 2568 atmel_handle_transmit(port, atmel_port->pending); 2569 atmel_port->pending = 0; 2570 } 2571 atmel_port->suspended = false; 2572 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2573 2574 uart_resume_port(&atmel_uart, port); 2575 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); 2576 2577 return 0; 2578 } 2579 #else 2580 #define atmel_serial_suspend NULL 2581 #define atmel_serial_resume NULL 2582 #endif 2583 2584 static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev) 2585 { 2586 enum mctrl_gpio_idx i; 2587 struct gpio_desc *gpiod; 2588 2589 p->gpios = mctrl_gpio_init(dev, 0); 2590 if (IS_ERR(p->gpios)) 2591 return PTR_ERR(p->gpios); 2592 2593 for (i = 0; i < UART_GPIO_MAX; i++) { 2594 gpiod = mctrl_gpio_to_gpiod(p->gpios, i); 2595 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN)) 2596 p->gpio_irq[i] = gpiod_to_irq(gpiod); 2597 else 2598 p->gpio_irq[i] = -EINVAL; 2599 } 2600 2601 return 0; 2602 } 2603 2604 static int atmel_serial_probe(struct platform_device *pdev) 2605 { 2606 struct atmel_uart_port *port; 2607 struct device_node *np = pdev->dev.of_node; 2608 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2609 void *data; 2610 int ret = -ENODEV; 2611 bool rs485_enabled; 2612 2613 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); 2614 2615 if (np) 2616 ret = of_alias_get_id(np, "serial"); 2617 else 2618 if (pdata) 2619 ret = pdata->num; 2620 2621 if (ret < 0) 2622 /* port id not found in platform data nor device-tree aliases: 2623 * auto-enumerate it */ 2624 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); 2625 2626 if (ret >= ATMEL_MAX_UART) { 2627 ret = -ENODEV; 2628 goto err; 2629 } 2630 2631 if (test_and_set_bit(ret, atmel_ports_in_use)) { 2632 /* port already in use */ 2633 ret = -EBUSY; 2634 goto err; 2635 } 2636 2637 port = &atmel_ports[ret]; 2638 port->backup_imr = 0; 2639 port->uart.line = ret; 2640 2641 spin_lock_init(&port->lock_suspended); 2642 2643 ret = atmel_init_gpios(port, &pdev->dev); 2644 if (ret < 0) { 2645 dev_err(&pdev->dev, "Failed to initialize GPIOs."); 2646 goto err; 2647 } 2648 2649 ret = atmel_init_port(port, pdev); 2650 if (ret) 2651 goto err_clear_bit; 2652 2653 if (!atmel_use_pdc_rx(&port->uart)) { 2654 ret = -ENOMEM; 2655 data = kmalloc(sizeof(struct atmel_uart_char) 2656 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); 2657 if (!data) 2658 goto err_alloc_ring; 2659 port->rx_ring.buf = data; 2660 } 2661 2662 rs485_enabled = port->uart.rs485.flags & SER_RS485_ENABLED; 2663 2664 ret = uart_add_one_port(&atmel_uart, &port->uart); 2665 if (ret) 2666 goto err_add_port; 2667 2668 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2669 if (atmel_is_console_port(&port->uart) 2670 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { 2671 /* 2672 * The serial core enabled the clock for us, so undo 2673 * the clk_prepare_enable() in atmel_console_setup() 2674 */ 2675 clk_disable_unprepare(port->clk); 2676 } 2677 #endif 2678 2679 device_init_wakeup(&pdev->dev, 1); 2680 platform_set_drvdata(pdev, port); 2681 2682 /* 2683 * The peripheral clock has been disabled by atmel_init_port(): 2684 * enable it before accessing I/O registers 2685 */ 2686 clk_prepare_enable(port->clk); 2687 2688 if (rs485_enabled) { 2689 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL); 2690 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN); 2691 } 2692 2693 /* 2694 * Get port name of usart or uart 2695 */ 2696 atmel_get_ip_name(&port->uart); 2697 2698 /* 2699 * The peripheral clock can now safely be disabled till the port 2700 * is used 2701 */ 2702 clk_disable_unprepare(port->clk); 2703 2704 return 0; 2705 2706 err_add_port: 2707 kfree(port->rx_ring.buf); 2708 port->rx_ring.buf = NULL; 2709 err_alloc_ring: 2710 if (!atmel_is_console_port(&port->uart)) { 2711 clk_put(port->clk); 2712 port->clk = NULL; 2713 } 2714 err_clear_bit: 2715 clear_bit(port->uart.line, atmel_ports_in_use); 2716 err: 2717 return ret; 2718 } 2719 2720 static int atmel_serial_remove(struct platform_device *pdev) 2721 { 2722 struct uart_port *port = platform_get_drvdata(pdev); 2723 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2724 int ret = 0; 2725 2726 tasklet_kill(&atmel_port->tasklet); 2727 2728 device_init_wakeup(&pdev->dev, 0); 2729 2730 ret = uart_remove_one_port(&atmel_uart, port); 2731 2732 kfree(atmel_port->rx_ring.buf); 2733 2734 /* "port" is allocated statically, so we shouldn't free it */ 2735 2736 clear_bit(port->line, atmel_ports_in_use); 2737 2738 clk_put(atmel_port->clk); 2739 2740 return ret; 2741 } 2742 2743 static struct platform_driver atmel_serial_driver = { 2744 .probe = atmel_serial_probe, 2745 .remove = atmel_serial_remove, 2746 .suspend = atmel_serial_suspend, 2747 .resume = atmel_serial_resume, 2748 .driver = { 2749 .name = "atmel_usart", 2750 .of_match_table = of_match_ptr(atmel_serial_dt_ids), 2751 }, 2752 }; 2753 2754 static int __init atmel_serial_init(void) 2755 { 2756 int ret; 2757 2758 ret = uart_register_driver(&atmel_uart); 2759 if (ret) 2760 return ret; 2761 2762 ret = platform_driver_register(&atmel_serial_driver); 2763 if (ret) 2764 uart_unregister_driver(&atmel_uart); 2765 2766 return ret; 2767 } 2768 2769 static void __exit atmel_serial_exit(void) 2770 { 2771 platform_driver_unregister(&atmel_serial_driver); 2772 uart_unregister_driver(&atmel_uart); 2773 } 2774 2775 module_init(atmel_serial_init); 2776 module_exit(atmel_serial_exit); 2777 2778 MODULE_AUTHOR("Rick Bronson"); 2779 MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); 2780 MODULE_LICENSE("GPL"); 2781 MODULE_ALIAS("platform:atmel_usart"); 2782