1 /* 2 * Driver for Atmel AT91 / AT32 Serial ports 3 * Copyright (C) 2003 Rick Bronson 4 * 5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. 6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 7 * 8 * DMA support added by Chip Coldwell. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 #include <linux/module.h> 26 #include <linux/tty.h> 27 #include <linux/ioport.h> 28 #include <linux/slab.h> 29 #include <linux/init.h> 30 #include <linux/serial.h> 31 #include <linux/clk.h> 32 #include <linux/console.h> 33 #include <linux/sysrq.h> 34 #include <linux/tty_flip.h> 35 #include <linux/platform_device.h> 36 #include <linux/of.h> 37 #include <linux/of_device.h> 38 #include <linux/of_gpio.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/dmaengine.h> 41 #include <linux/atmel_pdc.h> 42 #include <linux/atmel_serial.h> 43 #include <linux/uaccess.h> 44 #include <linux/platform_data/atmel.h> 45 #include <linux/timer.h> 46 #include <linux/gpio.h> 47 #include <linux/gpio/consumer.h> 48 #include <linux/err.h> 49 #include <linux/irq.h> 50 51 #include <asm/io.h> 52 #include <asm/ioctls.h> 53 54 #define PDC_BUFFER_SIZE 512 55 /* Revisit: We should calculate this based on the actual port settings */ 56 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ 57 58 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 59 #define SUPPORT_SYSRQ 60 #endif 61 62 #include <linux/serial_core.h> 63 64 #include "serial_mctrl_gpio.h" 65 66 static void atmel_start_rx(struct uart_port *port); 67 static void atmel_stop_rx(struct uart_port *port); 68 69 #ifdef CONFIG_SERIAL_ATMEL_TTYAT 70 71 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we 72 * should coexist with the 8250 driver, such as if we have an external 16C550 73 * UART. */ 74 #define SERIAL_ATMEL_MAJOR 204 75 #define MINOR_START 154 76 #define ATMEL_DEVICENAME "ttyAT" 77 78 #else 79 80 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port 81 * name, but it is legally reserved for the 8250 driver. */ 82 #define SERIAL_ATMEL_MAJOR TTY_MAJOR 83 #define MINOR_START 64 84 #define ATMEL_DEVICENAME "ttyS" 85 86 #endif 87 88 #define ATMEL_ISR_PASS_LIMIT 256 89 90 /* UART registers. CR is write-only, hence no GET macro */ 91 #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) 92 #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) 93 #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) 94 #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) 95 #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) 96 #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) 97 #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) 98 #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) 99 #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) 100 #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) 101 #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) 102 #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) 103 #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR) 104 #define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME) 105 #define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION) 106 107 /* PDC registers */ 108 #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) 109 #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) 110 111 #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) 112 #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) 113 #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) 114 #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) 115 #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) 116 117 #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) 118 #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) 119 #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR) 120 121 struct atmel_dma_buffer { 122 unsigned char *buf; 123 dma_addr_t dma_addr; 124 unsigned int dma_size; 125 unsigned int ofs; 126 }; 127 128 struct atmel_uart_char { 129 u16 status; 130 u16 ch; 131 }; 132 133 #define ATMEL_SERIAL_RINGSIZE 1024 134 135 /* 136 * We wrap our port structure around the generic uart_port. 137 */ 138 struct atmel_uart_port { 139 struct uart_port uart; /* uart */ 140 struct clk *clk; /* uart clock */ 141 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ 142 u32 backup_imr; /* IMR saved during suspend */ 143 int break_active; /* break being received */ 144 145 bool use_dma_rx; /* enable DMA receiver */ 146 bool use_pdc_rx; /* enable PDC receiver */ 147 short pdc_rx_idx; /* current PDC RX buffer */ 148 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ 149 150 bool use_dma_tx; /* enable DMA transmitter */ 151 bool use_pdc_tx; /* enable PDC transmitter */ 152 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ 153 154 spinlock_t lock_tx; /* port lock */ 155 spinlock_t lock_rx; /* port lock */ 156 struct dma_chan *chan_tx; 157 struct dma_chan *chan_rx; 158 struct dma_async_tx_descriptor *desc_tx; 159 struct dma_async_tx_descriptor *desc_rx; 160 dma_cookie_t cookie_tx; 161 dma_cookie_t cookie_rx; 162 struct scatterlist sg_tx; 163 struct scatterlist sg_rx; 164 struct tasklet_struct tasklet; 165 unsigned int irq_status; 166 unsigned int irq_status_prev; 167 168 struct circ_buf rx_ring; 169 170 struct serial_rs485 rs485; /* rs485 settings */ 171 struct mctrl_gpios *gpios; 172 int gpio_irq[UART_GPIO_MAX]; 173 unsigned int tx_done_mask; 174 bool ms_irq_enabled; 175 bool is_usart; /* usart or uart */ 176 struct timer_list uart_timer; /* uart timer */ 177 int (*prepare_rx)(struct uart_port *port); 178 int (*prepare_tx)(struct uart_port *port); 179 void (*schedule_rx)(struct uart_port *port); 180 void (*schedule_tx)(struct uart_port *port); 181 void (*release_rx)(struct uart_port *port); 182 void (*release_tx)(struct uart_port *port); 183 }; 184 185 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; 186 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); 187 188 #ifdef SUPPORT_SYSRQ 189 static struct console atmel_console; 190 #endif 191 192 #if defined(CONFIG_OF) 193 static const struct of_device_id atmel_serial_dt_ids[] = { 194 { .compatible = "atmel,at91rm9200-usart" }, 195 { .compatible = "atmel,at91sam9260-usart" }, 196 { /* sentinel */ } 197 }; 198 199 MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids); 200 #endif 201 202 static inline struct atmel_uart_port * 203 to_atmel_uart_port(struct uart_port *uart) 204 { 205 return container_of(uart, struct atmel_uart_port, uart); 206 } 207 208 #ifdef CONFIG_SERIAL_ATMEL_PDC 209 static bool atmel_use_pdc_rx(struct uart_port *port) 210 { 211 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 212 213 return atmel_port->use_pdc_rx; 214 } 215 216 static bool atmel_use_pdc_tx(struct uart_port *port) 217 { 218 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 219 220 return atmel_port->use_pdc_tx; 221 } 222 #else 223 static bool atmel_use_pdc_rx(struct uart_port *port) 224 { 225 return false; 226 } 227 228 static bool atmel_use_pdc_tx(struct uart_port *port) 229 { 230 return false; 231 } 232 #endif 233 234 static bool atmel_use_dma_tx(struct uart_port *port) 235 { 236 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 237 238 return atmel_port->use_dma_tx; 239 } 240 241 static bool atmel_use_dma_rx(struct uart_port *port) 242 { 243 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 244 245 return atmel_port->use_dma_rx; 246 } 247 248 static unsigned int atmel_get_lines_status(struct uart_port *port) 249 { 250 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 251 unsigned int status, ret = 0; 252 253 status = UART_GET_CSR(port); 254 255 mctrl_gpio_get(atmel_port->gpios, &ret); 256 257 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 258 UART_GPIO_CTS))) { 259 if (ret & TIOCM_CTS) 260 status &= ~ATMEL_US_CTS; 261 else 262 status |= ATMEL_US_CTS; 263 } 264 265 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 266 UART_GPIO_DSR))) { 267 if (ret & TIOCM_DSR) 268 status &= ~ATMEL_US_DSR; 269 else 270 status |= ATMEL_US_DSR; 271 } 272 273 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 274 UART_GPIO_RI))) { 275 if (ret & TIOCM_RI) 276 status &= ~ATMEL_US_RI; 277 else 278 status |= ATMEL_US_RI; 279 } 280 281 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 282 UART_GPIO_DCD))) { 283 if (ret & TIOCM_CD) 284 status &= ~ATMEL_US_DCD; 285 else 286 status |= ATMEL_US_DCD; 287 } 288 289 return status; 290 } 291 292 /* Enable or disable the rs485 support */ 293 void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf) 294 { 295 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 296 unsigned int mode; 297 unsigned long flags; 298 299 spin_lock_irqsave(&port->lock, flags); 300 301 /* Disable interrupts */ 302 UART_PUT_IDR(port, atmel_port->tx_done_mask); 303 304 mode = UART_GET_MR(port); 305 306 /* Resetting serial mode to RS232 (0x0) */ 307 mode &= ~ATMEL_US_USMODE; 308 309 atmel_port->rs485 = *rs485conf; 310 311 if (rs485conf->flags & SER_RS485_ENABLED) { 312 dev_dbg(port->dev, "Setting UART to RS485\n"); 313 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 314 if ((rs485conf->delay_rts_after_send) > 0) 315 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send); 316 mode |= ATMEL_US_USMODE_RS485; 317 } else { 318 dev_dbg(port->dev, "Setting UART to RS232\n"); 319 if (atmel_use_pdc_tx(port)) 320 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 321 ATMEL_US_TXBUFE; 322 else 323 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 324 } 325 UART_PUT_MR(port, mode); 326 327 /* Enable interrupts */ 328 UART_PUT_IER(port, atmel_port->tx_done_mask); 329 330 spin_unlock_irqrestore(&port->lock, flags); 331 332 } 333 334 /* 335 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. 336 */ 337 static u_int atmel_tx_empty(struct uart_port *port) 338 { 339 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; 340 } 341 342 /* 343 * Set state of the modem control output lines 344 */ 345 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) 346 { 347 unsigned int control = 0; 348 unsigned int mode; 349 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 350 351 if (mctrl & TIOCM_RTS) 352 control |= ATMEL_US_RTSEN; 353 else 354 control |= ATMEL_US_RTSDIS; 355 356 if (mctrl & TIOCM_DTR) 357 control |= ATMEL_US_DTREN; 358 else 359 control |= ATMEL_US_DTRDIS; 360 361 UART_PUT_CR(port, control); 362 363 mctrl_gpio_set(atmel_port->gpios, mctrl); 364 365 /* Local loopback mode? */ 366 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE; 367 if (mctrl & TIOCM_LOOP) 368 mode |= ATMEL_US_CHMODE_LOC_LOOP; 369 else 370 mode |= ATMEL_US_CHMODE_NORMAL; 371 372 /* Resetting serial mode to RS232 (0x0) */ 373 mode &= ~ATMEL_US_USMODE; 374 375 if (atmel_port->rs485.flags & SER_RS485_ENABLED) { 376 dev_dbg(port->dev, "Setting UART to RS485\n"); 377 if ((atmel_port->rs485.delay_rts_after_send) > 0) 378 UART_PUT_TTGR(port, 379 atmel_port->rs485.delay_rts_after_send); 380 mode |= ATMEL_US_USMODE_RS485; 381 } else { 382 dev_dbg(port->dev, "Setting UART to RS232\n"); 383 } 384 UART_PUT_MR(port, mode); 385 } 386 387 /* 388 * Get state of the modem control input lines 389 */ 390 static u_int atmel_get_mctrl(struct uart_port *port) 391 { 392 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 393 unsigned int ret = 0, status; 394 395 status = UART_GET_CSR(port); 396 397 /* 398 * The control signals are active low. 399 */ 400 if (!(status & ATMEL_US_DCD)) 401 ret |= TIOCM_CD; 402 if (!(status & ATMEL_US_CTS)) 403 ret |= TIOCM_CTS; 404 if (!(status & ATMEL_US_DSR)) 405 ret |= TIOCM_DSR; 406 if (!(status & ATMEL_US_RI)) 407 ret |= TIOCM_RI; 408 409 return mctrl_gpio_get(atmel_port->gpios, &ret); 410 } 411 412 /* 413 * Stop transmitting. 414 */ 415 static void atmel_stop_tx(struct uart_port *port) 416 { 417 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 418 419 if (atmel_use_pdc_tx(port)) { 420 /* disable PDC transmit */ 421 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 422 } 423 /* Disable interrupts */ 424 UART_PUT_IDR(port, atmel_port->tx_done_mask); 425 426 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && 427 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) 428 atmel_start_rx(port); 429 } 430 431 /* 432 * Start transmitting. 433 */ 434 static void atmel_start_tx(struct uart_port *port) 435 { 436 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 437 438 if (atmel_use_pdc_tx(port)) { 439 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) 440 /* The transmitter is already running. Yes, we 441 really need this.*/ 442 return; 443 444 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && 445 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) 446 atmel_stop_rx(port); 447 448 /* re-enable PDC transmit */ 449 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 450 } 451 /* Enable interrupts */ 452 UART_PUT_IER(port, atmel_port->tx_done_mask); 453 } 454 455 /* 456 * start receiving - port is in process of being opened. 457 */ 458 static void atmel_start_rx(struct uart_port *port) 459 { 460 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */ 461 462 UART_PUT_CR(port, ATMEL_US_RXEN); 463 464 if (atmel_use_pdc_rx(port)) { 465 /* enable PDC controller */ 466 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 467 port->read_status_mask); 468 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); 469 } else { 470 UART_PUT_IER(port, ATMEL_US_RXRDY); 471 } 472 } 473 474 /* 475 * Stop receiving - port is in process of being closed. 476 */ 477 static void atmel_stop_rx(struct uart_port *port) 478 { 479 UART_PUT_CR(port, ATMEL_US_RXDIS); 480 481 if (atmel_use_pdc_rx(port)) { 482 /* disable PDC receive */ 483 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); 484 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 485 port->read_status_mask); 486 } else { 487 UART_PUT_IDR(port, ATMEL_US_RXRDY); 488 } 489 } 490 491 /* 492 * Enable modem status interrupts 493 */ 494 static void atmel_enable_ms(struct uart_port *port) 495 { 496 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 497 uint32_t ier = 0; 498 499 /* 500 * Interrupt should not be enabled twice 501 */ 502 if (atmel_port->ms_irq_enabled) 503 return; 504 505 atmel_port->ms_irq_enabled = true; 506 507 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0) 508 enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]); 509 else 510 ier |= ATMEL_US_CTSIC; 511 512 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0) 513 enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]); 514 else 515 ier |= ATMEL_US_DSRIC; 516 517 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0) 518 enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]); 519 else 520 ier |= ATMEL_US_RIIC; 521 522 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0) 523 enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]); 524 else 525 ier |= ATMEL_US_DCDIC; 526 527 UART_PUT_IER(port, ier); 528 } 529 530 /* 531 * Disable modem status interrupts 532 */ 533 static void atmel_disable_ms(struct uart_port *port) 534 { 535 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 536 uint32_t idr = 0; 537 538 /* 539 * Interrupt should not be disabled twice 540 */ 541 if (!atmel_port->ms_irq_enabled) 542 return; 543 544 atmel_port->ms_irq_enabled = false; 545 546 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0) 547 disable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]); 548 else 549 idr |= ATMEL_US_CTSIC; 550 551 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0) 552 disable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]); 553 else 554 idr |= ATMEL_US_DSRIC; 555 556 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0) 557 disable_irq(atmel_port->gpio_irq[UART_GPIO_RI]); 558 else 559 idr |= ATMEL_US_RIIC; 560 561 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0) 562 disable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]); 563 else 564 idr |= ATMEL_US_DCDIC; 565 566 UART_PUT_IDR(port, idr); 567 } 568 569 /* 570 * Control the transmission of a break signal 571 */ 572 static void atmel_break_ctl(struct uart_port *port, int break_state) 573 { 574 if (break_state != 0) 575 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ 576 else 577 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ 578 } 579 580 /* 581 * Stores the incoming character in the ring buffer 582 */ 583 static void 584 atmel_buffer_rx_char(struct uart_port *port, unsigned int status, 585 unsigned int ch) 586 { 587 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 588 struct circ_buf *ring = &atmel_port->rx_ring; 589 struct atmel_uart_char *c; 590 591 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) 592 /* Buffer overflow, ignore char */ 593 return; 594 595 c = &((struct atmel_uart_char *)ring->buf)[ring->head]; 596 c->status = status; 597 c->ch = ch; 598 599 /* Make sure the character is stored before we update head. */ 600 smp_wmb(); 601 602 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 603 } 604 605 /* 606 * Deal with parity, framing and overrun errors. 607 */ 608 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) 609 { 610 /* clear error */ 611 UART_PUT_CR(port, ATMEL_US_RSTSTA); 612 613 if (status & ATMEL_US_RXBRK) { 614 /* ignore side-effect */ 615 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 616 port->icount.brk++; 617 } 618 if (status & ATMEL_US_PARE) 619 port->icount.parity++; 620 if (status & ATMEL_US_FRAME) 621 port->icount.frame++; 622 if (status & ATMEL_US_OVRE) 623 port->icount.overrun++; 624 } 625 626 /* 627 * Characters received (called from interrupt handler) 628 */ 629 static void atmel_rx_chars(struct uart_port *port) 630 { 631 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 632 unsigned int status, ch; 633 634 status = UART_GET_CSR(port); 635 while (status & ATMEL_US_RXRDY) { 636 ch = UART_GET_CHAR(port); 637 638 /* 639 * note that the error handling code is 640 * out of the main execution path 641 */ 642 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 643 | ATMEL_US_OVRE | ATMEL_US_RXBRK) 644 || atmel_port->break_active)) { 645 646 /* clear error */ 647 UART_PUT_CR(port, ATMEL_US_RSTSTA); 648 649 if (status & ATMEL_US_RXBRK 650 && !atmel_port->break_active) { 651 atmel_port->break_active = 1; 652 UART_PUT_IER(port, ATMEL_US_RXBRK); 653 } else { 654 /* 655 * This is either the end-of-break 656 * condition or we've received at 657 * least one character without RXBRK 658 * being set. In both cases, the next 659 * RXBRK will indicate start-of-break. 660 */ 661 UART_PUT_IDR(port, ATMEL_US_RXBRK); 662 status &= ~ATMEL_US_RXBRK; 663 atmel_port->break_active = 0; 664 } 665 } 666 667 atmel_buffer_rx_char(port, status, ch); 668 status = UART_GET_CSR(port); 669 } 670 671 tasklet_schedule(&atmel_port->tasklet); 672 } 673 674 /* 675 * Transmit characters (called from tasklet with TXRDY interrupt 676 * disabled) 677 */ 678 static void atmel_tx_chars(struct uart_port *port) 679 { 680 struct circ_buf *xmit = &port->state->xmit; 681 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 682 683 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) { 684 UART_PUT_CHAR(port, port->x_char); 685 port->icount.tx++; 686 port->x_char = 0; 687 } 688 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 689 return; 690 691 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) { 692 UART_PUT_CHAR(port, xmit->buf[xmit->tail]); 693 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 694 port->icount.tx++; 695 if (uart_circ_empty(xmit)) 696 break; 697 } 698 699 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 700 uart_write_wakeup(port); 701 702 if (!uart_circ_empty(xmit)) 703 /* Enable interrupts */ 704 UART_PUT_IER(port, atmel_port->tx_done_mask); 705 } 706 707 static void atmel_complete_tx_dma(void *arg) 708 { 709 struct atmel_uart_port *atmel_port = arg; 710 struct uart_port *port = &atmel_port->uart; 711 struct circ_buf *xmit = &port->state->xmit; 712 struct dma_chan *chan = atmel_port->chan_tx; 713 unsigned long flags; 714 715 spin_lock_irqsave(&port->lock, flags); 716 717 if (chan) 718 dmaengine_terminate_all(chan); 719 xmit->tail += sg_dma_len(&atmel_port->sg_tx); 720 xmit->tail &= UART_XMIT_SIZE - 1; 721 722 port->icount.tx += sg_dma_len(&atmel_port->sg_tx); 723 724 spin_lock_irq(&atmel_port->lock_tx); 725 async_tx_ack(atmel_port->desc_tx); 726 atmel_port->cookie_tx = -EINVAL; 727 atmel_port->desc_tx = NULL; 728 spin_unlock_irq(&atmel_port->lock_tx); 729 730 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 731 uart_write_wakeup(port); 732 733 /* Do we really need this? */ 734 if (!uart_circ_empty(xmit)) 735 tasklet_schedule(&atmel_port->tasklet); 736 737 spin_unlock_irqrestore(&port->lock, flags); 738 } 739 740 static void atmel_release_tx_dma(struct uart_port *port) 741 { 742 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 743 struct dma_chan *chan = atmel_port->chan_tx; 744 745 if (chan) { 746 dmaengine_terminate_all(chan); 747 dma_release_channel(chan); 748 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, 749 DMA_TO_DEVICE); 750 } 751 752 atmel_port->desc_tx = NULL; 753 atmel_port->chan_tx = NULL; 754 atmel_port->cookie_tx = -EINVAL; 755 } 756 757 /* 758 * Called from tasklet with TXRDY interrupt is disabled. 759 */ 760 static void atmel_tx_dma(struct uart_port *port) 761 { 762 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 763 struct circ_buf *xmit = &port->state->xmit; 764 struct dma_chan *chan = atmel_port->chan_tx; 765 struct dma_async_tx_descriptor *desc; 766 struct scatterlist *sg = &atmel_port->sg_tx; 767 768 /* Make sure we have an idle channel */ 769 if (atmel_port->desc_tx != NULL) 770 return; 771 772 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 773 /* 774 * DMA is idle now. 775 * Port xmit buffer is already mapped, 776 * and it is one page... Just adjust 777 * offsets and lengths. Since it is a circular buffer, 778 * we have to transmit till the end, and then the rest. 779 * Take the port lock to get a 780 * consistent xmit buffer state. 781 */ 782 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 783 sg_dma_address(sg) = (sg_dma_address(sg) & 784 ~(UART_XMIT_SIZE - 1)) 785 + sg->offset; 786 sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head, 787 xmit->tail, 788 UART_XMIT_SIZE); 789 BUG_ON(!sg_dma_len(sg)); 790 791 desc = dmaengine_prep_slave_sg(chan, 792 sg, 793 1, 794 DMA_MEM_TO_DEV, 795 DMA_PREP_INTERRUPT | 796 DMA_CTRL_ACK); 797 if (!desc) { 798 dev_err(port->dev, "Failed to send via dma!\n"); 799 return; 800 } 801 802 dma_sync_sg_for_device(port->dev, sg, 1, DMA_MEM_TO_DEV); 803 804 atmel_port->desc_tx = desc; 805 desc->callback = atmel_complete_tx_dma; 806 desc->callback_param = atmel_port; 807 atmel_port->cookie_tx = dmaengine_submit(desc); 808 809 } else { 810 if (atmel_port->rs485.flags & SER_RS485_ENABLED) { 811 /* DMA done, stop TX, start RX for RS485 */ 812 atmel_start_rx(port); 813 } 814 } 815 816 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 817 uart_write_wakeup(port); 818 } 819 820 static int atmel_prepare_tx_dma(struct uart_port *port) 821 { 822 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 823 dma_cap_mask_t mask; 824 struct dma_slave_config config; 825 int ret, nent; 826 827 dma_cap_zero(mask); 828 dma_cap_set(DMA_SLAVE, mask); 829 830 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx"); 831 if (atmel_port->chan_tx == NULL) 832 goto chan_err; 833 dev_info(port->dev, "using %s for tx DMA transfers\n", 834 dma_chan_name(atmel_port->chan_tx)); 835 836 spin_lock_init(&atmel_port->lock_tx); 837 sg_init_table(&atmel_port->sg_tx, 1); 838 /* UART circular tx buffer is an aligned page. */ 839 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); 840 sg_set_page(&atmel_port->sg_tx, 841 virt_to_page(port->state->xmit.buf), 842 UART_XMIT_SIZE, 843 (int)port->state->xmit.buf & ~PAGE_MASK); 844 nent = dma_map_sg(port->dev, 845 &atmel_port->sg_tx, 846 1, 847 DMA_TO_DEVICE); 848 849 if (!nent) { 850 dev_dbg(port->dev, "need to release resource of dma\n"); 851 goto chan_err; 852 } else { 853 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 854 sg_dma_len(&atmel_port->sg_tx), 855 port->state->xmit.buf, 856 sg_dma_address(&atmel_port->sg_tx)); 857 } 858 859 /* Configure the slave DMA */ 860 memset(&config, 0, sizeof(config)); 861 config.direction = DMA_MEM_TO_DEV; 862 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 863 config.dst_addr = port->mapbase + ATMEL_US_THR; 864 865 ret = dmaengine_device_control(atmel_port->chan_tx, 866 DMA_SLAVE_CONFIG, 867 (unsigned long)&config); 868 if (ret) { 869 dev_err(port->dev, "DMA tx slave configuration failed\n"); 870 goto chan_err; 871 } 872 873 return 0; 874 875 chan_err: 876 dev_err(port->dev, "TX channel not available, switch to pio\n"); 877 atmel_port->use_dma_tx = 0; 878 if (atmel_port->chan_tx) 879 atmel_release_tx_dma(port); 880 return -EINVAL; 881 } 882 883 static void atmel_flip_buffer_rx_dma(struct uart_port *port, 884 char *buf, size_t count) 885 { 886 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 887 struct tty_port *tport = &port->state->port; 888 889 dma_sync_sg_for_cpu(port->dev, 890 &atmel_port->sg_rx, 891 1, 892 DMA_DEV_TO_MEM); 893 894 tty_insert_flip_string(tport, buf, count); 895 896 dma_sync_sg_for_device(port->dev, 897 &atmel_port->sg_rx, 898 1, 899 DMA_DEV_TO_MEM); 900 /* 901 * Drop the lock here since it might end up calling 902 * uart_start(), which takes the lock. 903 */ 904 spin_unlock(&port->lock); 905 tty_flip_buffer_push(tport); 906 spin_lock(&port->lock); 907 } 908 909 static void atmel_complete_rx_dma(void *arg) 910 { 911 struct uart_port *port = arg; 912 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 913 914 tasklet_schedule(&atmel_port->tasklet); 915 } 916 917 static void atmel_release_rx_dma(struct uart_port *port) 918 { 919 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 920 struct dma_chan *chan = atmel_port->chan_rx; 921 922 if (chan) { 923 dmaengine_terminate_all(chan); 924 dma_release_channel(chan); 925 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, 926 DMA_FROM_DEVICE); 927 } 928 929 atmel_port->desc_rx = NULL; 930 atmel_port->chan_rx = NULL; 931 atmel_port->cookie_rx = -EINVAL; 932 } 933 934 static void atmel_rx_from_dma(struct uart_port *port) 935 { 936 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 937 struct circ_buf *ring = &atmel_port->rx_ring; 938 struct dma_chan *chan = atmel_port->chan_rx; 939 struct dma_tx_state state; 940 enum dma_status dmastat; 941 size_t pending, count; 942 943 944 /* Reset the UART timeout early so that we don't miss one */ 945 UART_PUT_CR(port, ATMEL_US_STTTO); 946 dmastat = dmaengine_tx_status(chan, 947 atmel_port->cookie_rx, 948 &state); 949 /* Restart a new tasklet if DMA status is error */ 950 if (dmastat == DMA_ERROR) { 951 dev_dbg(port->dev, "Get residue error, restart tasklet\n"); 952 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 953 tasklet_schedule(&atmel_port->tasklet); 954 return; 955 } 956 /* current transfer size should no larger than dma buffer */ 957 pending = sg_dma_len(&atmel_port->sg_rx) - state.residue; 958 BUG_ON(pending > sg_dma_len(&atmel_port->sg_rx)); 959 960 /* 961 * This will take the chars we have so far, 962 * ring->head will record the transfer size, only new bytes come 963 * will insert into the framework. 964 */ 965 if (pending > ring->head) { 966 count = pending - ring->head; 967 968 atmel_flip_buffer_rx_dma(port, ring->buf + ring->head, count); 969 970 ring->head += count; 971 if (ring->head == sg_dma_len(&atmel_port->sg_rx)) 972 ring->head = 0; 973 974 port->icount.rx += count; 975 } 976 977 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 978 } 979 980 static int atmel_prepare_rx_dma(struct uart_port *port) 981 { 982 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 983 struct dma_async_tx_descriptor *desc; 984 dma_cap_mask_t mask; 985 struct dma_slave_config config; 986 struct circ_buf *ring; 987 int ret, nent; 988 989 ring = &atmel_port->rx_ring; 990 991 dma_cap_zero(mask); 992 dma_cap_set(DMA_CYCLIC, mask); 993 994 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx"); 995 if (atmel_port->chan_rx == NULL) 996 goto chan_err; 997 dev_info(port->dev, "using %s for rx DMA transfers\n", 998 dma_chan_name(atmel_port->chan_rx)); 999 1000 spin_lock_init(&atmel_port->lock_rx); 1001 sg_init_table(&atmel_port->sg_rx, 1); 1002 /* UART circular rx buffer is an aligned page. */ 1003 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); 1004 sg_set_page(&atmel_port->sg_rx, 1005 virt_to_page(ring->buf), 1006 ATMEL_SERIAL_RINGSIZE, 1007 (int)ring->buf & ~PAGE_MASK); 1008 nent = dma_map_sg(port->dev, 1009 &atmel_port->sg_rx, 1010 1, 1011 DMA_FROM_DEVICE); 1012 1013 if (!nent) { 1014 dev_dbg(port->dev, "need to release resource of dma\n"); 1015 goto chan_err; 1016 } else { 1017 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 1018 sg_dma_len(&atmel_port->sg_rx), 1019 ring->buf, 1020 sg_dma_address(&atmel_port->sg_rx)); 1021 } 1022 1023 /* Configure the slave DMA */ 1024 memset(&config, 0, sizeof(config)); 1025 config.direction = DMA_DEV_TO_MEM; 1026 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1027 config.src_addr = port->mapbase + ATMEL_US_RHR; 1028 1029 ret = dmaengine_device_control(atmel_port->chan_rx, 1030 DMA_SLAVE_CONFIG, 1031 (unsigned long)&config); 1032 if (ret) { 1033 dev_err(port->dev, "DMA rx slave configuration failed\n"); 1034 goto chan_err; 1035 } 1036 /* 1037 * Prepare a cyclic dma transfer, assign 2 descriptors, 1038 * each one is half ring buffer size 1039 */ 1040 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, 1041 sg_dma_address(&atmel_port->sg_rx), 1042 sg_dma_len(&atmel_port->sg_rx), 1043 sg_dma_len(&atmel_port->sg_rx)/2, 1044 DMA_DEV_TO_MEM, 1045 DMA_PREP_INTERRUPT); 1046 desc->callback = atmel_complete_rx_dma; 1047 desc->callback_param = port; 1048 atmel_port->desc_rx = desc; 1049 atmel_port->cookie_rx = dmaengine_submit(desc); 1050 1051 return 0; 1052 1053 chan_err: 1054 dev_err(port->dev, "RX channel not available, switch to pio\n"); 1055 atmel_port->use_dma_rx = 0; 1056 if (atmel_port->chan_rx) 1057 atmel_release_rx_dma(port); 1058 return -EINVAL; 1059 } 1060 1061 static void atmel_uart_timer_callback(unsigned long data) 1062 { 1063 struct uart_port *port = (void *)data; 1064 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1065 1066 tasklet_schedule(&atmel_port->tasklet); 1067 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port)); 1068 } 1069 1070 /* 1071 * receive interrupt handler. 1072 */ 1073 static void 1074 atmel_handle_receive(struct uart_port *port, unsigned int pending) 1075 { 1076 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1077 1078 if (atmel_use_pdc_rx(port)) { 1079 /* 1080 * PDC receive. Just schedule the tasklet and let it 1081 * figure out the details. 1082 * 1083 * TODO: We're not handling error flags correctly at 1084 * the moment. 1085 */ 1086 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { 1087 UART_PUT_IDR(port, (ATMEL_US_ENDRX 1088 | ATMEL_US_TIMEOUT)); 1089 tasklet_schedule(&atmel_port->tasklet); 1090 } 1091 1092 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | 1093 ATMEL_US_FRAME | ATMEL_US_PARE)) 1094 atmel_pdc_rxerr(port, pending); 1095 } 1096 1097 if (atmel_use_dma_rx(port)) { 1098 if (pending & ATMEL_US_TIMEOUT) { 1099 UART_PUT_IDR(port, ATMEL_US_TIMEOUT); 1100 tasklet_schedule(&atmel_port->tasklet); 1101 } 1102 } 1103 1104 /* Interrupt receive */ 1105 if (pending & ATMEL_US_RXRDY) 1106 atmel_rx_chars(port); 1107 else if (pending & ATMEL_US_RXBRK) { 1108 /* 1109 * End of break detected. If it came along with a 1110 * character, atmel_rx_chars will handle it. 1111 */ 1112 UART_PUT_CR(port, ATMEL_US_RSTSTA); 1113 UART_PUT_IDR(port, ATMEL_US_RXBRK); 1114 atmel_port->break_active = 0; 1115 } 1116 } 1117 1118 /* 1119 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) 1120 */ 1121 static void 1122 atmel_handle_transmit(struct uart_port *port, unsigned int pending) 1123 { 1124 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1125 1126 if (pending & atmel_port->tx_done_mask) { 1127 /* Either PDC or interrupt transmission */ 1128 UART_PUT_IDR(port, atmel_port->tx_done_mask); 1129 tasklet_schedule(&atmel_port->tasklet); 1130 } 1131 } 1132 1133 /* 1134 * status flags interrupt handler. 1135 */ 1136 static void 1137 atmel_handle_status(struct uart_port *port, unsigned int pending, 1138 unsigned int status) 1139 { 1140 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1141 1142 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC 1143 | ATMEL_US_CTSIC)) { 1144 atmel_port->irq_status = status; 1145 tasklet_schedule(&atmel_port->tasklet); 1146 } 1147 } 1148 1149 /* 1150 * Interrupt handler 1151 */ 1152 static irqreturn_t atmel_interrupt(int irq, void *dev_id) 1153 { 1154 struct uart_port *port = dev_id; 1155 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1156 unsigned int status, pending, pass_counter = 0; 1157 bool gpio_handled = false; 1158 1159 do { 1160 status = atmel_get_lines_status(port); 1161 pending = status & UART_GET_IMR(port); 1162 if (!gpio_handled) { 1163 /* 1164 * Dealing with GPIO interrupt 1165 */ 1166 if (irq == atmel_port->gpio_irq[UART_GPIO_CTS]) 1167 pending |= ATMEL_US_CTSIC; 1168 1169 if (irq == atmel_port->gpio_irq[UART_GPIO_DSR]) 1170 pending |= ATMEL_US_DSRIC; 1171 1172 if (irq == atmel_port->gpio_irq[UART_GPIO_RI]) 1173 pending |= ATMEL_US_RIIC; 1174 1175 if (irq == atmel_port->gpio_irq[UART_GPIO_DCD]) 1176 pending |= ATMEL_US_DCDIC; 1177 1178 gpio_handled = true; 1179 } 1180 if (!pending) 1181 break; 1182 1183 atmel_handle_receive(port, pending); 1184 atmel_handle_status(port, pending, status); 1185 atmel_handle_transmit(port, pending); 1186 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); 1187 1188 return pass_counter ? IRQ_HANDLED : IRQ_NONE; 1189 } 1190 1191 static void atmel_release_tx_pdc(struct uart_port *port) 1192 { 1193 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1194 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1195 1196 dma_unmap_single(port->dev, 1197 pdc->dma_addr, 1198 pdc->dma_size, 1199 DMA_TO_DEVICE); 1200 } 1201 1202 /* 1203 * Called from tasklet with ENDTX and TXBUFE interrupts disabled. 1204 */ 1205 static void atmel_tx_pdc(struct uart_port *port) 1206 { 1207 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1208 struct circ_buf *xmit = &port->state->xmit; 1209 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1210 int count; 1211 1212 /* nothing left to transmit? */ 1213 if (UART_GET_TCR(port)) 1214 return; 1215 1216 xmit->tail += pdc->ofs; 1217 xmit->tail &= UART_XMIT_SIZE - 1; 1218 1219 port->icount.tx += pdc->ofs; 1220 pdc->ofs = 0; 1221 1222 /* more to transmit - setup next transfer */ 1223 1224 /* disable PDC transmit */ 1225 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 1226 1227 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 1228 dma_sync_single_for_device(port->dev, 1229 pdc->dma_addr, 1230 pdc->dma_size, 1231 DMA_TO_DEVICE); 1232 1233 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1234 pdc->ofs = count; 1235 1236 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); 1237 UART_PUT_TCR(port, count); 1238 /* re-enable PDC transmit */ 1239 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 1240 /* Enable interrupts */ 1241 UART_PUT_IER(port, atmel_port->tx_done_mask); 1242 } else { 1243 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && 1244 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) { 1245 /* DMA done, stop TX, start RX for RS485 */ 1246 atmel_start_rx(port); 1247 } 1248 } 1249 1250 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1251 uart_write_wakeup(port); 1252 } 1253 1254 static int atmel_prepare_tx_pdc(struct uart_port *port) 1255 { 1256 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1257 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1258 struct circ_buf *xmit = &port->state->xmit; 1259 1260 pdc->buf = xmit->buf; 1261 pdc->dma_addr = dma_map_single(port->dev, 1262 pdc->buf, 1263 UART_XMIT_SIZE, 1264 DMA_TO_DEVICE); 1265 pdc->dma_size = UART_XMIT_SIZE; 1266 pdc->ofs = 0; 1267 1268 return 0; 1269 } 1270 1271 static void atmel_rx_from_ring(struct uart_port *port) 1272 { 1273 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1274 struct circ_buf *ring = &atmel_port->rx_ring; 1275 unsigned int flg; 1276 unsigned int status; 1277 1278 while (ring->head != ring->tail) { 1279 struct atmel_uart_char c; 1280 1281 /* Make sure c is loaded after head. */ 1282 smp_rmb(); 1283 1284 c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; 1285 1286 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 1287 1288 port->icount.rx++; 1289 status = c.status; 1290 flg = TTY_NORMAL; 1291 1292 /* 1293 * note that the error handling code is 1294 * out of the main execution path 1295 */ 1296 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 1297 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { 1298 if (status & ATMEL_US_RXBRK) { 1299 /* ignore side-effect */ 1300 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 1301 1302 port->icount.brk++; 1303 if (uart_handle_break(port)) 1304 continue; 1305 } 1306 if (status & ATMEL_US_PARE) 1307 port->icount.parity++; 1308 if (status & ATMEL_US_FRAME) 1309 port->icount.frame++; 1310 if (status & ATMEL_US_OVRE) 1311 port->icount.overrun++; 1312 1313 status &= port->read_status_mask; 1314 1315 if (status & ATMEL_US_RXBRK) 1316 flg = TTY_BREAK; 1317 else if (status & ATMEL_US_PARE) 1318 flg = TTY_PARITY; 1319 else if (status & ATMEL_US_FRAME) 1320 flg = TTY_FRAME; 1321 } 1322 1323 1324 if (uart_handle_sysrq_char(port, c.ch)) 1325 continue; 1326 1327 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); 1328 } 1329 1330 /* 1331 * Drop the lock here since it might end up calling 1332 * uart_start(), which takes the lock. 1333 */ 1334 spin_unlock(&port->lock); 1335 tty_flip_buffer_push(&port->state->port); 1336 spin_lock(&port->lock); 1337 } 1338 1339 static void atmel_release_rx_pdc(struct uart_port *port) 1340 { 1341 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1342 int i; 1343 1344 for (i = 0; i < 2; i++) { 1345 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1346 1347 dma_unmap_single(port->dev, 1348 pdc->dma_addr, 1349 pdc->dma_size, 1350 DMA_FROM_DEVICE); 1351 kfree(pdc->buf); 1352 } 1353 } 1354 1355 static void atmel_rx_from_pdc(struct uart_port *port) 1356 { 1357 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1358 struct tty_port *tport = &port->state->port; 1359 struct atmel_dma_buffer *pdc; 1360 int rx_idx = atmel_port->pdc_rx_idx; 1361 unsigned int head; 1362 unsigned int tail; 1363 unsigned int count; 1364 1365 do { 1366 /* Reset the UART timeout early so that we don't miss one */ 1367 UART_PUT_CR(port, ATMEL_US_STTTO); 1368 1369 pdc = &atmel_port->pdc_rx[rx_idx]; 1370 head = UART_GET_RPR(port) - pdc->dma_addr; 1371 tail = pdc->ofs; 1372 1373 /* If the PDC has switched buffers, RPR won't contain 1374 * any address within the current buffer. Since head 1375 * is unsigned, we just need a one-way comparison to 1376 * find out. 1377 * 1378 * In this case, we just need to consume the entire 1379 * buffer and resubmit it for DMA. This will clear the 1380 * ENDRX bit as well, so that we can safely re-enable 1381 * all interrupts below. 1382 */ 1383 head = min(head, pdc->dma_size); 1384 1385 if (likely(head != tail)) { 1386 dma_sync_single_for_cpu(port->dev, pdc->dma_addr, 1387 pdc->dma_size, DMA_FROM_DEVICE); 1388 1389 /* 1390 * head will only wrap around when we recycle 1391 * the DMA buffer, and when that happens, we 1392 * explicitly set tail to 0. So head will 1393 * always be greater than tail. 1394 */ 1395 count = head - tail; 1396 1397 tty_insert_flip_string(tport, pdc->buf + pdc->ofs, 1398 count); 1399 1400 dma_sync_single_for_device(port->dev, pdc->dma_addr, 1401 pdc->dma_size, DMA_FROM_DEVICE); 1402 1403 port->icount.rx += count; 1404 pdc->ofs = head; 1405 } 1406 1407 /* 1408 * If the current buffer is full, we need to check if 1409 * the next one contains any additional data. 1410 */ 1411 if (head >= pdc->dma_size) { 1412 pdc->ofs = 0; 1413 UART_PUT_RNPR(port, pdc->dma_addr); 1414 UART_PUT_RNCR(port, pdc->dma_size); 1415 1416 rx_idx = !rx_idx; 1417 atmel_port->pdc_rx_idx = rx_idx; 1418 } 1419 } while (head >= pdc->dma_size); 1420 1421 /* 1422 * Drop the lock here since it might end up calling 1423 * uart_start(), which takes the lock. 1424 */ 1425 spin_unlock(&port->lock); 1426 tty_flip_buffer_push(tport); 1427 spin_lock(&port->lock); 1428 1429 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1430 } 1431 1432 static int atmel_prepare_rx_pdc(struct uart_port *port) 1433 { 1434 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1435 int i; 1436 1437 for (i = 0; i < 2; i++) { 1438 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1439 1440 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); 1441 if (pdc->buf == NULL) { 1442 if (i != 0) { 1443 dma_unmap_single(port->dev, 1444 atmel_port->pdc_rx[0].dma_addr, 1445 PDC_BUFFER_SIZE, 1446 DMA_FROM_DEVICE); 1447 kfree(atmel_port->pdc_rx[0].buf); 1448 } 1449 atmel_port->use_pdc_rx = 0; 1450 return -ENOMEM; 1451 } 1452 pdc->dma_addr = dma_map_single(port->dev, 1453 pdc->buf, 1454 PDC_BUFFER_SIZE, 1455 DMA_FROM_DEVICE); 1456 pdc->dma_size = PDC_BUFFER_SIZE; 1457 pdc->ofs = 0; 1458 } 1459 1460 atmel_port->pdc_rx_idx = 0; 1461 1462 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); 1463 UART_PUT_RCR(port, PDC_BUFFER_SIZE); 1464 1465 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); 1466 UART_PUT_RNCR(port, PDC_BUFFER_SIZE); 1467 1468 return 0; 1469 } 1470 1471 /* 1472 * tasklet handling tty stuff outside the interrupt handler. 1473 */ 1474 static void atmel_tasklet_func(unsigned long data) 1475 { 1476 struct uart_port *port = (struct uart_port *)data; 1477 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1478 unsigned int status; 1479 unsigned int status_change; 1480 1481 /* The interrupt handler does not take the lock */ 1482 spin_lock(&port->lock); 1483 1484 atmel_port->schedule_tx(port); 1485 1486 status = atmel_port->irq_status; 1487 status_change = status ^ atmel_port->irq_status_prev; 1488 1489 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR 1490 | ATMEL_US_DCD | ATMEL_US_CTS)) { 1491 /* TODO: All reads to CSR will clear these interrupts! */ 1492 if (status_change & ATMEL_US_RI) 1493 port->icount.rng++; 1494 if (status_change & ATMEL_US_DSR) 1495 port->icount.dsr++; 1496 if (status_change & ATMEL_US_DCD) 1497 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); 1498 if (status_change & ATMEL_US_CTS) 1499 uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); 1500 1501 wake_up_interruptible(&port->state->port.delta_msr_wait); 1502 1503 atmel_port->irq_status_prev = status; 1504 } 1505 1506 atmel_port->schedule_rx(port); 1507 1508 spin_unlock(&port->lock); 1509 } 1510 1511 static int atmel_init_property(struct atmel_uart_port *atmel_port, 1512 struct platform_device *pdev) 1513 { 1514 struct device_node *np = pdev->dev.of_node; 1515 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1516 1517 if (np) { 1518 /* DMA/PDC usage specification */ 1519 if (of_get_property(np, "atmel,use-dma-rx", NULL)) { 1520 if (of_get_property(np, "dmas", NULL)) { 1521 atmel_port->use_dma_rx = true; 1522 atmel_port->use_pdc_rx = false; 1523 } else { 1524 atmel_port->use_dma_rx = false; 1525 atmel_port->use_pdc_rx = true; 1526 } 1527 } else { 1528 atmel_port->use_dma_rx = false; 1529 atmel_port->use_pdc_rx = false; 1530 } 1531 1532 if (of_get_property(np, "atmel,use-dma-tx", NULL)) { 1533 if (of_get_property(np, "dmas", NULL)) { 1534 atmel_port->use_dma_tx = true; 1535 atmel_port->use_pdc_tx = false; 1536 } else { 1537 atmel_port->use_dma_tx = false; 1538 atmel_port->use_pdc_tx = true; 1539 } 1540 } else { 1541 atmel_port->use_dma_tx = false; 1542 atmel_port->use_pdc_tx = false; 1543 } 1544 1545 } else { 1546 atmel_port->use_pdc_rx = pdata->use_dma_rx; 1547 atmel_port->use_pdc_tx = pdata->use_dma_tx; 1548 atmel_port->use_dma_rx = false; 1549 atmel_port->use_dma_tx = false; 1550 } 1551 1552 return 0; 1553 } 1554 1555 static void atmel_init_rs485(struct atmel_uart_port *atmel_port, 1556 struct platform_device *pdev) 1557 { 1558 struct device_node *np = pdev->dev.of_node; 1559 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1560 1561 if (np) { 1562 u32 rs485_delay[2]; 1563 /* rs485 properties */ 1564 if (of_property_read_u32_array(np, "rs485-rts-delay", 1565 rs485_delay, 2) == 0) { 1566 struct serial_rs485 *rs485conf = &atmel_port->rs485; 1567 1568 rs485conf->delay_rts_before_send = rs485_delay[0]; 1569 rs485conf->delay_rts_after_send = rs485_delay[1]; 1570 rs485conf->flags = 0; 1571 1572 if (of_get_property(np, "rs485-rx-during-tx", NULL)) 1573 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1574 1575 if (of_get_property(np, "linux,rs485-enabled-at-boot-time", 1576 NULL)) 1577 rs485conf->flags |= SER_RS485_ENABLED; 1578 } 1579 } else { 1580 atmel_port->rs485 = pdata->rs485; 1581 } 1582 1583 } 1584 1585 static void atmel_set_ops(struct uart_port *port) 1586 { 1587 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1588 1589 if (atmel_use_dma_rx(port)) { 1590 atmel_port->prepare_rx = &atmel_prepare_rx_dma; 1591 atmel_port->schedule_rx = &atmel_rx_from_dma; 1592 atmel_port->release_rx = &atmel_release_rx_dma; 1593 } else if (atmel_use_pdc_rx(port)) { 1594 atmel_port->prepare_rx = &atmel_prepare_rx_pdc; 1595 atmel_port->schedule_rx = &atmel_rx_from_pdc; 1596 atmel_port->release_rx = &atmel_release_rx_pdc; 1597 } else { 1598 atmel_port->prepare_rx = NULL; 1599 atmel_port->schedule_rx = &atmel_rx_from_ring; 1600 atmel_port->release_rx = NULL; 1601 } 1602 1603 if (atmel_use_dma_tx(port)) { 1604 atmel_port->prepare_tx = &atmel_prepare_tx_dma; 1605 atmel_port->schedule_tx = &atmel_tx_dma; 1606 atmel_port->release_tx = &atmel_release_tx_dma; 1607 } else if (atmel_use_pdc_tx(port)) { 1608 atmel_port->prepare_tx = &atmel_prepare_tx_pdc; 1609 atmel_port->schedule_tx = &atmel_tx_pdc; 1610 atmel_port->release_tx = &atmel_release_tx_pdc; 1611 } else { 1612 atmel_port->prepare_tx = NULL; 1613 atmel_port->schedule_tx = &atmel_tx_chars; 1614 atmel_port->release_tx = NULL; 1615 } 1616 } 1617 1618 /* 1619 * Get ip name usart or uart 1620 */ 1621 static void atmel_get_ip_name(struct uart_port *port) 1622 { 1623 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1624 int name = UART_GET_IP_NAME(port); 1625 u32 version; 1626 int usart, uart; 1627 /* usart and uart ascii */ 1628 usart = 0x55534152; 1629 uart = 0x44424755; 1630 1631 atmel_port->is_usart = false; 1632 1633 if (name == usart) { 1634 dev_dbg(port->dev, "This is usart\n"); 1635 atmel_port->is_usart = true; 1636 } else if (name == uart) { 1637 dev_dbg(port->dev, "This is uart\n"); 1638 atmel_port->is_usart = false; 1639 } else { 1640 /* fallback for older SoCs: use version field */ 1641 version = UART_GET_IP_VERSION(port); 1642 switch (version) { 1643 case 0x302: 1644 case 0x10213: 1645 dev_dbg(port->dev, "This version is usart\n"); 1646 atmel_port->is_usart = true; 1647 break; 1648 case 0x203: 1649 case 0x10202: 1650 dev_dbg(port->dev, "This version is uart\n"); 1651 atmel_port->is_usart = false; 1652 break; 1653 default: 1654 dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); 1655 } 1656 } 1657 } 1658 1659 static void atmel_free_gpio_irq(struct uart_port *port) 1660 { 1661 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1662 enum mctrl_gpio_idx i; 1663 1664 for (i = 0; i < UART_GPIO_MAX; i++) 1665 if (atmel_port->gpio_irq[i] >= 0) 1666 free_irq(atmel_port->gpio_irq[i], port); 1667 } 1668 1669 static int atmel_request_gpio_irq(struct uart_port *port) 1670 { 1671 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1672 int *irq = atmel_port->gpio_irq; 1673 enum mctrl_gpio_idx i; 1674 int err = 0; 1675 1676 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) { 1677 if (irq[i] < 0) 1678 continue; 1679 1680 irq_set_status_flags(irq[i], IRQ_NOAUTOEN); 1681 err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH, 1682 "atmel_serial", port); 1683 if (err) 1684 dev_err(port->dev, "atmel_startup - Can't get %d irq\n", 1685 irq[i]); 1686 } 1687 1688 /* 1689 * If something went wrong, rollback. 1690 */ 1691 while (err && (--i >= 0)) 1692 if (irq[i] >= 0) 1693 free_irq(irq[i], port); 1694 1695 return err; 1696 } 1697 1698 /* 1699 * Perform initialization and enable port for reception 1700 */ 1701 static int atmel_startup(struct uart_port *port) 1702 { 1703 struct platform_device *pdev = to_platform_device(port->dev); 1704 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1705 struct tty_struct *tty = port->state->port.tty; 1706 int retval; 1707 1708 /* 1709 * Ensure that no interrupts are enabled otherwise when 1710 * request_irq() is called we could get stuck trying to 1711 * handle an unexpected interrupt 1712 */ 1713 UART_PUT_IDR(port, -1); 1714 atmel_port->ms_irq_enabled = false; 1715 1716 /* 1717 * Allocate the IRQ 1718 */ 1719 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, 1720 tty ? tty->name : "atmel_serial", port); 1721 if (retval) { 1722 dev_err(port->dev, "atmel_startup - Can't get irq\n"); 1723 return retval; 1724 } 1725 1726 /* 1727 * Get the GPIO lines IRQ 1728 */ 1729 retval = atmel_request_gpio_irq(port); 1730 if (retval) 1731 goto free_irq; 1732 1733 /* 1734 * Initialize DMA (if necessary) 1735 */ 1736 atmel_init_property(atmel_port, pdev); 1737 1738 if (atmel_port->prepare_rx) { 1739 retval = atmel_port->prepare_rx(port); 1740 if (retval < 0) 1741 atmel_set_ops(port); 1742 } 1743 1744 if (atmel_port->prepare_tx) { 1745 retval = atmel_port->prepare_tx(port); 1746 if (retval < 0) 1747 atmel_set_ops(port); 1748 } 1749 1750 /* Save current CSR for comparison in atmel_tasklet_func() */ 1751 atmel_port->irq_status_prev = atmel_get_lines_status(port); 1752 atmel_port->irq_status = atmel_port->irq_status_prev; 1753 1754 /* 1755 * Finally, enable the serial port 1756 */ 1757 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1758 /* enable xmit & rcvr */ 1759 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 1760 1761 setup_timer(&atmel_port->uart_timer, 1762 atmel_uart_timer_callback, 1763 (unsigned long)port); 1764 1765 if (atmel_use_pdc_rx(port)) { 1766 /* set UART timeout */ 1767 if (!atmel_port->is_usart) { 1768 mod_timer(&atmel_port->uart_timer, 1769 jiffies + uart_poll_timeout(port)); 1770 /* set USART timeout */ 1771 } else { 1772 UART_PUT_RTOR(port, PDC_RX_TIMEOUT); 1773 UART_PUT_CR(port, ATMEL_US_STTTO); 1774 1775 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1776 } 1777 /* enable PDC controller */ 1778 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); 1779 } else if (atmel_use_dma_rx(port)) { 1780 /* set UART timeout */ 1781 if (!atmel_port->is_usart) { 1782 mod_timer(&atmel_port->uart_timer, 1783 jiffies + uart_poll_timeout(port)); 1784 /* set USART timeout */ 1785 } else { 1786 UART_PUT_RTOR(port, PDC_RX_TIMEOUT); 1787 UART_PUT_CR(port, ATMEL_US_STTTO); 1788 1789 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 1790 } 1791 } else { 1792 /* enable receive only */ 1793 UART_PUT_IER(port, ATMEL_US_RXRDY); 1794 } 1795 1796 return 0; 1797 1798 free_irq: 1799 free_irq(port->irq, port); 1800 1801 return retval; 1802 } 1803 1804 /* 1805 * Disable the port 1806 */ 1807 static void atmel_shutdown(struct uart_port *port) 1808 { 1809 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1810 1811 /* 1812 * Prevent any tasklets being scheduled during 1813 * cleanup 1814 */ 1815 del_timer_sync(&atmel_port->uart_timer); 1816 1817 /* 1818 * Clear out any scheduled tasklets before 1819 * we destroy the buffers 1820 */ 1821 tasklet_kill(&atmel_port->tasklet); 1822 1823 /* 1824 * Ensure everything is stopped and 1825 * disable all interrupts, port and break condition. 1826 */ 1827 atmel_stop_rx(port); 1828 atmel_stop_tx(port); 1829 1830 UART_PUT_CR(port, ATMEL_US_RSTSTA); 1831 UART_PUT_IDR(port, -1); 1832 1833 1834 /* 1835 * Shut-down the DMA. 1836 */ 1837 if (atmel_port->release_rx) 1838 atmel_port->release_rx(port); 1839 if (atmel_port->release_tx) 1840 atmel_port->release_tx(port); 1841 1842 /* 1843 * Reset ring buffer pointers 1844 */ 1845 atmel_port->rx_ring.head = 0; 1846 atmel_port->rx_ring.tail = 0; 1847 1848 /* 1849 * Free the interrupts 1850 */ 1851 free_irq(port->irq, port); 1852 atmel_free_gpio_irq(port); 1853 1854 atmel_port->ms_irq_enabled = false; 1855 } 1856 1857 /* 1858 * Flush any TX data submitted for DMA. Called when the TX circular 1859 * buffer is reset. 1860 */ 1861 static void atmel_flush_buffer(struct uart_port *port) 1862 { 1863 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1864 1865 if (atmel_use_pdc_tx(port)) { 1866 UART_PUT_TCR(port, 0); 1867 atmel_port->pdc_tx.ofs = 0; 1868 } 1869 } 1870 1871 /* 1872 * Power / Clock management. 1873 */ 1874 static void atmel_serial_pm(struct uart_port *port, unsigned int state, 1875 unsigned int oldstate) 1876 { 1877 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1878 1879 switch (state) { 1880 case 0: 1881 /* 1882 * Enable the peripheral clock for this serial port. 1883 * This is called on uart_open() or a resume event. 1884 */ 1885 clk_prepare_enable(atmel_port->clk); 1886 1887 /* re-enable interrupts if we disabled some on suspend */ 1888 UART_PUT_IER(port, atmel_port->backup_imr); 1889 break; 1890 case 3: 1891 /* Back up the interrupt mask and disable all interrupts */ 1892 atmel_port->backup_imr = UART_GET_IMR(port); 1893 UART_PUT_IDR(port, -1); 1894 1895 /* 1896 * Disable the peripheral clock for this serial port. 1897 * This is called on uart_close() or a suspend event. 1898 */ 1899 clk_disable_unprepare(atmel_port->clk); 1900 break; 1901 default: 1902 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); 1903 } 1904 } 1905 1906 /* 1907 * Change the port parameters 1908 */ 1909 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, 1910 struct ktermios *old) 1911 { 1912 unsigned long flags; 1913 unsigned int mode, imr, quot, baud; 1914 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1915 1916 /* Get current mode register */ 1917 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL 1918 | ATMEL_US_NBSTOP | ATMEL_US_PAR 1919 | ATMEL_US_USMODE); 1920 1921 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1922 quot = uart_get_divisor(port, baud); 1923 1924 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ 1925 quot /= 8; 1926 mode |= ATMEL_US_USCLKS_MCK_DIV8; 1927 } 1928 1929 /* byte size */ 1930 switch (termios->c_cflag & CSIZE) { 1931 case CS5: 1932 mode |= ATMEL_US_CHRL_5; 1933 break; 1934 case CS6: 1935 mode |= ATMEL_US_CHRL_6; 1936 break; 1937 case CS7: 1938 mode |= ATMEL_US_CHRL_7; 1939 break; 1940 default: 1941 mode |= ATMEL_US_CHRL_8; 1942 break; 1943 } 1944 1945 /* stop bits */ 1946 if (termios->c_cflag & CSTOPB) 1947 mode |= ATMEL_US_NBSTOP_2; 1948 1949 /* parity */ 1950 if (termios->c_cflag & PARENB) { 1951 /* Mark or Space parity */ 1952 if (termios->c_cflag & CMSPAR) { 1953 if (termios->c_cflag & PARODD) 1954 mode |= ATMEL_US_PAR_MARK; 1955 else 1956 mode |= ATMEL_US_PAR_SPACE; 1957 } else if (termios->c_cflag & PARODD) 1958 mode |= ATMEL_US_PAR_ODD; 1959 else 1960 mode |= ATMEL_US_PAR_EVEN; 1961 } else 1962 mode |= ATMEL_US_PAR_NONE; 1963 1964 /* hardware handshake (RTS/CTS) */ 1965 if (termios->c_cflag & CRTSCTS) 1966 mode |= ATMEL_US_USMODE_HWHS; 1967 else 1968 mode |= ATMEL_US_USMODE_NORMAL; 1969 1970 spin_lock_irqsave(&port->lock, flags); 1971 1972 port->read_status_mask = ATMEL_US_OVRE; 1973 if (termios->c_iflag & INPCK) 1974 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 1975 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1976 port->read_status_mask |= ATMEL_US_RXBRK; 1977 1978 if (atmel_use_pdc_rx(port)) 1979 /* need to enable error interrupts */ 1980 UART_PUT_IER(port, port->read_status_mask); 1981 1982 /* 1983 * Characters to ignore 1984 */ 1985 port->ignore_status_mask = 0; 1986 if (termios->c_iflag & IGNPAR) 1987 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 1988 if (termios->c_iflag & IGNBRK) { 1989 port->ignore_status_mask |= ATMEL_US_RXBRK; 1990 /* 1991 * If we're ignoring parity and break indicators, 1992 * ignore overruns too (for real raw support). 1993 */ 1994 if (termios->c_iflag & IGNPAR) 1995 port->ignore_status_mask |= ATMEL_US_OVRE; 1996 } 1997 /* TODO: Ignore all characters if CREAD is set.*/ 1998 1999 /* update the per-port timeout */ 2000 uart_update_timeout(port, termios->c_cflag, baud); 2001 2002 /* 2003 * save/disable interrupts. The tty layer will ensure that the 2004 * transmitter is empty if requested by the caller, so there's 2005 * no need to wait for it here. 2006 */ 2007 imr = UART_GET_IMR(port); 2008 UART_PUT_IDR(port, -1); 2009 2010 /* disable receiver and transmitter */ 2011 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); 2012 2013 /* Resetting serial mode to RS232 (0x0) */ 2014 mode &= ~ATMEL_US_USMODE; 2015 2016 if (atmel_port->rs485.flags & SER_RS485_ENABLED) { 2017 if ((atmel_port->rs485.delay_rts_after_send) > 0) 2018 UART_PUT_TTGR(port, 2019 atmel_port->rs485.delay_rts_after_send); 2020 mode |= ATMEL_US_USMODE_RS485; 2021 } 2022 2023 /* set the parity, stop bits and data size */ 2024 UART_PUT_MR(port, mode); 2025 2026 /* set the baud rate */ 2027 UART_PUT_BRGR(port, quot); 2028 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2029 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 2030 2031 /* restore interrupts */ 2032 UART_PUT_IER(port, imr); 2033 2034 /* CTS flow-control and modem-status interrupts */ 2035 if (UART_ENABLE_MS(port, termios->c_cflag)) 2036 atmel_enable_ms(port); 2037 else 2038 atmel_disable_ms(port); 2039 2040 spin_unlock_irqrestore(&port->lock, flags); 2041 } 2042 2043 static void atmel_set_ldisc(struct uart_port *port, int new) 2044 { 2045 if (new == N_PPS) { 2046 port->flags |= UPF_HARDPPS_CD; 2047 atmel_enable_ms(port); 2048 } else { 2049 port->flags &= ~UPF_HARDPPS_CD; 2050 } 2051 } 2052 2053 /* 2054 * Return string describing the specified port 2055 */ 2056 static const char *atmel_type(struct uart_port *port) 2057 { 2058 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; 2059 } 2060 2061 /* 2062 * Release the memory region(s) being used by 'port'. 2063 */ 2064 static void atmel_release_port(struct uart_port *port) 2065 { 2066 struct platform_device *pdev = to_platform_device(port->dev); 2067 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 2068 2069 release_mem_region(port->mapbase, size); 2070 2071 if (port->flags & UPF_IOREMAP) { 2072 iounmap(port->membase); 2073 port->membase = NULL; 2074 } 2075 } 2076 2077 /* 2078 * Request the memory region(s) being used by 'port'. 2079 */ 2080 static int atmel_request_port(struct uart_port *port) 2081 { 2082 struct platform_device *pdev = to_platform_device(port->dev); 2083 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 2084 2085 if (!request_mem_region(port->mapbase, size, "atmel_serial")) 2086 return -EBUSY; 2087 2088 if (port->flags & UPF_IOREMAP) { 2089 port->membase = ioremap(port->mapbase, size); 2090 if (port->membase == NULL) { 2091 release_mem_region(port->mapbase, size); 2092 return -ENOMEM; 2093 } 2094 } 2095 2096 return 0; 2097 } 2098 2099 /* 2100 * Configure/autoconfigure the port. 2101 */ 2102 static void atmel_config_port(struct uart_port *port, int flags) 2103 { 2104 if (flags & UART_CONFIG_TYPE) { 2105 port->type = PORT_ATMEL; 2106 atmel_request_port(port); 2107 } 2108 } 2109 2110 /* 2111 * Verify the new serial_struct (for TIOCSSERIAL). 2112 */ 2113 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) 2114 { 2115 int ret = 0; 2116 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) 2117 ret = -EINVAL; 2118 if (port->irq != ser->irq) 2119 ret = -EINVAL; 2120 if (ser->io_type != SERIAL_IO_MEM) 2121 ret = -EINVAL; 2122 if (port->uartclk / 16 != ser->baud_base) 2123 ret = -EINVAL; 2124 if ((void *)port->mapbase != ser->iomem_base) 2125 ret = -EINVAL; 2126 if (port->iobase != ser->port) 2127 ret = -EINVAL; 2128 if (ser->hub6 != 0) 2129 ret = -EINVAL; 2130 return ret; 2131 } 2132 2133 #ifdef CONFIG_CONSOLE_POLL 2134 static int atmel_poll_get_char(struct uart_port *port) 2135 { 2136 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY)) 2137 cpu_relax(); 2138 2139 return UART_GET_CHAR(port); 2140 } 2141 2142 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) 2143 { 2144 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) 2145 cpu_relax(); 2146 2147 UART_PUT_CHAR(port, ch); 2148 } 2149 #endif 2150 2151 static int 2152 atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg) 2153 { 2154 struct serial_rs485 rs485conf; 2155 2156 switch (cmd) { 2157 case TIOCSRS485: 2158 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg, 2159 sizeof(rs485conf))) 2160 return -EFAULT; 2161 2162 atmel_config_rs485(port, &rs485conf); 2163 break; 2164 2165 case TIOCGRS485: 2166 if (copy_to_user((struct serial_rs485 *) arg, 2167 &(to_atmel_uart_port(port)->rs485), 2168 sizeof(rs485conf))) 2169 return -EFAULT; 2170 break; 2171 2172 default: 2173 return -ENOIOCTLCMD; 2174 } 2175 return 0; 2176 } 2177 2178 2179 2180 static struct uart_ops atmel_pops = { 2181 .tx_empty = atmel_tx_empty, 2182 .set_mctrl = atmel_set_mctrl, 2183 .get_mctrl = atmel_get_mctrl, 2184 .stop_tx = atmel_stop_tx, 2185 .start_tx = atmel_start_tx, 2186 .stop_rx = atmel_stop_rx, 2187 .enable_ms = atmel_enable_ms, 2188 .break_ctl = atmel_break_ctl, 2189 .startup = atmel_startup, 2190 .shutdown = atmel_shutdown, 2191 .flush_buffer = atmel_flush_buffer, 2192 .set_termios = atmel_set_termios, 2193 .set_ldisc = atmel_set_ldisc, 2194 .type = atmel_type, 2195 .release_port = atmel_release_port, 2196 .request_port = atmel_request_port, 2197 .config_port = atmel_config_port, 2198 .verify_port = atmel_verify_port, 2199 .pm = atmel_serial_pm, 2200 .ioctl = atmel_ioctl, 2201 #ifdef CONFIG_CONSOLE_POLL 2202 .poll_get_char = atmel_poll_get_char, 2203 .poll_put_char = atmel_poll_put_char, 2204 #endif 2205 }; 2206 2207 /* 2208 * Configure the port from the platform device resource info. 2209 */ 2210 static int atmel_init_port(struct atmel_uart_port *atmel_port, 2211 struct platform_device *pdev) 2212 { 2213 int ret; 2214 struct uart_port *port = &atmel_port->uart; 2215 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2216 2217 if (!atmel_init_property(atmel_port, pdev)) 2218 atmel_set_ops(port); 2219 2220 atmel_init_rs485(atmel_port, pdev); 2221 2222 port->iotype = UPIO_MEM; 2223 port->flags = UPF_BOOT_AUTOCONF; 2224 port->ops = &atmel_pops; 2225 port->fifosize = 1; 2226 port->dev = &pdev->dev; 2227 port->mapbase = pdev->resource[0].start; 2228 port->irq = pdev->resource[1].start; 2229 2230 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, 2231 (unsigned long)port); 2232 2233 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); 2234 2235 if (pdata && pdata->regs) { 2236 /* Already mapped by setup code */ 2237 port->membase = pdata->regs; 2238 } else { 2239 port->flags |= UPF_IOREMAP; 2240 port->membase = NULL; 2241 } 2242 2243 /* for console, the clock could already be configured */ 2244 if (!atmel_port->clk) { 2245 atmel_port->clk = clk_get(&pdev->dev, "usart"); 2246 if (IS_ERR(atmel_port->clk)) { 2247 ret = PTR_ERR(atmel_port->clk); 2248 atmel_port->clk = NULL; 2249 return ret; 2250 } 2251 ret = clk_prepare_enable(atmel_port->clk); 2252 if (ret) { 2253 clk_put(atmel_port->clk); 2254 atmel_port->clk = NULL; 2255 return ret; 2256 } 2257 port->uartclk = clk_get_rate(atmel_port->clk); 2258 clk_disable_unprepare(atmel_port->clk); 2259 /* only enable clock when USART is in use */ 2260 } 2261 2262 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ 2263 if (atmel_port->rs485.flags & SER_RS485_ENABLED) 2264 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 2265 else if (atmel_use_pdc_tx(port)) { 2266 port->fifosize = PDC_BUFFER_SIZE; 2267 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; 2268 } else { 2269 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 2270 } 2271 2272 return 0; 2273 } 2274 2275 struct platform_device *atmel_default_console_device; /* the serial console device */ 2276 2277 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2278 static void atmel_console_putchar(struct uart_port *port, int ch) 2279 { 2280 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) 2281 cpu_relax(); 2282 UART_PUT_CHAR(port, ch); 2283 } 2284 2285 /* 2286 * Interrupts are disabled on entering 2287 */ 2288 static void atmel_console_write(struct console *co, const char *s, u_int count) 2289 { 2290 struct uart_port *port = &atmel_ports[co->index].uart; 2291 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2292 unsigned int status, imr; 2293 unsigned int pdc_tx; 2294 2295 /* 2296 * First, save IMR and then disable interrupts 2297 */ 2298 imr = UART_GET_IMR(port); 2299 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask); 2300 2301 /* Store PDC transmit status and disable it */ 2302 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN; 2303 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 2304 2305 uart_console_write(port, s, count, atmel_console_putchar); 2306 2307 /* 2308 * Finally, wait for transmitter to become empty 2309 * and restore IMR 2310 */ 2311 do { 2312 status = UART_GET_CSR(port); 2313 } while (!(status & ATMEL_US_TXRDY)); 2314 2315 /* Restore PDC transmit status */ 2316 if (pdc_tx) 2317 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 2318 2319 /* set interrupts back the way they were */ 2320 UART_PUT_IER(port, imr); 2321 } 2322 2323 /* 2324 * If the port was already initialised (eg, by a boot loader), 2325 * try to determine the current setup. 2326 */ 2327 static void __init atmel_console_get_options(struct uart_port *port, int *baud, 2328 int *parity, int *bits) 2329 { 2330 unsigned int mr, quot; 2331 2332 /* 2333 * If the baud rate generator isn't running, the port wasn't 2334 * initialized by the boot loader. 2335 */ 2336 quot = UART_GET_BRGR(port) & ATMEL_US_CD; 2337 if (!quot) 2338 return; 2339 2340 mr = UART_GET_MR(port) & ATMEL_US_CHRL; 2341 if (mr == ATMEL_US_CHRL_8) 2342 *bits = 8; 2343 else 2344 *bits = 7; 2345 2346 mr = UART_GET_MR(port) & ATMEL_US_PAR; 2347 if (mr == ATMEL_US_PAR_EVEN) 2348 *parity = 'e'; 2349 else if (mr == ATMEL_US_PAR_ODD) 2350 *parity = 'o'; 2351 2352 /* 2353 * The serial core only rounds down when matching this to a 2354 * supported baud rate. Make sure we don't end up slightly 2355 * lower than one of those, as it would make us fall through 2356 * to a much lower baud rate than we really want. 2357 */ 2358 *baud = port->uartclk / (16 * (quot - 1)); 2359 } 2360 2361 static int __init atmel_console_setup(struct console *co, char *options) 2362 { 2363 int ret; 2364 struct uart_port *port = &atmel_ports[co->index].uart; 2365 int baud = 115200; 2366 int bits = 8; 2367 int parity = 'n'; 2368 int flow = 'n'; 2369 2370 if (port->membase == NULL) { 2371 /* Port not initialized yet - delay setup */ 2372 return -ENODEV; 2373 } 2374 2375 ret = clk_prepare_enable(atmel_ports[co->index].clk); 2376 if (ret) 2377 return ret; 2378 2379 UART_PUT_IDR(port, -1); 2380 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2381 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 2382 2383 if (options) 2384 uart_parse_options(options, &baud, &parity, &bits, &flow); 2385 else 2386 atmel_console_get_options(port, &baud, &parity, &bits); 2387 2388 return uart_set_options(port, co, baud, parity, bits, flow); 2389 } 2390 2391 static struct uart_driver atmel_uart; 2392 2393 static struct console atmel_console = { 2394 .name = ATMEL_DEVICENAME, 2395 .write = atmel_console_write, 2396 .device = uart_console_device, 2397 .setup = atmel_console_setup, 2398 .flags = CON_PRINTBUFFER, 2399 .index = -1, 2400 .data = &atmel_uart, 2401 }; 2402 2403 #define ATMEL_CONSOLE_DEVICE (&atmel_console) 2404 2405 /* 2406 * Early console initialization (before VM subsystem initialized). 2407 */ 2408 static int __init atmel_console_init(void) 2409 { 2410 int ret; 2411 if (atmel_default_console_device) { 2412 struct atmel_uart_data *pdata = 2413 dev_get_platdata(&atmel_default_console_device->dev); 2414 int id = pdata->num; 2415 struct atmel_uart_port *port = &atmel_ports[id]; 2416 2417 port->backup_imr = 0; 2418 port->uart.line = id; 2419 2420 add_preferred_console(ATMEL_DEVICENAME, id, NULL); 2421 ret = atmel_init_port(port, atmel_default_console_device); 2422 if (ret) 2423 return ret; 2424 register_console(&atmel_console); 2425 } 2426 2427 return 0; 2428 } 2429 2430 console_initcall(atmel_console_init); 2431 2432 /* 2433 * Late console initialization. 2434 */ 2435 static int __init atmel_late_console_init(void) 2436 { 2437 if (atmel_default_console_device 2438 && !(atmel_console.flags & CON_ENABLED)) 2439 register_console(&atmel_console); 2440 2441 return 0; 2442 } 2443 2444 core_initcall(atmel_late_console_init); 2445 2446 static inline bool atmel_is_console_port(struct uart_port *port) 2447 { 2448 return port->cons && port->cons->index == port->line; 2449 } 2450 2451 #else 2452 #define ATMEL_CONSOLE_DEVICE NULL 2453 2454 static inline bool atmel_is_console_port(struct uart_port *port) 2455 { 2456 return false; 2457 } 2458 #endif 2459 2460 static struct uart_driver atmel_uart = { 2461 .owner = THIS_MODULE, 2462 .driver_name = "atmel_serial", 2463 .dev_name = ATMEL_DEVICENAME, 2464 .major = SERIAL_ATMEL_MAJOR, 2465 .minor = MINOR_START, 2466 .nr = ATMEL_MAX_UART, 2467 .cons = ATMEL_CONSOLE_DEVICE, 2468 }; 2469 2470 #ifdef CONFIG_PM 2471 static bool atmel_serial_clk_will_stop(void) 2472 { 2473 #ifdef CONFIG_ARCH_AT91 2474 return at91_suspend_entering_slow_clock(); 2475 #else 2476 return false; 2477 #endif 2478 } 2479 2480 static int atmel_serial_suspend(struct platform_device *pdev, 2481 pm_message_t state) 2482 { 2483 struct uart_port *port = platform_get_drvdata(pdev); 2484 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2485 2486 if (atmel_is_console_port(port) && console_suspend_enabled) { 2487 /* Drain the TX shifter */ 2488 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) 2489 cpu_relax(); 2490 } 2491 2492 /* we can not wake up if we're running on slow clock */ 2493 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); 2494 if (atmel_serial_clk_will_stop()) 2495 device_set_wakeup_enable(&pdev->dev, 0); 2496 2497 uart_suspend_port(&atmel_uart, port); 2498 2499 return 0; 2500 } 2501 2502 static int atmel_serial_resume(struct platform_device *pdev) 2503 { 2504 struct uart_port *port = platform_get_drvdata(pdev); 2505 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2506 2507 uart_resume_port(&atmel_uart, port); 2508 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); 2509 2510 return 0; 2511 } 2512 #else 2513 #define atmel_serial_suspend NULL 2514 #define atmel_serial_resume NULL 2515 #endif 2516 2517 static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev) 2518 { 2519 enum mctrl_gpio_idx i; 2520 struct gpio_desc *gpiod; 2521 2522 p->gpios = mctrl_gpio_init(dev, 0); 2523 if (IS_ERR_OR_NULL(p->gpios)) 2524 return -1; 2525 2526 for (i = 0; i < UART_GPIO_MAX; i++) { 2527 gpiod = mctrl_gpio_to_gpiod(p->gpios, i); 2528 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN)) 2529 p->gpio_irq[i] = gpiod_to_irq(gpiod); 2530 else 2531 p->gpio_irq[i] = -EINVAL; 2532 } 2533 2534 return 0; 2535 } 2536 2537 static int atmel_serial_probe(struct platform_device *pdev) 2538 { 2539 struct atmel_uart_port *port; 2540 struct device_node *np = pdev->dev.of_node; 2541 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2542 void *data; 2543 int ret = -ENODEV; 2544 2545 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); 2546 2547 if (np) 2548 ret = of_alias_get_id(np, "serial"); 2549 else 2550 if (pdata) 2551 ret = pdata->num; 2552 2553 if (ret < 0) 2554 /* port id not found in platform data nor device-tree aliases: 2555 * auto-enumerate it */ 2556 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); 2557 2558 if (ret >= ATMEL_MAX_UART) { 2559 ret = -ENODEV; 2560 goto err; 2561 } 2562 2563 if (test_and_set_bit(ret, atmel_ports_in_use)) { 2564 /* port already in use */ 2565 ret = -EBUSY; 2566 goto err; 2567 } 2568 2569 port = &atmel_ports[ret]; 2570 port->backup_imr = 0; 2571 port->uart.line = ret; 2572 2573 ret = atmel_init_gpios(port, &pdev->dev); 2574 if (ret < 0) 2575 dev_err(&pdev->dev, "%s", 2576 "Failed to initialize GPIOs. The serial port may not work as expected"); 2577 2578 ret = atmel_init_port(port, pdev); 2579 if (ret) 2580 goto err; 2581 2582 if (!atmel_use_pdc_rx(&port->uart)) { 2583 ret = -ENOMEM; 2584 data = kmalloc(sizeof(struct atmel_uart_char) 2585 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); 2586 if (!data) 2587 goto err_alloc_ring; 2588 port->rx_ring.buf = data; 2589 } 2590 2591 ret = uart_add_one_port(&atmel_uart, &port->uart); 2592 if (ret) 2593 goto err_add_port; 2594 2595 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2596 if (atmel_is_console_port(&port->uart) 2597 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { 2598 /* 2599 * The serial core enabled the clock for us, so undo 2600 * the clk_prepare_enable() in atmel_console_setup() 2601 */ 2602 clk_disable_unprepare(port->clk); 2603 } 2604 #endif 2605 2606 device_init_wakeup(&pdev->dev, 1); 2607 platform_set_drvdata(pdev, port); 2608 2609 if (port->rs485.flags & SER_RS485_ENABLED) { 2610 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL); 2611 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN); 2612 } 2613 2614 /* 2615 * Get port name of usart or uart 2616 */ 2617 atmel_get_ip_name(&port->uart); 2618 2619 return 0; 2620 2621 err_add_port: 2622 kfree(port->rx_ring.buf); 2623 port->rx_ring.buf = NULL; 2624 err_alloc_ring: 2625 if (!atmel_is_console_port(&port->uart)) { 2626 clk_put(port->clk); 2627 port->clk = NULL; 2628 } 2629 err: 2630 return ret; 2631 } 2632 2633 static int atmel_serial_remove(struct platform_device *pdev) 2634 { 2635 struct uart_port *port = platform_get_drvdata(pdev); 2636 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2637 int ret = 0; 2638 2639 tasklet_kill(&atmel_port->tasklet); 2640 2641 device_init_wakeup(&pdev->dev, 0); 2642 2643 ret = uart_remove_one_port(&atmel_uart, port); 2644 2645 kfree(atmel_port->rx_ring.buf); 2646 2647 /* "port" is allocated statically, so we shouldn't free it */ 2648 2649 clear_bit(port->line, atmel_ports_in_use); 2650 2651 clk_put(atmel_port->clk); 2652 2653 return ret; 2654 } 2655 2656 static struct platform_driver atmel_serial_driver = { 2657 .probe = atmel_serial_probe, 2658 .remove = atmel_serial_remove, 2659 .suspend = atmel_serial_suspend, 2660 .resume = atmel_serial_resume, 2661 .driver = { 2662 .name = "atmel_usart", 2663 .owner = THIS_MODULE, 2664 .of_match_table = of_match_ptr(atmel_serial_dt_ids), 2665 }, 2666 }; 2667 2668 static int __init atmel_serial_init(void) 2669 { 2670 int ret; 2671 2672 ret = uart_register_driver(&atmel_uart); 2673 if (ret) 2674 return ret; 2675 2676 ret = platform_driver_register(&atmel_serial_driver); 2677 if (ret) 2678 uart_unregister_driver(&atmel_uart); 2679 2680 return ret; 2681 } 2682 2683 static void __exit atmel_serial_exit(void) 2684 { 2685 platform_driver_unregister(&atmel_serial_driver); 2686 uart_unregister_driver(&atmel_uart); 2687 } 2688 2689 module_init(atmel_serial_init); 2690 module_exit(atmel_serial_exit); 2691 2692 MODULE_AUTHOR("Rick Bronson"); 2693 MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); 2694 MODULE_LICENSE("GPL"); 2695 MODULE_ALIAS("platform:atmel_usart"); 2696