1 /* 2 * Driver for Atmel AT91 / AT32 Serial ports 3 * Copyright (C) 2003 Rick Bronson 4 * 5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. 6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 7 * 8 * DMA support added by Chip Coldwell. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 #include <linux/module.h> 26 #include <linux/tty.h> 27 #include <linux/ioport.h> 28 #include <linux/slab.h> 29 #include <linux/init.h> 30 #include <linux/serial.h> 31 #include <linux/clk.h> 32 #include <linux/console.h> 33 #include <linux/sysrq.h> 34 #include <linux/tty_flip.h> 35 #include <linux/platform_device.h> 36 #include <linux/of.h> 37 #include <linux/of_device.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/atmel_pdc.h> 40 #include <linux/atmel_serial.h> 41 #include <linux/uaccess.h> 42 #include <linux/platform_data/atmel.h> 43 #include <linux/timer.h> 44 45 #include <asm/io.h> 46 #include <asm/ioctls.h> 47 48 #ifdef CONFIG_ARM 49 #include <mach/cpu.h> 50 #include <asm/gpio.h> 51 #endif 52 53 #define PDC_BUFFER_SIZE 512 54 /* Revisit: We should calculate this based on the actual port settings */ 55 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ 56 57 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 58 #define SUPPORT_SYSRQ 59 #endif 60 61 #include <linux/serial_core.h> 62 63 static void atmel_start_rx(struct uart_port *port); 64 static void atmel_stop_rx(struct uart_port *port); 65 66 #ifdef CONFIG_SERIAL_ATMEL_TTYAT 67 68 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we 69 * should coexist with the 8250 driver, such as if we have an external 16C550 70 * UART. */ 71 #define SERIAL_ATMEL_MAJOR 204 72 #define MINOR_START 154 73 #define ATMEL_DEVICENAME "ttyAT" 74 75 #else 76 77 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port 78 * name, but it is legally reserved for the 8250 driver. */ 79 #define SERIAL_ATMEL_MAJOR TTY_MAJOR 80 #define MINOR_START 64 81 #define ATMEL_DEVICENAME "ttyS" 82 83 #endif 84 85 #define ATMEL_ISR_PASS_LIMIT 256 86 87 /* UART registers. CR is write-only, hence no GET macro */ 88 #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) 89 #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) 90 #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) 91 #define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) 92 #define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) 93 #define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) 94 #define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) 95 #define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) 96 #define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) 97 #define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) 98 #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) 99 #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) 100 #define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR) 101 #define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME) 102 #define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION) 103 104 /* PDC registers */ 105 #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) 106 #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) 107 108 #define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) 109 #define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) 110 #define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) 111 #define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) 112 #define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) 113 114 #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) 115 #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) 116 #define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR) 117 118 static int (*atmel_open_hook)(struct uart_port *); 119 static void (*atmel_close_hook)(struct uart_port *); 120 121 struct atmel_dma_buffer { 122 unsigned char *buf; 123 dma_addr_t dma_addr; 124 unsigned int dma_size; 125 unsigned int ofs; 126 }; 127 128 struct atmel_uart_char { 129 u16 status; 130 u16 ch; 131 }; 132 133 #define ATMEL_SERIAL_RINGSIZE 1024 134 135 /* 136 * We wrap our port structure around the generic uart_port. 137 */ 138 struct atmel_uart_port { 139 struct uart_port uart; /* uart */ 140 struct clk *clk; /* uart clock */ 141 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ 142 u32 backup_imr; /* IMR saved during suspend */ 143 int break_active; /* break being received */ 144 145 bool use_dma_rx; /* enable DMA receiver */ 146 bool use_pdc_rx; /* enable PDC receiver */ 147 short pdc_rx_idx; /* current PDC RX buffer */ 148 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ 149 150 bool use_dma_tx; /* enable DMA transmitter */ 151 bool use_pdc_tx; /* enable PDC transmitter */ 152 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ 153 154 spinlock_t lock_tx; /* port lock */ 155 spinlock_t lock_rx; /* port lock */ 156 struct dma_chan *chan_tx; 157 struct dma_chan *chan_rx; 158 struct dma_async_tx_descriptor *desc_tx; 159 struct dma_async_tx_descriptor *desc_rx; 160 dma_cookie_t cookie_tx; 161 dma_cookie_t cookie_rx; 162 struct scatterlist sg_tx; 163 struct scatterlist sg_rx; 164 struct tasklet_struct tasklet; 165 unsigned int irq_status; 166 unsigned int irq_status_prev; 167 168 struct circ_buf rx_ring; 169 170 struct serial_rs485 rs485; /* rs485 settings */ 171 unsigned int tx_done_mask; 172 bool is_usart; /* usart or uart */ 173 struct timer_list uart_timer; /* uart timer */ 174 int (*prepare_rx)(struct uart_port *port); 175 int (*prepare_tx)(struct uart_port *port); 176 void (*schedule_rx)(struct uart_port *port); 177 void (*schedule_tx)(struct uart_port *port); 178 void (*release_rx)(struct uart_port *port); 179 void (*release_tx)(struct uart_port *port); 180 }; 181 182 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; 183 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); 184 185 #ifdef SUPPORT_SYSRQ 186 static struct console atmel_console; 187 #endif 188 189 #if defined(CONFIG_OF) 190 static const struct of_device_id atmel_serial_dt_ids[] = { 191 { .compatible = "atmel,at91rm9200-usart" }, 192 { .compatible = "atmel,at91sam9260-usart" }, 193 { /* sentinel */ } 194 }; 195 196 MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids); 197 #endif 198 199 static inline struct atmel_uart_port * 200 to_atmel_uart_port(struct uart_port *uart) 201 { 202 return container_of(uart, struct atmel_uart_port, uart); 203 } 204 205 #ifdef CONFIG_SERIAL_ATMEL_PDC 206 static bool atmel_use_pdc_rx(struct uart_port *port) 207 { 208 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 209 210 return atmel_port->use_pdc_rx; 211 } 212 213 static bool atmel_use_pdc_tx(struct uart_port *port) 214 { 215 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 216 217 return atmel_port->use_pdc_tx; 218 } 219 #else 220 static bool atmel_use_pdc_rx(struct uart_port *port) 221 { 222 return false; 223 } 224 225 static bool atmel_use_pdc_tx(struct uart_port *port) 226 { 227 return false; 228 } 229 #endif 230 231 static bool atmel_use_dma_tx(struct uart_port *port) 232 { 233 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 234 235 return atmel_port->use_dma_tx; 236 } 237 238 static bool atmel_use_dma_rx(struct uart_port *port) 239 { 240 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 241 242 return atmel_port->use_dma_rx; 243 } 244 245 /* Enable or disable the rs485 support */ 246 void atmel_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf) 247 { 248 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 249 unsigned int mode; 250 unsigned long flags; 251 252 spin_lock_irqsave(&port->lock, flags); 253 254 /* Disable interrupts */ 255 UART_PUT_IDR(port, atmel_port->tx_done_mask); 256 257 mode = UART_GET_MR(port); 258 259 /* Resetting serial mode to RS232 (0x0) */ 260 mode &= ~ATMEL_US_USMODE; 261 262 atmel_port->rs485 = *rs485conf; 263 264 if (rs485conf->flags & SER_RS485_ENABLED) { 265 dev_dbg(port->dev, "Setting UART to RS485\n"); 266 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 267 if ((rs485conf->delay_rts_after_send) > 0) 268 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send); 269 mode |= ATMEL_US_USMODE_RS485; 270 } else { 271 dev_dbg(port->dev, "Setting UART to RS232\n"); 272 if (atmel_use_pdc_tx(port)) 273 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 274 ATMEL_US_TXBUFE; 275 else 276 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 277 } 278 UART_PUT_MR(port, mode); 279 280 /* Enable interrupts */ 281 UART_PUT_IER(port, atmel_port->tx_done_mask); 282 283 spin_unlock_irqrestore(&port->lock, flags); 284 285 } 286 287 /* 288 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. 289 */ 290 static u_int atmel_tx_empty(struct uart_port *port) 291 { 292 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; 293 } 294 295 /* 296 * Set state of the modem control output lines 297 */ 298 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) 299 { 300 unsigned int control = 0; 301 unsigned int mode; 302 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 303 304 #ifdef CONFIG_ARCH_AT91RM9200 305 if (cpu_is_at91rm9200()) { 306 /* 307 * AT91RM9200 Errata #39: RTS0 is not internally connected 308 * to PA21. We need to drive the pin manually. 309 */ 310 if (port->mapbase == AT91RM9200_BASE_US0) { 311 if (mctrl & TIOCM_RTS) 312 at91_set_gpio_value(AT91_PIN_PA21, 0); 313 else 314 at91_set_gpio_value(AT91_PIN_PA21, 1); 315 } 316 } 317 #endif 318 319 if (mctrl & TIOCM_RTS) 320 control |= ATMEL_US_RTSEN; 321 else 322 control |= ATMEL_US_RTSDIS; 323 324 if (mctrl & TIOCM_DTR) 325 control |= ATMEL_US_DTREN; 326 else 327 control |= ATMEL_US_DTRDIS; 328 329 UART_PUT_CR(port, control); 330 331 /* Local loopback mode? */ 332 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE; 333 if (mctrl & TIOCM_LOOP) 334 mode |= ATMEL_US_CHMODE_LOC_LOOP; 335 else 336 mode |= ATMEL_US_CHMODE_NORMAL; 337 338 /* Resetting serial mode to RS232 (0x0) */ 339 mode &= ~ATMEL_US_USMODE; 340 341 if (atmel_port->rs485.flags & SER_RS485_ENABLED) { 342 dev_dbg(port->dev, "Setting UART to RS485\n"); 343 if ((atmel_port->rs485.delay_rts_after_send) > 0) 344 UART_PUT_TTGR(port, 345 atmel_port->rs485.delay_rts_after_send); 346 mode |= ATMEL_US_USMODE_RS485; 347 } else { 348 dev_dbg(port->dev, "Setting UART to RS232\n"); 349 } 350 UART_PUT_MR(port, mode); 351 } 352 353 /* 354 * Get state of the modem control input lines 355 */ 356 static u_int atmel_get_mctrl(struct uart_port *port) 357 { 358 unsigned int status, ret = 0; 359 360 status = UART_GET_CSR(port); 361 362 /* 363 * The control signals are active low. 364 */ 365 if (!(status & ATMEL_US_DCD)) 366 ret |= TIOCM_CD; 367 if (!(status & ATMEL_US_CTS)) 368 ret |= TIOCM_CTS; 369 if (!(status & ATMEL_US_DSR)) 370 ret |= TIOCM_DSR; 371 if (!(status & ATMEL_US_RI)) 372 ret |= TIOCM_RI; 373 374 return ret; 375 } 376 377 /* 378 * Stop transmitting. 379 */ 380 static void atmel_stop_tx(struct uart_port *port) 381 { 382 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 383 384 if (atmel_use_pdc_tx(port)) { 385 /* disable PDC transmit */ 386 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 387 } 388 /* Disable interrupts */ 389 UART_PUT_IDR(port, atmel_port->tx_done_mask); 390 391 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && 392 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) 393 atmel_start_rx(port); 394 } 395 396 /* 397 * Start transmitting. 398 */ 399 static void atmel_start_tx(struct uart_port *port) 400 { 401 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 402 403 if (atmel_use_pdc_tx(port)) { 404 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) 405 /* The transmitter is already running. Yes, we 406 really need this.*/ 407 return; 408 409 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && 410 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) 411 atmel_stop_rx(port); 412 413 /* re-enable PDC transmit */ 414 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 415 } 416 /* Enable interrupts */ 417 UART_PUT_IER(port, atmel_port->tx_done_mask); 418 } 419 420 /* 421 * start receiving - port is in process of being opened. 422 */ 423 static void atmel_start_rx(struct uart_port *port) 424 { 425 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */ 426 427 UART_PUT_CR(port, ATMEL_US_RXEN); 428 429 if (atmel_use_pdc_rx(port)) { 430 /* enable PDC controller */ 431 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 432 port->read_status_mask); 433 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); 434 } else { 435 UART_PUT_IER(port, ATMEL_US_RXRDY); 436 } 437 } 438 439 /* 440 * Stop receiving - port is in process of being closed. 441 */ 442 static void atmel_stop_rx(struct uart_port *port) 443 { 444 UART_PUT_CR(port, ATMEL_US_RXDIS); 445 446 if (atmel_use_pdc_rx(port)) { 447 /* disable PDC receive */ 448 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); 449 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 450 port->read_status_mask); 451 } else { 452 UART_PUT_IDR(port, ATMEL_US_RXRDY); 453 } 454 } 455 456 /* 457 * Enable modem status interrupts 458 */ 459 static void atmel_enable_ms(struct uart_port *port) 460 { 461 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC 462 | ATMEL_US_DCDIC | ATMEL_US_CTSIC); 463 } 464 465 /* 466 * Control the transmission of a break signal 467 */ 468 static void atmel_break_ctl(struct uart_port *port, int break_state) 469 { 470 if (break_state != 0) 471 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ 472 else 473 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ 474 } 475 476 /* 477 * Stores the incoming character in the ring buffer 478 */ 479 static void 480 atmel_buffer_rx_char(struct uart_port *port, unsigned int status, 481 unsigned int ch) 482 { 483 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 484 struct circ_buf *ring = &atmel_port->rx_ring; 485 struct atmel_uart_char *c; 486 487 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) 488 /* Buffer overflow, ignore char */ 489 return; 490 491 c = &((struct atmel_uart_char *)ring->buf)[ring->head]; 492 c->status = status; 493 c->ch = ch; 494 495 /* Make sure the character is stored before we update head. */ 496 smp_wmb(); 497 498 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 499 } 500 501 /* 502 * Deal with parity, framing and overrun errors. 503 */ 504 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) 505 { 506 /* clear error */ 507 UART_PUT_CR(port, ATMEL_US_RSTSTA); 508 509 if (status & ATMEL_US_RXBRK) { 510 /* ignore side-effect */ 511 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 512 port->icount.brk++; 513 } 514 if (status & ATMEL_US_PARE) 515 port->icount.parity++; 516 if (status & ATMEL_US_FRAME) 517 port->icount.frame++; 518 if (status & ATMEL_US_OVRE) 519 port->icount.overrun++; 520 } 521 522 /* 523 * Characters received (called from interrupt handler) 524 */ 525 static void atmel_rx_chars(struct uart_port *port) 526 { 527 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 528 unsigned int status, ch; 529 530 status = UART_GET_CSR(port); 531 while (status & ATMEL_US_RXRDY) { 532 ch = UART_GET_CHAR(port); 533 534 /* 535 * note that the error handling code is 536 * out of the main execution path 537 */ 538 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 539 | ATMEL_US_OVRE | ATMEL_US_RXBRK) 540 || atmel_port->break_active)) { 541 542 /* clear error */ 543 UART_PUT_CR(port, ATMEL_US_RSTSTA); 544 545 if (status & ATMEL_US_RXBRK 546 && !atmel_port->break_active) { 547 atmel_port->break_active = 1; 548 UART_PUT_IER(port, ATMEL_US_RXBRK); 549 } else { 550 /* 551 * This is either the end-of-break 552 * condition or we've received at 553 * least one character without RXBRK 554 * being set. In both cases, the next 555 * RXBRK will indicate start-of-break. 556 */ 557 UART_PUT_IDR(port, ATMEL_US_RXBRK); 558 status &= ~ATMEL_US_RXBRK; 559 atmel_port->break_active = 0; 560 } 561 } 562 563 atmel_buffer_rx_char(port, status, ch); 564 status = UART_GET_CSR(port); 565 } 566 567 tasklet_schedule(&atmel_port->tasklet); 568 } 569 570 /* 571 * Transmit characters (called from tasklet with TXRDY interrupt 572 * disabled) 573 */ 574 static void atmel_tx_chars(struct uart_port *port) 575 { 576 struct circ_buf *xmit = &port->state->xmit; 577 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 578 579 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) { 580 UART_PUT_CHAR(port, port->x_char); 581 port->icount.tx++; 582 port->x_char = 0; 583 } 584 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 585 return; 586 587 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) { 588 UART_PUT_CHAR(port, xmit->buf[xmit->tail]); 589 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 590 port->icount.tx++; 591 if (uart_circ_empty(xmit)) 592 break; 593 } 594 595 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 596 uart_write_wakeup(port); 597 598 if (!uart_circ_empty(xmit)) 599 /* Enable interrupts */ 600 UART_PUT_IER(port, atmel_port->tx_done_mask); 601 } 602 603 static void atmel_complete_tx_dma(void *arg) 604 { 605 struct atmel_uart_port *atmel_port = arg; 606 struct uart_port *port = &atmel_port->uart; 607 struct circ_buf *xmit = &port->state->xmit; 608 struct dma_chan *chan = atmel_port->chan_tx; 609 unsigned long flags; 610 611 spin_lock_irqsave(&port->lock, flags); 612 613 if (chan) 614 dmaengine_terminate_all(chan); 615 xmit->tail += sg_dma_len(&atmel_port->sg_tx); 616 xmit->tail &= UART_XMIT_SIZE - 1; 617 618 port->icount.tx += sg_dma_len(&atmel_port->sg_tx); 619 620 spin_lock_irq(&atmel_port->lock_tx); 621 async_tx_ack(atmel_port->desc_tx); 622 atmel_port->cookie_tx = -EINVAL; 623 atmel_port->desc_tx = NULL; 624 spin_unlock_irq(&atmel_port->lock_tx); 625 626 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 627 uart_write_wakeup(port); 628 629 /* Do we really need this? */ 630 if (!uart_circ_empty(xmit)) 631 tasklet_schedule(&atmel_port->tasklet); 632 633 spin_unlock_irqrestore(&port->lock, flags); 634 } 635 636 static void atmel_release_tx_dma(struct uart_port *port) 637 { 638 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 639 struct dma_chan *chan = atmel_port->chan_tx; 640 641 if (chan) { 642 dmaengine_terminate_all(chan); 643 dma_release_channel(chan); 644 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, 645 DMA_MEM_TO_DEV); 646 } 647 648 atmel_port->desc_tx = NULL; 649 atmel_port->chan_tx = NULL; 650 atmel_port->cookie_tx = -EINVAL; 651 } 652 653 /* 654 * Called from tasklet with TXRDY interrupt is disabled. 655 */ 656 static void atmel_tx_dma(struct uart_port *port) 657 { 658 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 659 struct circ_buf *xmit = &port->state->xmit; 660 struct dma_chan *chan = atmel_port->chan_tx; 661 struct dma_async_tx_descriptor *desc; 662 struct scatterlist *sg = &atmel_port->sg_tx; 663 664 /* Make sure we have an idle channel */ 665 if (atmel_port->desc_tx != NULL) 666 return; 667 668 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 669 /* 670 * DMA is idle now. 671 * Port xmit buffer is already mapped, 672 * and it is one page... Just adjust 673 * offsets and lengths. Since it is a circular buffer, 674 * we have to transmit till the end, and then the rest. 675 * Take the port lock to get a 676 * consistent xmit buffer state. 677 */ 678 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 679 sg_dma_address(sg) = (sg_dma_address(sg) & 680 ~(UART_XMIT_SIZE - 1)) 681 + sg->offset; 682 sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head, 683 xmit->tail, 684 UART_XMIT_SIZE); 685 BUG_ON(!sg_dma_len(sg)); 686 687 desc = dmaengine_prep_slave_sg(chan, 688 sg, 689 1, 690 DMA_MEM_TO_DEV, 691 DMA_PREP_INTERRUPT | 692 DMA_CTRL_ACK); 693 if (!desc) { 694 dev_err(port->dev, "Failed to send via dma!\n"); 695 return; 696 } 697 698 dma_sync_sg_for_device(port->dev, sg, 1, DMA_MEM_TO_DEV); 699 700 atmel_port->desc_tx = desc; 701 desc->callback = atmel_complete_tx_dma; 702 desc->callback_param = atmel_port; 703 atmel_port->cookie_tx = dmaengine_submit(desc); 704 705 } else { 706 if (atmel_port->rs485.flags & SER_RS485_ENABLED) { 707 /* DMA done, stop TX, start RX for RS485 */ 708 atmel_start_rx(port); 709 } 710 } 711 712 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 713 uart_write_wakeup(port); 714 } 715 716 static int atmel_prepare_tx_dma(struct uart_port *port) 717 { 718 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 719 dma_cap_mask_t mask; 720 struct dma_slave_config config; 721 int ret, nent; 722 723 dma_cap_zero(mask); 724 dma_cap_set(DMA_SLAVE, mask); 725 726 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx"); 727 if (atmel_port->chan_tx == NULL) 728 goto chan_err; 729 dev_info(port->dev, "using %s for tx DMA transfers\n", 730 dma_chan_name(atmel_port->chan_tx)); 731 732 spin_lock_init(&atmel_port->lock_tx); 733 sg_init_table(&atmel_port->sg_tx, 1); 734 /* UART circular tx buffer is an aligned page. */ 735 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); 736 sg_set_page(&atmel_port->sg_tx, 737 virt_to_page(port->state->xmit.buf), 738 UART_XMIT_SIZE, 739 (int)port->state->xmit.buf & ~PAGE_MASK); 740 nent = dma_map_sg(port->dev, 741 &atmel_port->sg_tx, 742 1, 743 DMA_MEM_TO_DEV); 744 745 if (!nent) { 746 dev_dbg(port->dev, "need to release resource of dma\n"); 747 goto chan_err; 748 } else { 749 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 750 sg_dma_len(&atmel_port->sg_tx), 751 port->state->xmit.buf, 752 sg_dma_address(&atmel_port->sg_tx)); 753 } 754 755 /* Configure the slave DMA */ 756 memset(&config, 0, sizeof(config)); 757 config.direction = DMA_MEM_TO_DEV; 758 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 759 config.dst_addr = port->mapbase + ATMEL_US_THR; 760 761 ret = dmaengine_device_control(atmel_port->chan_tx, 762 DMA_SLAVE_CONFIG, 763 (unsigned long)&config); 764 if (ret) { 765 dev_err(port->dev, "DMA tx slave configuration failed\n"); 766 goto chan_err; 767 } 768 769 return 0; 770 771 chan_err: 772 dev_err(port->dev, "TX channel not available, switch to pio\n"); 773 atmel_port->use_dma_tx = 0; 774 if (atmel_port->chan_tx) 775 atmel_release_tx_dma(port); 776 return -EINVAL; 777 } 778 779 static void atmel_flip_buffer_rx_dma(struct uart_port *port, 780 char *buf, size_t count) 781 { 782 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 783 struct tty_port *tport = &port->state->port; 784 785 dma_sync_sg_for_cpu(port->dev, 786 &atmel_port->sg_rx, 787 1, 788 DMA_DEV_TO_MEM); 789 790 tty_insert_flip_string(tport, buf, count); 791 792 dma_sync_sg_for_device(port->dev, 793 &atmel_port->sg_rx, 794 1, 795 DMA_DEV_TO_MEM); 796 /* 797 * Drop the lock here since it might end up calling 798 * uart_start(), which takes the lock. 799 */ 800 spin_unlock(&port->lock); 801 tty_flip_buffer_push(tport); 802 spin_lock(&port->lock); 803 } 804 805 static void atmel_complete_rx_dma(void *arg) 806 { 807 struct uart_port *port = arg; 808 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 809 810 tasklet_schedule(&atmel_port->tasklet); 811 } 812 813 static void atmel_release_rx_dma(struct uart_port *port) 814 { 815 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 816 struct dma_chan *chan = atmel_port->chan_rx; 817 818 if (chan) { 819 dmaengine_terminate_all(chan); 820 dma_release_channel(chan); 821 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, 822 DMA_DEV_TO_MEM); 823 } 824 825 atmel_port->desc_rx = NULL; 826 atmel_port->chan_rx = NULL; 827 atmel_port->cookie_rx = -EINVAL; 828 829 if (!atmel_port->is_usart) 830 del_timer_sync(&atmel_port->uart_timer); 831 } 832 833 static void atmel_rx_from_dma(struct uart_port *port) 834 { 835 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 836 struct circ_buf *ring = &atmel_port->rx_ring; 837 struct dma_chan *chan = atmel_port->chan_rx; 838 struct dma_tx_state state; 839 enum dma_status dmastat; 840 size_t pending, count; 841 842 843 /* Reset the UART timeout early so that we don't miss one */ 844 UART_PUT_CR(port, ATMEL_US_STTTO); 845 dmastat = dmaengine_tx_status(chan, 846 atmel_port->cookie_rx, 847 &state); 848 /* Restart a new tasklet if DMA status is error */ 849 if (dmastat == DMA_ERROR) { 850 dev_dbg(port->dev, "Get residue error, restart tasklet\n"); 851 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 852 tasklet_schedule(&atmel_port->tasklet); 853 return; 854 } 855 /* current transfer size should no larger than dma buffer */ 856 pending = sg_dma_len(&atmel_port->sg_rx) - state.residue; 857 BUG_ON(pending > sg_dma_len(&atmel_port->sg_rx)); 858 859 /* 860 * This will take the chars we have so far, 861 * ring->head will record the transfer size, only new bytes come 862 * will insert into the framework. 863 */ 864 if (pending > ring->head) { 865 count = pending - ring->head; 866 867 atmel_flip_buffer_rx_dma(port, ring->buf + ring->head, count); 868 869 ring->head += count; 870 if (ring->head == sg_dma_len(&atmel_port->sg_rx)) 871 ring->head = 0; 872 873 port->icount.rx += count; 874 } 875 876 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 877 } 878 879 static int atmel_prepare_rx_dma(struct uart_port *port) 880 { 881 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 882 struct dma_async_tx_descriptor *desc; 883 dma_cap_mask_t mask; 884 struct dma_slave_config config; 885 struct circ_buf *ring; 886 int ret, nent; 887 888 ring = &atmel_port->rx_ring; 889 890 dma_cap_zero(mask); 891 dma_cap_set(DMA_CYCLIC, mask); 892 893 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx"); 894 if (atmel_port->chan_rx == NULL) 895 goto chan_err; 896 dev_info(port->dev, "using %s for rx DMA transfers\n", 897 dma_chan_name(atmel_port->chan_rx)); 898 899 spin_lock_init(&atmel_port->lock_rx); 900 sg_init_table(&atmel_port->sg_rx, 1); 901 /* UART circular rx buffer is an aligned page. */ 902 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); 903 sg_set_page(&atmel_port->sg_rx, 904 virt_to_page(ring->buf), 905 ATMEL_SERIAL_RINGSIZE, 906 (int)ring->buf & ~PAGE_MASK); 907 nent = dma_map_sg(port->dev, 908 &atmel_port->sg_rx, 909 1, 910 DMA_DEV_TO_MEM); 911 912 if (!nent) { 913 dev_dbg(port->dev, "need to release resource of dma\n"); 914 goto chan_err; 915 } else { 916 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 917 sg_dma_len(&atmel_port->sg_rx), 918 ring->buf, 919 sg_dma_address(&atmel_port->sg_rx)); 920 } 921 922 /* Configure the slave DMA */ 923 memset(&config, 0, sizeof(config)); 924 config.direction = DMA_DEV_TO_MEM; 925 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 926 config.src_addr = port->mapbase + ATMEL_US_RHR; 927 928 ret = dmaengine_device_control(atmel_port->chan_rx, 929 DMA_SLAVE_CONFIG, 930 (unsigned long)&config); 931 if (ret) { 932 dev_err(port->dev, "DMA rx slave configuration failed\n"); 933 goto chan_err; 934 } 935 /* 936 * Prepare a cyclic dma transfer, assign 2 descriptors, 937 * each one is half ring buffer size 938 */ 939 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, 940 sg_dma_address(&atmel_port->sg_rx), 941 sg_dma_len(&atmel_port->sg_rx), 942 sg_dma_len(&atmel_port->sg_rx)/2, 943 DMA_DEV_TO_MEM, 944 DMA_PREP_INTERRUPT); 945 desc->callback = atmel_complete_rx_dma; 946 desc->callback_param = port; 947 atmel_port->desc_rx = desc; 948 atmel_port->cookie_rx = dmaengine_submit(desc); 949 950 return 0; 951 952 chan_err: 953 dev_err(port->dev, "RX channel not available, switch to pio\n"); 954 atmel_port->use_dma_rx = 0; 955 if (atmel_port->chan_rx) 956 atmel_release_rx_dma(port); 957 return -EINVAL; 958 } 959 960 static void atmel_uart_timer_callback(unsigned long data) 961 { 962 struct uart_port *port = (void *)data; 963 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 964 965 tasklet_schedule(&atmel_port->tasklet); 966 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port)); 967 } 968 969 /* 970 * receive interrupt handler. 971 */ 972 static void 973 atmel_handle_receive(struct uart_port *port, unsigned int pending) 974 { 975 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 976 977 if (atmel_use_pdc_rx(port)) { 978 /* 979 * PDC receive. Just schedule the tasklet and let it 980 * figure out the details. 981 * 982 * TODO: We're not handling error flags correctly at 983 * the moment. 984 */ 985 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { 986 UART_PUT_IDR(port, (ATMEL_US_ENDRX 987 | ATMEL_US_TIMEOUT)); 988 tasklet_schedule(&atmel_port->tasklet); 989 } 990 991 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | 992 ATMEL_US_FRAME | ATMEL_US_PARE)) 993 atmel_pdc_rxerr(port, pending); 994 } 995 996 if (atmel_use_dma_rx(port)) { 997 if (pending & ATMEL_US_TIMEOUT) { 998 UART_PUT_IDR(port, ATMEL_US_TIMEOUT); 999 tasklet_schedule(&atmel_port->tasklet); 1000 } 1001 } 1002 1003 /* Interrupt receive */ 1004 if (pending & ATMEL_US_RXRDY) 1005 atmel_rx_chars(port); 1006 else if (pending & ATMEL_US_RXBRK) { 1007 /* 1008 * End of break detected. If it came along with a 1009 * character, atmel_rx_chars will handle it. 1010 */ 1011 UART_PUT_CR(port, ATMEL_US_RSTSTA); 1012 UART_PUT_IDR(port, ATMEL_US_RXBRK); 1013 atmel_port->break_active = 0; 1014 } 1015 } 1016 1017 /* 1018 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) 1019 */ 1020 static void 1021 atmel_handle_transmit(struct uart_port *port, unsigned int pending) 1022 { 1023 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1024 1025 if (pending & atmel_port->tx_done_mask) { 1026 /* Either PDC or interrupt transmission */ 1027 UART_PUT_IDR(port, atmel_port->tx_done_mask); 1028 tasklet_schedule(&atmel_port->tasklet); 1029 } 1030 } 1031 1032 /* 1033 * status flags interrupt handler. 1034 */ 1035 static void 1036 atmel_handle_status(struct uart_port *port, unsigned int pending, 1037 unsigned int status) 1038 { 1039 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1040 1041 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC 1042 | ATMEL_US_CTSIC)) { 1043 atmel_port->irq_status = status; 1044 tasklet_schedule(&atmel_port->tasklet); 1045 } 1046 } 1047 1048 /* 1049 * Interrupt handler 1050 */ 1051 static irqreturn_t atmel_interrupt(int irq, void *dev_id) 1052 { 1053 struct uart_port *port = dev_id; 1054 unsigned int status, pending, pass_counter = 0; 1055 1056 do { 1057 status = UART_GET_CSR(port); 1058 pending = status & UART_GET_IMR(port); 1059 if (!pending) 1060 break; 1061 1062 atmel_handle_receive(port, pending); 1063 atmel_handle_status(port, pending, status); 1064 atmel_handle_transmit(port, pending); 1065 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); 1066 1067 return pass_counter ? IRQ_HANDLED : IRQ_NONE; 1068 } 1069 1070 static void atmel_release_tx_pdc(struct uart_port *port) 1071 { 1072 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1073 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1074 1075 dma_unmap_single(port->dev, 1076 pdc->dma_addr, 1077 pdc->dma_size, 1078 DMA_TO_DEVICE); 1079 } 1080 1081 /* 1082 * Called from tasklet with ENDTX and TXBUFE interrupts disabled. 1083 */ 1084 static void atmel_tx_pdc(struct uart_port *port) 1085 { 1086 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1087 struct circ_buf *xmit = &port->state->xmit; 1088 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1089 int count; 1090 1091 /* nothing left to transmit? */ 1092 if (UART_GET_TCR(port)) 1093 return; 1094 1095 xmit->tail += pdc->ofs; 1096 xmit->tail &= UART_XMIT_SIZE - 1; 1097 1098 port->icount.tx += pdc->ofs; 1099 pdc->ofs = 0; 1100 1101 /* more to transmit - setup next transfer */ 1102 1103 /* disable PDC transmit */ 1104 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 1105 1106 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 1107 dma_sync_single_for_device(port->dev, 1108 pdc->dma_addr, 1109 pdc->dma_size, 1110 DMA_TO_DEVICE); 1111 1112 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1113 pdc->ofs = count; 1114 1115 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); 1116 UART_PUT_TCR(port, count); 1117 /* re-enable PDC transmit */ 1118 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 1119 /* Enable interrupts */ 1120 UART_PUT_IER(port, atmel_port->tx_done_mask); 1121 } else { 1122 if ((atmel_port->rs485.flags & SER_RS485_ENABLED) && 1123 !(atmel_port->rs485.flags & SER_RS485_RX_DURING_TX)) { 1124 /* DMA done, stop TX, start RX for RS485 */ 1125 atmel_start_rx(port); 1126 } 1127 } 1128 1129 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1130 uart_write_wakeup(port); 1131 } 1132 1133 static int atmel_prepare_tx_pdc(struct uart_port *port) 1134 { 1135 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1136 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1137 struct circ_buf *xmit = &port->state->xmit; 1138 1139 pdc->buf = xmit->buf; 1140 pdc->dma_addr = dma_map_single(port->dev, 1141 pdc->buf, 1142 UART_XMIT_SIZE, 1143 DMA_TO_DEVICE); 1144 pdc->dma_size = UART_XMIT_SIZE; 1145 pdc->ofs = 0; 1146 1147 return 0; 1148 } 1149 1150 static void atmel_rx_from_ring(struct uart_port *port) 1151 { 1152 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1153 struct circ_buf *ring = &atmel_port->rx_ring; 1154 unsigned int flg; 1155 unsigned int status; 1156 1157 while (ring->head != ring->tail) { 1158 struct atmel_uart_char c; 1159 1160 /* Make sure c is loaded after head. */ 1161 smp_rmb(); 1162 1163 c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; 1164 1165 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 1166 1167 port->icount.rx++; 1168 status = c.status; 1169 flg = TTY_NORMAL; 1170 1171 /* 1172 * note that the error handling code is 1173 * out of the main execution path 1174 */ 1175 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 1176 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { 1177 if (status & ATMEL_US_RXBRK) { 1178 /* ignore side-effect */ 1179 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 1180 1181 port->icount.brk++; 1182 if (uart_handle_break(port)) 1183 continue; 1184 } 1185 if (status & ATMEL_US_PARE) 1186 port->icount.parity++; 1187 if (status & ATMEL_US_FRAME) 1188 port->icount.frame++; 1189 if (status & ATMEL_US_OVRE) 1190 port->icount.overrun++; 1191 1192 status &= port->read_status_mask; 1193 1194 if (status & ATMEL_US_RXBRK) 1195 flg = TTY_BREAK; 1196 else if (status & ATMEL_US_PARE) 1197 flg = TTY_PARITY; 1198 else if (status & ATMEL_US_FRAME) 1199 flg = TTY_FRAME; 1200 } 1201 1202 1203 if (uart_handle_sysrq_char(port, c.ch)) 1204 continue; 1205 1206 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); 1207 } 1208 1209 /* 1210 * Drop the lock here since it might end up calling 1211 * uart_start(), which takes the lock. 1212 */ 1213 spin_unlock(&port->lock); 1214 tty_flip_buffer_push(&port->state->port); 1215 spin_lock(&port->lock); 1216 } 1217 1218 static void atmel_release_rx_pdc(struct uart_port *port) 1219 { 1220 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1221 int i; 1222 1223 for (i = 0; i < 2; i++) { 1224 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1225 1226 dma_unmap_single(port->dev, 1227 pdc->dma_addr, 1228 pdc->dma_size, 1229 DMA_FROM_DEVICE); 1230 kfree(pdc->buf); 1231 } 1232 1233 if (!atmel_port->is_usart) 1234 del_timer_sync(&atmel_port->uart_timer); 1235 } 1236 1237 static void atmel_rx_from_pdc(struct uart_port *port) 1238 { 1239 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1240 struct tty_port *tport = &port->state->port; 1241 struct atmel_dma_buffer *pdc; 1242 int rx_idx = atmel_port->pdc_rx_idx; 1243 unsigned int head; 1244 unsigned int tail; 1245 unsigned int count; 1246 1247 do { 1248 /* Reset the UART timeout early so that we don't miss one */ 1249 UART_PUT_CR(port, ATMEL_US_STTTO); 1250 1251 pdc = &atmel_port->pdc_rx[rx_idx]; 1252 head = UART_GET_RPR(port) - pdc->dma_addr; 1253 tail = pdc->ofs; 1254 1255 /* If the PDC has switched buffers, RPR won't contain 1256 * any address within the current buffer. Since head 1257 * is unsigned, we just need a one-way comparison to 1258 * find out. 1259 * 1260 * In this case, we just need to consume the entire 1261 * buffer and resubmit it for DMA. This will clear the 1262 * ENDRX bit as well, so that we can safely re-enable 1263 * all interrupts below. 1264 */ 1265 head = min(head, pdc->dma_size); 1266 1267 if (likely(head != tail)) { 1268 dma_sync_single_for_cpu(port->dev, pdc->dma_addr, 1269 pdc->dma_size, DMA_FROM_DEVICE); 1270 1271 /* 1272 * head will only wrap around when we recycle 1273 * the DMA buffer, and when that happens, we 1274 * explicitly set tail to 0. So head will 1275 * always be greater than tail. 1276 */ 1277 count = head - tail; 1278 1279 tty_insert_flip_string(tport, pdc->buf + pdc->ofs, 1280 count); 1281 1282 dma_sync_single_for_device(port->dev, pdc->dma_addr, 1283 pdc->dma_size, DMA_FROM_DEVICE); 1284 1285 port->icount.rx += count; 1286 pdc->ofs = head; 1287 } 1288 1289 /* 1290 * If the current buffer is full, we need to check if 1291 * the next one contains any additional data. 1292 */ 1293 if (head >= pdc->dma_size) { 1294 pdc->ofs = 0; 1295 UART_PUT_RNPR(port, pdc->dma_addr); 1296 UART_PUT_RNCR(port, pdc->dma_size); 1297 1298 rx_idx = !rx_idx; 1299 atmel_port->pdc_rx_idx = rx_idx; 1300 } 1301 } while (head >= pdc->dma_size); 1302 1303 /* 1304 * Drop the lock here since it might end up calling 1305 * uart_start(), which takes the lock. 1306 */ 1307 spin_unlock(&port->lock); 1308 tty_flip_buffer_push(tport); 1309 spin_lock(&port->lock); 1310 1311 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1312 } 1313 1314 static int atmel_prepare_rx_pdc(struct uart_port *port) 1315 { 1316 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1317 int i; 1318 1319 for (i = 0; i < 2; i++) { 1320 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1321 1322 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); 1323 if (pdc->buf == NULL) { 1324 if (i != 0) { 1325 dma_unmap_single(port->dev, 1326 atmel_port->pdc_rx[0].dma_addr, 1327 PDC_BUFFER_SIZE, 1328 DMA_FROM_DEVICE); 1329 kfree(atmel_port->pdc_rx[0].buf); 1330 } 1331 atmel_port->use_pdc_rx = 0; 1332 return -ENOMEM; 1333 } 1334 pdc->dma_addr = dma_map_single(port->dev, 1335 pdc->buf, 1336 PDC_BUFFER_SIZE, 1337 DMA_FROM_DEVICE); 1338 pdc->dma_size = PDC_BUFFER_SIZE; 1339 pdc->ofs = 0; 1340 } 1341 1342 atmel_port->pdc_rx_idx = 0; 1343 1344 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); 1345 UART_PUT_RCR(port, PDC_BUFFER_SIZE); 1346 1347 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); 1348 UART_PUT_RNCR(port, PDC_BUFFER_SIZE); 1349 1350 return 0; 1351 } 1352 1353 /* 1354 * tasklet handling tty stuff outside the interrupt handler. 1355 */ 1356 static void atmel_tasklet_func(unsigned long data) 1357 { 1358 struct uart_port *port = (struct uart_port *)data; 1359 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1360 unsigned int status; 1361 unsigned int status_change; 1362 1363 /* The interrupt handler does not take the lock */ 1364 spin_lock(&port->lock); 1365 1366 atmel_port->schedule_tx(port); 1367 1368 status = atmel_port->irq_status; 1369 status_change = status ^ atmel_port->irq_status_prev; 1370 1371 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR 1372 | ATMEL_US_DCD | ATMEL_US_CTS)) { 1373 /* TODO: All reads to CSR will clear these interrupts! */ 1374 if (status_change & ATMEL_US_RI) 1375 port->icount.rng++; 1376 if (status_change & ATMEL_US_DSR) 1377 port->icount.dsr++; 1378 if (status_change & ATMEL_US_DCD) 1379 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); 1380 if (status_change & ATMEL_US_CTS) 1381 uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); 1382 1383 wake_up_interruptible(&port->state->port.delta_msr_wait); 1384 1385 atmel_port->irq_status_prev = status; 1386 } 1387 1388 atmel_port->schedule_rx(port); 1389 1390 spin_unlock(&port->lock); 1391 } 1392 1393 static int atmel_init_property(struct atmel_uart_port *atmel_port, 1394 struct platform_device *pdev) 1395 { 1396 struct device_node *np = pdev->dev.of_node; 1397 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1398 1399 if (np) { 1400 /* DMA/PDC usage specification */ 1401 if (of_get_property(np, "atmel,use-dma-rx", NULL)) { 1402 if (of_get_property(np, "dmas", NULL)) { 1403 atmel_port->use_dma_rx = true; 1404 atmel_port->use_pdc_rx = false; 1405 } else { 1406 atmel_port->use_dma_rx = false; 1407 atmel_port->use_pdc_rx = true; 1408 } 1409 } else { 1410 atmel_port->use_dma_rx = false; 1411 atmel_port->use_pdc_rx = false; 1412 } 1413 1414 if (of_get_property(np, "atmel,use-dma-tx", NULL)) { 1415 if (of_get_property(np, "dmas", NULL)) { 1416 atmel_port->use_dma_tx = true; 1417 atmel_port->use_pdc_tx = false; 1418 } else { 1419 atmel_port->use_dma_tx = false; 1420 atmel_port->use_pdc_tx = true; 1421 } 1422 } else { 1423 atmel_port->use_dma_tx = false; 1424 atmel_port->use_pdc_tx = false; 1425 } 1426 1427 } else { 1428 atmel_port->use_pdc_rx = pdata->use_dma_rx; 1429 atmel_port->use_pdc_tx = pdata->use_dma_tx; 1430 atmel_port->use_dma_rx = false; 1431 atmel_port->use_dma_tx = false; 1432 } 1433 1434 return 0; 1435 } 1436 1437 static void atmel_init_rs485(struct atmel_uart_port *atmel_port, 1438 struct platform_device *pdev) 1439 { 1440 struct device_node *np = pdev->dev.of_node; 1441 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1442 1443 if (np) { 1444 u32 rs485_delay[2]; 1445 /* rs485 properties */ 1446 if (of_property_read_u32_array(np, "rs485-rts-delay", 1447 rs485_delay, 2) == 0) { 1448 struct serial_rs485 *rs485conf = &atmel_port->rs485; 1449 1450 rs485conf->delay_rts_before_send = rs485_delay[0]; 1451 rs485conf->delay_rts_after_send = rs485_delay[1]; 1452 rs485conf->flags = 0; 1453 1454 if (of_get_property(np, "rs485-rx-during-tx", NULL)) 1455 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1456 1457 if (of_get_property(np, "linux,rs485-enabled-at-boot-time", 1458 NULL)) 1459 rs485conf->flags |= SER_RS485_ENABLED; 1460 } 1461 } else { 1462 atmel_port->rs485 = pdata->rs485; 1463 } 1464 1465 } 1466 1467 static void atmel_set_ops(struct uart_port *port) 1468 { 1469 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1470 1471 if (atmel_use_dma_rx(port)) { 1472 atmel_port->prepare_rx = &atmel_prepare_rx_dma; 1473 atmel_port->schedule_rx = &atmel_rx_from_dma; 1474 atmel_port->release_rx = &atmel_release_rx_dma; 1475 } else if (atmel_use_pdc_rx(port)) { 1476 atmel_port->prepare_rx = &atmel_prepare_rx_pdc; 1477 atmel_port->schedule_rx = &atmel_rx_from_pdc; 1478 atmel_port->release_rx = &atmel_release_rx_pdc; 1479 } else { 1480 atmel_port->prepare_rx = NULL; 1481 atmel_port->schedule_rx = &atmel_rx_from_ring; 1482 atmel_port->release_rx = NULL; 1483 } 1484 1485 if (atmel_use_dma_tx(port)) { 1486 atmel_port->prepare_tx = &atmel_prepare_tx_dma; 1487 atmel_port->schedule_tx = &atmel_tx_dma; 1488 atmel_port->release_tx = &atmel_release_tx_dma; 1489 } else if (atmel_use_pdc_tx(port)) { 1490 atmel_port->prepare_tx = &atmel_prepare_tx_pdc; 1491 atmel_port->schedule_tx = &atmel_tx_pdc; 1492 atmel_port->release_tx = &atmel_release_tx_pdc; 1493 } else { 1494 atmel_port->prepare_tx = NULL; 1495 atmel_port->schedule_tx = &atmel_tx_chars; 1496 atmel_port->release_tx = NULL; 1497 } 1498 } 1499 1500 /* 1501 * Get ip name usart or uart 1502 */ 1503 static void atmel_get_ip_name(struct uart_port *port) 1504 { 1505 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1506 int name = UART_GET_IP_NAME(port); 1507 u32 version; 1508 int usart, uart; 1509 /* usart and uart ascii */ 1510 usart = 0x55534152; 1511 uart = 0x44424755; 1512 1513 atmel_port->is_usart = false; 1514 1515 if (name == usart) { 1516 dev_dbg(port->dev, "This is usart\n"); 1517 atmel_port->is_usart = true; 1518 } else if (name == uart) { 1519 dev_dbg(port->dev, "This is uart\n"); 1520 atmel_port->is_usart = false; 1521 } else { 1522 /* fallback for older SoCs: use version field */ 1523 version = UART_GET_IP_VERSION(port); 1524 switch (version) { 1525 case 0x302: 1526 case 0x10213: 1527 dev_dbg(port->dev, "This version is usart\n"); 1528 atmel_port->is_usart = true; 1529 break; 1530 case 0x203: 1531 case 0x10202: 1532 dev_dbg(port->dev, "This version is uart\n"); 1533 atmel_port->is_usart = false; 1534 break; 1535 default: 1536 dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); 1537 } 1538 } 1539 } 1540 1541 /* 1542 * Perform initialization and enable port for reception 1543 */ 1544 static int atmel_startup(struct uart_port *port) 1545 { 1546 struct platform_device *pdev = to_platform_device(port->dev); 1547 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1548 struct tty_struct *tty = port->state->port.tty; 1549 int retval; 1550 1551 /* 1552 * Ensure that no interrupts are enabled otherwise when 1553 * request_irq() is called we could get stuck trying to 1554 * handle an unexpected interrupt 1555 */ 1556 UART_PUT_IDR(port, -1); 1557 1558 /* 1559 * Allocate the IRQ 1560 */ 1561 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, 1562 tty ? tty->name : "atmel_serial", port); 1563 if (retval) { 1564 printk("atmel_serial: atmel_startup - Can't get irq\n"); 1565 return retval; 1566 } 1567 1568 /* 1569 * Initialize DMA (if necessary) 1570 */ 1571 atmel_init_property(atmel_port, pdev); 1572 1573 if (atmel_port->prepare_rx) { 1574 retval = atmel_port->prepare_rx(port); 1575 if (retval < 0) 1576 atmel_set_ops(port); 1577 } 1578 1579 if (atmel_port->prepare_tx) { 1580 retval = atmel_port->prepare_tx(port); 1581 if (retval < 0) 1582 atmel_set_ops(port); 1583 } 1584 /* 1585 * If there is a specific "open" function (to register 1586 * control line interrupts) 1587 */ 1588 if (atmel_open_hook) { 1589 retval = atmel_open_hook(port); 1590 if (retval) { 1591 free_irq(port->irq, port); 1592 return retval; 1593 } 1594 } 1595 1596 /* Save current CSR for comparison in atmel_tasklet_func() */ 1597 atmel_port->irq_status_prev = UART_GET_CSR(port); 1598 atmel_port->irq_status = atmel_port->irq_status_prev; 1599 1600 /* 1601 * Finally, enable the serial port 1602 */ 1603 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1604 /* enable xmit & rcvr */ 1605 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 1606 1607 if (atmel_use_pdc_rx(port)) { 1608 /* set UART timeout */ 1609 if (!atmel_port->is_usart) { 1610 setup_timer(&atmel_port->uart_timer, 1611 atmel_uart_timer_callback, 1612 (unsigned long)port); 1613 mod_timer(&atmel_port->uart_timer, 1614 jiffies + uart_poll_timeout(port)); 1615 /* set USART timeout */ 1616 } else { 1617 UART_PUT_RTOR(port, PDC_RX_TIMEOUT); 1618 UART_PUT_CR(port, ATMEL_US_STTTO); 1619 1620 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1621 } 1622 /* enable PDC controller */ 1623 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); 1624 } else if (atmel_use_dma_rx(port)) { 1625 /* set UART timeout */ 1626 if (!atmel_port->is_usart) { 1627 setup_timer(&atmel_port->uart_timer, 1628 atmel_uart_timer_callback, 1629 (unsigned long)port); 1630 mod_timer(&atmel_port->uart_timer, 1631 jiffies + uart_poll_timeout(port)); 1632 /* set USART timeout */ 1633 } else { 1634 UART_PUT_RTOR(port, PDC_RX_TIMEOUT); 1635 UART_PUT_CR(port, ATMEL_US_STTTO); 1636 1637 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 1638 } 1639 } else { 1640 /* enable receive only */ 1641 UART_PUT_IER(port, ATMEL_US_RXRDY); 1642 } 1643 1644 return 0; 1645 } 1646 1647 /* 1648 * Disable the port 1649 */ 1650 static void atmel_shutdown(struct uart_port *port) 1651 { 1652 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1653 /* 1654 * Ensure everything is stopped. 1655 */ 1656 atmel_stop_rx(port); 1657 atmel_stop_tx(port); 1658 1659 /* 1660 * Shut-down the DMA. 1661 */ 1662 if (atmel_port->release_rx) 1663 atmel_port->release_rx(port); 1664 if (atmel_port->release_tx) 1665 atmel_port->release_tx(port); 1666 1667 /* 1668 * Disable all interrupts, port and break condition. 1669 */ 1670 UART_PUT_CR(port, ATMEL_US_RSTSTA); 1671 UART_PUT_IDR(port, -1); 1672 1673 /* 1674 * Free the interrupt 1675 */ 1676 free_irq(port->irq, port); 1677 1678 /* 1679 * If there is a specific "close" function (to unregister 1680 * control line interrupts) 1681 */ 1682 if (atmel_close_hook) 1683 atmel_close_hook(port); 1684 } 1685 1686 /* 1687 * Flush any TX data submitted for DMA. Called when the TX circular 1688 * buffer is reset. 1689 */ 1690 static void atmel_flush_buffer(struct uart_port *port) 1691 { 1692 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1693 1694 if (atmel_use_pdc_tx(port)) { 1695 UART_PUT_TCR(port, 0); 1696 atmel_port->pdc_tx.ofs = 0; 1697 } 1698 } 1699 1700 /* 1701 * Power / Clock management. 1702 */ 1703 static void atmel_serial_pm(struct uart_port *port, unsigned int state, 1704 unsigned int oldstate) 1705 { 1706 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1707 1708 switch (state) { 1709 case 0: 1710 /* 1711 * Enable the peripheral clock for this serial port. 1712 * This is called on uart_open() or a resume event. 1713 */ 1714 clk_prepare_enable(atmel_port->clk); 1715 1716 /* re-enable interrupts if we disabled some on suspend */ 1717 UART_PUT_IER(port, atmel_port->backup_imr); 1718 break; 1719 case 3: 1720 /* Back up the interrupt mask and disable all interrupts */ 1721 atmel_port->backup_imr = UART_GET_IMR(port); 1722 UART_PUT_IDR(port, -1); 1723 1724 /* 1725 * Disable the peripheral clock for this serial port. 1726 * This is called on uart_close() or a suspend event. 1727 */ 1728 clk_disable_unprepare(atmel_port->clk); 1729 break; 1730 default: 1731 printk(KERN_ERR "atmel_serial: unknown pm %d\n", state); 1732 } 1733 } 1734 1735 /* 1736 * Change the port parameters 1737 */ 1738 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, 1739 struct ktermios *old) 1740 { 1741 unsigned long flags; 1742 unsigned int mode, imr, quot, baud; 1743 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1744 1745 /* Get current mode register */ 1746 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL 1747 | ATMEL_US_NBSTOP | ATMEL_US_PAR 1748 | ATMEL_US_USMODE); 1749 1750 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1751 quot = uart_get_divisor(port, baud); 1752 1753 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ 1754 quot /= 8; 1755 mode |= ATMEL_US_USCLKS_MCK_DIV8; 1756 } 1757 1758 /* byte size */ 1759 switch (termios->c_cflag & CSIZE) { 1760 case CS5: 1761 mode |= ATMEL_US_CHRL_5; 1762 break; 1763 case CS6: 1764 mode |= ATMEL_US_CHRL_6; 1765 break; 1766 case CS7: 1767 mode |= ATMEL_US_CHRL_7; 1768 break; 1769 default: 1770 mode |= ATMEL_US_CHRL_8; 1771 break; 1772 } 1773 1774 /* stop bits */ 1775 if (termios->c_cflag & CSTOPB) 1776 mode |= ATMEL_US_NBSTOP_2; 1777 1778 /* parity */ 1779 if (termios->c_cflag & PARENB) { 1780 /* Mark or Space parity */ 1781 if (termios->c_cflag & CMSPAR) { 1782 if (termios->c_cflag & PARODD) 1783 mode |= ATMEL_US_PAR_MARK; 1784 else 1785 mode |= ATMEL_US_PAR_SPACE; 1786 } else if (termios->c_cflag & PARODD) 1787 mode |= ATMEL_US_PAR_ODD; 1788 else 1789 mode |= ATMEL_US_PAR_EVEN; 1790 } else 1791 mode |= ATMEL_US_PAR_NONE; 1792 1793 /* hardware handshake (RTS/CTS) */ 1794 if (termios->c_cflag & CRTSCTS) 1795 mode |= ATMEL_US_USMODE_HWHS; 1796 else 1797 mode |= ATMEL_US_USMODE_NORMAL; 1798 1799 spin_lock_irqsave(&port->lock, flags); 1800 1801 port->read_status_mask = ATMEL_US_OVRE; 1802 if (termios->c_iflag & INPCK) 1803 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 1804 if (termios->c_iflag & (BRKINT | PARMRK)) 1805 port->read_status_mask |= ATMEL_US_RXBRK; 1806 1807 if (atmel_use_pdc_rx(port)) 1808 /* need to enable error interrupts */ 1809 UART_PUT_IER(port, port->read_status_mask); 1810 1811 /* 1812 * Characters to ignore 1813 */ 1814 port->ignore_status_mask = 0; 1815 if (termios->c_iflag & IGNPAR) 1816 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 1817 if (termios->c_iflag & IGNBRK) { 1818 port->ignore_status_mask |= ATMEL_US_RXBRK; 1819 /* 1820 * If we're ignoring parity and break indicators, 1821 * ignore overruns too (for real raw support). 1822 */ 1823 if (termios->c_iflag & IGNPAR) 1824 port->ignore_status_mask |= ATMEL_US_OVRE; 1825 } 1826 /* TODO: Ignore all characters if CREAD is set.*/ 1827 1828 /* update the per-port timeout */ 1829 uart_update_timeout(port, termios->c_cflag, baud); 1830 1831 /* 1832 * save/disable interrupts. The tty layer will ensure that the 1833 * transmitter is empty if requested by the caller, so there's 1834 * no need to wait for it here. 1835 */ 1836 imr = UART_GET_IMR(port); 1837 UART_PUT_IDR(port, -1); 1838 1839 /* disable receiver and transmitter */ 1840 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); 1841 1842 /* Resetting serial mode to RS232 (0x0) */ 1843 mode &= ~ATMEL_US_USMODE; 1844 1845 if (atmel_port->rs485.flags & SER_RS485_ENABLED) { 1846 dev_dbg(port->dev, "Setting UART to RS485\n"); 1847 if ((atmel_port->rs485.delay_rts_after_send) > 0) 1848 UART_PUT_TTGR(port, 1849 atmel_port->rs485.delay_rts_after_send); 1850 mode |= ATMEL_US_USMODE_RS485; 1851 } else { 1852 dev_dbg(port->dev, "Setting UART to RS232\n"); 1853 } 1854 1855 /* set the parity, stop bits and data size */ 1856 UART_PUT_MR(port, mode); 1857 1858 /* set the baud rate */ 1859 UART_PUT_BRGR(port, quot); 1860 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1861 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 1862 1863 /* restore interrupts */ 1864 UART_PUT_IER(port, imr); 1865 1866 /* CTS flow-control and modem-status interrupts */ 1867 if (UART_ENABLE_MS(port, termios->c_cflag)) 1868 port->ops->enable_ms(port); 1869 1870 spin_unlock_irqrestore(&port->lock, flags); 1871 } 1872 1873 static void atmel_set_ldisc(struct uart_port *port, int new) 1874 { 1875 if (new == N_PPS) { 1876 port->flags |= UPF_HARDPPS_CD; 1877 atmel_enable_ms(port); 1878 } else { 1879 port->flags &= ~UPF_HARDPPS_CD; 1880 } 1881 } 1882 1883 /* 1884 * Return string describing the specified port 1885 */ 1886 static const char *atmel_type(struct uart_port *port) 1887 { 1888 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; 1889 } 1890 1891 /* 1892 * Release the memory region(s) being used by 'port'. 1893 */ 1894 static void atmel_release_port(struct uart_port *port) 1895 { 1896 struct platform_device *pdev = to_platform_device(port->dev); 1897 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 1898 1899 release_mem_region(port->mapbase, size); 1900 1901 if (port->flags & UPF_IOREMAP) { 1902 iounmap(port->membase); 1903 port->membase = NULL; 1904 } 1905 } 1906 1907 /* 1908 * Request the memory region(s) being used by 'port'. 1909 */ 1910 static int atmel_request_port(struct uart_port *port) 1911 { 1912 struct platform_device *pdev = to_platform_device(port->dev); 1913 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 1914 1915 if (!request_mem_region(port->mapbase, size, "atmel_serial")) 1916 return -EBUSY; 1917 1918 if (port->flags & UPF_IOREMAP) { 1919 port->membase = ioremap(port->mapbase, size); 1920 if (port->membase == NULL) { 1921 release_mem_region(port->mapbase, size); 1922 return -ENOMEM; 1923 } 1924 } 1925 1926 return 0; 1927 } 1928 1929 /* 1930 * Configure/autoconfigure the port. 1931 */ 1932 static void atmel_config_port(struct uart_port *port, int flags) 1933 { 1934 if (flags & UART_CONFIG_TYPE) { 1935 port->type = PORT_ATMEL; 1936 atmel_request_port(port); 1937 } 1938 } 1939 1940 /* 1941 * Verify the new serial_struct (for TIOCSSERIAL). 1942 */ 1943 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) 1944 { 1945 int ret = 0; 1946 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) 1947 ret = -EINVAL; 1948 if (port->irq != ser->irq) 1949 ret = -EINVAL; 1950 if (ser->io_type != SERIAL_IO_MEM) 1951 ret = -EINVAL; 1952 if (port->uartclk / 16 != ser->baud_base) 1953 ret = -EINVAL; 1954 if ((void *)port->mapbase != ser->iomem_base) 1955 ret = -EINVAL; 1956 if (port->iobase != ser->port) 1957 ret = -EINVAL; 1958 if (ser->hub6 != 0) 1959 ret = -EINVAL; 1960 return ret; 1961 } 1962 1963 #ifdef CONFIG_CONSOLE_POLL 1964 static int atmel_poll_get_char(struct uart_port *port) 1965 { 1966 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY)) 1967 cpu_relax(); 1968 1969 return UART_GET_CHAR(port); 1970 } 1971 1972 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) 1973 { 1974 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) 1975 cpu_relax(); 1976 1977 UART_PUT_CHAR(port, ch); 1978 } 1979 #endif 1980 1981 static int 1982 atmel_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg) 1983 { 1984 struct serial_rs485 rs485conf; 1985 1986 switch (cmd) { 1987 case TIOCSRS485: 1988 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg, 1989 sizeof(rs485conf))) 1990 return -EFAULT; 1991 1992 atmel_config_rs485(port, &rs485conf); 1993 break; 1994 1995 case TIOCGRS485: 1996 if (copy_to_user((struct serial_rs485 *) arg, 1997 &(to_atmel_uart_port(port)->rs485), 1998 sizeof(rs485conf))) 1999 return -EFAULT; 2000 break; 2001 2002 default: 2003 return -ENOIOCTLCMD; 2004 } 2005 return 0; 2006 } 2007 2008 2009 2010 static struct uart_ops atmel_pops = { 2011 .tx_empty = atmel_tx_empty, 2012 .set_mctrl = atmel_set_mctrl, 2013 .get_mctrl = atmel_get_mctrl, 2014 .stop_tx = atmel_stop_tx, 2015 .start_tx = atmel_start_tx, 2016 .stop_rx = atmel_stop_rx, 2017 .enable_ms = atmel_enable_ms, 2018 .break_ctl = atmel_break_ctl, 2019 .startup = atmel_startup, 2020 .shutdown = atmel_shutdown, 2021 .flush_buffer = atmel_flush_buffer, 2022 .set_termios = atmel_set_termios, 2023 .set_ldisc = atmel_set_ldisc, 2024 .type = atmel_type, 2025 .release_port = atmel_release_port, 2026 .request_port = atmel_request_port, 2027 .config_port = atmel_config_port, 2028 .verify_port = atmel_verify_port, 2029 .pm = atmel_serial_pm, 2030 .ioctl = atmel_ioctl, 2031 #ifdef CONFIG_CONSOLE_POLL 2032 .poll_get_char = atmel_poll_get_char, 2033 .poll_put_char = atmel_poll_put_char, 2034 #endif 2035 }; 2036 2037 /* 2038 * Configure the port from the platform device resource info. 2039 */ 2040 static int atmel_init_port(struct atmel_uart_port *atmel_port, 2041 struct platform_device *pdev) 2042 { 2043 int ret; 2044 struct uart_port *port = &atmel_port->uart; 2045 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2046 2047 if (!atmel_init_property(atmel_port, pdev)) 2048 atmel_set_ops(port); 2049 2050 atmel_init_rs485(atmel_port, pdev); 2051 2052 port->iotype = UPIO_MEM; 2053 port->flags = UPF_BOOT_AUTOCONF; 2054 port->ops = &atmel_pops; 2055 port->fifosize = 1; 2056 port->dev = &pdev->dev; 2057 port->mapbase = pdev->resource[0].start; 2058 port->irq = pdev->resource[1].start; 2059 2060 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, 2061 (unsigned long)port); 2062 2063 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); 2064 2065 if (pdata && pdata->regs) { 2066 /* Already mapped by setup code */ 2067 port->membase = pdata->regs; 2068 } else { 2069 port->flags |= UPF_IOREMAP; 2070 port->membase = NULL; 2071 } 2072 2073 /* for console, the clock could already be configured */ 2074 if (!atmel_port->clk) { 2075 atmel_port->clk = clk_get(&pdev->dev, "usart"); 2076 if (IS_ERR(atmel_port->clk)) { 2077 ret = PTR_ERR(atmel_port->clk); 2078 atmel_port->clk = NULL; 2079 return ret; 2080 } 2081 ret = clk_prepare_enable(atmel_port->clk); 2082 if (ret) { 2083 clk_put(atmel_port->clk); 2084 atmel_port->clk = NULL; 2085 return ret; 2086 } 2087 port->uartclk = clk_get_rate(atmel_port->clk); 2088 clk_disable_unprepare(atmel_port->clk); 2089 /* only enable clock when USART is in use */ 2090 } 2091 2092 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ 2093 if (atmel_port->rs485.flags & SER_RS485_ENABLED) 2094 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 2095 else if (atmel_use_pdc_tx(port)) { 2096 port->fifosize = PDC_BUFFER_SIZE; 2097 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; 2098 } else { 2099 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 2100 } 2101 2102 return 0; 2103 } 2104 2105 struct platform_device *atmel_default_console_device; /* the serial console device */ 2106 2107 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2108 static void atmel_console_putchar(struct uart_port *port, int ch) 2109 { 2110 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) 2111 cpu_relax(); 2112 UART_PUT_CHAR(port, ch); 2113 } 2114 2115 /* 2116 * Interrupts are disabled on entering 2117 */ 2118 static void atmel_console_write(struct console *co, const char *s, u_int count) 2119 { 2120 struct uart_port *port = &atmel_ports[co->index].uart; 2121 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2122 unsigned int status, imr; 2123 unsigned int pdc_tx; 2124 2125 /* 2126 * First, save IMR and then disable interrupts 2127 */ 2128 imr = UART_GET_IMR(port); 2129 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask); 2130 2131 /* Store PDC transmit status and disable it */ 2132 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN; 2133 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 2134 2135 uart_console_write(port, s, count, atmel_console_putchar); 2136 2137 /* 2138 * Finally, wait for transmitter to become empty 2139 * and restore IMR 2140 */ 2141 do { 2142 status = UART_GET_CSR(port); 2143 } while (!(status & ATMEL_US_TXRDY)); 2144 2145 /* Restore PDC transmit status */ 2146 if (pdc_tx) 2147 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 2148 2149 /* set interrupts back the way they were */ 2150 UART_PUT_IER(port, imr); 2151 } 2152 2153 /* 2154 * If the port was already initialised (eg, by a boot loader), 2155 * try to determine the current setup. 2156 */ 2157 static void __init atmel_console_get_options(struct uart_port *port, int *baud, 2158 int *parity, int *bits) 2159 { 2160 unsigned int mr, quot; 2161 2162 /* 2163 * If the baud rate generator isn't running, the port wasn't 2164 * initialized by the boot loader. 2165 */ 2166 quot = UART_GET_BRGR(port) & ATMEL_US_CD; 2167 if (!quot) 2168 return; 2169 2170 mr = UART_GET_MR(port) & ATMEL_US_CHRL; 2171 if (mr == ATMEL_US_CHRL_8) 2172 *bits = 8; 2173 else 2174 *bits = 7; 2175 2176 mr = UART_GET_MR(port) & ATMEL_US_PAR; 2177 if (mr == ATMEL_US_PAR_EVEN) 2178 *parity = 'e'; 2179 else if (mr == ATMEL_US_PAR_ODD) 2180 *parity = 'o'; 2181 2182 /* 2183 * The serial core only rounds down when matching this to a 2184 * supported baud rate. Make sure we don't end up slightly 2185 * lower than one of those, as it would make us fall through 2186 * to a much lower baud rate than we really want. 2187 */ 2188 *baud = port->uartclk / (16 * (quot - 1)); 2189 } 2190 2191 static int __init atmel_console_setup(struct console *co, char *options) 2192 { 2193 int ret; 2194 struct uart_port *port = &atmel_ports[co->index].uart; 2195 int baud = 115200; 2196 int bits = 8; 2197 int parity = 'n'; 2198 int flow = 'n'; 2199 2200 if (port->membase == NULL) { 2201 /* Port not initialized yet - delay setup */ 2202 return -ENODEV; 2203 } 2204 2205 ret = clk_prepare_enable(atmel_ports[co->index].clk); 2206 if (ret) 2207 return ret; 2208 2209 UART_PUT_IDR(port, -1); 2210 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2211 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 2212 2213 if (options) 2214 uart_parse_options(options, &baud, &parity, &bits, &flow); 2215 else 2216 atmel_console_get_options(port, &baud, &parity, &bits); 2217 2218 return uart_set_options(port, co, baud, parity, bits, flow); 2219 } 2220 2221 static struct uart_driver atmel_uart; 2222 2223 static struct console atmel_console = { 2224 .name = ATMEL_DEVICENAME, 2225 .write = atmel_console_write, 2226 .device = uart_console_device, 2227 .setup = atmel_console_setup, 2228 .flags = CON_PRINTBUFFER, 2229 .index = -1, 2230 .data = &atmel_uart, 2231 }; 2232 2233 #define ATMEL_CONSOLE_DEVICE (&atmel_console) 2234 2235 /* 2236 * Early console initialization (before VM subsystem initialized). 2237 */ 2238 static int __init atmel_console_init(void) 2239 { 2240 int ret; 2241 if (atmel_default_console_device) { 2242 struct atmel_uart_data *pdata = 2243 dev_get_platdata(&atmel_default_console_device->dev); 2244 int id = pdata->num; 2245 struct atmel_uart_port *port = &atmel_ports[id]; 2246 2247 port->backup_imr = 0; 2248 port->uart.line = id; 2249 2250 add_preferred_console(ATMEL_DEVICENAME, id, NULL); 2251 ret = atmel_init_port(port, atmel_default_console_device); 2252 if (ret) 2253 return ret; 2254 register_console(&atmel_console); 2255 } 2256 2257 return 0; 2258 } 2259 2260 console_initcall(atmel_console_init); 2261 2262 /* 2263 * Late console initialization. 2264 */ 2265 static int __init atmel_late_console_init(void) 2266 { 2267 if (atmel_default_console_device 2268 && !(atmel_console.flags & CON_ENABLED)) 2269 register_console(&atmel_console); 2270 2271 return 0; 2272 } 2273 2274 core_initcall(atmel_late_console_init); 2275 2276 static inline bool atmel_is_console_port(struct uart_port *port) 2277 { 2278 return port->cons && port->cons->index == port->line; 2279 } 2280 2281 #else 2282 #define ATMEL_CONSOLE_DEVICE NULL 2283 2284 static inline bool atmel_is_console_port(struct uart_port *port) 2285 { 2286 return false; 2287 } 2288 #endif 2289 2290 static struct uart_driver atmel_uart = { 2291 .owner = THIS_MODULE, 2292 .driver_name = "atmel_serial", 2293 .dev_name = ATMEL_DEVICENAME, 2294 .major = SERIAL_ATMEL_MAJOR, 2295 .minor = MINOR_START, 2296 .nr = ATMEL_MAX_UART, 2297 .cons = ATMEL_CONSOLE_DEVICE, 2298 }; 2299 2300 #ifdef CONFIG_PM 2301 static bool atmel_serial_clk_will_stop(void) 2302 { 2303 #ifdef CONFIG_ARCH_AT91 2304 return at91_suspend_entering_slow_clock(); 2305 #else 2306 return false; 2307 #endif 2308 } 2309 2310 static int atmel_serial_suspend(struct platform_device *pdev, 2311 pm_message_t state) 2312 { 2313 struct uart_port *port = platform_get_drvdata(pdev); 2314 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2315 2316 if (atmel_is_console_port(port) && console_suspend_enabled) { 2317 /* Drain the TX shifter */ 2318 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) 2319 cpu_relax(); 2320 } 2321 2322 /* we can not wake up if we're running on slow clock */ 2323 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); 2324 if (atmel_serial_clk_will_stop()) 2325 device_set_wakeup_enable(&pdev->dev, 0); 2326 2327 uart_suspend_port(&atmel_uart, port); 2328 2329 return 0; 2330 } 2331 2332 static int atmel_serial_resume(struct platform_device *pdev) 2333 { 2334 struct uart_port *port = platform_get_drvdata(pdev); 2335 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2336 2337 uart_resume_port(&atmel_uart, port); 2338 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); 2339 2340 return 0; 2341 } 2342 #else 2343 #define atmel_serial_suspend NULL 2344 #define atmel_serial_resume NULL 2345 #endif 2346 2347 static int atmel_serial_probe(struct platform_device *pdev) 2348 { 2349 struct atmel_uart_port *port; 2350 struct device_node *np = pdev->dev.of_node; 2351 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2352 void *data; 2353 int ret = -ENODEV; 2354 2355 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); 2356 2357 if (np) 2358 ret = of_alias_get_id(np, "serial"); 2359 else 2360 if (pdata) 2361 ret = pdata->num; 2362 2363 if (ret < 0) 2364 /* port id not found in platform data nor device-tree aliases: 2365 * auto-enumerate it */ 2366 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); 2367 2368 if (ret >= ATMEL_MAX_UART) { 2369 ret = -ENODEV; 2370 goto err; 2371 } 2372 2373 if (test_and_set_bit(ret, atmel_ports_in_use)) { 2374 /* port already in use */ 2375 ret = -EBUSY; 2376 goto err; 2377 } 2378 2379 port = &atmel_ports[ret]; 2380 port->backup_imr = 0; 2381 port->uart.line = ret; 2382 2383 ret = atmel_init_port(port, pdev); 2384 if (ret) 2385 goto err; 2386 2387 if (!atmel_use_pdc_rx(&port->uart)) { 2388 ret = -ENOMEM; 2389 data = kmalloc(sizeof(struct atmel_uart_char) 2390 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); 2391 if (!data) 2392 goto err_alloc_ring; 2393 port->rx_ring.buf = data; 2394 } 2395 2396 ret = uart_add_one_port(&atmel_uart, &port->uart); 2397 if (ret) 2398 goto err_add_port; 2399 2400 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2401 if (atmel_is_console_port(&port->uart) 2402 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { 2403 /* 2404 * The serial core enabled the clock for us, so undo 2405 * the clk_prepare_enable() in atmel_console_setup() 2406 */ 2407 clk_disable_unprepare(port->clk); 2408 } 2409 #endif 2410 2411 device_init_wakeup(&pdev->dev, 1); 2412 platform_set_drvdata(pdev, port); 2413 2414 if (port->rs485.flags & SER_RS485_ENABLED) { 2415 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL); 2416 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN); 2417 } 2418 2419 /* 2420 * Get port name of usart or uart 2421 */ 2422 atmel_get_ip_name(&port->uart); 2423 2424 return 0; 2425 2426 err_add_port: 2427 kfree(port->rx_ring.buf); 2428 port->rx_ring.buf = NULL; 2429 err_alloc_ring: 2430 if (!atmel_is_console_port(&port->uart)) { 2431 clk_put(port->clk); 2432 port->clk = NULL; 2433 } 2434 err: 2435 return ret; 2436 } 2437 2438 static int atmel_serial_remove(struct platform_device *pdev) 2439 { 2440 struct uart_port *port = platform_get_drvdata(pdev); 2441 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2442 int ret = 0; 2443 2444 device_init_wakeup(&pdev->dev, 0); 2445 2446 ret = uart_remove_one_port(&atmel_uart, port); 2447 2448 tasklet_kill(&atmel_port->tasklet); 2449 kfree(atmel_port->rx_ring.buf); 2450 2451 /* "port" is allocated statically, so we shouldn't free it */ 2452 2453 clear_bit(port->line, atmel_ports_in_use); 2454 2455 clk_put(atmel_port->clk); 2456 2457 return ret; 2458 } 2459 2460 static struct platform_driver atmel_serial_driver = { 2461 .probe = atmel_serial_probe, 2462 .remove = atmel_serial_remove, 2463 .suspend = atmel_serial_suspend, 2464 .resume = atmel_serial_resume, 2465 .driver = { 2466 .name = "atmel_usart", 2467 .owner = THIS_MODULE, 2468 .of_match_table = of_match_ptr(atmel_serial_dt_ids), 2469 }, 2470 }; 2471 2472 static int __init atmel_serial_init(void) 2473 { 2474 int ret; 2475 2476 ret = uart_register_driver(&atmel_uart); 2477 if (ret) 2478 return ret; 2479 2480 ret = platform_driver_register(&atmel_serial_driver); 2481 if (ret) 2482 uart_unregister_driver(&atmel_uart); 2483 2484 return ret; 2485 } 2486 2487 static void __exit atmel_serial_exit(void) 2488 { 2489 platform_driver_unregister(&atmel_serial_driver); 2490 uart_unregister_driver(&atmel_uart); 2491 } 2492 2493 module_init(atmel_serial_init); 2494 module_exit(atmel_serial_exit); 2495 2496 MODULE_AUTHOR("Rick Bronson"); 2497 MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); 2498 MODULE_LICENSE("GPL"); 2499 MODULE_ALIAS("platform:atmel_usart"); 2500