1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Atmel AT91 Serial ports 4 * Copyright (C) 2003 Rick Bronson 5 * 6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. 7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 8 * 9 * DMA support added by Chip Coldwell. 10 */ 11 #include <linux/circ_buf.h> 12 #include <linux/tty.h> 13 #include <linux/ioport.h> 14 #include <linux/slab.h> 15 #include <linux/init.h> 16 #include <linux/serial.h> 17 #include <linux/clk.h> 18 #include <linux/console.h> 19 #include <linux/sysrq.h> 20 #include <linux/tty_flip.h> 21 #include <linux/platform_device.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/dmaengine.h> 26 #include <linux/atmel_pdc.h> 27 #include <linux/uaccess.h> 28 #include <linux/platform_data/atmel.h> 29 #include <linux/timer.h> 30 #include <linux/err.h> 31 #include <linux/irq.h> 32 #include <linux/suspend.h> 33 #include <linux/mm.h> 34 #include <linux/io.h> 35 36 #include <asm/div64.h> 37 #include <asm/ioctls.h> 38 39 #define PDC_BUFFER_SIZE 512 40 /* Revisit: We should calculate this based on the actual port settings */ 41 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ 42 43 /* The minium number of data FIFOs should be able to contain */ 44 #define ATMEL_MIN_FIFO_SIZE 8 45 /* 46 * These two offsets are substracted from the RX FIFO size to define the RTS 47 * high and low thresholds 48 */ 49 #define ATMEL_RTS_HIGH_OFFSET 16 50 #define ATMEL_RTS_LOW_OFFSET 20 51 52 #include <linux/serial_core.h> 53 54 #include "serial_mctrl_gpio.h" 55 #include "atmel_serial.h" 56 57 static void atmel_start_rx(struct uart_port *port); 58 static void atmel_stop_rx(struct uart_port *port); 59 60 #ifdef CONFIG_SERIAL_ATMEL_TTYAT 61 62 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we 63 * should coexist with the 8250 driver, such as if we have an external 16C550 64 * UART. */ 65 #define SERIAL_ATMEL_MAJOR 204 66 #define MINOR_START 154 67 #define ATMEL_DEVICENAME "ttyAT" 68 69 #else 70 71 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port 72 * name, but it is legally reserved for the 8250 driver. */ 73 #define SERIAL_ATMEL_MAJOR TTY_MAJOR 74 #define MINOR_START 64 75 #define ATMEL_DEVICENAME "ttyS" 76 77 #endif 78 79 #define ATMEL_ISR_PASS_LIMIT 256 80 81 struct atmel_dma_buffer { 82 unsigned char *buf; 83 dma_addr_t dma_addr; 84 unsigned int dma_size; 85 unsigned int ofs; 86 }; 87 88 struct atmel_uart_char { 89 u16 status; 90 u16 ch; 91 }; 92 93 /* 94 * Be careful, the real size of the ring buffer is 95 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer 96 * can contain up to 1024 characters in PIO mode and up to 4096 characters in 97 * DMA mode. 98 */ 99 #define ATMEL_SERIAL_RINGSIZE 1024 100 101 /* 102 * at91: 6 USARTs and one DBGU port (SAM9260) 103 * samx7: 3 USARTs and 5 UARTs 104 */ 105 #define ATMEL_MAX_UART 8 106 107 /* 108 * We wrap our port structure around the generic uart_port. 109 */ 110 struct atmel_uart_port { 111 struct uart_port uart; /* uart */ 112 struct clk *clk; /* uart clock */ 113 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ 114 u32 backup_imr; /* IMR saved during suspend */ 115 int break_active; /* break being received */ 116 117 bool use_dma_rx; /* enable DMA receiver */ 118 bool use_pdc_rx; /* enable PDC receiver */ 119 short pdc_rx_idx; /* current PDC RX buffer */ 120 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ 121 122 bool use_dma_tx; /* enable DMA transmitter */ 123 bool use_pdc_tx; /* enable PDC transmitter */ 124 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ 125 126 spinlock_t lock_tx; /* port lock */ 127 spinlock_t lock_rx; /* port lock */ 128 struct dma_chan *chan_tx; 129 struct dma_chan *chan_rx; 130 struct dma_async_tx_descriptor *desc_tx; 131 struct dma_async_tx_descriptor *desc_rx; 132 dma_cookie_t cookie_tx; 133 dma_cookie_t cookie_rx; 134 struct scatterlist sg_tx; 135 struct scatterlist sg_rx; 136 struct tasklet_struct tasklet_rx; 137 struct tasklet_struct tasklet_tx; 138 atomic_t tasklet_shutdown; 139 unsigned int irq_status_prev; 140 unsigned int tx_len; 141 142 struct circ_buf rx_ring; 143 144 struct mctrl_gpios *gpios; 145 u32 backup_mode; /* MR saved during iso7816 operations */ 146 u32 backup_brgr; /* BRGR saved during iso7816 operations */ 147 unsigned int tx_done_mask; 148 u32 fifo_size; 149 u32 rts_high; 150 u32 rts_low; 151 bool ms_irq_enabled; 152 u32 rtor; /* address of receiver timeout register if it exists */ 153 bool has_frac_baudrate; 154 bool has_hw_timer; 155 struct timer_list uart_timer; 156 157 bool tx_stopped; 158 bool suspended; 159 unsigned int pending; 160 unsigned int pending_status; 161 spinlock_t lock_suspended; 162 163 bool hd_start_rx; /* can start RX during half-duplex operation */ 164 165 /* ISO7816 */ 166 unsigned int fidi_min; 167 unsigned int fidi_max; 168 169 struct { 170 u32 cr; 171 u32 mr; 172 u32 imr; 173 u32 brgr; 174 u32 rtor; 175 u32 ttgr; 176 u32 fmr; 177 u32 fimr; 178 } cache; 179 180 int (*prepare_rx)(struct uart_port *port); 181 int (*prepare_tx)(struct uart_port *port); 182 void (*schedule_rx)(struct uart_port *port); 183 void (*schedule_tx)(struct uart_port *port); 184 void (*release_rx)(struct uart_port *port); 185 void (*release_tx)(struct uart_port *port); 186 }; 187 188 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; 189 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); 190 191 #if defined(CONFIG_OF) 192 static const struct of_device_id atmel_serial_dt_ids[] = { 193 { .compatible = "atmel,at91rm9200-usart-serial" }, 194 { /* sentinel */ } 195 }; 196 #endif 197 198 static inline struct atmel_uart_port * 199 to_atmel_uart_port(struct uart_port *uart) 200 { 201 return container_of(uart, struct atmel_uart_port, uart); 202 } 203 204 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg) 205 { 206 return __raw_readl(port->membase + reg); 207 } 208 209 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value) 210 { 211 __raw_writel(value, port->membase + reg); 212 } 213 214 static inline u8 atmel_uart_read_char(struct uart_port *port) 215 { 216 return __raw_readb(port->membase + ATMEL_US_RHR); 217 } 218 219 static inline void atmel_uart_write_char(struct uart_port *port, u8 value) 220 { 221 __raw_writeb(value, port->membase + ATMEL_US_THR); 222 } 223 224 static inline int atmel_uart_is_half_duplex(struct uart_port *port) 225 { 226 return ((port->rs485.flags & SER_RS485_ENABLED) && 227 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) || 228 (port->iso7816.flags & SER_ISO7816_ENABLED); 229 } 230 231 #ifdef CONFIG_SERIAL_ATMEL_PDC 232 static bool atmel_use_pdc_rx(struct uart_port *port) 233 { 234 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 235 236 return atmel_port->use_pdc_rx; 237 } 238 239 static bool atmel_use_pdc_tx(struct uart_port *port) 240 { 241 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 242 243 return atmel_port->use_pdc_tx; 244 } 245 #else 246 static bool atmel_use_pdc_rx(struct uart_port *port) 247 { 248 return false; 249 } 250 251 static bool atmel_use_pdc_tx(struct uart_port *port) 252 { 253 return false; 254 } 255 #endif 256 257 static bool atmel_use_dma_tx(struct uart_port *port) 258 { 259 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 260 261 return atmel_port->use_dma_tx; 262 } 263 264 static bool atmel_use_dma_rx(struct uart_port *port) 265 { 266 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 267 268 return atmel_port->use_dma_rx; 269 } 270 271 static bool atmel_use_fifo(struct uart_port *port) 272 { 273 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 274 275 return atmel_port->fifo_size; 276 } 277 278 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port, 279 struct tasklet_struct *t) 280 { 281 if (!atomic_read(&atmel_port->tasklet_shutdown)) 282 tasklet_schedule(t); 283 } 284 285 /* Enable or disable the rs485 support */ 286 static int atmel_config_rs485(struct uart_port *port, struct ktermios *termios, 287 struct serial_rs485 *rs485conf) 288 { 289 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 290 unsigned int mode; 291 292 /* Disable interrupts */ 293 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); 294 295 mode = atmel_uart_readl(port, ATMEL_US_MR); 296 297 /* Resetting serial mode to RS232 (0x0) */ 298 mode &= ~ATMEL_US_USMODE; 299 300 if (rs485conf->flags & SER_RS485_ENABLED) { 301 dev_dbg(port->dev, "Setting UART to RS485\n"); 302 if (rs485conf->flags & SER_RS485_RX_DURING_TX) 303 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 304 else 305 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 306 307 atmel_uart_writel(port, ATMEL_US_TTGR, 308 rs485conf->delay_rts_after_send); 309 mode |= ATMEL_US_USMODE_RS485; 310 } else { 311 dev_dbg(port->dev, "Setting UART to RS232\n"); 312 if (atmel_use_pdc_tx(port)) 313 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 314 ATMEL_US_TXBUFE; 315 else 316 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 317 } 318 atmel_uart_writel(port, ATMEL_US_MR, mode); 319 320 /* Enable interrupts */ 321 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 322 323 return 0; 324 } 325 326 static unsigned int atmel_calc_cd(struct uart_port *port, 327 struct serial_iso7816 *iso7816conf) 328 { 329 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 330 unsigned int cd; 331 u64 mck_rate; 332 333 mck_rate = (u64)clk_get_rate(atmel_port->clk); 334 do_div(mck_rate, iso7816conf->clk); 335 cd = mck_rate; 336 return cd; 337 } 338 339 static unsigned int atmel_calc_fidi(struct uart_port *port, 340 struct serial_iso7816 *iso7816conf) 341 { 342 u64 fidi = 0; 343 344 if (iso7816conf->sc_fi && iso7816conf->sc_di) { 345 fidi = (u64)iso7816conf->sc_fi; 346 do_div(fidi, iso7816conf->sc_di); 347 } 348 return (u32)fidi; 349 } 350 351 /* Enable or disable the iso7816 support */ 352 /* Called with interrupts disabled */ 353 static int atmel_config_iso7816(struct uart_port *port, 354 struct serial_iso7816 *iso7816conf) 355 { 356 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 357 unsigned int mode; 358 unsigned int cd, fidi; 359 int ret = 0; 360 361 /* Disable interrupts */ 362 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); 363 364 mode = atmel_uart_readl(port, ATMEL_US_MR); 365 366 if (iso7816conf->flags & SER_ISO7816_ENABLED) { 367 mode &= ~ATMEL_US_USMODE; 368 369 if (iso7816conf->tg > 255) { 370 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n"); 371 memset(iso7816conf, 0, sizeof(struct serial_iso7816)); 372 ret = -EINVAL; 373 goto err_out; 374 } 375 376 if ((iso7816conf->flags & SER_ISO7816_T_PARAM) 377 == SER_ISO7816_T(0)) { 378 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK; 379 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM) 380 == SER_ISO7816_T(1)) { 381 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK; 382 } else { 383 dev_err(port->dev, "ISO7816: Type not supported\n"); 384 memset(iso7816conf, 0, sizeof(struct serial_iso7816)); 385 ret = -EINVAL; 386 goto err_out; 387 } 388 389 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR); 390 391 /* select mck clock, and output */ 392 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO; 393 /* set parity for normal/inverse mode + max iterations */ 394 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3); 395 396 cd = atmel_calc_cd(port, iso7816conf); 397 fidi = atmel_calc_fidi(port, iso7816conf); 398 if (fidi == 0) { 399 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n"); 400 } else if (fidi < atmel_port->fidi_min 401 || fidi > atmel_port->fidi_max) { 402 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi); 403 memset(iso7816conf, 0, sizeof(struct serial_iso7816)); 404 ret = -EINVAL; 405 goto err_out; 406 } 407 408 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) { 409 /* port not yet in iso7816 mode: store configuration */ 410 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR); 411 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR); 412 } 413 414 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg); 415 atmel_uart_writel(port, ATMEL_US_BRGR, cd); 416 atmel_uart_writel(port, ATMEL_US_FIDI, fidi); 417 418 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN); 419 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION; 420 } else { 421 dev_dbg(port->dev, "Setting UART back to RS232\n"); 422 /* back to last RS232 settings */ 423 mode = atmel_port->backup_mode; 424 memset(iso7816conf, 0, sizeof(struct serial_iso7816)); 425 atmel_uart_writel(port, ATMEL_US_TTGR, 0); 426 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr); 427 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174); 428 429 if (atmel_use_pdc_tx(port)) 430 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 431 ATMEL_US_TXBUFE; 432 else 433 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 434 } 435 436 port->iso7816 = *iso7816conf; 437 438 atmel_uart_writel(port, ATMEL_US_MR, mode); 439 440 err_out: 441 /* Enable interrupts */ 442 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 443 444 return ret; 445 } 446 447 /* 448 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. 449 */ 450 static u_int atmel_tx_empty(struct uart_port *port) 451 { 452 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 453 454 if (atmel_port->tx_stopped) 455 return TIOCSER_TEMT; 456 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ? 457 TIOCSER_TEMT : 458 0; 459 } 460 461 /* 462 * Set state of the modem control output lines 463 */ 464 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) 465 { 466 unsigned int control = 0; 467 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR); 468 unsigned int rts_paused, rts_ready; 469 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 470 471 /* override mode to RS485 if needed, otherwise keep the current mode */ 472 if (port->rs485.flags & SER_RS485_ENABLED) { 473 atmel_uart_writel(port, ATMEL_US_TTGR, 474 port->rs485.delay_rts_after_send); 475 mode &= ~ATMEL_US_USMODE; 476 mode |= ATMEL_US_USMODE_RS485; 477 } 478 479 /* set the RTS line state according to the mode */ 480 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 481 /* force RTS line to high level */ 482 rts_paused = ATMEL_US_RTSEN; 483 484 /* give the control of the RTS line back to the hardware */ 485 rts_ready = ATMEL_US_RTSDIS; 486 } else { 487 /* force RTS line to high level */ 488 rts_paused = ATMEL_US_RTSDIS; 489 490 /* force RTS line to low level */ 491 rts_ready = ATMEL_US_RTSEN; 492 } 493 494 if (mctrl & TIOCM_RTS) 495 control |= rts_ready; 496 else 497 control |= rts_paused; 498 499 if (mctrl & TIOCM_DTR) 500 control |= ATMEL_US_DTREN; 501 else 502 control |= ATMEL_US_DTRDIS; 503 504 atmel_uart_writel(port, ATMEL_US_CR, control); 505 506 mctrl_gpio_set(atmel_port->gpios, mctrl); 507 508 /* Local loopback mode? */ 509 mode &= ~ATMEL_US_CHMODE; 510 if (mctrl & TIOCM_LOOP) 511 mode |= ATMEL_US_CHMODE_LOC_LOOP; 512 else 513 mode |= ATMEL_US_CHMODE_NORMAL; 514 515 atmel_uart_writel(port, ATMEL_US_MR, mode); 516 } 517 518 /* 519 * Get state of the modem control input lines 520 */ 521 static u_int atmel_get_mctrl(struct uart_port *port) 522 { 523 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 524 unsigned int ret = 0, status; 525 526 status = atmel_uart_readl(port, ATMEL_US_CSR); 527 528 /* 529 * The control signals are active low. 530 */ 531 if (!(status & ATMEL_US_DCD)) 532 ret |= TIOCM_CD; 533 if (!(status & ATMEL_US_CTS)) 534 ret |= TIOCM_CTS; 535 if (!(status & ATMEL_US_DSR)) 536 ret |= TIOCM_DSR; 537 if (!(status & ATMEL_US_RI)) 538 ret |= TIOCM_RI; 539 540 return mctrl_gpio_get(atmel_port->gpios, &ret); 541 } 542 543 /* 544 * Stop transmitting. 545 */ 546 static void atmel_stop_tx(struct uart_port *port) 547 { 548 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 549 550 if (atmel_use_pdc_tx(port)) { 551 /* disable PDC transmit */ 552 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 553 } 554 555 /* 556 * Disable the transmitter. 557 * This is mandatory when DMA is used, otherwise the DMA buffer 558 * is fully transmitted. 559 */ 560 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS); 561 atmel_port->tx_stopped = true; 562 563 /* Disable interrupts */ 564 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); 565 566 if (atmel_uart_is_half_duplex(port)) 567 if (!atomic_read(&atmel_port->tasklet_shutdown)) 568 atmel_start_rx(port); 569 570 } 571 572 /* 573 * Start transmitting. 574 */ 575 static void atmel_start_tx(struct uart_port *port) 576 { 577 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 578 579 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR) 580 & ATMEL_PDC_TXTEN)) 581 /* The transmitter is already running. Yes, we 582 really need this.*/ 583 return; 584 585 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port)) 586 if (atmel_uart_is_half_duplex(port)) 587 atmel_stop_rx(port); 588 589 if (atmel_use_pdc_tx(port)) 590 /* re-enable PDC transmit */ 591 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 592 593 /* Enable interrupts */ 594 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 595 596 /* re-enable the transmitter */ 597 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN); 598 atmel_port->tx_stopped = false; 599 } 600 601 /* 602 * start receiving - port is in process of being opened. 603 */ 604 static void atmel_start_rx(struct uart_port *port) 605 { 606 /* reset status and receiver */ 607 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 608 609 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN); 610 611 if (atmel_use_pdc_rx(port)) { 612 /* enable PDC controller */ 613 atmel_uart_writel(port, ATMEL_US_IER, 614 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 615 port->read_status_mask); 616 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 617 } else { 618 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY); 619 } 620 } 621 622 /* 623 * Stop receiving - port is in process of being closed. 624 */ 625 static void atmel_stop_rx(struct uart_port *port) 626 { 627 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS); 628 629 if (atmel_use_pdc_rx(port)) { 630 /* disable PDC receive */ 631 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS); 632 atmel_uart_writel(port, ATMEL_US_IDR, 633 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 634 port->read_status_mask); 635 } else { 636 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY); 637 } 638 } 639 640 /* 641 * Enable modem status interrupts 642 */ 643 static void atmel_enable_ms(struct uart_port *port) 644 { 645 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 646 uint32_t ier = 0; 647 648 /* 649 * Interrupt should not be enabled twice 650 */ 651 if (atmel_port->ms_irq_enabled) 652 return; 653 654 atmel_port->ms_irq_enabled = true; 655 656 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) 657 ier |= ATMEL_US_CTSIC; 658 659 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR)) 660 ier |= ATMEL_US_DSRIC; 661 662 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI)) 663 ier |= ATMEL_US_RIIC; 664 665 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD)) 666 ier |= ATMEL_US_DCDIC; 667 668 atmel_uart_writel(port, ATMEL_US_IER, ier); 669 670 mctrl_gpio_enable_ms(atmel_port->gpios); 671 } 672 673 /* 674 * Disable modem status interrupts 675 */ 676 static void atmel_disable_ms(struct uart_port *port) 677 { 678 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 679 uint32_t idr = 0; 680 681 /* 682 * Interrupt should not be disabled twice 683 */ 684 if (!atmel_port->ms_irq_enabled) 685 return; 686 687 atmel_port->ms_irq_enabled = false; 688 689 mctrl_gpio_disable_ms(atmel_port->gpios); 690 691 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) 692 idr |= ATMEL_US_CTSIC; 693 694 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR)) 695 idr |= ATMEL_US_DSRIC; 696 697 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI)) 698 idr |= ATMEL_US_RIIC; 699 700 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD)) 701 idr |= ATMEL_US_DCDIC; 702 703 atmel_uart_writel(port, ATMEL_US_IDR, idr); 704 } 705 706 /* 707 * Control the transmission of a break signal 708 */ 709 static void atmel_break_ctl(struct uart_port *port, int break_state) 710 { 711 if (break_state != 0) 712 /* start break */ 713 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK); 714 else 715 /* stop break */ 716 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK); 717 } 718 719 /* 720 * Stores the incoming character in the ring buffer 721 */ 722 static void 723 atmel_buffer_rx_char(struct uart_port *port, unsigned int status, 724 unsigned int ch) 725 { 726 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 727 struct circ_buf *ring = &atmel_port->rx_ring; 728 struct atmel_uart_char *c; 729 730 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) 731 /* Buffer overflow, ignore char */ 732 return; 733 734 c = &((struct atmel_uart_char *)ring->buf)[ring->head]; 735 c->status = status; 736 c->ch = ch; 737 738 /* Make sure the character is stored before we update head. */ 739 smp_wmb(); 740 741 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 742 } 743 744 /* 745 * Deal with parity, framing and overrun errors. 746 */ 747 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) 748 { 749 /* clear error */ 750 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 751 752 if (status & ATMEL_US_RXBRK) { 753 /* ignore side-effect */ 754 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 755 port->icount.brk++; 756 } 757 if (status & ATMEL_US_PARE) 758 port->icount.parity++; 759 if (status & ATMEL_US_FRAME) 760 port->icount.frame++; 761 if (status & ATMEL_US_OVRE) 762 port->icount.overrun++; 763 } 764 765 /* 766 * Characters received (called from interrupt handler) 767 */ 768 static void atmel_rx_chars(struct uart_port *port) 769 { 770 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 771 unsigned int status, ch; 772 773 status = atmel_uart_readl(port, ATMEL_US_CSR); 774 while (status & ATMEL_US_RXRDY) { 775 ch = atmel_uart_read_char(port); 776 777 /* 778 * note that the error handling code is 779 * out of the main execution path 780 */ 781 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 782 | ATMEL_US_OVRE | ATMEL_US_RXBRK) 783 || atmel_port->break_active)) { 784 785 /* clear error */ 786 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 787 788 if (status & ATMEL_US_RXBRK 789 && !atmel_port->break_active) { 790 atmel_port->break_active = 1; 791 atmel_uart_writel(port, ATMEL_US_IER, 792 ATMEL_US_RXBRK); 793 } else { 794 /* 795 * This is either the end-of-break 796 * condition or we've received at 797 * least one character without RXBRK 798 * being set. In both cases, the next 799 * RXBRK will indicate start-of-break. 800 */ 801 atmel_uart_writel(port, ATMEL_US_IDR, 802 ATMEL_US_RXBRK); 803 status &= ~ATMEL_US_RXBRK; 804 atmel_port->break_active = 0; 805 } 806 } 807 808 atmel_buffer_rx_char(port, status, ch); 809 status = atmel_uart_readl(port, ATMEL_US_CSR); 810 } 811 812 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx); 813 } 814 815 /* 816 * Transmit characters (called from tasklet with TXRDY interrupt 817 * disabled) 818 */ 819 static void atmel_tx_chars(struct uart_port *port) 820 { 821 struct circ_buf *xmit = &port->state->xmit; 822 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 823 824 if (port->x_char && 825 (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) { 826 atmel_uart_write_char(port, port->x_char); 827 port->icount.tx++; 828 port->x_char = 0; 829 } 830 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 831 return; 832 833 while (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY) { 834 atmel_uart_write_char(port, xmit->buf[xmit->tail]); 835 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 836 port->icount.tx++; 837 if (uart_circ_empty(xmit)) 838 break; 839 } 840 841 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 842 uart_write_wakeup(port); 843 844 if (!uart_circ_empty(xmit)) { 845 /* we still have characters to transmit, so we should continue 846 * transmitting them when TX is ready, regardless of 847 * mode or duplexity 848 */ 849 atmel_port->tx_done_mask |= ATMEL_US_TXRDY; 850 851 /* Enable interrupts */ 852 atmel_uart_writel(port, ATMEL_US_IER, 853 atmel_port->tx_done_mask); 854 } else { 855 if (atmel_uart_is_half_duplex(port)) 856 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY; 857 } 858 } 859 860 static void atmel_complete_tx_dma(void *arg) 861 { 862 struct atmel_uart_port *atmel_port = arg; 863 struct uart_port *port = &atmel_port->uart; 864 struct circ_buf *xmit = &port->state->xmit; 865 struct dma_chan *chan = atmel_port->chan_tx; 866 unsigned long flags; 867 868 spin_lock_irqsave(&port->lock, flags); 869 870 if (chan) 871 dmaengine_terminate_all(chan); 872 xmit->tail += atmel_port->tx_len; 873 xmit->tail &= UART_XMIT_SIZE - 1; 874 875 port->icount.tx += atmel_port->tx_len; 876 877 spin_lock_irq(&atmel_port->lock_tx); 878 async_tx_ack(atmel_port->desc_tx); 879 atmel_port->cookie_tx = -EINVAL; 880 atmel_port->desc_tx = NULL; 881 spin_unlock_irq(&atmel_port->lock_tx); 882 883 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 884 uart_write_wakeup(port); 885 886 /* 887 * xmit is a circular buffer so, if we have just send data from 888 * xmit->tail to the end of xmit->buf, now we have to transmit the 889 * remaining data from the beginning of xmit->buf to xmit->head. 890 */ 891 if (!uart_circ_empty(xmit)) 892 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx); 893 else if (atmel_uart_is_half_duplex(port)) { 894 /* 895 * DMA done, re-enable TXEMPTY and signal that we can stop 896 * TX and start RX for RS485 897 */ 898 atmel_port->hd_start_rx = true; 899 atmel_uart_writel(port, ATMEL_US_IER, 900 atmel_port->tx_done_mask); 901 } 902 903 spin_unlock_irqrestore(&port->lock, flags); 904 } 905 906 static void atmel_release_tx_dma(struct uart_port *port) 907 { 908 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 909 struct dma_chan *chan = atmel_port->chan_tx; 910 911 if (chan) { 912 dmaengine_terminate_all(chan); 913 dma_release_channel(chan); 914 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, 915 DMA_TO_DEVICE); 916 } 917 918 atmel_port->desc_tx = NULL; 919 atmel_port->chan_tx = NULL; 920 atmel_port->cookie_tx = -EINVAL; 921 } 922 923 /* 924 * Called from tasklet with TXRDY interrupt is disabled. 925 */ 926 static void atmel_tx_dma(struct uart_port *port) 927 { 928 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 929 struct circ_buf *xmit = &port->state->xmit; 930 struct dma_chan *chan = atmel_port->chan_tx; 931 struct dma_async_tx_descriptor *desc; 932 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx; 933 unsigned int tx_len, part1_len, part2_len, sg_len; 934 dma_addr_t phys_addr; 935 936 /* Make sure we have an idle channel */ 937 if (atmel_port->desc_tx != NULL) 938 return; 939 940 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 941 /* 942 * DMA is idle now. 943 * Port xmit buffer is already mapped, 944 * and it is one page... Just adjust 945 * offsets and lengths. Since it is a circular buffer, 946 * we have to transmit till the end, and then the rest. 947 * Take the port lock to get a 948 * consistent xmit buffer state. 949 */ 950 tx_len = CIRC_CNT_TO_END(xmit->head, 951 xmit->tail, 952 UART_XMIT_SIZE); 953 954 if (atmel_port->fifo_size) { 955 /* multi data mode */ 956 part1_len = (tx_len & ~0x3); /* DWORD access */ 957 part2_len = (tx_len & 0x3); /* BYTE access */ 958 } else { 959 /* single data (legacy) mode */ 960 part1_len = 0; 961 part2_len = tx_len; /* BYTE access only */ 962 } 963 964 sg_init_table(sgl, 2); 965 sg_len = 0; 966 phys_addr = sg_dma_address(sg_tx) + xmit->tail; 967 if (part1_len) { 968 sg = &sgl[sg_len++]; 969 sg_dma_address(sg) = phys_addr; 970 sg_dma_len(sg) = part1_len; 971 972 phys_addr += part1_len; 973 } 974 975 if (part2_len) { 976 sg = &sgl[sg_len++]; 977 sg_dma_address(sg) = phys_addr; 978 sg_dma_len(sg) = part2_len; 979 } 980 981 /* 982 * save tx_len so atmel_complete_tx_dma() will increase 983 * xmit->tail correctly 984 */ 985 atmel_port->tx_len = tx_len; 986 987 desc = dmaengine_prep_slave_sg(chan, 988 sgl, 989 sg_len, 990 DMA_MEM_TO_DEV, 991 DMA_PREP_INTERRUPT | 992 DMA_CTRL_ACK); 993 if (!desc) { 994 dev_err(port->dev, "Failed to send via dma!\n"); 995 return; 996 } 997 998 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE); 999 1000 atmel_port->desc_tx = desc; 1001 desc->callback = atmel_complete_tx_dma; 1002 desc->callback_param = atmel_port; 1003 atmel_port->cookie_tx = dmaengine_submit(desc); 1004 if (dma_submit_error(atmel_port->cookie_tx)) { 1005 dev_err(port->dev, "dma_submit_error %d\n", 1006 atmel_port->cookie_tx); 1007 return; 1008 } 1009 1010 dma_async_issue_pending(chan); 1011 } 1012 1013 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1014 uart_write_wakeup(port); 1015 } 1016 1017 static int atmel_prepare_tx_dma(struct uart_port *port) 1018 { 1019 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1020 struct device *mfd_dev = port->dev->parent; 1021 dma_cap_mask_t mask; 1022 struct dma_slave_config config; 1023 int ret, nent; 1024 1025 dma_cap_zero(mask); 1026 dma_cap_set(DMA_SLAVE, mask); 1027 1028 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx"); 1029 if (atmel_port->chan_tx == NULL) 1030 goto chan_err; 1031 dev_info(port->dev, "using %s for tx DMA transfers\n", 1032 dma_chan_name(atmel_port->chan_tx)); 1033 1034 spin_lock_init(&atmel_port->lock_tx); 1035 sg_init_table(&atmel_port->sg_tx, 1); 1036 /* UART circular tx buffer is an aligned page. */ 1037 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf)); 1038 sg_set_page(&atmel_port->sg_tx, 1039 virt_to_page(port->state->xmit.buf), 1040 UART_XMIT_SIZE, 1041 offset_in_page(port->state->xmit.buf)); 1042 nent = dma_map_sg(port->dev, 1043 &atmel_port->sg_tx, 1044 1, 1045 DMA_TO_DEVICE); 1046 1047 if (!nent) { 1048 dev_dbg(port->dev, "need to release resource of dma\n"); 1049 goto chan_err; 1050 } else { 1051 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, 1052 sg_dma_len(&atmel_port->sg_tx), 1053 port->state->xmit.buf, 1054 &sg_dma_address(&atmel_port->sg_tx)); 1055 } 1056 1057 /* Configure the slave DMA */ 1058 memset(&config, 0, sizeof(config)); 1059 config.direction = DMA_MEM_TO_DEV; 1060 config.dst_addr_width = (atmel_port->fifo_size) ? 1061 DMA_SLAVE_BUSWIDTH_4_BYTES : 1062 DMA_SLAVE_BUSWIDTH_1_BYTE; 1063 config.dst_addr = port->mapbase + ATMEL_US_THR; 1064 config.dst_maxburst = 1; 1065 1066 ret = dmaengine_slave_config(atmel_port->chan_tx, 1067 &config); 1068 if (ret) { 1069 dev_err(port->dev, "DMA tx slave configuration failed\n"); 1070 goto chan_err; 1071 } 1072 1073 return 0; 1074 1075 chan_err: 1076 dev_err(port->dev, "TX channel not available, switch to pio\n"); 1077 atmel_port->use_dma_tx = false; 1078 if (atmel_port->chan_tx) 1079 atmel_release_tx_dma(port); 1080 return -EINVAL; 1081 } 1082 1083 static void atmel_complete_rx_dma(void *arg) 1084 { 1085 struct uart_port *port = arg; 1086 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1087 1088 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx); 1089 } 1090 1091 static void atmel_release_rx_dma(struct uart_port *port) 1092 { 1093 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1094 struct dma_chan *chan = atmel_port->chan_rx; 1095 1096 if (chan) { 1097 dmaengine_terminate_all(chan); 1098 dma_release_channel(chan); 1099 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, 1100 DMA_FROM_DEVICE); 1101 } 1102 1103 atmel_port->desc_rx = NULL; 1104 atmel_port->chan_rx = NULL; 1105 atmel_port->cookie_rx = -EINVAL; 1106 } 1107 1108 static void atmel_rx_from_dma(struct uart_port *port) 1109 { 1110 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1111 struct tty_port *tport = &port->state->port; 1112 struct circ_buf *ring = &atmel_port->rx_ring; 1113 struct dma_chan *chan = atmel_port->chan_rx; 1114 struct dma_tx_state state; 1115 enum dma_status dmastat; 1116 size_t count; 1117 1118 1119 /* Reset the UART timeout early so that we don't miss one */ 1120 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1121 dmastat = dmaengine_tx_status(chan, 1122 atmel_port->cookie_rx, 1123 &state); 1124 /* Restart a new tasklet if DMA status is error */ 1125 if (dmastat == DMA_ERROR) { 1126 dev_dbg(port->dev, "Get residue error, restart tasklet\n"); 1127 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT); 1128 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx); 1129 return; 1130 } 1131 1132 /* CPU claims ownership of RX DMA buffer */ 1133 dma_sync_sg_for_cpu(port->dev, 1134 &atmel_port->sg_rx, 1135 1, 1136 DMA_FROM_DEVICE); 1137 1138 /* 1139 * ring->head points to the end of data already written by the DMA. 1140 * ring->tail points to the beginning of data to be read by the 1141 * framework. 1142 * The current transfer size should not be larger than the dma buffer 1143 * length. 1144 */ 1145 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue; 1146 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx)); 1147 /* 1148 * At this point ring->head may point to the first byte right after the 1149 * last byte of the dma buffer: 1150 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx) 1151 * 1152 * However ring->tail must always points inside the dma buffer: 1153 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1 1154 * 1155 * Since we use a ring buffer, we have to handle the case 1156 * where head is lower than tail. In such a case, we first read from 1157 * tail to the end of the buffer then reset tail. 1158 */ 1159 if (ring->head < ring->tail) { 1160 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail; 1161 1162 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 1163 ring->tail = 0; 1164 port->icount.rx += count; 1165 } 1166 1167 /* Finally we read data from tail to head */ 1168 if (ring->tail < ring->head) { 1169 count = ring->head - ring->tail; 1170 1171 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 1172 /* Wrap ring->head if needed */ 1173 if (ring->head >= sg_dma_len(&atmel_port->sg_rx)) 1174 ring->head = 0; 1175 ring->tail = ring->head; 1176 port->icount.rx += count; 1177 } 1178 1179 /* USART retreives ownership of RX DMA buffer */ 1180 dma_sync_sg_for_device(port->dev, 1181 &atmel_port->sg_rx, 1182 1, 1183 DMA_FROM_DEVICE); 1184 1185 tty_flip_buffer_push(tport); 1186 1187 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT); 1188 } 1189 1190 static int atmel_prepare_rx_dma(struct uart_port *port) 1191 { 1192 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1193 struct device *mfd_dev = port->dev->parent; 1194 struct dma_async_tx_descriptor *desc; 1195 dma_cap_mask_t mask; 1196 struct dma_slave_config config; 1197 struct circ_buf *ring; 1198 int ret, nent; 1199 1200 ring = &atmel_port->rx_ring; 1201 1202 dma_cap_zero(mask); 1203 dma_cap_set(DMA_CYCLIC, mask); 1204 1205 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx"); 1206 if (atmel_port->chan_rx == NULL) 1207 goto chan_err; 1208 dev_info(port->dev, "using %s for rx DMA transfers\n", 1209 dma_chan_name(atmel_port->chan_rx)); 1210 1211 spin_lock_init(&atmel_port->lock_rx); 1212 sg_init_table(&atmel_port->sg_rx, 1); 1213 /* UART circular rx buffer is an aligned page. */ 1214 BUG_ON(!PAGE_ALIGNED(ring->buf)); 1215 sg_set_page(&atmel_port->sg_rx, 1216 virt_to_page(ring->buf), 1217 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE, 1218 offset_in_page(ring->buf)); 1219 nent = dma_map_sg(port->dev, 1220 &atmel_port->sg_rx, 1221 1, 1222 DMA_FROM_DEVICE); 1223 1224 if (!nent) { 1225 dev_dbg(port->dev, "need to release resource of dma\n"); 1226 goto chan_err; 1227 } else { 1228 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, 1229 sg_dma_len(&atmel_port->sg_rx), 1230 ring->buf, 1231 &sg_dma_address(&atmel_port->sg_rx)); 1232 } 1233 1234 /* Configure the slave DMA */ 1235 memset(&config, 0, sizeof(config)); 1236 config.direction = DMA_DEV_TO_MEM; 1237 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1238 config.src_addr = port->mapbase + ATMEL_US_RHR; 1239 config.src_maxburst = 1; 1240 1241 ret = dmaengine_slave_config(atmel_port->chan_rx, 1242 &config); 1243 if (ret) { 1244 dev_err(port->dev, "DMA rx slave configuration failed\n"); 1245 goto chan_err; 1246 } 1247 /* 1248 * Prepare a cyclic dma transfer, assign 2 descriptors, 1249 * each one is half ring buffer size 1250 */ 1251 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, 1252 sg_dma_address(&atmel_port->sg_rx), 1253 sg_dma_len(&atmel_port->sg_rx), 1254 sg_dma_len(&atmel_port->sg_rx)/2, 1255 DMA_DEV_TO_MEM, 1256 DMA_PREP_INTERRUPT); 1257 if (!desc) { 1258 dev_err(port->dev, "Preparing DMA cyclic failed\n"); 1259 goto chan_err; 1260 } 1261 desc->callback = atmel_complete_rx_dma; 1262 desc->callback_param = port; 1263 atmel_port->desc_rx = desc; 1264 atmel_port->cookie_rx = dmaengine_submit(desc); 1265 if (dma_submit_error(atmel_port->cookie_rx)) { 1266 dev_err(port->dev, "dma_submit_error %d\n", 1267 atmel_port->cookie_rx); 1268 goto chan_err; 1269 } 1270 1271 dma_async_issue_pending(atmel_port->chan_rx); 1272 1273 return 0; 1274 1275 chan_err: 1276 dev_err(port->dev, "RX channel not available, switch to pio\n"); 1277 atmel_port->use_dma_rx = false; 1278 if (atmel_port->chan_rx) 1279 atmel_release_rx_dma(port); 1280 return -EINVAL; 1281 } 1282 1283 static void atmel_uart_timer_callback(struct timer_list *t) 1284 { 1285 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t, 1286 uart_timer); 1287 struct uart_port *port = &atmel_port->uart; 1288 1289 if (!atomic_read(&atmel_port->tasklet_shutdown)) { 1290 tasklet_schedule(&atmel_port->tasklet_rx); 1291 mod_timer(&atmel_port->uart_timer, 1292 jiffies + uart_poll_timeout(port)); 1293 } 1294 } 1295 1296 /* 1297 * receive interrupt handler. 1298 */ 1299 static void 1300 atmel_handle_receive(struct uart_port *port, unsigned int pending) 1301 { 1302 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1303 1304 if (atmel_use_pdc_rx(port)) { 1305 /* 1306 * PDC receive. Just schedule the tasklet and let it 1307 * figure out the details. 1308 * 1309 * TODO: We're not handling error flags correctly at 1310 * the moment. 1311 */ 1312 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { 1313 atmel_uart_writel(port, ATMEL_US_IDR, 1314 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)); 1315 atmel_tasklet_schedule(atmel_port, 1316 &atmel_port->tasklet_rx); 1317 } 1318 1319 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | 1320 ATMEL_US_FRAME | ATMEL_US_PARE)) 1321 atmel_pdc_rxerr(port, pending); 1322 } 1323 1324 if (atmel_use_dma_rx(port)) { 1325 if (pending & ATMEL_US_TIMEOUT) { 1326 atmel_uart_writel(port, ATMEL_US_IDR, 1327 ATMEL_US_TIMEOUT); 1328 atmel_tasklet_schedule(atmel_port, 1329 &atmel_port->tasklet_rx); 1330 } 1331 } 1332 1333 /* Interrupt receive */ 1334 if (pending & ATMEL_US_RXRDY) 1335 atmel_rx_chars(port); 1336 else if (pending & ATMEL_US_RXBRK) { 1337 /* 1338 * End of break detected. If it came along with a 1339 * character, atmel_rx_chars will handle it. 1340 */ 1341 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 1342 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK); 1343 atmel_port->break_active = 0; 1344 } 1345 } 1346 1347 /* 1348 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) 1349 */ 1350 static void 1351 atmel_handle_transmit(struct uart_port *port, unsigned int pending) 1352 { 1353 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1354 1355 if (pending & atmel_port->tx_done_mask) { 1356 atmel_uart_writel(port, ATMEL_US_IDR, 1357 atmel_port->tx_done_mask); 1358 1359 /* Start RX if flag was set and FIFO is empty */ 1360 if (atmel_port->hd_start_rx) { 1361 if (!(atmel_uart_readl(port, ATMEL_US_CSR) 1362 & ATMEL_US_TXEMPTY)) 1363 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n"); 1364 1365 atmel_port->hd_start_rx = false; 1366 atmel_start_rx(port); 1367 } 1368 1369 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx); 1370 } 1371 } 1372 1373 /* 1374 * status flags interrupt handler. 1375 */ 1376 static void 1377 atmel_handle_status(struct uart_port *port, unsigned int pending, 1378 unsigned int status) 1379 { 1380 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1381 unsigned int status_change; 1382 1383 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC 1384 | ATMEL_US_CTSIC)) { 1385 status_change = status ^ atmel_port->irq_status_prev; 1386 atmel_port->irq_status_prev = status; 1387 1388 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR 1389 | ATMEL_US_DCD | ATMEL_US_CTS)) { 1390 /* TODO: All reads to CSR will clear these interrupts! */ 1391 if (status_change & ATMEL_US_RI) 1392 port->icount.rng++; 1393 if (status_change & ATMEL_US_DSR) 1394 port->icount.dsr++; 1395 if (status_change & ATMEL_US_DCD) 1396 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); 1397 if (status_change & ATMEL_US_CTS) 1398 uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); 1399 1400 wake_up_interruptible(&port->state->port.delta_msr_wait); 1401 } 1402 } 1403 1404 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION)) 1405 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending); 1406 } 1407 1408 /* 1409 * Interrupt handler 1410 */ 1411 static irqreturn_t atmel_interrupt(int irq, void *dev_id) 1412 { 1413 struct uart_port *port = dev_id; 1414 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1415 unsigned int status, pending, mask, pass_counter = 0; 1416 1417 spin_lock(&atmel_port->lock_suspended); 1418 1419 do { 1420 status = atmel_uart_readl(port, ATMEL_US_CSR); 1421 mask = atmel_uart_readl(port, ATMEL_US_IMR); 1422 pending = status & mask; 1423 if (!pending) 1424 break; 1425 1426 if (atmel_port->suspended) { 1427 atmel_port->pending |= pending; 1428 atmel_port->pending_status = status; 1429 atmel_uart_writel(port, ATMEL_US_IDR, mask); 1430 pm_system_wakeup(); 1431 break; 1432 } 1433 1434 atmel_handle_receive(port, pending); 1435 atmel_handle_status(port, pending, status); 1436 atmel_handle_transmit(port, pending); 1437 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); 1438 1439 spin_unlock(&atmel_port->lock_suspended); 1440 1441 return pass_counter ? IRQ_HANDLED : IRQ_NONE; 1442 } 1443 1444 static void atmel_release_tx_pdc(struct uart_port *port) 1445 { 1446 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1447 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1448 1449 dma_unmap_single(port->dev, 1450 pdc->dma_addr, 1451 pdc->dma_size, 1452 DMA_TO_DEVICE); 1453 } 1454 1455 /* 1456 * Called from tasklet with ENDTX and TXBUFE interrupts disabled. 1457 */ 1458 static void atmel_tx_pdc(struct uart_port *port) 1459 { 1460 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1461 struct circ_buf *xmit = &port->state->xmit; 1462 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1463 int count; 1464 1465 /* nothing left to transmit? */ 1466 if (atmel_uart_readl(port, ATMEL_PDC_TCR)) 1467 return; 1468 1469 xmit->tail += pdc->ofs; 1470 xmit->tail &= UART_XMIT_SIZE - 1; 1471 1472 port->icount.tx += pdc->ofs; 1473 pdc->ofs = 0; 1474 1475 /* more to transmit - setup next transfer */ 1476 1477 /* disable PDC transmit */ 1478 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 1479 1480 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 1481 dma_sync_single_for_device(port->dev, 1482 pdc->dma_addr, 1483 pdc->dma_size, 1484 DMA_TO_DEVICE); 1485 1486 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1487 pdc->ofs = count; 1488 1489 atmel_uart_writel(port, ATMEL_PDC_TPR, 1490 pdc->dma_addr + xmit->tail); 1491 atmel_uart_writel(port, ATMEL_PDC_TCR, count); 1492 /* re-enable PDC transmit */ 1493 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 1494 /* Enable interrupts */ 1495 atmel_uart_writel(port, ATMEL_US_IER, 1496 atmel_port->tx_done_mask); 1497 } else { 1498 if (atmel_uart_is_half_duplex(port)) { 1499 /* DMA done, stop TX, start RX for RS485 */ 1500 atmel_start_rx(port); 1501 } 1502 } 1503 1504 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1505 uart_write_wakeup(port); 1506 } 1507 1508 static int atmel_prepare_tx_pdc(struct uart_port *port) 1509 { 1510 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1511 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1512 struct circ_buf *xmit = &port->state->xmit; 1513 1514 pdc->buf = xmit->buf; 1515 pdc->dma_addr = dma_map_single(port->dev, 1516 pdc->buf, 1517 UART_XMIT_SIZE, 1518 DMA_TO_DEVICE); 1519 pdc->dma_size = UART_XMIT_SIZE; 1520 pdc->ofs = 0; 1521 1522 return 0; 1523 } 1524 1525 static void atmel_rx_from_ring(struct uart_port *port) 1526 { 1527 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1528 struct circ_buf *ring = &atmel_port->rx_ring; 1529 unsigned int flg; 1530 unsigned int status; 1531 1532 while (ring->head != ring->tail) { 1533 struct atmel_uart_char c; 1534 1535 /* Make sure c is loaded after head. */ 1536 smp_rmb(); 1537 1538 c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; 1539 1540 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 1541 1542 port->icount.rx++; 1543 status = c.status; 1544 flg = TTY_NORMAL; 1545 1546 /* 1547 * note that the error handling code is 1548 * out of the main execution path 1549 */ 1550 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 1551 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { 1552 if (status & ATMEL_US_RXBRK) { 1553 /* ignore side-effect */ 1554 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 1555 1556 port->icount.brk++; 1557 if (uart_handle_break(port)) 1558 continue; 1559 } 1560 if (status & ATMEL_US_PARE) 1561 port->icount.parity++; 1562 if (status & ATMEL_US_FRAME) 1563 port->icount.frame++; 1564 if (status & ATMEL_US_OVRE) 1565 port->icount.overrun++; 1566 1567 status &= port->read_status_mask; 1568 1569 if (status & ATMEL_US_RXBRK) 1570 flg = TTY_BREAK; 1571 else if (status & ATMEL_US_PARE) 1572 flg = TTY_PARITY; 1573 else if (status & ATMEL_US_FRAME) 1574 flg = TTY_FRAME; 1575 } 1576 1577 1578 if (uart_handle_sysrq_char(port, c.ch)) 1579 continue; 1580 1581 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); 1582 } 1583 1584 tty_flip_buffer_push(&port->state->port); 1585 } 1586 1587 static void atmel_release_rx_pdc(struct uart_port *port) 1588 { 1589 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1590 int i; 1591 1592 for (i = 0; i < 2; i++) { 1593 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1594 1595 dma_unmap_single(port->dev, 1596 pdc->dma_addr, 1597 pdc->dma_size, 1598 DMA_FROM_DEVICE); 1599 kfree(pdc->buf); 1600 } 1601 } 1602 1603 static void atmel_rx_from_pdc(struct uart_port *port) 1604 { 1605 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1606 struct tty_port *tport = &port->state->port; 1607 struct atmel_dma_buffer *pdc; 1608 int rx_idx = atmel_port->pdc_rx_idx; 1609 unsigned int head; 1610 unsigned int tail; 1611 unsigned int count; 1612 1613 do { 1614 /* Reset the UART timeout early so that we don't miss one */ 1615 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1616 1617 pdc = &atmel_port->pdc_rx[rx_idx]; 1618 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr; 1619 tail = pdc->ofs; 1620 1621 /* If the PDC has switched buffers, RPR won't contain 1622 * any address within the current buffer. Since head 1623 * is unsigned, we just need a one-way comparison to 1624 * find out. 1625 * 1626 * In this case, we just need to consume the entire 1627 * buffer and resubmit it for DMA. This will clear the 1628 * ENDRX bit as well, so that we can safely re-enable 1629 * all interrupts below. 1630 */ 1631 head = min(head, pdc->dma_size); 1632 1633 if (likely(head != tail)) { 1634 dma_sync_single_for_cpu(port->dev, pdc->dma_addr, 1635 pdc->dma_size, DMA_FROM_DEVICE); 1636 1637 /* 1638 * head will only wrap around when we recycle 1639 * the DMA buffer, and when that happens, we 1640 * explicitly set tail to 0. So head will 1641 * always be greater than tail. 1642 */ 1643 count = head - tail; 1644 1645 tty_insert_flip_string(tport, pdc->buf + pdc->ofs, 1646 count); 1647 1648 dma_sync_single_for_device(port->dev, pdc->dma_addr, 1649 pdc->dma_size, DMA_FROM_DEVICE); 1650 1651 port->icount.rx += count; 1652 pdc->ofs = head; 1653 } 1654 1655 /* 1656 * If the current buffer is full, we need to check if 1657 * the next one contains any additional data. 1658 */ 1659 if (head >= pdc->dma_size) { 1660 pdc->ofs = 0; 1661 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr); 1662 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size); 1663 1664 rx_idx = !rx_idx; 1665 atmel_port->pdc_rx_idx = rx_idx; 1666 } 1667 } while (head >= pdc->dma_size); 1668 1669 tty_flip_buffer_push(tport); 1670 1671 atmel_uart_writel(port, ATMEL_US_IER, 1672 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1673 } 1674 1675 static int atmel_prepare_rx_pdc(struct uart_port *port) 1676 { 1677 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1678 int i; 1679 1680 for (i = 0; i < 2; i++) { 1681 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1682 1683 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); 1684 if (pdc->buf == NULL) { 1685 if (i != 0) { 1686 dma_unmap_single(port->dev, 1687 atmel_port->pdc_rx[0].dma_addr, 1688 PDC_BUFFER_SIZE, 1689 DMA_FROM_DEVICE); 1690 kfree(atmel_port->pdc_rx[0].buf); 1691 } 1692 atmel_port->use_pdc_rx = false; 1693 return -ENOMEM; 1694 } 1695 pdc->dma_addr = dma_map_single(port->dev, 1696 pdc->buf, 1697 PDC_BUFFER_SIZE, 1698 DMA_FROM_DEVICE); 1699 pdc->dma_size = PDC_BUFFER_SIZE; 1700 pdc->ofs = 0; 1701 } 1702 1703 atmel_port->pdc_rx_idx = 0; 1704 1705 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr); 1706 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE); 1707 1708 atmel_uart_writel(port, ATMEL_PDC_RNPR, 1709 atmel_port->pdc_rx[1].dma_addr); 1710 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE); 1711 1712 return 0; 1713 } 1714 1715 /* 1716 * tasklet handling tty stuff outside the interrupt handler. 1717 */ 1718 static void atmel_tasklet_rx_func(struct tasklet_struct *t) 1719 { 1720 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t, 1721 tasklet_rx); 1722 struct uart_port *port = &atmel_port->uart; 1723 1724 /* The interrupt handler does not take the lock */ 1725 spin_lock(&port->lock); 1726 atmel_port->schedule_rx(port); 1727 spin_unlock(&port->lock); 1728 } 1729 1730 static void atmel_tasklet_tx_func(struct tasklet_struct *t) 1731 { 1732 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t, 1733 tasklet_tx); 1734 struct uart_port *port = &atmel_port->uart; 1735 1736 /* The interrupt handler does not take the lock */ 1737 spin_lock(&port->lock); 1738 atmel_port->schedule_tx(port); 1739 spin_unlock(&port->lock); 1740 } 1741 1742 static void atmel_init_property(struct atmel_uart_port *atmel_port, 1743 struct platform_device *pdev) 1744 { 1745 struct device_node *np = pdev->dev.of_node; 1746 1747 /* DMA/PDC usage specification */ 1748 if (of_property_read_bool(np, "atmel,use-dma-rx")) { 1749 if (of_property_read_bool(np, "dmas")) { 1750 atmel_port->use_dma_rx = true; 1751 atmel_port->use_pdc_rx = false; 1752 } else { 1753 atmel_port->use_dma_rx = false; 1754 atmel_port->use_pdc_rx = true; 1755 } 1756 } else { 1757 atmel_port->use_dma_rx = false; 1758 atmel_port->use_pdc_rx = false; 1759 } 1760 1761 if (of_property_read_bool(np, "atmel,use-dma-tx")) { 1762 if (of_property_read_bool(np, "dmas")) { 1763 atmel_port->use_dma_tx = true; 1764 atmel_port->use_pdc_tx = false; 1765 } else { 1766 atmel_port->use_dma_tx = false; 1767 atmel_port->use_pdc_tx = true; 1768 } 1769 } else { 1770 atmel_port->use_dma_tx = false; 1771 atmel_port->use_pdc_tx = false; 1772 } 1773 } 1774 1775 static void atmel_set_ops(struct uart_port *port) 1776 { 1777 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1778 1779 if (atmel_use_dma_rx(port)) { 1780 atmel_port->prepare_rx = &atmel_prepare_rx_dma; 1781 atmel_port->schedule_rx = &atmel_rx_from_dma; 1782 atmel_port->release_rx = &atmel_release_rx_dma; 1783 } else if (atmel_use_pdc_rx(port)) { 1784 atmel_port->prepare_rx = &atmel_prepare_rx_pdc; 1785 atmel_port->schedule_rx = &atmel_rx_from_pdc; 1786 atmel_port->release_rx = &atmel_release_rx_pdc; 1787 } else { 1788 atmel_port->prepare_rx = NULL; 1789 atmel_port->schedule_rx = &atmel_rx_from_ring; 1790 atmel_port->release_rx = NULL; 1791 } 1792 1793 if (atmel_use_dma_tx(port)) { 1794 atmel_port->prepare_tx = &atmel_prepare_tx_dma; 1795 atmel_port->schedule_tx = &atmel_tx_dma; 1796 atmel_port->release_tx = &atmel_release_tx_dma; 1797 } else if (atmel_use_pdc_tx(port)) { 1798 atmel_port->prepare_tx = &atmel_prepare_tx_pdc; 1799 atmel_port->schedule_tx = &atmel_tx_pdc; 1800 atmel_port->release_tx = &atmel_release_tx_pdc; 1801 } else { 1802 atmel_port->prepare_tx = NULL; 1803 atmel_port->schedule_tx = &atmel_tx_chars; 1804 atmel_port->release_tx = NULL; 1805 } 1806 } 1807 1808 /* 1809 * Get ip name usart or uart 1810 */ 1811 static void atmel_get_ip_name(struct uart_port *port) 1812 { 1813 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1814 int name = atmel_uart_readl(port, ATMEL_US_NAME); 1815 u32 version; 1816 u32 usart, dbgu_uart, new_uart; 1817 /* ASCII decoding for IP version */ 1818 usart = 0x55534152; /* USAR(T) */ 1819 dbgu_uart = 0x44424755; /* DBGU */ 1820 new_uart = 0x55415254; /* UART */ 1821 1822 /* 1823 * Only USART devices from at91sam9260 SOC implement fractional 1824 * baudrate. It is available for all asynchronous modes, with the 1825 * following restriction: the sampling clock's duty cycle is not 1826 * constant. 1827 */ 1828 atmel_port->has_frac_baudrate = false; 1829 atmel_port->has_hw_timer = false; 1830 1831 if (name == new_uart) { 1832 dev_dbg(port->dev, "Uart with hw timer"); 1833 atmel_port->has_hw_timer = true; 1834 atmel_port->rtor = ATMEL_UA_RTOR; 1835 } else if (name == usart) { 1836 dev_dbg(port->dev, "Usart\n"); 1837 atmel_port->has_frac_baudrate = true; 1838 atmel_port->has_hw_timer = true; 1839 atmel_port->rtor = ATMEL_US_RTOR; 1840 version = atmel_uart_readl(port, ATMEL_US_VERSION); 1841 switch (version) { 1842 case 0x814: /* sama5d2 */ 1843 fallthrough; 1844 case 0x701: /* sama5d4 */ 1845 atmel_port->fidi_min = 3; 1846 atmel_port->fidi_max = 65535; 1847 break; 1848 case 0x502: /* sam9x5, sama5d3 */ 1849 atmel_port->fidi_min = 3; 1850 atmel_port->fidi_max = 2047; 1851 break; 1852 default: 1853 atmel_port->fidi_min = 1; 1854 atmel_port->fidi_max = 2047; 1855 } 1856 } else if (name == dbgu_uart) { 1857 dev_dbg(port->dev, "Dbgu or uart without hw timer\n"); 1858 } else { 1859 /* fallback for older SoCs: use version field */ 1860 version = atmel_uart_readl(port, ATMEL_US_VERSION); 1861 switch (version) { 1862 case 0x302: 1863 case 0x10213: 1864 case 0x10302: 1865 dev_dbg(port->dev, "This version is usart\n"); 1866 atmel_port->has_frac_baudrate = true; 1867 atmel_port->has_hw_timer = true; 1868 atmel_port->rtor = ATMEL_US_RTOR; 1869 break; 1870 case 0x203: 1871 case 0x10202: 1872 dev_dbg(port->dev, "This version is uart\n"); 1873 break; 1874 default: 1875 dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); 1876 } 1877 } 1878 } 1879 1880 /* 1881 * Perform initialization and enable port for reception 1882 */ 1883 static int atmel_startup(struct uart_port *port) 1884 { 1885 struct platform_device *pdev = to_platform_device(port->dev); 1886 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1887 int retval; 1888 1889 /* 1890 * Ensure that no interrupts are enabled otherwise when 1891 * request_irq() is called we could get stuck trying to 1892 * handle an unexpected interrupt 1893 */ 1894 atmel_uart_writel(port, ATMEL_US_IDR, -1); 1895 atmel_port->ms_irq_enabled = false; 1896 1897 /* 1898 * Allocate the IRQ 1899 */ 1900 retval = request_irq(port->irq, atmel_interrupt, 1901 IRQF_SHARED | IRQF_COND_SUSPEND, 1902 dev_name(&pdev->dev), port); 1903 if (retval) { 1904 dev_err(port->dev, "atmel_startup - Can't get irq\n"); 1905 return retval; 1906 } 1907 1908 atomic_set(&atmel_port->tasklet_shutdown, 0); 1909 tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func); 1910 tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func); 1911 1912 /* 1913 * Initialize DMA (if necessary) 1914 */ 1915 atmel_init_property(atmel_port, pdev); 1916 atmel_set_ops(port); 1917 1918 if (atmel_port->prepare_rx) { 1919 retval = atmel_port->prepare_rx(port); 1920 if (retval < 0) 1921 atmel_set_ops(port); 1922 } 1923 1924 if (atmel_port->prepare_tx) { 1925 retval = atmel_port->prepare_tx(port); 1926 if (retval < 0) 1927 atmel_set_ops(port); 1928 } 1929 1930 /* 1931 * Enable FIFO when available 1932 */ 1933 if (atmel_port->fifo_size) { 1934 unsigned int txrdym = ATMEL_US_ONE_DATA; 1935 unsigned int rxrdym = ATMEL_US_ONE_DATA; 1936 unsigned int fmr; 1937 1938 atmel_uart_writel(port, ATMEL_US_CR, 1939 ATMEL_US_FIFOEN | 1940 ATMEL_US_RXFCLR | 1941 ATMEL_US_TXFLCLR); 1942 1943 if (atmel_use_dma_tx(port)) 1944 txrdym = ATMEL_US_FOUR_DATA; 1945 1946 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym); 1947 if (atmel_port->rts_high && 1948 atmel_port->rts_low) 1949 fmr |= ATMEL_US_FRTSC | 1950 ATMEL_US_RXFTHRES(atmel_port->rts_high) | 1951 ATMEL_US_RXFTHRES2(atmel_port->rts_low); 1952 1953 atmel_uart_writel(port, ATMEL_US_FMR, fmr); 1954 } 1955 1956 /* Save current CSR for comparison in atmel_tasklet_func() */ 1957 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR); 1958 1959 /* 1960 * Finally, enable the serial port 1961 */ 1962 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1963 /* enable xmit & rcvr */ 1964 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 1965 atmel_port->tx_stopped = false; 1966 1967 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0); 1968 1969 if (atmel_use_pdc_rx(port)) { 1970 /* set UART timeout */ 1971 if (!atmel_port->has_hw_timer) { 1972 mod_timer(&atmel_port->uart_timer, 1973 jiffies + uart_poll_timeout(port)); 1974 /* set USART timeout */ 1975 } else { 1976 atmel_uart_writel(port, atmel_port->rtor, 1977 PDC_RX_TIMEOUT); 1978 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1979 1980 atmel_uart_writel(port, ATMEL_US_IER, 1981 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1982 } 1983 /* enable PDC controller */ 1984 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 1985 } else if (atmel_use_dma_rx(port)) { 1986 /* set UART timeout */ 1987 if (!atmel_port->has_hw_timer) { 1988 mod_timer(&atmel_port->uart_timer, 1989 jiffies + uart_poll_timeout(port)); 1990 /* set USART timeout */ 1991 } else { 1992 atmel_uart_writel(port, atmel_port->rtor, 1993 PDC_RX_TIMEOUT); 1994 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1995 1996 atmel_uart_writel(port, ATMEL_US_IER, 1997 ATMEL_US_TIMEOUT); 1998 } 1999 } else { 2000 /* enable receive only */ 2001 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY); 2002 } 2003 2004 return 0; 2005 } 2006 2007 /* 2008 * Flush any TX data submitted for DMA. Called when the TX circular 2009 * buffer is reset. 2010 */ 2011 static void atmel_flush_buffer(struct uart_port *port) 2012 { 2013 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2014 2015 if (atmel_use_pdc_tx(port)) { 2016 atmel_uart_writel(port, ATMEL_PDC_TCR, 0); 2017 atmel_port->pdc_tx.ofs = 0; 2018 } 2019 /* 2020 * in uart_flush_buffer(), the xmit circular buffer has just 2021 * been cleared, so we have to reset tx_len accordingly. 2022 */ 2023 atmel_port->tx_len = 0; 2024 } 2025 2026 /* 2027 * Disable the port 2028 */ 2029 static void atmel_shutdown(struct uart_port *port) 2030 { 2031 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2032 2033 /* Disable modem control lines interrupts */ 2034 atmel_disable_ms(port); 2035 2036 /* Disable interrupts at device level */ 2037 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2038 2039 /* Prevent spurious interrupts from scheduling the tasklet */ 2040 atomic_inc(&atmel_port->tasklet_shutdown); 2041 2042 /* 2043 * Prevent any tasklets being scheduled during 2044 * cleanup 2045 */ 2046 del_timer_sync(&atmel_port->uart_timer); 2047 2048 /* Make sure that no interrupt is on the fly */ 2049 synchronize_irq(port->irq); 2050 2051 /* 2052 * Clear out any scheduled tasklets before 2053 * we destroy the buffers 2054 */ 2055 tasklet_kill(&atmel_port->tasklet_rx); 2056 tasklet_kill(&atmel_port->tasklet_tx); 2057 2058 /* 2059 * Ensure everything is stopped and 2060 * disable port and break condition. 2061 */ 2062 atmel_stop_rx(port); 2063 atmel_stop_tx(port); 2064 2065 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 2066 2067 /* 2068 * Shut-down the DMA. 2069 */ 2070 if (atmel_port->release_rx) 2071 atmel_port->release_rx(port); 2072 if (atmel_port->release_tx) 2073 atmel_port->release_tx(port); 2074 2075 /* 2076 * Reset ring buffer pointers 2077 */ 2078 atmel_port->rx_ring.head = 0; 2079 atmel_port->rx_ring.tail = 0; 2080 2081 /* 2082 * Free the interrupts 2083 */ 2084 free_irq(port->irq, port); 2085 2086 atmel_flush_buffer(port); 2087 } 2088 2089 /* 2090 * Power / Clock management. 2091 */ 2092 static void atmel_serial_pm(struct uart_port *port, unsigned int state, 2093 unsigned int oldstate) 2094 { 2095 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2096 2097 switch (state) { 2098 case UART_PM_STATE_ON: 2099 /* 2100 * Enable the peripheral clock for this serial port. 2101 * This is called on uart_open() or a resume event. 2102 */ 2103 clk_prepare_enable(atmel_port->clk); 2104 2105 /* re-enable interrupts if we disabled some on suspend */ 2106 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr); 2107 break; 2108 case UART_PM_STATE_OFF: 2109 /* Back up the interrupt mask and disable all interrupts */ 2110 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR); 2111 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2112 2113 /* 2114 * Disable the peripheral clock for this serial port. 2115 * This is called on uart_close() or a suspend event. 2116 */ 2117 clk_disable_unprepare(atmel_port->clk); 2118 break; 2119 default: 2120 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); 2121 } 2122 } 2123 2124 /* 2125 * Change the port parameters 2126 */ 2127 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, 2128 struct ktermios *old) 2129 { 2130 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2131 unsigned long flags; 2132 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0; 2133 2134 /* save the current mode register */ 2135 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR); 2136 2137 /* reset the mode, clock divisor, parity, stop bits and data size */ 2138 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | 2139 ATMEL_US_PAR | ATMEL_US_USMODE); 2140 2141 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 2142 2143 /* byte size */ 2144 switch (termios->c_cflag & CSIZE) { 2145 case CS5: 2146 mode |= ATMEL_US_CHRL_5; 2147 break; 2148 case CS6: 2149 mode |= ATMEL_US_CHRL_6; 2150 break; 2151 case CS7: 2152 mode |= ATMEL_US_CHRL_7; 2153 break; 2154 default: 2155 mode |= ATMEL_US_CHRL_8; 2156 break; 2157 } 2158 2159 /* stop bits */ 2160 if (termios->c_cflag & CSTOPB) 2161 mode |= ATMEL_US_NBSTOP_2; 2162 2163 /* parity */ 2164 if (termios->c_cflag & PARENB) { 2165 /* Mark or Space parity */ 2166 if (termios->c_cflag & CMSPAR) { 2167 if (termios->c_cflag & PARODD) 2168 mode |= ATMEL_US_PAR_MARK; 2169 else 2170 mode |= ATMEL_US_PAR_SPACE; 2171 } else if (termios->c_cflag & PARODD) 2172 mode |= ATMEL_US_PAR_ODD; 2173 else 2174 mode |= ATMEL_US_PAR_EVEN; 2175 } else 2176 mode |= ATMEL_US_PAR_NONE; 2177 2178 spin_lock_irqsave(&port->lock, flags); 2179 2180 port->read_status_mask = ATMEL_US_OVRE; 2181 if (termios->c_iflag & INPCK) 2182 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2183 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2184 port->read_status_mask |= ATMEL_US_RXBRK; 2185 2186 if (atmel_use_pdc_rx(port)) 2187 /* need to enable error interrupts */ 2188 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask); 2189 2190 /* 2191 * Characters to ignore 2192 */ 2193 port->ignore_status_mask = 0; 2194 if (termios->c_iflag & IGNPAR) 2195 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2196 if (termios->c_iflag & IGNBRK) { 2197 port->ignore_status_mask |= ATMEL_US_RXBRK; 2198 /* 2199 * If we're ignoring parity and break indicators, 2200 * ignore overruns too (for real raw support). 2201 */ 2202 if (termios->c_iflag & IGNPAR) 2203 port->ignore_status_mask |= ATMEL_US_OVRE; 2204 } 2205 /* TODO: Ignore all characters if CREAD is set.*/ 2206 2207 /* update the per-port timeout */ 2208 uart_update_timeout(port, termios->c_cflag, baud); 2209 2210 /* 2211 * save/disable interrupts. The tty layer will ensure that the 2212 * transmitter is empty if requested by the caller, so there's 2213 * no need to wait for it here. 2214 */ 2215 imr = atmel_uart_readl(port, ATMEL_US_IMR); 2216 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2217 2218 /* disable receiver and transmitter */ 2219 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS); 2220 atmel_port->tx_stopped = true; 2221 2222 /* mode */ 2223 if (port->rs485.flags & SER_RS485_ENABLED) { 2224 atmel_uart_writel(port, ATMEL_US_TTGR, 2225 port->rs485.delay_rts_after_send); 2226 mode |= ATMEL_US_USMODE_RS485; 2227 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) { 2228 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg); 2229 /* select mck clock, and output */ 2230 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO; 2231 /* set max iterations */ 2232 mode |= ATMEL_US_MAX_ITER(3); 2233 if ((port->iso7816.flags & SER_ISO7816_T_PARAM) 2234 == SER_ISO7816_T(0)) 2235 mode |= ATMEL_US_USMODE_ISO7816_T0; 2236 else 2237 mode |= ATMEL_US_USMODE_ISO7816_T1; 2238 } else if (termios->c_cflag & CRTSCTS) { 2239 /* RS232 with hardware handshake (RTS/CTS) */ 2240 if (atmel_use_fifo(port) && 2241 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) { 2242 /* 2243 * with ATMEL_US_USMODE_HWHS set, the controller will 2244 * be able to drive the RTS pin high/low when the RX 2245 * FIFO is above RXFTHRES/below RXFTHRES2. 2246 * It will also disable the transmitter when the CTS 2247 * pin is high. 2248 * This mode is not activated if CTS pin is a GPIO 2249 * because in this case, the transmitter is always 2250 * disabled (there must be an internal pull-up 2251 * responsible for this behaviour). 2252 * If the RTS pin is a GPIO, the controller won't be 2253 * able to drive it according to the FIFO thresholds, 2254 * but it will be handled by the driver. 2255 */ 2256 mode |= ATMEL_US_USMODE_HWHS; 2257 } else { 2258 /* 2259 * For platforms without FIFO, the flow control is 2260 * handled by the driver. 2261 */ 2262 mode |= ATMEL_US_USMODE_NORMAL; 2263 } 2264 } else { 2265 /* RS232 without hadware handshake */ 2266 mode |= ATMEL_US_USMODE_NORMAL; 2267 } 2268 2269 /* 2270 * Set the baud rate: 2271 * Fractional baudrate allows to setup output frequency more 2272 * accurately. This feature is enabled only when using normal mode. 2273 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8)) 2274 * Currently, OVER is always set to 0 so we get 2275 * baudrate = selected clock / (16 * (CD + FP / 8)) 2276 * then 2277 * 8 CD + FP = selected clock / (2 * baudrate) 2278 */ 2279 if (atmel_port->has_frac_baudrate) { 2280 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2); 2281 cd = div >> 3; 2282 fp = div & ATMEL_US_FP_MASK; 2283 } else { 2284 cd = uart_get_divisor(port, baud); 2285 } 2286 2287 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */ 2288 cd /= 8; 2289 mode |= ATMEL_US_USCLKS_MCK_DIV8; 2290 } 2291 quot = cd | fp << ATMEL_US_FP_OFFSET; 2292 2293 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) 2294 atmel_uart_writel(port, ATMEL_US_BRGR, quot); 2295 2296 /* set the mode, clock divisor, parity, stop bits and data size */ 2297 atmel_uart_writel(port, ATMEL_US_MR, mode); 2298 2299 /* 2300 * when switching the mode, set the RTS line state according to the 2301 * new mode, otherwise keep the former state 2302 */ 2303 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) { 2304 unsigned int rts_state; 2305 2306 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 2307 /* let the hardware control the RTS line */ 2308 rts_state = ATMEL_US_RTSDIS; 2309 } else { 2310 /* force RTS line to low level */ 2311 rts_state = ATMEL_US_RTSEN; 2312 } 2313 2314 atmel_uart_writel(port, ATMEL_US_CR, rts_state); 2315 } 2316 2317 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2318 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 2319 atmel_port->tx_stopped = false; 2320 2321 /* restore interrupts */ 2322 atmel_uart_writel(port, ATMEL_US_IER, imr); 2323 2324 /* CTS flow-control and modem-status interrupts */ 2325 if (UART_ENABLE_MS(port, termios->c_cflag)) 2326 atmel_enable_ms(port); 2327 else 2328 atmel_disable_ms(port); 2329 2330 spin_unlock_irqrestore(&port->lock, flags); 2331 } 2332 2333 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios) 2334 { 2335 if (termios->c_line == N_PPS) { 2336 port->flags |= UPF_HARDPPS_CD; 2337 spin_lock_irq(&port->lock); 2338 atmel_enable_ms(port); 2339 spin_unlock_irq(&port->lock); 2340 } else { 2341 port->flags &= ~UPF_HARDPPS_CD; 2342 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 2343 spin_lock_irq(&port->lock); 2344 atmel_disable_ms(port); 2345 spin_unlock_irq(&port->lock); 2346 } 2347 } 2348 } 2349 2350 /* 2351 * Return string describing the specified port 2352 */ 2353 static const char *atmel_type(struct uart_port *port) 2354 { 2355 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; 2356 } 2357 2358 /* 2359 * Release the memory region(s) being used by 'port'. 2360 */ 2361 static void atmel_release_port(struct uart_port *port) 2362 { 2363 struct platform_device *mpdev = to_platform_device(port->dev->parent); 2364 int size = resource_size(mpdev->resource); 2365 2366 release_mem_region(port->mapbase, size); 2367 2368 if (port->flags & UPF_IOREMAP) { 2369 iounmap(port->membase); 2370 port->membase = NULL; 2371 } 2372 } 2373 2374 /* 2375 * Request the memory region(s) being used by 'port'. 2376 */ 2377 static int atmel_request_port(struct uart_port *port) 2378 { 2379 struct platform_device *mpdev = to_platform_device(port->dev->parent); 2380 int size = resource_size(mpdev->resource); 2381 2382 if (!request_mem_region(port->mapbase, size, "atmel_serial")) 2383 return -EBUSY; 2384 2385 if (port->flags & UPF_IOREMAP) { 2386 port->membase = ioremap(port->mapbase, size); 2387 if (port->membase == NULL) { 2388 release_mem_region(port->mapbase, size); 2389 return -ENOMEM; 2390 } 2391 } 2392 2393 return 0; 2394 } 2395 2396 /* 2397 * Configure/autoconfigure the port. 2398 */ 2399 static void atmel_config_port(struct uart_port *port, int flags) 2400 { 2401 if (flags & UART_CONFIG_TYPE) { 2402 port->type = PORT_ATMEL; 2403 atmel_request_port(port); 2404 } 2405 } 2406 2407 /* 2408 * Verify the new serial_struct (for TIOCSSERIAL). 2409 */ 2410 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) 2411 { 2412 int ret = 0; 2413 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) 2414 ret = -EINVAL; 2415 if (port->irq != ser->irq) 2416 ret = -EINVAL; 2417 if (ser->io_type != SERIAL_IO_MEM) 2418 ret = -EINVAL; 2419 if (port->uartclk / 16 != ser->baud_base) 2420 ret = -EINVAL; 2421 if (port->mapbase != (unsigned long)ser->iomem_base) 2422 ret = -EINVAL; 2423 if (port->iobase != ser->port) 2424 ret = -EINVAL; 2425 if (ser->hub6 != 0) 2426 ret = -EINVAL; 2427 return ret; 2428 } 2429 2430 #ifdef CONFIG_CONSOLE_POLL 2431 static int atmel_poll_get_char(struct uart_port *port) 2432 { 2433 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY)) 2434 cpu_relax(); 2435 2436 return atmel_uart_read_char(port); 2437 } 2438 2439 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) 2440 { 2441 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) 2442 cpu_relax(); 2443 2444 atmel_uart_write_char(port, ch); 2445 } 2446 #endif 2447 2448 static const struct uart_ops atmel_pops = { 2449 .tx_empty = atmel_tx_empty, 2450 .set_mctrl = atmel_set_mctrl, 2451 .get_mctrl = atmel_get_mctrl, 2452 .stop_tx = atmel_stop_tx, 2453 .start_tx = atmel_start_tx, 2454 .stop_rx = atmel_stop_rx, 2455 .enable_ms = atmel_enable_ms, 2456 .break_ctl = atmel_break_ctl, 2457 .startup = atmel_startup, 2458 .shutdown = atmel_shutdown, 2459 .flush_buffer = atmel_flush_buffer, 2460 .set_termios = atmel_set_termios, 2461 .set_ldisc = atmel_set_ldisc, 2462 .type = atmel_type, 2463 .release_port = atmel_release_port, 2464 .request_port = atmel_request_port, 2465 .config_port = atmel_config_port, 2466 .verify_port = atmel_verify_port, 2467 .pm = atmel_serial_pm, 2468 #ifdef CONFIG_CONSOLE_POLL 2469 .poll_get_char = atmel_poll_get_char, 2470 .poll_put_char = atmel_poll_put_char, 2471 #endif 2472 }; 2473 2474 static const struct serial_rs485 atmel_rs485_supported = { 2475 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND | SER_RS485_RX_DURING_TX, 2476 .delay_rts_before_send = 1, 2477 .delay_rts_after_send = 1, 2478 }; 2479 2480 /* 2481 * Configure the port from the platform device resource info. 2482 */ 2483 static int atmel_init_port(struct atmel_uart_port *atmel_port, 2484 struct platform_device *pdev) 2485 { 2486 int ret; 2487 struct uart_port *port = &atmel_port->uart; 2488 struct platform_device *mpdev = to_platform_device(pdev->dev.parent); 2489 2490 atmel_init_property(atmel_port, pdev); 2491 atmel_set_ops(port); 2492 2493 port->iotype = UPIO_MEM; 2494 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; 2495 port->ops = &atmel_pops; 2496 port->fifosize = 1; 2497 port->dev = &pdev->dev; 2498 port->mapbase = mpdev->resource[0].start; 2499 port->irq = platform_get_irq(mpdev, 0); 2500 port->rs485_config = atmel_config_rs485; 2501 port->rs485_supported = atmel_rs485_supported; 2502 port->iso7816_config = atmel_config_iso7816; 2503 port->membase = NULL; 2504 2505 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); 2506 2507 ret = uart_get_rs485_mode(port); 2508 if (ret) 2509 return ret; 2510 2511 port->uartclk = clk_get_rate(atmel_port->clk); 2512 2513 /* 2514 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or 2515 * ENDTX|TXBUFE 2516 */ 2517 if (atmel_uart_is_half_duplex(port)) 2518 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 2519 else if (atmel_use_pdc_tx(port)) { 2520 port->fifosize = PDC_BUFFER_SIZE; 2521 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; 2522 } else { 2523 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 2524 } 2525 2526 return 0; 2527 } 2528 2529 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2530 static void atmel_console_putchar(struct uart_port *port, unsigned char ch) 2531 { 2532 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) 2533 cpu_relax(); 2534 atmel_uart_write_char(port, ch); 2535 } 2536 2537 /* 2538 * Interrupts are disabled on entering 2539 */ 2540 static void atmel_console_write(struct console *co, const char *s, u_int count) 2541 { 2542 struct uart_port *port = &atmel_ports[co->index].uart; 2543 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2544 unsigned int status, imr; 2545 unsigned int pdc_tx; 2546 2547 /* 2548 * First, save IMR and then disable interrupts 2549 */ 2550 imr = atmel_uart_readl(port, ATMEL_US_IMR); 2551 atmel_uart_writel(port, ATMEL_US_IDR, 2552 ATMEL_US_RXRDY | atmel_port->tx_done_mask); 2553 2554 /* Store PDC transmit status and disable it */ 2555 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN; 2556 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 2557 2558 /* Make sure that tx path is actually able to send characters */ 2559 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN); 2560 atmel_port->tx_stopped = false; 2561 2562 uart_console_write(port, s, count, atmel_console_putchar); 2563 2564 /* 2565 * Finally, wait for transmitter to become empty 2566 * and restore IMR 2567 */ 2568 do { 2569 status = atmel_uart_readl(port, ATMEL_US_CSR); 2570 } while (!(status & ATMEL_US_TXRDY)); 2571 2572 /* Restore PDC transmit status */ 2573 if (pdc_tx) 2574 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 2575 2576 /* set interrupts back the way they were */ 2577 atmel_uart_writel(port, ATMEL_US_IER, imr); 2578 } 2579 2580 /* 2581 * If the port was already initialised (eg, by a boot loader), 2582 * try to determine the current setup. 2583 */ 2584 static void __init atmel_console_get_options(struct uart_port *port, int *baud, 2585 int *parity, int *bits) 2586 { 2587 unsigned int mr, quot; 2588 2589 /* 2590 * If the baud rate generator isn't running, the port wasn't 2591 * initialized by the boot loader. 2592 */ 2593 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD; 2594 if (!quot) 2595 return; 2596 2597 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL; 2598 if (mr == ATMEL_US_CHRL_8) 2599 *bits = 8; 2600 else 2601 *bits = 7; 2602 2603 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR; 2604 if (mr == ATMEL_US_PAR_EVEN) 2605 *parity = 'e'; 2606 else if (mr == ATMEL_US_PAR_ODD) 2607 *parity = 'o'; 2608 2609 /* 2610 * The serial core only rounds down when matching this to a 2611 * supported baud rate. Make sure we don't end up slightly 2612 * lower than one of those, as it would make us fall through 2613 * to a much lower baud rate than we really want. 2614 */ 2615 *baud = port->uartclk / (16 * (quot - 1)); 2616 } 2617 2618 static int __init atmel_console_setup(struct console *co, char *options) 2619 { 2620 struct uart_port *port = &atmel_ports[co->index].uart; 2621 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2622 int baud = 115200; 2623 int bits = 8; 2624 int parity = 'n'; 2625 int flow = 'n'; 2626 2627 if (port->membase == NULL) { 2628 /* Port not initialized yet - delay setup */ 2629 return -ENODEV; 2630 } 2631 2632 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2633 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2634 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 2635 atmel_port->tx_stopped = false; 2636 2637 if (options) 2638 uart_parse_options(options, &baud, &parity, &bits, &flow); 2639 else 2640 atmel_console_get_options(port, &baud, &parity, &bits); 2641 2642 return uart_set_options(port, co, baud, parity, bits, flow); 2643 } 2644 2645 static struct uart_driver atmel_uart; 2646 2647 static struct console atmel_console = { 2648 .name = ATMEL_DEVICENAME, 2649 .write = atmel_console_write, 2650 .device = uart_console_device, 2651 .setup = atmel_console_setup, 2652 .flags = CON_PRINTBUFFER, 2653 .index = -1, 2654 .data = &atmel_uart, 2655 }; 2656 2657 static void atmel_serial_early_write(struct console *con, const char *s, 2658 unsigned int n) 2659 { 2660 struct earlycon_device *dev = con->data; 2661 2662 uart_console_write(&dev->port, s, n, atmel_console_putchar); 2663 } 2664 2665 static int __init atmel_early_console_setup(struct earlycon_device *device, 2666 const char *options) 2667 { 2668 if (!device->port.membase) 2669 return -ENODEV; 2670 2671 device->con->write = atmel_serial_early_write; 2672 2673 return 0; 2674 } 2675 2676 OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91rm9200-usart", 2677 atmel_early_console_setup); 2678 OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91sam9260-usart", 2679 atmel_early_console_setup); 2680 2681 #define ATMEL_CONSOLE_DEVICE (&atmel_console) 2682 2683 #else 2684 #define ATMEL_CONSOLE_DEVICE NULL 2685 #endif 2686 2687 static struct uart_driver atmel_uart = { 2688 .owner = THIS_MODULE, 2689 .driver_name = "atmel_serial", 2690 .dev_name = ATMEL_DEVICENAME, 2691 .major = SERIAL_ATMEL_MAJOR, 2692 .minor = MINOR_START, 2693 .nr = ATMEL_MAX_UART, 2694 .cons = ATMEL_CONSOLE_DEVICE, 2695 }; 2696 2697 static bool atmel_serial_clk_will_stop(void) 2698 { 2699 #ifdef CONFIG_ARCH_AT91 2700 return at91_suspend_entering_slow_clock(); 2701 #else 2702 return false; 2703 #endif 2704 } 2705 2706 static int __maybe_unused atmel_serial_suspend(struct device *dev) 2707 { 2708 struct uart_port *port = dev_get_drvdata(dev); 2709 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2710 2711 if (uart_console(port) && console_suspend_enabled) { 2712 /* Drain the TX shifter */ 2713 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & 2714 ATMEL_US_TXEMPTY)) 2715 cpu_relax(); 2716 } 2717 2718 if (uart_console(port) && !console_suspend_enabled) { 2719 /* Cache register values as we won't get a full shutdown/startup 2720 * cycle 2721 */ 2722 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR); 2723 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR); 2724 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR); 2725 atmel_port->cache.rtor = atmel_uart_readl(port, 2726 atmel_port->rtor); 2727 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR); 2728 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR); 2729 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR); 2730 } 2731 2732 /* we can not wake up if we're running on slow clock */ 2733 atmel_port->may_wakeup = device_may_wakeup(dev); 2734 if (atmel_serial_clk_will_stop()) { 2735 unsigned long flags; 2736 2737 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2738 atmel_port->suspended = true; 2739 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2740 device_set_wakeup_enable(dev, 0); 2741 } 2742 2743 uart_suspend_port(&atmel_uart, port); 2744 2745 return 0; 2746 } 2747 2748 static int __maybe_unused atmel_serial_resume(struct device *dev) 2749 { 2750 struct uart_port *port = dev_get_drvdata(dev); 2751 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2752 unsigned long flags; 2753 2754 if (uart_console(port) && !console_suspend_enabled) { 2755 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr); 2756 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr); 2757 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr); 2758 atmel_uart_writel(port, atmel_port->rtor, 2759 atmel_port->cache.rtor); 2760 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr); 2761 2762 if (atmel_port->fifo_size) { 2763 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN | 2764 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR); 2765 atmel_uart_writel(port, ATMEL_US_FMR, 2766 atmel_port->cache.fmr); 2767 atmel_uart_writel(port, ATMEL_US_FIER, 2768 atmel_port->cache.fimr); 2769 } 2770 atmel_start_rx(port); 2771 } 2772 2773 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2774 if (atmel_port->pending) { 2775 atmel_handle_receive(port, atmel_port->pending); 2776 atmel_handle_status(port, atmel_port->pending, 2777 atmel_port->pending_status); 2778 atmel_handle_transmit(port, atmel_port->pending); 2779 atmel_port->pending = 0; 2780 } 2781 atmel_port->suspended = false; 2782 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2783 2784 uart_resume_port(&atmel_uart, port); 2785 device_set_wakeup_enable(dev, atmel_port->may_wakeup); 2786 2787 return 0; 2788 } 2789 2790 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port, 2791 struct platform_device *pdev) 2792 { 2793 atmel_port->fifo_size = 0; 2794 atmel_port->rts_low = 0; 2795 atmel_port->rts_high = 0; 2796 2797 if (of_property_read_u32(pdev->dev.of_node, 2798 "atmel,fifo-size", 2799 &atmel_port->fifo_size)) 2800 return; 2801 2802 if (!atmel_port->fifo_size) 2803 return; 2804 2805 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) { 2806 atmel_port->fifo_size = 0; 2807 dev_err(&pdev->dev, "Invalid FIFO size\n"); 2808 return; 2809 } 2810 2811 /* 2812 * 0 <= rts_low <= rts_high <= fifo_size 2813 * Once their CTS line asserted by the remote peer, some x86 UARTs tend 2814 * to flush their internal TX FIFO, commonly up to 16 data, before 2815 * actually stopping to send new data. So we try to set the RTS High 2816 * Threshold to a reasonably high value respecting this 16 data 2817 * empirical rule when possible. 2818 */ 2819 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1, 2820 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET); 2821 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2, 2822 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET); 2823 2824 dev_info(&pdev->dev, "Using FIFO (%u data)\n", 2825 atmel_port->fifo_size); 2826 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n", 2827 atmel_port->rts_high); 2828 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n", 2829 atmel_port->rts_low); 2830 } 2831 2832 static int atmel_serial_probe(struct platform_device *pdev) 2833 { 2834 struct atmel_uart_port *atmel_port; 2835 struct device_node *np = pdev->dev.parent->of_node; 2836 void *data; 2837 int ret; 2838 bool rs485_enabled; 2839 2840 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); 2841 2842 /* 2843 * In device tree there is no node with "atmel,at91rm9200-usart-serial" 2844 * as compatible string. This driver is probed by at91-usart mfd driver 2845 * which is just a wrapper over the atmel_serial driver and 2846 * spi-at91-usart driver. All attributes needed by this driver are 2847 * found in of_node of parent. 2848 */ 2849 pdev->dev.of_node = np; 2850 2851 ret = of_alias_get_id(np, "serial"); 2852 if (ret < 0) 2853 /* port id not found in platform data nor device-tree aliases: 2854 * auto-enumerate it */ 2855 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); 2856 2857 if (ret >= ATMEL_MAX_UART) { 2858 ret = -ENODEV; 2859 goto err; 2860 } 2861 2862 if (test_and_set_bit(ret, atmel_ports_in_use)) { 2863 /* port already in use */ 2864 ret = -EBUSY; 2865 goto err; 2866 } 2867 2868 atmel_port = &atmel_ports[ret]; 2869 atmel_port->backup_imr = 0; 2870 atmel_port->uart.line = ret; 2871 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE); 2872 atmel_serial_probe_fifos(atmel_port, pdev); 2873 2874 atomic_set(&atmel_port->tasklet_shutdown, 0); 2875 spin_lock_init(&atmel_port->lock_suspended); 2876 2877 atmel_port->clk = devm_clk_get(&pdev->dev, "usart"); 2878 if (IS_ERR(atmel_port->clk)) { 2879 ret = PTR_ERR(atmel_port->clk); 2880 goto err; 2881 } 2882 ret = clk_prepare_enable(atmel_port->clk); 2883 if (ret) 2884 goto err; 2885 2886 ret = atmel_init_port(atmel_port, pdev); 2887 if (ret) 2888 goto err_clk_disable_unprepare; 2889 2890 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0); 2891 if (IS_ERR(atmel_port->gpios)) { 2892 ret = PTR_ERR(atmel_port->gpios); 2893 goto err_clk_disable_unprepare; 2894 } 2895 2896 if (!atmel_use_pdc_rx(&atmel_port->uart)) { 2897 ret = -ENOMEM; 2898 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE, 2899 sizeof(struct atmel_uart_char), 2900 GFP_KERNEL); 2901 if (!data) 2902 goto err_clk_disable_unprepare; 2903 atmel_port->rx_ring.buf = data; 2904 } 2905 2906 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED; 2907 2908 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart); 2909 if (ret) 2910 goto err_add_port; 2911 2912 device_init_wakeup(&pdev->dev, 1); 2913 platform_set_drvdata(pdev, atmel_port); 2914 2915 if (rs485_enabled) { 2916 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR, 2917 ATMEL_US_USMODE_NORMAL); 2918 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR, 2919 ATMEL_US_RTSEN); 2920 } 2921 2922 /* 2923 * Get port name of usart or uart 2924 */ 2925 atmel_get_ip_name(&atmel_port->uart); 2926 2927 /* 2928 * The peripheral clock can now safely be disabled till the port 2929 * is used 2930 */ 2931 clk_disable_unprepare(atmel_port->clk); 2932 2933 return 0; 2934 2935 err_add_port: 2936 kfree(atmel_port->rx_ring.buf); 2937 atmel_port->rx_ring.buf = NULL; 2938 err_clk_disable_unprepare: 2939 clk_disable_unprepare(atmel_port->clk); 2940 clear_bit(atmel_port->uart.line, atmel_ports_in_use); 2941 err: 2942 return ret; 2943 } 2944 2945 /* 2946 * Even if the driver is not modular, it makes sense to be able to 2947 * unbind a device: there can be many bound devices, and there are 2948 * situations where dynamic binding and unbinding can be useful. 2949 * 2950 * For example, a connected device can require a specific firmware update 2951 * protocol that needs bitbanging on IO lines, but use the regular serial 2952 * port in the normal case. 2953 */ 2954 static int atmel_serial_remove(struct platform_device *pdev) 2955 { 2956 struct uart_port *port = platform_get_drvdata(pdev); 2957 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2958 int ret = 0; 2959 2960 tasklet_kill(&atmel_port->tasklet_rx); 2961 tasklet_kill(&atmel_port->tasklet_tx); 2962 2963 device_init_wakeup(&pdev->dev, 0); 2964 2965 ret = uart_remove_one_port(&atmel_uart, port); 2966 2967 kfree(atmel_port->rx_ring.buf); 2968 2969 /* "port" is allocated statically, so we shouldn't free it */ 2970 2971 clear_bit(port->line, atmel_ports_in_use); 2972 2973 pdev->dev.of_node = NULL; 2974 2975 return ret; 2976 } 2977 2978 static SIMPLE_DEV_PM_OPS(atmel_serial_pm_ops, atmel_serial_suspend, 2979 atmel_serial_resume); 2980 2981 static struct platform_driver atmel_serial_driver = { 2982 .probe = atmel_serial_probe, 2983 .remove = atmel_serial_remove, 2984 .driver = { 2985 .name = "atmel_usart_serial", 2986 .of_match_table = of_match_ptr(atmel_serial_dt_ids), 2987 .pm = pm_ptr(&atmel_serial_pm_ops), 2988 }, 2989 }; 2990 2991 static int __init atmel_serial_init(void) 2992 { 2993 int ret; 2994 2995 ret = uart_register_driver(&atmel_uart); 2996 if (ret) 2997 return ret; 2998 2999 ret = platform_driver_register(&atmel_serial_driver); 3000 if (ret) 3001 uart_unregister_driver(&atmel_uart); 3002 3003 return ret; 3004 } 3005 device_initcall(atmel_serial_init); 3006