1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for AMBA serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright 1999 ARM Limited 8 * Copyright (C) 2000 Deep Blue Solutions Ltd. 9 * Copyright (C) 2010 ST-Ericsson SA 10 * 11 * This is a generic driver for ARM AMBA-type serial ports. They 12 * have a lot of 16550-like features, but are not register compatible. 13 * Note that although they do have CTS, DCD and DSR inputs, they do 14 * not have an RI input, nor do they have DTR or RTS outputs. If 15 * required, these have to be supplied via some other means (eg, GPIO) 16 * and hooked into this driver. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/ioport.h> 21 #include <linux/init.h> 22 #include <linux/console.h> 23 #include <linux/sysrq.h> 24 #include <linux/device.h> 25 #include <linux/tty.h> 26 #include <linux/tty_flip.h> 27 #include <linux/serial_core.h> 28 #include <linux/serial.h> 29 #include <linux/amba/bus.h> 30 #include <linux/amba/serial.h> 31 #include <linux/clk.h> 32 #include <linux/slab.h> 33 #include <linux/dmaengine.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/scatterlist.h> 36 #include <linux/delay.h> 37 #include <linux/types.h> 38 #include <linux/of.h> 39 #include <linux/of_device.h> 40 #include <linux/pinctrl/consumer.h> 41 #include <linux/sizes.h> 42 #include <linux/io.h> 43 #include <linux/acpi.h> 44 45 #include "amba-pl011.h" 46 47 #define UART_NR 14 48 49 #define SERIAL_AMBA_MAJOR 204 50 #define SERIAL_AMBA_MINOR 64 51 #define SERIAL_AMBA_NR UART_NR 52 53 #define AMBA_ISR_PASS_LIMIT 256 54 55 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) 56 #define UART_DUMMY_DR_RX (1 << 16) 57 58 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = { 59 [REG_DR] = UART01x_DR, 60 [REG_FR] = UART01x_FR, 61 [REG_LCRH_RX] = UART011_LCRH, 62 [REG_LCRH_TX] = UART011_LCRH, 63 [REG_IBRD] = UART011_IBRD, 64 [REG_FBRD] = UART011_FBRD, 65 [REG_CR] = UART011_CR, 66 [REG_IFLS] = UART011_IFLS, 67 [REG_IMSC] = UART011_IMSC, 68 [REG_RIS] = UART011_RIS, 69 [REG_MIS] = UART011_MIS, 70 [REG_ICR] = UART011_ICR, 71 [REG_DMACR] = UART011_DMACR, 72 }; 73 74 /* There is by now at least one vendor with differing details, so handle it */ 75 struct vendor_data { 76 const u16 *reg_offset; 77 unsigned int ifls; 78 unsigned int fr_busy; 79 unsigned int fr_dsr; 80 unsigned int fr_cts; 81 unsigned int fr_ri; 82 unsigned int inv_fr; 83 bool access_32b; 84 bool oversampling; 85 bool dma_threshold; 86 bool cts_event_workaround; 87 bool always_enabled; 88 bool fixed_options; 89 90 unsigned int (*get_fifosize)(struct amba_device *dev); 91 }; 92 93 static unsigned int get_fifosize_arm(struct amba_device *dev) 94 { 95 return amba_rev(dev) < 3 ? 16 : 32; 96 } 97 98 static struct vendor_data vendor_arm = { 99 .reg_offset = pl011_std_offsets, 100 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 101 .fr_busy = UART01x_FR_BUSY, 102 .fr_dsr = UART01x_FR_DSR, 103 .fr_cts = UART01x_FR_CTS, 104 .fr_ri = UART011_FR_RI, 105 .oversampling = false, 106 .dma_threshold = false, 107 .cts_event_workaround = false, 108 .always_enabled = false, 109 .fixed_options = false, 110 .get_fifosize = get_fifosize_arm, 111 }; 112 113 static const struct vendor_data vendor_sbsa = { 114 .reg_offset = pl011_std_offsets, 115 .fr_busy = UART01x_FR_BUSY, 116 .fr_dsr = UART01x_FR_DSR, 117 .fr_cts = UART01x_FR_CTS, 118 .fr_ri = UART011_FR_RI, 119 .access_32b = true, 120 .oversampling = false, 121 .dma_threshold = false, 122 .cts_event_workaround = false, 123 .always_enabled = true, 124 .fixed_options = true, 125 }; 126 127 #ifdef CONFIG_ACPI_SPCR_TABLE 128 static const struct vendor_data vendor_qdt_qdf2400_e44 = { 129 .reg_offset = pl011_std_offsets, 130 .fr_busy = UART011_FR_TXFE, 131 .fr_dsr = UART01x_FR_DSR, 132 .fr_cts = UART01x_FR_CTS, 133 .fr_ri = UART011_FR_RI, 134 .inv_fr = UART011_FR_TXFE, 135 .access_32b = true, 136 .oversampling = false, 137 .dma_threshold = false, 138 .cts_event_workaround = false, 139 .always_enabled = true, 140 .fixed_options = true, 141 }; 142 #endif 143 144 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { 145 [REG_DR] = UART01x_DR, 146 [REG_ST_DMAWM] = ST_UART011_DMAWM, 147 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, 148 [REG_FR] = UART01x_FR, 149 [REG_LCRH_RX] = ST_UART011_LCRH_RX, 150 [REG_LCRH_TX] = ST_UART011_LCRH_TX, 151 [REG_IBRD] = UART011_IBRD, 152 [REG_FBRD] = UART011_FBRD, 153 [REG_CR] = UART011_CR, 154 [REG_IFLS] = UART011_IFLS, 155 [REG_IMSC] = UART011_IMSC, 156 [REG_RIS] = UART011_RIS, 157 [REG_MIS] = UART011_MIS, 158 [REG_ICR] = UART011_ICR, 159 [REG_DMACR] = UART011_DMACR, 160 [REG_ST_XFCR] = ST_UART011_XFCR, 161 [REG_ST_XON1] = ST_UART011_XON1, 162 [REG_ST_XON2] = ST_UART011_XON2, 163 [REG_ST_XOFF1] = ST_UART011_XOFF1, 164 [REG_ST_XOFF2] = ST_UART011_XOFF2, 165 [REG_ST_ITCR] = ST_UART011_ITCR, 166 [REG_ST_ITIP] = ST_UART011_ITIP, 167 [REG_ST_ABCR] = ST_UART011_ABCR, 168 [REG_ST_ABIMSC] = ST_UART011_ABIMSC, 169 }; 170 171 static unsigned int get_fifosize_st(struct amba_device *dev) 172 { 173 return 64; 174 } 175 176 static struct vendor_data vendor_st = { 177 .reg_offset = pl011_st_offsets, 178 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, 179 .fr_busy = UART01x_FR_BUSY, 180 .fr_dsr = UART01x_FR_DSR, 181 .fr_cts = UART01x_FR_CTS, 182 .fr_ri = UART011_FR_RI, 183 .oversampling = true, 184 .dma_threshold = true, 185 .cts_event_workaround = true, 186 .always_enabled = false, 187 .fixed_options = false, 188 .get_fifosize = get_fifosize_st, 189 }; 190 191 static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = { 192 [REG_DR] = ZX_UART011_DR, 193 [REG_FR] = ZX_UART011_FR, 194 [REG_LCRH_RX] = ZX_UART011_LCRH, 195 [REG_LCRH_TX] = ZX_UART011_LCRH, 196 [REG_IBRD] = ZX_UART011_IBRD, 197 [REG_FBRD] = ZX_UART011_FBRD, 198 [REG_CR] = ZX_UART011_CR, 199 [REG_IFLS] = ZX_UART011_IFLS, 200 [REG_IMSC] = ZX_UART011_IMSC, 201 [REG_RIS] = ZX_UART011_RIS, 202 [REG_MIS] = ZX_UART011_MIS, 203 [REG_ICR] = ZX_UART011_ICR, 204 [REG_DMACR] = ZX_UART011_DMACR, 205 }; 206 207 static unsigned int get_fifosize_zte(struct amba_device *dev) 208 { 209 return 16; 210 } 211 212 static struct vendor_data vendor_zte = { 213 .reg_offset = pl011_zte_offsets, 214 .access_32b = true, 215 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 216 .fr_busy = ZX_UART01x_FR_BUSY, 217 .fr_dsr = ZX_UART01x_FR_DSR, 218 .fr_cts = ZX_UART01x_FR_CTS, 219 .fr_ri = ZX_UART011_FR_RI, 220 .get_fifosize = get_fifosize_zte, 221 }; 222 223 /* Deals with DMA transactions */ 224 225 struct pl011_sgbuf { 226 struct scatterlist sg; 227 char *buf; 228 }; 229 230 struct pl011_dmarx_data { 231 struct dma_chan *chan; 232 struct completion complete; 233 bool use_buf_b; 234 struct pl011_sgbuf sgbuf_a; 235 struct pl011_sgbuf sgbuf_b; 236 dma_cookie_t cookie; 237 bool running; 238 struct timer_list timer; 239 unsigned int last_residue; 240 unsigned long last_jiffies; 241 bool auto_poll_rate; 242 unsigned int poll_rate; 243 unsigned int poll_timeout; 244 }; 245 246 struct pl011_dmatx_data { 247 struct dma_chan *chan; 248 struct scatterlist sg; 249 char *buf; 250 bool queued; 251 }; 252 253 /* 254 * We wrap our port structure around the generic uart_port. 255 */ 256 struct uart_amba_port { 257 struct uart_port port; 258 const u16 *reg_offset; 259 struct clk *clk; 260 const struct vendor_data *vendor; 261 unsigned int dmacr; /* dma control reg */ 262 unsigned int im; /* interrupt mask */ 263 unsigned int old_status; 264 unsigned int fifosize; /* vendor-specific */ 265 unsigned int old_cr; /* state during shutdown */ 266 unsigned int fixed_baud; /* vendor-set fixed baud rate */ 267 char type[12]; 268 bool rs485_tx_started; 269 unsigned int rs485_tx_drain_interval; /* usecs */ 270 #ifdef CONFIG_DMA_ENGINE 271 /* DMA stuff */ 272 bool using_tx_dma; 273 bool using_rx_dma; 274 struct pl011_dmarx_data dmarx; 275 struct pl011_dmatx_data dmatx; 276 bool dma_probed; 277 #endif 278 }; 279 280 static unsigned int pl011_tx_empty(struct uart_port *port); 281 282 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, 283 unsigned int reg) 284 { 285 return uap->reg_offset[reg]; 286 } 287 288 static unsigned int pl011_read(const struct uart_amba_port *uap, 289 unsigned int reg) 290 { 291 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 292 293 return (uap->port.iotype == UPIO_MEM32) ? 294 readl_relaxed(addr) : readw_relaxed(addr); 295 } 296 297 static void pl011_write(unsigned int val, const struct uart_amba_port *uap, 298 unsigned int reg) 299 { 300 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 301 302 if (uap->port.iotype == UPIO_MEM32) 303 writel_relaxed(val, addr); 304 else 305 writew_relaxed(val, addr); 306 } 307 308 /* 309 * Reads up to 256 characters from the FIFO or until it's empty and 310 * inserts them into the TTY layer. Returns the number of characters 311 * read from the FIFO. 312 */ 313 static int pl011_fifo_to_tty(struct uart_amba_port *uap) 314 { 315 unsigned int ch, flag, fifotaken; 316 int sysrq; 317 u16 status; 318 319 for (fifotaken = 0; fifotaken != 256; fifotaken++) { 320 status = pl011_read(uap, REG_FR); 321 if (status & UART01x_FR_RXFE) 322 break; 323 324 /* Take chars from the FIFO and update status */ 325 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; 326 flag = TTY_NORMAL; 327 uap->port.icount.rx++; 328 329 if (unlikely(ch & UART_DR_ERROR)) { 330 if (ch & UART011_DR_BE) { 331 ch &= ~(UART011_DR_FE | UART011_DR_PE); 332 uap->port.icount.brk++; 333 if (uart_handle_break(&uap->port)) 334 continue; 335 } else if (ch & UART011_DR_PE) 336 uap->port.icount.parity++; 337 else if (ch & UART011_DR_FE) 338 uap->port.icount.frame++; 339 if (ch & UART011_DR_OE) 340 uap->port.icount.overrun++; 341 342 ch &= uap->port.read_status_mask; 343 344 if (ch & UART011_DR_BE) 345 flag = TTY_BREAK; 346 else if (ch & UART011_DR_PE) 347 flag = TTY_PARITY; 348 else if (ch & UART011_DR_FE) 349 flag = TTY_FRAME; 350 } 351 352 spin_unlock(&uap->port.lock); 353 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255); 354 spin_lock(&uap->port.lock); 355 356 if (!sysrq) 357 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); 358 } 359 360 return fifotaken; 361 } 362 363 364 /* 365 * All the DMA operation mode stuff goes inside this ifdef. 366 * This assumes that you have a generic DMA device interface, 367 * no custom DMA interfaces are supported. 368 */ 369 #ifdef CONFIG_DMA_ENGINE 370 371 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE 372 373 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, 374 enum dma_data_direction dir) 375 { 376 dma_addr_t dma_addr; 377 378 sg->buf = dma_alloc_coherent(chan->device->dev, 379 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); 380 if (!sg->buf) 381 return -ENOMEM; 382 383 sg_init_table(&sg->sg, 1); 384 sg_set_page(&sg->sg, phys_to_page(dma_addr), 385 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); 386 sg_dma_address(&sg->sg) = dma_addr; 387 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; 388 389 return 0; 390 } 391 392 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, 393 enum dma_data_direction dir) 394 { 395 if (sg->buf) { 396 dma_free_coherent(chan->device->dev, 397 PL011_DMA_BUFFER_SIZE, sg->buf, 398 sg_dma_address(&sg->sg)); 399 } 400 } 401 402 static void pl011_dma_probe(struct uart_amba_port *uap) 403 { 404 /* DMA is the sole user of the platform data right now */ 405 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); 406 struct device *dev = uap->port.dev; 407 struct dma_slave_config tx_conf = { 408 .dst_addr = uap->port.mapbase + 409 pl011_reg_to_offset(uap, REG_DR), 410 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 411 .direction = DMA_MEM_TO_DEV, 412 .dst_maxburst = uap->fifosize >> 1, 413 .device_fc = false, 414 }; 415 struct dma_chan *chan; 416 dma_cap_mask_t mask; 417 418 uap->dma_probed = true; 419 chan = dma_request_chan(dev, "tx"); 420 if (IS_ERR(chan)) { 421 if (PTR_ERR(chan) == -EPROBE_DEFER) { 422 uap->dma_probed = false; 423 return; 424 } 425 426 /* We need platform data */ 427 if (!plat || !plat->dma_filter) { 428 dev_info(uap->port.dev, "no DMA platform data\n"); 429 return; 430 } 431 432 /* Try to acquire a generic DMA engine slave TX channel */ 433 dma_cap_zero(mask); 434 dma_cap_set(DMA_SLAVE, mask); 435 436 chan = dma_request_channel(mask, plat->dma_filter, 437 plat->dma_tx_param); 438 if (!chan) { 439 dev_err(uap->port.dev, "no TX DMA channel!\n"); 440 return; 441 } 442 } 443 444 dmaengine_slave_config(chan, &tx_conf); 445 uap->dmatx.chan = chan; 446 447 dev_info(uap->port.dev, "DMA channel TX %s\n", 448 dma_chan_name(uap->dmatx.chan)); 449 450 /* Optionally make use of an RX channel as well */ 451 chan = dma_request_slave_channel(dev, "rx"); 452 453 if (!chan && plat && plat->dma_rx_param) { 454 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); 455 456 if (!chan) { 457 dev_err(uap->port.dev, "no RX DMA channel!\n"); 458 return; 459 } 460 } 461 462 if (chan) { 463 struct dma_slave_config rx_conf = { 464 .src_addr = uap->port.mapbase + 465 pl011_reg_to_offset(uap, REG_DR), 466 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 467 .direction = DMA_DEV_TO_MEM, 468 .src_maxburst = uap->fifosize >> 2, 469 .device_fc = false, 470 }; 471 struct dma_slave_caps caps; 472 473 /* 474 * Some DMA controllers provide information on their capabilities. 475 * If the controller does, check for suitable residue processing 476 * otherwise assime all is well. 477 */ 478 if (0 == dma_get_slave_caps(chan, &caps)) { 479 if (caps.residue_granularity == 480 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { 481 dma_release_channel(chan); 482 dev_info(uap->port.dev, 483 "RX DMA disabled - no residue processing\n"); 484 return; 485 } 486 } 487 dmaengine_slave_config(chan, &rx_conf); 488 uap->dmarx.chan = chan; 489 490 uap->dmarx.auto_poll_rate = false; 491 if (plat && plat->dma_rx_poll_enable) { 492 /* Set poll rate if specified. */ 493 if (plat->dma_rx_poll_rate) { 494 uap->dmarx.auto_poll_rate = false; 495 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; 496 } else { 497 /* 498 * 100 ms defaults to poll rate if not 499 * specified. This will be adjusted with 500 * the baud rate at set_termios. 501 */ 502 uap->dmarx.auto_poll_rate = true; 503 uap->dmarx.poll_rate = 100; 504 } 505 /* 3 secs defaults poll_timeout if not specified. */ 506 if (plat->dma_rx_poll_timeout) 507 uap->dmarx.poll_timeout = 508 plat->dma_rx_poll_timeout; 509 else 510 uap->dmarx.poll_timeout = 3000; 511 } else if (!plat && dev->of_node) { 512 uap->dmarx.auto_poll_rate = of_property_read_bool( 513 dev->of_node, "auto-poll"); 514 if (uap->dmarx.auto_poll_rate) { 515 u32 x; 516 517 if (0 == of_property_read_u32(dev->of_node, 518 "poll-rate-ms", &x)) 519 uap->dmarx.poll_rate = x; 520 else 521 uap->dmarx.poll_rate = 100; 522 if (0 == of_property_read_u32(dev->of_node, 523 "poll-timeout-ms", &x)) 524 uap->dmarx.poll_timeout = x; 525 else 526 uap->dmarx.poll_timeout = 3000; 527 } 528 } 529 dev_info(uap->port.dev, "DMA channel RX %s\n", 530 dma_chan_name(uap->dmarx.chan)); 531 } 532 } 533 534 static void pl011_dma_remove(struct uart_amba_port *uap) 535 { 536 if (uap->dmatx.chan) 537 dma_release_channel(uap->dmatx.chan); 538 if (uap->dmarx.chan) 539 dma_release_channel(uap->dmarx.chan); 540 } 541 542 /* Forward declare these for the refill routine */ 543 static int pl011_dma_tx_refill(struct uart_amba_port *uap); 544 static void pl011_start_tx_pio(struct uart_amba_port *uap); 545 546 /* 547 * The current DMA TX buffer has been sent. 548 * Try to queue up another DMA buffer. 549 */ 550 static void pl011_dma_tx_callback(void *data) 551 { 552 struct uart_amba_port *uap = data; 553 struct pl011_dmatx_data *dmatx = &uap->dmatx; 554 unsigned long flags; 555 u16 dmacr; 556 557 spin_lock_irqsave(&uap->port.lock, flags); 558 if (uap->dmatx.queued) 559 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, 560 DMA_TO_DEVICE); 561 562 dmacr = uap->dmacr; 563 uap->dmacr = dmacr & ~UART011_TXDMAE; 564 pl011_write(uap->dmacr, uap, REG_DMACR); 565 566 /* 567 * If TX DMA was disabled, it means that we've stopped the DMA for 568 * some reason (eg, XOFF received, or we want to send an X-char.) 569 * 570 * Note: we need to be careful here of a potential race between DMA 571 * and the rest of the driver - if the driver disables TX DMA while 572 * a TX buffer completing, we must update the tx queued status to 573 * get further refills (hence we check dmacr). 574 */ 575 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || 576 uart_circ_empty(&uap->port.state->xmit)) { 577 uap->dmatx.queued = false; 578 spin_unlock_irqrestore(&uap->port.lock, flags); 579 return; 580 } 581 582 if (pl011_dma_tx_refill(uap) <= 0) 583 /* 584 * We didn't queue a DMA buffer for some reason, but we 585 * have data pending to be sent. Re-enable the TX IRQ. 586 */ 587 pl011_start_tx_pio(uap); 588 589 spin_unlock_irqrestore(&uap->port.lock, flags); 590 } 591 592 /* 593 * Try to refill the TX DMA buffer. 594 * Locking: called with port lock held and IRQs disabled. 595 * Returns: 596 * 1 if we queued up a TX DMA buffer. 597 * 0 if we didn't want to handle this by DMA 598 * <0 on error 599 */ 600 static int pl011_dma_tx_refill(struct uart_amba_port *uap) 601 { 602 struct pl011_dmatx_data *dmatx = &uap->dmatx; 603 struct dma_chan *chan = dmatx->chan; 604 struct dma_device *dma_dev = chan->device; 605 struct dma_async_tx_descriptor *desc; 606 struct circ_buf *xmit = &uap->port.state->xmit; 607 unsigned int count; 608 609 /* 610 * Try to avoid the overhead involved in using DMA if the 611 * transaction fits in the first half of the FIFO, by using 612 * the standard interrupt handling. This ensures that we 613 * issue a uart_write_wakeup() at the appropriate time. 614 */ 615 count = uart_circ_chars_pending(xmit); 616 if (count < (uap->fifosize >> 1)) { 617 uap->dmatx.queued = false; 618 return 0; 619 } 620 621 /* 622 * Bodge: don't send the last character by DMA, as this 623 * will prevent XON from notifying us to restart DMA. 624 */ 625 count -= 1; 626 627 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ 628 if (count > PL011_DMA_BUFFER_SIZE) 629 count = PL011_DMA_BUFFER_SIZE; 630 631 if (xmit->tail < xmit->head) 632 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); 633 else { 634 size_t first = UART_XMIT_SIZE - xmit->tail; 635 size_t second; 636 637 if (first > count) 638 first = count; 639 second = count - first; 640 641 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); 642 if (second) 643 memcpy(&dmatx->buf[first], &xmit->buf[0], second); 644 } 645 646 dmatx->sg.length = count; 647 648 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { 649 uap->dmatx.queued = false; 650 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); 651 return -EBUSY; 652 } 653 654 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, 655 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 656 if (!desc) { 657 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); 658 uap->dmatx.queued = false; 659 /* 660 * If DMA cannot be used right now, we complete this 661 * transaction via IRQ and let the TTY layer retry. 662 */ 663 dev_dbg(uap->port.dev, "TX DMA busy\n"); 664 return -EBUSY; 665 } 666 667 /* Some data to go along to the callback */ 668 desc->callback = pl011_dma_tx_callback; 669 desc->callback_param = uap; 670 671 /* All errors should happen at prepare time */ 672 dmaengine_submit(desc); 673 674 /* Fire the DMA transaction */ 675 dma_dev->device_issue_pending(chan); 676 677 uap->dmacr |= UART011_TXDMAE; 678 pl011_write(uap->dmacr, uap, REG_DMACR); 679 uap->dmatx.queued = true; 680 681 /* 682 * Now we know that DMA will fire, so advance the ring buffer 683 * with the stuff we just dispatched. 684 */ 685 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 686 uap->port.icount.tx += count; 687 688 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 689 uart_write_wakeup(&uap->port); 690 691 return 1; 692 } 693 694 /* 695 * We received a transmit interrupt without a pending X-char but with 696 * pending characters. 697 * Locking: called with port lock held and IRQs disabled. 698 * Returns: 699 * false if we want to use PIO to transmit 700 * true if we queued a DMA buffer 701 */ 702 static bool pl011_dma_tx_irq(struct uart_amba_port *uap) 703 { 704 if (!uap->using_tx_dma) 705 return false; 706 707 /* 708 * If we already have a TX buffer queued, but received a 709 * TX interrupt, it will be because we've just sent an X-char. 710 * Ensure the TX DMA is enabled and the TX IRQ is disabled. 711 */ 712 if (uap->dmatx.queued) { 713 uap->dmacr |= UART011_TXDMAE; 714 pl011_write(uap->dmacr, uap, REG_DMACR); 715 uap->im &= ~UART011_TXIM; 716 pl011_write(uap->im, uap, REG_IMSC); 717 return true; 718 } 719 720 /* 721 * We don't have a TX buffer queued, so try to queue one. 722 * If we successfully queued a buffer, mask the TX IRQ. 723 */ 724 if (pl011_dma_tx_refill(uap) > 0) { 725 uap->im &= ~UART011_TXIM; 726 pl011_write(uap->im, uap, REG_IMSC); 727 return true; 728 } 729 return false; 730 } 731 732 /* 733 * Stop the DMA transmit (eg, due to received XOFF). 734 * Locking: called with port lock held and IRQs disabled. 735 */ 736 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 737 { 738 if (uap->dmatx.queued) { 739 uap->dmacr &= ~UART011_TXDMAE; 740 pl011_write(uap->dmacr, uap, REG_DMACR); 741 } 742 } 743 744 /* 745 * Try to start a DMA transmit, or in the case of an XON/OFF 746 * character queued for send, try to get that character out ASAP. 747 * Locking: called with port lock held and IRQs disabled. 748 * Returns: 749 * false if we want the TX IRQ to be enabled 750 * true if we have a buffer queued 751 */ 752 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 753 { 754 u16 dmacr; 755 756 if (!uap->using_tx_dma) 757 return false; 758 759 if (!uap->port.x_char) { 760 /* no X-char, try to push chars out in DMA mode */ 761 bool ret = true; 762 763 if (!uap->dmatx.queued) { 764 if (pl011_dma_tx_refill(uap) > 0) { 765 uap->im &= ~UART011_TXIM; 766 pl011_write(uap->im, uap, REG_IMSC); 767 } else 768 ret = false; 769 } else if (!(uap->dmacr & UART011_TXDMAE)) { 770 uap->dmacr |= UART011_TXDMAE; 771 pl011_write(uap->dmacr, uap, REG_DMACR); 772 } 773 return ret; 774 } 775 776 /* 777 * We have an X-char to send. Disable DMA to prevent it loading 778 * the TX fifo, and then see if we can stuff it into the FIFO. 779 */ 780 dmacr = uap->dmacr; 781 uap->dmacr &= ~UART011_TXDMAE; 782 pl011_write(uap->dmacr, uap, REG_DMACR); 783 784 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { 785 /* 786 * No space in the FIFO, so enable the transmit interrupt 787 * so we know when there is space. Note that once we've 788 * loaded the character, we should just re-enable DMA. 789 */ 790 return false; 791 } 792 793 pl011_write(uap->port.x_char, uap, REG_DR); 794 uap->port.icount.tx++; 795 uap->port.x_char = 0; 796 797 /* Success - restore the DMA state */ 798 uap->dmacr = dmacr; 799 pl011_write(dmacr, uap, REG_DMACR); 800 801 return true; 802 } 803 804 /* 805 * Flush the transmit buffer. 806 * Locking: called with port lock held and IRQs disabled. 807 */ 808 static void pl011_dma_flush_buffer(struct uart_port *port) 809 __releases(&uap->port.lock) 810 __acquires(&uap->port.lock) 811 { 812 struct uart_amba_port *uap = 813 container_of(port, struct uart_amba_port, port); 814 815 if (!uap->using_tx_dma) 816 return; 817 818 dmaengine_terminate_async(uap->dmatx.chan); 819 820 if (uap->dmatx.queued) { 821 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 822 DMA_TO_DEVICE); 823 uap->dmatx.queued = false; 824 uap->dmacr &= ~UART011_TXDMAE; 825 pl011_write(uap->dmacr, uap, REG_DMACR); 826 } 827 } 828 829 static void pl011_dma_rx_callback(void *data); 830 831 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 832 { 833 struct dma_chan *rxchan = uap->dmarx.chan; 834 struct pl011_dmarx_data *dmarx = &uap->dmarx; 835 struct dma_async_tx_descriptor *desc; 836 struct pl011_sgbuf *sgbuf; 837 838 if (!rxchan) 839 return -EIO; 840 841 /* Start the RX DMA job */ 842 sgbuf = uap->dmarx.use_buf_b ? 843 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 844 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, 845 DMA_DEV_TO_MEM, 846 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 847 /* 848 * If the DMA engine is busy and cannot prepare a 849 * channel, no big deal, the driver will fall back 850 * to interrupt mode as a result of this error code. 851 */ 852 if (!desc) { 853 uap->dmarx.running = false; 854 dmaengine_terminate_all(rxchan); 855 return -EBUSY; 856 } 857 858 /* Some data to go along to the callback */ 859 desc->callback = pl011_dma_rx_callback; 860 desc->callback_param = uap; 861 dmarx->cookie = dmaengine_submit(desc); 862 dma_async_issue_pending(rxchan); 863 864 uap->dmacr |= UART011_RXDMAE; 865 pl011_write(uap->dmacr, uap, REG_DMACR); 866 uap->dmarx.running = true; 867 868 uap->im &= ~UART011_RXIM; 869 pl011_write(uap->im, uap, REG_IMSC); 870 871 return 0; 872 } 873 874 /* 875 * This is called when either the DMA job is complete, or 876 * the FIFO timeout interrupt occurred. This must be called 877 * with the port spinlock uap->port.lock held. 878 */ 879 static void pl011_dma_rx_chars(struct uart_amba_port *uap, 880 u32 pending, bool use_buf_b, 881 bool readfifo) 882 { 883 struct tty_port *port = &uap->port.state->port; 884 struct pl011_sgbuf *sgbuf = use_buf_b ? 885 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 886 int dma_count = 0; 887 u32 fifotaken = 0; /* only used for vdbg() */ 888 889 struct pl011_dmarx_data *dmarx = &uap->dmarx; 890 int dmataken = 0; 891 892 if (uap->dmarx.poll_rate) { 893 /* The data can be taken by polling */ 894 dmataken = sgbuf->sg.length - dmarx->last_residue; 895 /* Recalculate the pending size */ 896 if (pending >= dmataken) 897 pending -= dmataken; 898 } 899 900 /* Pick the remain data from the DMA */ 901 if (pending) { 902 903 /* 904 * First take all chars in the DMA pipe, then look in the FIFO. 905 * Note that tty_insert_flip_buf() tries to take as many chars 906 * as it can. 907 */ 908 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 909 pending); 910 911 uap->port.icount.rx += dma_count; 912 if (dma_count < pending) 913 dev_warn(uap->port.dev, 914 "couldn't insert all characters (TTY is full?)\n"); 915 } 916 917 /* Reset the last_residue for Rx DMA poll */ 918 if (uap->dmarx.poll_rate) 919 dmarx->last_residue = sgbuf->sg.length; 920 921 /* 922 * Only continue with trying to read the FIFO if all DMA chars have 923 * been taken first. 924 */ 925 if (dma_count == pending && readfifo) { 926 /* Clear any error flags */ 927 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 928 UART011_FEIS, uap, REG_ICR); 929 930 /* 931 * If we read all the DMA'd characters, and we had an 932 * incomplete buffer, that could be due to an rx error, or 933 * maybe we just timed out. Read any pending chars and check 934 * the error status. 935 * 936 * Error conditions will only occur in the FIFO, these will 937 * trigger an immediate interrupt and stop the DMA job, so we 938 * will always find the error in the FIFO, never in the DMA 939 * buffer. 940 */ 941 fifotaken = pl011_fifo_to_tty(uap); 942 } 943 944 dev_vdbg(uap->port.dev, 945 "Took %d chars from DMA buffer and %d chars from the FIFO\n", 946 dma_count, fifotaken); 947 tty_flip_buffer_push(port); 948 } 949 950 static void pl011_dma_rx_irq(struct uart_amba_port *uap) 951 { 952 struct pl011_dmarx_data *dmarx = &uap->dmarx; 953 struct dma_chan *rxchan = dmarx->chan; 954 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 955 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 956 size_t pending; 957 struct dma_tx_state state; 958 enum dma_status dmastat; 959 960 /* 961 * Pause the transfer so we can trust the current counter, 962 * do this before we pause the PL011 block, else we may 963 * overflow the FIFO. 964 */ 965 if (dmaengine_pause(rxchan)) 966 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 967 dmastat = rxchan->device->device_tx_status(rxchan, 968 dmarx->cookie, &state); 969 if (dmastat != DMA_PAUSED) 970 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 971 972 /* Disable RX DMA - incoming data will wait in the FIFO */ 973 uap->dmacr &= ~UART011_RXDMAE; 974 pl011_write(uap->dmacr, uap, REG_DMACR); 975 uap->dmarx.running = false; 976 977 pending = sgbuf->sg.length - state.residue; 978 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 979 /* Then we terminate the transfer - we now know our residue */ 980 dmaengine_terminate_all(rxchan); 981 982 /* 983 * This will take the chars we have so far and insert 984 * into the framework. 985 */ 986 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); 987 988 /* Switch buffer & re-trigger DMA job */ 989 dmarx->use_buf_b = !dmarx->use_buf_b; 990 if (pl011_dma_rx_trigger_dma(uap)) { 991 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 992 "fall back to interrupt mode\n"); 993 uap->im |= UART011_RXIM; 994 pl011_write(uap->im, uap, REG_IMSC); 995 } 996 } 997 998 static void pl011_dma_rx_callback(void *data) 999 { 1000 struct uart_amba_port *uap = data; 1001 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1002 struct dma_chan *rxchan = dmarx->chan; 1003 bool lastbuf = dmarx->use_buf_b; 1004 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 1005 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 1006 size_t pending; 1007 struct dma_tx_state state; 1008 int ret; 1009 1010 /* 1011 * This completion interrupt occurs typically when the 1012 * RX buffer is totally stuffed but no timeout has yet 1013 * occurred. When that happens, we just want the RX 1014 * routine to flush out the secondary DMA buffer while 1015 * we immediately trigger the next DMA job. 1016 */ 1017 spin_lock_irq(&uap->port.lock); 1018 /* 1019 * Rx data can be taken by the UART interrupts during 1020 * the DMA irq handler. So we check the residue here. 1021 */ 1022 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1023 pending = sgbuf->sg.length - state.residue; 1024 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 1025 /* Then we terminate the transfer - we now know our residue */ 1026 dmaengine_terminate_all(rxchan); 1027 1028 uap->dmarx.running = false; 1029 dmarx->use_buf_b = !lastbuf; 1030 ret = pl011_dma_rx_trigger_dma(uap); 1031 1032 pl011_dma_rx_chars(uap, pending, lastbuf, false); 1033 spin_unlock_irq(&uap->port.lock); 1034 /* 1035 * Do this check after we picked the DMA chars so we don't 1036 * get some IRQ immediately from RX. 1037 */ 1038 if (ret) { 1039 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 1040 "fall back to interrupt mode\n"); 1041 uap->im |= UART011_RXIM; 1042 pl011_write(uap->im, uap, REG_IMSC); 1043 } 1044 } 1045 1046 /* 1047 * Stop accepting received characters, when we're shutting down or 1048 * suspending this port. 1049 * Locking: called with port lock held and IRQs disabled. 1050 */ 1051 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1052 { 1053 /* FIXME. Just disable the DMA enable */ 1054 uap->dmacr &= ~UART011_RXDMAE; 1055 pl011_write(uap->dmacr, uap, REG_DMACR); 1056 } 1057 1058 /* 1059 * Timer handler for Rx DMA polling. 1060 * Every polling, It checks the residue in the dma buffer and transfer 1061 * data to the tty. Also, last_residue is updated for the next polling. 1062 */ 1063 static void pl011_dma_rx_poll(struct timer_list *t) 1064 { 1065 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer); 1066 struct tty_port *port = &uap->port.state->port; 1067 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1068 struct dma_chan *rxchan = uap->dmarx.chan; 1069 unsigned long flags; 1070 unsigned int dmataken = 0; 1071 unsigned int size = 0; 1072 struct pl011_sgbuf *sgbuf; 1073 int dma_count; 1074 struct dma_tx_state state; 1075 1076 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 1077 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1078 if (likely(state.residue < dmarx->last_residue)) { 1079 dmataken = sgbuf->sg.length - dmarx->last_residue; 1080 size = dmarx->last_residue - state.residue; 1081 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 1082 size); 1083 if (dma_count == size) 1084 dmarx->last_residue = state.residue; 1085 dmarx->last_jiffies = jiffies; 1086 } 1087 tty_flip_buffer_push(port); 1088 1089 /* 1090 * If no data is received in poll_timeout, the driver will fall back 1091 * to interrupt mode. We will retrigger DMA at the first interrupt. 1092 */ 1093 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) 1094 > uap->dmarx.poll_timeout) { 1095 1096 spin_lock_irqsave(&uap->port.lock, flags); 1097 pl011_dma_rx_stop(uap); 1098 uap->im |= UART011_RXIM; 1099 pl011_write(uap->im, uap, REG_IMSC); 1100 spin_unlock_irqrestore(&uap->port.lock, flags); 1101 1102 uap->dmarx.running = false; 1103 dmaengine_terminate_all(rxchan); 1104 del_timer(&uap->dmarx.timer); 1105 } else { 1106 mod_timer(&uap->dmarx.timer, 1107 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); 1108 } 1109 } 1110 1111 static void pl011_dma_startup(struct uart_amba_port *uap) 1112 { 1113 int ret; 1114 1115 if (!uap->dma_probed) 1116 pl011_dma_probe(uap); 1117 1118 if (!uap->dmatx.chan) 1119 return; 1120 1121 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); 1122 if (!uap->dmatx.buf) { 1123 dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); 1124 uap->port.fifosize = uap->fifosize; 1125 return; 1126 } 1127 1128 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); 1129 1130 /* The DMA buffer is now the FIFO the TTY subsystem can use */ 1131 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; 1132 uap->using_tx_dma = true; 1133 1134 if (!uap->dmarx.chan) 1135 goto skip_rx; 1136 1137 /* Allocate and map DMA RX buffers */ 1138 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1139 DMA_FROM_DEVICE); 1140 if (ret) { 1141 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1142 "RX buffer A", ret); 1143 goto skip_rx; 1144 } 1145 1146 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, 1147 DMA_FROM_DEVICE); 1148 if (ret) { 1149 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1150 "RX buffer B", ret); 1151 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1152 DMA_FROM_DEVICE); 1153 goto skip_rx; 1154 } 1155 1156 uap->using_rx_dma = true; 1157 1158 skip_rx: 1159 /* Turn on DMA error (RX/TX will be enabled on demand) */ 1160 uap->dmacr |= UART011_DMAONERR; 1161 pl011_write(uap->dmacr, uap, REG_DMACR); 1162 1163 /* 1164 * ST Micro variants has some specific dma burst threshold 1165 * compensation. Set this to 16 bytes, so burst will only 1166 * be issued above/below 16 bytes. 1167 */ 1168 if (uap->vendor->dma_threshold) 1169 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, 1170 uap, REG_ST_DMAWM); 1171 1172 if (uap->using_rx_dma) { 1173 if (pl011_dma_rx_trigger_dma(uap)) 1174 dev_dbg(uap->port.dev, "could not trigger initial " 1175 "RX DMA job, fall back to interrupt mode\n"); 1176 if (uap->dmarx.poll_rate) { 1177 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0); 1178 mod_timer(&uap->dmarx.timer, 1179 jiffies + 1180 msecs_to_jiffies(uap->dmarx.poll_rate)); 1181 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1182 uap->dmarx.last_jiffies = jiffies; 1183 } 1184 } 1185 } 1186 1187 static void pl011_dma_shutdown(struct uart_amba_port *uap) 1188 { 1189 if (!(uap->using_tx_dma || uap->using_rx_dma)) 1190 return; 1191 1192 /* Disable RX and TX DMA */ 1193 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) 1194 cpu_relax(); 1195 1196 spin_lock_irq(&uap->port.lock); 1197 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); 1198 pl011_write(uap->dmacr, uap, REG_DMACR); 1199 spin_unlock_irq(&uap->port.lock); 1200 1201 if (uap->using_tx_dma) { 1202 /* In theory, this should already be done by pl011_dma_flush_buffer */ 1203 dmaengine_terminate_all(uap->dmatx.chan); 1204 if (uap->dmatx.queued) { 1205 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 1206 DMA_TO_DEVICE); 1207 uap->dmatx.queued = false; 1208 } 1209 1210 kfree(uap->dmatx.buf); 1211 uap->using_tx_dma = false; 1212 } 1213 1214 if (uap->using_rx_dma) { 1215 dmaengine_terminate_all(uap->dmarx.chan); 1216 /* Clean up the RX DMA */ 1217 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); 1218 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); 1219 if (uap->dmarx.poll_rate) 1220 del_timer_sync(&uap->dmarx.timer); 1221 uap->using_rx_dma = false; 1222 } 1223 } 1224 1225 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1226 { 1227 return uap->using_rx_dma; 1228 } 1229 1230 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1231 { 1232 return uap->using_rx_dma && uap->dmarx.running; 1233 } 1234 1235 #else 1236 /* Blank functions if the DMA engine is not available */ 1237 static inline void pl011_dma_remove(struct uart_amba_port *uap) 1238 { 1239 } 1240 1241 static inline void pl011_dma_startup(struct uart_amba_port *uap) 1242 { 1243 } 1244 1245 static inline void pl011_dma_shutdown(struct uart_amba_port *uap) 1246 { 1247 } 1248 1249 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) 1250 { 1251 return false; 1252 } 1253 1254 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 1255 { 1256 } 1257 1258 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 1259 { 1260 return false; 1261 } 1262 1263 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) 1264 { 1265 } 1266 1267 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1268 { 1269 } 1270 1271 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 1272 { 1273 return -EIO; 1274 } 1275 1276 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1277 { 1278 return false; 1279 } 1280 1281 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1282 { 1283 return false; 1284 } 1285 1286 #define pl011_dma_flush_buffer NULL 1287 #endif 1288 1289 static void pl011_rs485_tx_stop(struct uart_amba_port *uap) 1290 { 1291 struct uart_port *port = &uap->port; 1292 int i = 0; 1293 u32 cr; 1294 1295 /* Wait until hardware tx queue is empty */ 1296 while (!pl011_tx_empty(port)) { 1297 if (i == port->fifosize) { 1298 dev_warn(port->dev, 1299 "timeout while draining hardware tx queue\n"); 1300 break; 1301 } 1302 1303 udelay(uap->rs485_tx_drain_interval); 1304 i++; 1305 } 1306 1307 if (port->rs485.delay_rts_after_send) 1308 mdelay(port->rs485.delay_rts_after_send); 1309 1310 cr = pl011_read(uap, REG_CR); 1311 1312 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 1313 cr &= ~UART011_CR_RTS; 1314 else 1315 cr |= UART011_CR_RTS; 1316 1317 /* Disable the transmitter and reenable the transceiver */ 1318 cr &= ~UART011_CR_TXE; 1319 cr |= UART011_CR_RXE; 1320 pl011_write(cr, uap, REG_CR); 1321 1322 uap->rs485_tx_started = false; 1323 } 1324 1325 static void pl011_stop_tx(struct uart_port *port) 1326 { 1327 struct uart_amba_port *uap = 1328 container_of(port, struct uart_amba_port, port); 1329 1330 uap->im &= ~UART011_TXIM; 1331 pl011_write(uap->im, uap, REG_IMSC); 1332 pl011_dma_tx_stop(uap); 1333 1334 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) 1335 pl011_rs485_tx_stop(uap); 1336 } 1337 1338 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); 1339 1340 /* Start TX with programmed I/O only (no DMA) */ 1341 static void pl011_start_tx_pio(struct uart_amba_port *uap) 1342 { 1343 if (pl011_tx_chars(uap, false)) { 1344 uap->im |= UART011_TXIM; 1345 pl011_write(uap->im, uap, REG_IMSC); 1346 } 1347 } 1348 1349 static void pl011_start_tx(struct uart_port *port) 1350 { 1351 struct uart_amba_port *uap = 1352 container_of(port, struct uart_amba_port, port); 1353 1354 if (!pl011_dma_tx_start(uap)) 1355 pl011_start_tx_pio(uap); 1356 } 1357 1358 static void pl011_stop_rx(struct uart_port *port) 1359 { 1360 struct uart_amba_port *uap = 1361 container_of(port, struct uart_amba_port, port); 1362 1363 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| 1364 UART011_PEIM|UART011_BEIM|UART011_OEIM); 1365 pl011_write(uap->im, uap, REG_IMSC); 1366 1367 pl011_dma_rx_stop(uap); 1368 } 1369 1370 static void pl011_enable_ms(struct uart_port *port) 1371 { 1372 struct uart_amba_port *uap = 1373 container_of(port, struct uart_amba_port, port); 1374 1375 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; 1376 pl011_write(uap->im, uap, REG_IMSC); 1377 } 1378 1379 static void pl011_rx_chars(struct uart_amba_port *uap) 1380 __releases(&uap->port.lock) 1381 __acquires(&uap->port.lock) 1382 { 1383 pl011_fifo_to_tty(uap); 1384 1385 spin_unlock(&uap->port.lock); 1386 tty_flip_buffer_push(&uap->port.state->port); 1387 /* 1388 * If we were temporarily out of DMA mode for a while, 1389 * attempt to switch back to DMA mode again. 1390 */ 1391 if (pl011_dma_rx_available(uap)) { 1392 if (pl011_dma_rx_trigger_dma(uap)) { 1393 dev_dbg(uap->port.dev, "could not trigger RX DMA job " 1394 "fall back to interrupt mode again\n"); 1395 uap->im |= UART011_RXIM; 1396 pl011_write(uap->im, uap, REG_IMSC); 1397 } else { 1398 #ifdef CONFIG_DMA_ENGINE 1399 /* Start Rx DMA poll */ 1400 if (uap->dmarx.poll_rate) { 1401 uap->dmarx.last_jiffies = jiffies; 1402 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1403 mod_timer(&uap->dmarx.timer, 1404 jiffies + 1405 msecs_to_jiffies(uap->dmarx.poll_rate)); 1406 } 1407 #endif 1408 } 1409 } 1410 spin_lock(&uap->port.lock); 1411 } 1412 1413 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, 1414 bool from_irq) 1415 { 1416 if (unlikely(!from_irq) && 1417 pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1418 return false; /* unable to transmit character */ 1419 1420 pl011_write(c, uap, REG_DR); 1421 uap->port.icount.tx++; 1422 1423 return true; 1424 } 1425 1426 static void pl011_rs485_tx_start(struct uart_amba_port *uap) 1427 { 1428 struct uart_port *port = &uap->port; 1429 u32 cr; 1430 1431 /* Enable transmitter */ 1432 cr = pl011_read(uap, REG_CR); 1433 cr |= UART011_CR_TXE; 1434 1435 /* Disable receiver if half-duplex */ 1436 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1437 cr &= ~UART011_CR_RXE; 1438 1439 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 1440 cr &= ~UART011_CR_RTS; 1441 else 1442 cr |= UART011_CR_RTS; 1443 1444 pl011_write(cr, uap, REG_CR); 1445 1446 if (port->rs485.delay_rts_before_send) 1447 mdelay(port->rs485.delay_rts_before_send); 1448 1449 uap->rs485_tx_started = true; 1450 } 1451 1452 /* Returns true if tx interrupts have to be (kept) enabled */ 1453 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) 1454 { 1455 struct circ_buf *xmit = &uap->port.state->xmit; 1456 int count = uap->fifosize >> 1; 1457 1458 if (uap->port.x_char) { 1459 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) 1460 return true; 1461 uap->port.x_char = 0; 1462 --count; 1463 } 1464 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { 1465 pl011_stop_tx(&uap->port); 1466 return false; 1467 } 1468 1469 if ((uap->port.rs485.flags & SER_RS485_ENABLED) && 1470 !uap->rs485_tx_started) 1471 pl011_rs485_tx_start(uap); 1472 1473 /* If we are using DMA mode, try to send some characters. */ 1474 if (pl011_dma_tx_irq(uap)) 1475 return true; 1476 1477 do { 1478 if (likely(from_irq) && count-- == 0) 1479 break; 1480 1481 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) 1482 break; 1483 1484 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1485 } while (!uart_circ_empty(xmit)); 1486 1487 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1488 uart_write_wakeup(&uap->port); 1489 1490 if (uart_circ_empty(xmit)) { 1491 pl011_stop_tx(&uap->port); 1492 return false; 1493 } 1494 return true; 1495 } 1496 1497 static void pl011_modem_status(struct uart_amba_port *uap) 1498 { 1499 unsigned int status, delta; 1500 1501 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1502 1503 delta = status ^ uap->old_status; 1504 uap->old_status = status; 1505 1506 if (!delta) 1507 return; 1508 1509 if (delta & UART01x_FR_DCD) 1510 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 1511 1512 if (delta & uap->vendor->fr_dsr) 1513 uap->port.icount.dsr++; 1514 1515 if (delta & uap->vendor->fr_cts) 1516 uart_handle_cts_change(&uap->port, 1517 status & uap->vendor->fr_cts); 1518 1519 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 1520 } 1521 1522 static void check_apply_cts_event_workaround(struct uart_amba_port *uap) 1523 { 1524 if (!uap->vendor->cts_event_workaround) 1525 return; 1526 1527 /* workaround to make sure that all bits are unlocked.. */ 1528 pl011_write(0x00, uap, REG_ICR); 1529 1530 /* 1531 * WA: introduce 26ns(1 uart clk) delay before W1C; 1532 * single apb access will incur 2 pclk(133.12Mhz) delay, 1533 * so add 2 dummy reads 1534 */ 1535 pl011_read(uap, REG_ICR); 1536 pl011_read(uap, REG_ICR); 1537 } 1538 1539 static irqreturn_t pl011_int(int irq, void *dev_id) 1540 { 1541 struct uart_amba_port *uap = dev_id; 1542 unsigned long flags; 1543 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 1544 int handled = 0; 1545 1546 spin_lock_irqsave(&uap->port.lock, flags); 1547 status = pl011_read(uap, REG_RIS) & uap->im; 1548 if (status) { 1549 do { 1550 check_apply_cts_event_workaround(uap); 1551 1552 pl011_write(status & ~(UART011_TXIS|UART011_RTIS| 1553 UART011_RXIS), 1554 uap, REG_ICR); 1555 1556 if (status & (UART011_RTIS|UART011_RXIS)) { 1557 if (pl011_dma_rx_running(uap)) 1558 pl011_dma_rx_irq(uap); 1559 else 1560 pl011_rx_chars(uap); 1561 } 1562 if (status & (UART011_DSRMIS|UART011_DCDMIS| 1563 UART011_CTSMIS|UART011_RIMIS)) 1564 pl011_modem_status(uap); 1565 if (status & UART011_TXIS) 1566 pl011_tx_chars(uap, true); 1567 1568 if (pass_counter-- == 0) 1569 break; 1570 1571 status = pl011_read(uap, REG_RIS) & uap->im; 1572 } while (status != 0); 1573 handled = 1; 1574 } 1575 1576 spin_unlock_irqrestore(&uap->port.lock, flags); 1577 1578 return IRQ_RETVAL(handled); 1579 } 1580 1581 static unsigned int pl011_tx_empty(struct uart_port *port) 1582 { 1583 struct uart_amba_port *uap = 1584 container_of(port, struct uart_amba_port, port); 1585 1586 /* Allow feature register bits to be inverted to work around errata */ 1587 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; 1588 1589 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? 1590 0 : TIOCSER_TEMT; 1591 } 1592 1593 static unsigned int pl011_get_mctrl(struct uart_port *port) 1594 { 1595 struct uart_amba_port *uap = 1596 container_of(port, struct uart_amba_port, port); 1597 unsigned int result = 0; 1598 unsigned int status = pl011_read(uap, REG_FR); 1599 1600 #define TIOCMBIT(uartbit, tiocmbit) \ 1601 if (status & uartbit) \ 1602 result |= tiocmbit 1603 1604 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); 1605 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR); 1606 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS); 1607 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG); 1608 #undef TIOCMBIT 1609 return result; 1610 } 1611 1612 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) 1613 { 1614 struct uart_amba_port *uap = 1615 container_of(port, struct uart_amba_port, port); 1616 unsigned int cr; 1617 1618 if (port->rs485.flags & SER_RS485_ENABLED) 1619 mctrl &= ~TIOCM_RTS; 1620 1621 cr = pl011_read(uap, REG_CR); 1622 1623 #define TIOCMBIT(tiocmbit, uartbit) \ 1624 if (mctrl & tiocmbit) \ 1625 cr |= uartbit; \ 1626 else \ 1627 cr &= ~uartbit 1628 1629 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); 1630 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); 1631 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); 1632 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); 1633 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); 1634 1635 if (port->status & UPSTAT_AUTORTS) { 1636 /* We need to disable auto-RTS if we want to turn RTS off */ 1637 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); 1638 } 1639 #undef TIOCMBIT 1640 1641 pl011_write(cr, uap, REG_CR); 1642 } 1643 1644 static void pl011_break_ctl(struct uart_port *port, int break_state) 1645 { 1646 struct uart_amba_port *uap = 1647 container_of(port, struct uart_amba_port, port); 1648 unsigned long flags; 1649 unsigned int lcr_h; 1650 1651 spin_lock_irqsave(&uap->port.lock, flags); 1652 lcr_h = pl011_read(uap, REG_LCRH_TX); 1653 if (break_state == -1) 1654 lcr_h |= UART01x_LCRH_BRK; 1655 else 1656 lcr_h &= ~UART01x_LCRH_BRK; 1657 pl011_write(lcr_h, uap, REG_LCRH_TX); 1658 spin_unlock_irqrestore(&uap->port.lock, flags); 1659 } 1660 1661 #ifdef CONFIG_CONSOLE_POLL 1662 1663 static void pl011_quiesce_irqs(struct uart_port *port) 1664 { 1665 struct uart_amba_port *uap = 1666 container_of(port, struct uart_amba_port, port); 1667 1668 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); 1669 /* 1670 * There is no way to clear TXIM as this is "ready to transmit IRQ", so 1671 * we simply mask it. start_tx() will unmask it. 1672 * 1673 * Note we can race with start_tx(), and if the race happens, the 1674 * polling user might get another interrupt just after we clear it. 1675 * But it should be OK and can happen even w/o the race, e.g. 1676 * controller immediately got some new data and raised the IRQ. 1677 * 1678 * And whoever uses polling routines assumes that it manages the device 1679 * (including tx queue), so we're also fine with start_tx()'s caller 1680 * side. 1681 */ 1682 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, 1683 REG_IMSC); 1684 } 1685 1686 static int pl011_get_poll_char(struct uart_port *port) 1687 { 1688 struct uart_amba_port *uap = 1689 container_of(port, struct uart_amba_port, port); 1690 unsigned int status; 1691 1692 /* 1693 * The caller might need IRQs lowered, e.g. if used with KDB NMI 1694 * debugger. 1695 */ 1696 pl011_quiesce_irqs(port); 1697 1698 status = pl011_read(uap, REG_FR); 1699 if (status & UART01x_FR_RXFE) 1700 return NO_POLL_CHAR; 1701 1702 return pl011_read(uap, REG_DR); 1703 } 1704 1705 static void pl011_put_poll_char(struct uart_port *port, 1706 unsigned char ch) 1707 { 1708 struct uart_amba_port *uap = 1709 container_of(port, struct uart_amba_port, port); 1710 1711 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1712 cpu_relax(); 1713 1714 pl011_write(ch, uap, REG_DR); 1715 } 1716 1717 #endif /* CONFIG_CONSOLE_POLL */ 1718 1719 static int pl011_hwinit(struct uart_port *port) 1720 { 1721 struct uart_amba_port *uap = 1722 container_of(port, struct uart_amba_port, port); 1723 int retval; 1724 1725 /* Optionaly enable pins to be muxed in and configured */ 1726 pinctrl_pm_select_default_state(port->dev); 1727 1728 /* 1729 * Try to enable the clock producer. 1730 */ 1731 retval = clk_prepare_enable(uap->clk); 1732 if (retval) 1733 return retval; 1734 1735 uap->port.uartclk = clk_get_rate(uap->clk); 1736 1737 /* Clear pending error and receive interrupts */ 1738 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 1739 UART011_FEIS | UART011_RTIS | UART011_RXIS, 1740 uap, REG_ICR); 1741 1742 /* 1743 * Save interrupts enable mask, and enable RX interrupts in case if 1744 * the interrupt is used for NMI entry. 1745 */ 1746 uap->im = pl011_read(uap, REG_IMSC); 1747 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); 1748 1749 if (dev_get_platdata(uap->port.dev)) { 1750 struct amba_pl011_data *plat; 1751 1752 plat = dev_get_platdata(uap->port.dev); 1753 if (plat->init) 1754 plat->init(); 1755 } 1756 return 0; 1757 } 1758 1759 static bool pl011_split_lcrh(const struct uart_amba_port *uap) 1760 { 1761 return pl011_reg_to_offset(uap, REG_LCRH_RX) != 1762 pl011_reg_to_offset(uap, REG_LCRH_TX); 1763 } 1764 1765 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) 1766 { 1767 pl011_write(lcr_h, uap, REG_LCRH_RX); 1768 if (pl011_split_lcrh(uap)) { 1769 int i; 1770 /* 1771 * Wait 10 PCLKs before writing LCRH_TX register, 1772 * to get this delay write read only register 10 times 1773 */ 1774 for (i = 0; i < 10; ++i) 1775 pl011_write(0xff, uap, REG_MIS); 1776 pl011_write(lcr_h, uap, REG_LCRH_TX); 1777 } 1778 } 1779 1780 static int pl011_allocate_irq(struct uart_amba_port *uap) 1781 { 1782 pl011_write(uap->im, uap, REG_IMSC); 1783 1784 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); 1785 } 1786 1787 /* 1788 * Enable interrupts, only timeouts when using DMA 1789 * if initial RX DMA job failed, start in interrupt mode 1790 * as well. 1791 */ 1792 static void pl011_enable_interrupts(struct uart_amba_port *uap) 1793 { 1794 unsigned int i; 1795 1796 spin_lock_irq(&uap->port.lock); 1797 1798 /* Clear out any spuriously appearing RX interrupts */ 1799 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); 1800 1801 /* 1802 * RXIS is asserted only when the RX FIFO transitions from below 1803 * to above the trigger threshold. If the RX FIFO is already 1804 * full to the threshold this can't happen and RXIS will now be 1805 * stuck off. Drain the RX FIFO explicitly to fix this: 1806 */ 1807 for (i = 0; i < uap->fifosize * 2; ++i) { 1808 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE) 1809 break; 1810 1811 pl011_read(uap, REG_DR); 1812 } 1813 1814 uap->im = UART011_RTIM; 1815 if (!pl011_dma_rx_running(uap)) 1816 uap->im |= UART011_RXIM; 1817 pl011_write(uap->im, uap, REG_IMSC); 1818 spin_unlock_irq(&uap->port.lock); 1819 } 1820 1821 static int pl011_startup(struct uart_port *port) 1822 { 1823 struct uart_amba_port *uap = 1824 container_of(port, struct uart_amba_port, port); 1825 unsigned int cr; 1826 int retval; 1827 1828 retval = pl011_hwinit(port); 1829 if (retval) 1830 goto clk_dis; 1831 1832 retval = pl011_allocate_irq(uap); 1833 if (retval) 1834 goto clk_dis; 1835 1836 pl011_write(uap->vendor->ifls, uap, REG_IFLS); 1837 1838 spin_lock_irq(&uap->port.lock); 1839 1840 /* restore RTS and DTR */ 1841 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); 1842 cr |= UART01x_CR_UARTEN | UART011_CR_RXE; 1843 1844 if (port->rs485.flags & SER_RS485_ENABLED) { 1845 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 1846 cr &= ~UART011_CR_RTS; 1847 else 1848 cr |= UART011_CR_RTS; 1849 } else { 1850 cr |= UART011_CR_TXE; 1851 } 1852 1853 pl011_write(cr, uap, REG_CR); 1854 1855 spin_unlock_irq(&uap->port.lock); 1856 1857 /* 1858 * initialise the old status of the modem signals 1859 */ 1860 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1861 1862 /* Startup DMA */ 1863 pl011_dma_startup(uap); 1864 1865 pl011_enable_interrupts(uap); 1866 1867 return 0; 1868 1869 clk_dis: 1870 clk_disable_unprepare(uap->clk); 1871 return retval; 1872 } 1873 1874 static int sbsa_uart_startup(struct uart_port *port) 1875 { 1876 struct uart_amba_port *uap = 1877 container_of(port, struct uart_amba_port, port); 1878 int retval; 1879 1880 retval = pl011_hwinit(port); 1881 if (retval) 1882 return retval; 1883 1884 retval = pl011_allocate_irq(uap); 1885 if (retval) 1886 return retval; 1887 1888 /* The SBSA UART does not support any modem status lines. */ 1889 uap->old_status = 0; 1890 1891 pl011_enable_interrupts(uap); 1892 1893 return 0; 1894 } 1895 1896 static void pl011_shutdown_channel(struct uart_amba_port *uap, 1897 unsigned int lcrh) 1898 { 1899 unsigned long val; 1900 1901 val = pl011_read(uap, lcrh); 1902 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); 1903 pl011_write(val, uap, lcrh); 1904 } 1905 1906 /* 1907 * disable the port. It should not disable RTS and DTR. 1908 * Also RTS and DTR state should be preserved to restore 1909 * it during startup(). 1910 */ 1911 static void pl011_disable_uart(struct uart_amba_port *uap) 1912 { 1913 unsigned int cr; 1914 1915 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1916 spin_lock_irq(&uap->port.lock); 1917 cr = pl011_read(uap, REG_CR); 1918 uap->old_cr = cr; 1919 cr &= UART011_CR_RTS | UART011_CR_DTR; 1920 cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 1921 pl011_write(cr, uap, REG_CR); 1922 spin_unlock_irq(&uap->port.lock); 1923 1924 /* 1925 * disable break condition and fifos 1926 */ 1927 pl011_shutdown_channel(uap, REG_LCRH_RX); 1928 if (pl011_split_lcrh(uap)) 1929 pl011_shutdown_channel(uap, REG_LCRH_TX); 1930 } 1931 1932 static void pl011_disable_interrupts(struct uart_amba_port *uap) 1933 { 1934 spin_lock_irq(&uap->port.lock); 1935 1936 /* mask all interrupts and clear all pending ones */ 1937 uap->im = 0; 1938 pl011_write(uap->im, uap, REG_IMSC); 1939 pl011_write(0xffff, uap, REG_ICR); 1940 1941 spin_unlock_irq(&uap->port.lock); 1942 } 1943 1944 static void pl011_shutdown(struct uart_port *port) 1945 { 1946 struct uart_amba_port *uap = 1947 container_of(port, struct uart_amba_port, port); 1948 1949 pl011_disable_interrupts(uap); 1950 1951 pl011_dma_shutdown(uap); 1952 1953 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) 1954 pl011_rs485_tx_stop(uap); 1955 1956 free_irq(uap->port.irq, uap); 1957 1958 pl011_disable_uart(uap); 1959 1960 /* 1961 * Shut down the clock producer 1962 */ 1963 clk_disable_unprepare(uap->clk); 1964 /* Optionally let pins go into sleep states */ 1965 pinctrl_pm_select_sleep_state(port->dev); 1966 1967 if (dev_get_platdata(uap->port.dev)) { 1968 struct amba_pl011_data *plat; 1969 1970 plat = dev_get_platdata(uap->port.dev); 1971 if (plat->exit) 1972 plat->exit(); 1973 } 1974 1975 if (uap->port.ops->flush_buffer) 1976 uap->port.ops->flush_buffer(port); 1977 } 1978 1979 static void sbsa_uart_shutdown(struct uart_port *port) 1980 { 1981 struct uart_amba_port *uap = 1982 container_of(port, struct uart_amba_port, port); 1983 1984 pl011_disable_interrupts(uap); 1985 1986 free_irq(uap->port.irq, uap); 1987 1988 if (uap->port.ops->flush_buffer) 1989 uap->port.ops->flush_buffer(port); 1990 } 1991 1992 static void 1993 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) 1994 { 1995 port->read_status_mask = UART011_DR_OE | 255; 1996 if (termios->c_iflag & INPCK) 1997 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; 1998 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1999 port->read_status_mask |= UART011_DR_BE; 2000 2001 /* 2002 * Characters to ignore 2003 */ 2004 port->ignore_status_mask = 0; 2005 if (termios->c_iflag & IGNPAR) 2006 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; 2007 if (termios->c_iflag & IGNBRK) { 2008 port->ignore_status_mask |= UART011_DR_BE; 2009 /* 2010 * If we're ignoring parity and break indicators, 2011 * ignore overruns too (for real raw support). 2012 */ 2013 if (termios->c_iflag & IGNPAR) 2014 port->ignore_status_mask |= UART011_DR_OE; 2015 } 2016 2017 /* 2018 * Ignore all characters if CREAD is not set. 2019 */ 2020 if ((termios->c_cflag & CREAD) == 0) 2021 port->ignore_status_mask |= UART_DUMMY_DR_RX; 2022 } 2023 2024 static void 2025 pl011_set_termios(struct uart_port *port, struct ktermios *termios, 2026 struct ktermios *old) 2027 { 2028 struct uart_amba_port *uap = 2029 container_of(port, struct uart_amba_port, port); 2030 unsigned int lcr_h, old_cr; 2031 unsigned long flags; 2032 unsigned int baud, quot, clkdiv; 2033 unsigned int bits; 2034 2035 if (uap->vendor->oversampling) 2036 clkdiv = 8; 2037 else 2038 clkdiv = 16; 2039 2040 /* 2041 * Ask the core to calculate the divisor for us. 2042 */ 2043 baud = uart_get_baud_rate(port, termios, old, 0, 2044 port->uartclk / clkdiv); 2045 #ifdef CONFIG_DMA_ENGINE 2046 /* 2047 * Adjust RX DMA polling rate with baud rate if not specified. 2048 */ 2049 if (uap->dmarx.auto_poll_rate) 2050 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); 2051 #endif 2052 2053 if (baud > port->uartclk/16) 2054 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); 2055 else 2056 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); 2057 2058 switch (termios->c_cflag & CSIZE) { 2059 case CS5: 2060 lcr_h = UART01x_LCRH_WLEN_5; 2061 break; 2062 case CS6: 2063 lcr_h = UART01x_LCRH_WLEN_6; 2064 break; 2065 case CS7: 2066 lcr_h = UART01x_LCRH_WLEN_7; 2067 break; 2068 default: // CS8 2069 lcr_h = UART01x_LCRH_WLEN_8; 2070 break; 2071 } 2072 if (termios->c_cflag & CSTOPB) 2073 lcr_h |= UART01x_LCRH_STP2; 2074 if (termios->c_cflag & PARENB) { 2075 lcr_h |= UART01x_LCRH_PEN; 2076 if (!(termios->c_cflag & PARODD)) 2077 lcr_h |= UART01x_LCRH_EPS; 2078 if (termios->c_cflag & CMSPAR) 2079 lcr_h |= UART011_LCRH_SPS; 2080 } 2081 if (uap->fifosize > 1) 2082 lcr_h |= UART01x_LCRH_FEN; 2083 2084 bits = tty_get_frame_size(termios->c_cflag); 2085 2086 spin_lock_irqsave(&port->lock, flags); 2087 2088 /* 2089 * Update the per-port timeout. 2090 */ 2091 uart_update_timeout(port, termios->c_cflag, baud); 2092 2093 /* 2094 * Calculate the approximated time it takes to transmit one character 2095 * with the given baud rate. We use this as the poll interval when we 2096 * wait for the tx queue to empty. 2097 */ 2098 uap->rs485_tx_drain_interval = (bits * 1000 * 1000) / baud; 2099 2100 pl011_setup_status_masks(port, termios); 2101 2102 if (UART_ENABLE_MS(port, termios->c_cflag)) 2103 pl011_enable_ms(port); 2104 2105 if (port->rs485.flags & SER_RS485_ENABLED) 2106 termios->c_cflag &= ~CRTSCTS; 2107 2108 /* first, disable everything */ 2109 old_cr = pl011_read(uap, REG_CR); 2110 pl011_write(0, uap, REG_CR); 2111 2112 if (termios->c_cflag & CRTSCTS) { 2113 if (old_cr & UART011_CR_RTS) 2114 old_cr |= UART011_CR_RTSEN; 2115 2116 old_cr |= UART011_CR_CTSEN; 2117 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 2118 } else { 2119 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); 2120 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 2121 } 2122 2123 if (uap->vendor->oversampling) { 2124 if (baud > port->uartclk / 16) 2125 old_cr |= ST_UART011_CR_OVSFACT; 2126 else 2127 old_cr &= ~ST_UART011_CR_OVSFACT; 2128 } 2129 2130 /* 2131 * Workaround for the ST Micro oversampling variants to 2132 * increase the bitrate slightly, by lowering the divisor, 2133 * to avoid delayed sampling of start bit at high speeds, 2134 * else we see data corruption. 2135 */ 2136 if (uap->vendor->oversampling) { 2137 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) 2138 quot -= 1; 2139 else if ((baud > 3250000) && (quot > 2)) 2140 quot -= 2; 2141 } 2142 /* Set baud rate */ 2143 pl011_write(quot & 0x3f, uap, REG_FBRD); 2144 pl011_write(quot >> 6, uap, REG_IBRD); 2145 2146 /* 2147 * ----------v----------v----------v----------v----- 2148 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER 2149 * REG_FBRD & REG_IBRD. 2150 * ----------^----------^----------^----------^----- 2151 */ 2152 pl011_write_lcr_h(uap, lcr_h); 2153 pl011_write(old_cr, uap, REG_CR); 2154 2155 spin_unlock_irqrestore(&port->lock, flags); 2156 } 2157 2158 static void 2159 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, 2160 struct ktermios *old) 2161 { 2162 struct uart_amba_port *uap = 2163 container_of(port, struct uart_amba_port, port); 2164 unsigned long flags; 2165 2166 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); 2167 2168 /* The SBSA UART only supports 8n1 without hardware flow control. */ 2169 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 2170 termios->c_cflag &= ~(CMSPAR | CRTSCTS); 2171 termios->c_cflag |= CS8 | CLOCAL; 2172 2173 spin_lock_irqsave(&port->lock, flags); 2174 uart_update_timeout(port, CS8, uap->fixed_baud); 2175 pl011_setup_status_masks(port, termios); 2176 spin_unlock_irqrestore(&port->lock, flags); 2177 } 2178 2179 static const char *pl011_type(struct uart_port *port) 2180 { 2181 struct uart_amba_port *uap = 2182 container_of(port, struct uart_amba_port, port); 2183 return uap->port.type == PORT_AMBA ? uap->type : NULL; 2184 } 2185 2186 /* 2187 * Release the memory region(s) being used by 'port' 2188 */ 2189 static void pl011_release_port(struct uart_port *port) 2190 { 2191 release_mem_region(port->mapbase, SZ_4K); 2192 } 2193 2194 /* 2195 * Request the memory region(s) being used by 'port' 2196 */ 2197 static int pl011_request_port(struct uart_port *port) 2198 { 2199 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") 2200 != NULL ? 0 : -EBUSY; 2201 } 2202 2203 /* 2204 * Configure/autoconfigure the port. 2205 */ 2206 static void pl011_config_port(struct uart_port *port, int flags) 2207 { 2208 if (flags & UART_CONFIG_TYPE) { 2209 port->type = PORT_AMBA; 2210 pl011_request_port(port); 2211 } 2212 } 2213 2214 /* 2215 * verify the new serial_struct (for TIOCSSERIAL). 2216 */ 2217 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) 2218 { 2219 int ret = 0; 2220 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 2221 ret = -EINVAL; 2222 if (ser->irq < 0 || ser->irq >= nr_irqs) 2223 ret = -EINVAL; 2224 if (ser->baud_base < 9600) 2225 ret = -EINVAL; 2226 return ret; 2227 } 2228 2229 static int pl011_rs485_config(struct uart_port *port, 2230 struct serial_rs485 *rs485) 2231 { 2232 struct uart_amba_port *uap = 2233 container_of(port, struct uart_amba_port, port); 2234 2235 /* pick sane settings if the user hasn't */ 2236 if (!(rs485->flags & SER_RS485_RTS_ON_SEND) == 2237 !(rs485->flags & SER_RS485_RTS_AFTER_SEND)) { 2238 rs485->flags |= SER_RS485_RTS_ON_SEND; 2239 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 2240 } 2241 /* clamp the delays to [0, 100ms] */ 2242 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U); 2243 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U); 2244 memset(rs485->padding, 0, sizeof(rs485->padding)); 2245 2246 if (port->rs485.flags & SER_RS485_ENABLED) 2247 pl011_rs485_tx_stop(uap); 2248 2249 /* Set new configuration */ 2250 port->rs485 = *rs485; 2251 2252 /* Make sure auto RTS is disabled */ 2253 if (port->rs485.flags & SER_RS485_ENABLED) { 2254 u32 cr = pl011_read(uap, REG_CR); 2255 2256 cr &= ~UART011_CR_RTSEN; 2257 pl011_write(cr, uap, REG_CR); 2258 port->status &= ~UPSTAT_AUTORTS; 2259 } 2260 2261 return 0; 2262 } 2263 2264 static const struct uart_ops amba_pl011_pops = { 2265 .tx_empty = pl011_tx_empty, 2266 .set_mctrl = pl011_set_mctrl, 2267 .get_mctrl = pl011_get_mctrl, 2268 .stop_tx = pl011_stop_tx, 2269 .start_tx = pl011_start_tx, 2270 .stop_rx = pl011_stop_rx, 2271 .enable_ms = pl011_enable_ms, 2272 .break_ctl = pl011_break_ctl, 2273 .startup = pl011_startup, 2274 .shutdown = pl011_shutdown, 2275 .flush_buffer = pl011_dma_flush_buffer, 2276 .set_termios = pl011_set_termios, 2277 .type = pl011_type, 2278 .release_port = pl011_release_port, 2279 .request_port = pl011_request_port, 2280 .config_port = pl011_config_port, 2281 .verify_port = pl011_verify_port, 2282 #ifdef CONFIG_CONSOLE_POLL 2283 .poll_init = pl011_hwinit, 2284 .poll_get_char = pl011_get_poll_char, 2285 .poll_put_char = pl011_put_poll_char, 2286 #endif 2287 }; 2288 2289 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 2290 { 2291 } 2292 2293 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) 2294 { 2295 return 0; 2296 } 2297 2298 static const struct uart_ops sbsa_uart_pops = { 2299 .tx_empty = pl011_tx_empty, 2300 .set_mctrl = sbsa_uart_set_mctrl, 2301 .get_mctrl = sbsa_uart_get_mctrl, 2302 .stop_tx = pl011_stop_tx, 2303 .start_tx = pl011_start_tx, 2304 .stop_rx = pl011_stop_rx, 2305 .startup = sbsa_uart_startup, 2306 .shutdown = sbsa_uart_shutdown, 2307 .set_termios = sbsa_uart_set_termios, 2308 .type = pl011_type, 2309 .release_port = pl011_release_port, 2310 .request_port = pl011_request_port, 2311 .config_port = pl011_config_port, 2312 .verify_port = pl011_verify_port, 2313 #ifdef CONFIG_CONSOLE_POLL 2314 .poll_init = pl011_hwinit, 2315 .poll_get_char = pl011_get_poll_char, 2316 .poll_put_char = pl011_put_poll_char, 2317 #endif 2318 }; 2319 2320 static struct uart_amba_port *amba_ports[UART_NR]; 2321 2322 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE 2323 2324 static void pl011_console_putchar(struct uart_port *port, int ch) 2325 { 2326 struct uart_amba_port *uap = 2327 container_of(port, struct uart_amba_port, port); 2328 2329 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 2330 cpu_relax(); 2331 pl011_write(ch, uap, REG_DR); 2332 } 2333 2334 static void 2335 pl011_console_write(struct console *co, const char *s, unsigned int count) 2336 { 2337 struct uart_amba_port *uap = amba_ports[co->index]; 2338 unsigned int old_cr = 0, new_cr; 2339 unsigned long flags; 2340 int locked = 1; 2341 2342 clk_enable(uap->clk); 2343 2344 local_irq_save(flags); 2345 if (uap->port.sysrq) 2346 locked = 0; 2347 else if (oops_in_progress) 2348 locked = spin_trylock(&uap->port.lock); 2349 else 2350 spin_lock(&uap->port.lock); 2351 2352 /* 2353 * First save the CR then disable the interrupts 2354 */ 2355 if (!uap->vendor->always_enabled) { 2356 old_cr = pl011_read(uap, REG_CR); 2357 new_cr = old_cr & ~UART011_CR_CTSEN; 2358 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 2359 pl011_write(new_cr, uap, REG_CR); 2360 } 2361 2362 uart_console_write(&uap->port, s, count, pl011_console_putchar); 2363 2364 /* 2365 * Finally, wait for transmitter to become empty and restore the 2366 * TCR. Allow feature register bits to be inverted to work around 2367 * errata. 2368 */ 2369 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) 2370 & uap->vendor->fr_busy) 2371 cpu_relax(); 2372 if (!uap->vendor->always_enabled) 2373 pl011_write(old_cr, uap, REG_CR); 2374 2375 if (locked) 2376 spin_unlock(&uap->port.lock); 2377 local_irq_restore(flags); 2378 2379 clk_disable(uap->clk); 2380 } 2381 2382 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud, 2383 int *parity, int *bits) 2384 { 2385 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) { 2386 unsigned int lcr_h, ibrd, fbrd; 2387 2388 lcr_h = pl011_read(uap, REG_LCRH_TX); 2389 2390 *parity = 'n'; 2391 if (lcr_h & UART01x_LCRH_PEN) { 2392 if (lcr_h & UART01x_LCRH_EPS) 2393 *parity = 'e'; 2394 else 2395 *parity = 'o'; 2396 } 2397 2398 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 2399 *bits = 7; 2400 else 2401 *bits = 8; 2402 2403 ibrd = pl011_read(uap, REG_IBRD); 2404 fbrd = pl011_read(uap, REG_FBRD); 2405 2406 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); 2407 2408 if (uap->vendor->oversampling) { 2409 if (pl011_read(uap, REG_CR) 2410 & ST_UART011_CR_OVSFACT) 2411 *baud *= 2; 2412 } 2413 } 2414 } 2415 2416 static int pl011_console_setup(struct console *co, char *options) 2417 { 2418 struct uart_amba_port *uap; 2419 int baud = 38400; 2420 int bits = 8; 2421 int parity = 'n'; 2422 int flow = 'n'; 2423 int ret; 2424 2425 /* 2426 * Check whether an invalid uart number has been specified, and 2427 * if so, search for the first available port that does have 2428 * console support. 2429 */ 2430 if (co->index >= UART_NR) 2431 co->index = 0; 2432 uap = amba_ports[co->index]; 2433 if (!uap) 2434 return -ENODEV; 2435 2436 /* Allow pins to be muxed in and configured */ 2437 pinctrl_pm_select_default_state(uap->port.dev); 2438 2439 ret = clk_prepare(uap->clk); 2440 if (ret) 2441 return ret; 2442 2443 if (dev_get_platdata(uap->port.dev)) { 2444 struct amba_pl011_data *plat; 2445 2446 plat = dev_get_platdata(uap->port.dev); 2447 if (plat->init) 2448 plat->init(); 2449 } 2450 2451 uap->port.uartclk = clk_get_rate(uap->clk); 2452 2453 if (uap->vendor->fixed_options) { 2454 baud = uap->fixed_baud; 2455 } else { 2456 if (options) 2457 uart_parse_options(options, 2458 &baud, &parity, &bits, &flow); 2459 else 2460 pl011_console_get_options(uap, &baud, &parity, &bits); 2461 } 2462 2463 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 2464 } 2465 2466 /** 2467 * pl011_console_match - non-standard console matching 2468 * @co: registering console 2469 * @name: name from console command line 2470 * @idx: index from console command line 2471 * @options: ptr to option string from console command line 2472 * 2473 * Only attempts to match console command lines of the form: 2474 * console=pl011,mmio|mmio32,<addr>[,<options>] 2475 * console=pl011,0x<addr>[,<options>] 2476 * This form is used to register an initial earlycon boot console and 2477 * replace it with the amba_console at pl011 driver init. 2478 * 2479 * Performs console setup for a match (as required by interface) 2480 * If no <options> are specified, then assume the h/w is already setup. 2481 * 2482 * Returns 0 if console matches; otherwise non-zero to use default matching 2483 */ 2484 static int pl011_console_match(struct console *co, char *name, int idx, 2485 char *options) 2486 { 2487 unsigned char iotype; 2488 resource_size_t addr; 2489 int i; 2490 2491 /* 2492 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum 2493 * have a distinct console name, so make sure we check for that. 2494 * The actual implementation of the erratum occurs in the probe 2495 * function. 2496 */ 2497 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0)) 2498 return -ENODEV; 2499 2500 if (uart_parse_earlycon(options, &iotype, &addr, &options)) 2501 return -ENODEV; 2502 2503 if (iotype != UPIO_MEM && iotype != UPIO_MEM32) 2504 return -ENODEV; 2505 2506 /* try to match the port specified on the command line */ 2507 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2508 struct uart_port *port; 2509 2510 if (!amba_ports[i]) 2511 continue; 2512 2513 port = &amba_ports[i]->port; 2514 2515 if (port->mapbase != addr) 2516 continue; 2517 2518 co->index = i; 2519 port->cons = co; 2520 return pl011_console_setup(co, options); 2521 } 2522 2523 return -ENODEV; 2524 } 2525 2526 static struct uart_driver amba_reg; 2527 static struct console amba_console = { 2528 .name = "ttyAMA", 2529 .write = pl011_console_write, 2530 .device = uart_console_device, 2531 .setup = pl011_console_setup, 2532 .match = pl011_console_match, 2533 .flags = CON_PRINTBUFFER | CON_ANYTIME, 2534 .index = -1, 2535 .data = &amba_reg, 2536 }; 2537 2538 #define AMBA_CONSOLE (&amba_console) 2539 2540 static void qdf2400_e44_putc(struct uart_port *port, int c) 2541 { 2542 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2543 cpu_relax(); 2544 writel(c, port->membase + UART01x_DR); 2545 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) 2546 cpu_relax(); 2547 } 2548 2549 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n) 2550 { 2551 struct earlycon_device *dev = con->data; 2552 2553 uart_console_write(&dev->port, s, n, qdf2400_e44_putc); 2554 } 2555 2556 static void pl011_putc(struct uart_port *port, int c) 2557 { 2558 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2559 cpu_relax(); 2560 if (port->iotype == UPIO_MEM32) 2561 writel(c, port->membase + UART01x_DR); 2562 else 2563 writeb(c, port->membase + UART01x_DR); 2564 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) 2565 cpu_relax(); 2566 } 2567 2568 static void pl011_early_write(struct console *con, const char *s, unsigned n) 2569 { 2570 struct earlycon_device *dev = con->data; 2571 2572 uart_console_write(&dev->port, s, n, pl011_putc); 2573 } 2574 2575 #ifdef CONFIG_CONSOLE_POLL 2576 static int pl011_getc(struct uart_port *port) 2577 { 2578 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE) 2579 return NO_POLL_CHAR; 2580 2581 if (port->iotype == UPIO_MEM32) 2582 return readl(port->membase + UART01x_DR); 2583 else 2584 return readb(port->membase + UART01x_DR); 2585 } 2586 2587 static int pl011_early_read(struct console *con, char *s, unsigned int n) 2588 { 2589 struct earlycon_device *dev = con->data; 2590 int ch, num_read = 0; 2591 2592 while (num_read < n) { 2593 ch = pl011_getc(&dev->port); 2594 if (ch == NO_POLL_CHAR) 2595 break; 2596 2597 s[num_read++] = ch; 2598 } 2599 2600 return num_read; 2601 } 2602 #else 2603 #define pl011_early_read NULL 2604 #endif 2605 2606 /* 2607 * On non-ACPI systems, earlycon is enabled by specifying 2608 * "earlycon=pl011,<address>" on the kernel command line. 2609 * 2610 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table, 2611 * by specifying only "earlycon" on the command line. Because it requires 2612 * SPCR, the console starts after ACPI is parsed, which is later than a 2613 * traditional early console. 2614 * 2615 * To get the traditional early console that starts before ACPI is parsed, 2616 * specify the full "earlycon=pl011,<address>" option. 2617 */ 2618 static int __init pl011_early_console_setup(struct earlycon_device *device, 2619 const char *opt) 2620 { 2621 if (!device->port.membase) 2622 return -ENODEV; 2623 2624 device->con->write = pl011_early_write; 2625 device->con->read = pl011_early_read; 2626 2627 return 0; 2628 } 2629 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); 2630 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup); 2631 2632 /* 2633 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by 2634 * Erratum 44, traditional earlycon can be enabled by specifying 2635 * "earlycon=qdf2400_e44,<address>". Any options are ignored. 2636 * 2637 * Alternatively, you can just specify "earlycon", and the early console 2638 * will be enabled with the information from the SPCR table. In this 2639 * case, the SPCR code will detect the need for the E44 work-around, 2640 * and set the console name to "qdf2400_e44". 2641 */ 2642 static int __init 2643 qdf2400_e44_early_console_setup(struct earlycon_device *device, 2644 const char *opt) 2645 { 2646 if (!device->port.membase) 2647 return -ENODEV; 2648 2649 device->con->write = qdf2400_e44_early_write; 2650 return 0; 2651 } 2652 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup); 2653 2654 #else 2655 #define AMBA_CONSOLE NULL 2656 #endif 2657 2658 static struct uart_driver amba_reg = { 2659 .owner = THIS_MODULE, 2660 .driver_name = "ttyAMA", 2661 .dev_name = "ttyAMA", 2662 .major = SERIAL_AMBA_MAJOR, 2663 .minor = SERIAL_AMBA_MINOR, 2664 .nr = UART_NR, 2665 .cons = AMBA_CONSOLE, 2666 }; 2667 2668 static int pl011_probe_dt_alias(int index, struct device *dev) 2669 { 2670 struct device_node *np; 2671 static bool seen_dev_with_alias = false; 2672 static bool seen_dev_without_alias = false; 2673 int ret = index; 2674 2675 if (!IS_ENABLED(CONFIG_OF)) 2676 return ret; 2677 2678 np = dev->of_node; 2679 if (!np) 2680 return ret; 2681 2682 ret = of_alias_get_id(np, "serial"); 2683 if (ret < 0) { 2684 seen_dev_without_alias = true; 2685 ret = index; 2686 } else { 2687 seen_dev_with_alias = true; 2688 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { 2689 dev_warn(dev, "requested serial port %d not available.\n", ret); 2690 ret = index; 2691 } 2692 } 2693 2694 if (seen_dev_with_alias && seen_dev_without_alias) 2695 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); 2696 2697 return ret; 2698 } 2699 2700 /* unregisters the driver also if no more ports are left */ 2701 static void pl011_unregister_port(struct uart_amba_port *uap) 2702 { 2703 int i; 2704 bool busy = false; 2705 2706 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2707 if (amba_ports[i] == uap) 2708 amba_ports[i] = NULL; 2709 else if (amba_ports[i]) 2710 busy = true; 2711 } 2712 pl011_dma_remove(uap); 2713 if (!busy) 2714 uart_unregister_driver(&amba_reg); 2715 } 2716 2717 static int pl011_find_free_port(void) 2718 { 2719 int i; 2720 2721 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2722 if (amba_ports[i] == NULL) 2723 return i; 2724 2725 return -EBUSY; 2726 } 2727 2728 static int pl011_get_rs485_mode(struct uart_amba_port *uap) 2729 { 2730 struct uart_port *port = &uap->port; 2731 struct serial_rs485 *rs485 = &port->rs485; 2732 int ret; 2733 2734 ret = uart_get_rs485_mode(port); 2735 if (ret) 2736 return ret; 2737 2738 /* clamp the delays to [0, 100ms] */ 2739 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U); 2740 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U); 2741 2742 return 0; 2743 } 2744 2745 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, 2746 struct resource *mmiobase, int index) 2747 { 2748 void __iomem *base; 2749 int ret; 2750 2751 base = devm_ioremap_resource(dev, mmiobase); 2752 if (IS_ERR(base)) 2753 return PTR_ERR(base); 2754 2755 index = pl011_probe_dt_alias(index, dev); 2756 2757 uap->old_cr = 0; 2758 uap->port.dev = dev; 2759 uap->port.mapbase = mmiobase->start; 2760 uap->port.membase = base; 2761 uap->port.fifosize = uap->fifosize; 2762 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE); 2763 uap->port.flags = UPF_BOOT_AUTOCONF; 2764 uap->port.line = index; 2765 2766 ret = pl011_get_rs485_mode(uap); 2767 if (ret) 2768 return ret; 2769 2770 amba_ports[index] = uap; 2771 2772 return 0; 2773 } 2774 2775 static int pl011_register_port(struct uart_amba_port *uap) 2776 { 2777 int ret, i; 2778 2779 /* Ensure interrupts from this UART are masked and cleared */ 2780 pl011_write(0, uap, REG_IMSC); 2781 pl011_write(0xffff, uap, REG_ICR); 2782 2783 if (!amba_reg.state) { 2784 ret = uart_register_driver(&amba_reg); 2785 if (ret < 0) { 2786 dev_err(uap->port.dev, 2787 "Failed to register AMBA-PL011 driver\n"); 2788 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2789 if (amba_ports[i] == uap) 2790 amba_ports[i] = NULL; 2791 return ret; 2792 } 2793 } 2794 2795 ret = uart_add_one_port(&amba_reg, &uap->port); 2796 if (ret) 2797 pl011_unregister_port(uap); 2798 2799 return ret; 2800 } 2801 2802 static int pl011_probe(struct amba_device *dev, const struct amba_id *id) 2803 { 2804 struct uart_amba_port *uap; 2805 struct vendor_data *vendor = id->data; 2806 int portnr, ret; 2807 2808 portnr = pl011_find_free_port(); 2809 if (portnr < 0) 2810 return portnr; 2811 2812 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), 2813 GFP_KERNEL); 2814 if (!uap) 2815 return -ENOMEM; 2816 2817 uap->clk = devm_clk_get(&dev->dev, NULL); 2818 if (IS_ERR(uap->clk)) 2819 return PTR_ERR(uap->clk); 2820 2821 uap->reg_offset = vendor->reg_offset; 2822 uap->vendor = vendor; 2823 uap->fifosize = vendor->get_fifosize(dev); 2824 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 2825 uap->port.irq = dev->irq[0]; 2826 uap->port.ops = &amba_pl011_pops; 2827 uap->port.rs485_config = pl011_rs485_config; 2828 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); 2829 2830 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); 2831 if (ret) 2832 return ret; 2833 2834 amba_set_drvdata(dev, uap); 2835 2836 return pl011_register_port(uap); 2837 } 2838 2839 static void pl011_remove(struct amba_device *dev) 2840 { 2841 struct uart_amba_port *uap = amba_get_drvdata(dev); 2842 2843 uart_remove_one_port(&amba_reg, &uap->port); 2844 pl011_unregister_port(uap); 2845 } 2846 2847 #ifdef CONFIG_PM_SLEEP 2848 static int pl011_suspend(struct device *dev) 2849 { 2850 struct uart_amba_port *uap = dev_get_drvdata(dev); 2851 2852 if (!uap) 2853 return -EINVAL; 2854 2855 return uart_suspend_port(&amba_reg, &uap->port); 2856 } 2857 2858 static int pl011_resume(struct device *dev) 2859 { 2860 struct uart_amba_port *uap = dev_get_drvdata(dev); 2861 2862 if (!uap) 2863 return -EINVAL; 2864 2865 return uart_resume_port(&amba_reg, &uap->port); 2866 } 2867 #endif 2868 2869 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); 2870 2871 static int sbsa_uart_probe(struct platform_device *pdev) 2872 { 2873 struct uart_amba_port *uap; 2874 struct resource *r; 2875 int portnr, ret; 2876 int baudrate; 2877 2878 /* 2879 * Check the mandatory baud rate parameter in the DT node early 2880 * so that we can easily exit with the error. 2881 */ 2882 if (pdev->dev.of_node) { 2883 struct device_node *np = pdev->dev.of_node; 2884 2885 ret = of_property_read_u32(np, "current-speed", &baudrate); 2886 if (ret) 2887 return ret; 2888 } else { 2889 baudrate = 115200; 2890 } 2891 2892 portnr = pl011_find_free_port(); 2893 if (portnr < 0) 2894 return portnr; 2895 2896 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), 2897 GFP_KERNEL); 2898 if (!uap) 2899 return -ENOMEM; 2900 2901 ret = platform_get_irq(pdev, 0); 2902 if (ret < 0) 2903 return ret; 2904 uap->port.irq = ret; 2905 2906 #ifdef CONFIG_ACPI_SPCR_TABLE 2907 if (qdf2400_e44_present) { 2908 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n"); 2909 uap->vendor = &vendor_qdt_qdf2400_e44; 2910 } else 2911 #endif 2912 uap->vendor = &vendor_sbsa; 2913 2914 uap->reg_offset = uap->vendor->reg_offset; 2915 uap->fifosize = 32; 2916 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 2917 uap->port.ops = &sbsa_uart_pops; 2918 uap->fixed_baud = baudrate; 2919 2920 snprintf(uap->type, sizeof(uap->type), "SBSA"); 2921 2922 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2923 2924 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); 2925 if (ret) 2926 return ret; 2927 2928 platform_set_drvdata(pdev, uap); 2929 2930 return pl011_register_port(uap); 2931 } 2932 2933 static int sbsa_uart_remove(struct platform_device *pdev) 2934 { 2935 struct uart_amba_port *uap = platform_get_drvdata(pdev); 2936 2937 uart_remove_one_port(&amba_reg, &uap->port); 2938 pl011_unregister_port(uap); 2939 return 0; 2940 } 2941 2942 static const struct of_device_id sbsa_uart_of_match[] = { 2943 { .compatible = "arm,sbsa-uart", }, 2944 {}, 2945 }; 2946 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); 2947 2948 static const struct acpi_device_id __maybe_unused sbsa_uart_acpi_match[] = { 2949 { "ARMH0011", 0 }, 2950 {}, 2951 }; 2952 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); 2953 2954 static struct platform_driver arm_sbsa_uart_platform_driver = { 2955 .probe = sbsa_uart_probe, 2956 .remove = sbsa_uart_remove, 2957 .driver = { 2958 .name = "sbsa-uart", 2959 .pm = &pl011_dev_pm_ops, 2960 .of_match_table = of_match_ptr(sbsa_uart_of_match), 2961 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match), 2962 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), 2963 }, 2964 }; 2965 2966 static const struct amba_id pl011_ids[] = { 2967 { 2968 .id = 0x00041011, 2969 .mask = 0x000fffff, 2970 .data = &vendor_arm, 2971 }, 2972 { 2973 .id = 0x00380802, 2974 .mask = 0x00ffffff, 2975 .data = &vendor_st, 2976 }, 2977 { 2978 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe), 2979 .mask = 0x00ffffff, 2980 .data = &vendor_zte, 2981 }, 2982 { 0, 0 }, 2983 }; 2984 2985 MODULE_DEVICE_TABLE(amba, pl011_ids); 2986 2987 static struct amba_driver pl011_driver = { 2988 .drv = { 2989 .name = "uart-pl011", 2990 .pm = &pl011_dev_pm_ops, 2991 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), 2992 }, 2993 .id_table = pl011_ids, 2994 .probe = pl011_probe, 2995 .remove = pl011_remove, 2996 }; 2997 2998 static int __init pl011_init(void) 2999 { 3000 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); 3001 3002 if (platform_driver_register(&arm_sbsa_uart_platform_driver)) 3003 pr_warn("could not register SBSA UART platform driver\n"); 3004 return amba_driver_register(&pl011_driver); 3005 } 3006 3007 static void __exit pl011_exit(void) 3008 { 3009 platform_driver_unregister(&arm_sbsa_uart_platform_driver); 3010 amba_driver_unregister(&pl011_driver); 3011 } 3012 3013 /* 3014 * While this can be a module, if builtin it's most likely the console 3015 * So let's leave module_exit but move module_init to an earlier place 3016 */ 3017 arch_initcall(pl011_init); 3018 module_exit(pl011_exit); 3019 3020 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 3021 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 3022 MODULE_LICENSE("GPL"); 3023