xref: /openbmc/linux/drivers/tty/serial/amba-pl011.c (revision e23feb16)
1 /*
2  *  Driver for AMBA serial ports
3  *
4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5  *
6  *  Copyright 1999 ARM Limited
7  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
8  *  Copyright (C) 2010 ST-Ericsson SA
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
23  *
24  * This is a generic driver for ARM AMBA-type serial ports.  They
25  * have a lot of 16550-like features, but are not register compatible.
26  * Note that although they do have CTS, DCD and DSR inputs, they do
27  * not have an RI input, nor do they have DTR or RTS outputs.  If
28  * required, these have to be supplied via some other means (eg, GPIO)
29  * and hooked into this driver.
30  */
31 
32 
33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34 #define SUPPORT_SYSRQ
35 #endif
36 
37 #include <linux/module.h>
38 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/console.h>
41 #include <linux/sysrq.h>
42 #include <linux/device.h>
43 #include <linux/tty.h>
44 #include <linux/tty_flip.h>
45 #include <linux/serial_core.h>
46 #include <linux/serial.h>
47 #include <linux/amba/bus.h>
48 #include <linux/amba/serial.h>
49 #include <linux/clk.h>
50 #include <linux/slab.h>
51 #include <linux/dmaengine.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/scatterlist.h>
54 #include <linux/delay.h>
55 #include <linux/types.h>
56 #include <linux/of.h>
57 #include <linux/of_device.h>
58 #include <linux/pinctrl/consumer.h>
59 #include <linux/sizes.h>
60 #include <linux/io.h>
61 
62 #define UART_NR			14
63 
64 #define SERIAL_AMBA_MAJOR	204
65 #define SERIAL_AMBA_MINOR	64
66 #define SERIAL_AMBA_NR		UART_NR
67 
68 #define AMBA_ISR_PASS_LIMIT	256
69 
70 #define UART_DR_ERROR		(UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
71 #define UART_DUMMY_DR_RX	(1 << 16)
72 
73 /* There is by now at least one vendor with differing details, so handle it */
74 struct vendor_data {
75 	unsigned int		ifls;
76 	unsigned int		lcrh_tx;
77 	unsigned int		lcrh_rx;
78 	bool			oversampling;
79 	bool			dma_threshold;
80 	bool			cts_event_workaround;
81 
82 	unsigned int (*get_fifosize)(struct amba_device *dev);
83 };
84 
85 static unsigned int get_fifosize_arm(struct amba_device *dev)
86 {
87 	return amba_rev(dev) < 3 ? 16 : 32;
88 }
89 
90 static struct vendor_data vendor_arm = {
91 	.ifls			= UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
92 	.lcrh_tx		= UART011_LCRH,
93 	.lcrh_rx		= UART011_LCRH,
94 	.oversampling		= false,
95 	.dma_threshold		= false,
96 	.cts_event_workaround	= false,
97 	.get_fifosize		= get_fifosize_arm,
98 };
99 
100 static unsigned int get_fifosize_st(struct amba_device *dev)
101 {
102 	return 64;
103 }
104 
105 static struct vendor_data vendor_st = {
106 	.ifls			= UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
107 	.lcrh_tx		= ST_UART011_LCRH_TX,
108 	.lcrh_rx		= ST_UART011_LCRH_RX,
109 	.oversampling		= true,
110 	.dma_threshold		= true,
111 	.cts_event_workaround	= true,
112 	.get_fifosize		= get_fifosize_st,
113 };
114 
115 static struct uart_amba_port *amba_ports[UART_NR];
116 
117 /* Deals with DMA transactions */
118 
119 struct pl011_sgbuf {
120 	struct scatterlist sg;
121 	char *buf;
122 };
123 
124 struct pl011_dmarx_data {
125 	struct dma_chan		*chan;
126 	struct completion	complete;
127 	bool			use_buf_b;
128 	struct pl011_sgbuf	sgbuf_a;
129 	struct pl011_sgbuf	sgbuf_b;
130 	dma_cookie_t		cookie;
131 	bool			running;
132 	struct timer_list	timer;
133 	unsigned int last_residue;
134 	unsigned long last_jiffies;
135 	bool auto_poll_rate;
136 	unsigned int poll_rate;
137 	unsigned int poll_timeout;
138 };
139 
140 struct pl011_dmatx_data {
141 	struct dma_chan		*chan;
142 	struct scatterlist	sg;
143 	char			*buf;
144 	bool			queued;
145 };
146 
147 /*
148  * We wrap our port structure around the generic uart_port.
149  */
150 struct uart_amba_port {
151 	struct uart_port	port;
152 	struct clk		*clk;
153 	const struct vendor_data *vendor;
154 	unsigned int		dmacr;		/* dma control reg */
155 	unsigned int		im;		/* interrupt mask */
156 	unsigned int		old_status;
157 	unsigned int		fifosize;	/* vendor-specific */
158 	unsigned int		lcrh_tx;	/* vendor-specific */
159 	unsigned int		lcrh_rx;	/* vendor-specific */
160 	unsigned int		old_cr;		/* state during shutdown */
161 	bool			autorts;
162 	char			type[12];
163 #ifdef CONFIG_DMA_ENGINE
164 	/* DMA stuff */
165 	bool			using_tx_dma;
166 	bool			using_rx_dma;
167 	struct pl011_dmarx_data dmarx;
168 	struct pl011_dmatx_data	dmatx;
169 #endif
170 };
171 
172 /*
173  * Reads up to 256 characters from the FIFO or until it's empty and
174  * inserts them into the TTY layer. Returns the number of characters
175  * read from the FIFO.
176  */
177 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
178 {
179 	u16 status, ch;
180 	unsigned int flag, max_count = 256;
181 	int fifotaken = 0;
182 
183 	while (max_count--) {
184 		status = readw(uap->port.membase + UART01x_FR);
185 		if (status & UART01x_FR_RXFE)
186 			break;
187 
188 		/* Take chars from the FIFO and update status */
189 		ch = readw(uap->port.membase + UART01x_DR) |
190 			UART_DUMMY_DR_RX;
191 		flag = TTY_NORMAL;
192 		uap->port.icount.rx++;
193 		fifotaken++;
194 
195 		if (unlikely(ch & UART_DR_ERROR)) {
196 			if (ch & UART011_DR_BE) {
197 				ch &= ~(UART011_DR_FE | UART011_DR_PE);
198 				uap->port.icount.brk++;
199 				if (uart_handle_break(&uap->port))
200 					continue;
201 			} else if (ch & UART011_DR_PE)
202 				uap->port.icount.parity++;
203 			else if (ch & UART011_DR_FE)
204 				uap->port.icount.frame++;
205 			if (ch & UART011_DR_OE)
206 				uap->port.icount.overrun++;
207 
208 			ch &= uap->port.read_status_mask;
209 
210 			if (ch & UART011_DR_BE)
211 				flag = TTY_BREAK;
212 			else if (ch & UART011_DR_PE)
213 				flag = TTY_PARITY;
214 			else if (ch & UART011_DR_FE)
215 				flag = TTY_FRAME;
216 		}
217 
218 		if (uart_handle_sysrq_char(&uap->port, ch & 255))
219 			continue;
220 
221 		uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
222 	}
223 
224 	return fifotaken;
225 }
226 
227 
228 /*
229  * All the DMA operation mode stuff goes inside this ifdef.
230  * This assumes that you have a generic DMA device interface,
231  * no custom DMA interfaces are supported.
232  */
233 #ifdef CONFIG_DMA_ENGINE
234 
235 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
236 
237 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
238 	enum dma_data_direction dir)
239 {
240 	dma_addr_t dma_addr;
241 
242 	sg->buf = dma_alloc_coherent(chan->device->dev,
243 		PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
244 	if (!sg->buf)
245 		return -ENOMEM;
246 
247 	sg_init_table(&sg->sg, 1);
248 	sg_set_page(&sg->sg, phys_to_page(dma_addr),
249 		PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
250 	sg_dma_address(&sg->sg) = dma_addr;
251 
252 	return 0;
253 }
254 
255 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
256 	enum dma_data_direction dir)
257 {
258 	if (sg->buf) {
259 		dma_free_coherent(chan->device->dev,
260 			PL011_DMA_BUFFER_SIZE, sg->buf,
261 			sg_dma_address(&sg->sg));
262 	}
263 }
264 
265 static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port *uap)
266 {
267 	/* DMA is the sole user of the platform data right now */
268 	struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
269 	struct dma_slave_config tx_conf = {
270 		.dst_addr = uap->port.mapbase + UART01x_DR,
271 		.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
272 		.direction = DMA_MEM_TO_DEV,
273 		.dst_maxburst = uap->fifosize >> 1,
274 		.device_fc = false,
275 	};
276 	struct dma_chan *chan;
277 	dma_cap_mask_t mask;
278 
279 	chan = dma_request_slave_channel(dev, "tx");
280 
281 	if (!chan) {
282 		/* We need platform data */
283 		if (!plat || !plat->dma_filter) {
284 			dev_info(uap->port.dev, "no DMA platform data\n");
285 			return;
286 		}
287 
288 		/* Try to acquire a generic DMA engine slave TX channel */
289 		dma_cap_zero(mask);
290 		dma_cap_set(DMA_SLAVE, mask);
291 
292 		chan = dma_request_channel(mask, plat->dma_filter,
293 						plat->dma_tx_param);
294 		if (!chan) {
295 			dev_err(uap->port.dev, "no TX DMA channel!\n");
296 			return;
297 		}
298 	}
299 
300 	dmaengine_slave_config(chan, &tx_conf);
301 	uap->dmatx.chan = chan;
302 
303 	dev_info(uap->port.dev, "DMA channel TX %s\n",
304 		 dma_chan_name(uap->dmatx.chan));
305 
306 	/* Optionally make use of an RX channel as well */
307 	chan = dma_request_slave_channel(dev, "rx");
308 
309 	if (!chan && plat->dma_rx_param) {
310 		chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
311 
312 		if (!chan) {
313 			dev_err(uap->port.dev, "no RX DMA channel!\n");
314 			return;
315 		}
316 	}
317 
318 	if (chan) {
319 		struct dma_slave_config rx_conf = {
320 			.src_addr = uap->port.mapbase + UART01x_DR,
321 			.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
322 			.direction = DMA_DEV_TO_MEM,
323 			.src_maxburst = uap->fifosize >> 1,
324 			.device_fc = false,
325 		};
326 
327 		dmaengine_slave_config(chan, &rx_conf);
328 		uap->dmarx.chan = chan;
329 
330 		if (plat && plat->dma_rx_poll_enable) {
331 			/* Set poll rate if specified. */
332 			if (plat->dma_rx_poll_rate) {
333 				uap->dmarx.auto_poll_rate = false;
334 				uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
335 			} else {
336 				/*
337 				 * 100 ms defaults to poll rate if not
338 				 * specified. This will be adjusted with
339 				 * the baud rate at set_termios.
340 				 */
341 				uap->dmarx.auto_poll_rate = true;
342 				uap->dmarx.poll_rate =  100;
343 			}
344 			/* 3 secs defaults poll_timeout if not specified. */
345 			if (plat->dma_rx_poll_timeout)
346 				uap->dmarx.poll_timeout =
347 					plat->dma_rx_poll_timeout;
348 			else
349 				uap->dmarx.poll_timeout = 3000;
350 		} else
351 			uap->dmarx.auto_poll_rate = false;
352 
353 		dev_info(uap->port.dev, "DMA channel RX %s\n",
354 			 dma_chan_name(uap->dmarx.chan));
355 	}
356 }
357 
358 #ifndef MODULE
359 /*
360  * Stack up the UARTs and let the above initcall be done at device
361  * initcall time, because the serial driver is called as an arch
362  * initcall, and at this time the DMA subsystem is not yet registered.
363  * At this point the driver will switch over to using DMA where desired.
364  */
365 struct dma_uap {
366 	struct list_head node;
367 	struct uart_amba_port *uap;
368 	struct device *dev;
369 };
370 
371 static LIST_HEAD(pl011_dma_uarts);
372 
373 static int __init pl011_dma_initcall(void)
374 {
375 	struct list_head *node, *tmp;
376 
377 	list_for_each_safe(node, tmp, &pl011_dma_uarts) {
378 		struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
379 		pl011_dma_probe_initcall(dmau->dev, dmau->uap);
380 		list_del(node);
381 		kfree(dmau);
382 	}
383 	return 0;
384 }
385 
386 device_initcall(pl011_dma_initcall);
387 
388 static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap)
389 {
390 	struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
391 	if (dmau) {
392 		dmau->uap = uap;
393 		dmau->dev = dev;
394 		list_add_tail(&dmau->node, &pl011_dma_uarts);
395 	}
396 }
397 #else
398 static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap)
399 {
400 	pl011_dma_probe_initcall(dev, uap);
401 }
402 #endif
403 
404 static void pl011_dma_remove(struct uart_amba_port *uap)
405 {
406 	/* TODO: remove the initcall if it has not yet executed */
407 	if (uap->dmatx.chan)
408 		dma_release_channel(uap->dmatx.chan);
409 	if (uap->dmarx.chan)
410 		dma_release_channel(uap->dmarx.chan);
411 }
412 
413 /* Forward declare this for the refill routine */
414 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
415 
416 /*
417  * The current DMA TX buffer has been sent.
418  * Try to queue up another DMA buffer.
419  */
420 static void pl011_dma_tx_callback(void *data)
421 {
422 	struct uart_amba_port *uap = data;
423 	struct pl011_dmatx_data *dmatx = &uap->dmatx;
424 	unsigned long flags;
425 	u16 dmacr;
426 
427 	spin_lock_irqsave(&uap->port.lock, flags);
428 	if (uap->dmatx.queued)
429 		dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
430 			     DMA_TO_DEVICE);
431 
432 	dmacr = uap->dmacr;
433 	uap->dmacr = dmacr & ~UART011_TXDMAE;
434 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);
435 
436 	/*
437 	 * If TX DMA was disabled, it means that we've stopped the DMA for
438 	 * some reason (eg, XOFF received, or we want to send an X-char.)
439 	 *
440 	 * Note: we need to be careful here of a potential race between DMA
441 	 * and the rest of the driver - if the driver disables TX DMA while
442 	 * a TX buffer completing, we must update the tx queued status to
443 	 * get further refills (hence we check dmacr).
444 	 */
445 	if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
446 	    uart_circ_empty(&uap->port.state->xmit)) {
447 		uap->dmatx.queued = false;
448 		spin_unlock_irqrestore(&uap->port.lock, flags);
449 		return;
450 	}
451 
452 	if (pl011_dma_tx_refill(uap) <= 0) {
453 		/*
454 		 * We didn't queue a DMA buffer for some reason, but we
455 		 * have data pending to be sent.  Re-enable the TX IRQ.
456 		 */
457 		uap->im |= UART011_TXIM;
458 		writew(uap->im, uap->port.membase + UART011_IMSC);
459 	}
460 	spin_unlock_irqrestore(&uap->port.lock, flags);
461 }
462 
463 /*
464  * Try to refill the TX DMA buffer.
465  * Locking: called with port lock held and IRQs disabled.
466  * Returns:
467  *   1 if we queued up a TX DMA buffer.
468  *   0 if we didn't want to handle this by DMA
469  *  <0 on error
470  */
471 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
472 {
473 	struct pl011_dmatx_data *dmatx = &uap->dmatx;
474 	struct dma_chan *chan = dmatx->chan;
475 	struct dma_device *dma_dev = chan->device;
476 	struct dma_async_tx_descriptor *desc;
477 	struct circ_buf *xmit = &uap->port.state->xmit;
478 	unsigned int count;
479 
480 	/*
481 	 * Try to avoid the overhead involved in using DMA if the
482 	 * transaction fits in the first half of the FIFO, by using
483 	 * the standard interrupt handling.  This ensures that we
484 	 * issue a uart_write_wakeup() at the appropriate time.
485 	 */
486 	count = uart_circ_chars_pending(xmit);
487 	if (count < (uap->fifosize >> 1)) {
488 		uap->dmatx.queued = false;
489 		return 0;
490 	}
491 
492 	/*
493 	 * Bodge: don't send the last character by DMA, as this
494 	 * will prevent XON from notifying us to restart DMA.
495 	 */
496 	count -= 1;
497 
498 	/* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
499 	if (count > PL011_DMA_BUFFER_SIZE)
500 		count = PL011_DMA_BUFFER_SIZE;
501 
502 	if (xmit->tail < xmit->head)
503 		memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
504 	else {
505 		size_t first = UART_XMIT_SIZE - xmit->tail;
506 		size_t second = xmit->head;
507 
508 		memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
509 		if (second)
510 			memcpy(&dmatx->buf[first], &xmit->buf[0], second);
511 	}
512 
513 	dmatx->sg.length = count;
514 
515 	if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
516 		uap->dmatx.queued = false;
517 		dev_dbg(uap->port.dev, "unable to map TX DMA\n");
518 		return -EBUSY;
519 	}
520 
521 	desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
522 					     DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
523 	if (!desc) {
524 		dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
525 		uap->dmatx.queued = false;
526 		/*
527 		 * If DMA cannot be used right now, we complete this
528 		 * transaction via IRQ and let the TTY layer retry.
529 		 */
530 		dev_dbg(uap->port.dev, "TX DMA busy\n");
531 		return -EBUSY;
532 	}
533 
534 	/* Some data to go along to the callback */
535 	desc->callback = pl011_dma_tx_callback;
536 	desc->callback_param = uap;
537 
538 	/* All errors should happen at prepare time */
539 	dmaengine_submit(desc);
540 
541 	/* Fire the DMA transaction */
542 	dma_dev->device_issue_pending(chan);
543 
544 	uap->dmacr |= UART011_TXDMAE;
545 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);
546 	uap->dmatx.queued = true;
547 
548 	/*
549 	 * Now we know that DMA will fire, so advance the ring buffer
550 	 * with the stuff we just dispatched.
551 	 */
552 	xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
553 	uap->port.icount.tx += count;
554 
555 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
556 		uart_write_wakeup(&uap->port);
557 
558 	return 1;
559 }
560 
561 /*
562  * We received a transmit interrupt without a pending X-char but with
563  * pending characters.
564  * Locking: called with port lock held and IRQs disabled.
565  * Returns:
566  *   false if we want to use PIO to transmit
567  *   true if we queued a DMA buffer
568  */
569 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
570 {
571 	if (!uap->using_tx_dma)
572 		return false;
573 
574 	/*
575 	 * If we already have a TX buffer queued, but received a
576 	 * TX interrupt, it will be because we've just sent an X-char.
577 	 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
578 	 */
579 	if (uap->dmatx.queued) {
580 		uap->dmacr |= UART011_TXDMAE;
581 		writew(uap->dmacr, uap->port.membase + UART011_DMACR);
582 		uap->im &= ~UART011_TXIM;
583 		writew(uap->im, uap->port.membase + UART011_IMSC);
584 		return true;
585 	}
586 
587 	/*
588 	 * We don't have a TX buffer queued, so try to queue one.
589 	 * If we successfully queued a buffer, mask the TX IRQ.
590 	 */
591 	if (pl011_dma_tx_refill(uap) > 0) {
592 		uap->im &= ~UART011_TXIM;
593 		writew(uap->im, uap->port.membase + UART011_IMSC);
594 		return true;
595 	}
596 	return false;
597 }
598 
599 /*
600  * Stop the DMA transmit (eg, due to received XOFF).
601  * Locking: called with port lock held and IRQs disabled.
602  */
603 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
604 {
605 	if (uap->dmatx.queued) {
606 		uap->dmacr &= ~UART011_TXDMAE;
607 		writew(uap->dmacr, uap->port.membase + UART011_DMACR);
608 	}
609 }
610 
611 /*
612  * Try to start a DMA transmit, or in the case of an XON/OFF
613  * character queued for send, try to get that character out ASAP.
614  * Locking: called with port lock held and IRQs disabled.
615  * Returns:
616  *   false if we want the TX IRQ to be enabled
617  *   true if we have a buffer queued
618  */
619 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
620 {
621 	u16 dmacr;
622 
623 	if (!uap->using_tx_dma)
624 		return false;
625 
626 	if (!uap->port.x_char) {
627 		/* no X-char, try to push chars out in DMA mode */
628 		bool ret = true;
629 
630 		if (!uap->dmatx.queued) {
631 			if (pl011_dma_tx_refill(uap) > 0) {
632 				uap->im &= ~UART011_TXIM;
633 				ret = true;
634 			} else {
635 				uap->im |= UART011_TXIM;
636 				ret = false;
637 			}
638 			writew(uap->im, uap->port.membase + UART011_IMSC);
639 		} else if (!(uap->dmacr & UART011_TXDMAE)) {
640 			uap->dmacr |= UART011_TXDMAE;
641 			writew(uap->dmacr,
642 				       uap->port.membase + UART011_DMACR);
643 		}
644 		return ret;
645 	}
646 
647 	/*
648 	 * We have an X-char to send.  Disable DMA to prevent it loading
649 	 * the TX fifo, and then see if we can stuff it into the FIFO.
650 	 */
651 	dmacr = uap->dmacr;
652 	uap->dmacr &= ~UART011_TXDMAE;
653 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);
654 
655 	if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
656 		/*
657 		 * No space in the FIFO, so enable the transmit interrupt
658 		 * so we know when there is space.  Note that once we've
659 		 * loaded the character, we should just re-enable DMA.
660 		 */
661 		return false;
662 	}
663 
664 	writew(uap->port.x_char, uap->port.membase + UART01x_DR);
665 	uap->port.icount.tx++;
666 	uap->port.x_char = 0;
667 
668 	/* Success - restore the DMA state */
669 	uap->dmacr = dmacr;
670 	writew(dmacr, uap->port.membase + UART011_DMACR);
671 
672 	return true;
673 }
674 
675 /*
676  * Flush the transmit buffer.
677  * Locking: called with port lock held and IRQs disabled.
678  */
679 static void pl011_dma_flush_buffer(struct uart_port *port)
680 __releases(&uap->port.lock)
681 __acquires(&uap->port.lock)
682 {
683 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
684 
685 	if (!uap->using_tx_dma)
686 		return;
687 
688 	/* Avoid deadlock with the DMA engine callback */
689 	spin_unlock(&uap->port.lock);
690 	dmaengine_terminate_all(uap->dmatx.chan);
691 	spin_lock(&uap->port.lock);
692 	if (uap->dmatx.queued) {
693 		dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
694 			     DMA_TO_DEVICE);
695 		uap->dmatx.queued = false;
696 		uap->dmacr &= ~UART011_TXDMAE;
697 		writew(uap->dmacr, uap->port.membase + UART011_DMACR);
698 	}
699 }
700 
701 static void pl011_dma_rx_callback(void *data);
702 
703 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
704 {
705 	struct dma_chan *rxchan = uap->dmarx.chan;
706 	struct pl011_dmarx_data *dmarx = &uap->dmarx;
707 	struct dma_async_tx_descriptor *desc;
708 	struct pl011_sgbuf *sgbuf;
709 
710 	if (!rxchan)
711 		return -EIO;
712 
713 	/* Start the RX DMA job */
714 	sgbuf = uap->dmarx.use_buf_b ?
715 		&uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
716 	desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
717 					DMA_DEV_TO_MEM,
718 					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
719 	/*
720 	 * If the DMA engine is busy and cannot prepare a
721 	 * channel, no big deal, the driver will fall back
722 	 * to interrupt mode as a result of this error code.
723 	 */
724 	if (!desc) {
725 		uap->dmarx.running = false;
726 		dmaengine_terminate_all(rxchan);
727 		return -EBUSY;
728 	}
729 
730 	/* Some data to go along to the callback */
731 	desc->callback = pl011_dma_rx_callback;
732 	desc->callback_param = uap;
733 	dmarx->cookie = dmaengine_submit(desc);
734 	dma_async_issue_pending(rxchan);
735 
736 	uap->dmacr |= UART011_RXDMAE;
737 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);
738 	uap->dmarx.running = true;
739 
740 	uap->im &= ~UART011_RXIM;
741 	writew(uap->im, uap->port.membase + UART011_IMSC);
742 
743 	return 0;
744 }
745 
746 /*
747  * This is called when either the DMA job is complete, or
748  * the FIFO timeout interrupt occurred. This must be called
749  * with the port spinlock uap->port.lock held.
750  */
751 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
752 			       u32 pending, bool use_buf_b,
753 			       bool readfifo)
754 {
755 	struct tty_port *port = &uap->port.state->port;
756 	struct pl011_sgbuf *sgbuf = use_buf_b ?
757 		&uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
758 	int dma_count = 0;
759 	u32 fifotaken = 0; /* only used for vdbg() */
760 
761 	struct pl011_dmarx_data *dmarx = &uap->dmarx;
762 	int dmataken = 0;
763 
764 	if (uap->dmarx.poll_rate) {
765 		/* The data can be taken by polling */
766 		dmataken = sgbuf->sg.length - dmarx->last_residue;
767 		/* Recalculate the pending size */
768 		if (pending >= dmataken)
769 			pending -= dmataken;
770 	}
771 
772 	/* Pick the remain data from the DMA */
773 	if (pending) {
774 
775 		/*
776 		 * First take all chars in the DMA pipe, then look in the FIFO.
777 		 * Note that tty_insert_flip_buf() tries to take as many chars
778 		 * as it can.
779 		 */
780 		dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
781 				pending);
782 
783 		uap->port.icount.rx += dma_count;
784 		if (dma_count < pending)
785 			dev_warn(uap->port.dev,
786 				 "couldn't insert all characters (TTY is full?)\n");
787 	}
788 
789 	/* Reset the last_residue for Rx DMA poll */
790 	if (uap->dmarx.poll_rate)
791 		dmarx->last_residue = sgbuf->sg.length;
792 
793 	/*
794 	 * Only continue with trying to read the FIFO if all DMA chars have
795 	 * been taken first.
796 	 */
797 	if (dma_count == pending && readfifo) {
798 		/* Clear any error flags */
799 		writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
800 		       uap->port.membase + UART011_ICR);
801 
802 		/*
803 		 * If we read all the DMA'd characters, and we had an
804 		 * incomplete buffer, that could be due to an rx error, or
805 		 * maybe we just timed out. Read any pending chars and check
806 		 * the error status.
807 		 *
808 		 * Error conditions will only occur in the FIFO, these will
809 		 * trigger an immediate interrupt and stop the DMA job, so we
810 		 * will always find the error in the FIFO, never in the DMA
811 		 * buffer.
812 		 */
813 		fifotaken = pl011_fifo_to_tty(uap);
814 	}
815 
816 	spin_unlock(&uap->port.lock);
817 	dev_vdbg(uap->port.dev,
818 		 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
819 		 dma_count, fifotaken);
820 	tty_flip_buffer_push(port);
821 	spin_lock(&uap->port.lock);
822 }
823 
824 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
825 {
826 	struct pl011_dmarx_data *dmarx = &uap->dmarx;
827 	struct dma_chan *rxchan = dmarx->chan;
828 	struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
829 		&dmarx->sgbuf_b : &dmarx->sgbuf_a;
830 	size_t pending;
831 	struct dma_tx_state state;
832 	enum dma_status dmastat;
833 
834 	/*
835 	 * Pause the transfer so we can trust the current counter,
836 	 * do this before we pause the PL011 block, else we may
837 	 * overflow the FIFO.
838 	 */
839 	if (dmaengine_pause(rxchan))
840 		dev_err(uap->port.dev, "unable to pause DMA transfer\n");
841 	dmastat = rxchan->device->device_tx_status(rxchan,
842 						   dmarx->cookie, &state);
843 	if (dmastat != DMA_PAUSED)
844 		dev_err(uap->port.dev, "unable to pause DMA transfer\n");
845 
846 	/* Disable RX DMA - incoming data will wait in the FIFO */
847 	uap->dmacr &= ~UART011_RXDMAE;
848 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);
849 	uap->dmarx.running = false;
850 
851 	pending = sgbuf->sg.length - state.residue;
852 	BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
853 	/* Then we terminate the transfer - we now know our residue */
854 	dmaengine_terminate_all(rxchan);
855 
856 	/*
857 	 * This will take the chars we have so far and insert
858 	 * into the framework.
859 	 */
860 	pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
861 
862 	/* Switch buffer & re-trigger DMA job */
863 	dmarx->use_buf_b = !dmarx->use_buf_b;
864 	if (pl011_dma_rx_trigger_dma(uap)) {
865 		dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
866 			"fall back to interrupt mode\n");
867 		uap->im |= UART011_RXIM;
868 		writew(uap->im, uap->port.membase + UART011_IMSC);
869 	}
870 }
871 
872 static void pl011_dma_rx_callback(void *data)
873 {
874 	struct uart_amba_port *uap = data;
875 	struct pl011_dmarx_data *dmarx = &uap->dmarx;
876 	struct dma_chan *rxchan = dmarx->chan;
877 	bool lastbuf = dmarx->use_buf_b;
878 	struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
879 		&dmarx->sgbuf_b : &dmarx->sgbuf_a;
880 	size_t pending;
881 	struct dma_tx_state state;
882 	int ret;
883 
884 	/*
885 	 * This completion interrupt occurs typically when the
886 	 * RX buffer is totally stuffed but no timeout has yet
887 	 * occurred. When that happens, we just want the RX
888 	 * routine to flush out the secondary DMA buffer while
889 	 * we immediately trigger the next DMA job.
890 	 */
891 	spin_lock_irq(&uap->port.lock);
892 	/*
893 	 * Rx data can be taken by the UART interrupts during
894 	 * the DMA irq handler. So we check the residue here.
895 	 */
896 	rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
897 	pending = sgbuf->sg.length - state.residue;
898 	BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
899 	/* Then we terminate the transfer - we now know our residue */
900 	dmaengine_terminate_all(rxchan);
901 
902 	uap->dmarx.running = false;
903 	dmarx->use_buf_b = !lastbuf;
904 	ret = pl011_dma_rx_trigger_dma(uap);
905 
906 	pl011_dma_rx_chars(uap, pending, lastbuf, false);
907 	spin_unlock_irq(&uap->port.lock);
908 	/*
909 	 * Do this check after we picked the DMA chars so we don't
910 	 * get some IRQ immediately from RX.
911 	 */
912 	if (ret) {
913 		dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
914 			"fall back to interrupt mode\n");
915 		uap->im |= UART011_RXIM;
916 		writew(uap->im, uap->port.membase + UART011_IMSC);
917 	}
918 }
919 
920 /*
921  * Stop accepting received characters, when we're shutting down or
922  * suspending this port.
923  * Locking: called with port lock held and IRQs disabled.
924  */
925 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
926 {
927 	/* FIXME.  Just disable the DMA enable */
928 	uap->dmacr &= ~UART011_RXDMAE;
929 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);
930 }
931 
932 /*
933  * Timer handler for Rx DMA polling.
934  * Every polling, It checks the residue in the dma buffer and transfer
935  * data to the tty. Also, last_residue is updated for the next polling.
936  */
937 static void pl011_dma_rx_poll(unsigned long args)
938 {
939 	struct uart_amba_port *uap = (struct uart_amba_port *)args;
940 	struct tty_port *port = &uap->port.state->port;
941 	struct pl011_dmarx_data *dmarx = &uap->dmarx;
942 	struct dma_chan *rxchan = uap->dmarx.chan;
943 	unsigned long flags = 0;
944 	unsigned int dmataken = 0;
945 	unsigned int size = 0;
946 	struct pl011_sgbuf *sgbuf;
947 	int dma_count;
948 	struct dma_tx_state state;
949 
950 	sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
951 	rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
952 	if (likely(state.residue < dmarx->last_residue)) {
953 		dmataken = sgbuf->sg.length - dmarx->last_residue;
954 		size = dmarx->last_residue - state.residue;
955 		dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
956 				size);
957 		if (dma_count == size)
958 			dmarx->last_residue =  state.residue;
959 		dmarx->last_jiffies = jiffies;
960 	}
961 	tty_flip_buffer_push(port);
962 
963 	/*
964 	 * If no data is received in poll_timeout, the driver will fall back
965 	 * to interrupt mode. We will retrigger DMA at the first interrupt.
966 	 */
967 	if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
968 			> uap->dmarx.poll_timeout) {
969 
970 		spin_lock_irqsave(&uap->port.lock, flags);
971 		pl011_dma_rx_stop(uap);
972 		spin_unlock_irqrestore(&uap->port.lock, flags);
973 
974 		uap->dmarx.running = false;
975 		dmaengine_terminate_all(rxchan);
976 		del_timer(&uap->dmarx.timer);
977 	} else {
978 		mod_timer(&uap->dmarx.timer,
979 			jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
980 	}
981 }
982 
983 static void pl011_dma_startup(struct uart_amba_port *uap)
984 {
985 	int ret;
986 
987 	if (!uap->dmatx.chan)
988 		return;
989 
990 	uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
991 	if (!uap->dmatx.buf) {
992 		dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
993 		uap->port.fifosize = uap->fifosize;
994 		return;
995 	}
996 
997 	sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
998 
999 	/* The DMA buffer is now the FIFO the TTY subsystem can use */
1000 	uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1001 	uap->using_tx_dma = true;
1002 
1003 	if (!uap->dmarx.chan)
1004 		goto skip_rx;
1005 
1006 	/* Allocate and map DMA RX buffers */
1007 	ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1008 			       DMA_FROM_DEVICE);
1009 	if (ret) {
1010 		dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1011 			"RX buffer A", ret);
1012 		goto skip_rx;
1013 	}
1014 
1015 	ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1016 			       DMA_FROM_DEVICE);
1017 	if (ret) {
1018 		dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1019 			"RX buffer B", ret);
1020 		pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1021 				 DMA_FROM_DEVICE);
1022 		goto skip_rx;
1023 	}
1024 
1025 	uap->using_rx_dma = true;
1026 
1027 skip_rx:
1028 	/* Turn on DMA error (RX/TX will be enabled on demand) */
1029 	uap->dmacr |= UART011_DMAONERR;
1030 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);
1031 
1032 	/*
1033 	 * ST Micro variants has some specific dma burst threshold
1034 	 * compensation. Set this to 16 bytes, so burst will only
1035 	 * be issued above/below 16 bytes.
1036 	 */
1037 	if (uap->vendor->dma_threshold)
1038 		writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1039 			       uap->port.membase + ST_UART011_DMAWM);
1040 
1041 	if (uap->using_rx_dma) {
1042 		if (pl011_dma_rx_trigger_dma(uap))
1043 			dev_dbg(uap->port.dev, "could not trigger initial "
1044 				"RX DMA job, fall back to interrupt mode\n");
1045 		if (uap->dmarx.poll_rate) {
1046 			init_timer(&(uap->dmarx.timer));
1047 			uap->dmarx.timer.function = pl011_dma_rx_poll;
1048 			uap->dmarx.timer.data = (unsigned long)uap;
1049 			mod_timer(&uap->dmarx.timer,
1050 				jiffies +
1051 				msecs_to_jiffies(uap->dmarx.poll_rate));
1052 			uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1053 			uap->dmarx.last_jiffies = jiffies;
1054 		}
1055 	}
1056 }
1057 
1058 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1059 {
1060 	if (!(uap->using_tx_dma || uap->using_rx_dma))
1061 		return;
1062 
1063 	/* Disable RX and TX DMA */
1064 	while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1065 		barrier();
1066 
1067 	spin_lock_irq(&uap->port.lock);
1068 	uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1069 	writew(uap->dmacr, uap->port.membase + UART011_DMACR);
1070 	spin_unlock_irq(&uap->port.lock);
1071 
1072 	if (uap->using_tx_dma) {
1073 		/* In theory, this should already be done by pl011_dma_flush_buffer */
1074 		dmaengine_terminate_all(uap->dmatx.chan);
1075 		if (uap->dmatx.queued) {
1076 			dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1077 				     DMA_TO_DEVICE);
1078 			uap->dmatx.queued = false;
1079 		}
1080 
1081 		kfree(uap->dmatx.buf);
1082 		uap->using_tx_dma = false;
1083 	}
1084 
1085 	if (uap->using_rx_dma) {
1086 		dmaengine_terminate_all(uap->dmarx.chan);
1087 		/* Clean up the RX DMA */
1088 		pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1089 		pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1090 		if (uap->dmarx.poll_rate)
1091 			del_timer_sync(&uap->dmarx.timer);
1092 		uap->using_rx_dma = false;
1093 	}
1094 }
1095 
1096 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1097 {
1098 	return uap->using_rx_dma;
1099 }
1100 
1101 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1102 {
1103 	return uap->using_rx_dma && uap->dmarx.running;
1104 }
1105 
1106 #else
1107 /* Blank functions if the DMA engine is not available */
1108 static inline void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap)
1109 {
1110 }
1111 
1112 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1113 {
1114 }
1115 
1116 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1117 {
1118 }
1119 
1120 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1121 {
1122 }
1123 
1124 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1125 {
1126 	return false;
1127 }
1128 
1129 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1130 {
1131 }
1132 
1133 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1134 {
1135 	return false;
1136 }
1137 
1138 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1139 {
1140 }
1141 
1142 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1143 {
1144 }
1145 
1146 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1147 {
1148 	return -EIO;
1149 }
1150 
1151 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1152 {
1153 	return false;
1154 }
1155 
1156 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1157 {
1158 	return false;
1159 }
1160 
1161 #define pl011_dma_flush_buffer	NULL
1162 #endif
1163 
1164 static void pl011_stop_tx(struct uart_port *port)
1165 {
1166 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1167 
1168 	uap->im &= ~UART011_TXIM;
1169 	writew(uap->im, uap->port.membase + UART011_IMSC);
1170 	pl011_dma_tx_stop(uap);
1171 }
1172 
1173 static void pl011_start_tx(struct uart_port *port)
1174 {
1175 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1176 
1177 	if (!pl011_dma_tx_start(uap)) {
1178 		uap->im |= UART011_TXIM;
1179 		writew(uap->im, uap->port.membase + UART011_IMSC);
1180 	}
1181 }
1182 
1183 static void pl011_stop_rx(struct uart_port *port)
1184 {
1185 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1186 
1187 	uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1188 		     UART011_PEIM|UART011_BEIM|UART011_OEIM);
1189 	writew(uap->im, uap->port.membase + UART011_IMSC);
1190 
1191 	pl011_dma_rx_stop(uap);
1192 }
1193 
1194 static void pl011_enable_ms(struct uart_port *port)
1195 {
1196 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1197 
1198 	uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1199 	writew(uap->im, uap->port.membase + UART011_IMSC);
1200 }
1201 
1202 static void pl011_rx_chars(struct uart_amba_port *uap)
1203 __releases(&uap->port.lock)
1204 __acquires(&uap->port.lock)
1205 {
1206 	pl011_fifo_to_tty(uap);
1207 
1208 	spin_unlock(&uap->port.lock);
1209 	tty_flip_buffer_push(&uap->port.state->port);
1210 	/*
1211 	 * If we were temporarily out of DMA mode for a while,
1212 	 * attempt to switch back to DMA mode again.
1213 	 */
1214 	if (pl011_dma_rx_available(uap)) {
1215 		if (pl011_dma_rx_trigger_dma(uap)) {
1216 			dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1217 				"fall back to interrupt mode again\n");
1218 			uap->im |= UART011_RXIM;
1219 		} else {
1220 			uap->im &= ~UART011_RXIM;
1221 #ifdef CONFIG_DMA_ENGINE
1222 			/* Start Rx DMA poll */
1223 			if (uap->dmarx.poll_rate) {
1224 				uap->dmarx.last_jiffies = jiffies;
1225 				uap->dmarx.last_residue	= PL011_DMA_BUFFER_SIZE;
1226 				mod_timer(&uap->dmarx.timer,
1227 					jiffies +
1228 					msecs_to_jiffies(uap->dmarx.poll_rate));
1229 			}
1230 #endif
1231 		}
1232 
1233 		writew(uap->im, uap->port.membase + UART011_IMSC);
1234 	}
1235 	spin_lock(&uap->port.lock);
1236 }
1237 
1238 static void pl011_tx_chars(struct uart_amba_port *uap)
1239 {
1240 	struct circ_buf *xmit = &uap->port.state->xmit;
1241 	int count;
1242 
1243 	if (uap->port.x_char) {
1244 		writew(uap->port.x_char, uap->port.membase + UART01x_DR);
1245 		uap->port.icount.tx++;
1246 		uap->port.x_char = 0;
1247 		return;
1248 	}
1249 	if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1250 		pl011_stop_tx(&uap->port);
1251 		return;
1252 	}
1253 
1254 	/* If we are using DMA mode, try to send some characters. */
1255 	if (pl011_dma_tx_irq(uap))
1256 		return;
1257 
1258 	count = uap->fifosize >> 1;
1259 	do {
1260 		writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
1261 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1262 		uap->port.icount.tx++;
1263 		if (uart_circ_empty(xmit))
1264 			break;
1265 	} while (--count > 0);
1266 
1267 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1268 		uart_write_wakeup(&uap->port);
1269 
1270 	if (uart_circ_empty(xmit))
1271 		pl011_stop_tx(&uap->port);
1272 }
1273 
1274 static void pl011_modem_status(struct uart_amba_port *uap)
1275 {
1276 	unsigned int status, delta;
1277 
1278 	status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1279 
1280 	delta = status ^ uap->old_status;
1281 	uap->old_status = status;
1282 
1283 	if (!delta)
1284 		return;
1285 
1286 	if (delta & UART01x_FR_DCD)
1287 		uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1288 
1289 	if (delta & UART01x_FR_DSR)
1290 		uap->port.icount.dsr++;
1291 
1292 	if (delta & UART01x_FR_CTS)
1293 		uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1294 
1295 	wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1296 }
1297 
1298 static irqreturn_t pl011_int(int irq, void *dev_id)
1299 {
1300 	struct uart_amba_port *uap = dev_id;
1301 	unsigned long flags;
1302 	unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1303 	int handled = 0;
1304 	unsigned int dummy_read;
1305 
1306 	spin_lock_irqsave(&uap->port.lock, flags);
1307 	status = readw(uap->port.membase + UART011_MIS);
1308 	if (status) {
1309 		do {
1310 			if (uap->vendor->cts_event_workaround) {
1311 				/* workaround to make sure that all bits are unlocked.. */
1312 				writew(0x00, uap->port.membase + UART011_ICR);
1313 
1314 				/*
1315 				 * WA: introduce 26ns(1 uart clk) delay before W1C;
1316 				 * single apb access will incur 2 pclk(133.12Mhz) delay,
1317 				 * so add 2 dummy reads
1318 				 */
1319 				dummy_read = readw(uap->port.membase + UART011_ICR);
1320 				dummy_read = readw(uap->port.membase + UART011_ICR);
1321 			}
1322 
1323 			writew(status & ~(UART011_TXIS|UART011_RTIS|
1324 					  UART011_RXIS),
1325 			       uap->port.membase + UART011_ICR);
1326 
1327 			if (status & (UART011_RTIS|UART011_RXIS)) {
1328 				if (pl011_dma_rx_running(uap))
1329 					pl011_dma_rx_irq(uap);
1330 				else
1331 					pl011_rx_chars(uap);
1332 			}
1333 			if (status & (UART011_DSRMIS|UART011_DCDMIS|
1334 				      UART011_CTSMIS|UART011_RIMIS))
1335 				pl011_modem_status(uap);
1336 			if (status & UART011_TXIS)
1337 				pl011_tx_chars(uap);
1338 
1339 			if (pass_counter-- == 0)
1340 				break;
1341 
1342 			status = readw(uap->port.membase + UART011_MIS);
1343 		} while (status != 0);
1344 		handled = 1;
1345 	}
1346 
1347 	spin_unlock_irqrestore(&uap->port.lock, flags);
1348 
1349 	return IRQ_RETVAL(handled);
1350 }
1351 
1352 static unsigned int pl011_tx_empty(struct uart_port *port)
1353 {
1354 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1355 	unsigned int status = readw(uap->port.membase + UART01x_FR);
1356 	return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1357 }
1358 
1359 static unsigned int pl011_get_mctrl(struct uart_port *port)
1360 {
1361 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1362 	unsigned int result = 0;
1363 	unsigned int status = readw(uap->port.membase + UART01x_FR);
1364 
1365 #define TIOCMBIT(uartbit, tiocmbit)	\
1366 	if (status & uartbit)		\
1367 		result |= tiocmbit
1368 
1369 	TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1370 	TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1371 	TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1372 	TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1373 #undef TIOCMBIT
1374 	return result;
1375 }
1376 
1377 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1378 {
1379 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1380 	unsigned int cr;
1381 
1382 	cr = readw(uap->port.membase + UART011_CR);
1383 
1384 #define	TIOCMBIT(tiocmbit, uartbit)		\
1385 	if (mctrl & tiocmbit)		\
1386 		cr |= uartbit;		\
1387 	else				\
1388 		cr &= ~uartbit
1389 
1390 	TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1391 	TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1392 	TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1393 	TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1394 	TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1395 
1396 	if (uap->autorts) {
1397 		/* We need to disable auto-RTS if we want to turn RTS off */
1398 		TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1399 	}
1400 #undef TIOCMBIT
1401 
1402 	writew(cr, uap->port.membase + UART011_CR);
1403 }
1404 
1405 static void pl011_break_ctl(struct uart_port *port, int break_state)
1406 {
1407 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1408 	unsigned long flags;
1409 	unsigned int lcr_h;
1410 
1411 	spin_lock_irqsave(&uap->port.lock, flags);
1412 	lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1413 	if (break_state == -1)
1414 		lcr_h |= UART01x_LCRH_BRK;
1415 	else
1416 		lcr_h &= ~UART01x_LCRH_BRK;
1417 	writew(lcr_h, uap->port.membase + uap->lcrh_tx);
1418 	spin_unlock_irqrestore(&uap->port.lock, flags);
1419 }
1420 
1421 #ifdef CONFIG_CONSOLE_POLL
1422 
1423 static void pl011_quiesce_irqs(struct uart_port *port)
1424 {
1425 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1426 	unsigned char __iomem *regs = uap->port.membase;
1427 
1428 	writew(readw(regs + UART011_MIS), regs + UART011_ICR);
1429 	/*
1430 	 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1431 	 * we simply mask it. start_tx() will unmask it.
1432 	 *
1433 	 * Note we can race with start_tx(), and if the race happens, the
1434 	 * polling user might get another interrupt just after we clear it.
1435 	 * But it should be OK and can happen even w/o the race, e.g.
1436 	 * controller immediately got some new data and raised the IRQ.
1437 	 *
1438 	 * And whoever uses polling routines assumes that it manages the device
1439 	 * (including tx queue), so we're also fine with start_tx()'s caller
1440 	 * side.
1441 	 */
1442 	writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC);
1443 }
1444 
1445 static int pl011_get_poll_char(struct uart_port *port)
1446 {
1447 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1448 	unsigned int status;
1449 
1450 	/*
1451 	 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1452 	 * debugger.
1453 	 */
1454 	pl011_quiesce_irqs(port);
1455 
1456 	status = readw(uap->port.membase + UART01x_FR);
1457 	if (status & UART01x_FR_RXFE)
1458 		return NO_POLL_CHAR;
1459 
1460 	return readw(uap->port.membase + UART01x_DR);
1461 }
1462 
1463 static void pl011_put_poll_char(struct uart_port *port,
1464 			 unsigned char ch)
1465 {
1466 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1467 
1468 	while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1469 		barrier();
1470 
1471 	writew(ch, uap->port.membase + UART01x_DR);
1472 }
1473 
1474 #endif /* CONFIG_CONSOLE_POLL */
1475 
1476 static int pl011_hwinit(struct uart_port *port)
1477 {
1478 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1479 	int retval;
1480 
1481 	/* Optionaly enable pins to be muxed in and configured */
1482 	pinctrl_pm_select_default_state(port->dev);
1483 
1484 	/*
1485 	 * Try to enable the clock producer.
1486 	 */
1487 	retval = clk_prepare_enable(uap->clk);
1488 	if (retval)
1489 		goto out;
1490 
1491 	uap->port.uartclk = clk_get_rate(uap->clk);
1492 
1493 	/* Clear pending error and receive interrupts */
1494 	writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
1495 	       UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
1496 
1497 	/*
1498 	 * Save interrupts enable mask, and enable RX interrupts in case if
1499 	 * the interrupt is used for NMI entry.
1500 	 */
1501 	uap->im = readw(uap->port.membase + UART011_IMSC);
1502 	writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC);
1503 
1504 	if (dev_get_platdata(uap->port.dev)) {
1505 		struct amba_pl011_data *plat;
1506 
1507 		plat = dev_get_platdata(uap->port.dev);
1508 		if (plat->init)
1509 			plat->init();
1510 	}
1511 	return 0;
1512  out:
1513 	return retval;
1514 }
1515 
1516 static int pl011_startup(struct uart_port *port)
1517 {
1518 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1519 	unsigned int cr;
1520 	int retval;
1521 
1522 	retval = pl011_hwinit(port);
1523 	if (retval)
1524 		goto clk_dis;
1525 
1526 	writew(uap->im, uap->port.membase + UART011_IMSC);
1527 
1528 	/*
1529 	 * Allocate the IRQ
1530 	 */
1531 	retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1532 	if (retval)
1533 		goto clk_dis;
1534 
1535 	writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
1536 
1537 	/*
1538 	 * Provoke TX FIFO interrupt into asserting.
1539 	 */
1540 	cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
1541 	writew(cr, uap->port.membase + UART011_CR);
1542 	writew(0, uap->port.membase + UART011_FBRD);
1543 	writew(1, uap->port.membase + UART011_IBRD);
1544 	writew(0, uap->port.membase + uap->lcrh_rx);
1545 	if (uap->lcrh_tx != uap->lcrh_rx) {
1546 		int i;
1547 		/*
1548 		 * Wait 10 PCLKs before writing LCRH_TX register,
1549 		 * to get this delay write read only register 10 times
1550 		 */
1551 		for (i = 0; i < 10; ++i)
1552 			writew(0xff, uap->port.membase + UART011_MIS);
1553 		writew(0, uap->port.membase + uap->lcrh_tx);
1554 	}
1555 	writew(0, uap->port.membase + UART01x_DR);
1556 	while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1557 		barrier();
1558 
1559 	/* restore RTS and DTR */
1560 	cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1561 	cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1562 	writew(cr, uap->port.membase + UART011_CR);
1563 
1564 	/*
1565 	 * initialise the old status of the modem signals
1566 	 */
1567 	uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1568 
1569 	/* Startup DMA */
1570 	pl011_dma_startup(uap);
1571 
1572 	/*
1573 	 * Finally, enable interrupts, only timeouts when using DMA
1574 	 * if initial RX DMA job failed, start in interrupt mode
1575 	 * as well.
1576 	 */
1577 	spin_lock_irq(&uap->port.lock);
1578 	/* Clear out any spuriously appearing RX interrupts */
1579 	 writew(UART011_RTIS | UART011_RXIS,
1580 		uap->port.membase + UART011_ICR);
1581 	uap->im = UART011_RTIM;
1582 	if (!pl011_dma_rx_running(uap))
1583 		uap->im |= UART011_RXIM;
1584 	writew(uap->im, uap->port.membase + UART011_IMSC);
1585 	spin_unlock_irq(&uap->port.lock);
1586 
1587 	return 0;
1588 
1589  clk_dis:
1590 	clk_disable_unprepare(uap->clk);
1591 	return retval;
1592 }
1593 
1594 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1595 					unsigned int lcrh)
1596 {
1597       unsigned long val;
1598 
1599       val = readw(uap->port.membase + lcrh);
1600       val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1601       writew(val, uap->port.membase + lcrh);
1602 }
1603 
1604 static void pl011_shutdown(struct uart_port *port)
1605 {
1606 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1607 	unsigned int cr;
1608 
1609 	/*
1610 	 * disable all interrupts
1611 	 */
1612 	spin_lock_irq(&uap->port.lock);
1613 	uap->im = 0;
1614 	writew(uap->im, uap->port.membase + UART011_IMSC);
1615 	writew(0xffff, uap->port.membase + UART011_ICR);
1616 	spin_unlock_irq(&uap->port.lock);
1617 
1618 	pl011_dma_shutdown(uap);
1619 
1620 	/*
1621 	 * Free the interrupt
1622 	 */
1623 	free_irq(uap->port.irq, uap);
1624 
1625 	/*
1626 	 * disable the port
1627 	 * disable the port. It should not disable RTS and DTR.
1628 	 * Also RTS and DTR state should be preserved to restore
1629 	 * it during startup().
1630 	 */
1631 	uap->autorts = false;
1632 	cr = readw(uap->port.membase + UART011_CR);
1633 	uap->old_cr = cr;
1634 	cr &= UART011_CR_RTS | UART011_CR_DTR;
1635 	cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1636 	writew(cr, uap->port.membase + UART011_CR);
1637 
1638 	/*
1639 	 * disable break condition and fifos
1640 	 */
1641 	pl011_shutdown_channel(uap, uap->lcrh_rx);
1642 	if (uap->lcrh_rx != uap->lcrh_tx)
1643 		pl011_shutdown_channel(uap, uap->lcrh_tx);
1644 
1645 	/*
1646 	 * Shut down the clock producer
1647 	 */
1648 	clk_disable_unprepare(uap->clk);
1649 	/* Optionally let pins go into sleep states */
1650 	pinctrl_pm_select_sleep_state(port->dev);
1651 
1652 	if (dev_get_platdata(uap->port.dev)) {
1653 		struct amba_pl011_data *plat;
1654 
1655 		plat = dev_get_platdata(uap->port.dev);
1656 		if (plat->exit)
1657 			plat->exit();
1658 	}
1659 
1660 }
1661 
1662 static void
1663 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1664 		     struct ktermios *old)
1665 {
1666 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1667 	unsigned int lcr_h, old_cr;
1668 	unsigned long flags;
1669 	unsigned int baud, quot, clkdiv;
1670 
1671 	if (uap->vendor->oversampling)
1672 		clkdiv = 8;
1673 	else
1674 		clkdiv = 16;
1675 
1676 	/*
1677 	 * Ask the core to calculate the divisor for us.
1678 	 */
1679 	baud = uart_get_baud_rate(port, termios, old, 0,
1680 				  port->uartclk / clkdiv);
1681 #ifdef CONFIG_DMA_ENGINE
1682 	/*
1683 	 * Adjust RX DMA polling rate with baud rate if not specified.
1684 	 */
1685 	if (uap->dmarx.auto_poll_rate)
1686 		uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1687 #endif
1688 
1689 	if (baud > port->uartclk/16)
1690 		quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1691 	else
1692 		quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1693 
1694 	switch (termios->c_cflag & CSIZE) {
1695 	case CS5:
1696 		lcr_h = UART01x_LCRH_WLEN_5;
1697 		break;
1698 	case CS6:
1699 		lcr_h = UART01x_LCRH_WLEN_6;
1700 		break;
1701 	case CS7:
1702 		lcr_h = UART01x_LCRH_WLEN_7;
1703 		break;
1704 	default: // CS8
1705 		lcr_h = UART01x_LCRH_WLEN_8;
1706 		break;
1707 	}
1708 	if (termios->c_cflag & CSTOPB)
1709 		lcr_h |= UART01x_LCRH_STP2;
1710 	if (termios->c_cflag & PARENB) {
1711 		lcr_h |= UART01x_LCRH_PEN;
1712 		if (!(termios->c_cflag & PARODD))
1713 			lcr_h |= UART01x_LCRH_EPS;
1714 	}
1715 	if (uap->fifosize > 1)
1716 		lcr_h |= UART01x_LCRH_FEN;
1717 
1718 	spin_lock_irqsave(&port->lock, flags);
1719 
1720 	/*
1721 	 * Update the per-port timeout.
1722 	 */
1723 	uart_update_timeout(port, termios->c_cflag, baud);
1724 
1725 	port->read_status_mask = UART011_DR_OE | 255;
1726 	if (termios->c_iflag & INPCK)
1727 		port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1728 	if (termios->c_iflag & (BRKINT | PARMRK))
1729 		port->read_status_mask |= UART011_DR_BE;
1730 
1731 	/*
1732 	 * Characters to ignore
1733 	 */
1734 	port->ignore_status_mask = 0;
1735 	if (termios->c_iflag & IGNPAR)
1736 		port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1737 	if (termios->c_iflag & IGNBRK) {
1738 		port->ignore_status_mask |= UART011_DR_BE;
1739 		/*
1740 		 * If we're ignoring parity and break indicators,
1741 		 * ignore overruns too (for real raw support).
1742 		 */
1743 		if (termios->c_iflag & IGNPAR)
1744 			port->ignore_status_mask |= UART011_DR_OE;
1745 	}
1746 
1747 	/*
1748 	 * Ignore all characters if CREAD is not set.
1749 	 */
1750 	if ((termios->c_cflag & CREAD) == 0)
1751 		port->ignore_status_mask |= UART_DUMMY_DR_RX;
1752 
1753 	if (UART_ENABLE_MS(port, termios->c_cflag))
1754 		pl011_enable_ms(port);
1755 
1756 	/* first, disable everything */
1757 	old_cr = readw(port->membase + UART011_CR);
1758 	writew(0, port->membase + UART011_CR);
1759 
1760 	if (termios->c_cflag & CRTSCTS) {
1761 		if (old_cr & UART011_CR_RTS)
1762 			old_cr |= UART011_CR_RTSEN;
1763 
1764 		old_cr |= UART011_CR_CTSEN;
1765 		uap->autorts = true;
1766 	} else {
1767 		old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1768 		uap->autorts = false;
1769 	}
1770 
1771 	if (uap->vendor->oversampling) {
1772 		if (baud > port->uartclk / 16)
1773 			old_cr |= ST_UART011_CR_OVSFACT;
1774 		else
1775 			old_cr &= ~ST_UART011_CR_OVSFACT;
1776 	}
1777 
1778 	/*
1779 	 * Workaround for the ST Micro oversampling variants to
1780 	 * increase the bitrate slightly, by lowering the divisor,
1781 	 * to avoid delayed sampling of start bit at high speeds,
1782 	 * else we see data corruption.
1783 	 */
1784 	if (uap->vendor->oversampling) {
1785 		if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
1786 			quot -= 1;
1787 		else if ((baud > 3250000) && (quot > 2))
1788 			quot -= 2;
1789 	}
1790 	/* Set baud rate */
1791 	writew(quot & 0x3f, port->membase + UART011_FBRD);
1792 	writew(quot >> 6, port->membase + UART011_IBRD);
1793 
1794 	/*
1795 	 * ----------v----------v----------v----------v-----
1796 	 * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER
1797 	 * UART011_FBRD & UART011_IBRD.
1798 	 * ----------^----------^----------^----------^-----
1799 	 */
1800 	writew(lcr_h, port->membase + uap->lcrh_rx);
1801 	if (uap->lcrh_rx != uap->lcrh_tx) {
1802 		int i;
1803 		/*
1804 		 * Wait 10 PCLKs before writing LCRH_TX register,
1805 		 * to get this delay write read only register 10 times
1806 		 */
1807 		for (i = 0; i < 10; ++i)
1808 			writew(0xff, uap->port.membase + UART011_MIS);
1809 		writew(lcr_h, port->membase + uap->lcrh_tx);
1810 	}
1811 	writew(old_cr, port->membase + UART011_CR);
1812 
1813 	spin_unlock_irqrestore(&port->lock, flags);
1814 }
1815 
1816 static const char *pl011_type(struct uart_port *port)
1817 {
1818 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1819 	return uap->port.type == PORT_AMBA ? uap->type : NULL;
1820 }
1821 
1822 /*
1823  * Release the memory region(s) being used by 'port'
1824  */
1825 static void pl011_release_port(struct uart_port *port)
1826 {
1827 	release_mem_region(port->mapbase, SZ_4K);
1828 }
1829 
1830 /*
1831  * Request the memory region(s) being used by 'port'
1832  */
1833 static int pl011_request_port(struct uart_port *port)
1834 {
1835 	return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1836 			!= NULL ? 0 : -EBUSY;
1837 }
1838 
1839 /*
1840  * Configure/autoconfigure the port.
1841  */
1842 static void pl011_config_port(struct uart_port *port, int flags)
1843 {
1844 	if (flags & UART_CONFIG_TYPE) {
1845 		port->type = PORT_AMBA;
1846 		pl011_request_port(port);
1847 	}
1848 }
1849 
1850 /*
1851  * verify the new serial_struct (for TIOCSSERIAL).
1852  */
1853 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
1854 {
1855 	int ret = 0;
1856 	if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
1857 		ret = -EINVAL;
1858 	if (ser->irq < 0 || ser->irq >= nr_irqs)
1859 		ret = -EINVAL;
1860 	if (ser->baud_base < 9600)
1861 		ret = -EINVAL;
1862 	return ret;
1863 }
1864 
1865 static struct uart_ops amba_pl011_pops = {
1866 	.tx_empty	= pl011_tx_empty,
1867 	.set_mctrl	= pl011_set_mctrl,
1868 	.get_mctrl	= pl011_get_mctrl,
1869 	.stop_tx	= pl011_stop_tx,
1870 	.start_tx	= pl011_start_tx,
1871 	.stop_rx	= pl011_stop_rx,
1872 	.enable_ms	= pl011_enable_ms,
1873 	.break_ctl	= pl011_break_ctl,
1874 	.startup	= pl011_startup,
1875 	.shutdown	= pl011_shutdown,
1876 	.flush_buffer	= pl011_dma_flush_buffer,
1877 	.set_termios	= pl011_set_termios,
1878 	.type		= pl011_type,
1879 	.release_port	= pl011_release_port,
1880 	.request_port	= pl011_request_port,
1881 	.config_port	= pl011_config_port,
1882 	.verify_port	= pl011_verify_port,
1883 #ifdef CONFIG_CONSOLE_POLL
1884 	.poll_init     = pl011_hwinit,
1885 	.poll_get_char = pl011_get_poll_char,
1886 	.poll_put_char = pl011_put_poll_char,
1887 #endif
1888 };
1889 
1890 static struct uart_amba_port *amba_ports[UART_NR];
1891 
1892 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
1893 
1894 static void pl011_console_putchar(struct uart_port *port, int ch)
1895 {
1896 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
1897 
1898 	while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1899 		barrier();
1900 	writew(ch, uap->port.membase + UART01x_DR);
1901 }
1902 
1903 static void
1904 pl011_console_write(struct console *co, const char *s, unsigned int count)
1905 {
1906 	struct uart_amba_port *uap = amba_ports[co->index];
1907 	unsigned int status, old_cr, new_cr;
1908 	unsigned long flags;
1909 	int locked = 1;
1910 
1911 	clk_enable(uap->clk);
1912 
1913 	local_irq_save(flags);
1914 	if (uap->port.sysrq)
1915 		locked = 0;
1916 	else if (oops_in_progress)
1917 		locked = spin_trylock(&uap->port.lock);
1918 	else
1919 		spin_lock(&uap->port.lock);
1920 
1921 	/*
1922 	 *	First save the CR then disable the interrupts
1923 	 */
1924 	old_cr = readw(uap->port.membase + UART011_CR);
1925 	new_cr = old_cr & ~UART011_CR_CTSEN;
1926 	new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1927 	writew(new_cr, uap->port.membase + UART011_CR);
1928 
1929 	uart_console_write(&uap->port, s, count, pl011_console_putchar);
1930 
1931 	/*
1932 	 *	Finally, wait for transmitter to become empty
1933 	 *	and restore the TCR
1934 	 */
1935 	do {
1936 		status = readw(uap->port.membase + UART01x_FR);
1937 	} while (status & UART01x_FR_BUSY);
1938 	writew(old_cr, uap->port.membase + UART011_CR);
1939 
1940 	if (locked)
1941 		spin_unlock(&uap->port.lock);
1942 	local_irq_restore(flags);
1943 
1944 	clk_disable(uap->clk);
1945 }
1946 
1947 static void __init
1948 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1949 			     int *parity, int *bits)
1950 {
1951 	if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
1952 		unsigned int lcr_h, ibrd, fbrd;
1953 
1954 		lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1955 
1956 		*parity = 'n';
1957 		if (lcr_h & UART01x_LCRH_PEN) {
1958 			if (lcr_h & UART01x_LCRH_EPS)
1959 				*parity = 'e';
1960 			else
1961 				*parity = 'o';
1962 		}
1963 
1964 		if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
1965 			*bits = 7;
1966 		else
1967 			*bits = 8;
1968 
1969 		ibrd = readw(uap->port.membase + UART011_IBRD);
1970 		fbrd = readw(uap->port.membase + UART011_FBRD);
1971 
1972 		*baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
1973 
1974 		if (uap->vendor->oversampling) {
1975 			if (readw(uap->port.membase + UART011_CR)
1976 				  & ST_UART011_CR_OVSFACT)
1977 				*baud *= 2;
1978 		}
1979 	}
1980 }
1981 
1982 static int __init pl011_console_setup(struct console *co, char *options)
1983 {
1984 	struct uart_amba_port *uap;
1985 	int baud = 38400;
1986 	int bits = 8;
1987 	int parity = 'n';
1988 	int flow = 'n';
1989 	int ret;
1990 
1991 	/*
1992 	 * Check whether an invalid uart number has been specified, and
1993 	 * if so, search for the first available port that does have
1994 	 * console support.
1995 	 */
1996 	if (co->index >= UART_NR)
1997 		co->index = 0;
1998 	uap = amba_ports[co->index];
1999 	if (!uap)
2000 		return -ENODEV;
2001 
2002 	/* Allow pins to be muxed in and configured */
2003 	pinctrl_pm_select_default_state(uap->port.dev);
2004 
2005 	ret = clk_prepare(uap->clk);
2006 	if (ret)
2007 		return ret;
2008 
2009 	if (dev_get_platdata(uap->port.dev)) {
2010 		struct amba_pl011_data *plat;
2011 
2012 		plat = dev_get_platdata(uap->port.dev);
2013 		if (plat->init)
2014 			plat->init();
2015 	}
2016 
2017 	uap->port.uartclk = clk_get_rate(uap->clk);
2018 
2019 	if (options)
2020 		uart_parse_options(options, &baud, &parity, &bits, &flow);
2021 	else
2022 		pl011_console_get_options(uap, &baud, &parity, &bits);
2023 
2024 	return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2025 }
2026 
2027 static struct uart_driver amba_reg;
2028 static struct console amba_console = {
2029 	.name		= "ttyAMA",
2030 	.write		= pl011_console_write,
2031 	.device		= uart_console_device,
2032 	.setup		= pl011_console_setup,
2033 	.flags		= CON_PRINTBUFFER,
2034 	.index		= -1,
2035 	.data		= &amba_reg,
2036 };
2037 
2038 #define AMBA_CONSOLE	(&amba_console)
2039 #else
2040 #define AMBA_CONSOLE	NULL
2041 #endif
2042 
2043 static struct uart_driver amba_reg = {
2044 	.owner			= THIS_MODULE,
2045 	.driver_name		= "ttyAMA",
2046 	.dev_name		= "ttyAMA",
2047 	.major			= SERIAL_AMBA_MAJOR,
2048 	.minor			= SERIAL_AMBA_MINOR,
2049 	.nr			= UART_NR,
2050 	.cons			= AMBA_CONSOLE,
2051 };
2052 
2053 static int pl011_probe_dt_alias(int index, struct device *dev)
2054 {
2055 	struct device_node *np;
2056 	static bool seen_dev_with_alias = false;
2057 	static bool seen_dev_without_alias = false;
2058 	int ret = index;
2059 
2060 	if (!IS_ENABLED(CONFIG_OF))
2061 		return ret;
2062 
2063 	np = dev->of_node;
2064 	if (!np)
2065 		return ret;
2066 
2067 	ret = of_alias_get_id(np, "serial");
2068 	if (IS_ERR_VALUE(ret)) {
2069 		seen_dev_without_alias = true;
2070 		ret = index;
2071 	} else {
2072 		seen_dev_with_alias = true;
2073 		if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2074 			dev_warn(dev, "requested serial port %d  not available.\n", ret);
2075 			ret = index;
2076 		}
2077 	}
2078 
2079 	if (seen_dev_with_alias && seen_dev_without_alias)
2080 		dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2081 
2082 	return ret;
2083 }
2084 
2085 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2086 {
2087 	struct uart_amba_port *uap;
2088 	struct vendor_data *vendor = id->data;
2089 	void __iomem *base;
2090 	int i, ret;
2091 
2092 	for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2093 		if (amba_ports[i] == NULL)
2094 			break;
2095 
2096 	if (i == ARRAY_SIZE(amba_ports)) {
2097 		ret = -EBUSY;
2098 		goto out;
2099 	}
2100 
2101 	uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2102 			   GFP_KERNEL);
2103 	if (uap == NULL) {
2104 		ret = -ENOMEM;
2105 		goto out;
2106 	}
2107 
2108 	i = pl011_probe_dt_alias(i, &dev->dev);
2109 
2110 	base = devm_ioremap(&dev->dev, dev->res.start,
2111 			    resource_size(&dev->res));
2112 	if (!base) {
2113 		ret = -ENOMEM;
2114 		goto out;
2115 	}
2116 
2117 	uap->clk = devm_clk_get(&dev->dev, NULL);
2118 	if (IS_ERR(uap->clk)) {
2119 		ret = PTR_ERR(uap->clk);
2120 		goto out;
2121 	}
2122 
2123 	uap->vendor = vendor;
2124 	uap->lcrh_rx = vendor->lcrh_rx;
2125 	uap->lcrh_tx = vendor->lcrh_tx;
2126 	uap->old_cr = 0;
2127 	uap->fifosize = vendor->get_fifosize(dev);
2128 	uap->port.dev = &dev->dev;
2129 	uap->port.mapbase = dev->res.start;
2130 	uap->port.membase = base;
2131 	uap->port.iotype = UPIO_MEM;
2132 	uap->port.irq = dev->irq[0];
2133 	uap->port.fifosize = uap->fifosize;
2134 	uap->port.ops = &amba_pl011_pops;
2135 	uap->port.flags = UPF_BOOT_AUTOCONF;
2136 	uap->port.line = i;
2137 	pl011_dma_probe(&dev->dev, uap);
2138 
2139 	/* Ensure interrupts from this UART are masked and cleared */
2140 	writew(0, uap->port.membase + UART011_IMSC);
2141 	writew(0xffff, uap->port.membase + UART011_ICR);
2142 
2143 	snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2144 
2145 	amba_ports[i] = uap;
2146 
2147 	amba_set_drvdata(dev, uap);
2148 	ret = uart_add_one_port(&amba_reg, &uap->port);
2149 	if (ret) {
2150 		amba_set_drvdata(dev, NULL);
2151 		amba_ports[i] = NULL;
2152 		pl011_dma_remove(uap);
2153 	}
2154  out:
2155 	return ret;
2156 }
2157 
2158 static int pl011_remove(struct amba_device *dev)
2159 {
2160 	struct uart_amba_port *uap = amba_get_drvdata(dev);
2161 	int i;
2162 
2163 	amba_set_drvdata(dev, NULL);
2164 
2165 	uart_remove_one_port(&amba_reg, &uap->port);
2166 
2167 	for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2168 		if (amba_ports[i] == uap)
2169 			amba_ports[i] = NULL;
2170 
2171 	pl011_dma_remove(uap);
2172 	return 0;
2173 }
2174 
2175 #ifdef CONFIG_PM
2176 static int pl011_suspend(struct amba_device *dev, pm_message_t state)
2177 {
2178 	struct uart_amba_port *uap = amba_get_drvdata(dev);
2179 
2180 	if (!uap)
2181 		return -EINVAL;
2182 
2183 	return uart_suspend_port(&amba_reg, &uap->port);
2184 }
2185 
2186 static int pl011_resume(struct amba_device *dev)
2187 {
2188 	struct uart_amba_port *uap = amba_get_drvdata(dev);
2189 
2190 	if (!uap)
2191 		return -EINVAL;
2192 
2193 	return uart_resume_port(&amba_reg, &uap->port);
2194 }
2195 #endif
2196 
2197 static struct amba_id pl011_ids[] = {
2198 	{
2199 		.id	= 0x00041011,
2200 		.mask	= 0x000fffff,
2201 		.data	= &vendor_arm,
2202 	},
2203 	{
2204 		.id	= 0x00380802,
2205 		.mask	= 0x00ffffff,
2206 		.data	= &vendor_st,
2207 	},
2208 	{ 0, 0 },
2209 };
2210 
2211 MODULE_DEVICE_TABLE(amba, pl011_ids);
2212 
2213 static struct amba_driver pl011_driver = {
2214 	.drv = {
2215 		.name	= "uart-pl011",
2216 	},
2217 	.id_table	= pl011_ids,
2218 	.probe		= pl011_probe,
2219 	.remove		= pl011_remove,
2220 #ifdef CONFIG_PM
2221 	.suspend	= pl011_suspend,
2222 	.resume		= pl011_resume,
2223 #endif
2224 };
2225 
2226 static int __init pl011_init(void)
2227 {
2228 	int ret;
2229 	printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2230 
2231 	ret = uart_register_driver(&amba_reg);
2232 	if (ret == 0) {
2233 		ret = amba_driver_register(&pl011_driver);
2234 		if (ret)
2235 			uart_unregister_driver(&amba_reg);
2236 	}
2237 	return ret;
2238 }
2239 
2240 static void __exit pl011_exit(void)
2241 {
2242 	amba_driver_unregister(&pl011_driver);
2243 	uart_unregister_driver(&amba_reg);
2244 }
2245 
2246 /*
2247  * While this can be a module, if builtin it's most likely the console
2248  * So let's leave module_exit but move module_init to an earlier place
2249  */
2250 arch_initcall(pl011_init);
2251 module_exit(pl011_exit);
2252 
2253 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2254 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2255 MODULE_LICENSE("GPL");
2256