1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for AMBA serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright 1999 ARM Limited 8 * Copyright (C) 2000 Deep Blue Solutions Ltd. 9 * Copyright (C) 2010 ST-Ericsson SA 10 * 11 * This is a generic driver for ARM AMBA-type serial ports. They 12 * have a lot of 16550-like features, but are not register compatible. 13 * Note that although they do have CTS, DCD and DSR inputs, they do 14 * not have an RI input, nor do they have DTR or RTS outputs. If 15 * required, these have to be supplied via some other means (eg, GPIO) 16 * and hooked into this driver. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/ioport.h> 21 #include <linux/init.h> 22 #include <linux/console.h> 23 #include <linux/sysrq.h> 24 #include <linux/device.h> 25 #include <linux/tty.h> 26 #include <linux/tty_flip.h> 27 #include <linux/serial_core.h> 28 #include <linux/serial.h> 29 #include <linux/amba/bus.h> 30 #include <linux/amba/serial.h> 31 #include <linux/clk.h> 32 #include <linux/slab.h> 33 #include <linux/dmaengine.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/scatterlist.h> 36 #include <linux/delay.h> 37 #include <linux/types.h> 38 #include <linux/of.h> 39 #include <linux/of_device.h> 40 #include <linux/pinctrl/consumer.h> 41 #include <linux/sizes.h> 42 #include <linux/io.h> 43 #include <linux/acpi.h> 44 45 #include "amba-pl011.h" 46 47 #define UART_NR 14 48 49 #define SERIAL_AMBA_MAJOR 204 50 #define SERIAL_AMBA_MINOR 64 51 #define SERIAL_AMBA_NR UART_NR 52 53 #define AMBA_ISR_PASS_LIMIT 256 54 55 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) 56 #define UART_DUMMY_DR_RX (1 << 16) 57 58 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = { 59 [REG_DR] = UART01x_DR, 60 [REG_FR] = UART01x_FR, 61 [REG_LCRH_RX] = UART011_LCRH, 62 [REG_LCRH_TX] = UART011_LCRH, 63 [REG_IBRD] = UART011_IBRD, 64 [REG_FBRD] = UART011_FBRD, 65 [REG_CR] = UART011_CR, 66 [REG_IFLS] = UART011_IFLS, 67 [REG_IMSC] = UART011_IMSC, 68 [REG_RIS] = UART011_RIS, 69 [REG_MIS] = UART011_MIS, 70 [REG_ICR] = UART011_ICR, 71 [REG_DMACR] = UART011_DMACR, 72 }; 73 74 /* There is by now at least one vendor with differing details, so handle it */ 75 struct vendor_data { 76 const u16 *reg_offset; 77 unsigned int ifls; 78 unsigned int fr_busy; 79 unsigned int fr_dsr; 80 unsigned int fr_cts; 81 unsigned int fr_ri; 82 unsigned int inv_fr; 83 bool access_32b; 84 bool oversampling; 85 bool dma_threshold; 86 bool cts_event_workaround; 87 bool always_enabled; 88 bool fixed_options; 89 90 unsigned int (*get_fifosize)(struct amba_device *dev); 91 }; 92 93 static unsigned int get_fifosize_arm(struct amba_device *dev) 94 { 95 return amba_rev(dev) < 3 ? 16 : 32; 96 } 97 98 static struct vendor_data vendor_arm = { 99 .reg_offset = pl011_std_offsets, 100 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 101 .fr_busy = UART01x_FR_BUSY, 102 .fr_dsr = UART01x_FR_DSR, 103 .fr_cts = UART01x_FR_CTS, 104 .fr_ri = UART011_FR_RI, 105 .oversampling = false, 106 .dma_threshold = false, 107 .cts_event_workaround = false, 108 .always_enabled = false, 109 .fixed_options = false, 110 .get_fifosize = get_fifosize_arm, 111 }; 112 113 static const struct vendor_data vendor_sbsa = { 114 .reg_offset = pl011_std_offsets, 115 .fr_busy = UART01x_FR_BUSY, 116 .fr_dsr = UART01x_FR_DSR, 117 .fr_cts = UART01x_FR_CTS, 118 .fr_ri = UART011_FR_RI, 119 .access_32b = true, 120 .oversampling = false, 121 .dma_threshold = false, 122 .cts_event_workaround = false, 123 .always_enabled = true, 124 .fixed_options = true, 125 }; 126 127 #ifdef CONFIG_ACPI_SPCR_TABLE 128 static const struct vendor_data vendor_qdt_qdf2400_e44 = { 129 .reg_offset = pl011_std_offsets, 130 .fr_busy = UART011_FR_TXFE, 131 .fr_dsr = UART01x_FR_DSR, 132 .fr_cts = UART01x_FR_CTS, 133 .fr_ri = UART011_FR_RI, 134 .inv_fr = UART011_FR_TXFE, 135 .access_32b = true, 136 .oversampling = false, 137 .dma_threshold = false, 138 .cts_event_workaround = false, 139 .always_enabled = true, 140 .fixed_options = true, 141 }; 142 #endif 143 144 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { 145 [REG_DR] = UART01x_DR, 146 [REG_ST_DMAWM] = ST_UART011_DMAWM, 147 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, 148 [REG_FR] = UART01x_FR, 149 [REG_LCRH_RX] = ST_UART011_LCRH_RX, 150 [REG_LCRH_TX] = ST_UART011_LCRH_TX, 151 [REG_IBRD] = UART011_IBRD, 152 [REG_FBRD] = UART011_FBRD, 153 [REG_CR] = UART011_CR, 154 [REG_IFLS] = UART011_IFLS, 155 [REG_IMSC] = UART011_IMSC, 156 [REG_RIS] = UART011_RIS, 157 [REG_MIS] = UART011_MIS, 158 [REG_ICR] = UART011_ICR, 159 [REG_DMACR] = UART011_DMACR, 160 [REG_ST_XFCR] = ST_UART011_XFCR, 161 [REG_ST_XON1] = ST_UART011_XON1, 162 [REG_ST_XON2] = ST_UART011_XON2, 163 [REG_ST_XOFF1] = ST_UART011_XOFF1, 164 [REG_ST_XOFF2] = ST_UART011_XOFF2, 165 [REG_ST_ITCR] = ST_UART011_ITCR, 166 [REG_ST_ITIP] = ST_UART011_ITIP, 167 [REG_ST_ABCR] = ST_UART011_ABCR, 168 [REG_ST_ABIMSC] = ST_UART011_ABIMSC, 169 }; 170 171 static unsigned int get_fifosize_st(struct amba_device *dev) 172 { 173 return 64; 174 } 175 176 static struct vendor_data vendor_st = { 177 .reg_offset = pl011_st_offsets, 178 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, 179 .fr_busy = UART01x_FR_BUSY, 180 .fr_dsr = UART01x_FR_DSR, 181 .fr_cts = UART01x_FR_CTS, 182 .fr_ri = UART011_FR_RI, 183 .oversampling = true, 184 .dma_threshold = true, 185 .cts_event_workaround = true, 186 .always_enabled = false, 187 .fixed_options = false, 188 .get_fifosize = get_fifosize_st, 189 }; 190 191 /* Deals with DMA transactions */ 192 193 struct pl011_sgbuf { 194 struct scatterlist sg; 195 char *buf; 196 }; 197 198 struct pl011_dmarx_data { 199 struct dma_chan *chan; 200 struct completion complete; 201 bool use_buf_b; 202 struct pl011_sgbuf sgbuf_a; 203 struct pl011_sgbuf sgbuf_b; 204 dma_cookie_t cookie; 205 bool running; 206 struct timer_list timer; 207 unsigned int last_residue; 208 unsigned long last_jiffies; 209 bool auto_poll_rate; 210 unsigned int poll_rate; 211 unsigned int poll_timeout; 212 }; 213 214 struct pl011_dmatx_data { 215 struct dma_chan *chan; 216 struct scatterlist sg; 217 char *buf; 218 bool queued; 219 }; 220 221 /* 222 * We wrap our port structure around the generic uart_port. 223 */ 224 struct uart_amba_port { 225 struct uart_port port; 226 const u16 *reg_offset; 227 struct clk *clk; 228 const struct vendor_data *vendor; 229 unsigned int dmacr; /* dma control reg */ 230 unsigned int im; /* interrupt mask */ 231 unsigned int old_status; 232 unsigned int fifosize; /* vendor-specific */ 233 unsigned int fixed_baud; /* vendor-set fixed baud rate */ 234 char type[12]; 235 bool rs485_tx_started; 236 unsigned int rs485_tx_drain_interval; /* usecs */ 237 #ifdef CONFIG_DMA_ENGINE 238 /* DMA stuff */ 239 bool using_tx_dma; 240 bool using_rx_dma; 241 struct pl011_dmarx_data dmarx; 242 struct pl011_dmatx_data dmatx; 243 bool dma_probed; 244 #endif 245 }; 246 247 static unsigned int pl011_tx_empty(struct uart_port *port); 248 249 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, 250 unsigned int reg) 251 { 252 return uap->reg_offset[reg]; 253 } 254 255 static unsigned int pl011_read(const struct uart_amba_port *uap, 256 unsigned int reg) 257 { 258 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 259 260 return (uap->port.iotype == UPIO_MEM32) ? 261 readl_relaxed(addr) : readw_relaxed(addr); 262 } 263 264 static void pl011_write(unsigned int val, const struct uart_amba_port *uap, 265 unsigned int reg) 266 { 267 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 268 269 if (uap->port.iotype == UPIO_MEM32) 270 writel_relaxed(val, addr); 271 else 272 writew_relaxed(val, addr); 273 } 274 275 /* 276 * Reads up to 256 characters from the FIFO or until it's empty and 277 * inserts them into the TTY layer. Returns the number of characters 278 * read from the FIFO. 279 */ 280 static int pl011_fifo_to_tty(struct uart_amba_port *uap) 281 { 282 unsigned int ch, flag, fifotaken; 283 int sysrq; 284 u16 status; 285 286 for (fifotaken = 0; fifotaken != 256; fifotaken++) { 287 status = pl011_read(uap, REG_FR); 288 if (status & UART01x_FR_RXFE) 289 break; 290 291 /* Take chars from the FIFO and update status */ 292 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; 293 flag = TTY_NORMAL; 294 uap->port.icount.rx++; 295 296 if (unlikely(ch & UART_DR_ERROR)) { 297 if (ch & UART011_DR_BE) { 298 ch &= ~(UART011_DR_FE | UART011_DR_PE); 299 uap->port.icount.brk++; 300 if (uart_handle_break(&uap->port)) 301 continue; 302 } else if (ch & UART011_DR_PE) 303 uap->port.icount.parity++; 304 else if (ch & UART011_DR_FE) 305 uap->port.icount.frame++; 306 if (ch & UART011_DR_OE) 307 uap->port.icount.overrun++; 308 309 ch &= uap->port.read_status_mask; 310 311 if (ch & UART011_DR_BE) 312 flag = TTY_BREAK; 313 else if (ch & UART011_DR_PE) 314 flag = TTY_PARITY; 315 else if (ch & UART011_DR_FE) 316 flag = TTY_FRAME; 317 } 318 319 spin_unlock(&uap->port.lock); 320 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255); 321 spin_lock(&uap->port.lock); 322 323 if (!sysrq) 324 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); 325 } 326 327 return fifotaken; 328 } 329 330 331 /* 332 * All the DMA operation mode stuff goes inside this ifdef. 333 * This assumes that you have a generic DMA device interface, 334 * no custom DMA interfaces are supported. 335 */ 336 #ifdef CONFIG_DMA_ENGINE 337 338 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE 339 340 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, 341 enum dma_data_direction dir) 342 { 343 dma_addr_t dma_addr; 344 345 sg->buf = dma_alloc_coherent(chan->device->dev, 346 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); 347 if (!sg->buf) 348 return -ENOMEM; 349 350 sg_init_table(&sg->sg, 1); 351 sg_set_page(&sg->sg, phys_to_page(dma_addr), 352 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); 353 sg_dma_address(&sg->sg) = dma_addr; 354 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; 355 356 return 0; 357 } 358 359 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, 360 enum dma_data_direction dir) 361 { 362 if (sg->buf) { 363 dma_free_coherent(chan->device->dev, 364 PL011_DMA_BUFFER_SIZE, sg->buf, 365 sg_dma_address(&sg->sg)); 366 } 367 } 368 369 static void pl011_dma_probe(struct uart_amba_port *uap) 370 { 371 /* DMA is the sole user of the platform data right now */ 372 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); 373 struct device *dev = uap->port.dev; 374 struct dma_slave_config tx_conf = { 375 .dst_addr = uap->port.mapbase + 376 pl011_reg_to_offset(uap, REG_DR), 377 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 378 .direction = DMA_MEM_TO_DEV, 379 .dst_maxburst = uap->fifosize >> 1, 380 .device_fc = false, 381 }; 382 struct dma_chan *chan; 383 dma_cap_mask_t mask; 384 385 uap->dma_probed = true; 386 chan = dma_request_chan(dev, "tx"); 387 if (IS_ERR(chan)) { 388 if (PTR_ERR(chan) == -EPROBE_DEFER) { 389 uap->dma_probed = false; 390 return; 391 } 392 393 /* We need platform data */ 394 if (!plat || !plat->dma_filter) { 395 dev_info(uap->port.dev, "no DMA platform data\n"); 396 return; 397 } 398 399 /* Try to acquire a generic DMA engine slave TX channel */ 400 dma_cap_zero(mask); 401 dma_cap_set(DMA_SLAVE, mask); 402 403 chan = dma_request_channel(mask, plat->dma_filter, 404 plat->dma_tx_param); 405 if (!chan) { 406 dev_err(uap->port.dev, "no TX DMA channel!\n"); 407 return; 408 } 409 } 410 411 dmaengine_slave_config(chan, &tx_conf); 412 uap->dmatx.chan = chan; 413 414 dev_info(uap->port.dev, "DMA channel TX %s\n", 415 dma_chan_name(uap->dmatx.chan)); 416 417 /* Optionally make use of an RX channel as well */ 418 chan = dma_request_slave_channel(dev, "rx"); 419 420 if (!chan && plat && plat->dma_rx_param) { 421 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); 422 423 if (!chan) { 424 dev_err(uap->port.dev, "no RX DMA channel!\n"); 425 return; 426 } 427 } 428 429 if (chan) { 430 struct dma_slave_config rx_conf = { 431 .src_addr = uap->port.mapbase + 432 pl011_reg_to_offset(uap, REG_DR), 433 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 434 .direction = DMA_DEV_TO_MEM, 435 .src_maxburst = uap->fifosize >> 2, 436 .device_fc = false, 437 }; 438 struct dma_slave_caps caps; 439 440 /* 441 * Some DMA controllers provide information on their capabilities. 442 * If the controller does, check for suitable residue processing 443 * otherwise assime all is well. 444 */ 445 if (0 == dma_get_slave_caps(chan, &caps)) { 446 if (caps.residue_granularity == 447 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { 448 dma_release_channel(chan); 449 dev_info(uap->port.dev, 450 "RX DMA disabled - no residue processing\n"); 451 return; 452 } 453 } 454 dmaengine_slave_config(chan, &rx_conf); 455 uap->dmarx.chan = chan; 456 457 uap->dmarx.auto_poll_rate = false; 458 if (plat && plat->dma_rx_poll_enable) { 459 /* Set poll rate if specified. */ 460 if (plat->dma_rx_poll_rate) { 461 uap->dmarx.auto_poll_rate = false; 462 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; 463 } else { 464 /* 465 * 100 ms defaults to poll rate if not 466 * specified. This will be adjusted with 467 * the baud rate at set_termios. 468 */ 469 uap->dmarx.auto_poll_rate = true; 470 uap->dmarx.poll_rate = 100; 471 } 472 /* 3 secs defaults poll_timeout if not specified. */ 473 if (plat->dma_rx_poll_timeout) 474 uap->dmarx.poll_timeout = 475 plat->dma_rx_poll_timeout; 476 else 477 uap->dmarx.poll_timeout = 3000; 478 } else if (!plat && dev->of_node) { 479 uap->dmarx.auto_poll_rate = of_property_read_bool( 480 dev->of_node, "auto-poll"); 481 if (uap->dmarx.auto_poll_rate) { 482 u32 x; 483 484 if (0 == of_property_read_u32(dev->of_node, 485 "poll-rate-ms", &x)) 486 uap->dmarx.poll_rate = x; 487 else 488 uap->dmarx.poll_rate = 100; 489 if (0 == of_property_read_u32(dev->of_node, 490 "poll-timeout-ms", &x)) 491 uap->dmarx.poll_timeout = x; 492 else 493 uap->dmarx.poll_timeout = 3000; 494 } 495 } 496 dev_info(uap->port.dev, "DMA channel RX %s\n", 497 dma_chan_name(uap->dmarx.chan)); 498 } 499 } 500 501 static void pl011_dma_remove(struct uart_amba_port *uap) 502 { 503 if (uap->dmatx.chan) 504 dma_release_channel(uap->dmatx.chan); 505 if (uap->dmarx.chan) 506 dma_release_channel(uap->dmarx.chan); 507 } 508 509 /* Forward declare these for the refill routine */ 510 static int pl011_dma_tx_refill(struct uart_amba_port *uap); 511 static void pl011_start_tx_pio(struct uart_amba_port *uap); 512 513 /* 514 * The current DMA TX buffer has been sent. 515 * Try to queue up another DMA buffer. 516 */ 517 static void pl011_dma_tx_callback(void *data) 518 { 519 struct uart_amba_port *uap = data; 520 struct pl011_dmatx_data *dmatx = &uap->dmatx; 521 unsigned long flags; 522 u16 dmacr; 523 524 spin_lock_irqsave(&uap->port.lock, flags); 525 if (uap->dmatx.queued) 526 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, 527 DMA_TO_DEVICE); 528 529 dmacr = uap->dmacr; 530 uap->dmacr = dmacr & ~UART011_TXDMAE; 531 pl011_write(uap->dmacr, uap, REG_DMACR); 532 533 /* 534 * If TX DMA was disabled, it means that we've stopped the DMA for 535 * some reason (eg, XOFF received, or we want to send an X-char.) 536 * 537 * Note: we need to be careful here of a potential race between DMA 538 * and the rest of the driver - if the driver disables TX DMA while 539 * a TX buffer completing, we must update the tx queued status to 540 * get further refills (hence we check dmacr). 541 */ 542 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || 543 uart_circ_empty(&uap->port.state->xmit)) { 544 uap->dmatx.queued = false; 545 spin_unlock_irqrestore(&uap->port.lock, flags); 546 return; 547 } 548 549 if (pl011_dma_tx_refill(uap) <= 0) 550 /* 551 * We didn't queue a DMA buffer for some reason, but we 552 * have data pending to be sent. Re-enable the TX IRQ. 553 */ 554 pl011_start_tx_pio(uap); 555 556 spin_unlock_irqrestore(&uap->port.lock, flags); 557 } 558 559 /* 560 * Try to refill the TX DMA buffer. 561 * Locking: called with port lock held and IRQs disabled. 562 * Returns: 563 * 1 if we queued up a TX DMA buffer. 564 * 0 if we didn't want to handle this by DMA 565 * <0 on error 566 */ 567 static int pl011_dma_tx_refill(struct uart_amba_port *uap) 568 { 569 struct pl011_dmatx_data *dmatx = &uap->dmatx; 570 struct dma_chan *chan = dmatx->chan; 571 struct dma_device *dma_dev = chan->device; 572 struct dma_async_tx_descriptor *desc; 573 struct circ_buf *xmit = &uap->port.state->xmit; 574 unsigned int count; 575 576 /* 577 * Try to avoid the overhead involved in using DMA if the 578 * transaction fits in the first half of the FIFO, by using 579 * the standard interrupt handling. This ensures that we 580 * issue a uart_write_wakeup() at the appropriate time. 581 */ 582 count = uart_circ_chars_pending(xmit); 583 if (count < (uap->fifosize >> 1)) { 584 uap->dmatx.queued = false; 585 return 0; 586 } 587 588 /* 589 * Bodge: don't send the last character by DMA, as this 590 * will prevent XON from notifying us to restart DMA. 591 */ 592 count -= 1; 593 594 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ 595 if (count > PL011_DMA_BUFFER_SIZE) 596 count = PL011_DMA_BUFFER_SIZE; 597 598 if (xmit->tail < xmit->head) 599 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); 600 else { 601 size_t first = UART_XMIT_SIZE - xmit->tail; 602 size_t second; 603 604 if (first > count) 605 first = count; 606 second = count - first; 607 608 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); 609 if (second) 610 memcpy(&dmatx->buf[first], &xmit->buf[0], second); 611 } 612 613 dmatx->sg.length = count; 614 615 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { 616 uap->dmatx.queued = false; 617 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); 618 return -EBUSY; 619 } 620 621 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, 622 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 623 if (!desc) { 624 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); 625 uap->dmatx.queued = false; 626 /* 627 * If DMA cannot be used right now, we complete this 628 * transaction via IRQ and let the TTY layer retry. 629 */ 630 dev_dbg(uap->port.dev, "TX DMA busy\n"); 631 return -EBUSY; 632 } 633 634 /* Some data to go along to the callback */ 635 desc->callback = pl011_dma_tx_callback; 636 desc->callback_param = uap; 637 638 /* All errors should happen at prepare time */ 639 dmaengine_submit(desc); 640 641 /* Fire the DMA transaction */ 642 dma_dev->device_issue_pending(chan); 643 644 uap->dmacr |= UART011_TXDMAE; 645 pl011_write(uap->dmacr, uap, REG_DMACR); 646 uap->dmatx.queued = true; 647 648 /* 649 * Now we know that DMA will fire, so advance the ring buffer 650 * with the stuff we just dispatched. 651 */ 652 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 653 uap->port.icount.tx += count; 654 655 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 656 uart_write_wakeup(&uap->port); 657 658 return 1; 659 } 660 661 /* 662 * We received a transmit interrupt without a pending X-char but with 663 * pending characters. 664 * Locking: called with port lock held and IRQs disabled. 665 * Returns: 666 * false if we want to use PIO to transmit 667 * true if we queued a DMA buffer 668 */ 669 static bool pl011_dma_tx_irq(struct uart_amba_port *uap) 670 { 671 if (!uap->using_tx_dma) 672 return false; 673 674 /* 675 * If we already have a TX buffer queued, but received a 676 * TX interrupt, it will be because we've just sent an X-char. 677 * Ensure the TX DMA is enabled and the TX IRQ is disabled. 678 */ 679 if (uap->dmatx.queued) { 680 uap->dmacr |= UART011_TXDMAE; 681 pl011_write(uap->dmacr, uap, REG_DMACR); 682 uap->im &= ~UART011_TXIM; 683 pl011_write(uap->im, uap, REG_IMSC); 684 return true; 685 } 686 687 /* 688 * We don't have a TX buffer queued, so try to queue one. 689 * If we successfully queued a buffer, mask the TX IRQ. 690 */ 691 if (pl011_dma_tx_refill(uap) > 0) { 692 uap->im &= ~UART011_TXIM; 693 pl011_write(uap->im, uap, REG_IMSC); 694 return true; 695 } 696 return false; 697 } 698 699 /* 700 * Stop the DMA transmit (eg, due to received XOFF). 701 * Locking: called with port lock held and IRQs disabled. 702 */ 703 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 704 { 705 if (uap->dmatx.queued) { 706 uap->dmacr &= ~UART011_TXDMAE; 707 pl011_write(uap->dmacr, uap, REG_DMACR); 708 } 709 } 710 711 /* 712 * Try to start a DMA transmit, or in the case of an XON/OFF 713 * character queued for send, try to get that character out ASAP. 714 * Locking: called with port lock held and IRQs disabled. 715 * Returns: 716 * false if we want the TX IRQ to be enabled 717 * true if we have a buffer queued 718 */ 719 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 720 { 721 u16 dmacr; 722 723 if (!uap->using_tx_dma) 724 return false; 725 726 if (!uap->port.x_char) { 727 /* no X-char, try to push chars out in DMA mode */ 728 bool ret = true; 729 730 if (!uap->dmatx.queued) { 731 if (pl011_dma_tx_refill(uap) > 0) { 732 uap->im &= ~UART011_TXIM; 733 pl011_write(uap->im, uap, REG_IMSC); 734 } else 735 ret = false; 736 } else if (!(uap->dmacr & UART011_TXDMAE)) { 737 uap->dmacr |= UART011_TXDMAE; 738 pl011_write(uap->dmacr, uap, REG_DMACR); 739 } 740 return ret; 741 } 742 743 /* 744 * We have an X-char to send. Disable DMA to prevent it loading 745 * the TX fifo, and then see if we can stuff it into the FIFO. 746 */ 747 dmacr = uap->dmacr; 748 uap->dmacr &= ~UART011_TXDMAE; 749 pl011_write(uap->dmacr, uap, REG_DMACR); 750 751 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { 752 /* 753 * No space in the FIFO, so enable the transmit interrupt 754 * so we know when there is space. Note that once we've 755 * loaded the character, we should just re-enable DMA. 756 */ 757 return false; 758 } 759 760 pl011_write(uap->port.x_char, uap, REG_DR); 761 uap->port.icount.tx++; 762 uap->port.x_char = 0; 763 764 /* Success - restore the DMA state */ 765 uap->dmacr = dmacr; 766 pl011_write(dmacr, uap, REG_DMACR); 767 768 return true; 769 } 770 771 /* 772 * Flush the transmit buffer. 773 * Locking: called with port lock held and IRQs disabled. 774 */ 775 static void pl011_dma_flush_buffer(struct uart_port *port) 776 __releases(&uap->port.lock) 777 __acquires(&uap->port.lock) 778 { 779 struct uart_amba_port *uap = 780 container_of(port, struct uart_amba_port, port); 781 782 if (!uap->using_tx_dma) 783 return; 784 785 dmaengine_terminate_async(uap->dmatx.chan); 786 787 if (uap->dmatx.queued) { 788 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 789 DMA_TO_DEVICE); 790 uap->dmatx.queued = false; 791 uap->dmacr &= ~UART011_TXDMAE; 792 pl011_write(uap->dmacr, uap, REG_DMACR); 793 } 794 } 795 796 static void pl011_dma_rx_callback(void *data); 797 798 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 799 { 800 struct dma_chan *rxchan = uap->dmarx.chan; 801 struct pl011_dmarx_data *dmarx = &uap->dmarx; 802 struct dma_async_tx_descriptor *desc; 803 struct pl011_sgbuf *sgbuf; 804 805 if (!rxchan) 806 return -EIO; 807 808 /* Start the RX DMA job */ 809 sgbuf = uap->dmarx.use_buf_b ? 810 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 811 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, 812 DMA_DEV_TO_MEM, 813 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 814 /* 815 * If the DMA engine is busy and cannot prepare a 816 * channel, no big deal, the driver will fall back 817 * to interrupt mode as a result of this error code. 818 */ 819 if (!desc) { 820 uap->dmarx.running = false; 821 dmaengine_terminate_all(rxchan); 822 return -EBUSY; 823 } 824 825 /* Some data to go along to the callback */ 826 desc->callback = pl011_dma_rx_callback; 827 desc->callback_param = uap; 828 dmarx->cookie = dmaengine_submit(desc); 829 dma_async_issue_pending(rxchan); 830 831 uap->dmacr |= UART011_RXDMAE; 832 pl011_write(uap->dmacr, uap, REG_DMACR); 833 uap->dmarx.running = true; 834 835 uap->im &= ~UART011_RXIM; 836 pl011_write(uap->im, uap, REG_IMSC); 837 838 return 0; 839 } 840 841 /* 842 * This is called when either the DMA job is complete, or 843 * the FIFO timeout interrupt occurred. This must be called 844 * with the port spinlock uap->port.lock held. 845 */ 846 static void pl011_dma_rx_chars(struct uart_amba_port *uap, 847 u32 pending, bool use_buf_b, 848 bool readfifo) 849 { 850 struct tty_port *port = &uap->port.state->port; 851 struct pl011_sgbuf *sgbuf = use_buf_b ? 852 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 853 int dma_count = 0; 854 u32 fifotaken = 0; /* only used for vdbg() */ 855 856 struct pl011_dmarx_data *dmarx = &uap->dmarx; 857 int dmataken = 0; 858 859 if (uap->dmarx.poll_rate) { 860 /* The data can be taken by polling */ 861 dmataken = sgbuf->sg.length - dmarx->last_residue; 862 /* Recalculate the pending size */ 863 if (pending >= dmataken) 864 pending -= dmataken; 865 } 866 867 /* Pick the remain data from the DMA */ 868 if (pending) { 869 870 /* 871 * First take all chars in the DMA pipe, then look in the FIFO. 872 * Note that tty_insert_flip_buf() tries to take as many chars 873 * as it can. 874 */ 875 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 876 pending); 877 878 uap->port.icount.rx += dma_count; 879 if (dma_count < pending) 880 dev_warn(uap->port.dev, 881 "couldn't insert all characters (TTY is full?)\n"); 882 } 883 884 /* Reset the last_residue for Rx DMA poll */ 885 if (uap->dmarx.poll_rate) 886 dmarx->last_residue = sgbuf->sg.length; 887 888 /* 889 * Only continue with trying to read the FIFO if all DMA chars have 890 * been taken first. 891 */ 892 if (dma_count == pending && readfifo) { 893 /* Clear any error flags */ 894 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 895 UART011_FEIS, uap, REG_ICR); 896 897 /* 898 * If we read all the DMA'd characters, and we had an 899 * incomplete buffer, that could be due to an rx error, or 900 * maybe we just timed out. Read any pending chars and check 901 * the error status. 902 * 903 * Error conditions will only occur in the FIFO, these will 904 * trigger an immediate interrupt and stop the DMA job, so we 905 * will always find the error in the FIFO, never in the DMA 906 * buffer. 907 */ 908 fifotaken = pl011_fifo_to_tty(uap); 909 } 910 911 dev_vdbg(uap->port.dev, 912 "Took %d chars from DMA buffer and %d chars from the FIFO\n", 913 dma_count, fifotaken); 914 tty_flip_buffer_push(port); 915 } 916 917 static void pl011_dma_rx_irq(struct uart_amba_port *uap) 918 { 919 struct pl011_dmarx_data *dmarx = &uap->dmarx; 920 struct dma_chan *rxchan = dmarx->chan; 921 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 922 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 923 size_t pending; 924 struct dma_tx_state state; 925 enum dma_status dmastat; 926 927 /* 928 * Pause the transfer so we can trust the current counter, 929 * do this before we pause the PL011 block, else we may 930 * overflow the FIFO. 931 */ 932 if (dmaengine_pause(rxchan)) 933 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 934 dmastat = rxchan->device->device_tx_status(rxchan, 935 dmarx->cookie, &state); 936 if (dmastat != DMA_PAUSED) 937 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 938 939 /* Disable RX DMA - incoming data will wait in the FIFO */ 940 uap->dmacr &= ~UART011_RXDMAE; 941 pl011_write(uap->dmacr, uap, REG_DMACR); 942 uap->dmarx.running = false; 943 944 pending = sgbuf->sg.length - state.residue; 945 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 946 /* Then we terminate the transfer - we now know our residue */ 947 dmaengine_terminate_all(rxchan); 948 949 /* 950 * This will take the chars we have so far and insert 951 * into the framework. 952 */ 953 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); 954 955 /* Switch buffer & re-trigger DMA job */ 956 dmarx->use_buf_b = !dmarx->use_buf_b; 957 if (pl011_dma_rx_trigger_dma(uap)) { 958 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 959 "fall back to interrupt mode\n"); 960 uap->im |= UART011_RXIM; 961 pl011_write(uap->im, uap, REG_IMSC); 962 } 963 } 964 965 static void pl011_dma_rx_callback(void *data) 966 { 967 struct uart_amba_port *uap = data; 968 struct pl011_dmarx_data *dmarx = &uap->dmarx; 969 struct dma_chan *rxchan = dmarx->chan; 970 bool lastbuf = dmarx->use_buf_b; 971 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 972 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 973 size_t pending; 974 struct dma_tx_state state; 975 int ret; 976 977 /* 978 * This completion interrupt occurs typically when the 979 * RX buffer is totally stuffed but no timeout has yet 980 * occurred. When that happens, we just want the RX 981 * routine to flush out the secondary DMA buffer while 982 * we immediately trigger the next DMA job. 983 */ 984 spin_lock_irq(&uap->port.lock); 985 /* 986 * Rx data can be taken by the UART interrupts during 987 * the DMA irq handler. So we check the residue here. 988 */ 989 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 990 pending = sgbuf->sg.length - state.residue; 991 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 992 /* Then we terminate the transfer - we now know our residue */ 993 dmaengine_terminate_all(rxchan); 994 995 uap->dmarx.running = false; 996 dmarx->use_buf_b = !lastbuf; 997 ret = pl011_dma_rx_trigger_dma(uap); 998 999 pl011_dma_rx_chars(uap, pending, lastbuf, false); 1000 spin_unlock_irq(&uap->port.lock); 1001 /* 1002 * Do this check after we picked the DMA chars so we don't 1003 * get some IRQ immediately from RX. 1004 */ 1005 if (ret) { 1006 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 1007 "fall back to interrupt mode\n"); 1008 uap->im |= UART011_RXIM; 1009 pl011_write(uap->im, uap, REG_IMSC); 1010 } 1011 } 1012 1013 /* 1014 * Stop accepting received characters, when we're shutting down or 1015 * suspending this port. 1016 * Locking: called with port lock held and IRQs disabled. 1017 */ 1018 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1019 { 1020 /* FIXME. Just disable the DMA enable */ 1021 uap->dmacr &= ~UART011_RXDMAE; 1022 pl011_write(uap->dmacr, uap, REG_DMACR); 1023 } 1024 1025 /* 1026 * Timer handler for Rx DMA polling. 1027 * Every polling, It checks the residue in the dma buffer and transfer 1028 * data to the tty. Also, last_residue is updated for the next polling. 1029 */ 1030 static void pl011_dma_rx_poll(struct timer_list *t) 1031 { 1032 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer); 1033 struct tty_port *port = &uap->port.state->port; 1034 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1035 struct dma_chan *rxchan = uap->dmarx.chan; 1036 unsigned long flags; 1037 unsigned int dmataken = 0; 1038 unsigned int size = 0; 1039 struct pl011_sgbuf *sgbuf; 1040 int dma_count; 1041 struct dma_tx_state state; 1042 1043 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 1044 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1045 if (likely(state.residue < dmarx->last_residue)) { 1046 dmataken = sgbuf->sg.length - dmarx->last_residue; 1047 size = dmarx->last_residue - state.residue; 1048 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 1049 size); 1050 if (dma_count == size) 1051 dmarx->last_residue = state.residue; 1052 dmarx->last_jiffies = jiffies; 1053 } 1054 tty_flip_buffer_push(port); 1055 1056 /* 1057 * If no data is received in poll_timeout, the driver will fall back 1058 * to interrupt mode. We will retrigger DMA at the first interrupt. 1059 */ 1060 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) 1061 > uap->dmarx.poll_timeout) { 1062 1063 spin_lock_irqsave(&uap->port.lock, flags); 1064 pl011_dma_rx_stop(uap); 1065 uap->im |= UART011_RXIM; 1066 pl011_write(uap->im, uap, REG_IMSC); 1067 spin_unlock_irqrestore(&uap->port.lock, flags); 1068 1069 uap->dmarx.running = false; 1070 dmaengine_terminate_all(rxchan); 1071 del_timer(&uap->dmarx.timer); 1072 } else { 1073 mod_timer(&uap->dmarx.timer, 1074 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); 1075 } 1076 } 1077 1078 static void pl011_dma_startup(struct uart_amba_port *uap) 1079 { 1080 int ret; 1081 1082 if (!uap->dma_probed) 1083 pl011_dma_probe(uap); 1084 1085 if (!uap->dmatx.chan) 1086 return; 1087 1088 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); 1089 if (!uap->dmatx.buf) { 1090 dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); 1091 uap->port.fifosize = uap->fifosize; 1092 return; 1093 } 1094 1095 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); 1096 1097 /* The DMA buffer is now the FIFO the TTY subsystem can use */ 1098 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; 1099 uap->using_tx_dma = true; 1100 1101 if (!uap->dmarx.chan) 1102 goto skip_rx; 1103 1104 /* Allocate and map DMA RX buffers */ 1105 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1106 DMA_FROM_DEVICE); 1107 if (ret) { 1108 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1109 "RX buffer A", ret); 1110 goto skip_rx; 1111 } 1112 1113 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, 1114 DMA_FROM_DEVICE); 1115 if (ret) { 1116 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1117 "RX buffer B", ret); 1118 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1119 DMA_FROM_DEVICE); 1120 goto skip_rx; 1121 } 1122 1123 uap->using_rx_dma = true; 1124 1125 skip_rx: 1126 /* Turn on DMA error (RX/TX will be enabled on demand) */ 1127 uap->dmacr |= UART011_DMAONERR; 1128 pl011_write(uap->dmacr, uap, REG_DMACR); 1129 1130 /* 1131 * ST Micro variants has some specific dma burst threshold 1132 * compensation. Set this to 16 bytes, so burst will only 1133 * be issued above/below 16 bytes. 1134 */ 1135 if (uap->vendor->dma_threshold) 1136 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, 1137 uap, REG_ST_DMAWM); 1138 1139 if (uap->using_rx_dma) { 1140 if (pl011_dma_rx_trigger_dma(uap)) 1141 dev_dbg(uap->port.dev, "could not trigger initial " 1142 "RX DMA job, fall back to interrupt mode\n"); 1143 if (uap->dmarx.poll_rate) { 1144 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0); 1145 mod_timer(&uap->dmarx.timer, 1146 jiffies + 1147 msecs_to_jiffies(uap->dmarx.poll_rate)); 1148 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1149 uap->dmarx.last_jiffies = jiffies; 1150 } 1151 } 1152 } 1153 1154 static void pl011_dma_shutdown(struct uart_amba_port *uap) 1155 { 1156 if (!(uap->using_tx_dma || uap->using_rx_dma)) 1157 return; 1158 1159 /* Disable RX and TX DMA */ 1160 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) 1161 cpu_relax(); 1162 1163 spin_lock_irq(&uap->port.lock); 1164 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); 1165 pl011_write(uap->dmacr, uap, REG_DMACR); 1166 spin_unlock_irq(&uap->port.lock); 1167 1168 if (uap->using_tx_dma) { 1169 /* In theory, this should already be done by pl011_dma_flush_buffer */ 1170 dmaengine_terminate_all(uap->dmatx.chan); 1171 if (uap->dmatx.queued) { 1172 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 1173 DMA_TO_DEVICE); 1174 uap->dmatx.queued = false; 1175 } 1176 1177 kfree(uap->dmatx.buf); 1178 uap->using_tx_dma = false; 1179 } 1180 1181 if (uap->using_rx_dma) { 1182 dmaengine_terminate_all(uap->dmarx.chan); 1183 /* Clean up the RX DMA */ 1184 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); 1185 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); 1186 if (uap->dmarx.poll_rate) 1187 del_timer_sync(&uap->dmarx.timer); 1188 uap->using_rx_dma = false; 1189 } 1190 } 1191 1192 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1193 { 1194 return uap->using_rx_dma; 1195 } 1196 1197 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1198 { 1199 return uap->using_rx_dma && uap->dmarx.running; 1200 } 1201 1202 #else 1203 /* Blank functions if the DMA engine is not available */ 1204 static inline void pl011_dma_remove(struct uart_amba_port *uap) 1205 { 1206 } 1207 1208 static inline void pl011_dma_startup(struct uart_amba_port *uap) 1209 { 1210 } 1211 1212 static inline void pl011_dma_shutdown(struct uart_amba_port *uap) 1213 { 1214 } 1215 1216 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) 1217 { 1218 return false; 1219 } 1220 1221 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 1222 { 1223 } 1224 1225 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 1226 { 1227 return false; 1228 } 1229 1230 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) 1231 { 1232 } 1233 1234 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1235 { 1236 } 1237 1238 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 1239 { 1240 return -EIO; 1241 } 1242 1243 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1244 { 1245 return false; 1246 } 1247 1248 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1249 { 1250 return false; 1251 } 1252 1253 #define pl011_dma_flush_buffer NULL 1254 #endif 1255 1256 static void pl011_rs485_tx_stop(struct uart_amba_port *uap) 1257 { 1258 struct uart_port *port = &uap->port; 1259 int i = 0; 1260 u32 cr; 1261 1262 /* Wait until hardware tx queue is empty */ 1263 while (!pl011_tx_empty(port)) { 1264 if (i == port->fifosize) { 1265 dev_warn(port->dev, 1266 "timeout while draining hardware tx queue\n"); 1267 break; 1268 } 1269 1270 udelay(uap->rs485_tx_drain_interval); 1271 i++; 1272 } 1273 1274 if (port->rs485.delay_rts_after_send) 1275 mdelay(port->rs485.delay_rts_after_send); 1276 1277 cr = pl011_read(uap, REG_CR); 1278 1279 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 1280 cr &= ~UART011_CR_RTS; 1281 else 1282 cr |= UART011_CR_RTS; 1283 1284 /* Disable the transmitter and reenable the transceiver */ 1285 cr &= ~UART011_CR_TXE; 1286 cr |= UART011_CR_RXE; 1287 pl011_write(cr, uap, REG_CR); 1288 1289 uap->rs485_tx_started = false; 1290 } 1291 1292 static void pl011_stop_tx(struct uart_port *port) 1293 { 1294 struct uart_amba_port *uap = 1295 container_of(port, struct uart_amba_port, port); 1296 1297 uap->im &= ~UART011_TXIM; 1298 pl011_write(uap->im, uap, REG_IMSC); 1299 pl011_dma_tx_stop(uap); 1300 1301 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) 1302 pl011_rs485_tx_stop(uap); 1303 } 1304 1305 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); 1306 1307 /* Start TX with programmed I/O only (no DMA) */ 1308 static void pl011_start_tx_pio(struct uart_amba_port *uap) 1309 { 1310 if (pl011_tx_chars(uap, false)) { 1311 uap->im |= UART011_TXIM; 1312 pl011_write(uap->im, uap, REG_IMSC); 1313 } 1314 } 1315 1316 static void pl011_start_tx(struct uart_port *port) 1317 { 1318 struct uart_amba_port *uap = 1319 container_of(port, struct uart_amba_port, port); 1320 1321 if (!pl011_dma_tx_start(uap)) 1322 pl011_start_tx_pio(uap); 1323 } 1324 1325 static void pl011_stop_rx(struct uart_port *port) 1326 { 1327 struct uart_amba_port *uap = 1328 container_of(port, struct uart_amba_port, port); 1329 1330 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| 1331 UART011_PEIM|UART011_BEIM|UART011_OEIM); 1332 pl011_write(uap->im, uap, REG_IMSC); 1333 1334 pl011_dma_rx_stop(uap); 1335 } 1336 1337 static void pl011_enable_ms(struct uart_port *port) 1338 { 1339 struct uart_amba_port *uap = 1340 container_of(port, struct uart_amba_port, port); 1341 1342 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; 1343 pl011_write(uap->im, uap, REG_IMSC); 1344 } 1345 1346 static void pl011_rx_chars(struct uart_amba_port *uap) 1347 __releases(&uap->port.lock) 1348 __acquires(&uap->port.lock) 1349 { 1350 pl011_fifo_to_tty(uap); 1351 1352 spin_unlock(&uap->port.lock); 1353 tty_flip_buffer_push(&uap->port.state->port); 1354 /* 1355 * If we were temporarily out of DMA mode for a while, 1356 * attempt to switch back to DMA mode again. 1357 */ 1358 if (pl011_dma_rx_available(uap)) { 1359 if (pl011_dma_rx_trigger_dma(uap)) { 1360 dev_dbg(uap->port.dev, "could not trigger RX DMA job " 1361 "fall back to interrupt mode again\n"); 1362 uap->im |= UART011_RXIM; 1363 pl011_write(uap->im, uap, REG_IMSC); 1364 } else { 1365 #ifdef CONFIG_DMA_ENGINE 1366 /* Start Rx DMA poll */ 1367 if (uap->dmarx.poll_rate) { 1368 uap->dmarx.last_jiffies = jiffies; 1369 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1370 mod_timer(&uap->dmarx.timer, 1371 jiffies + 1372 msecs_to_jiffies(uap->dmarx.poll_rate)); 1373 } 1374 #endif 1375 } 1376 } 1377 spin_lock(&uap->port.lock); 1378 } 1379 1380 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, 1381 bool from_irq) 1382 { 1383 if (unlikely(!from_irq) && 1384 pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1385 return false; /* unable to transmit character */ 1386 1387 pl011_write(c, uap, REG_DR); 1388 uap->port.icount.tx++; 1389 1390 return true; 1391 } 1392 1393 static void pl011_rs485_tx_start(struct uart_amba_port *uap) 1394 { 1395 struct uart_port *port = &uap->port; 1396 u32 cr; 1397 1398 /* Enable transmitter */ 1399 cr = pl011_read(uap, REG_CR); 1400 cr |= UART011_CR_TXE; 1401 1402 /* Disable receiver if half-duplex */ 1403 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1404 cr &= ~UART011_CR_RXE; 1405 1406 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 1407 cr &= ~UART011_CR_RTS; 1408 else 1409 cr |= UART011_CR_RTS; 1410 1411 pl011_write(cr, uap, REG_CR); 1412 1413 if (port->rs485.delay_rts_before_send) 1414 mdelay(port->rs485.delay_rts_before_send); 1415 1416 uap->rs485_tx_started = true; 1417 } 1418 1419 /* Returns true if tx interrupts have to be (kept) enabled */ 1420 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) 1421 { 1422 struct circ_buf *xmit = &uap->port.state->xmit; 1423 int count = uap->fifosize >> 1; 1424 1425 if (uap->port.x_char) { 1426 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) 1427 return true; 1428 uap->port.x_char = 0; 1429 --count; 1430 } 1431 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { 1432 pl011_stop_tx(&uap->port); 1433 return false; 1434 } 1435 1436 if ((uap->port.rs485.flags & SER_RS485_ENABLED) && 1437 !uap->rs485_tx_started) 1438 pl011_rs485_tx_start(uap); 1439 1440 /* If we are using DMA mode, try to send some characters. */ 1441 if (pl011_dma_tx_irq(uap)) 1442 return true; 1443 1444 do { 1445 if (likely(from_irq) && count-- == 0) 1446 break; 1447 1448 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) 1449 break; 1450 1451 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1452 } while (!uart_circ_empty(xmit)); 1453 1454 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1455 uart_write_wakeup(&uap->port); 1456 1457 if (uart_circ_empty(xmit)) { 1458 pl011_stop_tx(&uap->port); 1459 return false; 1460 } 1461 return true; 1462 } 1463 1464 static void pl011_modem_status(struct uart_amba_port *uap) 1465 { 1466 unsigned int status, delta; 1467 1468 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1469 1470 delta = status ^ uap->old_status; 1471 uap->old_status = status; 1472 1473 if (!delta) 1474 return; 1475 1476 if (delta & UART01x_FR_DCD) 1477 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 1478 1479 if (delta & uap->vendor->fr_dsr) 1480 uap->port.icount.dsr++; 1481 1482 if (delta & uap->vendor->fr_cts) 1483 uart_handle_cts_change(&uap->port, 1484 status & uap->vendor->fr_cts); 1485 1486 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 1487 } 1488 1489 static void check_apply_cts_event_workaround(struct uart_amba_port *uap) 1490 { 1491 if (!uap->vendor->cts_event_workaround) 1492 return; 1493 1494 /* workaround to make sure that all bits are unlocked.. */ 1495 pl011_write(0x00, uap, REG_ICR); 1496 1497 /* 1498 * WA: introduce 26ns(1 uart clk) delay before W1C; 1499 * single apb access will incur 2 pclk(133.12Mhz) delay, 1500 * so add 2 dummy reads 1501 */ 1502 pl011_read(uap, REG_ICR); 1503 pl011_read(uap, REG_ICR); 1504 } 1505 1506 static irqreturn_t pl011_int(int irq, void *dev_id) 1507 { 1508 struct uart_amba_port *uap = dev_id; 1509 unsigned long flags; 1510 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 1511 int handled = 0; 1512 1513 spin_lock_irqsave(&uap->port.lock, flags); 1514 status = pl011_read(uap, REG_RIS) & uap->im; 1515 if (status) { 1516 do { 1517 check_apply_cts_event_workaround(uap); 1518 1519 pl011_write(status & ~(UART011_TXIS|UART011_RTIS| 1520 UART011_RXIS), 1521 uap, REG_ICR); 1522 1523 if (status & (UART011_RTIS|UART011_RXIS)) { 1524 if (pl011_dma_rx_running(uap)) 1525 pl011_dma_rx_irq(uap); 1526 else 1527 pl011_rx_chars(uap); 1528 } 1529 if (status & (UART011_DSRMIS|UART011_DCDMIS| 1530 UART011_CTSMIS|UART011_RIMIS)) 1531 pl011_modem_status(uap); 1532 if (status & UART011_TXIS) 1533 pl011_tx_chars(uap, true); 1534 1535 if (pass_counter-- == 0) 1536 break; 1537 1538 status = pl011_read(uap, REG_RIS) & uap->im; 1539 } while (status != 0); 1540 handled = 1; 1541 } 1542 1543 spin_unlock_irqrestore(&uap->port.lock, flags); 1544 1545 return IRQ_RETVAL(handled); 1546 } 1547 1548 static unsigned int pl011_tx_empty(struct uart_port *port) 1549 { 1550 struct uart_amba_port *uap = 1551 container_of(port, struct uart_amba_port, port); 1552 1553 /* Allow feature register bits to be inverted to work around errata */ 1554 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; 1555 1556 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? 1557 0 : TIOCSER_TEMT; 1558 } 1559 1560 static unsigned int pl011_get_mctrl(struct uart_port *port) 1561 { 1562 struct uart_amba_port *uap = 1563 container_of(port, struct uart_amba_port, port); 1564 unsigned int result = 0; 1565 unsigned int status = pl011_read(uap, REG_FR); 1566 1567 #define TIOCMBIT(uartbit, tiocmbit) \ 1568 if (status & uartbit) \ 1569 result |= tiocmbit 1570 1571 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); 1572 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR); 1573 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS); 1574 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG); 1575 #undef TIOCMBIT 1576 return result; 1577 } 1578 1579 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) 1580 { 1581 struct uart_amba_port *uap = 1582 container_of(port, struct uart_amba_port, port); 1583 unsigned int cr; 1584 1585 cr = pl011_read(uap, REG_CR); 1586 1587 #define TIOCMBIT(tiocmbit, uartbit) \ 1588 if (mctrl & tiocmbit) \ 1589 cr |= uartbit; \ 1590 else \ 1591 cr &= ~uartbit 1592 1593 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); 1594 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); 1595 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); 1596 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); 1597 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); 1598 1599 if (port->status & UPSTAT_AUTORTS) { 1600 /* We need to disable auto-RTS if we want to turn RTS off */ 1601 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); 1602 } 1603 #undef TIOCMBIT 1604 1605 pl011_write(cr, uap, REG_CR); 1606 } 1607 1608 static void pl011_break_ctl(struct uart_port *port, int break_state) 1609 { 1610 struct uart_amba_port *uap = 1611 container_of(port, struct uart_amba_port, port); 1612 unsigned long flags; 1613 unsigned int lcr_h; 1614 1615 spin_lock_irqsave(&uap->port.lock, flags); 1616 lcr_h = pl011_read(uap, REG_LCRH_TX); 1617 if (break_state == -1) 1618 lcr_h |= UART01x_LCRH_BRK; 1619 else 1620 lcr_h &= ~UART01x_LCRH_BRK; 1621 pl011_write(lcr_h, uap, REG_LCRH_TX); 1622 spin_unlock_irqrestore(&uap->port.lock, flags); 1623 } 1624 1625 #ifdef CONFIG_CONSOLE_POLL 1626 1627 static void pl011_quiesce_irqs(struct uart_port *port) 1628 { 1629 struct uart_amba_port *uap = 1630 container_of(port, struct uart_amba_port, port); 1631 1632 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); 1633 /* 1634 * There is no way to clear TXIM as this is "ready to transmit IRQ", so 1635 * we simply mask it. start_tx() will unmask it. 1636 * 1637 * Note we can race with start_tx(), and if the race happens, the 1638 * polling user might get another interrupt just after we clear it. 1639 * But it should be OK and can happen even w/o the race, e.g. 1640 * controller immediately got some new data and raised the IRQ. 1641 * 1642 * And whoever uses polling routines assumes that it manages the device 1643 * (including tx queue), so we're also fine with start_tx()'s caller 1644 * side. 1645 */ 1646 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, 1647 REG_IMSC); 1648 } 1649 1650 static int pl011_get_poll_char(struct uart_port *port) 1651 { 1652 struct uart_amba_port *uap = 1653 container_of(port, struct uart_amba_port, port); 1654 unsigned int status; 1655 1656 /* 1657 * The caller might need IRQs lowered, e.g. if used with KDB NMI 1658 * debugger. 1659 */ 1660 pl011_quiesce_irqs(port); 1661 1662 status = pl011_read(uap, REG_FR); 1663 if (status & UART01x_FR_RXFE) 1664 return NO_POLL_CHAR; 1665 1666 return pl011_read(uap, REG_DR); 1667 } 1668 1669 static void pl011_put_poll_char(struct uart_port *port, 1670 unsigned char ch) 1671 { 1672 struct uart_amba_port *uap = 1673 container_of(port, struct uart_amba_port, port); 1674 1675 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1676 cpu_relax(); 1677 1678 pl011_write(ch, uap, REG_DR); 1679 } 1680 1681 #endif /* CONFIG_CONSOLE_POLL */ 1682 1683 static int pl011_hwinit(struct uart_port *port) 1684 { 1685 struct uart_amba_port *uap = 1686 container_of(port, struct uart_amba_port, port); 1687 int retval; 1688 1689 /* Optionaly enable pins to be muxed in and configured */ 1690 pinctrl_pm_select_default_state(port->dev); 1691 1692 /* 1693 * Try to enable the clock producer. 1694 */ 1695 retval = clk_prepare_enable(uap->clk); 1696 if (retval) 1697 return retval; 1698 1699 uap->port.uartclk = clk_get_rate(uap->clk); 1700 1701 /* Clear pending error and receive interrupts */ 1702 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 1703 UART011_FEIS | UART011_RTIS | UART011_RXIS, 1704 uap, REG_ICR); 1705 1706 /* 1707 * Save interrupts enable mask, and enable RX interrupts in case if 1708 * the interrupt is used for NMI entry. 1709 */ 1710 uap->im = pl011_read(uap, REG_IMSC); 1711 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); 1712 1713 if (dev_get_platdata(uap->port.dev)) { 1714 struct amba_pl011_data *plat; 1715 1716 plat = dev_get_platdata(uap->port.dev); 1717 if (plat->init) 1718 plat->init(); 1719 } 1720 return 0; 1721 } 1722 1723 static bool pl011_split_lcrh(const struct uart_amba_port *uap) 1724 { 1725 return pl011_reg_to_offset(uap, REG_LCRH_RX) != 1726 pl011_reg_to_offset(uap, REG_LCRH_TX); 1727 } 1728 1729 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) 1730 { 1731 pl011_write(lcr_h, uap, REG_LCRH_RX); 1732 if (pl011_split_lcrh(uap)) { 1733 int i; 1734 /* 1735 * Wait 10 PCLKs before writing LCRH_TX register, 1736 * to get this delay write read only register 10 times 1737 */ 1738 for (i = 0; i < 10; ++i) 1739 pl011_write(0xff, uap, REG_MIS); 1740 pl011_write(lcr_h, uap, REG_LCRH_TX); 1741 } 1742 } 1743 1744 static int pl011_allocate_irq(struct uart_amba_port *uap) 1745 { 1746 pl011_write(uap->im, uap, REG_IMSC); 1747 1748 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); 1749 } 1750 1751 /* 1752 * Enable interrupts, only timeouts when using DMA 1753 * if initial RX DMA job failed, start in interrupt mode 1754 * as well. 1755 */ 1756 static void pl011_enable_interrupts(struct uart_amba_port *uap) 1757 { 1758 unsigned int i; 1759 1760 spin_lock_irq(&uap->port.lock); 1761 1762 /* Clear out any spuriously appearing RX interrupts */ 1763 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); 1764 1765 /* 1766 * RXIS is asserted only when the RX FIFO transitions from below 1767 * to above the trigger threshold. If the RX FIFO is already 1768 * full to the threshold this can't happen and RXIS will now be 1769 * stuck off. Drain the RX FIFO explicitly to fix this: 1770 */ 1771 for (i = 0; i < uap->fifosize * 2; ++i) { 1772 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE) 1773 break; 1774 1775 pl011_read(uap, REG_DR); 1776 } 1777 1778 uap->im = UART011_RTIM; 1779 if (!pl011_dma_rx_running(uap)) 1780 uap->im |= UART011_RXIM; 1781 pl011_write(uap->im, uap, REG_IMSC); 1782 spin_unlock_irq(&uap->port.lock); 1783 } 1784 1785 static int pl011_startup(struct uart_port *port) 1786 { 1787 struct uart_amba_port *uap = 1788 container_of(port, struct uart_amba_port, port); 1789 unsigned int cr; 1790 int retval; 1791 1792 retval = pl011_hwinit(port); 1793 if (retval) 1794 goto clk_dis; 1795 1796 retval = pl011_allocate_irq(uap); 1797 if (retval) 1798 goto clk_dis; 1799 1800 pl011_write(uap->vendor->ifls, uap, REG_IFLS); 1801 1802 spin_lock_irq(&uap->port.lock); 1803 1804 cr = pl011_read(uap, REG_CR); 1805 cr &= UART011_CR_RTS | UART011_CR_DTR; 1806 cr |= UART01x_CR_UARTEN | UART011_CR_RXE; 1807 1808 if (!(port->rs485.flags & SER_RS485_ENABLED)) 1809 cr |= UART011_CR_TXE; 1810 1811 pl011_write(cr, uap, REG_CR); 1812 1813 spin_unlock_irq(&uap->port.lock); 1814 1815 /* 1816 * initialise the old status of the modem signals 1817 */ 1818 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1819 1820 /* Startup DMA */ 1821 pl011_dma_startup(uap); 1822 1823 pl011_enable_interrupts(uap); 1824 1825 return 0; 1826 1827 clk_dis: 1828 clk_disable_unprepare(uap->clk); 1829 return retval; 1830 } 1831 1832 static int sbsa_uart_startup(struct uart_port *port) 1833 { 1834 struct uart_amba_port *uap = 1835 container_of(port, struct uart_amba_port, port); 1836 int retval; 1837 1838 retval = pl011_hwinit(port); 1839 if (retval) 1840 return retval; 1841 1842 retval = pl011_allocate_irq(uap); 1843 if (retval) 1844 return retval; 1845 1846 /* The SBSA UART does not support any modem status lines. */ 1847 uap->old_status = 0; 1848 1849 pl011_enable_interrupts(uap); 1850 1851 return 0; 1852 } 1853 1854 static void pl011_shutdown_channel(struct uart_amba_port *uap, 1855 unsigned int lcrh) 1856 { 1857 unsigned long val; 1858 1859 val = pl011_read(uap, lcrh); 1860 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); 1861 pl011_write(val, uap, lcrh); 1862 } 1863 1864 /* 1865 * disable the port. It should not disable RTS and DTR. 1866 * Also RTS and DTR state should be preserved to restore 1867 * it during startup(). 1868 */ 1869 static void pl011_disable_uart(struct uart_amba_port *uap) 1870 { 1871 unsigned int cr; 1872 1873 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1874 spin_lock_irq(&uap->port.lock); 1875 cr = pl011_read(uap, REG_CR); 1876 cr &= UART011_CR_RTS | UART011_CR_DTR; 1877 cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 1878 pl011_write(cr, uap, REG_CR); 1879 spin_unlock_irq(&uap->port.lock); 1880 1881 /* 1882 * disable break condition and fifos 1883 */ 1884 pl011_shutdown_channel(uap, REG_LCRH_RX); 1885 if (pl011_split_lcrh(uap)) 1886 pl011_shutdown_channel(uap, REG_LCRH_TX); 1887 } 1888 1889 static void pl011_disable_interrupts(struct uart_amba_port *uap) 1890 { 1891 spin_lock_irq(&uap->port.lock); 1892 1893 /* mask all interrupts and clear all pending ones */ 1894 uap->im = 0; 1895 pl011_write(uap->im, uap, REG_IMSC); 1896 pl011_write(0xffff, uap, REG_ICR); 1897 1898 spin_unlock_irq(&uap->port.lock); 1899 } 1900 1901 static void pl011_shutdown(struct uart_port *port) 1902 { 1903 struct uart_amba_port *uap = 1904 container_of(port, struct uart_amba_port, port); 1905 1906 pl011_disable_interrupts(uap); 1907 1908 pl011_dma_shutdown(uap); 1909 1910 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) 1911 pl011_rs485_tx_stop(uap); 1912 1913 free_irq(uap->port.irq, uap); 1914 1915 pl011_disable_uart(uap); 1916 1917 /* 1918 * Shut down the clock producer 1919 */ 1920 clk_disable_unprepare(uap->clk); 1921 /* Optionally let pins go into sleep states */ 1922 pinctrl_pm_select_sleep_state(port->dev); 1923 1924 if (dev_get_platdata(uap->port.dev)) { 1925 struct amba_pl011_data *plat; 1926 1927 plat = dev_get_platdata(uap->port.dev); 1928 if (plat->exit) 1929 plat->exit(); 1930 } 1931 1932 if (uap->port.ops->flush_buffer) 1933 uap->port.ops->flush_buffer(port); 1934 } 1935 1936 static void sbsa_uart_shutdown(struct uart_port *port) 1937 { 1938 struct uart_amba_port *uap = 1939 container_of(port, struct uart_amba_port, port); 1940 1941 pl011_disable_interrupts(uap); 1942 1943 free_irq(uap->port.irq, uap); 1944 1945 if (uap->port.ops->flush_buffer) 1946 uap->port.ops->flush_buffer(port); 1947 } 1948 1949 static void 1950 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) 1951 { 1952 port->read_status_mask = UART011_DR_OE | 255; 1953 if (termios->c_iflag & INPCK) 1954 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; 1955 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1956 port->read_status_mask |= UART011_DR_BE; 1957 1958 /* 1959 * Characters to ignore 1960 */ 1961 port->ignore_status_mask = 0; 1962 if (termios->c_iflag & IGNPAR) 1963 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; 1964 if (termios->c_iflag & IGNBRK) { 1965 port->ignore_status_mask |= UART011_DR_BE; 1966 /* 1967 * If we're ignoring parity and break indicators, 1968 * ignore overruns too (for real raw support). 1969 */ 1970 if (termios->c_iflag & IGNPAR) 1971 port->ignore_status_mask |= UART011_DR_OE; 1972 } 1973 1974 /* 1975 * Ignore all characters if CREAD is not set. 1976 */ 1977 if ((termios->c_cflag & CREAD) == 0) 1978 port->ignore_status_mask |= UART_DUMMY_DR_RX; 1979 } 1980 1981 static void 1982 pl011_set_termios(struct uart_port *port, struct ktermios *termios, 1983 struct ktermios *old) 1984 { 1985 struct uart_amba_port *uap = 1986 container_of(port, struct uart_amba_port, port); 1987 unsigned int lcr_h, old_cr; 1988 unsigned long flags; 1989 unsigned int baud, quot, clkdiv; 1990 unsigned int bits; 1991 1992 if (uap->vendor->oversampling) 1993 clkdiv = 8; 1994 else 1995 clkdiv = 16; 1996 1997 /* 1998 * Ask the core to calculate the divisor for us. 1999 */ 2000 baud = uart_get_baud_rate(port, termios, old, 0, 2001 port->uartclk / clkdiv); 2002 #ifdef CONFIG_DMA_ENGINE 2003 /* 2004 * Adjust RX DMA polling rate with baud rate if not specified. 2005 */ 2006 if (uap->dmarx.auto_poll_rate) 2007 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); 2008 #endif 2009 2010 if (baud > port->uartclk/16) 2011 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); 2012 else 2013 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); 2014 2015 switch (termios->c_cflag & CSIZE) { 2016 case CS5: 2017 lcr_h = UART01x_LCRH_WLEN_5; 2018 break; 2019 case CS6: 2020 lcr_h = UART01x_LCRH_WLEN_6; 2021 break; 2022 case CS7: 2023 lcr_h = UART01x_LCRH_WLEN_7; 2024 break; 2025 default: // CS8 2026 lcr_h = UART01x_LCRH_WLEN_8; 2027 break; 2028 } 2029 if (termios->c_cflag & CSTOPB) 2030 lcr_h |= UART01x_LCRH_STP2; 2031 if (termios->c_cflag & PARENB) { 2032 lcr_h |= UART01x_LCRH_PEN; 2033 if (!(termios->c_cflag & PARODD)) 2034 lcr_h |= UART01x_LCRH_EPS; 2035 if (termios->c_cflag & CMSPAR) 2036 lcr_h |= UART011_LCRH_SPS; 2037 } 2038 if (uap->fifosize > 1) 2039 lcr_h |= UART01x_LCRH_FEN; 2040 2041 bits = tty_get_frame_size(termios->c_cflag); 2042 2043 spin_lock_irqsave(&port->lock, flags); 2044 2045 /* 2046 * Update the per-port timeout. 2047 */ 2048 uart_update_timeout(port, termios->c_cflag, baud); 2049 2050 /* 2051 * Calculate the approximated time it takes to transmit one character 2052 * with the given baud rate. We use this as the poll interval when we 2053 * wait for the tx queue to empty. 2054 */ 2055 uap->rs485_tx_drain_interval = (bits * 1000 * 1000) / baud; 2056 2057 pl011_setup_status_masks(port, termios); 2058 2059 if (UART_ENABLE_MS(port, termios->c_cflag)) 2060 pl011_enable_ms(port); 2061 2062 if (port->rs485.flags & SER_RS485_ENABLED) 2063 termios->c_cflag &= ~CRTSCTS; 2064 2065 old_cr = pl011_read(uap, REG_CR); 2066 2067 if (termios->c_cflag & CRTSCTS) { 2068 if (old_cr & UART011_CR_RTS) 2069 old_cr |= UART011_CR_RTSEN; 2070 2071 old_cr |= UART011_CR_CTSEN; 2072 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 2073 } else { 2074 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); 2075 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 2076 } 2077 2078 if (uap->vendor->oversampling) { 2079 if (baud > port->uartclk / 16) 2080 old_cr |= ST_UART011_CR_OVSFACT; 2081 else 2082 old_cr &= ~ST_UART011_CR_OVSFACT; 2083 } 2084 2085 /* 2086 * Workaround for the ST Micro oversampling variants to 2087 * increase the bitrate slightly, by lowering the divisor, 2088 * to avoid delayed sampling of start bit at high speeds, 2089 * else we see data corruption. 2090 */ 2091 if (uap->vendor->oversampling) { 2092 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) 2093 quot -= 1; 2094 else if ((baud > 3250000) && (quot > 2)) 2095 quot -= 2; 2096 } 2097 /* Set baud rate */ 2098 pl011_write(quot & 0x3f, uap, REG_FBRD); 2099 pl011_write(quot >> 6, uap, REG_IBRD); 2100 2101 /* 2102 * ----------v----------v----------v----------v----- 2103 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER 2104 * REG_FBRD & REG_IBRD. 2105 * ----------^----------^----------^----------^----- 2106 */ 2107 pl011_write_lcr_h(uap, lcr_h); 2108 pl011_write(old_cr, uap, REG_CR); 2109 2110 spin_unlock_irqrestore(&port->lock, flags); 2111 } 2112 2113 static void 2114 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, 2115 struct ktermios *old) 2116 { 2117 struct uart_amba_port *uap = 2118 container_of(port, struct uart_amba_port, port); 2119 unsigned long flags; 2120 2121 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); 2122 2123 /* The SBSA UART only supports 8n1 without hardware flow control. */ 2124 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 2125 termios->c_cflag &= ~(CMSPAR | CRTSCTS); 2126 termios->c_cflag |= CS8 | CLOCAL; 2127 2128 spin_lock_irqsave(&port->lock, flags); 2129 uart_update_timeout(port, CS8, uap->fixed_baud); 2130 pl011_setup_status_masks(port, termios); 2131 spin_unlock_irqrestore(&port->lock, flags); 2132 } 2133 2134 static const char *pl011_type(struct uart_port *port) 2135 { 2136 struct uart_amba_port *uap = 2137 container_of(port, struct uart_amba_port, port); 2138 return uap->port.type == PORT_AMBA ? uap->type : NULL; 2139 } 2140 2141 /* 2142 * Configure/autoconfigure the port. 2143 */ 2144 static void pl011_config_port(struct uart_port *port, int flags) 2145 { 2146 if (flags & UART_CONFIG_TYPE) 2147 port->type = PORT_AMBA; 2148 } 2149 2150 /* 2151 * verify the new serial_struct (for TIOCSSERIAL). 2152 */ 2153 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) 2154 { 2155 int ret = 0; 2156 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 2157 ret = -EINVAL; 2158 if (ser->irq < 0 || ser->irq >= nr_irqs) 2159 ret = -EINVAL; 2160 if (ser->baud_base < 9600) 2161 ret = -EINVAL; 2162 if (port->mapbase != (unsigned long) ser->iomem_base) 2163 ret = -EINVAL; 2164 return ret; 2165 } 2166 2167 static int pl011_rs485_config(struct uart_port *port, 2168 struct serial_rs485 *rs485) 2169 { 2170 struct uart_amba_port *uap = 2171 container_of(port, struct uart_amba_port, port); 2172 2173 /* pick sane settings if the user hasn't */ 2174 if (!(rs485->flags & SER_RS485_RTS_ON_SEND) == 2175 !(rs485->flags & SER_RS485_RTS_AFTER_SEND)) { 2176 rs485->flags |= SER_RS485_RTS_ON_SEND; 2177 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 2178 } 2179 /* clamp the delays to [0, 100ms] */ 2180 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U); 2181 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U); 2182 memset(rs485->padding, 0, sizeof(rs485->padding)); 2183 2184 if (port->rs485.flags & SER_RS485_ENABLED) 2185 pl011_rs485_tx_stop(uap); 2186 2187 /* Set new configuration */ 2188 port->rs485 = *rs485; 2189 2190 /* Make sure auto RTS is disabled */ 2191 if (port->rs485.flags & SER_RS485_ENABLED) { 2192 u32 cr = pl011_read(uap, REG_CR); 2193 2194 cr &= ~UART011_CR_RTSEN; 2195 pl011_write(cr, uap, REG_CR); 2196 port->status &= ~UPSTAT_AUTORTS; 2197 } 2198 2199 return 0; 2200 } 2201 2202 static const struct uart_ops amba_pl011_pops = { 2203 .tx_empty = pl011_tx_empty, 2204 .set_mctrl = pl011_set_mctrl, 2205 .get_mctrl = pl011_get_mctrl, 2206 .stop_tx = pl011_stop_tx, 2207 .start_tx = pl011_start_tx, 2208 .stop_rx = pl011_stop_rx, 2209 .enable_ms = pl011_enable_ms, 2210 .break_ctl = pl011_break_ctl, 2211 .startup = pl011_startup, 2212 .shutdown = pl011_shutdown, 2213 .flush_buffer = pl011_dma_flush_buffer, 2214 .set_termios = pl011_set_termios, 2215 .type = pl011_type, 2216 .config_port = pl011_config_port, 2217 .verify_port = pl011_verify_port, 2218 #ifdef CONFIG_CONSOLE_POLL 2219 .poll_init = pl011_hwinit, 2220 .poll_get_char = pl011_get_poll_char, 2221 .poll_put_char = pl011_put_poll_char, 2222 #endif 2223 }; 2224 2225 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 2226 { 2227 } 2228 2229 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) 2230 { 2231 return 0; 2232 } 2233 2234 static const struct uart_ops sbsa_uart_pops = { 2235 .tx_empty = pl011_tx_empty, 2236 .set_mctrl = sbsa_uart_set_mctrl, 2237 .get_mctrl = sbsa_uart_get_mctrl, 2238 .stop_tx = pl011_stop_tx, 2239 .start_tx = pl011_start_tx, 2240 .stop_rx = pl011_stop_rx, 2241 .startup = sbsa_uart_startup, 2242 .shutdown = sbsa_uart_shutdown, 2243 .set_termios = sbsa_uart_set_termios, 2244 .type = pl011_type, 2245 .config_port = pl011_config_port, 2246 .verify_port = pl011_verify_port, 2247 #ifdef CONFIG_CONSOLE_POLL 2248 .poll_init = pl011_hwinit, 2249 .poll_get_char = pl011_get_poll_char, 2250 .poll_put_char = pl011_put_poll_char, 2251 #endif 2252 }; 2253 2254 static struct uart_amba_port *amba_ports[UART_NR]; 2255 2256 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE 2257 2258 static void pl011_console_putchar(struct uart_port *port, unsigned char ch) 2259 { 2260 struct uart_amba_port *uap = 2261 container_of(port, struct uart_amba_port, port); 2262 2263 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 2264 cpu_relax(); 2265 pl011_write(ch, uap, REG_DR); 2266 } 2267 2268 static void 2269 pl011_console_write(struct console *co, const char *s, unsigned int count) 2270 { 2271 struct uart_amba_port *uap = amba_ports[co->index]; 2272 unsigned int old_cr = 0, new_cr; 2273 unsigned long flags; 2274 int locked = 1; 2275 2276 clk_enable(uap->clk); 2277 2278 local_irq_save(flags); 2279 if (uap->port.sysrq) 2280 locked = 0; 2281 else if (oops_in_progress) 2282 locked = spin_trylock(&uap->port.lock); 2283 else 2284 spin_lock(&uap->port.lock); 2285 2286 /* 2287 * First save the CR then disable the interrupts 2288 */ 2289 if (!uap->vendor->always_enabled) { 2290 old_cr = pl011_read(uap, REG_CR); 2291 new_cr = old_cr & ~UART011_CR_CTSEN; 2292 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 2293 pl011_write(new_cr, uap, REG_CR); 2294 } 2295 2296 uart_console_write(&uap->port, s, count, pl011_console_putchar); 2297 2298 /* 2299 * Finally, wait for transmitter to become empty and restore the 2300 * TCR. Allow feature register bits to be inverted to work around 2301 * errata. 2302 */ 2303 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) 2304 & uap->vendor->fr_busy) 2305 cpu_relax(); 2306 if (!uap->vendor->always_enabled) 2307 pl011_write(old_cr, uap, REG_CR); 2308 2309 if (locked) 2310 spin_unlock(&uap->port.lock); 2311 local_irq_restore(flags); 2312 2313 clk_disable(uap->clk); 2314 } 2315 2316 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud, 2317 int *parity, int *bits) 2318 { 2319 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) { 2320 unsigned int lcr_h, ibrd, fbrd; 2321 2322 lcr_h = pl011_read(uap, REG_LCRH_TX); 2323 2324 *parity = 'n'; 2325 if (lcr_h & UART01x_LCRH_PEN) { 2326 if (lcr_h & UART01x_LCRH_EPS) 2327 *parity = 'e'; 2328 else 2329 *parity = 'o'; 2330 } 2331 2332 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 2333 *bits = 7; 2334 else 2335 *bits = 8; 2336 2337 ibrd = pl011_read(uap, REG_IBRD); 2338 fbrd = pl011_read(uap, REG_FBRD); 2339 2340 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); 2341 2342 if (uap->vendor->oversampling) { 2343 if (pl011_read(uap, REG_CR) 2344 & ST_UART011_CR_OVSFACT) 2345 *baud *= 2; 2346 } 2347 } 2348 } 2349 2350 static int pl011_console_setup(struct console *co, char *options) 2351 { 2352 struct uart_amba_port *uap; 2353 int baud = 38400; 2354 int bits = 8; 2355 int parity = 'n'; 2356 int flow = 'n'; 2357 int ret; 2358 2359 /* 2360 * Check whether an invalid uart number has been specified, and 2361 * if so, search for the first available port that does have 2362 * console support. 2363 */ 2364 if (co->index >= UART_NR) 2365 co->index = 0; 2366 uap = amba_ports[co->index]; 2367 if (!uap) 2368 return -ENODEV; 2369 2370 /* Allow pins to be muxed in and configured */ 2371 pinctrl_pm_select_default_state(uap->port.dev); 2372 2373 ret = clk_prepare(uap->clk); 2374 if (ret) 2375 return ret; 2376 2377 if (dev_get_platdata(uap->port.dev)) { 2378 struct amba_pl011_data *plat; 2379 2380 plat = dev_get_platdata(uap->port.dev); 2381 if (plat->init) 2382 plat->init(); 2383 } 2384 2385 uap->port.uartclk = clk_get_rate(uap->clk); 2386 2387 if (uap->vendor->fixed_options) { 2388 baud = uap->fixed_baud; 2389 } else { 2390 if (options) 2391 uart_parse_options(options, 2392 &baud, &parity, &bits, &flow); 2393 else 2394 pl011_console_get_options(uap, &baud, &parity, &bits); 2395 } 2396 2397 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 2398 } 2399 2400 /** 2401 * pl011_console_match - non-standard console matching 2402 * @co: registering console 2403 * @name: name from console command line 2404 * @idx: index from console command line 2405 * @options: ptr to option string from console command line 2406 * 2407 * Only attempts to match console command lines of the form: 2408 * console=pl011,mmio|mmio32,<addr>[,<options>] 2409 * console=pl011,0x<addr>[,<options>] 2410 * This form is used to register an initial earlycon boot console and 2411 * replace it with the amba_console at pl011 driver init. 2412 * 2413 * Performs console setup for a match (as required by interface) 2414 * If no <options> are specified, then assume the h/w is already setup. 2415 * 2416 * Returns 0 if console matches; otherwise non-zero to use default matching 2417 */ 2418 static int pl011_console_match(struct console *co, char *name, int idx, 2419 char *options) 2420 { 2421 unsigned char iotype; 2422 resource_size_t addr; 2423 int i; 2424 2425 /* 2426 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum 2427 * have a distinct console name, so make sure we check for that. 2428 * The actual implementation of the erratum occurs in the probe 2429 * function. 2430 */ 2431 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0)) 2432 return -ENODEV; 2433 2434 if (uart_parse_earlycon(options, &iotype, &addr, &options)) 2435 return -ENODEV; 2436 2437 if (iotype != UPIO_MEM && iotype != UPIO_MEM32) 2438 return -ENODEV; 2439 2440 /* try to match the port specified on the command line */ 2441 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2442 struct uart_port *port; 2443 2444 if (!amba_ports[i]) 2445 continue; 2446 2447 port = &amba_ports[i]->port; 2448 2449 if (port->mapbase != addr) 2450 continue; 2451 2452 co->index = i; 2453 port->cons = co; 2454 return pl011_console_setup(co, options); 2455 } 2456 2457 return -ENODEV; 2458 } 2459 2460 static struct uart_driver amba_reg; 2461 static struct console amba_console = { 2462 .name = "ttyAMA", 2463 .write = pl011_console_write, 2464 .device = uart_console_device, 2465 .setup = pl011_console_setup, 2466 .match = pl011_console_match, 2467 .flags = CON_PRINTBUFFER | CON_ANYTIME, 2468 .index = -1, 2469 .data = &amba_reg, 2470 }; 2471 2472 #define AMBA_CONSOLE (&amba_console) 2473 2474 static void qdf2400_e44_putc(struct uart_port *port, unsigned char c) 2475 { 2476 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2477 cpu_relax(); 2478 writel(c, port->membase + UART01x_DR); 2479 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) 2480 cpu_relax(); 2481 } 2482 2483 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n) 2484 { 2485 struct earlycon_device *dev = con->data; 2486 2487 uart_console_write(&dev->port, s, n, qdf2400_e44_putc); 2488 } 2489 2490 static void pl011_putc(struct uart_port *port, unsigned char c) 2491 { 2492 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2493 cpu_relax(); 2494 if (port->iotype == UPIO_MEM32) 2495 writel(c, port->membase + UART01x_DR); 2496 else 2497 writeb(c, port->membase + UART01x_DR); 2498 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) 2499 cpu_relax(); 2500 } 2501 2502 static void pl011_early_write(struct console *con, const char *s, unsigned n) 2503 { 2504 struct earlycon_device *dev = con->data; 2505 2506 uart_console_write(&dev->port, s, n, pl011_putc); 2507 } 2508 2509 #ifdef CONFIG_CONSOLE_POLL 2510 static int pl011_getc(struct uart_port *port) 2511 { 2512 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE) 2513 return NO_POLL_CHAR; 2514 2515 if (port->iotype == UPIO_MEM32) 2516 return readl(port->membase + UART01x_DR); 2517 else 2518 return readb(port->membase + UART01x_DR); 2519 } 2520 2521 static int pl011_early_read(struct console *con, char *s, unsigned int n) 2522 { 2523 struct earlycon_device *dev = con->data; 2524 int ch, num_read = 0; 2525 2526 while (num_read < n) { 2527 ch = pl011_getc(&dev->port); 2528 if (ch == NO_POLL_CHAR) 2529 break; 2530 2531 s[num_read++] = ch; 2532 } 2533 2534 return num_read; 2535 } 2536 #else 2537 #define pl011_early_read NULL 2538 #endif 2539 2540 /* 2541 * On non-ACPI systems, earlycon is enabled by specifying 2542 * "earlycon=pl011,<address>" on the kernel command line. 2543 * 2544 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table, 2545 * by specifying only "earlycon" on the command line. Because it requires 2546 * SPCR, the console starts after ACPI is parsed, which is later than a 2547 * traditional early console. 2548 * 2549 * To get the traditional early console that starts before ACPI is parsed, 2550 * specify the full "earlycon=pl011,<address>" option. 2551 */ 2552 static int __init pl011_early_console_setup(struct earlycon_device *device, 2553 const char *opt) 2554 { 2555 if (!device->port.membase) 2556 return -ENODEV; 2557 2558 device->con->write = pl011_early_write; 2559 device->con->read = pl011_early_read; 2560 2561 return 0; 2562 } 2563 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); 2564 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup); 2565 2566 /* 2567 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by 2568 * Erratum 44, traditional earlycon can be enabled by specifying 2569 * "earlycon=qdf2400_e44,<address>". Any options are ignored. 2570 * 2571 * Alternatively, you can just specify "earlycon", and the early console 2572 * will be enabled with the information from the SPCR table. In this 2573 * case, the SPCR code will detect the need for the E44 work-around, 2574 * and set the console name to "qdf2400_e44". 2575 */ 2576 static int __init 2577 qdf2400_e44_early_console_setup(struct earlycon_device *device, 2578 const char *opt) 2579 { 2580 if (!device->port.membase) 2581 return -ENODEV; 2582 2583 device->con->write = qdf2400_e44_early_write; 2584 return 0; 2585 } 2586 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup); 2587 2588 #else 2589 #define AMBA_CONSOLE NULL 2590 #endif 2591 2592 static struct uart_driver amba_reg = { 2593 .owner = THIS_MODULE, 2594 .driver_name = "ttyAMA", 2595 .dev_name = "ttyAMA", 2596 .major = SERIAL_AMBA_MAJOR, 2597 .minor = SERIAL_AMBA_MINOR, 2598 .nr = UART_NR, 2599 .cons = AMBA_CONSOLE, 2600 }; 2601 2602 static int pl011_probe_dt_alias(int index, struct device *dev) 2603 { 2604 struct device_node *np; 2605 static bool seen_dev_with_alias = false; 2606 static bool seen_dev_without_alias = false; 2607 int ret = index; 2608 2609 if (!IS_ENABLED(CONFIG_OF)) 2610 return ret; 2611 2612 np = dev->of_node; 2613 if (!np) 2614 return ret; 2615 2616 ret = of_alias_get_id(np, "serial"); 2617 if (ret < 0) { 2618 seen_dev_without_alias = true; 2619 ret = index; 2620 } else { 2621 seen_dev_with_alias = true; 2622 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { 2623 dev_warn(dev, "requested serial port %d not available.\n", ret); 2624 ret = index; 2625 } 2626 } 2627 2628 if (seen_dev_with_alias && seen_dev_without_alias) 2629 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); 2630 2631 return ret; 2632 } 2633 2634 /* unregisters the driver also if no more ports are left */ 2635 static void pl011_unregister_port(struct uart_amba_port *uap) 2636 { 2637 int i; 2638 bool busy = false; 2639 2640 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2641 if (amba_ports[i] == uap) 2642 amba_ports[i] = NULL; 2643 else if (amba_ports[i]) 2644 busy = true; 2645 } 2646 pl011_dma_remove(uap); 2647 if (!busy) 2648 uart_unregister_driver(&amba_reg); 2649 } 2650 2651 static int pl011_find_free_port(void) 2652 { 2653 int i; 2654 2655 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2656 if (amba_ports[i] == NULL) 2657 return i; 2658 2659 return -EBUSY; 2660 } 2661 2662 static int pl011_get_rs485_mode(struct uart_amba_port *uap) 2663 { 2664 struct uart_port *port = &uap->port; 2665 struct serial_rs485 *rs485 = &port->rs485; 2666 int ret; 2667 2668 ret = uart_get_rs485_mode(port); 2669 if (ret) 2670 return ret; 2671 2672 /* clamp the delays to [0, 100ms] */ 2673 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U); 2674 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U); 2675 2676 return 0; 2677 } 2678 2679 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, 2680 struct resource *mmiobase, int index) 2681 { 2682 void __iomem *base; 2683 int ret; 2684 2685 base = devm_ioremap_resource(dev, mmiobase); 2686 if (IS_ERR(base)) 2687 return PTR_ERR(base); 2688 2689 index = pl011_probe_dt_alias(index, dev); 2690 2691 uap->port.dev = dev; 2692 uap->port.mapbase = mmiobase->start; 2693 uap->port.membase = base; 2694 uap->port.fifosize = uap->fifosize; 2695 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE); 2696 uap->port.flags = UPF_BOOT_AUTOCONF; 2697 uap->port.line = index; 2698 2699 ret = pl011_get_rs485_mode(uap); 2700 if (ret) 2701 return ret; 2702 2703 amba_ports[index] = uap; 2704 2705 return 0; 2706 } 2707 2708 static int pl011_register_port(struct uart_amba_port *uap) 2709 { 2710 int ret, i; 2711 2712 /* Ensure interrupts from this UART are masked and cleared */ 2713 pl011_write(0, uap, REG_IMSC); 2714 pl011_write(0xffff, uap, REG_ICR); 2715 2716 if (!amba_reg.state) { 2717 ret = uart_register_driver(&amba_reg); 2718 if (ret < 0) { 2719 dev_err(uap->port.dev, 2720 "Failed to register AMBA-PL011 driver\n"); 2721 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2722 if (amba_ports[i] == uap) 2723 amba_ports[i] = NULL; 2724 return ret; 2725 } 2726 } 2727 2728 ret = uart_add_one_port(&amba_reg, &uap->port); 2729 if (ret) 2730 pl011_unregister_port(uap); 2731 2732 return ret; 2733 } 2734 2735 static int pl011_probe(struct amba_device *dev, const struct amba_id *id) 2736 { 2737 struct uart_amba_port *uap; 2738 struct vendor_data *vendor = id->data; 2739 int portnr, ret; 2740 2741 portnr = pl011_find_free_port(); 2742 if (portnr < 0) 2743 return portnr; 2744 2745 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), 2746 GFP_KERNEL); 2747 if (!uap) 2748 return -ENOMEM; 2749 2750 uap->clk = devm_clk_get(&dev->dev, NULL); 2751 if (IS_ERR(uap->clk)) 2752 return PTR_ERR(uap->clk); 2753 2754 uap->reg_offset = vendor->reg_offset; 2755 uap->vendor = vendor; 2756 uap->fifosize = vendor->get_fifosize(dev); 2757 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 2758 uap->port.irq = dev->irq[0]; 2759 uap->port.ops = &amba_pl011_pops; 2760 uap->port.rs485_config = pl011_rs485_config; 2761 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); 2762 2763 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); 2764 if (ret) 2765 return ret; 2766 2767 amba_set_drvdata(dev, uap); 2768 2769 return pl011_register_port(uap); 2770 } 2771 2772 static void pl011_remove(struct amba_device *dev) 2773 { 2774 struct uart_amba_port *uap = amba_get_drvdata(dev); 2775 2776 uart_remove_one_port(&amba_reg, &uap->port); 2777 pl011_unregister_port(uap); 2778 } 2779 2780 #ifdef CONFIG_PM_SLEEP 2781 static int pl011_suspend(struct device *dev) 2782 { 2783 struct uart_amba_port *uap = dev_get_drvdata(dev); 2784 2785 if (!uap) 2786 return -EINVAL; 2787 2788 return uart_suspend_port(&amba_reg, &uap->port); 2789 } 2790 2791 static int pl011_resume(struct device *dev) 2792 { 2793 struct uart_amba_port *uap = dev_get_drvdata(dev); 2794 2795 if (!uap) 2796 return -EINVAL; 2797 2798 return uart_resume_port(&amba_reg, &uap->port); 2799 } 2800 #endif 2801 2802 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); 2803 2804 static int sbsa_uart_probe(struct platform_device *pdev) 2805 { 2806 struct uart_amba_port *uap; 2807 struct resource *r; 2808 int portnr, ret; 2809 int baudrate; 2810 2811 /* 2812 * Check the mandatory baud rate parameter in the DT node early 2813 * so that we can easily exit with the error. 2814 */ 2815 if (pdev->dev.of_node) { 2816 struct device_node *np = pdev->dev.of_node; 2817 2818 ret = of_property_read_u32(np, "current-speed", &baudrate); 2819 if (ret) 2820 return ret; 2821 } else { 2822 baudrate = 115200; 2823 } 2824 2825 portnr = pl011_find_free_port(); 2826 if (portnr < 0) 2827 return portnr; 2828 2829 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), 2830 GFP_KERNEL); 2831 if (!uap) 2832 return -ENOMEM; 2833 2834 ret = platform_get_irq(pdev, 0); 2835 if (ret < 0) 2836 return ret; 2837 uap->port.irq = ret; 2838 2839 #ifdef CONFIG_ACPI_SPCR_TABLE 2840 if (qdf2400_e44_present) { 2841 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n"); 2842 uap->vendor = &vendor_qdt_qdf2400_e44; 2843 } else 2844 #endif 2845 uap->vendor = &vendor_sbsa; 2846 2847 uap->reg_offset = uap->vendor->reg_offset; 2848 uap->fifosize = 32; 2849 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 2850 uap->port.ops = &sbsa_uart_pops; 2851 uap->fixed_baud = baudrate; 2852 2853 snprintf(uap->type, sizeof(uap->type), "SBSA"); 2854 2855 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2856 2857 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); 2858 if (ret) 2859 return ret; 2860 2861 platform_set_drvdata(pdev, uap); 2862 2863 return pl011_register_port(uap); 2864 } 2865 2866 static int sbsa_uart_remove(struct platform_device *pdev) 2867 { 2868 struct uart_amba_port *uap = platform_get_drvdata(pdev); 2869 2870 uart_remove_one_port(&amba_reg, &uap->port); 2871 pl011_unregister_port(uap); 2872 return 0; 2873 } 2874 2875 static const struct of_device_id sbsa_uart_of_match[] = { 2876 { .compatible = "arm,sbsa-uart", }, 2877 {}, 2878 }; 2879 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); 2880 2881 static const struct acpi_device_id __maybe_unused sbsa_uart_acpi_match[] = { 2882 { "ARMH0011", 0 }, 2883 { "ARMHB000", 0 }, 2884 {}, 2885 }; 2886 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); 2887 2888 static struct platform_driver arm_sbsa_uart_platform_driver = { 2889 .probe = sbsa_uart_probe, 2890 .remove = sbsa_uart_remove, 2891 .driver = { 2892 .name = "sbsa-uart", 2893 .pm = &pl011_dev_pm_ops, 2894 .of_match_table = of_match_ptr(sbsa_uart_of_match), 2895 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match), 2896 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), 2897 }, 2898 }; 2899 2900 static const struct amba_id pl011_ids[] = { 2901 { 2902 .id = 0x00041011, 2903 .mask = 0x000fffff, 2904 .data = &vendor_arm, 2905 }, 2906 { 2907 .id = 0x00380802, 2908 .mask = 0x00ffffff, 2909 .data = &vendor_st, 2910 }, 2911 { 0, 0 }, 2912 }; 2913 2914 MODULE_DEVICE_TABLE(amba, pl011_ids); 2915 2916 static struct amba_driver pl011_driver = { 2917 .drv = { 2918 .name = "uart-pl011", 2919 .pm = &pl011_dev_pm_ops, 2920 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), 2921 }, 2922 .id_table = pl011_ids, 2923 .probe = pl011_probe, 2924 .remove = pl011_remove, 2925 }; 2926 2927 static int __init pl011_init(void) 2928 { 2929 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); 2930 2931 if (platform_driver_register(&arm_sbsa_uart_platform_driver)) 2932 pr_warn("could not register SBSA UART platform driver\n"); 2933 return amba_driver_register(&pl011_driver); 2934 } 2935 2936 static void __exit pl011_exit(void) 2937 { 2938 platform_driver_unregister(&arm_sbsa_uart_platform_driver); 2939 amba_driver_unregister(&pl011_driver); 2940 } 2941 2942 /* 2943 * While this can be a module, if builtin it's most likely the console 2944 * So let's leave module_exit but move module_init to an earlier place 2945 */ 2946 arch_initcall(pl011_init); 2947 module_exit(pl011_exit); 2948 2949 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 2950 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 2951 MODULE_LICENSE("GPL"); 2952