1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for AMBA serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright 1999 ARM Limited 8 * Copyright (C) 2000 Deep Blue Solutions Ltd. 9 * Copyright (C) 2010 ST-Ericsson SA 10 * 11 * This is a generic driver for ARM AMBA-type serial ports. They 12 * have a lot of 16550-like features, but are not register compatible. 13 * Note that although they do have CTS, DCD and DSR inputs, they do 14 * not have an RI input, nor do they have DTR or RTS outputs. If 15 * required, these have to be supplied via some other means (eg, GPIO) 16 * and hooked into this driver. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/ioport.h> 21 #include <linux/init.h> 22 #include <linux/console.h> 23 #include <linux/platform_device.h> 24 #include <linux/sysrq.h> 25 #include <linux/device.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/amba/bus.h> 31 #include <linux/amba/serial.h> 32 #include <linux/clk.h> 33 #include <linux/slab.h> 34 #include <linux/dmaengine.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/scatterlist.h> 37 #include <linux/delay.h> 38 #include <linux/types.h> 39 #include <linux/of.h> 40 #include <linux/pinctrl/consumer.h> 41 #include <linux/sizes.h> 42 #include <linux/io.h> 43 #include <linux/acpi.h> 44 45 #define UART_NR 14 46 47 #define SERIAL_AMBA_MAJOR 204 48 #define SERIAL_AMBA_MINOR 64 49 #define SERIAL_AMBA_NR UART_NR 50 51 #define AMBA_ISR_PASS_LIMIT 256 52 53 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) 54 #define UART_DUMMY_DR_RX (1 << 16) 55 56 enum { 57 REG_DR, 58 REG_ST_DMAWM, 59 REG_ST_TIMEOUT, 60 REG_FR, 61 REG_LCRH_RX, 62 REG_LCRH_TX, 63 REG_IBRD, 64 REG_FBRD, 65 REG_CR, 66 REG_IFLS, 67 REG_IMSC, 68 REG_RIS, 69 REG_MIS, 70 REG_ICR, 71 REG_DMACR, 72 REG_ST_XFCR, 73 REG_ST_XON1, 74 REG_ST_XON2, 75 REG_ST_XOFF1, 76 REG_ST_XOFF2, 77 REG_ST_ITCR, 78 REG_ST_ITIP, 79 REG_ST_ABCR, 80 REG_ST_ABIMSC, 81 82 /* The size of the array - must be last */ 83 REG_ARRAY_SIZE, 84 }; 85 86 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = { 87 [REG_DR] = UART01x_DR, 88 [REG_FR] = UART01x_FR, 89 [REG_LCRH_RX] = UART011_LCRH, 90 [REG_LCRH_TX] = UART011_LCRH, 91 [REG_IBRD] = UART011_IBRD, 92 [REG_FBRD] = UART011_FBRD, 93 [REG_CR] = UART011_CR, 94 [REG_IFLS] = UART011_IFLS, 95 [REG_IMSC] = UART011_IMSC, 96 [REG_RIS] = UART011_RIS, 97 [REG_MIS] = UART011_MIS, 98 [REG_ICR] = UART011_ICR, 99 [REG_DMACR] = UART011_DMACR, 100 }; 101 102 /* There is by now at least one vendor with differing details, so handle it */ 103 struct vendor_data { 104 const u16 *reg_offset; 105 unsigned int ifls; 106 unsigned int fr_busy; 107 unsigned int fr_dsr; 108 unsigned int fr_cts; 109 unsigned int fr_ri; 110 unsigned int inv_fr; 111 bool access_32b; 112 bool oversampling; 113 bool dma_threshold; 114 bool cts_event_workaround; 115 bool always_enabled; 116 bool fixed_options; 117 118 unsigned int (*get_fifosize)(struct amba_device *dev); 119 }; 120 121 static unsigned int get_fifosize_arm(struct amba_device *dev) 122 { 123 return amba_rev(dev) < 3 ? 16 : 32; 124 } 125 126 static struct vendor_data vendor_arm = { 127 .reg_offset = pl011_std_offsets, 128 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 129 .fr_busy = UART01x_FR_BUSY, 130 .fr_dsr = UART01x_FR_DSR, 131 .fr_cts = UART01x_FR_CTS, 132 .fr_ri = UART011_FR_RI, 133 .oversampling = false, 134 .dma_threshold = false, 135 .cts_event_workaround = false, 136 .always_enabled = false, 137 .fixed_options = false, 138 .get_fifosize = get_fifosize_arm, 139 }; 140 141 static const struct vendor_data vendor_sbsa = { 142 .reg_offset = pl011_std_offsets, 143 .fr_busy = UART01x_FR_BUSY, 144 .fr_dsr = UART01x_FR_DSR, 145 .fr_cts = UART01x_FR_CTS, 146 .fr_ri = UART011_FR_RI, 147 .access_32b = true, 148 .oversampling = false, 149 .dma_threshold = false, 150 .cts_event_workaround = false, 151 .always_enabled = true, 152 .fixed_options = true, 153 }; 154 155 #ifdef CONFIG_ACPI_SPCR_TABLE 156 static const struct vendor_data vendor_qdt_qdf2400_e44 = { 157 .reg_offset = pl011_std_offsets, 158 .fr_busy = UART011_FR_TXFE, 159 .fr_dsr = UART01x_FR_DSR, 160 .fr_cts = UART01x_FR_CTS, 161 .fr_ri = UART011_FR_RI, 162 .inv_fr = UART011_FR_TXFE, 163 .access_32b = true, 164 .oversampling = false, 165 .dma_threshold = false, 166 .cts_event_workaround = false, 167 .always_enabled = true, 168 .fixed_options = true, 169 }; 170 #endif 171 172 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { 173 [REG_DR] = UART01x_DR, 174 [REG_ST_DMAWM] = ST_UART011_DMAWM, 175 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, 176 [REG_FR] = UART01x_FR, 177 [REG_LCRH_RX] = ST_UART011_LCRH_RX, 178 [REG_LCRH_TX] = ST_UART011_LCRH_TX, 179 [REG_IBRD] = UART011_IBRD, 180 [REG_FBRD] = UART011_FBRD, 181 [REG_CR] = UART011_CR, 182 [REG_IFLS] = UART011_IFLS, 183 [REG_IMSC] = UART011_IMSC, 184 [REG_RIS] = UART011_RIS, 185 [REG_MIS] = UART011_MIS, 186 [REG_ICR] = UART011_ICR, 187 [REG_DMACR] = UART011_DMACR, 188 [REG_ST_XFCR] = ST_UART011_XFCR, 189 [REG_ST_XON1] = ST_UART011_XON1, 190 [REG_ST_XON2] = ST_UART011_XON2, 191 [REG_ST_XOFF1] = ST_UART011_XOFF1, 192 [REG_ST_XOFF2] = ST_UART011_XOFF2, 193 [REG_ST_ITCR] = ST_UART011_ITCR, 194 [REG_ST_ITIP] = ST_UART011_ITIP, 195 [REG_ST_ABCR] = ST_UART011_ABCR, 196 [REG_ST_ABIMSC] = ST_UART011_ABIMSC, 197 }; 198 199 static unsigned int get_fifosize_st(struct amba_device *dev) 200 { 201 return 64; 202 } 203 204 static struct vendor_data vendor_st = { 205 .reg_offset = pl011_st_offsets, 206 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, 207 .fr_busy = UART01x_FR_BUSY, 208 .fr_dsr = UART01x_FR_DSR, 209 .fr_cts = UART01x_FR_CTS, 210 .fr_ri = UART011_FR_RI, 211 .oversampling = true, 212 .dma_threshold = true, 213 .cts_event_workaround = true, 214 .always_enabled = false, 215 .fixed_options = false, 216 .get_fifosize = get_fifosize_st, 217 }; 218 219 /* Deals with DMA transactions */ 220 221 struct pl011_dmabuf { 222 dma_addr_t dma; 223 size_t len; 224 char *buf; 225 }; 226 227 struct pl011_dmarx_data { 228 struct dma_chan *chan; 229 struct completion complete; 230 bool use_buf_b; 231 struct pl011_dmabuf dbuf_a; 232 struct pl011_dmabuf dbuf_b; 233 dma_cookie_t cookie; 234 bool running; 235 struct timer_list timer; 236 unsigned int last_residue; 237 unsigned long last_jiffies; 238 bool auto_poll_rate; 239 unsigned int poll_rate; 240 unsigned int poll_timeout; 241 }; 242 243 struct pl011_dmatx_data { 244 struct dma_chan *chan; 245 dma_addr_t dma; 246 size_t len; 247 char *buf; 248 bool queued; 249 }; 250 251 /* 252 * We wrap our port structure around the generic uart_port. 253 */ 254 struct uart_amba_port { 255 struct uart_port port; 256 const u16 *reg_offset; 257 struct clk *clk; 258 const struct vendor_data *vendor; 259 unsigned int dmacr; /* dma control reg */ 260 unsigned int im; /* interrupt mask */ 261 unsigned int old_status; 262 unsigned int fifosize; /* vendor-specific */ 263 unsigned int fixed_baud; /* vendor-set fixed baud rate */ 264 char type[12]; 265 bool rs485_tx_started; 266 unsigned int rs485_tx_drain_interval; /* usecs */ 267 #ifdef CONFIG_DMA_ENGINE 268 /* DMA stuff */ 269 bool using_tx_dma; 270 bool using_rx_dma; 271 struct pl011_dmarx_data dmarx; 272 struct pl011_dmatx_data dmatx; 273 bool dma_probed; 274 #endif 275 }; 276 277 static unsigned int pl011_tx_empty(struct uart_port *port); 278 279 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, 280 unsigned int reg) 281 { 282 return uap->reg_offset[reg]; 283 } 284 285 static unsigned int pl011_read(const struct uart_amba_port *uap, 286 unsigned int reg) 287 { 288 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 289 290 return (uap->port.iotype == UPIO_MEM32) ? 291 readl_relaxed(addr) : readw_relaxed(addr); 292 } 293 294 static void pl011_write(unsigned int val, const struct uart_amba_port *uap, 295 unsigned int reg) 296 { 297 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 298 299 if (uap->port.iotype == UPIO_MEM32) 300 writel_relaxed(val, addr); 301 else 302 writew_relaxed(val, addr); 303 } 304 305 /* 306 * Reads up to 256 characters from the FIFO or until it's empty and 307 * inserts them into the TTY layer. Returns the number of characters 308 * read from the FIFO. 309 */ 310 static int pl011_fifo_to_tty(struct uart_amba_port *uap) 311 { 312 unsigned int ch, fifotaken; 313 int sysrq; 314 u16 status; 315 u8 flag; 316 317 for (fifotaken = 0; fifotaken != 256; fifotaken++) { 318 status = pl011_read(uap, REG_FR); 319 if (status & UART01x_FR_RXFE) 320 break; 321 322 /* Take chars from the FIFO and update status */ 323 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; 324 flag = TTY_NORMAL; 325 uap->port.icount.rx++; 326 327 if (unlikely(ch & UART_DR_ERROR)) { 328 if (ch & UART011_DR_BE) { 329 ch &= ~(UART011_DR_FE | UART011_DR_PE); 330 uap->port.icount.brk++; 331 if (uart_handle_break(&uap->port)) 332 continue; 333 } else if (ch & UART011_DR_PE) 334 uap->port.icount.parity++; 335 else if (ch & UART011_DR_FE) 336 uap->port.icount.frame++; 337 if (ch & UART011_DR_OE) 338 uap->port.icount.overrun++; 339 340 ch &= uap->port.read_status_mask; 341 342 if (ch & UART011_DR_BE) 343 flag = TTY_BREAK; 344 else if (ch & UART011_DR_PE) 345 flag = TTY_PARITY; 346 else if (ch & UART011_DR_FE) 347 flag = TTY_FRAME; 348 } 349 350 uart_port_unlock(&uap->port); 351 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255); 352 uart_port_lock(&uap->port); 353 354 if (!sysrq) 355 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); 356 } 357 358 return fifotaken; 359 } 360 361 362 /* 363 * All the DMA operation mode stuff goes inside this ifdef. 364 * This assumes that you have a generic DMA device interface, 365 * no custom DMA interfaces are supported. 366 */ 367 #ifdef CONFIG_DMA_ENGINE 368 369 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE 370 371 static int pl011_dmabuf_init(struct dma_chan *chan, struct pl011_dmabuf *db, 372 enum dma_data_direction dir) 373 { 374 db->buf = dma_alloc_coherent(chan->device->dev, PL011_DMA_BUFFER_SIZE, 375 &db->dma, GFP_KERNEL); 376 if (!db->buf) 377 return -ENOMEM; 378 db->len = PL011_DMA_BUFFER_SIZE; 379 380 return 0; 381 } 382 383 static void pl011_dmabuf_free(struct dma_chan *chan, struct pl011_dmabuf *db, 384 enum dma_data_direction dir) 385 { 386 if (db->buf) { 387 dma_free_coherent(chan->device->dev, 388 PL011_DMA_BUFFER_SIZE, db->buf, db->dma); 389 } 390 } 391 392 static void pl011_dma_probe(struct uart_amba_port *uap) 393 { 394 /* DMA is the sole user of the platform data right now */ 395 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); 396 struct device *dev = uap->port.dev; 397 struct dma_slave_config tx_conf = { 398 .dst_addr = uap->port.mapbase + 399 pl011_reg_to_offset(uap, REG_DR), 400 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 401 .direction = DMA_MEM_TO_DEV, 402 .dst_maxburst = uap->fifosize >> 1, 403 .device_fc = false, 404 }; 405 struct dma_chan *chan; 406 dma_cap_mask_t mask; 407 408 uap->dma_probed = true; 409 chan = dma_request_chan(dev, "tx"); 410 if (IS_ERR(chan)) { 411 if (PTR_ERR(chan) == -EPROBE_DEFER) { 412 uap->dma_probed = false; 413 return; 414 } 415 416 /* We need platform data */ 417 if (!plat || !plat->dma_filter) { 418 dev_info(uap->port.dev, "no DMA platform data\n"); 419 return; 420 } 421 422 /* Try to acquire a generic DMA engine slave TX channel */ 423 dma_cap_zero(mask); 424 dma_cap_set(DMA_SLAVE, mask); 425 426 chan = dma_request_channel(mask, plat->dma_filter, 427 plat->dma_tx_param); 428 if (!chan) { 429 dev_err(uap->port.dev, "no TX DMA channel!\n"); 430 return; 431 } 432 } 433 434 dmaengine_slave_config(chan, &tx_conf); 435 uap->dmatx.chan = chan; 436 437 dev_info(uap->port.dev, "DMA channel TX %s\n", 438 dma_chan_name(uap->dmatx.chan)); 439 440 /* Optionally make use of an RX channel as well */ 441 chan = dma_request_slave_channel(dev, "rx"); 442 443 if (!chan && plat && plat->dma_rx_param) { 444 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); 445 446 if (!chan) { 447 dev_err(uap->port.dev, "no RX DMA channel!\n"); 448 return; 449 } 450 } 451 452 if (chan) { 453 struct dma_slave_config rx_conf = { 454 .src_addr = uap->port.mapbase + 455 pl011_reg_to_offset(uap, REG_DR), 456 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 457 .direction = DMA_DEV_TO_MEM, 458 .src_maxburst = uap->fifosize >> 2, 459 .device_fc = false, 460 }; 461 struct dma_slave_caps caps; 462 463 /* 464 * Some DMA controllers provide information on their capabilities. 465 * If the controller does, check for suitable residue processing 466 * otherwise assime all is well. 467 */ 468 if (0 == dma_get_slave_caps(chan, &caps)) { 469 if (caps.residue_granularity == 470 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { 471 dma_release_channel(chan); 472 dev_info(uap->port.dev, 473 "RX DMA disabled - no residue processing\n"); 474 return; 475 } 476 } 477 dmaengine_slave_config(chan, &rx_conf); 478 uap->dmarx.chan = chan; 479 480 uap->dmarx.auto_poll_rate = false; 481 if (plat && plat->dma_rx_poll_enable) { 482 /* Set poll rate if specified. */ 483 if (plat->dma_rx_poll_rate) { 484 uap->dmarx.auto_poll_rate = false; 485 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; 486 } else { 487 /* 488 * 100 ms defaults to poll rate if not 489 * specified. This will be adjusted with 490 * the baud rate at set_termios. 491 */ 492 uap->dmarx.auto_poll_rate = true; 493 uap->dmarx.poll_rate = 100; 494 } 495 /* 3 secs defaults poll_timeout if not specified. */ 496 if (plat->dma_rx_poll_timeout) 497 uap->dmarx.poll_timeout = 498 plat->dma_rx_poll_timeout; 499 else 500 uap->dmarx.poll_timeout = 3000; 501 } else if (!plat && dev->of_node) { 502 uap->dmarx.auto_poll_rate = of_property_read_bool( 503 dev->of_node, "auto-poll"); 504 if (uap->dmarx.auto_poll_rate) { 505 u32 x; 506 507 if (0 == of_property_read_u32(dev->of_node, 508 "poll-rate-ms", &x)) 509 uap->dmarx.poll_rate = x; 510 else 511 uap->dmarx.poll_rate = 100; 512 if (0 == of_property_read_u32(dev->of_node, 513 "poll-timeout-ms", &x)) 514 uap->dmarx.poll_timeout = x; 515 else 516 uap->dmarx.poll_timeout = 3000; 517 } 518 } 519 dev_info(uap->port.dev, "DMA channel RX %s\n", 520 dma_chan_name(uap->dmarx.chan)); 521 } 522 } 523 524 static void pl011_dma_remove(struct uart_amba_port *uap) 525 { 526 if (uap->dmatx.chan) 527 dma_release_channel(uap->dmatx.chan); 528 if (uap->dmarx.chan) 529 dma_release_channel(uap->dmarx.chan); 530 } 531 532 /* Forward declare these for the refill routine */ 533 static int pl011_dma_tx_refill(struct uart_amba_port *uap); 534 static void pl011_start_tx_pio(struct uart_amba_port *uap); 535 536 /* 537 * The current DMA TX buffer has been sent. 538 * Try to queue up another DMA buffer. 539 */ 540 static void pl011_dma_tx_callback(void *data) 541 { 542 struct uart_amba_port *uap = data; 543 struct pl011_dmatx_data *dmatx = &uap->dmatx; 544 unsigned long flags; 545 u16 dmacr; 546 547 uart_port_lock_irqsave(&uap->port, &flags); 548 if (uap->dmatx.queued) 549 dma_unmap_single(dmatx->chan->device->dev, dmatx->dma, 550 dmatx->len, DMA_TO_DEVICE); 551 552 dmacr = uap->dmacr; 553 uap->dmacr = dmacr & ~UART011_TXDMAE; 554 pl011_write(uap->dmacr, uap, REG_DMACR); 555 556 /* 557 * If TX DMA was disabled, it means that we've stopped the DMA for 558 * some reason (eg, XOFF received, or we want to send an X-char.) 559 * 560 * Note: we need to be careful here of a potential race between DMA 561 * and the rest of the driver - if the driver disables TX DMA while 562 * a TX buffer completing, we must update the tx queued status to 563 * get further refills (hence we check dmacr). 564 */ 565 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || 566 uart_circ_empty(&uap->port.state->xmit)) { 567 uap->dmatx.queued = false; 568 uart_port_unlock_irqrestore(&uap->port, flags); 569 return; 570 } 571 572 if (pl011_dma_tx_refill(uap) <= 0) 573 /* 574 * We didn't queue a DMA buffer for some reason, but we 575 * have data pending to be sent. Re-enable the TX IRQ. 576 */ 577 pl011_start_tx_pio(uap); 578 579 uart_port_unlock_irqrestore(&uap->port, flags); 580 } 581 582 /* 583 * Try to refill the TX DMA buffer. 584 * Locking: called with port lock held and IRQs disabled. 585 * Returns: 586 * 1 if we queued up a TX DMA buffer. 587 * 0 if we didn't want to handle this by DMA 588 * <0 on error 589 */ 590 static int pl011_dma_tx_refill(struct uart_amba_port *uap) 591 { 592 struct pl011_dmatx_data *dmatx = &uap->dmatx; 593 struct dma_chan *chan = dmatx->chan; 594 struct dma_device *dma_dev = chan->device; 595 struct dma_async_tx_descriptor *desc; 596 struct circ_buf *xmit = &uap->port.state->xmit; 597 unsigned int count; 598 599 /* 600 * Try to avoid the overhead involved in using DMA if the 601 * transaction fits in the first half of the FIFO, by using 602 * the standard interrupt handling. This ensures that we 603 * issue a uart_write_wakeup() at the appropriate time. 604 */ 605 count = uart_circ_chars_pending(xmit); 606 if (count < (uap->fifosize >> 1)) { 607 uap->dmatx.queued = false; 608 return 0; 609 } 610 611 /* 612 * Bodge: don't send the last character by DMA, as this 613 * will prevent XON from notifying us to restart DMA. 614 */ 615 count -= 1; 616 617 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ 618 if (count > PL011_DMA_BUFFER_SIZE) 619 count = PL011_DMA_BUFFER_SIZE; 620 621 if (xmit->tail < xmit->head) 622 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); 623 else { 624 size_t first = UART_XMIT_SIZE - xmit->tail; 625 size_t second; 626 627 if (first > count) 628 first = count; 629 second = count - first; 630 631 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); 632 if (second) 633 memcpy(&dmatx->buf[first], &xmit->buf[0], second); 634 } 635 636 dmatx->len = count; 637 dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count, 638 DMA_TO_DEVICE); 639 if (dmatx->dma == DMA_MAPPING_ERROR) { 640 uap->dmatx.queued = false; 641 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); 642 return -EBUSY; 643 } 644 645 desc = dmaengine_prep_slave_single(chan, dmatx->dma, dmatx->len, DMA_MEM_TO_DEV, 646 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 647 if (!desc) { 648 dma_unmap_single(dma_dev->dev, dmatx->dma, dmatx->len, DMA_TO_DEVICE); 649 uap->dmatx.queued = false; 650 /* 651 * If DMA cannot be used right now, we complete this 652 * transaction via IRQ and let the TTY layer retry. 653 */ 654 dev_dbg(uap->port.dev, "TX DMA busy\n"); 655 return -EBUSY; 656 } 657 658 /* Some data to go along to the callback */ 659 desc->callback = pl011_dma_tx_callback; 660 desc->callback_param = uap; 661 662 /* All errors should happen at prepare time */ 663 dmaengine_submit(desc); 664 665 /* Fire the DMA transaction */ 666 dma_dev->device_issue_pending(chan); 667 668 uap->dmacr |= UART011_TXDMAE; 669 pl011_write(uap->dmacr, uap, REG_DMACR); 670 uap->dmatx.queued = true; 671 672 /* 673 * Now we know that DMA will fire, so advance the ring buffer 674 * with the stuff we just dispatched. 675 */ 676 uart_xmit_advance(&uap->port, count); 677 678 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 679 uart_write_wakeup(&uap->port); 680 681 return 1; 682 } 683 684 /* 685 * We received a transmit interrupt without a pending X-char but with 686 * pending characters. 687 * Locking: called with port lock held and IRQs disabled. 688 * Returns: 689 * false if we want to use PIO to transmit 690 * true if we queued a DMA buffer 691 */ 692 static bool pl011_dma_tx_irq(struct uart_amba_port *uap) 693 { 694 if (!uap->using_tx_dma) 695 return false; 696 697 /* 698 * If we already have a TX buffer queued, but received a 699 * TX interrupt, it will be because we've just sent an X-char. 700 * Ensure the TX DMA is enabled and the TX IRQ is disabled. 701 */ 702 if (uap->dmatx.queued) { 703 uap->dmacr |= UART011_TXDMAE; 704 pl011_write(uap->dmacr, uap, REG_DMACR); 705 uap->im &= ~UART011_TXIM; 706 pl011_write(uap->im, uap, REG_IMSC); 707 return true; 708 } 709 710 /* 711 * We don't have a TX buffer queued, so try to queue one. 712 * If we successfully queued a buffer, mask the TX IRQ. 713 */ 714 if (pl011_dma_tx_refill(uap) > 0) { 715 uap->im &= ~UART011_TXIM; 716 pl011_write(uap->im, uap, REG_IMSC); 717 return true; 718 } 719 return false; 720 } 721 722 /* 723 * Stop the DMA transmit (eg, due to received XOFF). 724 * Locking: called with port lock held and IRQs disabled. 725 */ 726 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 727 { 728 if (uap->dmatx.queued) { 729 uap->dmacr &= ~UART011_TXDMAE; 730 pl011_write(uap->dmacr, uap, REG_DMACR); 731 } 732 } 733 734 /* 735 * Try to start a DMA transmit, or in the case of an XON/OFF 736 * character queued for send, try to get that character out ASAP. 737 * Locking: called with port lock held and IRQs disabled. 738 * Returns: 739 * false if we want the TX IRQ to be enabled 740 * true if we have a buffer queued 741 */ 742 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 743 { 744 u16 dmacr; 745 746 if (!uap->using_tx_dma) 747 return false; 748 749 if (!uap->port.x_char) { 750 /* no X-char, try to push chars out in DMA mode */ 751 bool ret = true; 752 753 if (!uap->dmatx.queued) { 754 if (pl011_dma_tx_refill(uap) > 0) { 755 uap->im &= ~UART011_TXIM; 756 pl011_write(uap->im, uap, REG_IMSC); 757 } else 758 ret = false; 759 } else if (!(uap->dmacr & UART011_TXDMAE)) { 760 uap->dmacr |= UART011_TXDMAE; 761 pl011_write(uap->dmacr, uap, REG_DMACR); 762 } 763 return ret; 764 } 765 766 /* 767 * We have an X-char to send. Disable DMA to prevent it loading 768 * the TX fifo, and then see if we can stuff it into the FIFO. 769 */ 770 dmacr = uap->dmacr; 771 uap->dmacr &= ~UART011_TXDMAE; 772 pl011_write(uap->dmacr, uap, REG_DMACR); 773 774 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { 775 /* 776 * No space in the FIFO, so enable the transmit interrupt 777 * so we know when there is space. Note that once we've 778 * loaded the character, we should just re-enable DMA. 779 */ 780 return false; 781 } 782 783 pl011_write(uap->port.x_char, uap, REG_DR); 784 uap->port.icount.tx++; 785 uap->port.x_char = 0; 786 787 /* Success - restore the DMA state */ 788 uap->dmacr = dmacr; 789 pl011_write(dmacr, uap, REG_DMACR); 790 791 return true; 792 } 793 794 /* 795 * Flush the transmit buffer. 796 * Locking: called with port lock held and IRQs disabled. 797 */ 798 static void pl011_dma_flush_buffer(struct uart_port *port) 799 __releases(&uap->port.lock) 800 __acquires(&uap->port.lock) 801 { 802 struct uart_amba_port *uap = 803 container_of(port, struct uart_amba_port, port); 804 805 if (!uap->using_tx_dma) 806 return; 807 808 dmaengine_terminate_async(uap->dmatx.chan); 809 810 if (uap->dmatx.queued) { 811 dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma, 812 uap->dmatx.len, DMA_TO_DEVICE); 813 uap->dmatx.queued = false; 814 uap->dmacr &= ~UART011_TXDMAE; 815 pl011_write(uap->dmacr, uap, REG_DMACR); 816 } 817 } 818 819 static void pl011_dma_rx_callback(void *data); 820 821 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 822 { 823 struct dma_chan *rxchan = uap->dmarx.chan; 824 struct pl011_dmarx_data *dmarx = &uap->dmarx; 825 struct dma_async_tx_descriptor *desc; 826 struct pl011_dmabuf *dbuf; 827 828 if (!rxchan) 829 return -EIO; 830 831 /* Start the RX DMA job */ 832 dbuf = uap->dmarx.use_buf_b ? 833 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; 834 desc = dmaengine_prep_slave_single(rxchan, dbuf->dma, dbuf->len, 835 DMA_DEV_TO_MEM, 836 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 837 /* 838 * If the DMA engine is busy and cannot prepare a 839 * channel, no big deal, the driver will fall back 840 * to interrupt mode as a result of this error code. 841 */ 842 if (!desc) { 843 uap->dmarx.running = false; 844 dmaengine_terminate_all(rxchan); 845 return -EBUSY; 846 } 847 848 /* Some data to go along to the callback */ 849 desc->callback = pl011_dma_rx_callback; 850 desc->callback_param = uap; 851 dmarx->cookie = dmaengine_submit(desc); 852 dma_async_issue_pending(rxchan); 853 854 uap->dmacr |= UART011_RXDMAE; 855 pl011_write(uap->dmacr, uap, REG_DMACR); 856 uap->dmarx.running = true; 857 858 uap->im &= ~UART011_RXIM; 859 pl011_write(uap->im, uap, REG_IMSC); 860 861 return 0; 862 } 863 864 /* 865 * This is called when either the DMA job is complete, or 866 * the FIFO timeout interrupt occurred. This must be called 867 * with the port spinlock uap->port.lock held. 868 */ 869 static void pl011_dma_rx_chars(struct uart_amba_port *uap, 870 u32 pending, bool use_buf_b, 871 bool readfifo) 872 { 873 struct tty_port *port = &uap->port.state->port; 874 struct pl011_dmabuf *dbuf = use_buf_b ? 875 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; 876 int dma_count = 0; 877 u32 fifotaken = 0; /* only used for vdbg() */ 878 879 struct pl011_dmarx_data *dmarx = &uap->dmarx; 880 int dmataken = 0; 881 882 if (uap->dmarx.poll_rate) { 883 /* The data can be taken by polling */ 884 dmataken = dbuf->len - dmarx->last_residue; 885 /* Recalculate the pending size */ 886 if (pending >= dmataken) 887 pending -= dmataken; 888 } 889 890 /* Pick the remain data from the DMA */ 891 if (pending) { 892 893 /* 894 * First take all chars in the DMA pipe, then look in the FIFO. 895 * Note that tty_insert_flip_buf() tries to take as many chars 896 * as it can. 897 */ 898 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, 899 pending); 900 901 uap->port.icount.rx += dma_count; 902 if (dma_count < pending) 903 dev_warn(uap->port.dev, 904 "couldn't insert all characters (TTY is full?)\n"); 905 } 906 907 /* Reset the last_residue for Rx DMA poll */ 908 if (uap->dmarx.poll_rate) 909 dmarx->last_residue = dbuf->len; 910 911 /* 912 * Only continue with trying to read the FIFO if all DMA chars have 913 * been taken first. 914 */ 915 if (dma_count == pending && readfifo) { 916 /* Clear any error flags */ 917 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 918 UART011_FEIS, uap, REG_ICR); 919 920 /* 921 * If we read all the DMA'd characters, and we had an 922 * incomplete buffer, that could be due to an rx error, or 923 * maybe we just timed out. Read any pending chars and check 924 * the error status. 925 * 926 * Error conditions will only occur in the FIFO, these will 927 * trigger an immediate interrupt and stop the DMA job, so we 928 * will always find the error in the FIFO, never in the DMA 929 * buffer. 930 */ 931 fifotaken = pl011_fifo_to_tty(uap); 932 } 933 934 dev_vdbg(uap->port.dev, 935 "Took %d chars from DMA buffer and %d chars from the FIFO\n", 936 dma_count, fifotaken); 937 tty_flip_buffer_push(port); 938 } 939 940 static void pl011_dma_rx_irq(struct uart_amba_port *uap) 941 { 942 struct pl011_dmarx_data *dmarx = &uap->dmarx; 943 struct dma_chan *rxchan = dmarx->chan; 944 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ? 945 &dmarx->dbuf_b : &dmarx->dbuf_a; 946 size_t pending; 947 struct dma_tx_state state; 948 enum dma_status dmastat; 949 950 /* 951 * Pause the transfer so we can trust the current counter, 952 * do this before we pause the PL011 block, else we may 953 * overflow the FIFO. 954 */ 955 if (dmaengine_pause(rxchan)) 956 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 957 dmastat = rxchan->device->device_tx_status(rxchan, 958 dmarx->cookie, &state); 959 if (dmastat != DMA_PAUSED) 960 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 961 962 /* Disable RX DMA - incoming data will wait in the FIFO */ 963 uap->dmacr &= ~UART011_RXDMAE; 964 pl011_write(uap->dmacr, uap, REG_DMACR); 965 uap->dmarx.running = false; 966 967 pending = dbuf->len - state.residue; 968 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 969 /* Then we terminate the transfer - we now know our residue */ 970 dmaengine_terminate_all(rxchan); 971 972 /* 973 * This will take the chars we have so far and insert 974 * into the framework. 975 */ 976 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); 977 978 /* Switch buffer & re-trigger DMA job */ 979 dmarx->use_buf_b = !dmarx->use_buf_b; 980 if (pl011_dma_rx_trigger_dma(uap)) { 981 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 982 "fall back to interrupt mode\n"); 983 uap->im |= UART011_RXIM; 984 pl011_write(uap->im, uap, REG_IMSC); 985 } 986 } 987 988 static void pl011_dma_rx_callback(void *data) 989 { 990 struct uart_amba_port *uap = data; 991 struct pl011_dmarx_data *dmarx = &uap->dmarx; 992 struct dma_chan *rxchan = dmarx->chan; 993 bool lastbuf = dmarx->use_buf_b; 994 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ? 995 &dmarx->dbuf_b : &dmarx->dbuf_a; 996 size_t pending; 997 struct dma_tx_state state; 998 int ret; 999 1000 /* 1001 * This completion interrupt occurs typically when the 1002 * RX buffer is totally stuffed but no timeout has yet 1003 * occurred. When that happens, we just want the RX 1004 * routine to flush out the secondary DMA buffer while 1005 * we immediately trigger the next DMA job. 1006 */ 1007 uart_port_lock_irq(&uap->port); 1008 /* 1009 * Rx data can be taken by the UART interrupts during 1010 * the DMA irq handler. So we check the residue here. 1011 */ 1012 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1013 pending = dbuf->len - state.residue; 1014 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 1015 /* Then we terminate the transfer - we now know our residue */ 1016 dmaengine_terminate_all(rxchan); 1017 1018 uap->dmarx.running = false; 1019 dmarx->use_buf_b = !lastbuf; 1020 ret = pl011_dma_rx_trigger_dma(uap); 1021 1022 pl011_dma_rx_chars(uap, pending, lastbuf, false); 1023 uart_port_unlock_irq(&uap->port); 1024 /* 1025 * Do this check after we picked the DMA chars so we don't 1026 * get some IRQ immediately from RX. 1027 */ 1028 if (ret) { 1029 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 1030 "fall back to interrupt mode\n"); 1031 uap->im |= UART011_RXIM; 1032 pl011_write(uap->im, uap, REG_IMSC); 1033 } 1034 } 1035 1036 /* 1037 * Stop accepting received characters, when we're shutting down or 1038 * suspending this port. 1039 * Locking: called with port lock held and IRQs disabled. 1040 */ 1041 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1042 { 1043 if (!uap->using_rx_dma) 1044 return; 1045 1046 /* FIXME. Just disable the DMA enable */ 1047 uap->dmacr &= ~UART011_RXDMAE; 1048 pl011_write(uap->dmacr, uap, REG_DMACR); 1049 } 1050 1051 /* 1052 * Timer handler for Rx DMA polling. 1053 * Every polling, It checks the residue in the dma buffer and transfer 1054 * data to the tty. Also, last_residue is updated for the next polling. 1055 */ 1056 static void pl011_dma_rx_poll(struct timer_list *t) 1057 { 1058 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer); 1059 struct tty_port *port = &uap->port.state->port; 1060 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1061 struct dma_chan *rxchan = uap->dmarx.chan; 1062 unsigned long flags; 1063 unsigned int dmataken = 0; 1064 unsigned int size = 0; 1065 struct pl011_dmabuf *dbuf; 1066 int dma_count; 1067 struct dma_tx_state state; 1068 1069 dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; 1070 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1071 if (likely(state.residue < dmarx->last_residue)) { 1072 dmataken = dbuf->len - dmarx->last_residue; 1073 size = dmarx->last_residue - state.residue; 1074 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, 1075 size); 1076 if (dma_count == size) 1077 dmarx->last_residue = state.residue; 1078 dmarx->last_jiffies = jiffies; 1079 } 1080 tty_flip_buffer_push(port); 1081 1082 /* 1083 * If no data is received in poll_timeout, the driver will fall back 1084 * to interrupt mode. We will retrigger DMA at the first interrupt. 1085 */ 1086 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) 1087 > uap->dmarx.poll_timeout) { 1088 1089 uart_port_lock_irqsave(&uap->port, &flags); 1090 pl011_dma_rx_stop(uap); 1091 uap->im |= UART011_RXIM; 1092 pl011_write(uap->im, uap, REG_IMSC); 1093 uart_port_unlock_irqrestore(&uap->port, flags); 1094 1095 uap->dmarx.running = false; 1096 dmaengine_terminate_all(rxchan); 1097 del_timer(&uap->dmarx.timer); 1098 } else { 1099 mod_timer(&uap->dmarx.timer, 1100 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); 1101 } 1102 } 1103 1104 static void pl011_dma_startup(struct uart_amba_port *uap) 1105 { 1106 int ret; 1107 1108 if (!uap->dma_probed) 1109 pl011_dma_probe(uap); 1110 1111 if (!uap->dmatx.chan) 1112 return; 1113 1114 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); 1115 if (!uap->dmatx.buf) { 1116 dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); 1117 uap->port.fifosize = uap->fifosize; 1118 return; 1119 } 1120 1121 uap->dmatx.len = PL011_DMA_BUFFER_SIZE; 1122 1123 /* The DMA buffer is now the FIFO the TTY subsystem can use */ 1124 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; 1125 uap->using_tx_dma = true; 1126 1127 if (!uap->dmarx.chan) 1128 goto skip_rx; 1129 1130 /* Allocate and map DMA RX buffers */ 1131 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a, 1132 DMA_FROM_DEVICE); 1133 if (ret) { 1134 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1135 "RX buffer A", ret); 1136 goto skip_rx; 1137 } 1138 1139 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b, 1140 DMA_FROM_DEVICE); 1141 if (ret) { 1142 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1143 "RX buffer B", ret); 1144 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, 1145 DMA_FROM_DEVICE); 1146 goto skip_rx; 1147 } 1148 1149 uap->using_rx_dma = true; 1150 1151 skip_rx: 1152 /* Turn on DMA error (RX/TX will be enabled on demand) */ 1153 uap->dmacr |= UART011_DMAONERR; 1154 pl011_write(uap->dmacr, uap, REG_DMACR); 1155 1156 /* 1157 * ST Micro variants has some specific dma burst threshold 1158 * compensation. Set this to 16 bytes, so burst will only 1159 * be issued above/below 16 bytes. 1160 */ 1161 if (uap->vendor->dma_threshold) 1162 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, 1163 uap, REG_ST_DMAWM); 1164 1165 if (uap->using_rx_dma) { 1166 if (pl011_dma_rx_trigger_dma(uap)) 1167 dev_dbg(uap->port.dev, "could not trigger initial " 1168 "RX DMA job, fall back to interrupt mode\n"); 1169 if (uap->dmarx.poll_rate) { 1170 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0); 1171 mod_timer(&uap->dmarx.timer, 1172 jiffies + 1173 msecs_to_jiffies(uap->dmarx.poll_rate)); 1174 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1175 uap->dmarx.last_jiffies = jiffies; 1176 } 1177 } 1178 } 1179 1180 static void pl011_dma_shutdown(struct uart_amba_port *uap) 1181 { 1182 if (!(uap->using_tx_dma || uap->using_rx_dma)) 1183 return; 1184 1185 /* Disable RX and TX DMA */ 1186 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) 1187 cpu_relax(); 1188 1189 uart_port_lock_irq(&uap->port); 1190 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); 1191 pl011_write(uap->dmacr, uap, REG_DMACR); 1192 uart_port_unlock_irq(&uap->port); 1193 1194 if (uap->using_tx_dma) { 1195 /* In theory, this should already be done by pl011_dma_flush_buffer */ 1196 dmaengine_terminate_all(uap->dmatx.chan); 1197 if (uap->dmatx.queued) { 1198 dma_unmap_single(uap->dmatx.chan->device->dev, 1199 uap->dmatx.dma, uap->dmatx.len, 1200 DMA_TO_DEVICE); 1201 uap->dmatx.queued = false; 1202 } 1203 1204 kfree(uap->dmatx.buf); 1205 uap->using_tx_dma = false; 1206 } 1207 1208 if (uap->using_rx_dma) { 1209 dmaengine_terminate_all(uap->dmarx.chan); 1210 /* Clean up the RX DMA */ 1211 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE); 1212 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE); 1213 if (uap->dmarx.poll_rate) 1214 del_timer_sync(&uap->dmarx.timer); 1215 uap->using_rx_dma = false; 1216 } 1217 } 1218 1219 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1220 { 1221 return uap->using_rx_dma; 1222 } 1223 1224 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1225 { 1226 return uap->using_rx_dma && uap->dmarx.running; 1227 } 1228 1229 #else 1230 /* Blank functions if the DMA engine is not available */ 1231 static inline void pl011_dma_remove(struct uart_amba_port *uap) 1232 { 1233 } 1234 1235 static inline void pl011_dma_startup(struct uart_amba_port *uap) 1236 { 1237 } 1238 1239 static inline void pl011_dma_shutdown(struct uart_amba_port *uap) 1240 { 1241 } 1242 1243 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) 1244 { 1245 return false; 1246 } 1247 1248 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 1249 { 1250 } 1251 1252 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 1253 { 1254 return false; 1255 } 1256 1257 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) 1258 { 1259 } 1260 1261 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1262 { 1263 } 1264 1265 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 1266 { 1267 return -EIO; 1268 } 1269 1270 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1271 { 1272 return false; 1273 } 1274 1275 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1276 { 1277 return false; 1278 } 1279 1280 #define pl011_dma_flush_buffer NULL 1281 #endif 1282 1283 static void pl011_rs485_tx_stop(struct uart_amba_port *uap) 1284 { 1285 /* 1286 * To be on the safe side only time out after twice as many iterations 1287 * as fifo size. 1288 */ 1289 const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2; 1290 struct uart_port *port = &uap->port; 1291 int i = 0; 1292 u32 cr; 1293 1294 /* Wait until hardware tx queue is empty */ 1295 while (!pl011_tx_empty(port)) { 1296 if (i > MAX_TX_DRAIN_ITERS) { 1297 dev_warn(port->dev, 1298 "timeout while draining hardware tx queue\n"); 1299 break; 1300 } 1301 1302 udelay(uap->rs485_tx_drain_interval); 1303 i++; 1304 } 1305 1306 if (port->rs485.delay_rts_after_send) 1307 mdelay(port->rs485.delay_rts_after_send); 1308 1309 cr = pl011_read(uap, REG_CR); 1310 1311 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 1312 cr &= ~UART011_CR_RTS; 1313 else 1314 cr |= UART011_CR_RTS; 1315 1316 /* Disable the transmitter and reenable the transceiver */ 1317 cr &= ~UART011_CR_TXE; 1318 cr |= UART011_CR_RXE; 1319 pl011_write(cr, uap, REG_CR); 1320 1321 uap->rs485_tx_started = false; 1322 } 1323 1324 static void pl011_stop_tx(struct uart_port *port) 1325 { 1326 struct uart_amba_port *uap = 1327 container_of(port, struct uart_amba_port, port); 1328 1329 uap->im &= ~UART011_TXIM; 1330 pl011_write(uap->im, uap, REG_IMSC); 1331 pl011_dma_tx_stop(uap); 1332 1333 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) 1334 pl011_rs485_tx_stop(uap); 1335 } 1336 1337 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); 1338 1339 /* Start TX with programmed I/O only (no DMA) */ 1340 static void pl011_start_tx_pio(struct uart_amba_port *uap) 1341 { 1342 if (pl011_tx_chars(uap, false)) { 1343 uap->im |= UART011_TXIM; 1344 pl011_write(uap->im, uap, REG_IMSC); 1345 } 1346 } 1347 1348 static void pl011_rs485_tx_start(struct uart_amba_port *uap) 1349 { 1350 struct uart_port *port = &uap->port; 1351 u32 cr; 1352 1353 /* Enable transmitter */ 1354 cr = pl011_read(uap, REG_CR); 1355 cr |= UART011_CR_TXE; 1356 1357 /* Disable receiver if half-duplex */ 1358 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1359 cr &= ~UART011_CR_RXE; 1360 1361 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 1362 cr &= ~UART011_CR_RTS; 1363 else 1364 cr |= UART011_CR_RTS; 1365 1366 pl011_write(cr, uap, REG_CR); 1367 1368 if (port->rs485.delay_rts_before_send) 1369 mdelay(port->rs485.delay_rts_before_send); 1370 1371 uap->rs485_tx_started = true; 1372 } 1373 1374 static void pl011_start_tx(struct uart_port *port) 1375 { 1376 struct uart_amba_port *uap = 1377 container_of(port, struct uart_amba_port, port); 1378 1379 if ((uap->port.rs485.flags & SER_RS485_ENABLED) && 1380 !uap->rs485_tx_started) 1381 pl011_rs485_tx_start(uap); 1382 1383 if (!pl011_dma_tx_start(uap)) 1384 pl011_start_tx_pio(uap); 1385 } 1386 1387 static void pl011_stop_rx(struct uart_port *port) 1388 { 1389 struct uart_amba_port *uap = 1390 container_of(port, struct uart_amba_port, port); 1391 1392 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| 1393 UART011_PEIM|UART011_BEIM|UART011_OEIM); 1394 pl011_write(uap->im, uap, REG_IMSC); 1395 1396 pl011_dma_rx_stop(uap); 1397 } 1398 1399 static void pl011_throttle_rx(struct uart_port *port) 1400 { 1401 unsigned long flags; 1402 1403 uart_port_lock_irqsave(port, &flags); 1404 pl011_stop_rx(port); 1405 uart_port_unlock_irqrestore(port, flags); 1406 } 1407 1408 static void pl011_enable_ms(struct uart_port *port) 1409 { 1410 struct uart_amba_port *uap = 1411 container_of(port, struct uart_amba_port, port); 1412 1413 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; 1414 pl011_write(uap->im, uap, REG_IMSC); 1415 } 1416 1417 static void pl011_rx_chars(struct uart_amba_port *uap) 1418 __releases(&uap->port.lock) 1419 __acquires(&uap->port.lock) 1420 { 1421 pl011_fifo_to_tty(uap); 1422 1423 uart_port_unlock(&uap->port); 1424 tty_flip_buffer_push(&uap->port.state->port); 1425 /* 1426 * If we were temporarily out of DMA mode for a while, 1427 * attempt to switch back to DMA mode again. 1428 */ 1429 if (pl011_dma_rx_available(uap)) { 1430 if (pl011_dma_rx_trigger_dma(uap)) { 1431 dev_dbg(uap->port.dev, "could not trigger RX DMA job " 1432 "fall back to interrupt mode again\n"); 1433 uap->im |= UART011_RXIM; 1434 pl011_write(uap->im, uap, REG_IMSC); 1435 } else { 1436 #ifdef CONFIG_DMA_ENGINE 1437 /* Start Rx DMA poll */ 1438 if (uap->dmarx.poll_rate) { 1439 uap->dmarx.last_jiffies = jiffies; 1440 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1441 mod_timer(&uap->dmarx.timer, 1442 jiffies + 1443 msecs_to_jiffies(uap->dmarx.poll_rate)); 1444 } 1445 #endif 1446 } 1447 } 1448 uart_port_lock(&uap->port); 1449 } 1450 1451 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, 1452 bool from_irq) 1453 { 1454 if (unlikely(!from_irq) && 1455 pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1456 return false; /* unable to transmit character */ 1457 1458 pl011_write(c, uap, REG_DR); 1459 uap->port.icount.tx++; 1460 1461 return true; 1462 } 1463 1464 /* Returns true if tx interrupts have to be (kept) enabled */ 1465 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) 1466 { 1467 struct circ_buf *xmit = &uap->port.state->xmit; 1468 int count = uap->fifosize >> 1; 1469 1470 if (uap->port.x_char) { 1471 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) 1472 return true; 1473 uap->port.x_char = 0; 1474 --count; 1475 } 1476 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { 1477 pl011_stop_tx(&uap->port); 1478 return false; 1479 } 1480 1481 /* If we are using DMA mode, try to send some characters. */ 1482 if (pl011_dma_tx_irq(uap)) 1483 return true; 1484 1485 do { 1486 if (likely(from_irq) && count-- == 0) 1487 break; 1488 1489 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) 1490 break; 1491 1492 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1493 } while (!uart_circ_empty(xmit)); 1494 1495 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1496 uart_write_wakeup(&uap->port); 1497 1498 if (uart_circ_empty(xmit)) { 1499 pl011_stop_tx(&uap->port); 1500 return false; 1501 } 1502 return true; 1503 } 1504 1505 static void pl011_modem_status(struct uart_amba_port *uap) 1506 { 1507 unsigned int status, delta; 1508 1509 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1510 1511 delta = status ^ uap->old_status; 1512 uap->old_status = status; 1513 1514 if (!delta) 1515 return; 1516 1517 if (delta & UART01x_FR_DCD) 1518 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 1519 1520 if (delta & uap->vendor->fr_dsr) 1521 uap->port.icount.dsr++; 1522 1523 if (delta & uap->vendor->fr_cts) 1524 uart_handle_cts_change(&uap->port, 1525 status & uap->vendor->fr_cts); 1526 1527 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 1528 } 1529 1530 static void check_apply_cts_event_workaround(struct uart_amba_port *uap) 1531 { 1532 if (!uap->vendor->cts_event_workaround) 1533 return; 1534 1535 /* workaround to make sure that all bits are unlocked.. */ 1536 pl011_write(0x00, uap, REG_ICR); 1537 1538 /* 1539 * WA: introduce 26ns(1 uart clk) delay before W1C; 1540 * single apb access will incur 2 pclk(133.12Mhz) delay, 1541 * so add 2 dummy reads 1542 */ 1543 pl011_read(uap, REG_ICR); 1544 pl011_read(uap, REG_ICR); 1545 } 1546 1547 static irqreturn_t pl011_int(int irq, void *dev_id) 1548 { 1549 struct uart_amba_port *uap = dev_id; 1550 unsigned long flags; 1551 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 1552 int handled = 0; 1553 1554 uart_port_lock_irqsave(&uap->port, &flags); 1555 status = pl011_read(uap, REG_RIS) & uap->im; 1556 if (status) { 1557 do { 1558 check_apply_cts_event_workaround(uap); 1559 1560 pl011_write(status & ~(UART011_TXIS|UART011_RTIS| 1561 UART011_RXIS), 1562 uap, REG_ICR); 1563 1564 if (status & (UART011_RTIS|UART011_RXIS)) { 1565 if (pl011_dma_rx_running(uap)) 1566 pl011_dma_rx_irq(uap); 1567 else 1568 pl011_rx_chars(uap); 1569 } 1570 if (status & (UART011_DSRMIS|UART011_DCDMIS| 1571 UART011_CTSMIS|UART011_RIMIS)) 1572 pl011_modem_status(uap); 1573 if (status & UART011_TXIS) 1574 pl011_tx_chars(uap, true); 1575 1576 if (pass_counter-- == 0) 1577 break; 1578 1579 status = pl011_read(uap, REG_RIS) & uap->im; 1580 } while (status != 0); 1581 handled = 1; 1582 } 1583 1584 uart_port_unlock_irqrestore(&uap->port, flags); 1585 1586 return IRQ_RETVAL(handled); 1587 } 1588 1589 static unsigned int pl011_tx_empty(struct uart_port *port) 1590 { 1591 struct uart_amba_port *uap = 1592 container_of(port, struct uart_amba_port, port); 1593 1594 /* Allow feature register bits to be inverted to work around errata */ 1595 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; 1596 1597 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? 1598 0 : TIOCSER_TEMT; 1599 } 1600 1601 static unsigned int pl011_get_mctrl(struct uart_port *port) 1602 { 1603 struct uart_amba_port *uap = 1604 container_of(port, struct uart_amba_port, port); 1605 unsigned int result = 0; 1606 unsigned int status = pl011_read(uap, REG_FR); 1607 1608 #define TIOCMBIT(uartbit, tiocmbit) \ 1609 if (status & uartbit) \ 1610 result |= tiocmbit 1611 1612 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); 1613 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR); 1614 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS); 1615 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG); 1616 #undef TIOCMBIT 1617 return result; 1618 } 1619 1620 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) 1621 { 1622 struct uart_amba_port *uap = 1623 container_of(port, struct uart_amba_port, port); 1624 unsigned int cr; 1625 1626 cr = pl011_read(uap, REG_CR); 1627 1628 #define TIOCMBIT(tiocmbit, uartbit) \ 1629 if (mctrl & tiocmbit) \ 1630 cr |= uartbit; \ 1631 else \ 1632 cr &= ~uartbit 1633 1634 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); 1635 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); 1636 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); 1637 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); 1638 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); 1639 1640 if (port->status & UPSTAT_AUTORTS) { 1641 /* We need to disable auto-RTS if we want to turn RTS off */ 1642 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); 1643 } 1644 #undef TIOCMBIT 1645 1646 pl011_write(cr, uap, REG_CR); 1647 } 1648 1649 static void pl011_break_ctl(struct uart_port *port, int break_state) 1650 { 1651 struct uart_amba_port *uap = 1652 container_of(port, struct uart_amba_port, port); 1653 unsigned long flags; 1654 unsigned int lcr_h; 1655 1656 uart_port_lock_irqsave(&uap->port, &flags); 1657 lcr_h = pl011_read(uap, REG_LCRH_TX); 1658 if (break_state == -1) 1659 lcr_h |= UART01x_LCRH_BRK; 1660 else 1661 lcr_h &= ~UART01x_LCRH_BRK; 1662 pl011_write(lcr_h, uap, REG_LCRH_TX); 1663 uart_port_unlock_irqrestore(&uap->port, flags); 1664 } 1665 1666 #ifdef CONFIG_CONSOLE_POLL 1667 1668 static void pl011_quiesce_irqs(struct uart_port *port) 1669 { 1670 struct uart_amba_port *uap = 1671 container_of(port, struct uart_amba_port, port); 1672 1673 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); 1674 /* 1675 * There is no way to clear TXIM as this is "ready to transmit IRQ", so 1676 * we simply mask it. start_tx() will unmask it. 1677 * 1678 * Note we can race with start_tx(), and if the race happens, the 1679 * polling user might get another interrupt just after we clear it. 1680 * But it should be OK and can happen even w/o the race, e.g. 1681 * controller immediately got some new data and raised the IRQ. 1682 * 1683 * And whoever uses polling routines assumes that it manages the device 1684 * (including tx queue), so we're also fine with start_tx()'s caller 1685 * side. 1686 */ 1687 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, 1688 REG_IMSC); 1689 } 1690 1691 static int pl011_get_poll_char(struct uart_port *port) 1692 { 1693 struct uart_amba_port *uap = 1694 container_of(port, struct uart_amba_port, port); 1695 unsigned int status; 1696 1697 /* 1698 * The caller might need IRQs lowered, e.g. if used with KDB NMI 1699 * debugger. 1700 */ 1701 pl011_quiesce_irqs(port); 1702 1703 status = pl011_read(uap, REG_FR); 1704 if (status & UART01x_FR_RXFE) 1705 return NO_POLL_CHAR; 1706 1707 return pl011_read(uap, REG_DR); 1708 } 1709 1710 static void pl011_put_poll_char(struct uart_port *port, 1711 unsigned char ch) 1712 { 1713 struct uart_amba_port *uap = 1714 container_of(port, struct uart_amba_port, port); 1715 1716 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1717 cpu_relax(); 1718 1719 pl011_write(ch, uap, REG_DR); 1720 } 1721 1722 #endif /* CONFIG_CONSOLE_POLL */ 1723 1724 static int pl011_hwinit(struct uart_port *port) 1725 { 1726 struct uart_amba_port *uap = 1727 container_of(port, struct uart_amba_port, port); 1728 int retval; 1729 1730 /* Optionaly enable pins to be muxed in and configured */ 1731 pinctrl_pm_select_default_state(port->dev); 1732 1733 /* 1734 * Try to enable the clock producer. 1735 */ 1736 retval = clk_prepare_enable(uap->clk); 1737 if (retval) 1738 return retval; 1739 1740 uap->port.uartclk = clk_get_rate(uap->clk); 1741 1742 /* Clear pending error and receive interrupts */ 1743 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 1744 UART011_FEIS | UART011_RTIS | UART011_RXIS, 1745 uap, REG_ICR); 1746 1747 /* 1748 * Save interrupts enable mask, and enable RX interrupts in case if 1749 * the interrupt is used for NMI entry. 1750 */ 1751 uap->im = pl011_read(uap, REG_IMSC); 1752 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); 1753 1754 if (dev_get_platdata(uap->port.dev)) { 1755 struct amba_pl011_data *plat; 1756 1757 plat = dev_get_platdata(uap->port.dev); 1758 if (plat->init) 1759 plat->init(); 1760 } 1761 return 0; 1762 } 1763 1764 static bool pl011_split_lcrh(const struct uart_amba_port *uap) 1765 { 1766 return pl011_reg_to_offset(uap, REG_LCRH_RX) != 1767 pl011_reg_to_offset(uap, REG_LCRH_TX); 1768 } 1769 1770 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) 1771 { 1772 pl011_write(lcr_h, uap, REG_LCRH_RX); 1773 if (pl011_split_lcrh(uap)) { 1774 int i; 1775 /* 1776 * Wait 10 PCLKs before writing LCRH_TX register, 1777 * to get this delay write read only register 10 times 1778 */ 1779 for (i = 0; i < 10; ++i) 1780 pl011_write(0xff, uap, REG_MIS); 1781 pl011_write(lcr_h, uap, REG_LCRH_TX); 1782 } 1783 } 1784 1785 static int pl011_allocate_irq(struct uart_amba_port *uap) 1786 { 1787 pl011_write(uap->im, uap, REG_IMSC); 1788 1789 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); 1790 } 1791 1792 /* 1793 * Enable interrupts, only timeouts when using DMA 1794 * if initial RX DMA job failed, start in interrupt mode 1795 * as well. 1796 */ 1797 static void pl011_enable_interrupts(struct uart_amba_port *uap) 1798 { 1799 unsigned long flags; 1800 unsigned int i; 1801 1802 uart_port_lock_irqsave(&uap->port, &flags); 1803 1804 /* Clear out any spuriously appearing RX interrupts */ 1805 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); 1806 1807 /* 1808 * RXIS is asserted only when the RX FIFO transitions from below 1809 * to above the trigger threshold. If the RX FIFO is already 1810 * full to the threshold this can't happen and RXIS will now be 1811 * stuck off. Drain the RX FIFO explicitly to fix this: 1812 */ 1813 for (i = 0; i < uap->fifosize * 2; ++i) { 1814 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE) 1815 break; 1816 1817 pl011_read(uap, REG_DR); 1818 } 1819 1820 uap->im = UART011_RTIM; 1821 if (!pl011_dma_rx_running(uap)) 1822 uap->im |= UART011_RXIM; 1823 pl011_write(uap->im, uap, REG_IMSC); 1824 uart_port_unlock_irqrestore(&uap->port, flags); 1825 } 1826 1827 static void pl011_unthrottle_rx(struct uart_port *port) 1828 { 1829 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port); 1830 unsigned long flags; 1831 1832 uart_port_lock_irqsave(&uap->port, &flags); 1833 1834 uap->im = UART011_RTIM; 1835 if (!pl011_dma_rx_running(uap)) 1836 uap->im |= UART011_RXIM; 1837 1838 pl011_write(uap->im, uap, REG_IMSC); 1839 1840 if (uap->using_rx_dma) { 1841 uap->dmacr |= UART011_RXDMAE; 1842 pl011_write(uap->dmacr, uap, REG_DMACR); 1843 } 1844 1845 uart_port_unlock_irqrestore(&uap->port, flags); 1846 } 1847 1848 static int pl011_startup(struct uart_port *port) 1849 { 1850 struct uart_amba_port *uap = 1851 container_of(port, struct uart_amba_port, port); 1852 unsigned int cr; 1853 int retval; 1854 1855 retval = pl011_hwinit(port); 1856 if (retval) 1857 goto clk_dis; 1858 1859 retval = pl011_allocate_irq(uap); 1860 if (retval) 1861 goto clk_dis; 1862 1863 pl011_write(uap->vendor->ifls, uap, REG_IFLS); 1864 1865 uart_port_lock_irq(&uap->port); 1866 1867 cr = pl011_read(uap, REG_CR); 1868 cr &= UART011_CR_RTS | UART011_CR_DTR; 1869 cr |= UART01x_CR_UARTEN | UART011_CR_RXE; 1870 1871 if (!(port->rs485.flags & SER_RS485_ENABLED)) 1872 cr |= UART011_CR_TXE; 1873 1874 pl011_write(cr, uap, REG_CR); 1875 1876 uart_port_unlock_irq(&uap->port); 1877 1878 /* 1879 * initialise the old status of the modem signals 1880 */ 1881 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1882 1883 /* Startup DMA */ 1884 pl011_dma_startup(uap); 1885 1886 pl011_enable_interrupts(uap); 1887 1888 return 0; 1889 1890 clk_dis: 1891 clk_disable_unprepare(uap->clk); 1892 return retval; 1893 } 1894 1895 static int sbsa_uart_startup(struct uart_port *port) 1896 { 1897 struct uart_amba_port *uap = 1898 container_of(port, struct uart_amba_port, port); 1899 int retval; 1900 1901 retval = pl011_hwinit(port); 1902 if (retval) 1903 return retval; 1904 1905 retval = pl011_allocate_irq(uap); 1906 if (retval) 1907 return retval; 1908 1909 /* The SBSA UART does not support any modem status lines. */ 1910 uap->old_status = 0; 1911 1912 pl011_enable_interrupts(uap); 1913 1914 return 0; 1915 } 1916 1917 static void pl011_shutdown_channel(struct uart_amba_port *uap, 1918 unsigned int lcrh) 1919 { 1920 unsigned long val; 1921 1922 val = pl011_read(uap, lcrh); 1923 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); 1924 pl011_write(val, uap, lcrh); 1925 } 1926 1927 /* 1928 * disable the port. It should not disable RTS and DTR. 1929 * Also RTS and DTR state should be preserved to restore 1930 * it during startup(). 1931 */ 1932 static void pl011_disable_uart(struct uart_amba_port *uap) 1933 { 1934 unsigned int cr; 1935 1936 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1937 uart_port_lock_irq(&uap->port); 1938 cr = pl011_read(uap, REG_CR); 1939 cr &= UART011_CR_RTS | UART011_CR_DTR; 1940 cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 1941 pl011_write(cr, uap, REG_CR); 1942 uart_port_unlock_irq(&uap->port); 1943 1944 /* 1945 * disable break condition and fifos 1946 */ 1947 pl011_shutdown_channel(uap, REG_LCRH_RX); 1948 if (pl011_split_lcrh(uap)) 1949 pl011_shutdown_channel(uap, REG_LCRH_TX); 1950 } 1951 1952 static void pl011_disable_interrupts(struct uart_amba_port *uap) 1953 { 1954 uart_port_lock_irq(&uap->port); 1955 1956 /* mask all interrupts and clear all pending ones */ 1957 uap->im = 0; 1958 pl011_write(uap->im, uap, REG_IMSC); 1959 pl011_write(0xffff, uap, REG_ICR); 1960 1961 uart_port_unlock_irq(&uap->port); 1962 } 1963 1964 static void pl011_shutdown(struct uart_port *port) 1965 { 1966 struct uart_amba_port *uap = 1967 container_of(port, struct uart_amba_port, port); 1968 1969 pl011_disable_interrupts(uap); 1970 1971 pl011_dma_shutdown(uap); 1972 1973 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) 1974 pl011_rs485_tx_stop(uap); 1975 1976 free_irq(uap->port.irq, uap); 1977 1978 pl011_disable_uart(uap); 1979 1980 /* 1981 * Shut down the clock producer 1982 */ 1983 clk_disable_unprepare(uap->clk); 1984 /* Optionally let pins go into sleep states */ 1985 pinctrl_pm_select_sleep_state(port->dev); 1986 1987 if (dev_get_platdata(uap->port.dev)) { 1988 struct amba_pl011_data *plat; 1989 1990 plat = dev_get_platdata(uap->port.dev); 1991 if (plat->exit) 1992 plat->exit(); 1993 } 1994 1995 if (uap->port.ops->flush_buffer) 1996 uap->port.ops->flush_buffer(port); 1997 } 1998 1999 static void sbsa_uart_shutdown(struct uart_port *port) 2000 { 2001 struct uart_amba_port *uap = 2002 container_of(port, struct uart_amba_port, port); 2003 2004 pl011_disable_interrupts(uap); 2005 2006 free_irq(uap->port.irq, uap); 2007 2008 if (uap->port.ops->flush_buffer) 2009 uap->port.ops->flush_buffer(port); 2010 } 2011 2012 static void 2013 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) 2014 { 2015 port->read_status_mask = UART011_DR_OE | 255; 2016 if (termios->c_iflag & INPCK) 2017 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; 2018 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2019 port->read_status_mask |= UART011_DR_BE; 2020 2021 /* 2022 * Characters to ignore 2023 */ 2024 port->ignore_status_mask = 0; 2025 if (termios->c_iflag & IGNPAR) 2026 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; 2027 if (termios->c_iflag & IGNBRK) { 2028 port->ignore_status_mask |= UART011_DR_BE; 2029 /* 2030 * If we're ignoring parity and break indicators, 2031 * ignore overruns too (for real raw support). 2032 */ 2033 if (termios->c_iflag & IGNPAR) 2034 port->ignore_status_mask |= UART011_DR_OE; 2035 } 2036 2037 /* 2038 * Ignore all characters if CREAD is not set. 2039 */ 2040 if ((termios->c_cflag & CREAD) == 0) 2041 port->ignore_status_mask |= UART_DUMMY_DR_RX; 2042 } 2043 2044 static void 2045 pl011_set_termios(struct uart_port *port, struct ktermios *termios, 2046 const struct ktermios *old) 2047 { 2048 struct uart_amba_port *uap = 2049 container_of(port, struct uart_amba_port, port); 2050 unsigned int lcr_h, old_cr; 2051 unsigned long flags; 2052 unsigned int baud, quot, clkdiv; 2053 unsigned int bits; 2054 2055 if (uap->vendor->oversampling) 2056 clkdiv = 8; 2057 else 2058 clkdiv = 16; 2059 2060 /* 2061 * Ask the core to calculate the divisor for us. 2062 */ 2063 baud = uart_get_baud_rate(port, termios, old, 0, 2064 port->uartclk / clkdiv); 2065 #ifdef CONFIG_DMA_ENGINE 2066 /* 2067 * Adjust RX DMA polling rate with baud rate if not specified. 2068 */ 2069 if (uap->dmarx.auto_poll_rate) 2070 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); 2071 #endif 2072 2073 if (baud > port->uartclk/16) 2074 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); 2075 else 2076 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); 2077 2078 switch (termios->c_cflag & CSIZE) { 2079 case CS5: 2080 lcr_h = UART01x_LCRH_WLEN_5; 2081 break; 2082 case CS6: 2083 lcr_h = UART01x_LCRH_WLEN_6; 2084 break; 2085 case CS7: 2086 lcr_h = UART01x_LCRH_WLEN_7; 2087 break; 2088 default: // CS8 2089 lcr_h = UART01x_LCRH_WLEN_8; 2090 break; 2091 } 2092 if (termios->c_cflag & CSTOPB) 2093 lcr_h |= UART01x_LCRH_STP2; 2094 if (termios->c_cflag & PARENB) { 2095 lcr_h |= UART01x_LCRH_PEN; 2096 if (!(termios->c_cflag & PARODD)) 2097 lcr_h |= UART01x_LCRH_EPS; 2098 if (termios->c_cflag & CMSPAR) 2099 lcr_h |= UART011_LCRH_SPS; 2100 } 2101 if (uap->fifosize > 1) 2102 lcr_h |= UART01x_LCRH_FEN; 2103 2104 bits = tty_get_frame_size(termios->c_cflag); 2105 2106 uart_port_lock_irqsave(port, &flags); 2107 2108 /* 2109 * Update the per-port timeout. 2110 */ 2111 uart_update_timeout(port, termios->c_cflag, baud); 2112 2113 /* 2114 * Calculate the approximated time it takes to transmit one character 2115 * with the given baud rate. We use this as the poll interval when we 2116 * wait for the tx queue to empty. 2117 */ 2118 uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud); 2119 2120 pl011_setup_status_masks(port, termios); 2121 2122 if (UART_ENABLE_MS(port, termios->c_cflag)) 2123 pl011_enable_ms(port); 2124 2125 if (port->rs485.flags & SER_RS485_ENABLED) 2126 termios->c_cflag &= ~CRTSCTS; 2127 2128 old_cr = pl011_read(uap, REG_CR); 2129 2130 if (termios->c_cflag & CRTSCTS) { 2131 if (old_cr & UART011_CR_RTS) 2132 old_cr |= UART011_CR_RTSEN; 2133 2134 old_cr |= UART011_CR_CTSEN; 2135 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 2136 } else { 2137 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); 2138 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 2139 } 2140 2141 if (uap->vendor->oversampling) { 2142 if (baud > port->uartclk / 16) 2143 old_cr |= ST_UART011_CR_OVSFACT; 2144 else 2145 old_cr &= ~ST_UART011_CR_OVSFACT; 2146 } 2147 2148 /* 2149 * Workaround for the ST Micro oversampling variants to 2150 * increase the bitrate slightly, by lowering the divisor, 2151 * to avoid delayed sampling of start bit at high speeds, 2152 * else we see data corruption. 2153 */ 2154 if (uap->vendor->oversampling) { 2155 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) 2156 quot -= 1; 2157 else if ((baud > 3250000) && (quot > 2)) 2158 quot -= 2; 2159 } 2160 /* Set baud rate */ 2161 pl011_write(quot & 0x3f, uap, REG_FBRD); 2162 pl011_write(quot >> 6, uap, REG_IBRD); 2163 2164 /* 2165 * ----------v----------v----------v----------v----- 2166 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER 2167 * REG_FBRD & REG_IBRD. 2168 * ----------^----------^----------^----------^----- 2169 */ 2170 pl011_write_lcr_h(uap, lcr_h); 2171 2172 /* 2173 * Receive was disabled by pl011_disable_uart during shutdown. 2174 * Need to reenable receive if you need to use a tty_driver 2175 * returns from tty_find_polling_driver() after a port shutdown. 2176 */ 2177 old_cr |= UART011_CR_RXE; 2178 pl011_write(old_cr, uap, REG_CR); 2179 2180 uart_port_unlock_irqrestore(port, flags); 2181 } 2182 2183 static void 2184 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, 2185 const struct ktermios *old) 2186 { 2187 struct uart_amba_port *uap = 2188 container_of(port, struct uart_amba_port, port); 2189 unsigned long flags; 2190 2191 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); 2192 2193 /* The SBSA UART only supports 8n1 without hardware flow control. */ 2194 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 2195 termios->c_cflag &= ~(CMSPAR | CRTSCTS); 2196 termios->c_cflag |= CS8 | CLOCAL; 2197 2198 uart_port_lock_irqsave(port, &flags); 2199 uart_update_timeout(port, CS8, uap->fixed_baud); 2200 pl011_setup_status_masks(port, termios); 2201 uart_port_unlock_irqrestore(port, flags); 2202 } 2203 2204 static const char *pl011_type(struct uart_port *port) 2205 { 2206 struct uart_amba_port *uap = 2207 container_of(port, struct uart_amba_port, port); 2208 return uap->port.type == PORT_AMBA ? uap->type : NULL; 2209 } 2210 2211 /* 2212 * Configure/autoconfigure the port. 2213 */ 2214 static void pl011_config_port(struct uart_port *port, int flags) 2215 { 2216 if (flags & UART_CONFIG_TYPE) 2217 port->type = PORT_AMBA; 2218 } 2219 2220 /* 2221 * verify the new serial_struct (for TIOCSSERIAL). 2222 */ 2223 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) 2224 { 2225 int ret = 0; 2226 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 2227 ret = -EINVAL; 2228 if (ser->irq < 0 || ser->irq >= nr_irqs) 2229 ret = -EINVAL; 2230 if (ser->baud_base < 9600) 2231 ret = -EINVAL; 2232 if (port->mapbase != (unsigned long) ser->iomem_base) 2233 ret = -EINVAL; 2234 return ret; 2235 } 2236 2237 static int pl011_rs485_config(struct uart_port *port, struct ktermios *termios, 2238 struct serial_rs485 *rs485) 2239 { 2240 struct uart_amba_port *uap = 2241 container_of(port, struct uart_amba_port, port); 2242 2243 if (port->rs485.flags & SER_RS485_ENABLED) 2244 pl011_rs485_tx_stop(uap); 2245 2246 /* Make sure auto RTS is disabled */ 2247 if (rs485->flags & SER_RS485_ENABLED) { 2248 u32 cr = pl011_read(uap, REG_CR); 2249 2250 cr &= ~UART011_CR_RTSEN; 2251 pl011_write(cr, uap, REG_CR); 2252 port->status &= ~UPSTAT_AUTORTS; 2253 } 2254 2255 return 0; 2256 } 2257 2258 static const struct uart_ops amba_pl011_pops = { 2259 .tx_empty = pl011_tx_empty, 2260 .set_mctrl = pl011_set_mctrl, 2261 .get_mctrl = pl011_get_mctrl, 2262 .stop_tx = pl011_stop_tx, 2263 .start_tx = pl011_start_tx, 2264 .stop_rx = pl011_stop_rx, 2265 .throttle = pl011_throttle_rx, 2266 .unthrottle = pl011_unthrottle_rx, 2267 .enable_ms = pl011_enable_ms, 2268 .break_ctl = pl011_break_ctl, 2269 .startup = pl011_startup, 2270 .shutdown = pl011_shutdown, 2271 .flush_buffer = pl011_dma_flush_buffer, 2272 .set_termios = pl011_set_termios, 2273 .type = pl011_type, 2274 .config_port = pl011_config_port, 2275 .verify_port = pl011_verify_port, 2276 #ifdef CONFIG_CONSOLE_POLL 2277 .poll_init = pl011_hwinit, 2278 .poll_get_char = pl011_get_poll_char, 2279 .poll_put_char = pl011_put_poll_char, 2280 #endif 2281 }; 2282 2283 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 2284 { 2285 } 2286 2287 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) 2288 { 2289 return 0; 2290 } 2291 2292 static const struct uart_ops sbsa_uart_pops = { 2293 .tx_empty = pl011_tx_empty, 2294 .set_mctrl = sbsa_uart_set_mctrl, 2295 .get_mctrl = sbsa_uart_get_mctrl, 2296 .stop_tx = pl011_stop_tx, 2297 .start_tx = pl011_start_tx, 2298 .stop_rx = pl011_stop_rx, 2299 .startup = sbsa_uart_startup, 2300 .shutdown = sbsa_uart_shutdown, 2301 .set_termios = sbsa_uart_set_termios, 2302 .type = pl011_type, 2303 .config_port = pl011_config_port, 2304 .verify_port = pl011_verify_port, 2305 #ifdef CONFIG_CONSOLE_POLL 2306 .poll_init = pl011_hwinit, 2307 .poll_get_char = pl011_get_poll_char, 2308 .poll_put_char = pl011_put_poll_char, 2309 #endif 2310 }; 2311 2312 static struct uart_amba_port *amba_ports[UART_NR]; 2313 2314 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE 2315 2316 static void pl011_console_putchar(struct uart_port *port, unsigned char ch) 2317 { 2318 struct uart_amba_port *uap = 2319 container_of(port, struct uart_amba_port, port); 2320 2321 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 2322 cpu_relax(); 2323 pl011_write(ch, uap, REG_DR); 2324 } 2325 2326 static void 2327 pl011_console_write(struct console *co, const char *s, unsigned int count) 2328 { 2329 struct uart_amba_port *uap = amba_ports[co->index]; 2330 unsigned int old_cr = 0, new_cr; 2331 unsigned long flags; 2332 int locked = 1; 2333 2334 clk_enable(uap->clk); 2335 2336 local_irq_save(flags); 2337 if (uap->port.sysrq) 2338 locked = 0; 2339 else if (oops_in_progress) 2340 locked = uart_port_trylock(&uap->port); 2341 else 2342 uart_port_lock(&uap->port); 2343 2344 /* 2345 * First save the CR then disable the interrupts 2346 */ 2347 if (!uap->vendor->always_enabled) { 2348 old_cr = pl011_read(uap, REG_CR); 2349 new_cr = old_cr & ~UART011_CR_CTSEN; 2350 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 2351 pl011_write(new_cr, uap, REG_CR); 2352 } 2353 2354 uart_console_write(&uap->port, s, count, pl011_console_putchar); 2355 2356 /* 2357 * Finally, wait for transmitter to become empty and restore the 2358 * TCR. Allow feature register bits to be inverted to work around 2359 * errata. 2360 */ 2361 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) 2362 & uap->vendor->fr_busy) 2363 cpu_relax(); 2364 if (!uap->vendor->always_enabled) 2365 pl011_write(old_cr, uap, REG_CR); 2366 2367 if (locked) 2368 uart_port_unlock(&uap->port); 2369 local_irq_restore(flags); 2370 2371 clk_disable(uap->clk); 2372 } 2373 2374 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud, 2375 int *parity, int *bits) 2376 { 2377 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) { 2378 unsigned int lcr_h, ibrd, fbrd; 2379 2380 lcr_h = pl011_read(uap, REG_LCRH_TX); 2381 2382 *parity = 'n'; 2383 if (lcr_h & UART01x_LCRH_PEN) { 2384 if (lcr_h & UART01x_LCRH_EPS) 2385 *parity = 'e'; 2386 else 2387 *parity = 'o'; 2388 } 2389 2390 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 2391 *bits = 7; 2392 else 2393 *bits = 8; 2394 2395 ibrd = pl011_read(uap, REG_IBRD); 2396 fbrd = pl011_read(uap, REG_FBRD); 2397 2398 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); 2399 2400 if (uap->vendor->oversampling) { 2401 if (pl011_read(uap, REG_CR) 2402 & ST_UART011_CR_OVSFACT) 2403 *baud *= 2; 2404 } 2405 } 2406 } 2407 2408 static int pl011_console_setup(struct console *co, char *options) 2409 { 2410 struct uart_amba_port *uap; 2411 int baud = 38400; 2412 int bits = 8; 2413 int parity = 'n'; 2414 int flow = 'n'; 2415 int ret; 2416 2417 /* 2418 * Check whether an invalid uart number has been specified, and 2419 * if so, search for the first available port that does have 2420 * console support. 2421 */ 2422 if (co->index >= UART_NR) 2423 co->index = 0; 2424 uap = amba_ports[co->index]; 2425 if (!uap) 2426 return -ENODEV; 2427 2428 /* Allow pins to be muxed in and configured */ 2429 pinctrl_pm_select_default_state(uap->port.dev); 2430 2431 ret = clk_prepare(uap->clk); 2432 if (ret) 2433 return ret; 2434 2435 if (dev_get_platdata(uap->port.dev)) { 2436 struct amba_pl011_data *plat; 2437 2438 plat = dev_get_platdata(uap->port.dev); 2439 if (plat->init) 2440 plat->init(); 2441 } 2442 2443 uap->port.uartclk = clk_get_rate(uap->clk); 2444 2445 if (uap->vendor->fixed_options) { 2446 baud = uap->fixed_baud; 2447 } else { 2448 if (options) 2449 uart_parse_options(options, 2450 &baud, &parity, &bits, &flow); 2451 else 2452 pl011_console_get_options(uap, &baud, &parity, &bits); 2453 } 2454 2455 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 2456 } 2457 2458 /** 2459 * pl011_console_match - non-standard console matching 2460 * @co: registering console 2461 * @name: name from console command line 2462 * @idx: index from console command line 2463 * @options: ptr to option string from console command line 2464 * 2465 * Only attempts to match console command lines of the form: 2466 * console=pl011,mmio|mmio32,<addr>[,<options>] 2467 * console=pl011,0x<addr>[,<options>] 2468 * This form is used to register an initial earlycon boot console and 2469 * replace it with the amba_console at pl011 driver init. 2470 * 2471 * Performs console setup for a match (as required by interface) 2472 * If no <options> are specified, then assume the h/w is already setup. 2473 * 2474 * Returns 0 if console matches; otherwise non-zero to use default matching 2475 */ 2476 static int pl011_console_match(struct console *co, char *name, int idx, 2477 char *options) 2478 { 2479 unsigned char iotype; 2480 resource_size_t addr; 2481 int i; 2482 2483 /* 2484 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum 2485 * have a distinct console name, so make sure we check for that. 2486 * The actual implementation of the erratum occurs in the probe 2487 * function. 2488 */ 2489 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0)) 2490 return -ENODEV; 2491 2492 if (uart_parse_earlycon(options, &iotype, &addr, &options)) 2493 return -ENODEV; 2494 2495 if (iotype != UPIO_MEM && iotype != UPIO_MEM32) 2496 return -ENODEV; 2497 2498 /* try to match the port specified on the command line */ 2499 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2500 struct uart_port *port; 2501 2502 if (!amba_ports[i]) 2503 continue; 2504 2505 port = &amba_ports[i]->port; 2506 2507 if (port->mapbase != addr) 2508 continue; 2509 2510 co->index = i; 2511 port->cons = co; 2512 return pl011_console_setup(co, options); 2513 } 2514 2515 return -ENODEV; 2516 } 2517 2518 static struct uart_driver amba_reg; 2519 static struct console amba_console = { 2520 .name = "ttyAMA", 2521 .write = pl011_console_write, 2522 .device = uart_console_device, 2523 .setup = pl011_console_setup, 2524 .match = pl011_console_match, 2525 .flags = CON_PRINTBUFFER | CON_ANYTIME, 2526 .index = -1, 2527 .data = &amba_reg, 2528 }; 2529 2530 #define AMBA_CONSOLE (&amba_console) 2531 2532 static void qdf2400_e44_putc(struct uart_port *port, unsigned char c) 2533 { 2534 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2535 cpu_relax(); 2536 writel(c, port->membase + UART01x_DR); 2537 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) 2538 cpu_relax(); 2539 } 2540 2541 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n) 2542 { 2543 struct earlycon_device *dev = con->data; 2544 2545 uart_console_write(&dev->port, s, n, qdf2400_e44_putc); 2546 } 2547 2548 static void pl011_putc(struct uart_port *port, unsigned char c) 2549 { 2550 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2551 cpu_relax(); 2552 if (port->iotype == UPIO_MEM32) 2553 writel(c, port->membase + UART01x_DR); 2554 else 2555 writeb(c, port->membase + UART01x_DR); 2556 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) 2557 cpu_relax(); 2558 } 2559 2560 static void pl011_early_write(struct console *con, const char *s, unsigned n) 2561 { 2562 struct earlycon_device *dev = con->data; 2563 2564 uart_console_write(&dev->port, s, n, pl011_putc); 2565 } 2566 2567 #ifdef CONFIG_CONSOLE_POLL 2568 static int pl011_getc(struct uart_port *port) 2569 { 2570 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE) 2571 return NO_POLL_CHAR; 2572 2573 if (port->iotype == UPIO_MEM32) 2574 return readl(port->membase + UART01x_DR); 2575 else 2576 return readb(port->membase + UART01x_DR); 2577 } 2578 2579 static int pl011_early_read(struct console *con, char *s, unsigned int n) 2580 { 2581 struct earlycon_device *dev = con->data; 2582 int ch, num_read = 0; 2583 2584 while (num_read < n) { 2585 ch = pl011_getc(&dev->port); 2586 if (ch == NO_POLL_CHAR) 2587 break; 2588 2589 s[num_read++] = ch; 2590 } 2591 2592 return num_read; 2593 } 2594 #else 2595 #define pl011_early_read NULL 2596 #endif 2597 2598 /* 2599 * On non-ACPI systems, earlycon is enabled by specifying 2600 * "earlycon=pl011,<address>" on the kernel command line. 2601 * 2602 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table, 2603 * by specifying only "earlycon" on the command line. Because it requires 2604 * SPCR, the console starts after ACPI is parsed, which is later than a 2605 * traditional early console. 2606 * 2607 * To get the traditional early console that starts before ACPI is parsed, 2608 * specify the full "earlycon=pl011,<address>" option. 2609 */ 2610 static int __init pl011_early_console_setup(struct earlycon_device *device, 2611 const char *opt) 2612 { 2613 if (!device->port.membase) 2614 return -ENODEV; 2615 2616 device->con->write = pl011_early_write; 2617 device->con->read = pl011_early_read; 2618 2619 return 0; 2620 } 2621 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); 2622 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup); 2623 2624 /* 2625 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by 2626 * Erratum 44, traditional earlycon can be enabled by specifying 2627 * "earlycon=qdf2400_e44,<address>". Any options are ignored. 2628 * 2629 * Alternatively, you can just specify "earlycon", and the early console 2630 * will be enabled with the information from the SPCR table. In this 2631 * case, the SPCR code will detect the need for the E44 work-around, 2632 * and set the console name to "qdf2400_e44". 2633 */ 2634 static int __init 2635 qdf2400_e44_early_console_setup(struct earlycon_device *device, 2636 const char *opt) 2637 { 2638 if (!device->port.membase) 2639 return -ENODEV; 2640 2641 device->con->write = qdf2400_e44_early_write; 2642 return 0; 2643 } 2644 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup); 2645 2646 #else 2647 #define AMBA_CONSOLE NULL 2648 #endif 2649 2650 static struct uart_driver amba_reg = { 2651 .owner = THIS_MODULE, 2652 .driver_name = "ttyAMA", 2653 .dev_name = "ttyAMA", 2654 .major = SERIAL_AMBA_MAJOR, 2655 .minor = SERIAL_AMBA_MINOR, 2656 .nr = UART_NR, 2657 .cons = AMBA_CONSOLE, 2658 }; 2659 2660 static int pl011_probe_dt_alias(int index, struct device *dev) 2661 { 2662 struct device_node *np; 2663 static bool seen_dev_with_alias = false; 2664 static bool seen_dev_without_alias = false; 2665 int ret = index; 2666 2667 if (!IS_ENABLED(CONFIG_OF)) 2668 return ret; 2669 2670 np = dev->of_node; 2671 if (!np) 2672 return ret; 2673 2674 ret = of_alias_get_id(np, "serial"); 2675 if (ret < 0) { 2676 seen_dev_without_alias = true; 2677 ret = index; 2678 } else { 2679 seen_dev_with_alias = true; 2680 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { 2681 dev_warn(dev, "requested serial port %d not available.\n", ret); 2682 ret = index; 2683 } 2684 } 2685 2686 if (seen_dev_with_alias && seen_dev_without_alias) 2687 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); 2688 2689 return ret; 2690 } 2691 2692 /* unregisters the driver also if no more ports are left */ 2693 static void pl011_unregister_port(struct uart_amba_port *uap) 2694 { 2695 int i; 2696 bool busy = false; 2697 2698 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2699 if (amba_ports[i] == uap) 2700 amba_ports[i] = NULL; 2701 else if (amba_ports[i]) 2702 busy = true; 2703 } 2704 pl011_dma_remove(uap); 2705 if (!busy) 2706 uart_unregister_driver(&amba_reg); 2707 } 2708 2709 static int pl011_find_free_port(void) 2710 { 2711 int i; 2712 2713 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2714 if (amba_ports[i] == NULL) 2715 return i; 2716 2717 return -EBUSY; 2718 } 2719 2720 static int pl011_get_rs485_mode(struct uart_amba_port *uap) 2721 { 2722 struct uart_port *port = &uap->port; 2723 int ret; 2724 2725 ret = uart_get_rs485_mode(port); 2726 if (ret) 2727 return ret; 2728 2729 return 0; 2730 } 2731 2732 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, 2733 struct resource *mmiobase, int index) 2734 { 2735 void __iomem *base; 2736 int ret; 2737 2738 base = devm_ioremap_resource(dev, mmiobase); 2739 if (IS_ERR(base)) 2740 return PTR_ERR(base); 2741 2742 index = pl011_probe_dt_alias(index, dev); 2743 2744 uap->port.dev = dev; 2745 uap->port.mapbase = mmiobase->start; 2746 uap->port.membase = base; 2747 uap->port.fifosize = uap->fifosize; 2748 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE); 2749 uap->port.flags = UPF_BOOT_AUTOCONF; 2750 uap->port.line = index; 2751 2752 ret = pl011_get_rs485_mode(uap); 2753 if (ret) 2754 return ret; 2755 2756 amba_ports[index] = uap; 2757 2758 return 0; 2759 } 2760 2761 static int pl011_register_port(struct uart_amba_port *uap) 2762 { 2763 int ret, i; 2764 2765 /* Ensure interrupts from this UART are masked and cleared */ 2766 pl011_write(0, uap, REG_IMSC); 2767 pl011_write(0xffff, uap, REG_ICR); 2768 2769 if (!amba_reg.state) { 2770 ret = uart_register_driver(&amba_reg); 2771 if (ret < 0) { 2772 dev_err(uap->port.dev, 2773 "Failed to register AMBA-PL011 driver\n"); 2774 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2775 if (amba_ports[i] == uap) 2776 amba_ports[i] = NULL; 2777 return ret; 2778 } 2779 } 2780 2781 ret = uart_add_one_port(&amba_reg, &uap->port); 2782 if (ret) 2783 pl011_unregister_port(uap); 2784 2785 return ret; 2786 } 2787 2788 static const struct serial_rs485 pl011_rs485_supported = { 2789 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | 2790 SER_RS485_RX_DURING_TX, 2791 .delay_rts_before_send = 1, 2792 .delay_rts_after_send = 1, 2793 }; 2794 2795 static int pl011_probe(struct amba_device *dev, const struct amba_id *id) 2796 { 2797 struct uart_amba_port *uap; 2798 struct vendor_data *vendor = id->data; 2799 int portnr, ret; 2800 u32 val; 2801 2802 portnr = pl011_find_free_port(); 2803 if (portnr < 0) 2804 return portnr; 2805 2806 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), 2807 GFP_KERNEL); 2808 if (!uap) 2809 return -ENOMEM; 2810 2811 uap->clk = devm_clk_get(&dev->dev, NULL); 2812 if (IS_ERR(uap->clk)) 2813 return PTR_ERR(uap->clk); 2814 2815 uap->reg_offset = vendor->reg_offset; 2816 uap->vendor = vendor; 2817 uap->fifosize = vendor->get_fifosize(dev); 2818 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 2819 uap->port.irq = dev->irq[0]; 2820 uap->port.ops = &amba_pl011_pops; 2821 uap->port.rs485_config = pl011_rs485_config; 2822 uap->port.rs485_supported = pl011_rs485_supported; 2823 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); 2824 2825 if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) { 2826 switch (val) { 2827 case 1: 2828 uap->port.iotype = UPIO_MEM; 2829 break; 2830 case 4: 2831 uap->port.iotype = UPIO_MEM32; 2832 break; 2833 default: 2834 dev_warn(&dev->dev, "unsupported reg-io-width (%d)\n", 2835 val); 2836 return -EINVAL; 2837 } 2838 } 2839 2840 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); 2841 if (ret) 2842 return ret; 2843 2844 amba_set_drvdata(dev, uap); 2845 2846 return pl011_register_port(uap); 2847 } 2848 2849 static void pl011_remove(struct amba_device *dev) 2850 { 2851 struct uart_amba_port *uap = amba_get_drvdata(dev); 2852 2853 uart_remove_one_port(&amba_reg, &uap->port); 2854 pl011_unregister_port(uap); 2855 } 2856 2857 #ifdef CONFIG_PM_SLEEP 2858 static int pl011_suspend(struct device *dev) 2859 { 2860 struct uart_amba_port *uap = dev_get_drvdata(dev); 2861 2862 if (!uap) 2863 return -EINVAL; 2864 2865 return uart_suspend_port(&amba_reg, &uap->port); 2866 } 2867 2868 static int pl011_resume(struct device *dev) 2869 { 2870 struct uart_amba_port *uap = dev_get_drvdata(dev); 2871 2872 if (!uap) 2873 return -EINVAL; 2874 2875 return uart_resume_port(&amba_reg, &uap->port); 2876 } 2877 #endif 2878 2879 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); 2880 2881 static int sbsa_uart_probe(struct platform_device *pdev) 2882 { 2883 struct uart_amba_port *uap; 2884 struct resource *r; 2885 int portnr, ret; 2886 int baudrate; 2887 2888 /* 2889 * Check the mandatory baud rate parameter in the DT node early 2890 * so that we can easily exit with the error. 2891 */ 2892 if (pdev->dev.of_node) { 2893 struct device_node *np = pdev->dev.of_node; 2894 2895 ret = of_property_read_u32(np, "current-speed", &baudrate); 2896 if (ret) 2897 return ret; 2898 } else { 2899 baudrate = 115200; 2900 } 2901 2902 portnr = pl011_find_free_port(); 2903 if (portnr < 0) 2904 return portnr; 2905 2906 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), 2907 GFP_KERNEL); 2908 if (!uap) 2909 return -ENOMEM; 2910 2911 ret = platform_get_irq(pdev, 0); 2912 if (ret < 0) 2913 return ret; 2914 uap->port.irq = ret; 2915 2916 #ifdef CONFIG_ACPI_SPCR_TABLE 2917 if (qdf2400_e44_present) { 2918 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n"); 2919 uap->vendor = &vendor_qdt_qdf2400_e44; 2920 } else 2921 #endif 2922 uap->vendor = &vendor_sbsa; 2923 2924 uap->reg_offset = uap->vendor->reg_offset; 2925 uap->fifosize = 32; 2926 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 2927 uap->port.ops = &sbsa_uart_pops; 2928 uap->fixed_baud = baudrate; 2929 2930 snprintf(uap->type, sizeof(uap->type), "SBSA"); 2931 2932 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2933 2934 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); 2935 if (ret) 2936 return ret; 2937 2938 platform_set_drvdata(pdev, uap); 2939 2940 return pl011_register_port(uap); 2941 } 2942 2943 static int sbsa_uart_remove(struct platform_device *pdev) 2944 { 2945 struct uart_amba_port *uap = platform_get_drvdata(pdev); 2946 2947 uart_remove_one_port(&amba_reg, &uap->port); 2948 pl011_unregister_port(uap); 2949 return 0; 2950 } 2951 2952 static const struct of_device_id sbsa_uart_of_match[] = { 2953 { .compatible = "arm,sbsa-uart", }, 2954 {}, 2955 }; 2956 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); 2957 2958 static const struct acpi_device_id __maybe_unused sbsa_uart_acpi_match[] = { 2959 { "ARMH0011", 0 }, 2960 { "ARMHB000", 0 }, 2961 {}, 2962 }; 2963 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); 2964 2965 static struct platform_driver arm_sbsa_uart_platform_driver = { 2966 .probe = sbsa_uart_probe, 2967 .remove = sbsa_uart_remove, 2968 .driver = { 2969 .name = "sbsa-uart", 2970 .pm = &pl011_dev_pm_ops, 2971 .of_match_table = of_match_ptr(sbsa_uart_of_match), 2972 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match), 2973 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), 2974 }, 2975 }; 2976 2977 static const struct amba_id pl011_ids[] = { 2978 { 2979 .id = 0x00041011, 2980 .mask = 0x000fffff, 2981 .data = &vendor_arm, 2982 }, 2983 { 2984 .id = 0x00380802, 2985 .mask = 0x00ffffff, 2986 .data = &vendor_st, 2987 }, 2988 { 0, 0 }, 2989 }; 2990 2991 MODULE_DEVICE_TABLE(amba, pl011_ids); 2992 2993 static struct amba_driver pl011_driver = { 2994 .drv = { 2995 .name = "uart-pl011", 2996 .pm = &pl011_dev_pm_ops, 2997 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), 2998 }, 2999 .id_table = pl011_ids, 3000 .probe = pl011_probe, 3001 .remove = pl011_remove, 3002 }; 3003 3004 static int __init pl011_init(void) 3005 { 3006 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); 3007 3008 if (platform_driver_register(&arm_sbsa_uart_platform_driver)) 3009 pr_warn("could not register SBSA UART platform driver\n"); 3010 return amba_driver_register(&pl011_driver); 3011 } 3012 3013 static void __exit pl011_exit(void) 3014 { 3015 platform_driver_unregister(&arm_sbsa_uart_platform_driver); 3016 amba_driver_unregister(&pl011_driver); 3017 } 3018 3019 /* 3020 * While this can be a module, if builtin it's most likely the console 3021 * So let's leave module_exit but move module_init to an earlier place 3022 */ 3023 arch_initcall(pl011_init); 3024 module_exit(pl011_exit); 3025 3026 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 3027 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 3028 MODULE_LICENSE("GPL"); 3029