1 /* 2 * Driver for AMBA serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright 1999 ARM Limited 7 * Copyright (C) 2000 Deep Blue Solutions Ltd. 8 * Copyright (C) 2010 ST-Ericsson SA 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 * This is a generic driver for ARM AMBA-type serial ports. They 25 * have a lot of 16550-like features, but are not register compatible. 26 * Note that although they do have CTS, DCD and DSR inputs, they do 27 * not have an RI input, nor do they have DTR or RTS outputs. If 28 * required, these have to be supplied via some other means (eg, GPIO) 29 * and hooked into this driver. 30 */ 31 32 33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 34 #define SUPPORT_SYSRQ 35 #endif 36 37 #include <linux/module.h> 38 #include <linux/ioport.h> 39 #include <linux/init.h> 40 #include <linux/console.h> 41 #include <linux/sysrq.h> 42 #include <linux/device.h> 43 #include <linux/tty.h> 44 #include <linux/tty_flip.h> 45 #include <linux/serial_core.h> 46 #include <linux/serial.h> 47 #include <linux/amba/bus.h> 48 #include <linux/amba/serial.h> 49 #include <linux/clk.h> 50 #include <linux/slab.h> 51 #include <linux/dmaengine.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/scatterlist.h> 54 #include <linux/delay.h> 55 #include <linux/types.h> 56 #include <linux/of.h> 57 #include <linux/of_device.h> 58 #include <linux/pinctrl/consumer.h> 59 #include <linux/sizes.h> 60 #include <linux/io.h> 61 #include <linux/acpi.h> 62 63 #include "amba-pl011.h" 64 65 #define UART_NR 14 66 67 #define SERIAL_AMBA_MAJOR 204 68 #define SERIAL_AMBA_MINOR 64 69 #define SERIAL_AMBA_NR UART_NR 70 71 #define AMBA_ISR_PASS_LIMIT 256 72 73 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) 74 #define UART_DUMMY_DR_RX (1 << 16) 75 76 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = { 77 [REG_DR] = UART01x_DR, 78 [REG_FR] = UART01x_FR, 79 [REG_LCRH_RX] = UART011_LCRH, 80 [REG_LCRH_TX] = UART011_LCRH, 81 [REG_IBRD] = UART011_IBRD, 82 [REG_FBRD] = UART011_FBRD, 83 [REG_CR] = UART011_CR, 84 [REG_IFLS] = UART011_IFLS, 85 [REG_IMSC] = UART011_IMSC, 86 [REG_RIS] = UART011_RIS, 87 [REG_MIS] = UART011_MIS, 88 [REG_ICR] = UART011_ICR, 89 [REG_DMACR] = UART011_DMACR, 90 }; 91 92 /* There is by now at least one vendor with differing details, so handle it */ 93 struct vendor_data { 94 const u16 *reg_offset; 95 unsigned int ifls; 96 unsigned int fr_busy; 97 unsigned int fr_dsr; 98 unsigned int fr_cts; 99 unsigned int fr_ri; 100 bool access_32b; 101 bool oversampling; 102 bool dma_threshold; 103 bool cts_event_workaround; 104 bool always_enabled; 105 bool fixed_options; 106 107 unsigned int (*get_fifosize)(struct amba_device *dev); 108 }; 109 110 static unsigned int get_fifosize_arm(struct amba_device *dev) 111 { 112 return amba_rev(dev) < 3 ? 16 : 32; 113 } 114 115 static struct vendor_data vendor_arm = { 116 .reg_offset = pl011_std_offsets, 117 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 118 .fr_busy = UART01x_FR_BUSY, 119 .fr_dsr = UART01x_FR_DSR, 120 .fr_cts = UART01x_FR_CTS, 121 .fr_ri = UART011_FR_RI, 122 .oversampling = false, 123 .dma_threshold = false, 124 .cts_event_workaround = false, 125 .always_enabled = false, 126 .fixed_options = false, 127 .get_fifosize = get_fifosize_arm, 128 }; 129 130 static struct vendor_data vendor_sbsa = { 131 .reg_offset = pl011_std_offsets, 132 .fr_busy = UART01x_FR_BUSY, 133 .fr_dsr = UART01x_FR_DSR, 134 .fr_cts = UART01x_FR_CTS, 135 .fr_ri = UART011_FR_RI, 136 .access_32b = true, 137 .oversampling = false, 138 .dma_threshold = false, 139 .cts_event_workaround = false, 140 .always_enabled = true, 141 .fixed_options = true, 142 }; 143 144 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { 145 [REG_DR] = UART01x_DR, 146 [REG_ST_DMAWM] = ST_UART011_DMAWM, 147 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, 148 [REG_FR] = UART01x_FR, 149 [REG_LCRH_RX] = ST_UART011_LCRH_RX, 150 [REG_LCRH_TX] = ST_UART011_LCRH_TX, 151 [REG_IBRD] = UART011_IBRD, 152 [REG_FBRD] = UART011_FBRD, 153 [REG_CR] = UART011_CR, 154 [REG_IFLS] = UART011_IFLS, 155 [REG_IMSC] = UART011_IMSC, 156 [REG_RIS] = UART011_RIS, 157 [REG_MIS] = UART011_MIS, 158 [REG_ICR] = UART011_ICR, 159 [REG_DMACR] = UART011_DMACR, 160 [REG_ST_XFCR] = ST_UART011_XFCR, 161 [REG_ST_XON1] = ST_UART011_XON1, 162 [REG_ST_XON2] = ST_UART011_XON2, 163 [REG_ST_XOFF1] = ST_UART011_XOFF1, 164 [REG_ST_XOFF2] = ST_UART011_XOFF2, 165 [REG_ST_ITCR] = ST_UART011_ITCR, 166 [REG_ST_ITIP] = ST_UART011_ITIP, 167 [REG_ST_ABCR] = ST_UART011_ABCR, 168 [REG_ST_ABIMSC] = ST_UART011_ABIMSC, 169 }; 170 171 static unsigned int get_fifosize_st(struct amba_device *dev) 172 { 173 return 64; 174 } 175 176 static struct vendor_data vendor_st = { 177 .reg_offset = pl011_st_offsets, 178 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, 179 .fr_busy = UART01x_FR_BUSY, 180 .fr_dsr = UART01x_FR_DSR, 181 .fr_cts = UART01x_FR_CTS, 182 .fr_ri = UART011_FR_RI, 183 .oversampling = true, 184 .dma_threshold = true, 185 .cts_event_workaround = true, 186 .always_enabled = false, 187 .fixed_options = false, 188 .get_fifosize = get_fifosize_st, 189 }; 190 191 static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = { 192 [REG_DR] = ZX_UART011_DR, 193 [REG_FR] = ZX_UART011_FR, 194 [REG_LCRH_RX] = ZX_UART011_LCRH, 195 [REG_LCRH_TX] = ZX_UART011_LCRH, 196 [REG_IBRD] = ZX_UART011_IBRD, 197 [REG_FBRD] = ZX_UART011_FBRD, 198 [REG_CR] = ZX_UART011_CR, 199 [REG_IFLS] = ZX_UART011_IFLS, 200 [REG_IMSC] = ZX_UART011_IMSC, 201 [REG_RIS] = ZX_UART011_RIS, 202 [REG_MIS] = ZX_UART011_MIS, 203 [REG_ICR] = ZX_UART011_ICR, 204 [REG_DMACR] = ZX_UART011_DMACR, 205 }; 206 207 static unsigned int get_fifosize_zte(struct amba_device *dev) 208 { 209 return 16; 210 } 211 212 static struct vendor_data vendor_zte = { 213 .reg_offset = pl011_zte_offsets, 214 .access_32b = true, 215 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 216 .fr_busy = ZX_UART01x_FR_BUSY, 217 .fr_dsr = ZX_UART01x_FR_DSR, 218 .fr_cts = ZX_UART01x_FR_CTS, 219 .fr_ri = ZX_UART011_FR_RI, 220 .get_fifosize = get_fifosize_zte, 221 }; 222 223 /* Deals with DMA transactions */ 224 225 struct pl011_sgbuf { 226 struct scatterlist sg; 227 char *buf; 228 }; 229 230 struct pl011_dmarx_data { 231 struct dma_chan *chan; 232 struct completion complete; 233 bool use_buf_b; 234 struct pl011_sgbuf sgbuf_a; 235 struct pl011_sgbuf sgbuf_b; 236 dma_cookie_t cookie; 237 bool running; 238 struct timer_list timer; 239 unsigned int last_residue; 240 unsigned long last_jiffies; 241 bool auto_poll_rate; 242 unsigned int poll_rate; 243 unsigned int poll_timeout; 244 }; 245 246 struct pl011_dmatx_data { 247 struct dma_chan *chan; 248 struct scatterlist sg; 249 char *buf; 250 bool queued; 251 }; 252 253 /* 254 * We wrap our port structure around the generic uart_port. 255 */ 256 struct uart_amba_port { 257 struct uart_port port; 258 const u16 *reg_offset; 259 struct clk *clk; 260 const struct vendor_data *vendor; 261 unsigned int dmacr; /* dma control reg */ 262 unsigned int im; /* interrupt mask */ 263 unsigned int old_status; 264 unsigned int fifosize; /* vendor-specific */ 265 unsigned int old_cr; /* state during shutdown */ 266 bool autorts; 267 unsigned int fixed_baud; /* vendor-set fixed baud rate */ 268 char type[12]; 269 #ifdef CONFIG_DMA_ENGINE 270 /* DMA stuff */ 271 bool using_tx_dma; 272 bool using_rx_dma; 273 struct pl011_dmarx_data dmarx; 274 struct pl011_dmatx_data dmatx; 275 bool dma_probed; 276 #endif 277 }; 278 279 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, 280 unsigned int reg) 281 { 282 return uap->reg_offset[reg]; 283 } 284 285 static unsigned int pl011_read(const struct uart_amba_port *uap, 286 unsigned int reg) 287 { 288 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 289 290 return (uap->port.iotype == UPIO_MEM32) ? 291 readl_relaxed(addr) : readw_relaxed(addr); 292 } 293 294 static void pl011_write(unsigned int val, const struct uart_amba_port *uap, 295 unsigned int reg) 296 { 297 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 298 299 if (uap->port.iotype == UPIO_MEM32) 300 writel_relaxed(val, addr); 301 else 302 writew_relaxed(val, addr); 303 } 304 305 /* 306 * Reads up to 256 characters from the FIFO or until it's empty and 307 * inserts them into the TTY layer. Returns the number of characters 308 * read from the FIFO. 309 */ 310 static int pl011_fifo_to_tty(struct uart_amba_port *uap) 311 { 312 u16 status; 313 unsigned int ch, flag, max_count = 256; 314 int fifotaken = 0; 315 316 while (max_count--) { 317 status = pl011_read(uap, REG_FR); 318 if (status & UART01x_FR_RXFE) 319 break; 320 321 /* Take chars from the FIFO and update status */ 322 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; 323 flag = TTY_NORMAL; 324 uap->port.icount.rx++; 325 fifotaken++; 326 327 if (unlikely(ch & UART_DR_ERROR)) { 328 if (ch & UART011_DR_BE) { 329 ch &= ~(UART011_DR_FE | UART011_DR_PE); 330 uap->port.icount.brk++; 331 if (uart_handle_break(&uap->port)) 332 continue; 333 } else if (ch & UART011_DR_PE) 334 uap->port.icount.parity++; 335 else if (ch & UART011_DR_FE) 336 uap->port.icount.frame++; 337 if (ch & UART011_DR_OE) 338 uap->port.icount.overrun++; 339 340 ch &= uap->port.read_status_mask; 341 342 if (ch & UART011_DR_BE) 343 flag = TTY_BREAK; 344 else if (ch & UART011_DR_PE) 345 flag = TTY_PARITY; 346 else if (ch & UART011_DR_FE) 347 flag = TTY_FRAME; 348 } 349 350 if (uart_handle_sysrq_char(&uap->port, ch & 255)) 351 continue; 352 353 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); 354 } 355 356 return fifotaken; 357 } 358 359 360 /* 361 * All the DMA operation mode stuff goes inside this ifdef. 362 * This assumes that you have a generic DMA device interface, 363 * no custom DMA interfaces are supported. 364 */ 365 #ifdef CONFIG_DMA_ENGINE 366 367 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE 368 369 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, 370 enum dma_data_direction dir) 371 { 372 dma_addr_t dma_addr; 373 374 sg->buf = dma_alloc_coherent(chan->device->dev, 375 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); 376 if (!sg->buf) 377 return -ENOMEM; 378 379 sg_init_table(&sg->sg, 1); 380 sg_set_page(&sg->sg, phys_to_page(dma_addr), 381 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); 382 sg_dma_address(&sg->sg) = dma_addr; 383 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; 384 385 return 0; 386 } 387 388 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, 389 enum dma_data_direction dir) 390 { 391 if (sg->buf) { 392 dma_free_coherent(chan->device->dev, 393 PL011_DMA_BUFFER_SIZE, sg->buf, 394 sg_dma_address(&sg->sg)); 395 } 396 } 397 398 static void pl011_dma_probe(struct uart_amba_port *uap) 399 { 400 /* DMA is the sole user of the platform data right now */ 401 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); 402 struct device *dev = uap->port.dev; 403 struct dma_slave_config tx_conf = { 404 .dst_addr = uap->port.mapbase + 405 pl011_reg_to_offset(uap, REG_DR), 406 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 407 .direction = DMA_MEM_TO_DEV, 408 .dst_maxburst = uap->fifosize >> 1, 409 .device_fc = false, 410 }; 411 struct dma_chan *chan; 412 dma_cap_mask_t mask; 413 414 uap->dma_probed = true; 415 chan = dma_request_slave_channel_reason(dev, "tx"); 416 if (IS_ERR(chan)) { 417 if (PTR_ERR(chan) == -EPROBE_DEFER) { 418 uap->dma_probed = false; 419 return; 420 } 421 422 /* We need platform data */ 423 if (!plat || !plat->dma_filter) { 424 dev_info(uap->port.dev, "no DMA platform data\n"); 425 return; 426 } 427 428 /* Try to acquire a generic DMA engine slave TX channel */ 429 dma_cap_zero(mask); 430 dma_cap_set(DMA_SLAVE, mask); 431 432 chan = dma_request_channel(mask, plat->dma_filter, 433 plat->dma_tx_param); 434 if (!chan) { 435 dev_err(uap->port.dev, "no TX DMA channel!\n"); 436 return; 437 } 438 } 439 440 dmaengine_slave_config(chan, &tx_conf); 441 uap->dmatx.chan = chan; 442 443 dev_info(uap->port.dev, "DMA channel TX %s\n", 444 dma_chan_name(uap->dmatx.chan)); 445 446 /* Optionally make use of an RX channel as well */ 447 chan = dma_request_slave_channel(dev, "rx"); 448 449 if (!chan && plat && plat->dma_rx_param) { 450 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); 451 452 if (!chan) { 453 dev_err(uap->port.dev, "no RX DMA channel!\n"); 454 return; 455 } 456 } 457 458 if (chan) { 459 struct dma_slave_config rx_conf = { 460 .src_addr = uap->port.mapbase + 461 pl011_reg_to_offset(uap, REG_DR), 462 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 463 .direction = DMA_DEV_TO_MEM, 464 .src_maxburst = uap->fifosize >> 2, 465 .device_fc = false, 466 }; 467 struct dma_slave_caps caps; 468 469 /* 470 * Some DMA controllers provide information on their capabilities. 471 * If the controller does, check for suitable residue processing 472 * otherwise assime all is well. 473 */ 474 if (0 == dma_get_slave_caps(chan, &caps)) { 475 if (caps.residue_granularity == 476 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { 477 dma_release_channel(chan); 478 dev_info(uap->port.dev, 479 "RX DMA disabled - no residue processing\n"); 480 return; 481 } 482 } 483 dmaengine_slave_config(chan, &rx_conf); 484 uap->dmarx.chan = chan; 485 486 uap->dmarx.auto_poll_rate = false; 487 if (plat && plat->dma_rx_poll_enable) { 488 /* Set poll rate if specified. */ 489 if (plat->dma_rx_poll_rate) { 490 uap->dmarx.auto_poll_rate = false; 491 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; 492 } else { 493 /* 494 * 100 ms defaults to poll rate if not 495 * specified. This will be adjusted with 496 * the baud rate at set_termios. 497 */ 498 uap->dmarx.auto_poll_rate = true; 499 uap->dmarx.poll_rate = 100; 500 } 501 /* 3 secs defaults poll_timeout if not specified. */ 502 if (plat->dma_rx_poll_timeout) 503 uap->dmarx.poll_timeout = 504 plat->dma_rx_poll_timeout; 505 else 506 uap->dmarx.poll_timeout = 3000; 507 } else if (!plat && dev->of_node) { 508 uap->dmarx.auto_poll_rate = of_property_read_bool( 509 dev->of_node, "auto-poll"); 510 if (uap->dmarx.auto_poll_rate) { 511 u32 x; 512 513 if (0 == of_property_read_u32(dev->of_node, 514 "poll-rate-ms", &x)) 515 uap->dmarx.poll_rate = x; 516 else 517 uap->dmarx.poll_rate = 100; 518 if (0 == of_property_read_u32(dev->of_node, 519 "poll-timeout-ms", &x)) 520 uap->dmarx.poll_timeout = x; 521 else 522 uap->dmarx.poll_timeout = 3000; 523 } 524 } 525 dev_info(uap->port.dev, "DMA channel RX %s\n", 526 dma_chan_name(uap->dmarx.chan)); 527 } 528 } 529 530 static void pl011_dma_remove(struct uart_amba_port *uap) 531 { 532 if (uap->dmatx.chan) 533 dma_release_channel(uap->dmatx.chan); 534 if (uap->dmarx.chan) 535 dma_release_channel(uap->dmarx.chan); 536 } 537 538 /* Forward declare these for the refill routine */ 539 static int pl011_dma_tx_refill(struct uart_amba_port *uap); 540 static void pl011_start_tx_pio(struct uart_amba_port *uap); 541 542 /* 543 * The current DMA TX buffer has been sent. 544 * Try to queue up another DMA buffer. 545 */ 546 static void pl011_dma_tx_callback(void *data) 547 { 548 struct uart_amba_port *uap = data; 549 struct pl011_dmatx_data *dmatx = &uap->dmatx; 550 unsigned long flags; 551 u16 dmacr; 552 553 spin_lock_irqsave(&uap->port.lock, flags); 554 if (uap->dmatx.queued) 555 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, 556 DMA_TO_DEVICE); 557 558 dmacr = uap->dmacr; 559 uap->dmacr = dmacr & ~UART011_TXDMAE; 560 pl011_write(uap->dmacr, uap, REG_DMACR); 561 562 /* 563 * If TX DMA was disabled, it means that we've stopped the DMA for 564 * some reason (eg, XOFF received, or we want to send an X-char.) 565 * 566 * Note: we need to be careful here of a potential race between DMA 567 * and the rest of the driver - if the driver disables TX DMA while 568 * a TX buffer completing, we must update the tx queued status to 569 * get further refills (hence we check dmacr). 570 */ 571 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || 572 uart_circ_empty(&uap->port.state->xmit)) { 573 uap->dmatx.queued = false; 574 spin_unlock_irqrestore(&uap->port.lock, flags); 575 return; 576 } 577 578 if (pl011_dma_tx_refill(uap) <= 0) 579 /* 580 * We didn't queue a DMA buffer for some reason, but we 581 * have data pending to be sent. Re-enable the TX IRQ. 582 */ 583 pl011_start_tx_pio(uap); 584 585 spin_unlock_irqrestore(&uap->port.lock, flags); 586 } 587 588 /* 589 * Try to refill the TX DMA buffer. 590 * Locking: called with port lock held and IRQs disabled. 591 * Returns: 592 * 1 if we queued up a TX DMA buffer. 593 * 0 if we didn't want to handle this by DMA 594 * <0 on error 595 */ 596 static int pl011_dma_tx_refill(struct uart_amba_port *uap) 597 { 598 struct pl011_dmatx_data *dmatx = &uap->dmatx; 599 struct dma_chan *chan = dmatx->chan; 600 struct dma_device *dma_dev = chan->device; 601 struct dma_async_tx_descriptor *desc; 602 struct circ_buf *xmit = &uap->port.state->xmit; 603 unsigned int count; 604 605 /* 606 * Try to avoid the overhead involved in using DMA if the 607 * transaction fits in the first half of the FIFO, by using 608 * the standard interrupt handling. This ensures that we 609 * issue a uart_write_wakeup() at the appropriate time. 610 */ 611 count = uart_circ_chars_pending(xmit); 612 if (count < (uap->fifosize >> 1)) { 613 uap->dmatx.queued = false; 614 return 0; 615 } 616 617 /* 618 * Bodge: don't send the last character by DMA, as this 619 * will prevent XON from notifying us to restart DMA. 620 */ 621 count -= 1; 622 623 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ 624 if (count > PL011_DMA_BUFFER_SIZE) 625 count = PL011_DMA_BUFFER_SIZE; 626 627 if (xmit->tail < xmit->head) 628 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); 629 else { 630 size_t first = UART_XMIT_SIZE - xmit->tail; 631 size_t second; 632 633 if (first > count) 634 first = count; 635 second = count - first; 636 637 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); 638 if (second) 639 memcpy(&dmatx->buf[first], &xmit->buf[0], second); 640 } 641 642 dmatx->sg.length = count; 643 644 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { 645 uap->dmatx.queued = false; 646 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); 647 return -EBUSY; 648 } 649 650 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, 651 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 652 if (!desc) { 653 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); 654 uap->dmatx.queued = false; 655 /* 656 * If DMA cannot be used right now, we complete this 657 * transaction via IRQ and let the TTY layer retry. 658 */ 659 dev_dbg(uap->port.dev, "TX DMA busy\n"); 660 return -EBUSY; 661 } 662 663 /* Some data to go along to the callback */ 664 desc->callback = pl011_dma_tx_callback; 665 desc->callback_param = uap; 666 667 /* All errors should happen at prepare time */ 668 dmaengine_submit(desc); 669 670 /* Fire the DMA transaction */ 671 dma_dev->device_issue_pending(chan); 672 673 uap->dmacr |= UART011_TXDMAE; 674 pl011_write(uap->dmacr, uap, REG_DMACR); 675 uap->dmatx.queued = true; 676 677 /* 678 * Now we know that DMA will fire, so advance the ring buffer 679 * with the stuff we just dispatched. 680 */ 681 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 682 uap->port.icount.tx += count; 683 684 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 685 uart_write_wakeup(&uap->port); 686 687 return 1; 688 } 689 690 /* 691 * We received a transmit interrupt without a pending X-char but with 692 * pending characters. 693 * Locking: called with port lock held and IRQs disabled. 694 * Returns: 695 * false if we want to use PIO to transmit 696 * true if we queued a DMA buffer 697 */ 698 static bool pl011_dma_tx_irq(struct uart_amba_port *uap) 699 { 700 if (!uap->using_tx_dma) 701 return false; 702 703 /* 704 * If we already have a TX buffer queued, but received a 705 * TX interrupt, it will be because we've just sent an X-char. 706 * Ensure the TX DMA is enabled and the TX IRQ is disabled. 707 */ 708 if (uap->dmatx.queued) { 709 uap->dmacr |= UART011_TXDMAE; 710 pl011_write(uap->dmacr, uap, REG_DMACR); 711 uap->im &= ~UART011_TXIM; 712 pl011_write(uap->im, uap, REG_IMSC); 713 return true; 714 } 715 716 /* 717 * We don't have a TX buffer queued, so try to queue one. 718 * If we successfully queued a buffer, mask the TX IRQ. 719 */ 720 if (pl011_dma_tx_refill(uap) > 0) { 721 uap->im &= ~UART011_TXIM; 722 pl011_write(uap->im, uap, REG_IMSC); 723 return true; 724 } 725 return false; 726 } 727 728 /* 729 * Stop the DMA transmit (eg, due to received XOFF). 730 * Locking: called with port lock held and IRQs disabled. 731 */ 732 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 733 { 734 if (uap->dmatx.queued) { 735 uap->dmacr &= ~UART011_TXDMAE; 736 pl011_write(uap->dmacr, uap, REG_DMACR); 737 } 738 } 739 740 /* 741 * Try to start a DMA transmit, or in the case of an XON/OFF 742 * character queued for send, try to get that character out ASAP. 743 * Locking: called with port lock held and IRQs disabled. 744 * Returns: 745 * false if we want the TX IRQ to be enabled 746 * true if we have a buffer queued 747 */ 748 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 749 { 750 u16 dmacr; 751 752 if (!uap->using_tx_dma) 753 return false; 754 755 if (!uap->port.x_char) { 756 /* no X-char, try to push chars out in DMA mode */ 757 bool ret = true; 758 759 if (!uap->dmatx.queued) { 760 if (pl011_dma_tx_refill(uap) > 0) { 761 uap->im &= ~UART011_TXIM; 762 pl011_write(uap->im, uap, REG_IMSC); 763 } else 764 ret = false; 765 } else if (!(uap->dmacr & UART011_TXDMAE)) { 766 uap->dmacr |= UART011_TXDMAE; 767 pl011_write(uap->dmacr, uap, REG_DMACR); 768 } 769 return ret; 770 } 771 772 /* 773 * We have an X-char to send. Disable DMA to prevent it loading 774 * the TX fifo, and then see if we can stuff it into the FIFO. 775 */ 776 dmacr = uap->dmacr; 777 uap->dmacr &= ~UART011_TXDMAE; 778 pl011_write(uap->dmacr, uap, REG_DMACR); 779 780 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { 781 /* 782 * No space in the FIFO, so enable the transmit interrupt 783 * so we know when there is space. Note that once we've 784 * loaded the character, we should just re-enable DMA. 785 */ 786 return false; 787 } 788 789 pl011_write(uap->port.x_char, uap, REG_DR); 790 uap->port.icount.tx++; 791 uap->port.x_char = 0; 792 793 /* Success - restore the DMA state */ 794 uap->dmacr = dmacr; 795 pl011_write(dmacr, uap, REG_DMACR); 796 797 return true; 798 } 799 800 /* 801 * Flush the transmit buffer. 802 * Locking: called with port lock held and IRQs disabled. 803 */ 804 static void pl011_dma_flush_buffer(struct uart_port *port) 805 __releases(&uap->port.lock) 806 __acquires(&uap->port.lock) 807 { 808 struct uart_amba_port *uap = 809 container_of(port, struct uart_amba_port, port); 810 811 if (!uap->using_tx_dma) 812 return; 813 814 /* Avoid deadlock with the DMA engine callback */ 815 spin_unlock(&uap->port.lock); 816 dmaengine_terminate_all(uap->dmatx.chan); 817 spin_lock(&uap->port.lock); 818 if (uap->dmatx.queued) { 819 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 820 DMA_TO_DEVICE); 821 uap->dmatx.queued = false; 822 uap->dmacr &= ~UART011_TXDMAE; 823 pl011_write(uap->dmacr, uap, REG_DMACR); 824 } 825 } 826 827 static void pl011_dma_rx_callback(void *data); 828 829 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 830 { 831 struct dma_chan *rxchan = uap->dmarx.chan; 832 struct pl011_dmarx_data *dmarx = &uap->dmarx; 833 struct dma_async_tx_descriptor *desc; 834 struct pl011_sgbuf *sgbuf; 835 836 if (!rxchan) 837 return -EIO; 838 839 /* Start the RX DMA job */ 840 sgbuf = uap->dmarx.use_buf_b ? 841 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 842 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, 843 DMA_DEV_TO_MEM, 844 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 845 /* 846 * If the DMA engine is busy and cannot prepare a 847 * channel, no big deal, the driver will fall back 848 * to interrupt mode as a result of this error code. 849 */ 850 if (!desc) { 851 uap->dmarx.running = false; 852 dmaengine_terminate_all(rxchan); 853 return -EBUSY; 854 } 855 856 /* Some data to go along to the callback */ 857 desc->callback = pl011_dma_rx_callback; 858 desc->callback_param = uap; 859 dmarx->cookie = dmaengine_submit(desc); 860 dma_async_issue_pending(rxchan); 861 862 uap->dmacr |= UART011_RXDMAE; 863 pl011_write(uap->dmacr, uap, REG_DMACR); 864 uap->dmarx.running = true; 865 866 uap->im &= ~UART011_RXIM; 867 pl011_write(uap->im, uap, REG_IMSC); 868 869 return 0; 870 } 871 872 /* 873 * This is called when either the DMA job is complete, or 874 * the FIFO timeout interrupt occurred. This must be called 875 * with the port spinlock uap->port.lock held. 876 */ 877 static void pl011_dma_rx_chars(struct uart_amba_port *uap, 878 u32 pending, bool use_buf_b, 879 bool readfifo) 880 { 881 struct tty_port *port = &uap->port.state->port; 882 struct pl011_sgbuf *sgbuf = use_buf_b ? 883 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 884 int dma_count = 0; 885 u32 fifotaken = 0; /* only used for vdbg() */ 886 887 struct pl011_dmarx_data *dmarx = &uap->dmarx; 888 int dmataken = 0; 889 890 if (uap->dmarx.poll_rate) { 891 /* The data can be taken by polling */ 892 dmataken = sgbuf->sg.length - dmarx->last_residue; 893 /* Recalculate the pending size */ 894 if (pending >= dmataken) 895 pending -= dmataken; 896 } 897 898 /* Pick the remain data from the DMA */ 899 if (pending) { 900 901 /* 902 * First take all chars in the DMA pipe, then look in the FIFO. 903 * Note that tty_insert_flip_buf() tries to take as many chars 904 * as it can. 905 */ 906 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 907 pending); 908 909 uap->port.icount.rx += dma_count; 910 if (dma_count < pending) 911 dev_warn(uap->port.dev, 912 "couldn't insert all characters (TTY is full?)\n"); 913 } 914 915 /* Reset the last_residue for Rx DMA poll */ 916 if (uap->dmarx.poll_rate) 917 dmarx->last_residue = sgbuf->sg.length; 918 919 /* 920 * Only continue with trying to read the FIFO if all DMA chars have 921 * been taken first. 922 */ 923 if (dma_count == pending && readfifo) { 924 /* Clear any error flags */ 925 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 926 UART011_FEIS, uap, REG_ICR); 927 928 /* 929 * If we read all the DMA'd characters, and we had an 930 * incomplete buffer, that could be due to an rx error, or 931 * maybe we just timed out. Read any pending chars and check 932 * the error status. 933 * 934 * Error conditions will only occur in the FIFO, these will 935 * trigger an immediate interrupt and stop the DMA job, so we 936 * will always find the error in the FIFO, never in the DMA 937 * buffer. 938 */ 939 fifotaken = pl011_fifo_to_tty(uap); 940 } 941 942 spin_unlock(&uap->port.lock); 943 dev_vdbg(uap->port.dev, 944 "Took %d chars from DMA buffer and %d chars from the FIFO\n", 945 dma_count, fifotaken); 946 tty_flip_buffer_push(port); 947 spin_lock(&uap->port.lock); 948 } 949 950 static void pl011_dma_rx_irq(struct uart_amba_port *uap) 951 { 952 struct pl011_dmarx_data *dmarx = &uap->dmarx; 953 struct dma_chan *rxchan = dmarx->chan; 954 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 955 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 956 size_t pending; 957 struct dma_tx_state state; 958 enum dma_status dmastat; 959 960 /* 961 * Pause the transfer so we can trust the current counter, 962 * do this before we pause the PL011 block, else we may 963 * overflow the FIFO. 964 */ 965 if (dmaengine_pause(rxchan)) 966 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 967 dmastat = rxchan->device->device_tx_status(rxchan, 968 dmarx->cookie, &state); 969 if (dmastat != DMA_PAUSED) 970 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 971 972 /* Disable RX DMA - incoming data will wait in the FIFO */ 973 uap->dmacr &= ~UART011_RXDMAE; 974 pl011_write(uap->dmacr, uap, REG_DMACR); 975 uap->dmarx.running = false; 976 977 pending = sgbuf->sg.length - state.residue; 978 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 979 /* Then we terminate the transfer - we now know our residue */ 980 dmaengine_terminate_all(rxchan); 981 982 /* 983 * This will take the chars we have so far and insert 984 * into the framework. 985 */ 986 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); 987 988 /* Switch buffer & re-trigger DMA job */ 989 dmarx->use_buf_b = !dmarx->use_buf_b; 990 if (pl011_dma_rx_trigger_dma(uap)) { 991 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 992 "fall back to interrupt mode\n"); 993 uap->im |= UART011_RXIM; 994 pl011_write(uap->im, uap, REG_IMSC); 995 } 996 } 997 998 static void pl011_dma_rx_callback(void *data) 999 { 1000 struct uart_amba_port *uap = data; 1001 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1002 struct dma_chan *rxchan = dmarx->chan; 1003 bool lastbuf = dmarx->use_buf_b; 1004 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 1005 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 1006 size_t pending; 1007 struct dma_tx_state state; 1008 int ret; 1009 1010 /* 1011 * This completion interrupt occurs typically when the 1012 * RX buffer is totally stuffed but no timeout has yet 1013 * occurred. When that happens, we just want the RX 1014 * routine to flush out the secondary DMA buffer while 1015 * we immediately trigger the next DMA job. 1016 */ 1017 spin_lock_irq(&uap->port.lock); 1018 /* 1019 * Rx data can be taken by the UART interrupts during 1020 * the DMA irq handler. So we check the residue here. 1021 */ 1022 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1023 pending = sgbuf->sg.length - state.residue; 1024 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 1025 /* Then we terminate the transfer - we now know our residue */ 1026 dmaengine_terminate_all(rxchan); 1027 1028 uap->dmarx.running = false; 1029 dmarx->use_buf_b = !lastbuf; 1030 ret = pl011_dma_rx_trigger_dma(uap); 1031 1032 pl011_dma_rx_chars(uap, pending, lastbuf, false); 1033 spin_unlock_irq(&uap->port.lock); 1034 /* 1035 * Do this check after we picked the DMA chars so we don't 1036 * get some IRQ immediately from RX. 1037 */ 1038 if (ret) { 1039 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 1040 "fall back to interrupt mode\n"); 1041 uap->im |= UART011_RXIM; 1042 pl011_write(uap->im, uap, REG_IMSC); 1043 } 1044 } 1045 1046 /* 1047 * Stop accepting received characters, when we're shutting down or 1048 * suspending this port. 1049 * Locking: called with port lock held and IRQs disabled. 1050 */ 1051 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1052 { 1053 /* FIXME. Just disable the DMA enable */ 1054 uap->dmacr &= ~UART011_RXDMAE; 1055 pl011_write(uap->dmacr, uap, REG_DMACR); 1056 } 1057 1058 /* 1059 * Timer handler for Rx DMA polling. 1060 * Every polling, It checks the residue in the dma buffer and transfer 1061 * data to the tty. Also, last_residue is updated for the next polling. 1062 */ 1063 static void pl011_dma_rx_poll(unsigned long args) 1064 { 1065 struct uart_amba_port *uap = (struct uart_amba_port *)args; 1066 struct tty_port *port = &uap->port.state->port; 1067 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1068 struct dma_chan *rxchan = uap->dmarx.chan; 1069 unsigned long flags = 0; 1070 unsigned int dmataken = 0; 1071 unsigned int size = 0; 1072 struct pl011_sgbuf *sgbuf; 1073 int dma_count; 1074 struct dma_tx_state state; 1075 1076 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 1077 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1078 if (likely(state.residue < dmarx->last_residue)) { 1079 dmataken = sgbuf->sg.length - dmarx->last_residue; 1080 size = dmarx->last_residue - state.residue; 1081 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 1082 size); 1083 if (dma_count == size) 1084 dmarx->last_residue = state.residue; 1085 dmarx->last_jiffies = jiffies; 1086 } 1087 tty_flip_buffer_push(port); 1088 1089 /* 1090 * If no data is received in poll_timeout, the driver will fall back 1091 * to interrupt mode. We will retrigger DMA at the first interrupt. 1092 */ 1093 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) 1094 > uap->dmarx.poll_timeout) { 1095 1096 spin_lock_irqsave(&uap->port.lock, flags); 1097 pl011_dma_rx_stop(uap); 1098 uap->im |= UART011_RXIM; 1099 pl011_write(uap->im, uap, REG_IMSC); 1100 spin_unlock_irqrestore(&uap->port.lock, flags); 1101 1102 uap->dmarx.running = false; 1103 dmaengine_terminate_all(rxchan); 1104 del_timer(&uap->dmarx.timer); 1105 } else { 1106 mod_timer(&uap->dmarx.timer, 1107 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); 1108 } 1109 } 1110 1111 static void pl011_dma_startup(struct uart_amba_port *uap) 1112 { 1113 int ret; 1114 1115 if (!uap->dma_probed) 1116 pl011_dma_probe(uap); 1117 1118 if (!uap->dmatx.chan) 1119 return; 1120 1121 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); 1122 if (!uap->dmatx.buf) { 1123 dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); 1124 uap->port.fifosize = uap->fifosize; 1125 return; 1126 } 1127 1128 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); 1129 1130 /* The DMA buffer is now the FIFO the TTY subsystem can use */ 1131 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; 1132 uap->using_tx_dma = true; 1133 1134 if (!uap->dmarx.chan) 1135 goto skip_rx; 1136 1137 /* Allocate and map DMA RX buffers */ 1138 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1139 DMA_FROM_DEVICE); 1140 if (ret) { 1141 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1142 "RX buffer A", ret); 1143 goto skip_rx; 1144 } 1145 1146 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, 1147 DMA_FROM_DEVICE); 1148 if (ret) { 1149 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1150 "RX buffer B", ret); 1151 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1152 DMA_FROM_DEVICE); 1153 goto skip_rx; 1154 } 1155 1156 uap->using_rx_dma = true; 1157 1158 skip_rx: 1159 /* Turn on DMA error (RX/TX will be enabled on demand) */ 1160 uap->dmacr |= UART011_DMAONERR; 1161 pl011_write(uap->dmacr, uap, REG_DMACR); 1162 1163 /* 1164 * ST Micro variants has some specific dma burst threshold 1165 * compensation. Set this to 16 bytes, so burst will only 1166 * be issued above/below 16 bytes. 1167 */ 1168 if (uap->vendor->dma_threshold) 1169 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, 1170 uap, REG_ST_DMAWM); 1171 1172 if (uap->using_rx_dma) { 1173 if (pl011_dma_rx_trigger_dma(uap)) 1174 dev_dbg(uap->port.dev, "could not trigger initial " 1175 "RX DMA job, fall back to interrupt mode\n"); 1176 if (uap->dmarx.poll_rate) { 1177 init_timer(&(uap->dmarx.timer)); 1178 uap->dmarx.timer.function = pl011_dma_rx_poll; 1179 uap->dmarx.timer.data = (unsigned long)uap; 1180 mod_timer(&uap->dmarx.timer, 1181 jiffies + 1182 msecs_to_jiffies(uap->dmarx.poll_rate)); 1183 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1184 uap->dmarx.last_jiffies = jiffies; 1185 } 1186 } 1187 } 1188 1189 static void pl011_dma_shutdown(struct uart_amba_port *uap) 1190 { 1191 if (!(uap->using_tx_dma || uap->using_rx_dma)) 1192 return; 1193 1194 /* Disable RX and TX DMA */ 1195 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) 1196 cpu_relax(); 1197 1198 spin_lock_irq(&uap->port.lock); 1199 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); 1200 pl011_write(uap->dmacr, uap, REG_DMACR); 1201 spin_unlock_irq(&uap->port.lock); 1202 1203 if (uap->using_tx_dma) { 1204 /* In theory, this should already be done by pl011_dma_flush_buffer */ 1205 dmaengine_terminate_all(uap->dmatx.chan); 1206 if (uap->dmatx.queued) { 1207 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 1208 DMA_TO_DEVICE); 1209 uap->dmatx.queued = false; 1210 } 1211 1212 kfree(uap->dmatx.buf); 1213 uap->using_tx_dma = false; 1214 } 1215 1216 if (uap->using_rx_dma) { 1217 dmaengine_terminate_all(uap->dmarx.chan); 1218 /* Clean up the RX DMA */ 1219 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); 1220 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); 1221 if (uap->dmarx.poll_rate) 1222 del_timer_sync(&uap->dmarx.timer); 1223 uap->using_rx_dma = false; 1224 } 1225 } 1226 1227 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1228 { 1229 return uap->using_rx_dma; 1230 } 1231 1232 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1233 { 1234 return uap->using_rx_dma && uap->dmarx.running; 1235 } 1236 1237 #else 1238 /* Blank functions if the DMA engine is not available */ 1239 static inline void pl011_dma_probe(struct uart_amba_port *uap) 1240 { 1241 } 1242 1243 static inline void pl011_dma_remove(struct uart_amba_port *uap) 1244 { 1245 } 1246 1247 static inline void pl011_dma_startup(struct uart_amba_port *uap) 1248 { 1249 } 1250 1251 static inline void pl011_dma_shutdown(struct uart_amba_port *uap) 1252 { 1253 } 1254 1255 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) 1256 { 1257 return false; 1258 } 1259 1260 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 1261 { 1262 } 1263 1264 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 1265 { 1266 return false; 1267 } 1268 1269 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) 1270 { 1271 } 1272 1273 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1274 { 1275 } 1276 1277 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 1278 { 1279 return -EIO; 1280 } 1281 1282 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1283 { 1284 return false; 1285 } 1286 1287 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1288 { 1289 return false; 1290 } 1291 1292 #define pl011_dma_flush_buffer NULL 1293 #endif 1294 1295 static void pl011_stop_tx(struct uart_port *port) 1296 { 1297 struct uart_amba_port *uap = 1298 container_of(port, struct uart_amba_port, port); 1299 1300 uap->im &= ~UART011_TXIM; 1301 pl011_write(uap->im, uap, REG_IMSC); 1302 pl011_dma_tx_stop(uap); 1303 } 1304 1305 static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); 1306 1307 /* Start TX with programmed I/O only (no DMA) */ 1308 static void pl011_start_tx_pio(struct uart_amba_port *uap) 1309 { 1310 uap->im |= UART011_TXIM; 1311 pl011_write(uap->im, uap, REG_IMSC); 1312 pl011_tx_chars(uap, false); 1313 } 1314 1315 static void pl011_start_tx(struct uart_port *port) 1316 { 1317 struct uart_amba_port *uap = 1318 container_of(port, struct uart_amba_port, port); 1319 1320 if (!pl011_dma_tx_start(uap)) 1321 pl011_start_tx_pio(uap); 1322 } 1323 1324 static void pl011_stop_rx(struct uart_port *port) 1325 { 1326 struct uart_amba_port *uap = 1327 container_of(port, struct uart_amba_port, port); 1328 1329 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| 1330 UART011_PEIM|UART011_BEIM|UART011_OEIM); 1331 pl011_write(uap->im, uap, REG_IMSC); 1332 1333 pl011_dma_rx_stop(uap); 1334 } 1335 1336 static void pl011_enable_ms(struct uart_port *port) 1337 { 1338 struct uart_amba_port *uap = 1339 container_of(port, struct uart_amba_port, port); 1340 1341 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; 1342 pl011_write(uap->im, uap, REG_IMSC); 1343 } 1344 1345 static void pl011_rx_chars(struct uart_amba_port *uap) 1346 __releases(&uap->port.lock) 1347 __acquires(&uap->port.lock) 1348 { 1349 pl011_fifo_to_tty(uap); 1350 1351 spin_unlock(&uap->port.lock); 1352 tty_flip_buffer_push(&uap->port.state->port); 1353 /* 1354 * If we were temporarily out of DMA mode for a while, 1355 * attempt to switch back to DMA mode again. 1356 */ 1357 if (pl011_dma_rx_available(uap)) { 1358 if (pl011_dma_rx_trigger_dma(uap)) { 1359 dev_dbg(uap->port.dev, "could not trigger RX DMA job " 1360 "fall back to interrupt mode again\n"); 1361 uap->im |= UART011_RXIM; 1362 pl011_write(uap->im, uap, REG_IMSC); 1363 } else { 1364 #ifdef CONFIG_DMA_ENGINE 1365 /* Start Rx DMA poll */ 1366 if (uap->dmarx.poll_rate) { 1367 uap->dmarx.last_jiffies = jiffies; 1368 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1369 mod_timer(&uap->dmarx.timer, 1370 jiffies + 1371 msecs_to_jiffies(uap->dmarx.poll_rate)); 1372 } 1373 #endif 1374 } 1375 } 1376 spin_lock(&uap->port.lock); 1377 } 1378 1379 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, 1380 bool from_irq) 1381 { 1382 if (unlikely(!from_irq) && 1383 pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1384 return false; /* unable to transmit character */ 1385 1386 pl011_write(c, uap, REG_DR); 1387 uap->port.icount.tx++; 1388 1389 return true; 1390 } 1391 1392 static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) 1393 { 1394 struct circ_buf *xmit = &uap->port.state->xmit; 1395 int count = uap->fifosize >> 1; 1396 1397 if (uap->port.x_char) { 1398 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) 1399 return; 1400 uap->port.x_char = 0; 1401 --count; 1402 } 1403 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { 1404 pl011_stop_tx(&uap->port); 1405 return; 1406 } 1407 1408 /* If we are using DMA mode, try to send some characters. */ 1409 if (pl011_dma_tx_irq(uap)) 1410 return; 1411 1412 do { 1413 if (likely(from_irq) && count-- == 0) 1414 break; 1415 1416 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) 1417 break; 1418 1419 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1420 } while (!uart_circ_empty(xmit)); 1421 1422 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1423 uart_write_wakeup(&uap->port); 1424 1425 if (uart_circ_empty(xmit)) 1426 pl011_stop_tx(&uap->port); 1427 } 1428 1429 static void pl011_modem_status(struct uart_amba_port *uap) 1430 { 1431 unsigned int status, delta; 1432 1433 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1434 1435 delta = status ^ uap->old_status; 1436 uap->old_status = status; 1437 1438 if (!delta) 1439 return; 1440 1441 if (delta & UART01x_FR_DCD) 1442 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 1443 1444 if (delta & uap->vendor->fr_dsr) 1445 uap->port.icount.dsr++; 1446 1447 if (delta & uap->vendor->fr_cts) 1448 uart_handle_cts_change(&uap->port, 1449 status & uap->vendor->fr_cts); 1450 1451 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 1452 } 1453 1454 static void check_apply_cts_event_workaround(struct uart_amba_port *uap) 1455 { 1456 unsigned int dummy_read; 1457 1458 if (!uap->vendor->cts_event_workaround) 1459 return; 1460 1461 /* workaround to make sure that all bits are unlocked.. */ 1462 pl011_write(0x00, uap, REG_ICR); 1463 1464 /* 1465 * WA: introduce 26ns(1 uart clk) delay before W1C; 1466 * single apb access will incur 2 pclk(133.12Mhz) delay, 1467 * so add 2 dummy reads 1468 */ 1469 dummy_read = pl011_read(uap, REG_ICR); 1470 dummy_read = pl011_read(uap, REG_ICR); 1471 } 1472 1473 static irqreturn_t pl011_int(int irq, void *dev_id) 1474 { 1475 struct uart_amba_port *uap = dev_id; 1476 unsigned long flags; 1477 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 1478 u16 imsc; 1479 int handled = 0; 1480 1481 spin_lock_irqsave(&uap->port.lock, flags); 1482 imsc = pl011_read(uap, REG_IMSC); 1483 status = pl011_read(uap, REG_RIS) & imsc; 1484 if (status) { 1485 do { 1486 check_apply_cts_event_workaround(uap); 1487 1488 pl011_write(status & ~(UART011_TXIS|UART011_RTIS| 1489 UART011_RXIS), 1490 uap, REG_ICR); 1491 1492 if (status & (UART011_RTIS|UART011_RXIS)) { 1493 if (pl011_dma_rx_running(uap)) 1494 pl011_dma_rx_irq(uap); 1495 else 1496 pl011_rx_chars(uap); 1497 } 1498 if (status & (UART011_DSRMIS|UART011_DCDMIS| 1499 UART011_CTSMIS|UART011_RIMIS)) 1500 pl011_modem_status(uap); 1501 if (status & UART011_TXIS) 1502 pl011_tx_chars(uap, true); 1503 1504 if (pass_counter-- == 0) 1505 break; 1506 1507 status = pl011_read(uap, REG_RIS) & imsc; 1508 } while (status != 0); 1509 handled = 1; 1510 } 1511 1512 spin_unlock_irqrestore(&uap->port.lock, flags); 1513 1514 return IRQ_RETVAL(handled); 1515 } 1516 1517 static unsigned int pl011_tx_empty(struct uart_port *port) 1518 { 1519 struct uart_amba_port *uap = 1520 container_of(port, struct uart_amba_port, port); 1521 unsigned int status = pl011_read(uap, REG_FR); 1522 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? 1523 0 : TIOCSER_TEMT; 1524 } 1525 1526 static unsigned int pl011_get_mctrl(struct uart_port *port) 1527 { 1528 struct uart_amba_port *uap = 1529 container_of(port, struct uart_amba_port, port); 1530 unsigned int result = 0; 1531 unsigned int status = pl011_read(uap, REG_FR); 1532 1533 #define TIOCMBIT(uartbit, tiocmbit) \ 1534 if (status & uartbit) \ 1535 result |= tiocmbit 1536 1537 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); 1538 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR); 1539 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS); 1540 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG); 1541 #undef TIOCMBIT 1542 return result; 1543 } 1544 1545 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) 1546 { 1547 struct uart_amba_port *uap = 1548 container_of(port, struct uart_amba_port, port); 1549 unsigned int cr; 1550 1551 cr = pl011_read(uap, REG_CR); 1552 1553 #define TIOCMBIT(tiocmbit, uartbit) \ 1554 if (mctrl & tiocmbit) \ 1555 cr |= uartbit; \ 1556 else \ 1557 cr &= ~uartbit 1558 1559 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); 1560 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); 1561 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); 1562 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); 1563 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); 1564 1565 if (uap->autorts) { 1566 /* We need to disable auto-RTS if we want to turn RTS off */ 1567 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); 1568 } 1569 #undef TIOCMBIT 1570 1571 pl011_write(cr, uap, REG_CR); 1572 } 1573 1574 static void pl011_break_ctl(struct uart_port *port, int break_state) 1575 { 1576 struct uart_amba_port *uap = 1577 container_of(port, struct uart_amba_port, port); 1578 unsigned long flags; 1579 unsigned int lcr_h; 1580 1581 spin_lock_irqsave(&uap->port.lock, flags); 1582 lcr_h = pl011_read(uap, REG_LCRH_TX); 1583 if (break_state == -1) 1584 lcr_h |= UART01x_LCRH_BRK; 1585 else 1586 lcr_h &= ~UART01x_LCRH_BRK; 1587 pl011_write(lcr_h, uap, REG_LCRH_TX); 1588 spin_unlock_irqrestore(&uap->port.lock, flags); 1589 } 1590 1591 #ifdef CONFIG_CONSOLE_POLL 1592 1593 static void pl011_quiesce_irqs(struct uart_port *port) 1594 { 1595 struct uart_amba_port *uap = 1596 container_of(port, struct uart_amba_port, port); 1597 1598 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); 1599 /* 1600 * There is no way to clear TXIM as this is "ready to transmit IRQ", so 1601 * we simply mask it. start_tx() will unmask it. 1602 * 1603 * Note we can race with start_tx(), and if the race happens, the 1604 * polling user might get another interrupt just after we clear it. 1605 * But it should be OK and can happen even w/o the race, e.g. 1606 * controller immediately got some new data and raised the IRQ. 1607 * 1608 * And whoever uses polling routines assumes that it manages the device 1609 * (including tx queue), so we're also fine with start_tx()'s caller 1610 * side. 1611 */ 1612 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, 1613 REG_IMSC); 1614 } 1615 1616 static int pl011_get_poll_char(struct uart_port *port) 1617 { 1618 struct uart_amba_port *uap = 1619 container_of(port, struct uart_amba_port, port); 1620 unsigned int status; 1621 1622 /* 1623 * The caller might need IRQs lowered, e.g. if used with KDB NMI 1624 * debugger. 1625 */ 1626 pl011_quiesce_irqs(port); 1627 1628 status = pl011_read(uap, REG_FR); 1629 if (status & UART01x_FR_RXFE) 1630 return NO_POLL_CHAR; 1631 1632 return pl011_read(uap, REG_DR); 1633 } 1634 1635 static void pl011_put_poll_char(struct uart_port *port, 1636 unsigned char ch) 1637 { 1638 struct uart_amba_port *uap = 1639 container_of(port, struct uart_amba_port, port); 1640 1641 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1642 cpu_relax(); 1643 1644 pl011_write(ch, uap, REG_DR); 1645 } 1646 1647 #endif /* CONFIG_CONSOLE_POLL */ 1648 1649 static int pl011_hwinit(struct uart_port *port) 1650 { 1651 struct uart_amba_port *uap = 1652 container_of(port, struct uart_amba_port, port); 1653 int retval; 1654 1655 /* Optionaly enable pins to be muxed in and configured */ 1656 pinctrl_pm_select_default_state(port->dev); 1657 1658 /* 1659 * Try to enable the clock producer. 1660 */ 1661 retval = clk_prepare_enable(uap->clk); 1662 if (retval) 1663 return retval; 1664 1665 uap->port.uartclk = clk_get_rate(uap->clk); 1666 1667 /* Clear pending error and receive interrupts */ 1668 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 1669 UART011_FEIS | UART011_RTIS | UART011_RXIS, 1670 uap, REG_ICR); 1671 1672 /* 1673 * Save interrupts enable mask, and enable RX interrupts in case if 1674 * the interrupt is used for NMI entry. 1675 */ 1676 uap->im = pl011_read(uap, REG_IMSC); 1677 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); 1678 1679 if (dev_get_platdata(uap->port.dev)) { 1680 struct amba_pl011_data *plat; 1681 1682 plat = dev_get_platdata(uap->port.dev); 1683 if (plat->init) 1684 plat->init(); 1685 } 1686 return 0; 1687 } 1688 1689 static bool pl011_split_lcrh(const struct uart_amba_port *uap) 1690 { 1691 return pl011_reg_to_offset(uap, REG_LCRH_RX) != 1692 pl011_reg_to_offset(uap, REG_LCRH_TX); 1693 } 1694 1695 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) 1696 { 1697 pl011_write(lcr_h, uap, REG_LCRH_RX); 1698 if (pl011_split_lcrh(uap)) { 1699 int i; 1700 /* 1701 * Wait 10 PCLKs before writing LCRH_TX register, 1702 * to get this delay write read only register 10 times 1703 */ 1704 for (i = 0; i < 10; ++i) 1705 pl011_write(0xff, uap, REG_MIS); 1706 pl011_write(lcr_h, uap, REG_LCRH_TX); 1707 } 1708 } 1709 1710 static int pl011_allocate_irq(struct uart_amba_port *uap) 1711 { 1712 pl011_write(uap->im, uap, REG_IMSC); 1713 1714 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); 1715 } 1716 1717 /* 1718 * Enable interrupts, only timeouts when using DMA 1719 * if initial RX DMA job failed, start in interrupt mode 1720 * as well. 1721 */ 1722 static void pl011_enable_interrupts(struct uart_amba_port *uap) 1723 { 1724 spin_lock_irq(&uap->port.lock); 1725 1726 /* Clear out any spuriously appearing RX interrupts */ 1727 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); 1728 uap->im = UART011_RTIM; 1729 if (!pl011_dma_rx_running(uap)) 1730 uap->im |= UART011_RXIM; 1731 pl011_write(uap->im, uap, REG_IMSC); 1732 spin_unlock_irq(&uap->port.lock); 1733 } 1734 1735 static int pl011_startup(struct uart_port *port) 1736 { 1737 struct uart_amba_port *uap = 1738 container_of(port, struct uart_amba_port, port); 1739 unsigned int cr; 1740 int retval; 1741 1742 retval = pl011_hwinit(port); 1743 if (retval) 1744 goto clk_dis; 1745 1746 retval = pl011_allocate_irq(uap); 1747 if (retval) 1748 goto clk_dis; 1749 1750 pl011_write(uap->vendor->ifls, uap, REG_IFLS); 1751 1752 spin_lock_irq(&uap->port.lock); 1753 1754 /* restore RTS and DTR */ 1755 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); 1756 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; 1757 pl011_write(cr, uap, REG_CR); 1758 1759 spin_unlock_irq(&uap->port.lock); 1760 1761 /* 1762 * initialise the old status of the modem signals 1763 */ 1764 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1765 1766 /* Startup DMA */ 1767 pl011_dma_startup(uap); 1768 1769 pl011_enable_interrupts(uap); 1770 1771 return 0; 1772 1773 clk_dis: 1774 clk_disable_unprepare(uap->clk); 1775 return retval; 1776 } 1777 1778 static int sbsa_uart_startup(struct uart_port *port) 1779 { 1780 struct uart_amba_port *uap = 1781 container_of(port, struct uart_amba_port, port); 1782 int retval; 1783 1784 retval = pl011_hwinit(port); 1785 if (retval) 1786 return retval; 1787 1788 retval = pl011_allocate_irq(uap); 1789 if (retval) 1790 return retval; 1791 1792 /* The SBSA UART does not support any modem status lines. */ 1793 uap->old_status = 0; 1794 1795 pl011_enable_interrupts(uap); 1796 1797 return 0; 1798 } 1799 1800 static void pl011_shutdown_channel(struct uart_amba_port *uap, 1801 unsigned int lcrh) 1802 { 1803 unsigned long val; 1804 1805 val = pl011_read(uap, lcrh); 1806 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); 1807 pl011_write(val, uap, lcrh); 1808 } 1809 1810 /* 1811 * disable the port. It should not disable RTS and DTR. 1812 * Also RTS and DTR state should be preserved to restore 1813 * it during startup(). 1814 */ 1815 static void pl011_disable_uart(struct uart_amba_port *uap) 1816 { 1817 unsigned int cr; 1818 1819 uap->autorts = false; 1820 spin_lock_irq(&uap->port.lock); 1821 cr = pl011_read(uap, REG_CR); 1822 uap->old_cr = cr; 1823 cr &= UART011_CR_RTS | UART011_CR_DTR; 1824 cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 1825 pl011_write(cr, uap, REG_CR); 1826 spin_unlock_irq(&uap->port.lock); 1827 1828 /* 1829 * disable break condition and fifos 1830 */ 1831 pl011_shutdown_channel(uap, REG_LCRH_RX); 1832 if (pl011_split_lcrh(uap)) 1833 pl011_shutdown_channel(uap, REG_LCRH_TX); 1834 } 1835 1836 static void pl011_disable_interrupts(struct uart_amba_port *uap) 1837 { 1838 spin_lock_irq(&uap->port.lock); 1839 1840 /* mask all interrupts and clear all pending ones */ 1841 uap->im = 0; 1842 pl011_write(uap->im, uap, REG_IMSC); 1843 pl011_write(0xffff, uap, REG_ICR); 1844 1845 spin_unlock_irq(&uap->port.lock); 1846 } 1847 1848 static void pl011_shutdown(struct uart_port *port) 1849 { 1850 struct uart_amba_port *uap = 1851 container_of(port, struct uart_amba_port, port); 1852 1853 pl011_disable_interrupts(uap); 1854 1855 pl011_dma_shutdown(uap); 1856 1857 free_irq(uap->port.irq, uap); 1858 1859 pl011_disable_uart(uap); 1860 1861 /* 1862 * Shut down the clock producer 1863 */ 1864 clk_disable_unprepare(uap->clk); 1865 /* Optionally let pins go into sleep states */ 1866 pinctrl_pm_select_sleep_state(port->dev); 1867 1868 if (dev_get_platdata(uap->port.dev)) { 1869 struct amba_pl011_data *plat; 1870 1871 plat = dev_get_platdata(uap->port.dev); 1872 if (plat->exit) 1873 plat->exit(); 1874 } 1875 1876 if (uap->port.ops->flush_buffer) 1877 uap->port.ops->flush_buffer(port); 1878 } 1879 1880 static void sbsa_uart_shutdown(struct uart_port *port) 1881 { 1882 struct uart_amba_port *uap = 1883 container_of(port, struct uart_amba_port, port); 1884 1885 pl011_disable_interrupts(uap); 1886 1887 free_irq(uap->port.irq, uap); 1888 1889 if (uap->port.ops->flush_buffer) 1890 uap->port.ops->flush_buffer(port); 1891 } 1892 1893 static void 1894 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) 1895 { 1896 port->read_status_mask = UART011_DR_OE | 255; 1897 if (termios->c_iflag & INPCK) 1898 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; 1899 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1900 port->read_status_mask |= UART011_DR_BE; 1901 1902 /* 1903 * Characters to ignore 1904 */ 1905 port->ignore_status_mask = 0; 1906 if (termios->c_iflag & IGNPAR) 1907 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; 1908 if (termios->c_iflag & IGNBRK) { 1909 port->ignore_status_mask |= UART011_DR_BE; 1910 /* 1911 * If we're ignoring parity and break indicators, 1912 * ignore overruns too (for real raw support). 1913 */ 1914 if (termios->c_iflag & IGNPAR) 1915 port->ignore_status_mask |= UART011_DR_OE; 1916 } 1917 1918 /* 1919 * Ignore all characters if CREAD is not set. 1920 */ 1921 if ((termios->c_cflag & CREAD) == 0) 1922 port->ignore_status_mask |= UART_DUMMY_DR_RX; 1923 } 1924 1925 static void 1926 pl011_set_termios(struct uart_port *port, struct ktermios *termios, 1927 struct ktermios *old) 1928 { 1929 struct uart_amba_port *uap = 1930 container_of(port, struct uart_amba_port, port); 1931 unsigned int lcr_h, old_cr; 1932 unsigned long flags; 1933 unsigned int baud, quot, clkdiv; 1934 1935 if (uap->vendor->oversampling) 1936 clkdiv = 8; 1937 else 1938 clkdiv = 16; 1939 1940 /* 1941 * Ask the core to calculate the divisor for us. 1942 */ 1943 baud = uart_get_baud_rate(port, termios, old, 0, 1944 port->uartclk / clkdiv); 1945 #ifdef CONFIG_DMA_ENGINE 1946 /* 1947 * Adjust RX DMA polling rate with baud rate if not specified. 1948 */ 1949 if (uap->dmarx.auto_poll_rate) 1950 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); 1951 #endif 1952 1953 if (baud > port->uartclk/16) 1954 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); 1955 else 1956 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); 1957 1958 switch (termios->c_cflag & CSIZE) { 1959 case CS5: 1960 lcr_h = UART01x_LCRH_WLEN_5; 1961 break; 1962 case CS6: 1963 lcr_h = UART01x_LCRH_WLEN_6; 1964 break; 1965 case CS7: 1966 lcr_h = UART01x_LCRH_WLEN_7; 1967 break; 1968 default: // CS8 1969 lcr_h = UART01x_LCRH_WLEN_8; 1970 break; 1971 } 1972 if (termios->c_cflag & CSTOPB) 1973 lcr_h |= UART01x_LCRH_STP2; 1974 if (termios->c_cflag & PARENB) { 1975 lcr_h |= UART01x_LCRH_PEN; 1976 if (!(termios->c_cflag & PARODD)) 1977 lcr_h |= UART01x_LCRH_EPS; 1978 if (termios->c_cflag & CMSPAR) 1979 lcr_h |= UART011_LCRH_SPS; 1980 } 1981 if (uap->fifosize > 1) 1982 lcr_h |= UART01x_LCRH_FEN; 1983 1984 spin_lock_irqsave(&port->lock, flags); 1985 1986 /* 1987 * Update the per-port timeout. 1988 */ 1989 uart_update_timeout(port, termios->c_cflag, baud); 1990 1991 pl011_setup_status_masks(port, termios); 1992 1993 if (UART_ENABLE_MS(port, termios->c_cflag)) 1994 pl011_enable_ms(port); 1995 1996 /* first, disable everything */ 1997 old_cr = pl011_read(uap, REG_CR); 1998 pl011_write(0, uap, REG_CR); 1999 2000 if (termios->c_cflag & CRTSCTS) { 2001 if (old_cr & UART011_CR_RTS) 2002 old_cr |= UART011_CR_RTSEN; 2003 2004 old_cr |= UART011_CR_CTSEN; 2005 uap->autorts = true; 2006 } else { 2007 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); 2008 uap->autorts = false; 2009 } 2010 2011 if (uap->vendor->oversampling) { 2012 if (baud > port->uartclk / 16) 2013 old_cr |= ST_UART011_CR_OVSFACT; 2014 else 2015 old_cr &= ~ST_UART011_CR_OVSFACT; 2016 } 2017 2018 /* 2019 * Workaround for the ST Micro oversampling variants to 2020 * increase the bitrate slightly, by lowering the divisor, 2021 * to avoid delayed sampling of start bit at high speeds, 2022 * else we see data corruption. 2023 */ 2024 if (uap->vendor->oversampling) { 2025 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) 2026 quot -= 1; 2027 else if ((baud > 3250000) && (quot > 2)) 2028 quot -= 2; 2029 } 2030 /* Set baud rate */ 2031 pl011_write(quot & 0x3f, uap, REG_FBRD); 2032 pl011_write(quot >> 6, uap, REG_IBRD); 2033 2034 /* 2035 * ----------v----------v----------v----------v----- 2036 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER 2037 * REG_FBRD & REG_IBRD. 2038 * ----------^----------^----------^----------^----- 2039 */ 2040 pl011_write_lcr_h(uap, lcr_h); 2041 pl011_write(old_cr, uap, REG_CR); 2042 2043 spin_unlock_irqrestore(&port->lock, flags); 2044 } 2045 2046 static void 2047 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, 2048 struct ktermios *old) 2049 { 2050 struct uart_amba_port *uap = 2051 container_of(port, struct uart_amba_port, port); 2052 unsigned long flags; 2053 2054 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); 2055 2056 /* The SBSA UART only supports 8n1 without hardware flow control. */ 2057 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 2058 termios->c_cflag &= ~(CMSPAR | CRTSCTS); 2059 termios->c_cflag |= CS8 | CLOCAL; 2060 2061 spin_lock_irqsave(&port->lock, flags); 2062 uart_update_timeout(port, CS8, uap->fixed_baud); 2063 pl011_setup_status_masks(port, termios); 2064 spin_unlock_irqrestore(&port->lock, flags); 2065 } 2066 2067 static const char *pl011_type(struct uart_port *port) 2068 { 2069 struct uart_amba_port *uap = 2070 container_of(port, struct uart_amba_port, port); 2071 return uap->port.type == PORT_AMBA ? uap->type : NULL; 2072 } 2073 2074 /* 2075 * Release the memory region(s) being used by 'port' 2076 */ 2077 static void pl011_release_port(struct uart_port *port) 2078 { 2079 release_mem_region(port->mapbase, SZ_4K); 2080 } 2081 2082 /* 2083 * Request the memory region(s) being used by 'port' 2084 */ 2085 static int pl011_request_port(struct uart_port *port) 2086 { 2087 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") 2088 != NULL ? 0 : -EBUSY; 2089 } 2090 2091 /* 2092 * Configure/autoconfigure the port. 2093 */ 2094 static void pl011_config_port(struct uart_port *port, int flags) 2095 { 2096 if (flags & UART_CONFIG_TYPE) { 2097 port->type = PORT_AMBA; 2098 pl011_request_port(port); 2099 } 2100 } 2101 2102 /* 2103 * verify the new serial_struct (for TIOCSSERIAL). 2104 */ 2105 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) 2106 { 2107 int ret = 0; 2108 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 2109 ret = -EINVAL; 2110 if (ser->irq < 0 || ser->irq >= nr_irqs) 2111 ret = -EINVAL; 2112 if (ser->baud_base < 9600) 2113 ret = -EINVAL; 2114 return ret; 2115 } 2116 2117 static struct uart_ops amba_pl011_pops = { 2118 .tx_empty = pl011_tx_empty, 2119 .set_mctrl = pl011_set_mctrl, 2120 .get_mctrl = pl011_get_mctrl, 2121 .stop_tx = pl011_stop_tx, 2122 .start_tx = pl011_start_tx, 2123 .stop_rx = pl011_stop_rx, 2124 .enable_ms = pl011_enable_ms, 2125 .break_ctl = pl011_break_ctl, 2126 .startup = pl011_startup, 2127 .shutdown = pl011_shutdown, 2128 .flush_buffer = pl011_dma_flush_buffer, 2129 .set_termios = pl011_set_termios, 2130 .type = pl011_type, 2131 .release_port = pl011_release_port, 2132 .request_port = pl011_request_port, 2133 .config_port = pl011_config_port, 2134 .verify_port = pl011_verify_port, 2135 #ifdef CONFIG_CONSOLE_POLL 2136 .poll_init = pl011_hwinit, 2137 .poll_get_char = pl011_get_poll_char, 2138 .poll_put_char = pl011_put_poll_char, 2139 #endif 2140 }; 2141 2142 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 2143 { 2144 } 2145 2146 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) 2147 { 2148 return 0; 2149 } 2150 2151 static const struct uart_ops sbsa_uart_pops = { 2152 .tx_empty = pl011_tx_empty, 2153 .set_mctrl = sbsa_uart_set_mctrl, 2154 .get_mctrl = sbsa_uart_get_mctrl, 2155 .stop_tx = pl011_stop_tx, 2156 .start_tx = pl011_start_tx, 2157 .stop_rx = pl011_stop_rx, 2158 .startup = sbsa_uart_startup, 2159 .shutdown = sbsa_uart_shutdown, 2160 .set_termios = sbsa_uart_set_termios, 2161 .type = pl011_type, 2162 .release_port = pl011_release_port, 2163 .request_port = pl011_request_port, 2164 .config_port = pl011_config_port, 2165 .verify_port = pl011_verify_port, 2166 #ifdef CONFIG_CONSOLE_POLL 2167 .poll_init = pl011_hwinit, 2168 .poll_get_char = pl011_get_poll_char, 2169 .poll_put_char = pl011_put_poll_char, 2170 #endif 2171 }; 2172 2173 static struct uart_amba_port *amba_ports[UART_NR]; 2174 2175 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE 2176 2177 static void pl011_console_putchar(struct uart_port *port, int ch) 2178 { 2179 struct uart_amba_port *uap = 2180 container_of(port, struct uart_amba_port, port); 2181 2182 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 2183 cpu_relax(); 2184 pl011_write(ch, uap, REG_DR); 2185 } 2186 2187 static void 2188 pl011_console_write(struct console *co, const char *s, unsigned int count) 2189 { 2190 struct uart_amba_port *uap = amba_ports[co->index]; 2191 unsigned int old_cr = 0, new_cr; 2192 unsigned long flags; 2193 int locked = 1; 2194 2195 clk_enable(uap->clk); 2196 2197 local_irq_save(flags); 2198 if (uap->port.sysrq) 2199 locked = 0; 2200 else if (oops_in_progress) 2201 locked = spin_trylock(&uap->port.lock); 2202 else 2203 spin_lock(&uap->port.lock); 2204 2205 /* 2206 * First save the CR then disable the interrupts 2207 */ 2208 if (!uap->vendor->always_enabled) { 2209 old_cr = pl011_read(uap, REG_CR); 2210 new_cr = old_cr & ~UART011_CR_CTSEN; 2211 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 2212 pl011_write(new_cr, uap, REG_CR); 2213 } 2214 2215 uart_console_write(&uap->port, s, count, pl011_console_putchar); 2216 2217 /* 2218 * Finally, wait for transmitter to become empty 2219 * and restore the TCR 2220 */ 2221 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) 2222 cpu_relax(); 2223 if (!uap->vendor->always_enabled) 2224 pl011_write(old_cr, uap, REG_CR); 2225 2226 if (locked) 2227 spin_unlock(&uap->port.lock); 2228 local_irq_restore(flags); 2229 2230 clk_disable(uap->clk); 2231 } 2232 2233 static void __init 2234 pl011_console_get_options(struct uart_amba_port *uap, int *baud, 2235 int *parity, int *bits) 2236 { 2237 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) { 2238 unsigned int lcr_h, ibrd, fbrd; 2239 2240 lcr_h = pl011_read(uap, REG_LCRH_TX); 2241 2242 *parity = 'n'; 2243 if (lcr_h & UART01x_LCRH_PEN) { 2244 if (lcr_h & UART01x_LCRH_EPS) 2245 *parity = 'e'; 2246 else 2247 *parity = 'o'; 2248 } 2249 2250 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 2251 *bits = 7; 2252 else 2253 *bits = 8; 2254 2255 ibrd = pl011_read(uap, REG_IBRD); 2256 fbrd = pl011_read(uap, REG_FBRD); 2257 2258 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); 2259 2260 if (uap->vendor->oversampling) { 2261 if (pl011_read(uap, REG_CR) 2262 & ST_UART011_CR_OVSFACT) 2263 *baud *= 2; 2264 } 2265 } 2266 } 2267 2268 static int __init pl011_console_setup(struct console *co, char *options) 2269 { 2270 struct uart_amba_port *uap; 2271 int baud = 38400; 2272 int bits = 8; 2273 int parity = 'n'; 2274 int flow = 'n'; 2275 int ret; 2276 2277 /* 2278 * Check whether an invalid uart number has been specified, and 2279 * if so, search for the first available port that does have 2280 * console support. 2281 */ 2282 if (co->index >= UART_NR) 2283 co->index = 0; 2284 uap = amba_ports[co->index]; 2285 if (!uap) 2286 return -ENODEV; 2287 2288 /* Allow pins to be muxed in and configured */ 2289 pinctrl_pm_select_default_state(uap->port.dev); 2290 2291 ret = clk_prepare(uap->clk); 2292 if (ret) 2293 return ret; 2294 2295 if (dev_get_platdata(uap->port.dev)) { 2296 struct amba_pl011_data *plat; 2297 2298 plat = dev_get_platdata(uap->port.dev); 2299 if (plat->init) 2300 plat->init(); 2301 } 2302 2303 uap->port.uartclk = clk_get_rate(uap->clk); 2304 2305 if (uap->vendor->fixed_options) { 2306 baud = uap->fixed_baud; 2307 } else { 2308 if (options) 2309 uart_parse_options(options, 2310 &baud, &parity, &bits, &flow); 2311 else 2312 pl011_console_get_options(uap, &baud, &parity, &bits); 2313 } 2314 2315 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 2316 } 2317 2318 static struct uart_driver amba_reg; 2319 static struct console amba_console = { 2320 .name = "ttyAMA", 2321 .write = pl011_console_write, 2322 .device = uart_console_device, 2323 .setup = pl011_console_setup, 2324 .flags = CON_PRINTBUFFER, 2325 .index = -1, 2326 .data = &amba_reg, 2327 }; 2328 2329 #define AMBA_CONSOLE (&amba_console) 2330 2331 static void pl011_putc(struct uart_port *port, int c) 2332 { 2333 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2334 cpu_relax(); 2335 if (port->iotype == UPIO_MEM32) 2336 writel(c, port->membase + UART01x_DR); 2337 else 2338 writeb(c, port->membase + UART01x_DR); 2339 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) 2340 cpu_relax(); 2341 } 2342 2343 static void pl011_early_write(struct console *con, const char *s, unsigned n) 2344 { 2345 struct earlycon_device *dev = con->data; 2346 2347 uart_console_write(&dev->port, s, n, pl011_putc); 2348 } 2349 2350 static int __init pl011_early_console_setup(struct earlycon_device *device, 2351 const char *opt) 2352 { 2353 if (!device->port.membase) 2354 return -ENODEV; 2355 2356 device->con->write = pl011_early_write; 2357 return 0; 2358 } 2359 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); 2360 2361 #else 2362 #define AMBA_CONSOLE NULL 2363 #endif 2364 2365 static struct uart_driver amba_reg = { 2366 .owner = THIS_MODULE, 2367 .driver_name = "ttyAMA", 2368 .dev_name = "ttyAMA", 2369 .major = SERIAL_AMBA_MAJOR, 2370 .minor = SERIAL_AMBA_MINOR, 2371 .nr = UART_NR, 2372 .cons = AMBA_CONSOLE, 2373 }; 2374 2375 static int pl011_probe_dt_alias(int index, struct device *dev) 2376 { 2377 struct device_node *np; 2378 static bool seen_dev_with_alias = false; 2379 static bool seen_dev_without_alias = false; 2380 int ret = index; 2381 2382 if (!IS_ENABLED(CONFIG_OF)) 2383 return ret; 2384 2385 np = dev->of_node; 2386 if (!np) 2387 return ret; 2388 2389 ret = of_alias_get_id(np, "serial"); 2390 if (ret < 0) { 2391 seen_dev_without_alias = true; 2392 ret = index; 2393 } else { 2394 seen_dev_with_alias = true; 2395 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { 2396 dev_warn(dev, "requested serial port %d not available.\n", ret); 2397 ret = index; 2398 } 2399 } 2400 2401 if (seen_dev_with_alias && seen_dev_without_alias) 2402 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); 2403 2404 return ret; 2405 } 2406 2407 /* unregisters the driver also if no more ports are left */ 2408 static void pl011_unregister_port(struct uart_amba_port *uap) 2409 { 2410 int i; 2411 bool busy = false; 2412 2413 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2414 if (amba_ports[i] == uap) 2415 amba_ports[i] = NULL; 2416 else if (amba_ports[i]) 2417 busy = true; 2418 } 2419 pl011_dma_remove(uap); 2420 if (!busy) 2421 uart_unregister_driver(&amba_reg); 2422 } 2423 2424 static int pl011_find_free_port(void) 2425 { 2426 int i; 2427 2428 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2429 if (amba_ports[i] == NULL) 2430 return i; 2431 2432 return -EBUSY; 2433 } 2434 2435 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, 2436 struct resource *mmiobase, int index) 2437 { 2438 void __iomem *base; 2439 2440 base = devm_ioremap_resource(dev, mmiobase); 2441 if (IS_ERR(base)) 2442 return PTR_ERR(base); 2443 2444 index = pl011_probe_dt_alias(index, dev); 2445 2446 uap->old_cr = 0; 2447 uap->port.dev = dev; 2448 uap->port.mapbase = mmiobase->start; 2449 uap->port.membase = base; 2450 uap->port.fifosize = uap->fifosize; 2451 uap->port.flags = UPF_BOOT_AUTOCONF; 2452 uap->port.line = index; 2453 2454 amba_ports[index] = uap; 2455 2456 return 0; 2457 } 2458 2459 static int pl011_register_port(struct uart_amba_port *uap) 2460 { 2461 int ret; 2462 2463 /* Ensure interrupts from this UART are masked and cleared */ 2464 pl011_write(0, uap, REG_IMSC); 2465 pl011_write(0xffff, uap, REG_ICR); 2466 2467 if (!amba_reg.state) { 2468 ret = uart_register_driver(&amba_reg); 2469 if (ret < 0) { 2470 dev_err(uap->port.dev, 2471 "Failed to register AMBA-PL011 driver\n"); 2472 return ret; 2473 } 2474 } 2475 2476 ret = uart_add_one_port(&amba_reg, &uap->port); 2477 if (ret) 2478 pl011_unregister_port(uap); 2479 2480 return ret; 2481 } 2482 2483 static int pl011_probe(struct amba_device *dev, const struct amba_id *id) 2484 { 2485 struct uart_amba_port *uap; 2486 struct vendor_data *vendor = id->data; 2487 int portnr, ret; 2488 2489 portnr = pl011_find_free_port(); 2490 if (portnr < 0) 2491 return portnr; 2492 2493 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), 2494 GFP_KERNEL); 2495 if (!uap) 2496 return -ENOMEM; 2497 2498 uap->clk = devm_clk_get(&dev->dev, NULL); 2499 if (IS_ERR(uap->clk)) 2500 return PTR_ERR(uap->clk); 2501 2502 uap->reg_offset = vendor->reg_offset; 2503 uap->vendor = vendor; 2504 uap->fifosize = vendor->get_fifosize(dev); 2505 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 2506 uap->port.irq = dev->irq[0]; 2507 uap->port.ops = &amba_pl011_pops; 2508 2509 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); 2510 2511 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); 2512 if (ret) 2513 return ret; 2514 2515 amba_set_drvdata(dev, uap); 2516 2517 return pl011_register_port(uap); 2518 } 2519 2520 static int pl011_remove(struct amba_device *dev) 2521 { 2522 struct uart_amba_port *uap = amba_get_drvdata(dev); 2523 2524 uart_remove_one_port(&amba_reg, &uap->port); 2525 pl011_unregister_port(uap); 2526 return 0; 2527 } 2528 2529 #ifdef CONFIG_PM_SLEEP 2530 static int pl011_suspend(struct device *dev) 2531 { 2532 struct uart_amba_port *uap = dev_get_drvdata(dev); 2533 2534 if (!uap) 2535 return -EINVAL; 2536 2537 return uart_suspend_port(&amba_reg, &uap->port); 2538 } 2539 2540 static int pl011_resume(struct device *dev) 2541 { 2542 struct uart_amba_port *uap = dev_get_drvdata(dev); 2543 2544 if (!uap) 2545 return -EINVAL; 2546 2547 return uart_resume_port(&amba_reg, &uap->port); 2548 } 2549 #endif 2550 2551 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); 2552 2553 static int sbsa_uart_probe(struct platform_device *pdev) 2554 { 2555 struct uart_amba_port *uap; 2556 struct resource *r; 2557 int portnr, ret; 2558 int baudrate; 2559 2560 /* 2561 * Check the mandatory baud rate parameter in the DT node early 2562 * so that we can easily exit with the error. 2563 */ 2564 if (pdev->dev.of_node) { 2565 struct device_node *np = pdev->dev.of_node; 2566 2567 ret = of_property_read_u32(np, "current-speed", &baudrate); 2568 if (ret) 2569 return ret; 2570 } else { 2571 baudrate = 115200; 2572 } 2573 2574 portnr = pl011_find_free_port(); 2575 if (portnr < 0) 2576 return portnr; 2577 2578 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), 2579 GFP_KERNEL); 2580 if (!uap) 2581 return -ENOMEM; 2582 2583 ret = platform_get_irq(pdev, 0); 2584 if (ret < 0) { 2585 if (ret != -EPROBE_DEFER) 2586 dev_err(&pdev->dev, "cannot obtain irq\n"); 2587 return ret; 2588 } 2589 uap->port.irq = ret; 2590 2591 uap->reg_offset = vendor_sbsa.reg_offset; 2592 uap->vendor = &vendor_sbsa; 2593 uap->fifosize = 32; 2594 uap->port.iotype = vendor_sbsa.access_32b ? UPIO_MEM32 : UPIO_MEM; 2595 uap->port.ops = &sbsa_uart_pops; 2596 uap->fixed_baud = baudrate; 2597 2598 snprintf(uap->type, sizeof(uap->type), "SBSA"); 2599 2600 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2601 2602 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); 2603 if (ret) 2604 return ret; 2605 2606 platform_set_drvdata(pdev, uap); 2607 2608 return pl011_register_port(uap); 2609 } 2610 2611 static int sbsa_uart_remove(struct platform_device *pdev) 2612 { 2613 struct uart_amba_port *uap = platform_get_drvdata(pdev); 2614 2615 uart_remove_one_port(&amba_reg, &uap->port); 2616 pl011_unregister_port(uap); 2617 return 0; 2618 } 2619 2620 static const struct of_device_id sbsa_uart_of_match[] = { 2621 { .compatible = "arm,sbsa-uart", }, 2622 {}, 2623 }; 2624 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); 2625 2626 static const struct acpi_device_id sbsa_uart_acpi_match[] = { 2627 { "ARMH0011", 0 }, 2628 {}, 2629 }; 2630 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); 2631 2632 static struct platform_driver arm_sbsa_uart_platform_driver = { 2633 .probe = sbsa_uart_probe, 2634 .remove = sbsa_uart_remove, 2635 .driver = { 2636 .name = "sbsa-uart", 2637 .of_match_table = of_match_ptr(sbsa_uart_of_match), 2638 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match), 2639 }, 2640 }; 2641 2642 static struct amba_id pl011_ids[] = { 2643 { 2644 .id = 0x00041011, 2645 .mask = 0x000fffff, 2646 .data = &vendor_arm, 2647 }, 2648 { 2649 .id = 0x00380802, 2650 .mask = 0x00ffffff, 2651 .data = &vendor_st, 2652 }, 2653 { 2654 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe), 2655 .mask = 0x00ffffff, 2656 .data = &vendor_zte, 2657 }, 2658 { 0, 0 }, 2659 }; 2660 2661 MODULE_DEVICE_TABLE(amba, pl011_ids); 2662 2663 static struct amba_driver pl011_driver = { 2664 .drv = { 2665 .name = "uart-pl011", 2666 .pm = &pl011_dev_pm_ops, 2667 }, 2668 .id_table = pl011_ids, 2669 .probe = pl011_probe, 2670 .remove = pl011_remove, 2671 }; 2672 2673 static int __init pl011_init(void) 2674 { 2675 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); 2676 2677 if (platform_driver_register(&arm_sbsa_uart_platform_driver)) 2678 pr_warn("could not register SBSA UART platform driver\n"); 2679 return amba_driver_register(&pl011_driver); 2680 } 2681 2682 static void __exit pl011_exit(void) 2683 { 2684 platform_driver_unregister(&arm_sbsa_uart_platform_driver); 2685 amba_driver_unregister(&pl011_driver); 2686 } 2687 2688 /* 2689 * While this can be a module, if builtin it's most likely the console 2690 * So let's leave module_exit but move module_init to an earlier place 2691 */ 2692 arch_initcall(pl011_init); 2693 module_exit(pl011_exit); 2694 2695 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 2696 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 2697 MODULE_LICENSE("GPL"); 2698