1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for AMBA serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright 1999 ARM Limited 8 * Copyright (C) 2000 Deep Blue Solutions Ltd. 9 * Copyright (C) 2010 ST-Ericsson SA 10 * 11 * This is a generic driver for ARM AMBA-type serial ports. They 12 * have a lot of 16550-like features, but are not register compatible. 13 * Note that although they do have CTS, DCD and DSR inputs, they do 14 * not have an RI input, nor do they have DTR or RTS outputs. If 15 * required, these have to be supplied via some other means (eg, GPIO) 16 * and hooked into this driver. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/ioport.h> 21 #include <linux/init.h> 22 #include <linux/console.h> 23 #include <linux/sysrq.h> 24 #include <linux/device.h> 25 #include <linux/tty.h> 26 #include <linux/tty_flip.h> 27 #include <linux/serial_core.h> 28 #include <linux/serial.h> 29 #include <linux/amba/bus.h> 30 #include <linux/amba/serial.h> 31 #include <linux/clk.h> 32 #include <linux/slab.h> 33 #include <linux/dmaengine.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/scatterlist.h> 36 #include <linux/delay.h> 37 #include <linux/types.h> 38 #include <linux/of.h> 39 #include <linux/of_device.h> 40 #include <linux/pinctrl/consumer.h> 41 #include <linux/sizes.h> 42 #include <linux/io.h> 43 #include <linux/acpi.h> 44 45 #include "amba-pl011.h" 46 47 #define UART_NR 14 48 49 #define SERIAL_AMBA_MAJOR 204 50 #define SERIAL_AMBA_MINOR 64 51 #define SERIAL_AMBA_NR UART_NR 52 53 #define AMBA_ISR_PASS_LIMIT 256 54 55 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) 56 #define UART_DUMMY_DR_RX (1 << 16) 57 58 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = { 59 [REG_DR] = UART01x_DR, 60 [REG_FR] = UART01x_FR, 61 [REG_LCRH_RX] = UART011_LCRH, 62 [REG_LCRH_TX] = UART011_LCRH, 63 [REG_IBRD] = UART011_IBRD, 64 [REG_FBRD] = UART011_FBRD, 65 [REG_CR] = UART011_CR, 66 [REG_IFLS] = UART011_IFLS, 67 [REG_IMSC] = UART011_IMSC, 68 [REG_RIS] = UART011_RIS, 69 [REG_MIS] = UART011_MIS, 70 [REG_ICR] = UART011_ICR, 71 [REG_DMACR] = UART011_DMACR, 72 }; 73 74 /* There is by now at least one vendor with differing details, so handle it */ 75 struct vendor_data { 76 const u16 *reg_offset; 77 unsigned int ifls; 78 unsigned int fr_busy; 79 unsigned int fr_dsr; 80 unsigned int fr_cts; 81 unsigned int fr_ri; 82 unsigned int inv_fr; 83 bool access_32b; 84 bool oversampling; 85 bool dma_threshold; 86 bool cts_event_workaround; 87 bool always_enabled; 88 bool fixed_options; 89 90 unsigned int (*get_fifosize)(struct amba_device *dev); 91 }; 92 93 static unsigned int get_fifosize_arm(struct amba_device *dev) 94 { 95 return amba_rev(dev) < 3 ? 16 : 32; 96 } 97 98 static struct vendor_data vendor_arm = { 99 .reg_offset = pl011_std_offsets, 100 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 101 .fr_busy = UART01x_FR_BUSY, 102 .fr_dsr = UART01x_FR_DSR, 103 .fr_cts = UART01x_FR_CTS, 104 .fr_ri = UART011_FR_RI, 105 .oversampling = false, 106 .dma_threshold = false, 107 .cts_event_workaround = false, 108 .always_enabled = false, 109 .fixed_options = false, 110 .get_fifosize = get_fifosize_arm, 111 }; 112 113 static const struct vendor_data vendor_sbsa = { 114 .reg_offset = pl011_std_offsets, 115 .fr_busy = UART01x_FR_BUSY, 116 .fr_dsr = UART01x_FR_DSR, 117 .fr_cts = UART01x_FR_CTS, 118 .fr_ri = UART011_FR_RI, 119 .access_32b = true, 120 .oversampling = false, 121 .dma_threshold = false, 122 .cts_event_workaround = false, 123 .always_enabled = true, 124 .fixed_options = true, 125 }; 126 127 #ifdef CONFIG_ACPI_SPCR_TABLE 128 static const struct vendor_data vendor_qdt_qdf2400_e44 = { 129 .reg_offset = pl011_std_offsets, 130 .fr_busy = UART011_FR_TXFE, 131 .fr_dsr = UART01x_FR_DSR, 132 .fr_cts = UART01x_FR_CTS, 133 .fr_ri = UART011_FR_RI, 134 .inv_fr = UART011_FR_TXFE, 135 .access_32b = true, 136 .oversampling = false, 137 .dma_threshold = false, 138 .cts_event_workaround = false, 139 .always_enabled = true, 140 .fixed_options = true, 141 }; 142 #endif 143 144 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { 145 [REG_DR] = UART01x_DR, 146 [REG_ST_DMAWM] = ST_UART011_DMAWM, 147 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, 148 [REG_FR] = UART01x_FR, 149 [REG_LCRH_RX] = ST_UART011_LCRH_RX, 150 [REG_LCRH_TX] = ST_UART011_LCRH_TX, 151 [REG_IBRD] = UART011_IBRD, 152 [REG_FBRD] = UART011_FBRD, 153 [REG_CR] = UART011_CR, 154 [REG_IFLS] = UART011_IFLS, 155 [REG_IMSC] = UART011_IMSC, 156 [REG_RIS] = UART011_RIS, 157 [REG_MIS] = UART011_MIS, 158 [REG_ICR] = UART011_ICR, 159 [REG_DMACR] = UART011_DMACR, 160 [REG_ST_XFCR] = ST_UART011_XFCR, 161 [REG_ST_XON1] = ST_UART011_XON1, 162 [REG_ST_XON2] = ST_UART011_XON2, 163 [REG_ST_XOFF1] = ST_UART011_XOFF1, 164 [REG_ST_XOFF2] = ST_UART011_XOFF2, 165 [REG_ST_ITCR] = ST_UART011_ITCR, 166 [REG_ST_ITIP] = ST_UART011_ITIP, 167 [REG_ST_ABCR] = ST_UART011_ABCR, 168 [REG_ST_ABIMSC] = ST_UART011_ABIMSC, 169 }; 170 171 static unsigned int get_fifosize_st(struct amba_device *dev) 172 { 173 return 64; 174 } 175 176 static struct vendor_data vendor_st = { 177 .reg_offset = pl011_st_offsets, 178 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, 179 .fr_busy = UART01x_FR_BUSY, 180 .fr_dsr = UART01x_FR_DSR, 181 .fr_cts = UART01x_FR_CTS, 182 .fr_ri = UART011_FR_RI, 183 .oversampling = true, 184 .dma_threshold = true, 185 .cts_event_workaround = true, 186 .always_enabled = false, 187 .fixed_options = false, 188 .get_fifosize = get_fifosize_st, 189 }; 190 191 static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = { 192 [REG_DR] = ZX_UART011_DR, 193 [REG_FR] = ZX_UART011_FR, 194 [REG_LCRH_RX] = ZX_UART011_LCRH, 195 [REG_LCRH_TX] = ZX_UART011_LCRH, 196 [REG_IBRD] = ZX_UART011_IBRD, 197 [REG_FBRD] = ZX_UART011_FBRD, 198 [REG_CR] = ZX_UART011_CR, 199 [REG_IFLS] = ZX_UART011_IFLS, 200 [REG_IMSC] = ZX_UART011_IMSC, 201 [REG_RIS] = ZX_UART011_RIS, 202 [REG_MIS] = ZX_UART011_MIS, 203 [REG_ICR] = ZX_UART011_ICR, 204 [REG_DMACR] = ZX_UART011_DMACR, 205 }; 206 207 static unsigned int get_fifosize_zte(struct amba_device *dev) 208 { 209 return 16; 210 } 211 212 static struct vendor_data vendor_zte = { 213 .reg_offset = pl011_zte_offsets, 214 .access_32b = true, 215 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 216 .fr_busy = ZX_UART01x_FR_BUSY, 217 .fr_dsr = ZX_UART01x_FR_DSR, 218 .fr_cts = ZX_UART01x_FR_CTS, 219 .fr_ri = ZX_UART011_FR_RI, 220 .get_fifosize = get_fifosize_zte, 221 }; 222 223 /* Deals with DMA transactions */ 224 225 struct pl011_sgbuf { 226 struct scatterlist sg; 227 char *buf; 228 }; 229 230 struct pl011_dmarx_data { 231 struct dma_chan *chan; 232 struct completion complete; 233 bool use_buf_b; 234 struct pl011_sgbuf sgbuf_a; 235 struct pl011_sgbuf sgbuf_b; 236 dma_cookie_t cookie; 237 bool running; 238 struct timer_list timer; 239 unsigned int last_residue; 240 unsigned long last_jiffies; 241 bool auto_poll_rate; 242 unsigned int poll_rate; 243 unsigned int poll_timeout; 244 }; 245 246 struct pl011_dmatx_data { 247 struct dma_chan *chan; 248 struct scatterlist sg; 249 char *buf; 250 bool queued; 251 }; 252 253 /* 254 * We wrap our port structure around the generic uart_port. 255 */ 256 struct uart_amba_port { 257 struct uart_port port; 258 const u16 *reg_offset; 259 struct clk *clk; 260 const struct vendor_data *vendor; 261 unsigned int dmacr; /* dma control reg */ 262 unsigned int im; /* interrupt mask */ 263 unsigned int old_status; 264 unsigned int fifosize; /* vendor-specific */ 265 unsigned int old_cr; /* state during shutdown */ 266 unsigned int fixed_baud; /* vendor-set fixed baud rate */ 267 char type[12]; 268 #ifdef CONFIG_DMA_ENGINE 269 /* DMA stuff */ 270 bool using_tx_dma; 271 bool using_rx_dma; 272 struct pl011_dmarx_data dmarx; 273 struct pl011_dmatx_data dmatx; 274 bool dma_probed; 275 #endif 276 }; 277 278 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, 279 unsigned int reg) 280 { 281 return uap->reg_offset[reg]; 282 } 283 284 static unsigned int pl011_read(const struct uart_amba_port *uap, 285 unsigned int reg) 286 { 287 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 288 289 return (uap->port.iotype == UPIO_MEM32) ? 290 readl_relaxed(addr) : readw_relaxed(addr); 291 } 292 293 static void pl011_write(unsigned int val, const struct uart_amba_port *uap, 294 unsigned int reg) 295 { 296 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 297 298 if (uap->port.iotype == UPIO_MEM32) 299 writel_relaxed(val, addr); 300 else 301 writew_relaxed(val, addr); 302 } 303 304 /* 305 * Reads up to 256 characters from the FIFO or until it's empty and 306 * inserts them into the TTY layer. Returns the number of characters 307 * read from the FIFO. 308 */ 309 static int pl011_fifo_to_tty(struct uart_amba_port *uap) 310 { 311 unsigned int ch, flag, fifotaken; 312 int sysrq; 313 u16 status; 314 315 for (fifotaken = 0; fifotaken != 256; fifotaken++) { 316 status = pl011_read(uap, REG_FR); 317 if (status & UART01x_FR_RXFE) 318 break; 319 320 /* Take chars from the FIFO and update status */ 321 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; 322 flag = TTY_NORMAL; 323 uap->port.icount.rx++; 324 325 if (unlikely(ch & UART_DR_ERROR)) { 326 if (ch & UART011_DR_BE) { 327 ch &= ~(UART011_DR_FE | UART011_DR_PE); 328 uap->port.icount.brk++; 329 if (uart_handle_break(&uap->port)) 330 continue; 331 } else if (ch & UART011_DR_PE) 332 uap->port.icount.parity++; 333 else if (ch & UART011_DR_FE) 334 uap->port.icount.frame++; 335 if (ch & UART011_DR_OE) 336 uap->port.icount.overrun++; 337 338 ch &= uap->port.read_status_mask; 339 340 if (ch & UART011_DR_BE) 341 flag = TTY_BREAK; 342 else if (ch & UART011_DR_PE) 343 flag = TTY_PARITY; 344 else if (ch & UART011_DR_FE) 345 flag = TTY_FRAME; 346 } 347 348 spin_unlock(&uap->port.lock); 349 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255); 350 spin_lock(&uap->port.lock); 351 352 if (!sysrq) 353 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); 354 } 355 356 return fifotaken; 357 } 358 359 360 /* 361 * All the DMA operation mode stuff goes inside this ifdef. 362 * This assumes that you have a generic DMA device interface, 363 * no custom DMA interfaces are supported. 364 */ 365 #ifdef CONFIG_DMA_ENGINE 366 367 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE 368 369 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, 370 enum dma_data_direction dir) 371 { 372 dma_addr_t dma_addr; 373 374 sg->buf = dma_alloc_coherent(chan->device->dev, 375 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); 376 if (!sg->buf) 377 return -ENOMEM; 378 379 sg_init_table(&sg->sg, 1); 380 sg_set_page(&sg->sg, phys_to_page(dma_addr), 381 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); 382 sg_dma_address(&sg->sg) = dma_addr; 383 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; 384 385 return 0; 386 } 387 388 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, 389 enum dma_data_direction dir) 390 { 391 if (sg->buf) { 392 dma_free_coherent(chan->device->dev, 393 PL011_DMA_BUFFER_SIZE, sg->buf, 394 sg_dma_address(&sg->sg)); 395 } 396 } 397 398 static void pl011_dma_probe(struct uart_amba_port *uap) 399 { 400 /* DMA is the sole user of the platform data right now */ 401 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); 402 struct device *dev = uap->port.dev; 403 struct dma_slave_config tx_conf = { 404 .dst_addr = uap->port.mapbase + 405 pl011_reg_to_offset(uap, REG_DR), 406 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 407 .direction = DMA_MEM_TO_DEV, 408 .dst_maxburst = uap->fifosize >> 1, 409 .device_fc = false, 410 }; 411 struct dma_chan *chan; 412 dma_cap_mask_t mask; 413 414 uap->dma_probed = true; 415 chan = dma_request_chan(dev, "tx"); 416 if (IS_ERR(chan)) { 417 if (PTR_ERR(chan) == -EPROBE_DEFER) { 418 uap->dma_probed = false; 419 return; 420 } 421 422 /* We need platform data */ 423 if (!plat || !plat->dma_filter) { 424 dev_info(uap->port.dev, "no DMA platform data\n"); 425 return; 426 } 427 428 /* Try to acquire a generic DMA engine slave TX channel */ 429 dma_cap_zero(mask); 430 dma_cap_set(DMA_SLAVE, mask); 431 432 chan = dma_request_channel(mask, plat->dma_filter, 433 plat->dma_tx_param); 434 if (!chan) { 435 dev_err(uap->port.dev, "no TX DMA channel!\n"); 436 return; 437 } 438 } 439 440 dmaengine_slave_config(chan, &tx_conf); 441 uap->dmatx.chan = chan; 442 443 dev_info(uap->port.dev, "DMA channel TX %s\n", 444 dma_chan_name(uap->dmatx.chan)); 445 446 /* Optionally make use of an RX channel as well */ 447 chan = dma_request_slave_channel(dev, "rx"); 448 449 if (!chan && plat && plat->dma_rx_param) { 450 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); 451 452 if (!chan) { 453 dev_err(uap->port.dev, "no RX DMA channel!\n"); 454 return; 455 } 456 } 457 458 if (chan) { 459 struct dma_slave_config rx_conf = { 460 .src_addr = uap->port.mapbase + 461 pl011_reg_to_offset(uap, REG_DR), 462 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 463 .direction = DMA_DEV_TO_MEM, 464 .src_maxburst = uap->fifosize >> 2, 465 .device_fc = false, 466 }; 467 struct dma_slave_caps caps; 468 469 /* 470 * Some DMA controllers provide information on their capabilities. 471 * If the controller does, check for suitable residue processing 472 * otherwise assime all is well. 473 */ 474 if (0 == dma_get_slave_caps(chan, &caps)) { 475 if (caps.residue_granularity == 476 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { 477 dma_release_channel(chan); 478 dev_info(uap->port.dev, 479 "RX DMA disabled - no residue processing\n"); 480 return; 481 } 482 } 483 dmaengine_slave_config(chan, &rx_conf); 484 uap->dmarx.chan = chan; 485 486 uap->dmarx.auto_poll_rate = false; 487 if (plat && plat->dma_rx_poll_enable) { 488 /* Set poll rate if specified. */ 489 if (plat->dma_rx_poll_rate) { 490 uap->dmarx.auto_poll_rate = false; 491 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; 492 } else { 493 /* 494 * 100 ms defaults to poll rate if not 495 * specified. This will be adjusted with 496 * the baud rate at set_termios. 497 */ 498 uap->dmarx.auto_poll_rate = true; 499 uap->dmarx.poll_rate = 100; 500 } 501 /* 3 secs defaults poll_timeout if not specified. */ 502 if (plat->dma_rx_poll_timeout) 503 uap->dmarx.poll_timeout = 504 plat->dma_rx_poll_timeout; 505 else 506 uap->dmarx.poll_timeout = 3000; 507 } else if (!plat && dev->of_node) { 508 uap->dmarx.auto_poll_rate = of_property_read_bool( 509 dev->of_node, "auto-poll"); 510 if (uap->dmarx.auto_poll_rate) { 511 u32 x; 512 513 if (0 == of_property_read_u32(dev->of_node, 514 "poll-rate-ms", &x)) 515 uap->dmarx.poll_rate = x; 516 else 517 uap->dmarx.poll_rate = 100; 518 if (0 == of_property_read_u32(dev->of_node, 519 "poll-timeout-ms", &x)) 520 uap->dmarx.poll_timeout = x; 521 else 522 uap->dmarx.poll_timeout = 3000; 523 } 524 } 525 dev_info(uap->port.dev, "DMA channel RX %s\n", 526 dma_chan_name(uap->dmarx.chan)); 527 } 528 } 529 530 static void pl011_dma_remove(struct uart_amba_port *uap) 531 { 532 if (uap->dmatx.chan) 533 dma_release_channel(uap->dmatx.chan); 534 if (uap->dmarx.chan) 535 dma_release_channel(uap->dmarx.chan); 536 } 537 538 /* Forward declare these for the refill routine */ 539 static int pl011_dma_tx_refill(struct uart_amba_port *uap); 540 static void pl011_start_tx_pio(struct uart_amba_port *uap); 541 542 /* 543 * The current DMA TX buffer has been sent. 544 * Try to queue up another DMA buffer. 545 */ 546 static void pl011_dma_tx_callback(void *data) 547 { 548 struct uart_amba_port *uap = data; 549 struct pl011_dmatx_data *dmatx = &uap->dmatx; 550 unsigned long flags; 551 u16 dmacr; 552 553 spin_lock_irqsave(&uap->port.lock, flags); 554 if (uap->dmatx.queued) 555 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, 556 DMA_TO_DEVICE); 557 558 dmacr = uap->dmacr; 559 uap->dmacr = dmacr & ~UART011_TXDMAE; 560 pl011_write(uap->dmacr, uap, REG_DMACR); 561 562 /* 563 * If TX DMA was disabled, it means that we've stopped the DMA for 564 * some reason (eg, XOFF received, or we want to send an X-char.) 565 * 566 * Note: we need to be careful here of a potential race between DMA 567 * and the rest of the driver - if the driver disables TX DMA while 568 * a TX buffer completing, we must update the tx queued status to 569 * get further refills (hence we check dmacr). 570 */ 571 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || 572 uart_circ_empty(&uap->port.state->xmit)) { 573 uap->dmatx.queued = false; 574 spin_unlock_irqrestore(&uap->port.lock, flags); 575 return; 576 } 577 578 if (pl011_dma_tx_refill(uap) <= 0) 579 /* 580 * We didn't queue a DMA buffer for some reason, but we 581 * have data pending to be sent. Re-enable the TX IRQ. 582 */ 583 pl011_start_tx_pio(uap); 584 585 spin_unlock_irqrestore(&uap->port.lock, flags); 586 } 587 588 /* 589 * Try to refill the TX DMA buffer. 590 * Locking: called with port lock held and IRQs disabled. 591 * Returns: 592 * 1 if we queued up a TX DMA buffer. 593 * 0 if we didn't want to handle this by DMA 594 * <0 on error 595 */ 596 static int pl011_dma_tx_refill(struct uart_amba_port *uap) 597 { 598 struct pl011_dmatx_data *dmatx = &uap->dmatx; 599 struct dma_chan *chan = dmatx->chan; 600 struct dma_device *dma_dev = chan->device; 601 struct dma_async_tx_descriptor *desc; 602 struct circ_buf *xmit = &uap->port.state->xmit; 603 unsigned int count; 604 605 /* 606 * Try to avoid the overhead involved in using DMA if the 607 * transaction fits in the first half of the FIFO, by using 608 * the standard interrupt handling. This ensures that we 609 * issue a uart_write_wakeup() at the appropriate time. 610 */ 611 count = uart_circ_chars_pending(xmit); 612 if (count < (uap->fifosize >> 1)) { 613 uap->dmatx.queued = false; 614 return 0; 615 } 616 617 /* 618 * Bodge: don't send the last character by DMA, as this 619 * will prevent XON from notifying us to restart DMA. 620 */ 621 count -= 1; 622 623 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ 624 if (count > PL011_DMA_BUFFER_SIZE) 625 count = PL011_DMA_BUFFER_SIZE; 626 627 if (xmit->tail < xmit->head) 628 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); 629 else { 630 size_t first = UART_XMIT_SIZE - xmit->tail; 631 size_t second; 632 633 if (first > count) 634 first = count; 635 second = count - first; 636 637 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); 638 if (second) 639 memcpy(&dmatx->buf[first], &xmit->buf[0], second); 640 } 641 642 dmatx->sg.length = count; 643 644 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { 645 uap->dmatx.queued = false; 646 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); 647 return -EBUSY; 648 } 649 650 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, 651 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 652 if (!desc) { 653 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); 654 uap->dmatx.queued = false; 655 /* 656 * If DMA cannot be used right now, we complete this 657 * transaction via IRQ and let the TTY layer retry. 658 */ 659 dev_dbg(uap->port.dev, "TX DMA busy\n"); 660 return -EBUSY; 661 } 662 663 /* Some data to go along to the callback */ 664 desc->callback = pl011_dma_tx_callback; 665 desc->callback_param = uap; 666 667 /* All errors should happen at prepare time */ 668 dmaengine_submit(desc); 669 670 /* Fire the DMA transaction */ 671 dma_dev->device_issue_pending(chan); 672 673 uap->dmacr |= UART011_TXDMAE; 674 pl011_write(uap->dmacr, uap, REG_DMACR); 675 uap->dmatx.queued = true; 676 677 /* 678 * Now we know that DMA will fire, so advance the ring buffer 679 * with the stuff we just dispatched. 680 */ 681 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 682 uap->port.icount.tx += count; 683 684 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 685 uart_write_wakeup(&uap->port); 686 687 return 1; 688 } 689 690 /* 691 * We received a transmit interrupt without a pending X-char but with 692 * pending characters. 693 * Locking: called with port lock held and IRQs disabled. 694 * Returns: 695 * false if we want to use PIO to transmit 696 * true if we queued a DMA buffer 697 */ 698 static bool pl011_dma_tx_irq(struct uart_amba_port *uap) 699 { 700 if (!uap->using_tx_dma) 701 return false; 702 703 /* 704 * If we already have a TX buffer queued, but received a 705 * TX interrupt, it will be because we've just sent an X-char. 706 * Ensure the TX DMA is enabled and the TX IRQ is disabled. 707 */ 708 if (uap->dmatx.queued) { 709 uap->dmacr |= UART011_TXDMAE; 710 pl011_write(uap->dmacr, uap, REG_DMACR); 711 uap->im &= ~UART011_TXIM; 712 pl011_write(uap->im, uap, REG_IMSC); 713 return true; 714 } 715 716 /* 717 * We don't have a TX buffer queued, so try to queue one. 718 * If we successfully queued a buffer, mask the TX IRQ. 719 */ 720 if (pl011_dma_tx_refill(uap) > 0) { 721 uap->im &= ~UART011_TXIM; 722 pl011_write(uap->im, uap, REG_IMSC); 723 return true; 724 } 725 return false; 726 } 727 728 /* 729 * Stop the DMA transmit (eg, due to received XOFF). 730 * Locking: called with port lock held and IRQs disabled. 731 */ 732 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 733 { 734 if (uap->dmatx.queued) { 735 uap->dmacr &= ~UART011_TXDMAE; 736 pl011_write(uap->dmacr, uap, REG_DMACR); 737 } 738 } 739 740 /* 741 * Try to start a DMA transmit, or in the case of an XON/OFF 742 * character queued for send, try to get that character out ASAP. 743 * Locking: called with port lock held and IRQs disabled. 744 * Returns: 745 * false if we want the TX IRQ to be enabled 746 * true if we have a buffer queued 747 */ 748 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 749 { 750 u16 dmacr; 751 752 if (!uap->using_tx_dma) 753 return false; 754 755 if (!uap->port.x_char) { 756 /* no X-char, try to push chars out in DMA mode */ 757 bool ret = true; 758 759 if (!uap->dmatx.queued) { 760 if (pl011_dma_tx_refill(uap) > 0) { 761 uap->im &= ~UART011_TXIM; 762 pl011_write(uap->im, uap, REG_IMSC); 763 } else 764 ret = false; 765 } else if (!(uap->dmacr & UART011_TXDMAE)) { 766 uap->dmacr |= UART011_TXDMAE; 767 pl011_write(uap->dmacr, uap, REG_DMACR); 768 } 769 return ret; 770 } 771 772 /* 773 * We have an X-char to send. Disable DMA to prevent it loading 774 * the TX fifo, and then see if we can stuff it into the FIFO. 775 */ 776 dmacr = uap->dmacr; 777 uap->dmacr &= ~UART011_TXDMAE; 778 pl011_write(uap->dmacr, uap, REG_DMACR); 779 780 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { 781 /* 782 * No space in the FIFO, so enable the transmit interrupt 783 * so we know when there is space. Note that once we've 784 * loaded the character, we should just re-enable DMA. 785 */ 786 return false; 787 } 788 789 pl011_write(uap->port.x_char, uap, REG_DR); 790 uap->port.icount.tx++; 791 uap->port.x_char = 0; 792 793 /* Success - restore the DMA state */ 794 uap->dmacr = dmacr; 795 pl011_write(dmacr, uap, REG_DMACR); 796 797 return true; 798 } 799 800 /* 801 * Flush the transmit buffer. 802 * Locking: called with port lock held and IRQs disabled. 803 */ 804 static void pl011_dma_flush_buffer(struct uart_port *port) 805 __releases(&uap->port.lock) 806 __acquires(&uap->port.lock) 807 { 808 struct uart_amba_port *uap = 809 container_of(port, struct uart_amba_port, port); 810 811 if (!uap->using_tx_dma) 812 return; 813 814 dmaengine_terminate_async(uap->dmatx.chan); 815 816 if (uap->dmatx.queued) { 817 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 818 DMA_TO_DEVICE); 819 uap->dmatx.queued = false; 820 uap->dmacr &= ~UART011_TXDMAE; 821 pl011_write(uap->dmacr, uap, REG_DMACR); 822 } 823 } 824 825 static void pl011_dma_rx_callback(void *data); 826 827 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 828 { 829 struct dma_chan *rxchan = uap->dmarx.chan; 830 struct pl011_dmarx_data *dmarx = &uap->dmarx; 831 struct dma_async_tx_descriptor *desc; 832 struct pl011_sgbuf *sgbuf; 833 834 if (!rxchan) 835 return -EIO; 836 837 /* Start the RX DMA job */ 838 sgbuf = uap->dmarx.use_buf_b ? 839 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 840 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, 841 DMA_DEV_TO_MEM, 842 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 843 /* 844 * If the DMA engine is busy and cannot prepare a 845 * channel, no big deal, the driver will fall back 846 * to interrupt mode as a result of this error code. 847 */ 848 if (!desc) { 849 uap->dmarx.running = false; 850 dmaengine_terminate_all(rxchan); 851 return -EBUSY; 852 } 853 854 /* Some data to go along to the callback */ 855 desc->callback = pl011_dma_rx_callback; 856 desc->callback_param = uap; 857 dmarx->cookie = dmaengine_submit(desc); 858 dma_async_issue_pending(rxchan); 859 860 uap->dmacr |= UART011_RXDMAE; 861 pl011_write(uap->dmacr, uap, REG_DMACR); 862 uap->dmarx.running = true; 863 864 uap->im &= ~UART011_RXIM; 865 pl011_write(uap->im, uap, REG_IMSC); 866 867 return 0; 868 } 869 870 /* 871 * This is called when either the DMA job is complete, or 872 * the FIFO timeout interrupt occurred. This must be called 873 * with the port spinlock uap->port.lock held. 874 */ 875 static void pl011_dma_rx_chars(struct uart_amba_port *uap, 876 u32 pending, bool use_buf_b, 877 bool readfifo) 878 { 879 struct tty_port *port = &uap->port.state->port; 880 struct pl011_sgbuf *sgbuf = use_buf_b ? 881 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 882 int dma_count = 0; 883 u32 fifotaken = 0; /* only used for vdbg() */ 884 885 struct pl011_dmarx_data *dmarx = &uap->dmarx; 886 int dmataken = 0; 887 888 if (uap->dmarx.poll_rate) { 889 /* The data can be taken by polling */ 890 dmataken = sgbuf->sg.length - dmarx->last_residue; 891 /* Recalculate the pending size */ 892 if (pending >= dmataken) 893 pending -= dmataken; 894 } 895 896 /* Pick the remain data from the DMA */ 897 if (pending) { 898 899 /* 900 * First take all chars in the DMA pipe, then look in the FIFO. 901 * Note that tty_insert_flip_buf() tries to take as many chars 902 * as it can. 903 */ 904 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 905 pending); 906 907 uap->port.icount.rx += dma_count; 908 if (dma_count < pending) 909 dev_warn(uap->port.dev, 910 "couldn't insert all characters (TTY is full?)\n"); 911 } 912 913 /* Reset the last_residue for Rx DMA poll */ 914 if (uap->dmarx.poll_rate) 915 dmarx->last_residue = sgbuf->sg.length; 916 917 /* 918 * Only continue with trying to read the FIFO if all DMA chars have 919 * been taken first. 920 */ 921 if (dma_count == pending && readfifo) { 922 /* Clear any error flags */ 923 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 924 UART011_FEIS, uap, REG_ICR); 925 926 /* 927 * If we read all the DMA'd characters, and we had an 928 * incomplete buffer, that could be due to an rx error, or 929 * maybe we just timed out. Read any pending chars and check 930 * the error status. 931 * 932 * Error conditions will only occur in the FIFO, these will 933 * trigger an immediate interrupt and stop the DMA job, so we 934 * will always find the error in the FIFO, never in the DMA 935 * buffer. 936 */ 937 fifotaken = pl011_fifo_to_tty(uap); 938 } 939 940 spin_unlock(&uap->port.lock); 941 dev_vdbg(uap->port.dev, 942 "Took %d chars from DMA buffer and %d chars from the FIFO\n", 943 dma_count, fifotaken); 944 tty_flip_buffer_push(port); 945 spin_lock(&uap->port.lock); 946 } 947 948 static void pl011_dma_rx_irq(struct uart_amba_port *uap) 949 { 950 struct pl011_dmarx_data *dmarx = &uap->dmarx; 951 struct dma_chan *rxchan = dmarx->chan; 952 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 953 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 954 size_t pending; 955 struct dma_tx_state state; 956 enum dma_status dmastat; 957 958 /* 959 * Pause the transfer so we can trust the current counter, 960 * do this before we pause the PL011 block, else we may 961 * overflow the FIFO. 962 */ 963 if (dmaengine_pause(rxchan)) 964 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 965 dmastat = rxchan->device->device_tx_status(rxchan, 966 dmarx->cookie, &state); 967 if (dmastat != DMA_PAUSED) 968 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 969 970 /* Disable RX DMA - incoming data will wait in the FIFO */ 971 uap->dmacr &= ~UART011_RXDMAE; 972 pl011_write(uap->dmacr, uap, REG_DMACR); 973 uap->dmarx.running = false; 974 975 pending = sgbuf->sg.length - state.residue; 976 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 977 /* Then we terminate the transfer - we now know our residue */ 978 dmaengine_terminate_all(rxchan); 979 980 /* 981 * This will take the chars we have so far and insert 982 * into the framework. 983 */ 984 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); 985 986 /* Switch buffer & re-trigger DMA job */ 987 dmarx->use_buf_b = !dmarx->use_buf_b; 988 if (pl011_dma_rx_trigger_dma(uap)) { 989 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 990 "fall back to interrupt mode\n"); 991 uap->im |= UART011_RXIM; 992 pl011_write(uap->im, uap, REG_IMSC); 993 } 994 } 995 996 static void pl011_dma_rx_callback(void *data) 997 { 998 struct uart_amba_port *uap = data; 999 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1000 struct dma_chan *rxchan = dmarx->chan; 1001 bool lastbuf = dmarx->use_buf_b; 1002 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 1003 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 1004 size_t pending; 1005 struct dma_tx_state state; 1006 int ret; 1007 1008 /* 1009 * This completion interrupt occurs typically when the 1010 * RX buffer is totally stuffed but no timeout has yet 1011 * occurred. When that happens, we just want the RX 1012 * routine to flush out the secondary DMA buffer while 1013 * we immediately trigger the next DMA job. 1014 */ 1015 spin_lock_irq(&uap->port.lock); 1016 /* 1017 * Rx data can be taken by the UART interrupts during 1018 * the DMA irq handler. So we check the residue here. 1019 */ 1020 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1021 pending = sgbuf->sg.length - state.residue; 1022 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 1023 /* Then we terminate the transfer - we now know our residue */ 1024 dmaengine_terminate_all(rxchan); 1025 1026 uap->dmarx.running = false; 1027 dmarx->use_buf_b = !lastbuf; 1028 ret = pl011_dma_rx_trigger_dma(uap); 1029 1030 pl011_dma_rx_chars(uap, pending, lastbuf, false); 1031 spin_unlock_irq(&uap->port.lock); 1032 /* 1033 * Do this check after we picked the DMA chars so we don't 1034 * get some IRQ immediately from RX. 1035 */ 1036 if (ret) { 1037 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 1038 "fall back to interrupt mode\n"); 1039 uap->im |= UART011_RXIM; 1040 pl011_write(uap->im, uap, REG_IMSC); 1041 } 1042 } 1043 1044 /* 1045 * Stop accepting received characters, when we're shutting down or 1046 * suspending this port. 1047 * Locking: called with port lock held and IRQs disabled. 1048 */ 1049 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1050 { 1051 /* FIXME. Just disable the DMA enable */ 1052 uap->dmacr &= ~UART011_RXDMAE; 1053 pl011_write(uap->dmacr, uap, REG_DMACR); 1054 } 1055 1056 /* 1057 * Timer handler for Rx DMA polling. 1058 * Every polling, It checks the residue in the dma buffer and transfer 1059 * data to the tty. Also, last_residue is updated for the next polling. 1060 */ 1061 static void pl011_dma_rx_poll(struct timer_list *t) 1062 { 1063 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer); 1064 struct tty_port *port = &uap->port.state->port; 1065 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1066 struct dma_chan *rxchan = uap->dmarx.chan; 1067 unsigned long flags = 0; 1068 unsigned int dmataken = 0; 1069 unsigned int size = 0; 1070 struct pl011_sgbuf *sgbuf; 1071 int dma_count; 1072 struct dma_tx_state state; 1073 1074 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 1075 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1076 if (likely(state.residue < dmarx->last_residue)) { 1077 dmataken = sgbuf->sg.length - dmarx->last_residue; 1078 size = dmarx->last_residue - state.residue; 1079 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 1080 size); 1081 if (dma_count == size) 1082 dmarx->last_residue = state.residue; 1083 dmarx->last_jiffies = jiffies; 1084 } 1085 tty_flip_buffer_push(port); 1086 1087 /* 1088 * If no data is received in poll_timeout, the driver will fall back 1089 * to interrupt mode. We will retrigger DMA at the first interrupt. 1090 */ 1091 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) 1092 > uap->dmarx.poll_timeout) { 1093 1094 spin_lock_irqsave(&uap->port.lock, flags); 1095 pl011_dma_rx_stop(uap); 1096 uap->im |= UART011_RXIM; 1097 pl011_write(uap->im, uap, REG_IMSC); 1098 spin_unlock_irqrestore(&uap->port.lock, flags); 1099 1100 uap->dmarx.running = false; 1101 dmaengine_terminate_all(rxchan); 1102 del_timer(&uap->dmarx.timer); 1103 } else { 1104 mod_timer(&uap->dmarx.timer, 1105 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); 1106 } 1107 } 1108 1109 static void pl011_dma_startup(struct uart_amba_port *uap) 1110 { 1111 int ret; 1112 1113 if (!uap->dma_probed) 1114 pl011_dma_probe(uap); 1115 1116 if (!uap->dmatx.chan) 1117 return; 1118 1119 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); 1120 if (!uap->dmatx.buf) { 1121 dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); 1122 uap->port.fifosize = uap->fifosize; 1123 return; 1124 } 1125 1126 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); 1127 1128 /* The DMA buffer is now the FIFO the TTY subsystem can use */ 1129 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; 1130 uap->using_tx_dma = true; 1131 1132 if (!uap->dmarx.chan) 1133 goto skip_rx; 1134 1135 /* Allocate and map DMA RX buffers */ 1136 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1137 DMA_FROM_DEVICE); 1138 if (ret) { 1139 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1140 "RX buffer A", ret); 1141 goto skip_rx; 1142 } 1143 1144 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, 1145 DMA_FROM_DEVICE); 1146 if (ret) { 1147 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1148 "RX buffer B", ret); 1149 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1150 DMA_FROM_DEVICE); 1151 goto skip_rx; 1152 } 1153 1154 uap->using_rx_dma = true; 1155 1156 skip_rx: 1157 /* Turn on DMA error (RX/TX will be enabled on demand) */ 1158 uap->dmacr |= UART011_DMAONERR; 1159 pl011_write(uap->dmacr, uap, REG_DMACR); 1160 1161 /* 1162 * ST Micro variants has some specific dma burst threshold 1163 * compensation. Set this to 16 bytes, so burst will only 1164 * be issued above/below 16 bytes. 1165 */ 1166 if (uap->vendor->dma_threshold) 1167 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, 1168 uap, REG_ST_DMAWM); 1169 1170 if (uap->using_rx_dma) { 1171 if (pl011_dma_rx_trigger_dma(uap)) 1172 dev_dbg(uap->port.dev, "could not trigger initial " 1173 "RX DMA job, fall back to interrupt mode\n"); 1174 if (uap->dmarx.poll_rate) { 1175 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0); 1176 mod_timer(&uap->dmarx.timer, 1177 jiffies + 1178 msecs_to_jiffies(uap->dmarx.poll_rate)); 1179 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1180 uap->dmarx.last_jiffies = jiffies; 1181 } 1182 } 1183 } 1184 1185 static void pl011_dma_shutdown(struct uart_amba_port *uap) 1186 { 1187 if (!(uap->using_tx_dma || uap->using_rx_dma)) 1188 return; 1189 1190 /* Disable RX and TX DMA */ 1191 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) 1192 cpu_relax(); 1193 1194 spin_lock_irq(&uap->port.lock); 1195 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); 1196 pl011_write(uap->dmacr, uap, REG_DMACR); 1197 spin_unlock_irq(&uap->port.lock); 1198 1199 if (uap->using_tx_dma) { 1200 /* In theory, this should already be done by pl011_dma_flush_buffer */ 1201 dmaengine_terminate_all(uap->dmatx.chan); 1202 if (uap->dmatx.queued) { 1203 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 1204 DMA_TO_DEVICE); 1205 uap->dmatx.queued = false; 1206 } 1207 1208 kfree(uap->dmatx.buf); 1209 uap->using_tx_dma = false; 1210 } 1211 1212 if (uap->using_rx_dma) { 1213 dmaengine_terminate_all(uap->dmarx.chan); 1214 /* Clean up the RX DMA */ 1215 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); 1216 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); 1217 if (uap->dmarx.poll_rate) 1218 del_timer_sync(&uap->dmarx.timer); 1219 uap->using_rx_dma = false; 1220 } 1221 } 1222 1223 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1224 { 1225 return uap->using_rx_dma; 1226 } 1227 1228 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1229 { 1230 return uap->using_rx_dma && uap->dmarx.running; 1231 } 1232 1233 #else 1234 /* Blank functions if the DMA engine is not available */ 1235 static inline void pl011_dma_remove(struct uart_amba_port *uap) 1236 { 1237 } 1238 1239 static inline void pl011_dma_startup(struct uart_amba_port *uap) 1240 { 1241 } 1242 1243 static inline void pl011_dma_shutdown(struct uart_amba_port *uap) 1244 { 1245 } 1246 1247 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) 1248 { 1249 return false; 1250 } 1251 1252 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 1253 { 1254 } 1255 1256 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 1257 { 1258 return false; 1259 } 1260 1261 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) 1262 { 1263 } 1264 1265 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1266 { 1267 } 1268 1269 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 1270 { 1271 return -EIO; 1272 } 1273 1274 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1275 { 1276 return false; 1277 } 1278 1279 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1280 { 1281 return false; 1282 } 1283 1284 #define pl011_dma_flush_buffer NULL 1285 #endif 1286 1287 static void pl011_stop_tx(struct uart_port *port) 1288 { 1289 struct uart_amba_port *uap = 1290 container_of(port, struct uart_amba_port, port); 1291 1292 uap->im &= ~UART011_TXIM; 1293 pl011_write(uap->im, uap, REG_IMSC); 1294 pl011_dma_tx_stop(uap); 1295 } 1296 1297 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); 1298 1299 /* Start TX with programmed I/O only (no DMA) */ 1300 static void pl011_start_tx_pio(struct uart_amba_port *uap) 1301 { 1302 if (pl011_tx_chars(uap, false)) { 1303 uap->im |= UART011_TXIM; 1304 pl011_write(uap->im, uap, REG_IMSC); 1305 } 1306 } 1307 1308 static void pl011_start_tx(struct uart_port *port) 1309 { 1310 struct uart_amba_port *uap = 1311 container_of(port, struct uart_amba_port, port); 1312 1313 if (!pl011_dma_tx_start(uap)) 1314 pl011_start_tx_pio(uap); 1315 } 1316 1317 static void pl011_stop_rx(struct uart_port *port) 1318 { 1319 struct uart_amba_port *uap = 1320 container_of(port, struct uart_amba_port, port); 1321 1322 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| 1323 UART011_PEIM|UART011_BEIM|UART011_OEIM); 1324 pl011_write(uap->im, uap, REG_IMSC); 1325 1326 pl011_dma_rx_stop(uap); 1327 } 1328 1329 static void pl011_enable_ms(struct uart_port *port) 1330 { 1331 struct uart_amba_port *uap = 1332 container_of(port, struct uart_amba_port, port); 1333 1334 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; 1335 pl011_write(uap->im, uap, REG_IMSC); 1336 } 1337 1338 static void pl011_rx_chars(struct uart_amba_port *uap) 1339 __releases(&uap->port.lock) 1340 __acquires(&uap->port.lock) 1341 { 1342 pl011_fifo_to_tty(uap); 1343 1344 spin_unlock(&uap->port.lock); 1345 tty_flip_buffer_push(&uap->port.state->port); 1346 /* 1347 * If we were temporarily out of DMA mode for a while, 1348 * attempt to switch back to DMA mode again. 1349 */ 1350 if (pl011_dma_rx_available(uap)) { 1351 if (pl011_dma_rx_trigger_dma(uap)) { 1352 dev_dbg(uap->port.dev, "could not trigger RX DMA job " 1353 "fall back to interrupt mode again\n"); 1354 uap->im |= UART011_RXIM; 1355 pl011_write(uap->im, uap, REG_IMSC); 1356 } else { 1357 #ifdef CONFIG_DMA_ENGINE 1358 /* Start Rx DMA poll */ 1359 if (uap->dmarx.poll_rate) { 1360 uap->dmarx.last_jiffies = jiffies; 1361 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1362 mod_timer(&uap->dmarx.timer, 1363 jiffies + 1364 msecs_to_jiffies(uap->dmarx.poll_rate)); 1365 } 1366 #endif 1367 } 1368 } 1369 spin_lock(&uap->port.lock); 1370 } 1371 1372 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, 1373 bool from_irq) 1374 { 1375 if (unlikely(!from_irq) && 1376 pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1377 return false; /* unable to transmit character */ 1378 1379 pl011_write(c, uap, REG_DR); 1380 uap->port.icount.tx++; 1381 1382 return true; 1383 } 1384 1385 /* Returns true if tx interrupts have to be (kept) enabled */ 1386 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) 1387 { 1388 struct circ_buf *xmit = &uap->port.state->xmit; 1389 int count = uap->fifosize >> 1; 1390 1391 if (uap->port.x_char) { 1392 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) 1393 return true; 1394 uap->port.x_char = 0; 1395 --count; 1396 } 1397 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { 1398 pl011_stop_tx(&uap->port); 1399 return false; 1400 } 1401 1402 /* If we are using DMA mode, try to send some characters. */ 1403 if (pl011_dma_tx_irq(uap)) 1404 return true; 1405 1406 do { 1407 if (likely(from_irq) && count-- == 0) 1408 break; 1409 1410 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) 1411 break; 1412 1413 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1414 } while (!uart_circ_empty(xmit)); 1415 1416 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1417 uart_write_wakeup(&uap->port); 1418 1419 if (uart_circ_empty(xmit)) { 1420 pl011_stop_tx(&uap->port); 1421 return false; 1422 } 1423 return true; 1424 } 1425 1426 static void pl011_modem_status(struct uart_amba_port *uap) 1427 { 1428 unsigned int status, delta; 1429 1430 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1431 1432 delta = status ^ uap->old_status; 1433 uap->old_status = status; 1434 1435 if (!delta) 1436 return; 1437 1438 if (delta & UART01x_FR_DCD) 1439 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 1440 1441 if (delta & uap->vendor->fr_dsr) 1442 uap->port.icount.dsr++; 1443 1444 if (delta & uap->vendor->fr_cts) 1445 uart_handle_cts_change(&uap->port, 1446 status & uap->vendor->fr_cts); 1447 1448 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 1449 } 1450 1451 static void check_apply_cts_event_workaround(struct uart_amba_port *uap) 1452 { 1453 if (!uap->vendor->cts_event_workaround) 1454 return; 1455 1456 /* workaround to make sure that all bits are unlocked.. */ 1457 pl011_write(0x00, uap, REG_ICR); 1458 1459 /* 1460 * WA: introduce 26ns(1 uart clk) delay before W1C; 1461 * single apb access will incur 2 pclk(133.12Mhz) delay, 1462 * so add 2 dummy reads 1463 */ 1464 pl011_read(uap, REG_ICR); 1465 pl011_read(uap, REG_ICR); 1466 } 1467 1468 static irqreturn_t pl011_int(int irq, void *dev_id) 1469 { 1470 struct uart_amba_port *uap = dev_id; 1471 unsigned long flags; 1472 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 1473 int handled = 0; 1474 1475 spin_lock_irqsave(&uap->port.lock, flags); 1476 status = pl011_read(uap, REG_RIS) & uap->im; 1477 if (status) { 1478 do { 1479 check_apply_cts_event_workaround(uap); 1480 1481 pl011_write(status & ~(UART011_TXIS|UART011_RTIS| 1482 UART011_RXIS), 1483 uap, REG_ICR); 1484 1485 if (status & (UART011_RTIS|UART011_RXIS)) { 1486 if (pl011_dma_rx_running(uap)) 1487 pl011_dma_rx_irq(uap); 1488 else 1489 pl011_rx_chars(uap); 1490 } 1491 if (status & (UART011_DSRMIS|UART011_DCDMIS| 1492 UART011_CTSMIS|UART011_RIMIS)) 1493 pl011_modem_status(uap); 1494 if (status & UART011_TXIS) 1495 pl011_tx_chars(uap, true); 1496 1497 if (pass_counter-- == 0) 1498 break; 1499 1500 status = pl011_read(uap, REG_RIS) & uap->im; 1501 } while (status != 0); 1502 handled = 1; 1503 } 1504 1505 spin_unlock_irqrestore(&uap->port.lock, flags); 1506 1507 return IRQ_RETVAL(handled); 1508 } 1509 1510 static unsigned int pl011_tx_empty(struct uart_port *port) 1511 { 1512 struct uart_amba_port *uap = 1513 container_of(port, struct uart_amba_port, port); 1514 1515 /* Allow feature register bits to be inverted to work around errata */ 1516 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; 1517 1518 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? 1519 0 : TIOCSER_TEMT; 1520 } 1521 1522 static unsigned int pl011_get_mctrl(struct uart_port *port) 1523 { 1524 struct uart_amba_port *uap = 1525 container_of(port, struct uart_amba_port, port); 1526 unsigned int result = 0; 1527 unsigned int status = pl011_read(uap, REG_FR); 1528 1529 #define TIOCMBIT(uartbit, tiocmbit) \ 1530 if (status & uartbit) \ 1531 result |= tiocmbit 1532 1533 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); 1534 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR); 1535 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS); 1536 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG); 1537 #undef TIOCMBIT 1538 return result; 1539 } 1540 1541 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) 1542 { 1543 struct uart_amba_port *uap = 1544 container_of(port, struct uart_amba_port, port); 1545 unsigned int cr; 1546 1547 cr = pl011_read(uap, REG_CR); 1548 1549 #define TIOCMBIT(tiocmbit, uartbit) \ 1550 if (mctrl & tiocmbit) \ 1551 cr |= uartbit; \ 1552 else \ 1553 cr &= ~uartbit 1554 1555 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); 1556 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); 1557 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); 1558 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); 1559 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); 1560 1561 if (port->status & UPSTAT_AUTORTS) { 1562 /* We need to disable auto-RTS if we want to turn RTS off */ 1563 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); 1564 } 1565 #undef TIOCMBIT 1566 1567 pl011_write(cr, uap, REG_CR); 1568 } 1569 1570 static void pl011_break_ctl(struct uart_port *port, int break_state) 1571 { 1572 struct uart_amba_port *uap = 1573 container_of(port, struct uart_amba_port, port); 1574 unsigned long flags; 1575 unsigned int lcr_h; 1576 1577 spin_lock_irqsave(&uap->port.lock, flags); 1578 lcr_h = pl011_read(uap, REG_LCRH_TX); 1579 if (break_state == -1) 1580 lcr_h |= UART01x_LCRH_BRK; 1581 else 1582 lcr_h &= ~UART01x_LCRH_BRK; 1583 pl011_write(lcr_h, uap, REG_LCRH_TX); 1584 spin_unlock_irqrestore(&uap->port.lock, flags); 1585 } 1586 1587 #ifdef CONFIG_CONSOLE_POLL 1588 1589 static void pl011_quiesce_irqs(struct uart_port *port) 1590 { 1591 struct uart_amba_port *uap = 1592 container_of(port, struct uart_amba_port, port); 1593 1594 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); 1595 /* 1596 * There is no way to clear TXIM as this is "ready to transmit IRQ", so 1597 * we simply mask it. start_tx() will unmask it. 1598 * 1599 * Note we can race with start_tx(), and if the race happens, the 1600 * polling user might get another interrupt just after we clear it. 1601 * But it should be OK and can happen even w/o the race, e.g. 1602 * controller immediately got some new data and raised the IRQ. 1603 * 1604 * And whoever uses polling routines assumes that it manages the device 1605 * (including tx queue), so we're also fine with start_tx()'s caller 1606 * side. 1607 */ 1608 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, 1609 REG_IMSC); 1610 } 1611 1612 static int pl011_get_poll_char(struct uart_port *port) 1613 { 1614 struct uart_amba_port *uap = 1615 container_of(port, struct uart_amba_port, port); 1616 unsigned int status; 1617 1618 /* 1619 * The caller might need IRQs lowered, e.g. if used with KDB NMI 1620 * debugger. 1621 */ 1622 pl011_quiesce_irqs(port); 1623 1624 status = pl011_read(uap, REG_FR); 1625 if (status & UART01x_FR_RXFE) 1626 return NO_POLL_CHAR; 1627 1628 return pl011_read(uap, REG_DR); 1629 } 1630 1631 static void pl011_put_poll_char(struct uart_port *port, 1632 unsigned char ch) 1633 { 1634 struct uart_amba_port *uap = 1635 container_of(port, struct uart_amba_port, port); 1636 1637 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1638 cpu_relax(); 1639 1640 pl011_write(ch, uap, REG_DR); 1641 } 1642 1643 #endif /* CONFIG_CONSOLE_POLL */ 1644 1645 static int pl011_hwinit(struct uart_port *port) 1646 { 1647 struct uart_amba_port *uap = 1648 container_of(port, struct uart_amba_port, port); 1649 int retval; 1650 1651 /* Optionaly enable pins to be muxed in and configured */ 1652 pinctrl_pm_select_default_state(port->dev); 1653 1654 /* 1655 * Try to enable the clock producer. 1656 */ 1657 retval = clk_prepare_enable(uap->clk); 1658 if (retval) 1659 return retval; 1660 1661 uap->port.uartclk = clk_get_rate(uap->clk); 1662 1663 /* Clear pending error and receive interrupts */ 1664 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 1665 UART011_FEIS | UART011_RTIS | UART011_RXIS, 1666 uap, REG_ICR); 1667 1668 /* 1669 * Save interrupts enable mask, and enable RX interrupts in case if 1670 * the interrupt is used for NMI entry. 1671 */ 1672 uap->im = pl011_read(uap, REG_IMSC); 1673 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); 1674 1675 if (dev_get_platdata(uap->port.dev)) { 1676 struct amba_pl011_data *plat; 1677 1678 plat = dev_get_platdata(uap->port.dev); 1679 if (plat->init) 1680 plat->init(); 1681 } 1682 return 0; 1683 } 1684 1685 static bool pl011_split_lcrh(const struct uart_amba_port *uap) 1686 { 1687 return pl011_reg_to_offset(uap, REG_LCRH_RX) != 1688 pl011_reg_to_offset(uap, REG_LCRH_TX); 1689 } 1690 1691 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) 1692 { 1693 pl011_write(lcr_h, uap, REG_LCRH_RX); 1694 if (pl011_split_lcrh(uap)) { 1695 int i; 1696 /* 1697 * Wait 10 PCLKs before writing LCRH_TX register, 1698 * to get this delay write read only register 10 times 1699 */ 1700 for (i = 0; i < 10; ++i) 1701 pl011_write(0xff, uap, REG_MIS); 1702 pl011_write(lcr_h, uap, REG_LCRH_TX); 1703 } 1704 } 1705 1706 static int pl011_allocate_irq(struct uart_amba_port *uap) 1707 { 1708 pl011_write(uap->im, uap, REG_IMSC); 1709 1710 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); 1711 } 1712 1713 /* 1714 * Enable interrupts, only timeouts when using DMA 1715 * if initial RX DMA job failed, start in interrupt mode 1716 * as well. 1717 */ 1718 static void pl011_enable_interrupts(struct uart_amba_port *uap) 1719 { 1720 unsigned int i; 1721 1722 spin_lock_irq(&uap->port.lock); 1723 1724 /* Clear out any spuriously appearing RX interrupts */ 1725 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); 1726 1727 /* 1728 * RXIS is asserted only when the RX FIFO transitions from below 1729 * to above the trigger threshold. If the RX FIFO is already 1730 * full to the threshold this can't happen and RXIS will now be 1731 * stuck off. Drain the RX FIFO explicitly to fix this: 1732 */ 1733 for (i = 0; i < uap->fifosize * 2; ++i) { 1734 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE) 1735 break; 1736 1737 pl011_read(uap, REG_DR); 1738 } 1739 1740 uap->im = UART011_RTIM; 1741 if (!pl011_dma_rx_running(uap)) 1742 uap->im |= UART011_RXIM; 1743 pl011_write(uap->im, uap, REG_IMSC); 1744 spin_unlock_irq(&uap->port.lock); 1745 } 1746 1747 static int pl011_startup(struct uart_port *port) 1748 { 1749 struct uart_amba_port *uap = 1750 container_of(port, struct uart_amba_port, port); 1751 unsigned int cr; 1752 int retval; 1753 1754 retval = pl011_hwinit(port); 1755 if (retval) 1756 goto clk_dis; 1757 1758 retval = pl011_allocate_irq(uap); 1759 if (retval) 1760 goto clk_dis; 1761 1762 pl011_write(uap->vendor->ifls, uap, REG_IFLS); 1763 1764 spin_lock_irq(&uap->port.lock); 1765 1766 /* restore RTS and DTR */ 1767 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); 1768 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; 1769 pl011_write(cr, uap, REG_CR); 1770 1771 spin_unlock_irq(&uap->port.lock); 1772 1773 /* 1774 * initialise the old status of the modem signals 1775 */ 1776 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1777 1778 /* Startup DMA */ 1779 pl011_dma_startup(uap); 1780 1781 pl011_enable_interrupts(uap); 1782 1783 return 0; 1784 1785 clk_dis: 1786 clk_disable_unprepare(uap->clk); 1787 return retval; 1788 } 1789 1790 static int sbsa_uart_startup(struct uart_port *port) 1791 { 1792 struct uart_amba_port *uap = 1793 container_of(port, struct uart_amba_port, port); 1794 int retval; 1795 1796 retval = pl011_hwinit(port); 1797 if (retval) 1798 return retval; 1799 1800 retval = pl011_allocate_irq(uap); 1801 if (retval) 1802 return retval; 1803 1804 /* The SBSA UART does not support any modem status lines. */ 1805 uap->old_status = 0; 1806 1807 pl011_enable_interrupts(uap); 1808 1809 return 0; 1810 } 1811 1812 static void pl011_shutdown_channel(struct uart_amba_port *uap, 1813 unsigned int lcrh) 1814 { 1815 unsigned long val; 1816 1817 val = pl011_read(uap, lcrh); 1818 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); 1819 pl011_write(val, uap, lcrh); 1820 } 1821 1822 /* 1823 * disable the port. It should not disable RTS and DTR. 1824 * Also RTS and DTR state should be preserved to restore 1825 * it during startup(). 1826 */ 1827 static void pl011_disable_uart(struct uart_amba_port *uap) 1828 { 1829 unsigned int cr; 1830 1831 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1832 spin_lock_irq(&uap->port.lock); 1833 cr = pl011_read(uap, REG_CR); 1834 uap->old_cr = cr; 1835 cr &= UART011_CR_RTS | UART011_CR_DTR; 1836 cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 1837 pl011_write(cr, uap, REG_CR); 1838 spin_unlock_irq(&uap->port.lock); 1839 1840 /* 1841 * disable break condition and fifos 1842 */ 1843 pl011_shutdown_channel(uap, REG_LCRH_RX); 1844 if (pl011_split_lcrh(uap)) 1845 pl011_shutdown_channel(uap, REG_LCRH_TX); 1846 } 1847 1848 static void pl011_disable_interrupts(struct uart_amba_port *uap) 1849 { 1850 spin_lock_irq(&uap->port.lock); 1851 1852 /* mask all interrupts and clear all pending ones */ 1853 uap->im = 0; 1854 pl011_write(uap->im, uap, REG_IMSC); 1855 pl011_write(0xffff, uap, REG_ICR); 1856 1857 spin_unlock_irq(&uap->port.lock); 1858 } 1859 1860 static void pl011_shutdown(struct uart_port *port) 1861 { 1862 struct uart_amba_port *uap = 1863 container_of(port, struct uart_amba_port, port); 1864 1865 pl011_disable_interrupts(uap); 1866 1867 pl011_dma_shutdown(uap); 1868 1869 free_irq(uap->port.irq, uap); 1870 1871 pl011_disable_uart(uap); 1872 1873 /* 1874 * Shut down the clock producer 1875 */ 1876 clk_disable_unprepare(uap->clk); 1877 /* Optionally let pins go into sleep states */ 1878 pinctrl_pm_select_sleep_state(port->dev); 1879 1880 if (dev_get_platdata(uap->port.dev)) { 1881 struct amba_pl011_data *plat; 1882 1883 plat = dev_get_platdata(uap->port.dev); 1884 if (plat->exit) 1885 plat->exit(); 1886 } 1887 1888 if (uap->port.ops->flush_buffer) 1889 uap->port.ops->flush_buffer(port); 1890 } 1891 1892 static void sbsa_uart_shutdown(struct uart_port *port) 1893 { 1894 struct uart_amba_port *uap = 1895 container_of(port, struct uart_amba_port, port); 1896 1897 pl011_disable_interrupts(uap); 1898 1899 free_irq(uap->port.irq, uap); 1900 1901 if (uap->port.ops->flush_buffer) 1902 uap->port.ops->flush_buffer(port); 1903 } 1904 1905 static void 1906 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) 1907 { 1908 port->read_status_mask = UART011_DR_OE | 255; 1909 if (termios->c_iflag & INPCK) 1910 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; 1911 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1912 port->read_status_mask |= UART011_DR_BE; 1913 1914 /* 1915 * Characters to ignore 1916 */ 1917 port->ignore_status_mask = 0; 1918 if (termios->c_iflag & IGNPAR) 1919 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; 1920 if (termios->c_iflag & IGNBRK) { 1921 port->ignore_status_mask |= UART011_DR_BE; 1922 /* 1923 * If we're ignoring parity and break indicators, 1924 * ignore overruns too (for real raw support). 1925 */ 1926 if (termios->c_iflag & IGNPAR) 1927 port->ignore_status_mask |= UART011_DR_OE; 1928 } 1929 1930 /* 1931 * Ignore all characters if CREAD is not set. 1932 */ 1933 if ((termios->c_cflag & CREAD) == 0) 1934 port->ignore_status_mask |= UART_DUMMY_DR_RX; 1935 } 1936 1937 static void 1938 pl011_set_termios(struct uart_port *port, struct ktermios *termios, 1939 struct ktermios *old) 1940 { 1941 struct uart_amba_port *uap = 1942 container_of(port, struct uart_amba_port, port); 1943 unsigned int lcr_h, old_cr; 1944 unsigned long flags; 1945 unsigned int baud, quot, clkdiv; 1946 1947 if (uap->vendor->oversampling) 1948 clkdiv = 8; 1949 else 1950 clkdiv = 16; 1951 1952 /* 1953 * Ask the core to calculate the divisor for us. 1954 */ 1955 baud = uart_get_baud_rate(port, termios, old, 0, 1956 port->uartclk / clkdiv); 1957 #ifdef CONFIG_DMA_ENGINE 1958 /* 1959 * Adjust RX DMA polling rate with baud rate if not specified. 1960 */ 1961 if (uap->dmarx.auto_poll_rate) 1962 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); 1963 #endif 1964 1965 if (baud > port->uartclk/16) 1966 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); 1967 else 1968 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); 1969 1970 switch (termios->c_cflag & CSIZE) { 1971 case CS5: 1972 lcr_h = UART01x_LCRH_WLEN_5; 1973 break; 1974 case CS6: 1975 lcr_h = UART01x_LCRH_WLEN_6; 1976 break; 1977 case CS7: 1978 lcr_h = UART01x_LCRH_WLEN_7; 1979 break; 1980 default: // CS8 1981 lcr_h = UART01x_LCRH_WLEN_8; 1982 break; 1983 } 1984 if (termios->c_cflag & CSTOPB) 1985 lcr_h |= UART01x_LCRH_STP2; 1986 if (termios->c_cflag & PARENB) { 1987 lcr_h |= UART01x_LCRH_PEN; 1988 if (!(termios->c_cflag & PARODD)) 1989 lcr_h |= UART01x_LCRH_EPS; 1990 if (termios->c_cflag & CMSPAR) 1991 lcr_h |= UART011_LCRH_SPS; 1992 } 1993 if (uap->fifosize > 1) 1994 lcr_h |= UART01x_LCRH_FEN; 1995 1996 spin_lock_irqsave(&port->lock, flags); 1997 1998 /* 1999 * Update the per-port timeout. 2000 */ 2001 uart_update_timeout(port, termios->c_cflag, baud); 2002 2003 pl011_setup_status_masks(port, termios); 2004 2005 if (UART_ENABLE_MS(port, termios->c_cflag)) 2006 pl011_enable_ms(port); 2007 2008 /* first, disable everything */ 2009 old_cr = pl011_read(uap, REG_CR); 2010 pl011_write(0, uap, REG_CR); 2011 2012 if (termios->c_cflag & CRTSCTS) { 2013 if (old_cr & UART011_CR_RTS) 2014 old_cr |= UART011_CR_RTSEN; 2015 2016 old_cr |= UART011_CR_CTSEN; 2017 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 2018 } else { 2019 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); 2020 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 2021 } 2022 2023 if (uap->vendor->oversampling) { 2024 if (baud > port->uartclk / 16) 2025 old_cr |= ST_UART011_CR_OVSFACT; 2026 else 2027 old_cr &= ~ST_UART011_CR_OVSFACT; 2028 } 2029 2030 /* 2031 * Workaround for the ST Micro oversampling variants to 2032 * increase the bitrate slightly, by lowering the divisor, 2033 * to avoid delayed sampling of start bit at high speeds, 2034 * else we see data corruption. 2035 */ 2036 if (uap->vendor->oversampling) { 2037 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) 2038 quot -= 1; 2039 else if ((baud > 3250000) && (quot > 2)) 2040 quot -= 2; 2041 } 2042 /* Set baud rate */ 2043 pl011_write(quot & 0x3f, uap, REG_FBRD); 2044 pl011_write(quot >> 6, uap, REG_IBRD); 2045 2046 /* 2047 * ----------v----------v----------v----------v----- 2048 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER 2049 * REG_FBRD & REG_IBRD. 2050 * ----------^----------^----------^----------^----- 2051 */ 2052 pl011_write_lcr_h(uap, lcr_h); 2053 pl011_write(old_cr, uap, REG_CR); 2054 2055 spin_unlock_irqrestore(&port->lock, flags); 2056 } 2057 2058 static void 2059 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, 2060 struct ktermios *old) 2061 { 2062 struct uart_amba_port *uap = 2063 container_of(port, struct uart_amba_port, port); 2064 unsigned long flags; 2065 2066 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); 2067 2068 /* The SBSA UART only supports 8n1 without hardware flow control. */ 2069 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 2070 termios->c_cflag &= ~(CMSPAR | CRTSCTS); 2071 termios->c_cflag |= CS8 | CLOCAL; 2072 2073 spin_lock_irqsave(&port->lock, flags); 2074 uart_update_timeout(port, CS8, uap->fixed_baud); 2075 pl011_setup_status_masks(port, termios); 2076 spin_unlock_irqrestore(&port->lock, flags); 2077 } 2078 2079 static const char *pl011_type(struct uart_port *port) 2080 { 2081 struct uart_amba_port *uap = 2082 container_of(port, struct uart_amba_port, port); 2083 return uap->port.type == PORT_AMBA ? uap->type : NULL; 2084 } 2085 2086 /* 2087 * Release the memory region(s) being used by 'port' 2088 */ 2089 static void pl011_release_port(struct uart_port *port) 2090 { 2091 release_mem_region(port->mapbase, SZ_4K); 2092 } 2093 2094 /* 2095 * Request the memory region(s) being used by 'port' 2096 */ 2097 static int pl011_request_port(struct uart_port *port) 2098 { 2099 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") 2100 != NULL ? 0 : -EBUSY; 2101 } 2102 2103 /* 2104 * Configure/autoconfigure the port. 2105 */ 2106 static void pl011_config_port(struct uart_port *port, int flags) 2107 { 2108 if (flags & UART_CONFIG_TYPE) { 2109 port->type = PORT_AMBA; 2110 pl011_request_port(port); 2111 } 2112 } 2113 2114 /* 2115 * verify the new serial_struct (for TIOCSSERIAL). 2116 */ 2117 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) 2118 { 2119 int ret = 0; 2120 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 2121 ret = -EINVAL; 2122 if (ser->irq < 0 || ser->irq >= nr_irqs) 2123 ret = -EINVAL; 2124 if (ser->baud_base < 9600) 2125 ret = -EINVAL; 2126 return ret; 2127 } 2128 2129 static const struct uart_ops amba_pl011_pops = { 2130 .tx_empty = pl011_tx_empty, 2131 .set_mctrl = pl011_set_mctrl, 2132 .get_mctrl = pl011_get_mctrl, 2133 .stop_tx = pl011_stop_tx, 2134 .start_tx = pl011_start_tx, 2135 .stop_rx = pl011_stop_rx, 2136 .enable_ms = pl011_enable_ms, 2137 .break_ctl = pl011_break_ctl, 2138 .startup = pl011_startup, 2139 .shutdown = pl011_shutdown, 2140 .flush_buffer = pl011_dma_flush_buffer, 2141 .set_termios = pl011_set_termios, 2142 .type = pl011_type, 2143 .release_port = pl011_release_port, 2144 .request_port = pl011_request_port, 2145 .config_port = pl011_config_port, 2146 .verify_port = pl011_verify_port, 2147 #ifdef CONFIG_CONSOLE_POLL 2148 .poll_init = pl011_hwinit, 2149 .poll_get_char = pl011_get_poll_char, 2150 .poll_put_char = pl011_put_poll_char, 2151 #endif 2152 }; 2153 2154 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 2155 { 2156 } 2157 2158 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) 2159 { 2160 return 0; 2161 } 2162 2163 static const struct uart_ops sbsa_uart_pops = { 2164 .tx_empty = pl011_tx_empty, 2165 .set_mctrl = sbsa_uart_set_mctrl, 2166 .get_mctrl = sbsa_uart_get_mctrl, 2167 .stop_tx = pl011_stop_tx, 2168 .start_tx = pl011_start_tx, 2169 .stop_rx = pl011_stop_rx, 2170 .startup = sbsa_uart_startup, 2171 .shutdown = sbsa_uart_shutdown, 2172 .set_termios = sbsa_uart_set_termios, 2173 .type = pl011_type, 2174 .release_port = pl011_release_port, 2175 .request_port = pl011_request_port, 2176 .config_port = pl011_config_port, 2177 .verify_port = pl011_verify_port, 2178 #ifdef CONFIG_CONSOLE_POLL 2179 .poll_init = pl011_hwinit, 2180 .poll_get_char = pl011_get_poll_char, 2181 .poll_put_char = pl011_put_poll_char, 2182 #endif 2183 }; 2184 2185 static struct uart_amba_port *amba_ports[UART_NR]; 2186 2187 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE 2188 2189 static void pl011_console_putchar(struct uart_port *port, int ch) 2190 { 2191 struct uart_amba_port *uap = 2192 container_of(port, struct uart_amba_port, port); 2193 2194 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 2195 cpu_relax(); 2196 pl011_write(ch, uap, REG_DR); 2197 } 2198 2199 static void 2200 pl011_console_write(struct console *co, const char *s, unsigned int count) 2201 { 2202 struct uart_amba_port *uap = amba_ports[co->index]; 2203 unsigned int old_cr = 0, new_cr; 2204 unsigned long flags; 2205 int locked = 1; 2206 2207 clk_enable(uap->clk); 2208 2209 local_irq_save(flags); 2210 if (uap->port.sysrq) 2211 locked = 0; 2212 else if (oops_in_progress) 2213 locked = spin_trylock(&uap->port.lock); 2214 else 2215 spin_lock(&uap->port.lock); 2216 2217 /* 2218 * First save the CR then disable the interrupts 2219 */ 2220 if (!uap->vendor->always_enabled) { 2221 old_cr = pl011_read(uap, REG_CR); 2222 new_cr = old_cr & ~UART011_CR_CTSEN; 2223 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 2224 pl011_write(new_cr, uap, REG_CR); 2225 } 2226 2227 uart_console_write(&uap->port, s, count, pl011_console_putchar); 2228 2229 /* 2230 * Finally, wait for transmitter to become empty and restore the 2231 * TCR. Allow feature register bits to be inverted to work around 2232 * errata. 2233 */ 2234 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) 2235 & uap->vendor->fr_busy) 2236 cpu_relax(); 2237 if (!uap->vendor->always_enabled) 2238 pl011_write(old_cr, uap, REG_CR); 2239 2240 if (locked) 2241 spin_unlock(&uap->port.lock); 2242 local_irq_restore(flags); 2243 2244 clk_disable(uap->clk); 2245 } 2246 2247 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud, 2248 int *parity, int *bits) 2249 { 2250 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) { 2251 unsigned int lcr_h, ibrd, fbrd; 2252 2253 lcr_h = pl011_read(uap, REG_LCRH_TX); 2254 2255 *parity = 'n'; 2256 if (lcr_h & UART01x_LCRH_PEN) { 2257 if (lcr_h & UART01x_LCRH_EPS) 2258 *parity = 'e'; 2259 else 2260 *parity = 'o'; 2261 } 2262 2263 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 2264 *bits = 7; 2265 else 2266 *bits = 8; 2267 2268 ibrd = pl011_read(uap, REG_IBRD); 2269 fbrd = pl011_read(uap, REG_FBRD); 2270 2271 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); 2272 2273 if (uap->vendor->oversampling) { 2274 if (pl011_read(uap, REG_CR) 2275 & ST_UART011_CR_OVSFACT) 2276 *baud *= 2; 2277 } 2278 } 2279 } 2280 2281 static int pl011_console_setup(struct console *co, char *options) 2282 { 2283 struct uart_amba_port *uap; 2284 int baud = 38400; 2285 int bits = 8; 2286 int parity = 'n'; 2287 int flow = 'n'; 2288 int ret; 2289 2290 /* 2291 * Check whether an invalid uart number has been specified, and 2292 * if so, search for the first available port that does have 2293 * console support. 2294 */ 2295 if (co->index >= UART_NR) 2296 co->index = 0; 2297 uap = amba_ports[co->index]; 2298 if (!uap) 2299 return -ENODEV; 2300 2301 /* Allow pins to be muxed in and configured */ 2302 pinctrl_pm_select_default_state(uap->port.dev); 2303 2304 ret = clk_prepare(uap->clk); 2305 if (ret) 2306 return ret; 2307 2308 if (dev_get_platdata(uap->port.dev)) { 2309 struct amba_pl011_data *plat; 2310 2311 plat = dev_get_platdata(uap->port.dev); 2312 if (plat->init) 2313 plat->init(); 2314 } 2315 2316 uap->port.uartclk = clk_get_rate(uap->clk); 2317 2318 if (uap->vendor->fixed_options) { 2319 baud = uap->fixed_baud; 2320 } else { 2321 if (options) 2322 uart_parse_options(options, 2323 &baud, &parity, &bits, &flow); 2324 else 2325 pl011_console_get_options(uap, &baud, &parity, &bits); 2326 } 2327 2328 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 2329 } 2330 2331 /** 2332 * pl011_console_match - non-standard console matching 2333 * @co: registering console 2334 * @name: name from console command line 2335 * @idx: index from console command line 2336 * @options: ptr to option string from console command line 2337 * 2338 * Only attempts to match console command lines of the form: 2339 * console=pl011,mmio|mmio32,<addr>[,<options>] 2340 * console=pl011,0x<addr>[,<options>] 2341 * This form is used to register an initial earlycon boot console and 2342 * replace it with the amba_console at pl011 driver init. 2343 * 2344 * Performs console setup for a match (as required by interface) 2345 * If no <options> are specified, then assume the h/w is already setup. 2346 * 2347 * Returns 0 if console matches; otherwise non-zero to use default matching 2348 */ 2349 static int pl011_console_match(struct console *co, char *name, int idx, 2350 char *options) 2351 { 2352 unsigned char iotype; 2353 resource_size_t addr; 2354 int i; 2355 2356 /* 2357 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum 2358 * have a distinct console name, so make sure we check for that. 2359 * The actual implementation of the erratum occurs in the probe 2360 * function. 2361 */ 2362 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0)) 2363 return -ENODEV; 2364 2365 if (uart_parse_earlycon(options, &iotype, &addr, &options)) 2366 return -ENODEV; 2367 2368 if (iotype != UPIO_MEM && iotype != UPIO_MEM32) 2369 return -ENODEV; 2370 2371 /* try to match the port specified on the command line */ 2372 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2373 struct uart_port *port; 2374 2375 if (!amba_ports[i]) 2376 continue; 2377 2378 port = &amba_ports[i]->port; 2379 2380 if (port->mapbase != addr) 2381 continue; 2382 2383 co->index = i; 2384 port->cons = co; 2385 return pl011_console_setup(co, options); 2386 } 2387 2388 return -ENODEV; 2389 } 2390 2391 static struct uart_driver amba_reg; 2392 static struct console amba_console = { 2393 .name = "ttyAMA", 2394 .write = pl011_console_write, 2395 .device = uart_console_device, 2396 .setup = pl011_console_setup, 2397 .match = pl011_console_match, 2398 .flags = CON_PRINTBUFFER | CON_ANYTIME, 2399 .index = -1, 2400 .data = &amba_reg, 2401 }; 2402 2403 #define AMBA_CONSOLE (&amba_console) 2404 2405 static void qdf2400_e44_putc(struct uart_port *port, int c) 2406 { 2407 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2408 cpu_relax(); 2409 writel(c, port->membase + UART01x_DR); 2410 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) 2411 cpu_relax(); 2412 } 2413 2414 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n) 2415 { 2416 struct earlycon_device *dev = con->data; 2417 2418 uart_console_write(&dev->port, s, n, qdf2400_e44_putc); 2419 } 2420 2421 static void pl011_putc(struct uart_port *port, int c) 2422 { 2423 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2424 cpu_relax(); 2425 if (port->iotype == UPIO_MEM32) 2426 writel(c, port->membase + UART01x_DR); 2427 else 2428 writeb(c, port->membase + UART01x_DR); 2429 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) 2430 cpu_relax(); 2431 } 2432 2433 static void pl011_early_write(struct console *con, const char *s, unsigned n) 2434 { 2435 struct earlycon_device *dev = con->data; 2436 2437 uart_console_write(&dev->port, s, n, pl011_putc); 2438 } 2439 2440 #ifdef CONFIG_CONSOLE_POLL 2441 static int pl011_getc(struct uart_port *port) 2442 { 2443 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE) 2444 return NO_POLL_CHAR; 2445 2446 if (port->iotype == UPIO_MEM32) 2447 return readl(port->membase + UART01x_DR); 2448 else 2449 return readb(port->membase + UART01x_DR); 2450 } 2451 2452 static int pl011_early_read(struct console *con, char *s, unsigned int n) 2453 { 2454 struct earlycon_device *dev = con->data; 2455 int ch, num_read = 0; 2456 2457 while (num_read < n) { 2458 ch = pl011_getc(&dev->port); 2459 if (ch == NO_POLL_CHAR) 2460 break; 2461 2462 s[num_read++] = ch; 2463 } 2464 2465 return num_read; 2466 } 2467 #else 2468 #define pl011_early_read NULL 2469 #endif 2470 2471 /* 2472 * On non-ACPI systems, earlycon is enabled by specifying 2473 * "earlycon=pl011,<address>" on the kernel command line. 2474 * 2475 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table, 2476 * by specifying only "earlycon" on the command line. Because it requires 2477 * SPCR, the console starts after ACPI is parsed, which is later than a 2478 * traditional early console. 2479 * 2480 * To get the traditional early console that starts before ACPI is parsed, 2481 * specify the full "earlycon=pl011,<address>" option. 2482 */ 2483 static int __init pl011_early_console_setup(struct earlycon_device *device, 2484 const char *opt) 2485 { 2486 if (!device->port.membase) 2487 return -ENODEV; 2488 2489 device->con->write = pl011_early_write; 2490 device->con->read = pl011_early_read; 2491 2492 return 0; 2493 } 2494 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); 2495 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup); 2496 2497 /* 2498 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by 2499 * Erratum 44, traditional earlycon can be enabled by specifying 2500 * "earlycon=qdf2400_e44,<address>". Any options are ignored. 2501 * 2502 * Alternatively, you can just specify "earlycon", and the early console 2503 * will be enabled with the information from the SPCR table. In this 2504 * case, the SPCR code will detect the need for the E44 work-around, 2505 * and set the console name to "qdf2400_e44". 2506 */ 2507 static int __init 2508 qdf2400_e44_early_console_setup(struct earlycon_device *device, 2509 const char *opt) 2510 { 2511 if (!device->port.membase) 2512 return -ENODEV; 2513 2514 device->con->write = qdf2400_e44_early_write; 2515 return 0; 2516 } 2517 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup); 2518 2519 #else 2520 #define AMBA_CONSOLE NULL 2521 #endif 2522 2523 static struct uart_driver amba_reg = { 2524 .owner = THIS_MODULE, 2525 .driver_name = "ttyAMA", 2526 .dev_name = "ttyAMA", 2527 .major = SERIAL_AMBA_MAJOR, 2528 .minor = SERIAL_AMBA_MINOR, 2529 .nr = UART_NR, 2530 .cons = AMBA_CONSOLE, 2531 }; 2532 2533 static int pl011_probe_dt_alias(int index, struct device *dev) 2534 { 2535 struct device_node *np; 2536 static bool seen_dev_with_alias = false; 2537 static bool seen_dev_without_alias = false; 2538 int ret = index; 2539 2540 if (!IS_ENABLED(CONFIG_OF)) 2541 return ret; 2542 2543 np = dev->of_node; 2544 if (!np) 2545 return ret; 2546 2547 ret = of_alias_get_id(np, "serial"); 2548 if (ret < 0) { 2549 seen_dev_without_alias = true; 2550 ret = index; 2551 } else { 2552 seen_dev_with_alias = true; 2553 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { 2554 dev_warn(dev, "requested serial port %d not available.\n", ret); 2555 ret = index; 2556 } 2557 } 2558 2559 if (seen_dev_with_alias && seen_dev_without_alias) 2560 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); 2561 2562 return ret; 2563 } 2564 2565 /* unregisters the driver also if no more ports are left */ 2566 static void pl011_unregister_port(struct uart_amba_port *uap) 2567 { 2568 int i; 2569 bool busy = false; 2570 2571 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2572 if (amba_ports[i] == uap) 2573 amba_ports[i] = NULL; 2574 else if (amba_ports[i]) 2575 busy = true; 2576 } 2577 pl011_dma_remove(uap); 2578 if (!busy) 2579 uart_unregister_driver(&amba_reg); 2580 } 2581 2582 static int pl011_find_free_port(void) 2583 { 2584 int i; 2585 2586 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2587 if (amba_ports[i] == NULL) 2588 return i; 2589 2590 return -EBUSY; 2591 } 2592 2593 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, 2594 struct resource *mmiobase, int index) 2595 { 2596 void __iomem *base; 2597 2598 base = devm_ioremap_resource(dev, mmiobase); 2599 if (IS_ERR(base)) 2600 return PTR_ERR(base); 2601 2602 index = pl011_probe_dt_alias(index, dev); 2603 2604 uap->old_cr = 0; 2605 uap->port.dev = dev; 2606 uap->port.mapbase = mmiobase->start; 2607 uap->port.membase = base; 2608 uap->port.fifosize = uap->fifosize; 2609 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE); 2610 uap->port.flags = UPF_BOOT_AUTOCONF; 2611 uap->port.line = index; 2612 2613 amba_ports[index] = uap; 2614 2615 return 0; 2616 } 2617 2618 static int pl011_register_port(struct uart_amba_port *uap) 2619 { 2620 int ret, i; 2621 2622 /* Ensure interrupts from this UART are masked and cleared */ 2623 pl011_write(0, uap, REG_IMSC); 2624 pl011_write(0xffff, uap, REG_ICR); 2625 2626 if (!amba_reg.state) { 2627 ret = uart_register_driver(&amba_reg); 2628 if (ret < 0) { 2629 dev_err(uap->port.dev, 2630 "Failed to register AMBA-PL011 driver\n"); 2631 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2632 if (amba_ports[i] == uap) 2633 amba_ports[i] = NULL; 2634 return ret; 2635 } 2636 } 2637 2638 ret = uart_add_one_port(&amba_reg, &uap->port); 2639 if (ret) 2640 pl011_unregister_port(uap); 2641 2642 return ret; 2643 } 2644 2645 static int pl011_probe(struct amba_device *dev, const struct amba_id *id) 2646 { 2647 struct uart_amba_port *uap; 2648 struct vendor_data *vendor = id->data; 2649 int portnr, ret; 2650 2651 portnr = pl011_find_free_port(); 2652 if (portnr < 0) 2653 return portnr; 2654 2655 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), 2656 GFP_KERNEL); 2657 if (!uap) 2658 return -ENOMEM; 2659 2660 uap->clk = devm_clk_get(&dev->dev, NULL); 2661 if (IS_ERR(uap->clk)) 2662 return PTR_ERR(uap->clk); 2663 2664 uap->reg_offset = vendor->reg_offset; 2665 uap->vendor = vendor; 2666 uap->fifosize = vendor->get_fifosize(dev); 2667 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 2668 uap->port.irq = dev->irq[0]; 2669 uap->port.ops = &amba_pl011_pops; 2670 2671 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); 2672 2673 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); 2674 if (ret) 2675 return ret; 2676 2677 amba_set_drvdata(dev, uap); 2678 2679 return pl011_register_port(uap); 2680 } 2681 2682 static void pl011_remove(struct amba_device *dev) 2683 { 2684 struct uart_amba_port *uap = amba_get_drvdata(dev); 2685 2686 uart_remove_one_port(&amba_reg, &uap->port); 2687 pl011_unregister_port(uap); 2688 } 2689 2690 #ifdef CONFIG_PM_SLEEP 2691 static int pl011_suspend(struct device *dev) 2692 { 2693 struct uart_amba_port *uap = dev_get_drvdata(dev); 2694 2695 if (!uap) 2696 return -EINVAL; 2697 2698 return uart_suspend_port(&amba_reg, &uap->port); 2699 } 2700 2701 static int pl011_resume(struct device *dev) 2702 { 2703 struct uart_amba_port *uap = dev_get_drvdata(dev); 2704 2705 if (!uap) 2706 return -EINVAL; 2707 2708 return uart_resume_port(&amba_reg, &uap->port); 2709 } 2710 #endif 2711 2712 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); 2713 2714 static int sbsa_uart_probe(struct platform_device *pdev) 2715 { 2716 struct uart_amba_port *uap; 2717 struct resource *r; 2718 int portnr, ret; 2719 int baudrate; 2720 2721 /* 2722 * Check the mandatory baud rate parameter in the DT node early 2723 * so that we can easily exit with the error. 2724 */ 2725 if (pdev->dev.of_node) { 2726 struct device_node *np = pdev->dev.of_node; 2727 2728 ret = of_property_read_u32(np, "current-speed", &baudrate); 2729 if (ret) 2730 return ret; 2731 } else { 2732 baudrate = 115200; 2733 } 2734 2735 portnr = pl011_find_free_port(); 2736 if (portnr < 0) 2737 return portnr; 2738 2739 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), 2740 GFP_KERNEL); 2741 if (!uap) 2742 return -ENOMEM; 2743 2744 ret = platform_get_irq(pdev, 0); 2745 if (ret < 0) 2746 return ret; 2747 uap->port.irq = ret; 2748 2749 #ifdef CONFIG_ACPI_SPCR_TABLE 2750 if (qdf2400_e44_present) { 2751 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n"); 2752 uap->vendor = &vendor_qdt_qdf2400_e44; 2753 } else 2754 #endif 2755 uap->vendor = &vendor_sbsa; 2756 2757 uap->reg_offset = uap->vendor->reg_offset; 2758 uap->fifosize = 32; 2759 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 2760 uap->port.ops = &sbsa_uart_pops; 2761 uap->fixed_baud = baudrate; 2762 2763 snprintf(uap->type, sizeof(uap->type), "SBSA"); 2764 2765 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2766 2767 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); 2768 if (ret) 2769 return ret; 2770 2771 platform_set_drvdata(pdev, uap); 2772 2773 return pl011_register_port(uap); 2774 } 2775 2776 static int sbsa_uart_remove(struct platform_device *pdev) 2777 { 2778 struct uart_amba_port *uap = platform_get_drvdata(pdev); 2779 2780 uart_remove_one_port(&amba_reg, &uap->port); 2781 pl011_unregister_port(uap); 2782 return 0; 2783 } 2784 2785 static const struct of_device_id sbsa_uart_of_match[] = { 2786 { .compatible = "arm,sbsa-uart", }, 2787 {}, 2788 }; 2789 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); 2790 2791 static const struct acpi_device_id __maybe_unused sbsa_uart_acpi_match[] = { 2792 { "ARMH0011", 0 }, 2793 {}, 2794 }; 2795 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); 2796 2797 static struct platform_driver arm_sbsa_uart_platform_driver = { 2798 .probe = sbsa_uart_probe, 2799 .remove = sbsa_uart_remove, 2800 .driver = { 2801 .name = "sbsa-uart", 2802 .pm = &pl011_dev_pm_ops, 2803 .of_match_table = of_match_ptr(sbsa_uart_of_match), 2804 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match), 2805 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), 2806 }, 2807 }; 2808 2809 static const struct amba_id pl011_ids[] = { 2810 { 2811 .id = 0x00041011, 2812 .mask = 0x000fffff, 2813 .data = &vendor_arm, 2814 }, 2815 { 2816 .id = 0x00380802, 2817 .mask = 0x00ffffff, 2818 .data = &vendor_st, 2819 }, 2820 { 2821 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe), 2822 .mask = 0x00ffffff, 2823 .data = &vendor_zte, 2824 }, 2825 { 0, 0 }, 2826 }; 2827 2828 MODULE_DEVICE_TABLE(amba, pl011_ids); 2829 2830 static struct amba_driver pl011_driver = { 2831 .drv = { 2832 .name = "uart-pl011", 2833 .pm = &pl011_dev_pm_ops, 2834 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), 2835 }, 2836 .id_table = pl011_ids, 2837 .probe = pl011_probe, 2838 .remove = pl011_remove, 2839 }; 2840 2841 static int __init pl011_init(void) 2842 { 2843 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); 2844 2845 if (platform_driver_register(&arm_sbsa_uart_platform_driver)) 2846 pr_warn("could not register SBSA UART platform driver\n"); 2847 return amba_driver_register(&pl011_driver); 2848 } 2849 2850 static void __exit pl011_exit(void) 2851 { 2852 platform_driver_unregister(&arm_sbsa_uart_platform_driver); 2853 amba_driver_unregister(&pl011_driver); 2854 } 2855 2856 /* 2857 * While this can be a module, if builtin it's most likely the console 2858 * So let's leave module_exit but move module_init to an earlier place 2859 */ 2860 arch_initcall(pl011_init); 2861 module_exit(pl011_exit); 2862 2863 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 2864 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 2865 MODULE_LICENSE("GPL"); 2866