1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for AMBA serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright 1999 ARM Limited 8 * Copyright (C) 2000 Deep Blue Solutions Ltd. 9 * Copyright (C) 2010 ST-Ericsson SA 10 * 11 * This is a generic driver for ARM AMBA-type serial ports. They 12 * have a lot of 16550-like features, but are not register compatible. 13 * Note that although they do have CTS, DCD and DSR inputs, they do 14 * not have an RI input, nor do they have DTR or RTS outputs. If 15 * required, these have to be supplied via some other means (eg, GPIO) 16 * and hooked into this driver. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/ioport.h> 21 #include <linux/init.h> 22 #include <linux/console.h> 23 #include <linux/sysrq.h> 24 #include <linux/device.h> 25 #include <linux/tty.h> 26 #include <linux/tty_flip.h> 27 #include <linux/serial_core.h> 28 #include <linux/serial.h> 29 #include <linux/amba/bus.h> 30 #include <linux/amba/serial.h> 31 #include <linux/clk.h> 32 #include <linux/slab.h> 33 #include <linux/dmaengine.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/scatterlist.h> 36 #include <linux/delay.h> 37 #include <linux/types.h> 38 #include <linux/of.h> 39 #include <linux/of_device.h> 40 #include <linux/pinctrl/consumer.h> 41 #include <linux/sizes.h> 42 #include <linux/io.h> 43 #include <linux/acpi.h> 44 45 #define UART_NR 14 46 47 #define SERIAL_AMBA_MAJOR 204 48 #define SERIAL_AMBA_MINOR 64 49 #define SERIAL_AMBA_NR UART_NR 50 51 #define AMBA_ISR_PASS_LIMIT 256 52 53 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) 54 #define UART_DUMMY_DR_RX (1 << 16) 55 56 enum { 57 REG_DR, 58 REG_ST_DMAWM, 59 REG_ST_TIMEOUT, 60 REG_FR, 61 REG_LCRH_RX, 62 REG_LCRH_TX, 63 REG_IBRD, 64 REG_FBRD, 65 REG_CR, 66 REG_IFLS, 67 REG_IMSC, 68 REG_RIS, 69 REG_MIS, 70 REG_ICR, 71 REG_DMACR, 72 REG_ST_XFCR, 73 REG_ST_XON1, 74 REG_ST_XON2, 75 REG_ST_XOFF1, 76 REG_ST_XOFF2, 77 REG_ST_ITCR, 78 REG_ST_ITIP, 79 REG_ST_ABCR, 80 REG_ST_ABIMSC, 81 82 /* The size of the array - must be last */ 83 REG_ARRAY_SIZE, 84 }; 85 86 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = { 87 [REG_DR] = UART01x_DR, 88 [REG_FR] = UART01x_FR, 89 [REG_LCRH_RX] = UART011_LCRH, 90 [REG_LCRH_TX] = UART011_LCRH, 91 [REG_IBRD] = UART011_IBRD, 92 [REG_FBRD] = UART011_FBRD, 93 [REG_CR] = UART011_CR, 94 [REG_IFLS] = UART011_IFLS, 95 [REG_IMSC] = UART011_IMSC, 96 [REG_RIS] = UART011_RIS, 97 [REG_MIS] = UART011_MIS, 98 [REG_ICR] = UART011_ICR, 99 [REG_DMACR] = UART011_DMACR, 100 }; 101 102 /* There is by now at least one vendor with differing details, so handle it */ 103 struct vendor_data { 104 const u16 *reg_offset; 105 unsigned int ifls; 106 unsigned int fr_busy; 107 unsigned int fr_dsr; 108 unsigned int fr_cts; 109 unsigned int fr_ri; 110 unsigned int inv_fr; 111 bool access_32b; 112 bool oversampling; 113 bool dma_threshold; 114 bool cts_event_workaround; 115 bool always_enabled; 116 bool fixed_options; 117 118 unsigned int (*get_fifosize)(struct amba_device *dev); 119 }; 120 121 static unsigned int get_fifosize_arm(struct amba_device *dev) 122 { 123 return amba_rev(dev) < 3 ? 16 : 32; 124 } 125 126 static struct vendor_data vendor_arm = { 127 .reg_offset = pl011_std_offsets, 128 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 129 .fr_busy = UART01x_FR_BUSY, 130 .fr_dsr = UART01x_FR_DSR, 131 .fr_cts = UART01x_FR_CTS, 132 .fr_ri = UART011_FR_RI, 133 .oversampling = false, 134 .dma_threshold = false, 135 .cts_event_workaround = false, 136 .always_enabled = false, 137 .fixed_options = false, 138 .get_fifosize = get_fifosize_arm, 139 }; 140 141 static const struct vendor_data vendor_sbsa = { 142 .reg_offset = pl011_std_offsets, 143 .fr_busy = UART01x_FR_BUSY, 144 .fr_dsr = UART01x_FR_DSR, 145 .fr_cts = UART01x_FR_CTS, 146 .fr_ri = UART011_FR_RI, 147 .access_32b = true, 148 .oversampling = false, 149 .dma_threshold = false, 150 .cts_event_workaround = false, 151 .always_enabled = true, 152 .fixed_options = true, 153 }; 154 155 #ifdef CONFIG_ACPI_SPCR_TABLE 156 static const struct vendor_data vendor_qdt_qdf2400_e44 = { 157 .reg_offset = pl011_std_offsets, 158 .fr_busy = UART011_FR_TXFE, 159 .fr_dsr = UART01x_FR_DSR, 160 .fr_cts = UART01x_FR_CTS, 161 .fr_ri = UART011_FR_RI, 162 .inv_fr = UART011_FR_TXFE, 163 .access_32b = true, 164 .oversampling = false, 165 .dma_threshold = false, 166 .cts_event_workaround = false, 167 .always_enabled = true, 168 .fixed_options = true, 169 }; 170 #endif 171 172 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { 173 [REG_DR] = UART01x_DR, 174 [REG_ST_DMAWM] = ST_UART011_DMAWM, 175 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, 176 [REG_FR] = UART01x_FR, 177 [REG_LCRH_RX] = ST_UART011_LCRH_RX, 178 [REG_LCRH_TX] = ST_UART011_LCRH_TX, 179 [REG_IBRD] = UART011_IBRD, 180 [REG_FBRD] = UART011_FBRD, 181 [REG_CR] = UART011_CR, 182 [REG_IFLS] = UART011_IFLS, 183 [REG_IMSC] = UART011_IMSC, 184 [REG_RIS] = UART011_RIS, 185 [REG_MIS] = UART011_MIS, 186 [REG_ICR] = UART011_ICR, 187 [REG_DMACR] = UART011_DMACR, 188 [REG_ST_XFCR] = ST_UART011_XFCR, 189 [REG_ST_XON1] = ST_UART011_XON1, 190 [REG_ST_XON2] = ST_UART011_XON2, 191 [REG_ST_XOFF1] = ST_UART011_XOFF1, 192 [REG_ST_XOFF2] = ST_UART011_XOFF2, 193 [REG_ST_ITCR] = ST_UART011_ITCR, 194 [REG_ST_ITIP] = ST_UART011_ITIP, 195 [REG_ST_ABCR] = ST_UART011_ABCR, 196 [REG_ST_ABIMSC] = ST_UART011_ABIMSC, 197 }; 198 199 static unsigned int get_fifosize_st(struct amba_device *dev) 200 { 201 return 64; 202 } 203 204 static struct vendor_data vendor_st = { 205 .reg_offset = pl011_st_offsets, 206 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, 207 .fr_busy = UART01x_FR_BUSY, 208 .fr_dsr = UART01x_FR_DSR, 209 .fr_cts = UART01x_FR_CTS, 210 .fr_ri = UART011_FR_RI, 211 .oversampling = true, 212 .dma_threshold = true, 213 .cts_event_workaround = true, 214 .always_enabled = false, 215 .fixed_options = false, 216 .get_fifosize = get_fifosize_st, 217 }; 218 219 /* Deals with DMA transactions */ 220 221 struct pl011_sgbuf { 222 struct scatterlist sg; 223 char *buf; 224 }; 225 226 struct pl011_dmarx_data { 227 struct dma_chan *chan; 228 struct completion complete; 229 bool use_buf_b; 230 struct pl011_sgbuf sgbuf_a; 231 struct pl011_sgbuf sgbuf_b; 232 dma_cookie_t cookie; 233 bool running; 234 struct timer_list timer; 235 unsigned int last_residue; 236 unsigned long last_jiffies; 237 bool auto_poll_rate; 238 unsigned int poll_rate; 239 unsigned int poll_timeout; 240 }; 241 242 struct pl011_dmatx_data { 243 struct dma_chan *chan; 244 struct scatterlist sg; 245 char *buf; 246 bool queued; 247 }; 248 249 /* 250 * We wrap our port structure around the generic uart_port. 251 */ 252 struct uart_amba_port { 253 struct uart_port port; 254 const u16 *reg_offset; 255 struct clk *clk; 256 const struct vendor_data *vendor; 257 unsigned int dmacr; /* dma control reg */ 258 unsigned int im; /* interrupt mask */ 259 unsigned int old_status; 260 unsigned int fifosize; /* vendor-specific */ 261 unsigned int fixed_baud; /* vendor-set fixed baud rate */ 262 char type[12]; 263 bool rs485_tx_started; 264 unsigned int rs485_tx_drain_interval; /* usecs */ 265 #ifdef CONFIG_DMA_ENGINE 266 /* DMA stuff */ 267 bool using_tx_dma; 268 bool using_rx_dma; 269 struct pl011_dmarx_data dmarx; 270 struct pl011_dmatx_data dmatx; 271 bool dma_probed; 272 #endif 273 }; 274 275 static unsigned int pl011_tx_empty(struct uart_port *port); 276 277 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, 278 unsigned int reg) 279 { 280 return uap->reg_offset[reg]; 281 } 282 283 static unsigned int pl011_read(const struct uart_amba_port *uap, 284 unsigned int reg) 285 { 286 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 287 288 return (uap->port.iotype == UPIO_MEM32) ? 289 readl_relaxed(addr) : readw_relaxed(addr); 290 } 291 292 static void pl011_write(unsigned int val, const struct uart_amba_port *uap, 293 unsigned int reg) 294 { 295 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 296 297 if (uap->port.iotype == UPIO_MEM32) 298 writel_relaxed(val, addr); 299 else 300 writew_relaxed(val, addr); 301 } 302 303 /* 304 * Reads up to 256 characters from the FIFO or until it's empty and 305 * inserts them into the TTY layer. Returns the number of characters 306 * read from the FIFO. 307 */ 308 static int pl011_fifo_to_tty(struct uart_amba_port *uap) 309 { 310 unsigned int ch, flag, fifotaken; 311 int sysrq; 312 u16 status; 313 314 for (fifotaken = 0; fifotaken != 256; fifotaken++) { 315 status = pl011_read(uap, REG_FR); 316 if (status & UART01x_FR_RXFE) 317 break; 318 319 /* Take chars from the FIFO and update status */ 320 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; 321 flag = TTY_NORMAL; 322 uap->port.icount.rx++; 323 324 if (unlikely(ch & UART_DR_ERROR)) { 325 if (ch & UART011_DR_BE) { 326 ch &= ~(UART011_DR_FE | UART011_DR_PE); 327 uap->port.icount.brk++; 328 if (uart_handle_break(&uap->port)) 329 continue; 330 } else if (ch & UART011_DR_PE) 331 uap->port.icount.parity++; 332 else if (ch & UART011_DR_FE) 333 uap->port.icount.frame++; 334 if (ch & UART011_DR_OE) 335 uap->port.icount.overrun++; 336 337 ch &= uap->port.read_status_mask; 338 339 if (ch & UART011_DR_BE) 340 flag = TTY_BREAK; 341 else if (ch & UART011_DR_PE) 342 flag = TTY_PARITY; 343 else if (ch & UART011_DR_FE) 344 flag = TTY_FRAME; 345 } 346 347 spin_unlock(&uap->port.lock); 348 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255); 349 spin_lock(&uap->port.lock); 350 351 if (!sysrq) 352 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); 353 } 354 355 return fifotaken; 356 } 357 358 359 /* 360 * All the DMA operation mode stuff goes inside this ifdef. 361 * This assumes that you have a generic DMA device interface, 362 * no custom DMA interfaces are supported. 363 */ 364 #ifdef CONFIG_DMA_ENGINE 365 366 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE 367 368 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, 369 enum dma_data_direction dir) 370 { 371 dma_addr_t dma_addr; 372 373 sg->buf = dma_alloc_coherent(chan->device->dev, 374 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); 375 if (!sg->buf) 376 return -ENOMEM; 377 378 sg_init_table(&sg->sg, 1); 379 sg_set_page(&sg->sg, phys_to_page(dma_addr), 380 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); 381 sg_dma_address(&sg->sg) = dma_addr; 382 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; 383 384 return 0; 385 } 386 387 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, 388 enum dma_data_direction dir) 389 { 390 if (sg->buf) { 391 dma_free_coherent(chan->device->dev, 392 PL011_DMA_BUFFER_SIZE, sg->buf, 393 sg_dma_address(&sg->sg)); 394 } 395 } 396 397 static void pl011_dma_probe(struct uart_amba_port *uap) 398 { 399 /* DMA is the sole user of the platform data right now */ 400 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); 401 struct device *dev = uap->port.dev; 402 struct dma_slave_config tx_conf = { 403 .dst_addr = uap->port.mapbase + 404 pl011_reg_to_offset(uap, REG_DR), 405 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 406 .direction = DMA_MEM_TO_DEV, 407 .dst_maxburst = uap->fifosize >> 1, 408 .device_fc = false, 409 }; 410 struct dma_chan *chan; 411 dma_cap_mask_t mask; 412 413 uap->dma_probed = true; 414 chan = dma_request_chan(dev, "tx"); 415 if (IS_ERR(chan)) { 416 if (PTR_ERR(chan) == -EPROBE_DEFER) { 417 uap->dma_probed = false; 418 return; 419 } 420 421 /* We need platform data */ 422 if (!plat || !plat->dma_filter) { 423 dev_info(uap->port.dev, "no DMA platform data\n"); 424 return; 425 } 426 427 /* Try to acquire a generic DMA engine slave TX channel */ 428 dma_cap_zero(mask); 429 dma_cap_set(DMA_SLAVE, mask); 430 431 chan = dma_request_channel(mask, plat->dma_filter, 432 plat->dma_tx_param); 433 if (!chan) { 434 dev_err(uap->port.dev, "no TX DMA channel!\n"); 435 return; 436 } 437 } 438 439 dmaengine_slave_config(chan, &tx_conf); 440 uap->dmatx.chan = chan; 441 442 dev_info(uap->port.dev, "DMA channel TX %s\n", 443 dma_chan_name(uap->dmatx.chan)); 444 445 /* Optionally make use of an RX channel as well */ 446 chan = dma_request_slave_channel(dev, "rx"); 447 448 if (!chan && plat && plat->dma_rx_param) { 449 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); 450 451 if (!chan) { 452 dev_err(uap->port.dev, "no RX DMA channel!\n"); 453 return; 454 } 455 } 456 457 if (chan) { 458 struct dma_slave_config rx_conf = { 459 .src_addr = uap->port.mapbase + 460 pl011_reg_to_offset(uap, REG_DR), 461 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 462 .direction = DMA_DEV_TO_MEM, 463 .src_maxburst = uap->fifosize >> 2, 464 .device_fc = false, 465 }; 466 struct dma_slave_caps caps; 467 468 /* 469 * Some DMA controllers provide information on their capabilities. 470 * If the controller does, check for suitable residue processing 471 * otherwise assime all is well. 472 */ 473 if (0 == dma_get_slave_caps(chan, &caps)) { 474 if (caps.residue_granularity == 475 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { 476 dma_release_channel(chan); 477 dev_info(uap->port.dev, 478 "RX DMA disabled - no residue processing\n"); 479 return; 480 } 481 } 482 dmaengine_slave_config(chan, &rx_conf); 483 uap->dmarx.chan = chan; 484 485 uap->dmarx.auto_poll_rate = false; 486 if (plat && plat->dma_rx_poll_enable) { 487 /* Set poll rate if specified. */ 488 if (plat->dma_rx_poll_rate) { 489 uap->dmarx.auto_poll_rate = false; 490 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; 491 } else { 492 /* 493 * 100 ms defaults to poll rate if not 494 * specified. This will be adjusted with 495 * the baud rate at set_termios. 496 */ 497 uap->dmarx.auto_poll_rate = true; 498 uap->dmarx.poll_rate = 100; 499 } 500 /* 3 secs defaults poll_timeout if not specified. */ 501 if (plat->dma_rx_poll_timeout) 502 uap->dmarx.poll_timeout = 503 plat->dma_rx_poll_timeout; 504 else 505 uap->dmarx.poll_timeout = 3000; 506 } else if (!plat && dev->of_node) { 507 uap->dmarx.auto_poll_rate = of_property_read_bool( 508 dev->of_node, "auto-poll"); 509 if (uap->dmarx.auto_poll_rate) { 510 u32 x; 511 512 if (0 == of_property_read_u32(dev->of_node, 513 "poll-rate-ms", &x)) 514 uap->dmarx.poll_rate = x; 515 else 516 uap->dmarx.poll_rate = 100; 517 if (0 == of_property_read_u32(dev->of_node, 518 "poll-timeout-ms", &x)) 519 uap->dmarx.poll_timeout = x; 520 else 521 uap->dmarx.poll_timeout = 3000; 522 } 523 } 524 dev_info(uap->port.dev, "DMA channel RX %s\n", 525 dma_chan_name(uap->dmarx.chan)); 526 } 527 } 528 529 static void pl011_dma_remove(struct uart_amba_port *uap) 530 { 531 if (uap->dmatx.chan) 532 dma_release_channel(uap->dmatx.chan); 533 if (uap->dmarx.chan) 534 dma_release_channel(uap->dmarx.chan); 535 } 536 537 /* Forward declare these for the refill routine */ 538 static int pl011_dma_tx_refill(struct uart_amba_port *uap); 539 static void pl011_start_tx_pio(struct uart_amba_port *uap); 540 541 /* 542 * The current DMA TX buffer has been sent. 543 * Try to queue up another DMA buffer. 544 */ 545 static void pl011_dma_tx_callback(void *data) 546 { 547 struct uart_amba_port *uap = data; 548 struct pl011_dmatx_data *dmatx = &uap->dmatx; 549 unsigned long flags; 550 u16 dmacr; 551 552 spin_lock_irqsave(&uap->port.lock, flags); 553 if (uap->dmatx.queued) 554 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, 555 DMA_TO_DEVICE); 556 557 dmacr = uap->dmacr; 558 uap->dmacr = dmacr & ~UART011_TXDMAE; 559 pl011_write(uap->dmacr, uap, REG_DMACR); 560 561 /* 562 * If TX DMA was disabled, it means that we've stopped the DMA for 563 * some reason (eg, XOFF received, or we want to send an X-char.) 564 * 565 * Note: we need to be careful here of a potential race between DMA 566 * and the rest of the driver - if the driver disables TX DMA while 567 * a TX buffer completing, we must update the tx queued status to 568 * get further refills (hence we check dmacr). 569 */ 570 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || 571 uart_circ_empty(&uap->port.state->xmit)) { 572 uap->dmatx.queued = false; 573 spin_unlock_irqrestore(&uap->port.lock, flags); 574 return; 575 } 576 577 if (pl011_dma_tx_refill(uap) <= 0) 578 /* 579 * We didn't queue a DMA buffer for some reason, but we 580 * have data pending to be sent. Re-enable the TX IRQ. 581 */ 582 pl011_start_tx_pio(uap); 583 584 spin_unlock_irqrestore(&uap->port.lock, flags); 585 } 586 587 /* 588 * Try to refill the TX DMA buffer. 589 * Locking: called with port lock held and IRQs disabled. 590 * Returns: 591 * 1 if we queued up a TX DMA buffer. 592 * 0 if we didn't want to handle this by DMA 593 * <0 on error 594 */ 595 static int pl011_dma_tx_refill(struct uart_amba_port *uap) 596 { 597 struct pl011_dmatx_data *dmatx = &uap->dmatx; 598 struct dma_chan *chan = dmatx->chan; 599 struct dma_device *dma_dev = chan->device; 600 struct dma_async_tx_descriptor *desc; 601 struct circ_buf *xmit = &uap->port.state->xmit; 602 unsigned int count; 603 604 /* 605 * Try to avoid the overhead involved in using DMA if the 606 * transaction fits in the first half of the FIFO, by using 607 * the standard interrupt handling. This ensures that we 608 * issue a uart_write_wakeup() at the appropriate time. 609 */ 610 count = uart_circ_chars_pending(xmit); 611 if (count < (uap->fifosize >> 1)) { 612 uap->dmatx.queued = false; 613 return 0; 614 } 615 616 /* 617 * Bodge: don't send the last character by DMA, as this 618 * will prevent XON from notifying us to restart DMA. 619 */ 620 count -= 1; 621 622 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ 623 if (count > PL011_DMA_BUFFER_SIZE) 624 count = PL011_DMA_BUFFER_SIZE; 625 626 if (xmit->tail < xmit->head) 627 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); 628 else { 629 size_t first = UART_XMIT_SIZE - xmit->tail; 630 size_t second; 631 632 if (first > count) 633 first = count; 634 second = count - first; 635 636 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); 637 if (second) 638 memcpy(&dmatx->buf[first], &xmit->buf[0], second); 639 } 640 641 dmatx->sg.length = count; 642 643 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { 644 uap->dmatx.queued = false; 645 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); 646 return -EBUSY; 647 } 648 649 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, 650 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 651 if (!desc) { 652 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); 653 uap->dmatx.queued = false; 654 /* 655 * If DMA cannot be used right now, we complete this 656 * transaction via IRQ and let the TTY layer retry. 657 */ 658 dev_dbg(uap->port.dev, "TX DMA busy\n"); 659 return -EBUSY; 660 } 661 662 /* Some data to go along to the callback */ 663 desc->callback = pl011_dma_tx_callback; 664 desc->callback_param = uap; 665 666 /* All errors should happen at prepare time */ 667 dmaengine_submit(desc); 668 669 /* Fire the DMA transaction */ 670 dma_dev->device_issue_pending(chan); 671 672 uap->dmacr |= UART011_TXDMAE; 673 pl011_write(uap->dmacr, uap, REG_DMACR); 674 uap->dmatx.queued = true; 675 676 /* 677 * Now we know that DMA will fire, so advance the ring buffer 678 * with the stuff we just dispatched. 679 */ 680 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 681 uap->port.icount.tx += count; 682 683 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 684 uart_write_wakeup(&uap->port); 685 686 return 1; 687 } 688 689 /* 690 * We received a transmit interrupt without a pending X-char but with 691 * pending characters. 692 * Locking: called with port lock held and IRQs disabled. 693 * Returns: 694 * false if we want to use PIO to transmit 695 * true if we queued a DMA buffer 696 */ 697 static bool pl011_dma_tx_irq(struct uart_amba_port *uap) 698 { 699 if (!uap->using_tx_dma) 700 return false; 701 702 /* 703 * If we already have a TX buffer queued, but received a 704 * TX interrupt, it will be because we've just sent an X-char. 705 * Ensure the TX DMA is enabled and the TX IRQ is disabled. 706 */ 707 if (uap->dmatx.queued) { 708 uap->dmacr |= UART011_TXDMAE; 709 pl011_write(uap->dmacr, uap, REG_DMACR); 710 uap->im &= ~UART011_TXIM; 711 pl011_write(uap->im, uap, REG_IMSC); 712 return true; 713 } 714 715 /* 716 * We don't have a TX buffer queued, so try to queue one. 717 * If we successfully queued a buffer, mask the TX IRQ. 718 */ 719 if (pl011_dma_tx_refill(uap) > 0) { 720 uap->im &= ~UART011_TXIM; 721 pl011_write(uap->im, uap, REG_IMSC); 722 return true; 723 } 724 return false; 725 } 726 727 /* 728 * Stop the DMA transmit (eg, due to received XOFF). 729 * Locking: called with port lock held and IRQs disabled. 730 */ 731 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 732 { 733 if (uap->dmatx.queued) { 734 uap->dmacr &= ~UART011_TXDMAE; 735 pl011_write(uap->dmacr, uap, REG_DMACR); 736 } 737 } 738 739 /* 740 * Try to start a DMA transmit, or in the case of an XON/OFF 741 * character queued for send, try to get that character out ASAP. 742 * Locking: called with port lock held and IRQs disabled. 743 * Returns: 744 * false if we want the TX IRQ to be enabled 745 * true if we have a buffer queued 746 */ 747 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 748 { 749 u16 dmacr; 750 751 if (!uap->using_tx_dma) 752 return false; 753 754 if (!uap->port.x_char) { 755 /* no X-char, try to push chars out in DMA mode */ 756 bool ret = true; 757 758 if (!uap->dmatx.queued) { 759 if (pl011_dma_tx_refill(uap) > 0) { 760 uap->im &= ~UART011_TXIM; 761 pl011_write(uap->im, uap, REG_IMSC); 762 } else 763 ret = false; 764 } else if (!(uap->dmacr & UART011_TXDMAE)) { 765 uap->dmacr |= UART011_TXDMAE; 766 pl011_write(uap->dmacr, uap, REG_DMACR); 767 } 768 return ret; 769 } 770 771 /* 772 * We have an X-char to send. Disable DMA to prevent it loading 773 * the TX fifo, and then see if we can stuff it into the FIFO. 774 */ 775 dmacr = uap->dmacr; 776 uap->dmacr &= ~UART011_TXDMAE; 777 pl011_write(uap->dmacr, uap, REG_DMACR); 778 779 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { 780 /* 781 * No space in the FIFO, so enable the transmit interrupt 782 * so we know when there is space. Note that once we've 783 * loaded the character, we should just re-enable DMA. 784 */ 785 return false; 786 } 787 788 pl011_write(uap->port.x_char, uap, REG_DR); 789 uap->port.icount.tx++; 790 uap->port.x_char = 0; 791 792 /* Success - restore the DMA state */ 793 uap->dmacr = dmacr; 794 pl011_write(dmacr, uap, REG_DMACR); 795 796 return true; 797 } 798 799 /* 800 * Flush the transmit buffer. 801 * Locking: called with port lock held and IRQs disabled. 802 */ 803 static void pl011_dma_flush_buffer(struct uart_port *port) 804 __releases(&uap->port.lock) 805 __acquires(&uap->port.lock) 806 { 807 struct uart_amba_port *uap = 808 container_of(port, struct uart_amba_port, port); 809 810 if (!uap->using_tx_dma) 811 return; 812 813 dmaengine_terminate_async(uap->dmatx.chan); 814 815 if (uap->dmatx.queued) { 816 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 817 DMA_TO_DEVICE); 818 uap->dmatx.queued = false; 819 uap->dmacr &= ~UART011_TXDMAE; 820 pl011_write(uap->dmacr, uap, REG_DMACR); 821 } 822 } 823 824 static void pl011_dma_rx_callback(void *data); 825 826 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 827 { 828 struct dma_chan *rxchan = uap->dmarx.chan; 829 struct pl011_dmarx_data *dmarx = &uap->dmarx; 830 struct dma_async_tx_descriptor *desc; 831 struct pl011_sgbuf *sgbuf; 832 833 if (!rxchan) 834 return -EIO; 835 836 /* Start the RX DMA job */ 837 sgbuf = uap->dmarx.use_buf_b ? 838 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 839 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, 840 DMA_DEV_TO_MEM, 841 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 842 /* 843 * If the DMA engine is busy and cannot prepare a 844 * channel, no big deal, the driver will fall back 845 * to interrupt mode as a result of this error code. 846 */ 847 if (!desc) { 848 uap->dmarx.running = false; 849 dmaengine_terminate_all(rxchan); 850 return -EBUSY; 851 } 852 853 /* Some data to go along to the callback */ 854 desc->callback = pl011_dma_rx_callback; 855 desc->callback_param = uap; 856 dmarx->cookie = dmaengine_submit(desc); 857 dma_async_issue_pending(rxchan); 858 859 uap->dmacr |= UART011_RXDMAE; 860 pl011_write(uap->dmacr, uap, REG_DMACR); 861 uap->dmarx.running = true; 862 863 uap->im &= ~UART011_RXIM; 864 pl011_write(uap->im, uap, REG_IMSC); 865 866 return 0; 867 } 868 869 /* 870 * This is called when either the DMA job is complete, or 871 * the FIFO timeout interrupt occurred. This must be called 872 * with the port spinlock uap->port.lock held. 873 */ 874 static void pl011_dma_rx_chars(struct uart_amba_port *uap, 875 u32 pending, bool use_buf_b, 876 bool readfifo) 877 { 878 struct tty_port *port = &uap->port.state->port; 879 struct pl011_sgbuf *sgbuf = use_buf_b ? 880 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 881 int dma_count = 0; 882 u32 fifotaken = 0; /* only used for vdbg() */ 883 884 struct pl011_dmarx_data *dmarx = &uap->dmarx; 885 int dmataken = 0; 886 887 if (uap->dmarx.poll_rate) { 888 /* The data can be taken by polling */ 889 dmataken = sgbuf->sg.length - dmarx->last_residue; 890 /* Recalculate the pending size */ 891 if (pending >= dmataken) 892 pending -= dmataken; 893 } 894 895 /* Pick the remain data from the DMA */ 896 if (pending) { 897 898 /* 899 * First take all chars in the DMA pipe, then look in the FIFO. 900 * Note that tty_insert_flip_buf() tries to take as many chars 901 * as it can. 902 */ 903 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 904 pending); 905 906 uap->port.icount.rx += dma_count; 907 if (dma_count < pending) 908 dev_warn(uap->port.dev, 909 "couldn't insert all characters (TTY is full?)\n"); 910 } 911 912 /* Reset the last_residue for Rx DMA poll */ 913 if (uap->dmarx.poll_rate) 914 dmarx->last_residue = sgbuf->sg.length; 915 916 /* 917 * Only continue with trying to read the FIFO if all DMA chars have 918 * been taken first. 919 */ 920 if (dma_count == pending && readfifo) { 921 /* Clear any error flags */ 922 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 923 UART011_FEIS, uap, REG_ICR); 924 925 /* 926 * If we read all the DMA'd characters, and we had an 927 * incomplete buffer, that could be due to an rx error, or 928 * maybe we just timed out. Read any pending chars and check 929 * the error status. 930 * 931 * Error conditions will only occur in the FIFO, these will 932 * trigger an immediate interrupt and stop the DMA job, so we 933 * will always find the error in the FIFO, never in the DMA 934 * buffer. 935 */ 936 fifotaken = pl011_fifo_to_tty(uap); 937 } 938 939 dev_vdbg(uap->port.dev, 940 "Took %d chars from DMA buffer and %d chars from the FIFO\n", 941 dma_count, fifotaken); 942 tty_flip_buffer_push(port); 943 } 944 945 static void pl011_dma_rx_irq(struct uart_amba_port *uap) 946 { 947 struct pl011_dmarx_data *dmarx = &uap->dmarx; 948 struct dma_chan *rxchan = dmarx->chan; 949 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 950 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 951 size_t pending; 952 struct dma_tx_state state; 953 enum dma_status dmastat; 954 955 /* 956 * Pause the transfer so we can trust the current counter, 957 * do this before we pause the PL011 block, else we may 958 * overflow the FIFO. 959 */ 960 if (dmaengine_pause(rxchan)) 961 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 962 dmastat = rxchan->device->device_tx_status(rxchan, 963 dmarx->cookie, &state); 964 if (dmastat != DMA_PAUSED) 965 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 966 967 /* Disable RX DMA - incoming data will wait in the FIFO */ 968 uap->dmacr &= ~UART011_RXDMAE; 969 pl011_write(uap->dmacr, uap, REG_DMACR); 970 uap->dmarx.running = false; 971 972 pending = sgbuf->sg.length - state.residue; 973 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 974 /* Then we terminate the transfer - we now know our residue */ 975 dmaengine_terminate_all(rxchan); 976 977 /* 978 * This will take the chars we have so far and insert 979 * into the framework. 980 */ 981 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); 982 983 /* Switch buffer & re-trigger DMA job */ 984 dmarx->use_buf_b = !dmarx->use_buf_b; 985 if (pl011_dma_rx_trigger_dma(uap)) { 986 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 987 "fall back to interrupt mode\n"); 988 uap->im |= UART011_RXIM; 989 pl011_write(uap->im, uap, REG_IMSC); 990 } 991 } 992 993 static void pl011_dma_rx_callback(void *data) 994 { 995 struct uart_amba_port *uap = data; 996 struct pl011_dmarx_data *dmarx = &uap->dmarx; 997 struct dma_chan *rxchan = dmarx->chan; 998 bool lastbuf = dmarx->use_buf_b; 999 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 1000 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 1001 size_t pending; 1002 struct dma_tx_state state; 1003 int ret; 1004 1005 /* 1006 * This completion interrupt occurs typically when the 1007 * RX buffer is totally stuffed but no timeout has yet 1008 * occurred. When that happens, we just want the RX 1009 * routine to flush out the secondary DMA buffer while 1010 * we immediately trigger the next DMA job. 1011 */ 1012 spin_lock_irq(&uap->port.lock); 1013 /* 1014 * Rx data can be taken by the UART interrupts during 1015 * the DMA irq handler. So we check the residue here. 1016 */ 1017 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1018 pending = sgbuf->sg.length - state.residue; 1019 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 1020 /* Then we terminate the transfer - we now know our residue */ 1021 dmaengine_terminate_all(rxchan); 1022 1023 uap->dmarx.running = false; 1024 dmarx->use_buf_b = !lastbuf; 1025 ret = pl011_dma_rx_trigger_dma(uap); 1026 1027 pl011_dma_rx_chars(uap, pending, lastbuf, false); 1028 spin_unlock_irq(&uap->port.lock); 1029 /* 1030 * Do this check after we picked the DMA chars so we don't 1031 * get some IRQ immediately from RX. 1032 */ 1033 if (ret) { 1034 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 1035 "fall back to interrupt mode\n"); 1036 uap->im |= UART011_RXIM; 1037 pl011_write(uap->im, uap, REG_IMSC); 1038 } 1039 } 1040 1041 /* 1042 * Stop accepting received characters, when we're shutting down or 1043 * suspending this port. 1044 * Locking: called with port lock held and IRQs disabled. 1045 */ 1046 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1047 { 1048 /* FIXME. Just disable the DMA enable */ 1049 uap->dmacr &= ~UART011_RXDMAE; 1050 pl011_write(uap->dmacr, uap, REG_DMACR); 1051 } 1052 1053 /* 1054 * Timer handler for Rx DMA polling. 1055 * Every polling, It checks the residue in the dma buffer and transfer 1056 * data to the tty. Also, last_residue is updated for the next polling. 1057 */ 1058 static void pl011_dma_rx_poll(struct timer_list *t) 1059 { 1060 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer); 1061 struct tty_port *port = &uap->port.state->port; 1062 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1063 struct dma_chan *rxchan = uap->dmarx.chan; 1064 unsigned long flags; 1065 unsigned int dmataken = 0; 1066 unsigned int size = 0; 1067 struct pl011_sgbuf *sgbuf; 1068 int dma_count; 1069 struct dma_tx_state state; 1070 1071 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 1072 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1073 if (likely(state.residue < dmarx->last_residue)) { 1074 dmataken = sgbuf->sg.length - dmarx->last_residue; 1075 size = dmarx->last_residue - state.residue; 1076 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 1077 size); 1078 if (dma_count == size) 1079 dmarx->last_residue = state.residue; 1080 dmarx->last_jiffies = jiffies; 1081 } 1082 tty_flip_buffer_push(port); 1083 1084 /* 1085 * If no data is received in poll_timeout, the driver will fall back 1086 * to interrupt mode. We will retrigger DMA at the first interrupt. 1087 */ 1088 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) 1089 > uap->dmarx.poll_timeout) { 1090 1091 spin_lock_irqsave(&uap->port.lock, flags); 1092 pl011_dma_rx_stop(uap); 1093 uap->im |= UART011_RXIM; 1094 pl011_write(uap->im, uap, REG_IMSC); 1095 spin_unlock_irqrestore(&uap->port.lock, flags); 1096 1097 uap->dmarx.running = false; 1098 dmaengine_terminate_all(rxchan); 1099 del_timer(&uap->dmarx.timer); 1100 } else { 1101 mod_timer(&uap->dmarx.timer, 1102 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); 1103 } 1104 } 1105 1106 static void pl011_dma_startup(struct uart_amba_port *uap) 1107 { 1108 int ret; 1109 1110 if (!uap->dma_probed) 1111 pl011_dma_probe(uap); 1112 1113 if (!uap->dmatx.chan) 1114 return; 1115 1116 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); 1117 if (!uap->dmatx.buf) { 1118 dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); 1119 uap->port.fifosize = uap->fifosize; 1120 return; 1121 } 1122 1123 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); 1124 1125 /* The DMA buffer is now the FIFO the TTY subsystem can use */ 1126 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; 1127 uap->using_tx_dma = true; 1128 1129 if (!uap->dmarx.chan) 1130 goto skip_rx; 1131 1132 /* Allocate and map DMA RX buffers */ 1133 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1134 DMA_FROM_DEVICE); 1135 if (ret) { 1136 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1137 "RX buffer A", ret); 1138 goto skip_rx; 1139 } 1140 1141 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, 1142 DMA_FROM_DEVICE); 1143 if (ret) { 1144 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1145 "RX buffer B", ret); 1146 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1147 DMA_FROM_DEVICE); 1148 goto skip_rx; 1149 } 1150 1151 uap->using_rx_dma = true; 1152 1153 skip_rx: 1154 /* Turn on DMA error (RX/TX will be enabled on demand) */ 1155 uap->dmacr |= UART011_DMAONERR; 1156 pl011_write(uap->dmacr, uap, REG_DMACR); 1157 1158 /* 1159 * ST Micro variants has some specific dma burst threshold 1160 * compensation. Set this to 16 bytes, so burst will only 1161 * be issued above/below 16 bytes. 1162 */ 1163 if (uap->vendor->dma_threshold) 1164 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, 1165 uap, REG_ST_DMAWM); 1166 1167 if (uap->using_rx_dma) { 1168 if (pl011_dma_rx_trigger_dma(uap)) 1169 dev_dbg(uap->port.dev, "could not trigger initial " 1170 "RX DMA job, fall back to interrupt mode\n"); 1171 if (uap->dmarx.poll_rate) { 1172 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0); 1173 mod_timer(&uap->dmarx.timer, 1174 jiffies + 1175 msecs_to_jiffies(uap->dmarx.poll_rate)); 1176 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1177 uap->dmarx.last_jiffies = jiffies; 1178 } 1179 } 1180 } 1181 1182 static void pl011_dma_shutdown(struct uart_amba_port *uap) 1183 { 1184 if (!(uap->using_tx_dma || uap->using_rx_dma)) 1185 return; 1186 1187 /* Disable RX and TX DMA */ 1188 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) 1189 cpu_relax(); 1190 1191 spin_lock_irq(&uap->port.lock); 1192 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); 1193 pl011_write(uap->dmacr, uap, REG_DMACR); 1194 spin_unlock_irq(&uap->port.lock); 1195 1196 if (uap->using_tx_dma) { 1197 /* In theory, this should already be done by pl011_dma_flush_buffer */ 1198 dmaengine_terminate_all(uap->dmatx.chan); 1199 if (uap->dmatx.queued) { 1200 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 1201 DMA_TO_DEVICE); 1202 uap->dmatx.queued = false; 1203 } 1204 1205 kfree(uap->dmatx.buf); 1206 uap->using_tx_dma = false; 1207 } 1208 1209 if (uap->using_rx_dma) { 1210 dmaengine_terminate_all(uap->dmarx.chan); 1211 /* Clean up the RX DMA */ 1212 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); 1213 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); 1214 if (uap->dmarx.poll_rate) 1215 del_timer_sync(&uap->dmarx.timer); 1216 uap->using_rx_dma = false; 1217 } 1218 } 1219 1220 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1221 { 1222 return uap->using_rx_dma; 1223 } 1224 1225 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1226 { 1227 return uap->using_rx_dma && uap->dmarx.running; 1228 } 1229 1230 #else 1231 /* Blank functions if the DMA engine is not available */ 1232 static inline void pl011_dma_remove(struct uart_amba_port *uap) 1233 { 1234 } 1235 1236 static inline void pl011_dma_startup(struct uart_amba_port *uap) 1237 { 1238 } 1239 1240 static inline void pl011_dma_shutdown(struct uart_amba_port *uap) 1241 { 1242 } 1243 1244 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) 1245 { 1246 return false; 1247 } 1248 1249 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 1250 { 1251 } 1252 1253 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 1254 { 1255 return false; 1256 } 1257 1258 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) 1259 { 1260 } 1261 1262 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1263 { 1264 } 1265 1266 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 1267 { 1268 return -EIO; 1269 } 1270 1271 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1272 { 1273 return false; 1274 } 1275 1276 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1277 { 1278 return false; 1279 } 1280 1281 #define pl011_dma_flush_buffer NULL 1282 #endif 1283 1284 static void pl011_rs485_tx_stop(struct uart_amba_port *uap) 1285 { 1286 /* 1287 * To be on the safe side only time out after twice as many iterations 1288 * as fifo size. 1289 */ 1290 const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2; 1291 struct uart_port *port = &uap->port; 1292 int i = 0; 1293 u32 cr; 1294 1295 /* Wait until hardware tx queue is empty */ 1296 while (!pl011_tx_empty(port)) { 1297 if (i > MAX_TX_DRAIN_ITERS) { 1298 dev_warn(port->dev, 1299 "timeout while draining hardware tx queue\n"); 1300 break; 1301 } 1302 1303 udelay(uap->rs485_tx_drain_interval); 1304 i++; 1305 } 1306 1307 if (port->rs485.delay_rts_after_send) 1308 mdelay(port->rs485.delay_rts_after_send); 1309 1310 cr = pl011_read(uap, REG_CR); 1311 1312 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 1313 cr &= ~UART011_CR_RTS; 1314 else 1315 cr |= UART011_CR_RTS; 1316 1317 /* Disable the transmitter and reenable the transceiver */ 1318 cr &= ~UART011_CR_TXE; 1319 cr |= UART011_CR_RXE; 1320 pl011_write(cr, uap, REG_CR); 1321 1322 uap->rs485_tx_started = false; 1323 } 1324 1325 static void pl011_stop_tx(struct uart_port *port) 1326 { 1327 struct uart_amba_port *uap = 1328 container_of(port, struct uart_amba_port, port); 1329 1330 uap->im &= ~UART011_TXIM; 1331 pl011_write(uap->im, uap, REG_IMSC); 1332 pl011_dma_tx_stop(uap); 1333 1334 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) 1335 pl011_rs485_tx_stop(uap); 1336 } 1337 1338 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); 1339 1340 /* Start TX with programmed I/O only (no DMA) */ 1341 static void pl011_start_tx_pio(struct uart_amba_port *uap) 1342 { 1343 if (pl011_tx_chars(uap, false)) { 1344 uap->im |= UART011_TXIM; 1345 pl011_write(uap->im, uap, REG_IMSC); 1346 } 1347 } 1348 1349 static void pl011_start_tx(struct uart_port *port) 1350 { 1351 struct uart_amba_port *uap = 1352 container_of(port, struct uart_amba_port, port); 1353 1354 if (!pl011_dma_tx_start(uap)) 1355 pl011_start_tx_pio(uap); 1356 } 1357 1358 static void pl011_stop_rx(struct uart_port *port) 1359 { 1360 struct uart_amba_port *uap = 1361 container_of(port, struct uart_amba_port, port); 1362 1363 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| 1364 UART011_PEIM|UART011_BEIM|UART011_OEIM); 1365 pl011_write(uap->im, uap, REG_IMSC); 1366 1367 pl011_dma_rx_stop(uap); 1368 } 1369 1370 static void pl011_throttle_rx(struct uart_port *port) 1371 { 1372 unsigned long flags; 1373 1374 spin_lock_irqsave(&port->lock, flags); 1375 pl011_stop_rx(port); 1376 spin_unlock_irqrestore(&port->lock, flags); 1377 } 1378 1379 static void pl011_enable_ms(struct uart_port *port) 1380 { 1381 struct uart_amba_port *uap = 1382 container_of(port, struct uart_amba_port, port); 1383 1384 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; 1385 pl011_write(uap->im, uap, REG_IMSC); 1386 } 1387 1388 static void pl011_rx_chars(struct uart_amba_port *uap) 1389 __releases(&uap->port.lock) 1390 __acquires(&uap->port.lock) 1391 { 1392 pl011_fifo_to_tty(uap); 1393 1394 spin_unlock(&uap->port.lock); 1395 tty_flip_buffer_push(&uap->port.state->port); 1396 /* 1397 * If we were temporarily out of DMA mode for a while, 1398 * attempt to switch back to DMA mode again. 1399 */ 1400 if (pl011_dma_rx_available(uap)) { 1401 if (pl011_dma_rx_trigger_dma(uap)) { 1402 dev_dbg(uap->port.dev, "could not trigger RX DMA job " 1403 "fall back to interrupt mode again\n"); 1404 uap->im |= UART011_RXIM; 1405 pl011_write(uap->im, uap, REG_IMSC); 1406 } else { 1407 #ifdef CONFIG_DMA_ENGINE 1408 /* Start Rx DMA poll */ 1409 if (uap->dmarx.poll_rate) { 1410 uap->dmarx.last_jiffies = jiffies; 1411 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1412 mod_timer(&uap->dmarx.timer, 1413 jiffies + 1414 msecs_to_jiffies(uap->dmarx.poll_rate)); 1415 } 1416 #endif 1417 } 1418 } 1419 spin_lock(&uap->port.lock); 1420 } 1421 1422 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, 1423 bool from_irq) 1424 { 1425 if (unlikely(!from_irq) && 1426 pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1427 return false; /* unable to transmit character */ 1428 1429 pl011_write(c, uap, REG_DR); 1430 uap->port.icount.tx++; 1431 1432 return true; 1433 } 1434 1435 static void pl011_rs485_tx_start(struct uart_amba_port *uap) 1436 { 1437 struct uart_port *port = &uap->port; 1438 u32 cr; 1439 1440 /* Enable transmitter */ 1441 cr = pl011_read(uap, REG_CR); 1442 cr |= UART011_CR_TXE; 1443 1444 /* Disable receiver if half-duplex */ 1445 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1446 cr &= ~UART011_CR_RXE; 1447 1448 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 1449 cr &= ~UART011_CR_RTS; 1450 else 1451 cr |= UART011_CR_RTS; 1452 1453 pl011_write(cr, uap, REG_CR); 1454 1455 if (port->rs485.delay_rts_before_send) 1456 mdelay(port->rs485.delay_rts_before_send); 1457 1458 uap->rs485_tx_started = true; 1459 } 1460 1461 /* Returns true if tx interrupts have to be (kept) enabled */ 1462 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) 1463 { 1464 struct circ_buf *xmit = &uap->port.state->xmit; 1465 int count = uap->fifosize >> 1; 1466 1467 if (uap->port.x_char) { 1468 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) 1469 return true; 1470 uap->port.x_char = 0; 1471 --count; 1472 } 1473 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { 1474 pl011_stop_tx(&uap->port); 1475 return false; 1476 } 1477 1478 if ((uap->port.rs485.flags & SER_RS485_ENABLED) && 1479 !uap->rs485_tx_started) 1480 pl011_rs485_tx_start(uap); 1481 1482 /* If we are using DMA mode, try to send some characters. */ 1483 if (pl011_dma_tx_irq(uap)) 1484 return true; 1485 1486 do { 1487 if (likely(from_irq) && count-- == 0) 1488 break; 1489 1490 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) 1491 break; 1492 1493 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1494 } while (!uart_circ_empty(xmit)); 1495 1496 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1497 uart_write_wakeup(&uap->port); 1498 1499 if (uart_circ_empty(xmit)) { 1500 pl011_stop_tx(&uap->port); 1501 return false; 1502 } 1503 return true; 1504 } 1505 1506 static void pl011_modem_status(struct uart_amba_port *uap) 1507 { 1508 unsigned int status, delta; 1509 1510 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1511 1512 delta = status ^ uap->old_status; 1513 uap->old_status = status; 1514 1515 if (!delta) 1516 return; 1517 1518 if (delta & UART01x_FR_DCD) 1519 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 1520 1521 if (delta & uap->vendor->fr_dsr) 1522 uap->port.icount.dsr++; 1523 1524 if (delta & uap->vendor->fr_cts) 1525 uart_handle_cts_change(&uap->port, 1526 status & uap->vendor->fr_cts); 1527 1528 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 1529 } 1530 1531 static void check_apply_cts_event_workaround(struct uart_amba_port *uap) 1532 { 1533 if (!uap->vendor->cts_event_workaround) 1534 return; 1535 1536 /* workaround to make sure that all bits are unlocked.. */ 1537 pl011_write(0x00, uap, REG_ICR); 1538 1539 /* 1540 * WA: introduce 26ns(1 uart clk) delay before W1C; 1541 * single apb access will incur 2 pclk(133.12Mhz) delay, 1542 * so add 2 dummy reads 1543 */ 1544 pl011_read(uap, REG_ICR); 1545 pl011_read(uap, REG_ICR); 1546 } 1547 1548 static irqreturn_t pl011_int(int irq, void *dev_id) 1549 { 1550 struct uart_amba_port *uap = dev_id; 1551 unsigned long flags; 1552 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 1553 int handled = 0; 1554 1555 spin_lock_irqsave(&uap->port.lock, flags); 1556 status = pl011_read(uap, REG_RIS) & uap->im; 1557 if (status) { 1558 do { 1559 check_apply_cts_event_workaround(uap); 1560 1561 pl011_write(status & ~(UART011_TXIS|UART011_RTIS| 1562 UART011_RXIS), 1563 uap, REG_ICR); 1564 1565 if (status & (UART011_RTIS|UART011_RXIS)) { 1566 if (pl011_dma_rx_running(uap)) 1567 pl011_dma_rx_irq(uap); 1568 else 1569 pl011_rx_chars(uap); 1570 } 1571 if (status & (UART011_DSRMIS|UART011_DCDMIS| 1572 UART011_CTSMIS|UART011_RIMIS)) 1573 pl011_modem_status(uap); 1574 if (status & UART011_TXIS) 1575 pl011_tx_chars(uap, true); 1576 1577 if (pass_counter-- == 0) 1578 break; 1579 1580 status = pl011_read(uap, REG_RIS) & uap->im; 1581 } while (status != 0); 1582 handled = 1; 1583 } 1584 1585 spin_unlock_irqrestore(&uap->port.lock, flags); 1586 1587 return IRQ_RETVAL(handled); 1588 } 1589 1590 static unsigned int pl011_tx_empty(struct uart_port *port) 1591 { 1592 struct uart_amba_port *uap = 1593 container_of(port, struct uart_amba_port, port); 1594 1595 /* Allow feature register bits to be inverted to work around errata */ 1596 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; 1597 1598 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? 1599 0 : TIOCSER_TEMT; 1600 } 1601 1602 static unsigned int pl011_get_mctrl(struct uart_port *port) 1603 { 1604 struct uart_amba_port *uap = 1605 container_of(port, struct uart_amba_port, port); 1606 unsigned int result = 0; 1607 unsigned int status = pl011_read(uap, REG_FR); 1608 1609 #define TIOCMBIT(uartbit, tiocmbit) \ 1610 if (status & uartbit) \ 1611 result |= tiocmbit 1612 1613 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); 1614 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR); 1615 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS); 1616 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG); 1617 #undef TIOCMBIT 1618 return result; 1619 } 1620 1621 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) 1622 { 1623 struct uart_amba_port *uap = 1624 container_of(port, struct uart_amba_port, port); 1625 unsigned int cr; 1626 1627 cr = pl011_read(uap, REG_CR); 1628 1629 #define TIOCMBIT(tiocmbit, uartbit) \ 1630 if (mctrl & tiocmbit) \ 1631 cr |= uartbit; \ 1632 else \ 1633 cr &= ~uartbit 1634 1635 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); 1636 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); 1637 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); 1638 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); 1639 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); 1640 1641 if (port->status & UPSTAT_AUTORTS) { 1642 /* We need to disable auto-RTS if we want to turn RTS off */ 1643 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); 1644 } 1645 #undef TIOCMBIT 1646 1647 pl011_write(cr, uap, REG_CR); 1648 } 1649 1650 static void pl011_break_ctl(struct uart_port *port, int break_state) 1651 { 1652 struct uart_amba_port *uap = 1653 container_of(port, struct uart_amba_port, port); 1654 unsigned long flags; 1655 unsigned int lcr_h; 1656 1657 spin_lock_irqsave(&uap->port.lock, flags); 1658 lcr_h = pl011_read(uap, REG_LCRH_TX); 1659 if (break_state == -1) 1660 lcr_h |= UART01x_LCRH_BRK; 1661 else 1662 lcr_h &= ~UART01x_LCRH_BRK; 1663 pl011_write(lcr_h, uap, REG_LCRH_TX); 1664 spin_unlock_irqrestore(&uap->port.lock, flags); 1665 } 1666 1667 #ifdef CONFIG_CONSOLE_POLL 1668 1669 static void pl011_quiesce_irqs(struct uart_port *port) 1670 { 1671 struct uart_amba_port *uap = 1672 container_of(port, struct uart_amba_port, port); 1673 1674 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); 1675 /* 1676 * There is no way to clear TXIM as this is "ready to transmit IRQ", so 1677 * we simply mask it. start_tx() will unmask it. 1678 * 1679 * Note we can race with start_tx(), and if the race happens, the 1680 * polling user might get another interrupt just after we clear it. 1681 * But it should be OK and can happen even w/o the race, e.g. 1682 * controller immediately got some new data and raised the IRQ. 1683 * 1684 * And whoever uses polling routines assumes that it manages the device 1685 * (including tx queue), so we're also fine with start_tx()'s caller 1686 * side. 1687 */ 1688 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, 1689 REG_IMSC); 1690 } 1691 1692 static int pl011_get_poll_char(struct uart_port *port) 1693 { 1694 struct uart_amba_port *uap = 1695 container_of(port, struct uart_amba_port, port); 1696 unsigned int status; 1697 1698 /* 1699 * The caller might need IRQs lowered, e.g. if used with KDB NMI 1700 * debugger. 1701 */ 1702 pl011_quiesce_irqs(port); 1703 1704 status = pl011_read(uap, REG_FR); 1705 if (status & UART01x_FR_RXFE) 1706 return NO_POLL_CHAR; 1707 1708 return pl011_read(uap, REG_DR); 1709 } 1710 1711 static void pl011_put_poll_char(struct uart_port *port, 1712 unsigned char ch) 1713 { 1714 struct uart_amba_port *uap = 1715 container_of(port, struct uart_amba_port, port); 1716 1717 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1718 cpu_relax(); 1719 1720 pl011_write(ch, uap, REG_DR); 1721 } 1722 1723 #endif /* CONFIG_CONSOLE_POLL */ 1724 1725 static int pl011_hwinit(struct uart_port *port) 1726 { 1727 struct uart_amba_port *uap = 1728 container_of(port, struct uart_amba_port, port); 1729 int retval; 1730 1731 /* Optionaly enable pins to be muxed in and configured */ 1732 pinctrl_pm_select_default_state(port->dev); 1733 1734 /* 1735 * Try to enable the clock producer. 1736 */ 1737 retval = clk_prepare_enable(uap->clk); 1738 if (retval) 1739 return retval; 1740 1741 uap->port.uartclk = clk_get_rate(uap->clk); 1742 1743 /* Clear pending error and receive interrupts */ 1744 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 1745 UART011_FEIS | UART011_RTIS | UART011_RXIS, 1746 uap, REG_ICR); 1747 1748 /* 1749 * Save interrupts enable mask, and enable RX interrupts in case if 1750 * the interrupt is used for NMI entry. 1751 */ 1752 uap->im = pl011_read(uap, REG_IMSC); 1753 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); 1754 1755 if (dev_get_platdata(uap->port.dev)) { 1756 struct amba_pl011_data *plat; 1757 1758 plat = dev_get_platdata(uap->port.dev); 1759 if (plat->init) 1760 plat->init(); 1761 } 1762 return 0; 1763 } 1764 1765 static bool pl011_split_lcrh(const struct uart_amba_port *uap) 1766 { 1767 return pl011_reg_to_offset(uap, REG_LCRH_RX) != 1768 pl011_reg_to_offset(uap, REG_LCRH_TX); 1769 } 1770 1771 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) 1772 { 1773 pl011_write(lcr_h, uap, REG_LCRH_RX); 1774 if (pl011_split_lcrh(uap)) { 1775 int i; 1776 /* 1777 * Wait 10 PCLKs before writing LCRH_TX register, 1778 * to get this delay write read only register 10 times 1779 */ 1780 for (i = 0; i < 10; ++i) 1781 pl011_write(0xff, uap, REG_MIS); 1782 pl011_write(lcr_h, uap, REG_LCRH_TX); 1783 } 1784 } 1785 1786 static int pl011_allocate_irq(struct uart_amba_port *uap) 1787 { 1788 pl011_write(uap->im, uap, REG_IMSC); 1789 1790 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); 1791 } 1792 1793 /* 1794 * Enable interrupts, only timeouts when using DMA 1795 * if initial RX DMA job failed, start in interrupt mode 1796 * as well. 1797 */ 1798 static void pl011_enable_interrupts(struct uart_amba_port *uap) 1799 { 1800 unsigned long flags; 1801 unsigned int i; 1802 1803 spin_lock_irqsave(&uap->port.lock, flags); 1804 1805 /* Clear out any spuriously appearing RX interrupts */ 1806 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); 1807 1808 /* 1809 * RXIS is asserted only when the RX FIFO transitions from below 1810 * to above the trigger threshold. If the RX FIFO is already 1811 * full to the threshold this can't happen and RXIS will now be 1812 * stuck off. Drain the RX FIFO explicitly to fix this: 1813 */ 1814 for (i = 0; i < uap->fifosize * 2; ++i) { 1815 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE) 1816 break; 1817 1818 pl011_read(uap, REG_DR); 1819 } 1820 1821 uap->im = UART011_RTIM; 1822 if (!pl011_dma_rx_running(uap)) 1823 uap->im |= UART011_RXIM; 1824 pl011_write(uap->im, uap, REG_IMSC); 1825 spin_unlock_irqrestore(&uap->port.lock, flags); 1826 } 1827 1828 static void pl011_unthrottle_rx(struct uart_port *port) 1829 { 1830 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port); 1831 1832 pl011_enable_interrupts(uap); 1833 } 1834 1835 static int pl011_startup(struct uart_port *port) 1836 { 1837 struct uart_amba_port *uap = 1838 container_of(port, struct uart_amba_port, port); 1839 unsigned int cr; 1840 int retval; 1841 1842 retval = pl011_hwinit(port); 1843 if (retval) 1844 goto clk_dis; 1845 1846 retval = pl011_allocate_irq(uap); 1847 if (retval) 1848 goto clk_dis; 1849 1850 pl011_write(uap->vendor->ifls, uap, REG_IFLS); 1851 1852 spin_lock_irq(&uap->port.lock); 1853 1854 cr = pl011_read(uap, REG_CR); 1855 cr &= UART011_CR_RTS | UART011_CR_DTR; 1856 cr |= UART01x_CR_UARTEN | UART011_CR_RXE; 1857 1858 if (!(port->rs485.flags & SER_RS485_ENABLED)) 1859 cr |= UART011_CR_TXE; 1860 1861 pl011_write(cr, uap, REG_CR); 1862 1863 spin_unlock_irq(&uap->port.lock); 1864 1865 /* 1866 * initialise the old status of the modem signals 1867 */ 1868 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1869 1870 /* Startup DMA */ 1871 pl011_dma_startup(uap); 1872 1873 pl011_enable_interrupts(uap); 1874 1875 return 0; 1876 1877 clk_dis: 1878 clk_disable_unprepare(uap->clk); 1879 return retval; 1880 } 1881 1882 static int sbsa_uart_startup(struct uart_port *port) 1883 { 1884 struct uart_amba_port *uap = 1885 container_of(port, struct uart_amba_port, port); 1886 int retval; 1887 1888 retval = pl011_hwinit(port); 1889 if (retval) 1890 return retval; 1891 1892 retval = pl011_allocate_irq(uap); 1893 if (retval) 1894 return retval; 1895 1896 /* The SBSA UART does not support any modem status lines. */ 1897 uap->old_status = 0; 1898 1899 pl011_enable_interrupts(uap); 1900 1901 return 0; 1902 } 1903 1904 static void pl011_shutdown_channel(struct uart_amba_port *uap, 1905 unsigned int lcrh) 1906 { 1907 unsigned long val; 1908 1909 val = pl011_read(uap, lcrh); 1910 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); 1911 pl011_write(val, uap, lcrh); 1912 } 1913 1914 /* 1915 * disable the port. It should not disable RTS and DTR. 1916 * Also RTS and DTR state should be preserved to restore 1917 * it during startup(). 1918 */ 1919 static void pl011_disable_uart(struct uart_amba_port *uap) 1920 { 1921 unsigned int cr; 1922 1923 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1924 spin_lock_irq(&uap->port.lock); 1925 cr = pl011_read(uap, REG_CR); 1926 cr &= UART011_CR_RTS | UART011_CR_DTR; 1927 cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 1928 pl011_write(cr, uap, REG_CR); 1929 spin_unlock_irq(&uap->port.lock); 1930 1931 /* 1932 * disable break condition and fifos 1933 */ 1934 pl011_shutdown_channel(uap, REG_LCRH_RX); 1935 if (pl011_split_lcrh(uap)) 1936 pl011_shutdown_channel(uap, REG_LCRH_TX); 1937 } 1938 1939 static void pl011_disable_interrupts(struct uart_amba_port *uap) 1940 { 1941 spin_lock_irq(&uap->port.lock); 1942 1943 /* mask all interrupts and clear all pending ones */ 1944 uap->im = 0; 1945 pl011_write(uap->im, uap, REG_IMSC); 1946 pl011_write(0xffff, uap, REG_ICR); 1947 1948 spin_unlock_irq(&uap->port.lock); 1949 } 1950 1951 static void pl011_shutdown(struct uart_port *port) 1952 { 1953 struct uart_amba_port *uap = 1954 container_of(port, struct uart_amba_port, port); 1955 1956 pl011_disable_interrupts(uap); 1957 1958 pl011_dma_shutdown(uap); 1959 1960 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) 1961 pl011_rs485_tx_stop(uap); 1962 1963 free_irq(uap->port.irq, uap); 1964 1965 pl011_disable_uart(uap); 1966 1967 /* 1968 * Shut down the clock producer 1969 */ 1970 clk_disable_unprepare(uap->clk); 1971 /* Optionally let pins go into sleep states */ 1972 pinctrl_pm_select_sleep_state(port->dev); 1973 1974 if (dev_get_platdata(uap->port.dev)) { 1975 struct amba_pl011_data *plat; 1976 1977 plat = dev_get_platdata(uap->port.dev); 1978 if (plat->exit) 1979 plat->exit(); 1980 } 1981 1982 if (uap->port.ops->flush_buffer) 1983 uap->port.ops->flush_buffer(port); 1984 } 1985 1986 static void sbsa_uart_shutdown(struct uart_port *port) 1987 { 1988 struct uart_amba_port *uap = 1989 container_of(port, struct uart_amba_port, port); 1990 1991 pl011_disable_interrupts(uap); 1992 1993 free_irq(uap->port.irq, uap); 1994 1995 if (uap->port.ops->flush_buffer) 1996 uap->port.ops->flush_buffer(port); 1997 } 1998 1999 static void 2000 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) 2001 { 2002 port->read_status_mask = UART011_DR_OE | 255; 2003 if (termios->c_iflag & INPCK) 2004 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; 2005 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2006 port->read_status_mask |= UART011_DR_BE; 2007 2008 /* 2009 * Characters to ignore 2010 */ 2011 port->ignore_status_mask = 0; 2012 if (termios->c_iflag & IGNPAR) 2013 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; 2014 if (termios->c_iflag & IGNBRK) { 2015 port->ignore_status_mask |= UART011_DR_BE; 2016 /* 2017 * If we're ignoring parity and break indicators, 2018 * ignore overruns too (for real raw support). 2019 */ 2020 if (termios->c_iflag & IGNPAR) 2021 port->ignore_status_mask |= UART011_DR_OE; 2022 } 2023 2024 /* 2025 * Ignore all characters if CREAD is not set. 2026 */ 2027 if ((termios->c_cflag & CREAD) == 0) 2028 port->ignore_status_mask |= UART_DUMMY_DR_RX; 2029 } 2030 2031 static void 2032 pl011_set_termios(struct uart_port *port, struct ktermios *termios, 2033 struct ktermios *old) 2034 { 2035 struct uart_amba_port *uap = 2036 container_of(port, struct uart_amba_port, port); 2037 unsigned int lcr_h, old_cr; 2038 unsigned long flags; 2039 unsigned int baud, quot, clkdiv; 2040 unsigned int bits; 2041 2042 if (uap->vendor->oversampling) 2043 clkdiv = 8; 2044 else 2045 clkdiv = 16; 2046 2047 /* 2048 * Ask the core to calculate the divisor for us. 2049 */ 2050 baud = uart_get_baud_rate(port, termios, old, 0, 2051 port->uartclk / clkdiv); 2052 #ifdef CONFIG_DMA_ENGINE 2053 /* 2054 * Adjust RX DMA polling rate with baud rate if not specified. 2055 */ 2056 if (uap->dmarx.auto_poll_rate) 2057 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); 2058 #endif 2059 2060 if (baud > port->uartclk/16) 2061 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); 2062 else 2063 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); 2064 2065 switch (termios->c_cflag & CSIZE) { 2066 case CS5: 2067 lcr_h = UART01x_LCRH_WLEN_5; 2068 break; 2069 case CS6: 2070 lcr_h = UART01x_LCRH_WLEN_6; 2071 break; 2072 case CS7: 2073 lcr_h = UART01x_LCRH_WLEN_7; 2074 break; 2075 default: // CS8 2076 lcr_h = UART01x_LCRH_WLEN_8; 2077 break; 2078 } 2079 if (termios->c_cflag & CSTOPB) 2080 lcr_h |= UART01x_LCRH_STP2; 2081 if (termios->c_cflag & PARENB) { 2082 lcr_h |= UART01x_LCRH_PEN; 2083 if (!(termios->c_cflag & PARODD)) 2084 lcr_h |= UART01x_LCRH_EPS; 2085 if (termios->c_cflag & CMSPAR) 2086 lcr_h |= UART011_LCRH_SPS; 2087 } 2088 if (uap->fifosize > 1) 2089 lcr_h |= UART01x_LCRH_FEN; 2090 2091 bits = tty_get_frame_size(termios->c_cflag); 2092 2093 spin_lock_irqsave(&port->lock, flags); 2094 2095 /* 2096 * Update the per-port timeout. 2097 */ 2098 uart_update_timeout(port, termios->c_cflag, baud); 2099 2100 /* 2101 * Calculate the approximated time it takes to transmit one character 2102 * with the given baud rate. We use this as the poll interval when we 2103 * wait for the tx queue to empty. 2104 */ 2105 uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud); 2106 2107 pl011_setup_status_masks(port, termios); 2108 2109 if (UART_ENABLE_MS(port, termios->c_cflag)) 2110 pl011_enable_ms(port); 2111 2112 if (port->rs485.flags & SER_RS485_ENABLED) 2113 termios->c_cflag &= ~CRTSCTS; 2114 2115 old_cr = pl011_read(uap, REG_CR); 2116 2117 if (termios->c_cflag & CRTSCTS) { 2118 if (old_cr & UART011_CR_RTS) 2119 old_cr |= UART011_CR_RTSEN; 2120 2121 old_cr |= UART011_CR_CTSEN; 2122 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 2123 } else { 2124 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); 2125 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 2126 } 2127 2128 if (uap->vendor->oversampling) { 2129 if (baud > port->uartclk / 16) 2130 old_cr |= ST_UART011_CR_OVSFACT; 2131 else 2132 old_cr &= ~ST_UART011_CR_OVSFACT; 2133 } 2134 2135 /* 2136 * Workaround for the ST Micro oversampling variants to 2137 * increase the bitrate slightly, by lowering the divisor, 2138 * to avoid delayed sampling of start bit at high speeds, 2139 * else we see data corruption. 2140 */ 2141 if (uap->vendor->oversampling) { 2142 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) 2143 quot -= 1; 2144 else if ((baud > 3250000) && (quot > 2)) 2145 quot -= 2; 2146 } 2147 /* Set baud rate */ 2148 pl011_write(quot & 0x3f, uap, REG_FBRD); 2149 pl011_write(quot >> 6, uap, REG_IBRD); 2150 2151 /* 2152 * ----------v----------v----------v----------v----- 2153 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER 2154 * REG_FBRD & REG_IBRD. 2155 * ----------^----------^----------^----------^----- 2156 */ 2157 pl011_write_lcr_h(uap, lcr_h); 2158 pl011_write(old_cr, uap, REG_CR); 2159 2160 spin_unlock_irqrestore(&port->lock, flags); 2161 } 2162 2163 static void 2164 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, 2165 struct ktermios *old) 2166 { 2167 struct uart_amba_port *uap = 2168 container_of(port, struct uart_amba_port, port); 2169 unsigned long flags; 2170 2171 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); 2172 2173 /* The SBSA UART only supports 8n1 without hardware flow control. */ 2174 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 2175 termios->c_cflag &= ~(CMSPAR | CRTSCTS); 2176 termios->c_cflag |= CS8 | CLOCAL; 2177 2178 spin_lock_irqsave(&port->lock, flags); 2179 uart_update_timeout(port, CS8, uap->fixed_baud); 2180 pl011_setup_status_masks(port, termios); 2181 spin_unlock_irqrestore(&port->lock, flags); 2182 } 2183 2184 static const char *pl011_type(struct uart_port *port) 2185 { 2186 struct uart_amba_port *uap = 2187 container_of(port, struct uart_amba_port, port); 2188 return uap->port.type == PORT_AMBA ? uap->type : NULL; 2189 } 2190 2191 /* 2192 * Configure/autoconfigure the port. 2193 */ 2194 static void pl011_config_port(struct uart_port *port, int flags) 2195 { 2196 if (flags & UART_CONFIG_TYPE) 2197 port->type = PORT_AMBA; 2198 } 2199 2200 /* 2201 * verify the new serial_struct (for TIOCSSERIAL). 2202 */ 2203 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) 2204 { 2205 int ret = 0; 2206 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 2207 ret = -EINVAL; 2208 if (ser->irq < 0 || ser->irq >= nr_irqs) 2209 ret = -EINVAL; 2210 if (ser->baud_base < 9600) 2211 ret = -EINVAL; 2212 if (port->mapbase != (unsigned long) ser->iomem_base) 2213 ret = -EINVAL; 2214 return ret; 2215 } 2216 2217 static int pl011_rs485_config(struct uart_port *port, 2218 struct serial_rs485 *rs485) 2219 { 2220 struct uart_amba_port *uap = 2221 container_of(port, struct uart_amba_port, port); 2222 2223 if (port->rs485.flags & SER_RS485_ENABLED) 2224 pl011_rs485_tx_stop(uap); 2225 2226 /* Make sure auto RTS is disabled */ 2227 if (rs485->flags & SER_RS485_ENABLED) { 2228 u32 cr = pl011_read(uap, REG_CR); 2229 2230 cr &= ~UART011_CR_RTSEN; 2231 pl011_write(cr, uap, REG_CR); 2232 port->status &= ~UPSTAT_AUTORTS; 2233 } 2234 2235 return 0; 2236 } 2237 2238 static const struct uart_ops amba_pl011_pops = { 2239 .tx_empty = pl011_tx_empty, 2240 .set_mctrl = pl011_set_mctrl, 2241 .get_mctrl = pl011_get_mctrl, 2242 .stop_tx = pl011_stop_tx, 2243 .start_tx = pl011_start_tx, 2244 .stop_rx = pl011_stop_rx, 2245 .throttle = pl011_throttle_rx, 2246 .unthrottle = pl011_unthrottle_rx, 2247 .enable_ms = pl011_enable_ms, 2248 .break_ctl = pl011_break_ctl, 2249 .startup = pl011_startup, 2250 .shutdown = pl011_shutdown, 2251 .flush_buffer = pl011_dma_flush_buffer, 2252 .set_termios = pl011_set_termios, 2253 .type = pl011_type, 2254 .config_port = pl011_config_port, 2255 .verify_port = pl011_verify_port, 2256 #ifdef CONFIG_CONSOLE_POLL 2257 .poll_init = pl011_hwinit, 2258 .poll_get_char = pl011_get_poll_char, 2259 .poll_put_char = pl011_put_poll_char, 2260 #endif 2261 }; 2262 2263 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 2264 { 2265 } 2266 2267 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) 2268 { 2269 return 0; 2270 } 2271 2272 static const struct uart_ops sbsa_uart_pops = { 2273 .tx_empty = pl011_tx_empty, 2274 .set_mctrl = sbsa_uart_set_mctrl, 2275 .get_mctrl = sbsa_uart_get_mctrl, 2276 .stop_tx = pl011_stop_tx, 2277 .start_tx = pl011_start_tx, 2278 .stop_rx = pl011_stop_rx, 2279 .startup = sbsa_uart_startup, 2280 .shutdown = sbsa_uart_shutdown, 2281 .set_termios = sbsa_uart_set_termios, 2282 .type = pl011_type, 2283 .config_port = pl011_config_port, 2284 .verify_port = pl011_verify_port, 2285 #ifdef CONFIG_CONSOLE_POLL 2286 .poll_init = pl011_hwinit, 2287 .poll_get_char = pl011_get_poll_char, 2288 .poll_put_char = pl011_put_poll_char, 2289 #endif 2290 }; 2291 2292 static struct uart_amba_port *amba_ports[UART_NR]; 2293 2294 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE 2295 2296 static void pl011_console_putchar(struct uart_port *port, unsigned char ch) 2297 { 2298 struct uart_amba_port *uap = 2299 container_of(port, struct uart_amba_port, port); 2300 2301 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 2302 cpu_relax(); 2303 pl011_write(ch, uap, REG_DR); 2304 } 2305 2306 static void 2307 pl011_console_write(struct console *co, const char *s, unsigned int count) 2308 { 2309 struct uart_amba_port *uap = amba_ports[co->index]; 2310 unsigned int old_cr = 0, new_cr; 2311 unsigned long flags; 2312 int locked = 1; 2313 2314 clk_enable(uap->clk); 2315 2316 local_irq_save(flags); 2317 if (uap->port.sysrq) 2318 locked = 0; 2319 else if (oops_in_progress) 2320 locked = spin_trylock(&uap->port.lock); 2321 else 2322 spin_lock(&uap->port.lock); 2323 2324 /* 2325 * First save the CR then disable the interrupts 2326 */ 2327 if (!uap->vendor->always_enabled) { 2328 old_cr = pl011_read(uap, REG_CR); 2329 new_cr = old_cr & ~UART011_CR_CTSEN; 2330 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 2331 pl011_write(new_cr, uap, REG_CR); 2332 } 2333 2334 uart_console_write(&uap->port, s, count, pl011_console_putchar); 2335 2336 /* 2337 * Finally, wait for transmitter to become empty and restore the 2338 * TCR. Allow feature register bits to be inverted to work around 2339 * errata. 2340 */ 2341 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) 2342 & uap->vendor->fr_busy) 2343 cpu_relax(); 2344 if (!uap->vendor->always_enabled) 2345 pl011_write(old_cr, uap, REG_CR); 2346 2347 if (locked) 2348 spin_unlock(&uap->port.lock); 2349 local_irq_restore(flags); 2350 2351 clk_disable(uap->clk); 2352 } 2353 2354 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud, 2355 int *parity, int *bits) 2356 { 2357 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) { 2358 unsigned int lcr_h, ibrd, fbrd; 2359 2360 lcr_h = pl011_read(uap, REG_LCRH_TX); 2361 2362 *parity = 'n'; 2363 if (lcr_h & UART01x_LCRH_PEN) { 2364 if (lcr_h & UART01x_LCRH_EPS) 2365 *parity = 'e'; 2366 else 2367 *parity = 'o'; 2368 } 2369 2370 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 2371 *bits = 7; 2372 else 2373 *bits = 8; 2374 2375 ibrd = pl011_read(uap, REG_IBRD); 2376 fbrd = pl011_read(uap, REG_FBRD); 2377 2378 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); 2379 2380 if (uap->vendor->oversampling) { 2381 if (pl011_read(uap, REG_CR) 2382 & ST_UART011_CR_OVSFACT) 2383 *baud *= 2; 2384 } 2385 } 2386 } 2387 2388 static int pl011_console_setup(struct console *co, char *options) 2389 { 2390 struct uart_amba_port *uap; 2391 int baud = 38400; 2392 int bits = 8; 2393 int parity = 'n'; 2394 int flow = 'n'; 2395 int ret; 2396 2397 /* 2398 * Check whether an invalid uart number has been specified, and 2399 * if so, search for the first available port that does have 2400 * console support. 2401 */ 2402 if (co->index >= UART_NR) 2403 co->index = 0; 2404 uap = amba_ports[co->index]; 2405 if (!uap) 2406 return -ENODEV; 2407 2408 /* Allow pins to be muxed in and configured */ 2409 pinctrl_pm_select_default_state(uap->port.dev); 2410 2411 ret = clk_prepare(uap->clk); 2412 if (ret) 2413 return ret; 2414 2415 if (dev_get_platdata(uap->port.dev)) { 2416 struct amba_pl011_data *plat; 2417 2418 plat = dev_get_platdata(uap->port.dev); 2419 if (plat->init) 2420 plat->init(); 2421 } 2422 2423 uap->port.uartclk = clk_get_rate(uap->clk); 2424 2425 if (uap->vendor->fixed_options) { 2426 baud = uap->fixed_baud; 2427 } else { 2428 if (options) 2429 uart_parse_options(options, 2430 &baud, &parity, &bits, &flow); 2431 else 2432 pl011_console_get_options(uap, &baud, &parity, &bits); 2433 } 2434 2435 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 2436 } 2437 2438 /** 2439 * pl011_console_match - non-standard console matching 2440 * @co: registering console 2441 * @name: name from console command line 2442 * @idx: index from console command line 2443 * @options: ptr to option string from console command line 2444 * 2445 * Only attempts to match console command lines of the form: 2446 * console=pl011,mmio|mmio32,<addr>[,<options>] 2447 * console=pl011,0x<addr>[,<options>] 2448 * This form is used to register an initial earlycon boot console and 2449 * replace it with the amba_console at pl011 driver init. 2450 * 2451 * Performs console setup for a match (as required by interface) 2452 * If no <options> are specified, then assume the h/w is already setup. 2453 * 2454 * Returns 0 if console matches; otherwise non-zero to use default matching 2455 */ 2456 static int pl011_console_match(struct console *co, char *name, int idx, 2457 char *options) 2458 { 2459 unsigned char iotype; 2460 resource_size_t addr; 2461 int i; 2462 2463 /* 2464 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum 2465 * have a distinct console name, so make sure we check for that. 2466 * The actual implementation of the erratum occurs in the probe 2467 * function. 2468 */ 2469 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0)) 2470 return -ENODEV; 2471 2472 if (uart_parse_earlycon(options, &iotype, &addr, &options)) 2473 return -ENODEV; 2474 2475 if (iotype != UPIO_MEM && iotype != UPIO_MEM32) 2476 return -ENODEV; 2477 2478 /* try to match the port specified on the command line */ 2479 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2480 struct uart_port *port; 2481 2482 if (!amba_ports[i]) 2483 continue; 2484 2485 port = &amba_ports[i]->port; 2486 2487 if (port->mapbase != addr) 2488 continue; 2489 2490 co->index = i; 2491 port->cons = co; 2492 return pl011_console_setup(co, options); 2493 } 2494 2495 return -ENODEV; 2496 } 2497 2498 static struct uart_driver amba_reg; 2499 static struct console amba_console = { 2500 .name = "ttyAMA", 2501 .write = pl011_console_write, 2502 .device = uart_console_device, 2503 .setup = pl011_console_setup, 2504 .match = pl011_console_match, 2505 .flags = CON_PRINTBUFFER | CON_ANYTIME, 2506 .index = -1, 2507 .data = &amba_reg, 2508 }; 2509 2510 #define AMBA_CONSOLE (&amba_console) 2511 2512 static void qdf2400_e44_putc(struct uart_port *port, unsigned char c) 2513 { 2514 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2515 cpu_relax(); 2516 writel(c, port->membase + UART01x_DR); 2517 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) 2518 cpu_relax(); 2519 } 2520 2521 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n) 2522 { 2523 struct earlycon_device *dev = con->data; 2524 2525 uart_console_write(&dev->port, s, n, qdf2400_e44_putc); 2526 } 2527 2528 static void pl011_putc(struct uart_port *port, unsigned char c) 2529 { 2530 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2531 cpu_relax(); 2532 if (port->iotype == UPIO_MEM32) 2533 writel(c, port->membase + UART01x_DR); 2534 else 2535 writeb(c, port->membase + UART01x_DR); 2536 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) 2537 cpu_relax(); 2538 } 2539 2540 static void pl011_early_write(struct console *con, const char *s, unsigned n) 2541 { 2542 struct earlycon_device *dev = con->data; 2543 2544 uart_console_write(&dev->port, s, n, pl011_putc); 2545 } 2546 2547 #ifdef CONFIG_CONSOLE_POLL 2548 static int pl011_getc(struct uart_port *port) 2549 { 2550 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE) 2551 return NO_POLL_CHAR; 2552 2553 if (port->iotype == UPIO_MEM32) 2554 return readl(port->membase + UART01x_DR); 2555 else 2556 return readb(port->membase + UART01x_DR); 2557 } 2558 2559 static int pl011_early_read(struct console *con, char *s, unsigned int n) 2560 { 2561 struct earlycon_device *dev = con->data; 2562 int ch, num_read = 0; 2563 2564 while (num_read < n) { 2565 ch = pl011_getc(&dev->port); 2566 if (ch == NO_POLL_CHAR) 2567 break; 2568 2569 s[num_read++] = ch; 2570 } 2571 2572 return num_read; 2573 } 2574 #else 2575 #define pl011_early_read NULL 2576 #endif 2577 2578 /* 2579 * On non-ACPI systems, earlycon is enabled by specifying 2580 * "earlycon=pl011,<address>" on the kernel command line. 2581 * 2582 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table, 2583 * by specifying only "earlycon" on the command line. Because it requires 2584 * SPCR, the console starts after ACPI is parsed, which is later than a 2585 * traditional early console. 2586 * 2587 * To get the traditional early console that starts before ACPI is parsed, 2588 * specify the full "earlycon=pl011,<address>" option. 2589 */ 2590 static int __init pl011_early_console_setup(struct earlycon_device *device, 2591 const char *opt) 2592 { 2593 if (!device->port.membase) 2594 return -ENODEV; 2595 2596 device->con->write = pl011_early_write; 2597 device->con->read = pl011_early_read; 2598 2599 return 0; 2600 } 2601 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); 2602 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup); 2603 2604 /* 2605 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by 2606 * Erratum 44, traditional earlycon can be enabled by specifying 2607 * "earlycon=qdf2400_e44,<address>". Any options are ignored. 2608 * 2609 * Alternatively, you can just specify "earlycon", and the early console 2610 * will be enabled with the information from the SPCR table. In this 2611 * case, the SPCR code will detect the need for the E44 work-around, 2612 * and set the console name to "qdf2400_e44". 2613 */ 2614 static int __init 2615 qdf2400_e44_early_console_setup(struct earlycon_device *device, 2616 const char *opt) 2617 { 2618 if (!device->port.membase) 2619 return -ENODEV; 2620 2621 device->con->write = qdf2400_e44_early_write; 2622 return 0; 2623 } 2624 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup); 2625 2626 #else 2627 #define AMBA_CONSOLE NULL 2628 #endif 2629 2630 static struct uart_driver amba_reg = { 2631 .owner = THIS_MODULE, 2632 .driver_name = "ttyAMA", 2633 .dev_name = "ttyAMA", 2634 .major = SERIAL_AMBA_MAJOR, 2635 .minor = SERIAL_AMBA_MINOR, 2636 .nr = UART_NR, 2637 .cons = AMBA_CONSOLE, 2638 }; 2639 2640 static int pl011_probe_dt_alias(int index, struct device *dev) 2641 { 2642 struct device_node *np; 2643 static bool seen_dev_with_alias = false; 2644 static bool seen_dev_without_alias = false; 2645 int ret = index; 2646 2647 if (!IS_ENABLED(CONFIG_OF)) 2648 return ret; 2649 2650 np = dev->of_node; 2651 if (!np) 2652 return ret; 2653 2654 ret = of_alias_get_id(np, "serial"); 2655 if (ret < 0) { 2656 seen_dev_without_alias = true; 2657 ret = index; 2658 } else { 2659 seen_dev_with_alias = true; 2660 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { 2661 dev_warn(dev, "requested serial port %d not available.\n", ret); 2662 ret = index; 2663 } 2664 } 2665 2666 if (seen_dev_with_alias && seen_dev_without_alias) 2667 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); 2668 2669 return ret; 2670 } 2671 2672 /* unregisters the driver also if no more ports are left */ 2673 static void pl011_unregister_port(struct uart_amba_port *uap) 2674 { 2675 int i; 2676 bool busy = false; 2677 2678 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2679 if (amba_ports[i] == uap) 2680 amba_ports[i] = NULL; 2681 else if (amba_ports[i]) 2682 busy = true; 2683 } 2684 pl011_dma_remove(uap); 2685 if (!busy) 2686 uart_unregister_driver(&amba_reg); 2687 } 2688 2689 static int pl011_find_free_port(void) 2690 { 2691 int i; 2692 2693 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2694 if (amba_ports[i] == NULL) 2695 return i; 2696 2697 return -EBUSY; 2698 } 2699 2700 static int pl011_get_rs485_mode(struct uart_amba_port *uap) 2701 { 2702 struct uart_port *port = &uap->port; 2703 struct serial_rs485 *rs485 = &port->rs485; 2704 int ret; 2705 2706 ret = uart_get_rs485_mode(port); 2707 if (ret) 2708 return ret; 2709 2710 /* clamp the delays to [0, 100ms] */ 2711 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U); 2712 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U); 2713 2714 return 0; 2715 } 2716 2717 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, 2718 struct resource *mmiobase, int index) 2719 { 2720 void __iomem *base; 2721 int ret; 2722 2723 base = devm_ioremap_resource(dev, mmiobase); 2724 if (IS_ERR(base)) 2725 return PTR_ERR(base); 2726 2727 index = pl011_probe_dt_alias(index, dev); 2728 2729 uap->port.dev = dev; 2730 uap->port.mapbase = mmiobase->start; 2731 uap->port.membase = base; 2732 uap->port.fifosize = uap->fifosize; 2733 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE); 2734 uap->port.flags = UPF_BOOT_AUTOCONF; 2735 uap->port.line = index; 2736 2737 ret = pl011_get_rs485_mode(uap); 2738 if (ret) 2739 return ret; 2740 2741 amba_ports[index] = uap; 2742 2743 return 0; 2744 } 2745 2746 static int pl011_register_port(struct uart_amba_port *uap) 2747 { 2748 int ret, i; 2749 2750 /* Ensure interrupts from this UART are masked and cleared */ 2751 pl011_write(0, uap, REG_IMSC); 2752 pl011_write(0xffff, uap, REG_ICR); 2753 2754 if (!amba_reg.state) { 2755 ret = uart_register_driver(&amba_reg); 2756 if (ret < 0) { 2757 dev_err(uap->port.dev, 2758 "Failed to register AMBA-PL011 driver\n"); 2759 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2760 if (amba_ports[i] == uap) 2761 amba_ports[i] = NULL; 2762 return ret; 2763 } 2764 } 2765 2766 ret = uart_add_one_port(&amba_reg, &uap->port); 2767 if (ret) 2768 pl011_unregister_port(uap); 2769 2770 return ret; 2771 } 2772 2773 static int pl011_probe(struct amba_device *dev, const struct amba_id *id) 2774 { 2775 struct uart_amba_port *uap; 2776 struct vendor_data *vendor = id->data; 2777 int portnr, ret; 2778 2779 portnr = pl011_find_free_port(); 2780 if (portnr < 0) 2781 return portnr; 2782 2783 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), 2784 GFP_KERNEL); 2785 if (!uap) 2786 return -ENOMEM; 2787 2788 uap->clk = devm_clk_get(&dev->dev, NULL); 2789 if (IS_ERR(uap->clk)) 2790 return PTR_ERR(uap->clk); 2791 2792 uap->reg_offset = vendor->reg_offset; 2793 uap->vendor = vendor; 2794 uap->fifosize = vendor->get_fifosize(dev); 2795 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 2796 uap->port.irq = dev->irq[0]; 2797 uap->port.ops = &amba_pl011_pops; 2798 uap->port.rs485_config = pl011_rs485_config; 2799 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); 2800 2801 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); 2802 if (ret) 2803 return ret; 2804 2805 amba_set_drvdata(dev, uap); 2806 2807 return pl011_register_port(uap); 2808 } 2809 2810 static void pl011_remove(struct amba_device *dev) 2811 { 2812 struct uart_amba_port *uap = amba_get_drvdata(dev); 2813 2814 uart_remove_one_port(&amba_reg, &uap->port); 2815 pl011_unregister_port(uap); 2816 } 2817 2818 #ifdef CONFIG_PM_SLEEP 2819 static int pl011_suspend(struct device *dev) 2820 { 2821 struct uart_amba_port *uap = dev_get_drvdata(dev); 2822 2823 if (!uap) 2824 return -EINVAL; 2825 2826 return uart_suspend_port(&amba_reg, &uap->port); 2827 } 2828 2829 static int pl011_resume(struct device *dev) 2830 { 2831 struct uart_amba_port *uap = dev_get_drvdata(dev); 2832 2833 if (!uap) 2834 return -EINVAL; 2835 2836 return uart_resume_port(&amba_reg, &uap->port); 2837 } 2838 #endif 2839 2840 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); 2841 2842 static int sbsa_uart_probe(struct platform_device *pdev) 2843 { 2844 struct uart_amba_port *uap; 2845 struct resource *r; 2846 int portnr, ret; 2847 int baudrate; 2848 2849 /* 2850 * Check the mandatory baud rate parameter in the DT node early 2851 * so that we can easily exit with the error. 2852 */ 2853 if (pdev->dev.of_node) { 2854 struct device_node *np = pdev->dev.of_node; 2855 2856 ret = of_property_read_u32(np, "current-speed", &baudrate); 2857 if (ret) 2858 return ret; 2859 } else { 2860 baudrate = 115200; 2861 } 2862 2863 portnr = pl011_find_free_port(); 2864 if (portnr < 0) 2865 return portnr; 2866 2867 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), 2868 GFP_KERNEL); 2869 if (!uap) 2870 return -ENOMEM; 2871 2872 ret = platform_get_irq(pdev, 0); 2873 if (ret < 0) 2874 return ret; 2875 uap->port.irq = ret; 2876 2877 #ifdef CONFIG_ACPI_SPCR_TABLE 2878 if (qdf2400_e44_present) { 2879 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n"); 2880 uap->vendor = &vendor_qdt_qdf2400_e44; 2881 } else 2882 #endif 2883 uap->vendor = &vendor_sbsa; 2884 2885 uap->reg_offset = uap->vendor->reg_offset; 2886 uap->fifosize = 32; 2887 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 2888 uap->port.ops = &sbsa_uart_pops; 2889 uap->fixed_baud = baudrate; 2890 2891 snprintf(uap->type, sizeof(uap->type), "SBSA"); 2892 2893 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2894 2895 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); 2896 if (ret) 2897 return ret; 2898 2899 platform_set_drvdata(pdev, uap); 2900 2901 return pl011_register_port(uap); 2902 } 2903 2904 static int sbsa_uart_remove(struct platform_device *pdev) 2905 { 2906 struct uart_amba_port *uap = platform_get_drvdata(pdev); 2907 2908 uart_remove_one_port(&amba_reg, &uap->port); 2909 pl011_unregister_port(uap); 2910 return 0; 2911 } 2912 2913 static const struct of_device_id sbsa_uart_of_match[] = { 2914 { .compatible = "arm,sbsa-uart", }, 2915 {}, 2916 }; 2917 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); 2918 2919 static const struct acpi_device_id __maybe_unused sbsa_uart_acpi_match[] = { 2920 { "ARMH0011", 0 }, 2921 { "ARMHB000", 0 }, 2922 {}, 2923 }; 2924 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); 2925 2926 static struct platform_driver arm_sbsa_uart_platform_driver = { 2927 .probe = sbsa_uart_probe, 2928 .remove = sbsa_uart_remove, 2929 .driver = { 2930 .name = "sbsa-uart", 2931 .pm = &pl011_dev_pm_ops, 2932 .of_match_table = of_match_ptr(sbsa_uart_of_match), 2933 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match), 2934 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), 2935 }, 2936 }; 2937 2938 static const struct amba_id pl011_ids[] = { 2939 { 2940 .id = 0x00041011, 2941 .mask = 0x000fffff, 2942 .data = &vendor_arm, 2943 }, 2944 { 2945 .id = 0x00380802, 2946 .mask = 0x00ffffff, 2947 .data = &vendor_st, 2948 }, 2949 { 0, 0 }, 2950 }; 2951 2952 MODULE_DEVICE_TABLE(amba, pl011_ids); 2953 2954 static struct amba_driver pl011_driver = { 2955 .drv = { 2956 .name = "uart-pl011", 2957 .pm = &pl011_dev_pm_ops, 2958 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), 2959 }, 2960 .id_table = pl011_ids, 2961 .probe = pl011_probe, 2962 .remove = pl011_remove, 2963 }; 2964 2965 static int __init pl011_init(void) 2966 { 2967 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); 2968 2969 if (platform_driver_register(&arm_sbsa_uart_platform_driver)) 2970 pr_warn("could not register SBSA UART platform driver\n"); 2971 return amba_driver_register(&pl011_driver); 2972 } 2973 2974 static void __exit pl011_exit(void) 2975 { 2976 platform_driver_unregister(&arm_sbsa_uart_platform_driver); 2977 amba_driver_unregister(&pl011_driver); 2978 } 2979 2980 /* 2981 * While this can be a module, if builtin it's most likely the console 2982 * So let's leave module_exit but move module_init to an earlier place 2983 */ 2984 arch_initcall(pl011_init); 2985 module_exit(pl011_exit); 2986 2987 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 2988 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 2989 MODULE_LICENSE("GPL"); 2990