1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for AMBA serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright 1999 ARM Limited 8 * Copyright (C) 2000 Deep Blue Solutions Ltd. 9 * Copyright (C) 2010 ST-Ericsson SA 10 * 11 * This is a generic driver for ARM AMBA-type serial ports. They 12 * have a lot of 16550-like features, but are not register compatible. 13 * Note that although they do have CTS, DCD and DSR inputs, they do 14 * not have an RI input, nor do they have DTR or RTS outputs. If 15 * required, these have to be supplied via some other means (eg, GPIO) 16 * and hooked into this driver. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/ioport.h> 21 #include <linux/init.h> 22 #include <linux/console.h> 23 #include <linux/sysrq.h> 24 #include <linux/device.h> 25 #include <linux/tty.h> 26 #include <linux/tty_flip.h> 27 #include <linux/serial_core.h> 28 #include <linux/serial.h> 29 #include <linux/amba/bus.h> 30 #include <linux/amba/serial.h> 31 #include <linux/clk.h> 32 #include <linux/slab.h> 33 #include <linux/dmaengine.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/scatterlist.h> 36 #include <linux/delay.h> 37 #include <linux/types.h> 38 #include <linux/of.h> 39 #include <linux/of_device.h> 40 #include <linux/pinctrl/consumer.h> 41 #include <linux/sizes.h> 42 #include <linux/io.h> 43 #include <linux/acpi.h> 44 45 #include "amba-pl011.h" 46 47 #define UART_NR 14 48 49 #define SERIAL_AMBA_MAJOR 204 50 #define SERIAL_AMBA_MINOR 64 51 #define SERIAL_AMBA_NR UART_NR 52 53 #define AMBA_ISR_PASS_LIMIT 256 54 55 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) 56 #define UART_DUMMY_DR_RX (1 << 16) 57 58 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = { 59 [REG_DR] = UART01x_DR, 60 [REG_FR] = UART01x_FR, 61 [REG_LCRH_RX] = UART011_LCRH, 62 [REG_LCRH_TX] = UART011_LCRH, 63 [REG_IBRD] = UART011_IBRD, 64 [REG_FBRD] = UART011_FBRD, 65 [REG_CR] = UART011_CR, 66 [REG_IFLS] = UART011_IFLS, 67 [REG_IMSC] = UART011_IMSC, 68 [REG_RIS] = UART011_RIS, 69 [REG_MIS] = UART011_MIS, 70 [REG_ICR] = UART011_ICR, 71 [REG_DMACR] = UART011_DMACR, 72 }; 73 74 /* There is by now at least one vendor with differing details, so handle it */ 75 struct vendor_data { 76 const u16 *reg_offset; 77 unsigned int ifls; 78 unsigned int fr_busy; 79 unsigned int fr_dsr; 80 unsigned int fr_cts; 81 unsigned int fr_ri; 82 unsigned int inv_fr; 83 bool access_32b; 84 bool oversampling; 85 bool dma_threshold; 86 bool cts_event_workaround; 87 bool always_enabled; 88 bool fixed_options; 89 90 unsigned int (*get_fifosize)(struct amba_device *dev); 91 }; 92 93 static unsigned int get_fifosize_arm(struct amba_device *dev) 94 { 95 return amba_rev(dev) < 3 ? 16 : 32; 96 } 97 98 static struct vendor_data vendor_arm = { 99 .reg_offset = pl011_std_offsets, 100 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 101 .fr_busy = UART01x_FR_BUSY, 102 .fr_dsr = UART01x_FR_DSR, 103 .fr_cts = UART01x_FR_CTS, 104 .fr_ri = UART011_FR_RI, 105 .oversampling = false, 106 .dma_threshold = false, 107 .cts_event_workaround = false, 108 .always_enabled = false, 109 .fixed_options = false, 110 .get_fifosize = get_fifosize_arm, 111 }; 112 113 static const struct vendor_data vendor_sbsa = { 114 .reg_offset = pl011_std_offsets, 115 .fr_busy = UART01x_FR_BUSY, 116 .fr_dsr = UART01x_FR_DSR, 117 .fr_cts = UART01x_FR_CTS, 118 .fr_ri = UART011_FR_RI, 119 .access_32b = true, 120 .oversampling = false, 121 .dma_threshold = false, 122 .cts_event_workaround = false, 123 .always_enabled = true, 124 .fixed_options = true, 125 }; 126 127 #ifdef CONFIG_ACPI_SPCR_TABLE 128 static const struct vendor_data vendor_qdt_qdf2400_e44 = { 129 .reg_offset = pl011_std_offsets, 130 .fr_busy = UART011_FR_TXFE, 131 .fr_dsr = UART01x_FR_DSR, 132 .fr_cts = UART01x_FR_CTS, 133 .fr_ri = UART011_FR_RI, 134 .inv_fr = UART011_FR_TXFE, 135 .access_32b = true, 136 .oversampling = false, 137 .dma_threshold = false, 138 .cts_event_workaround = false, 139 .always_enabled = true, 140 .fixed_options = true, 141 }; 142 #endif 143 144 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { 145 [REG_DR] = UART01x_DR, 146 [REG_ST_DMAWM] = ST_UART011_DMAWM, 147 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, 148 [REG_FR] = UART01x_FR, 149 [REG_LCRH_RX] = ST_UART011_LCRH_RX, 150 [REG_LCRH_TX] = ST_UART011_LCRH_TX, 151 [REG_IBRD] = UART011_IBRD, 152 [REG_FBRD] = UART011_FBRD, 153 [REG_CR] = UART011_CR, 154 [REG_IFLS] = UART011_IFLS, 155 [REG_IMSC] = UART011_IMSC, 156 [REG_RIS] = UART011_RIS, 157 [REG_MIS] = UART011_MIS, 158 [REG_ICR] = UART011_ICR, 159 [REG_DMACR] = UART011_DMACR, 160 [REG_ST_XFCR] = ST_UART011_XFCR, 161 [REG_ST_XON1] = ST_UART011_XON1, 162 [REG_ST_XON2] = ST_UART011_XON2, 163 [REG_ST_XOFF1] = ST_UART011_XOFF1, 164 [REG_ST_XOFF2] = ST_UART011_XOFF2, 165 [REG_ST_ITCR] = ST_UART011_ITCR, 166 [REG_ST_ITIP] = ST_UART011_ITIP, 167 [REG_ST_ABCR] = ST_UART011_ABCR, 168 [REG_ST_ABIMSC] = ST_UART011_ABIMSC, 169 }; 170 171 static unsigned int get_fifosize_st(struct amba_device *dev) 172 { 173 return 64; 174 } 175 176 static struct vendor_data vendor_st = { 177 .reg_offset = pl011_st_offsets, 178 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, 179 .fr_busy = UART01x_FR_BUSY, 180 .fr_dsr = UART01x_FR_DSR, 181 .fr_cts = UART01x_FR_CTS, 182 .fr_ri = UART011_FR_RI, 183 .oversampling = true, 184 .dma_threshold = true, 185 .cts_event_workaround = true, 186 .always_enabled = false, 187 .fixed_options = false, 188 .get_fifosize = get_fifosize_st, 189 }; 190 191 static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = { 192 [REG_DR] = ZX_UART011_DR, 193 [REG_FR] = ZX_UART011_FR, 194 [REG_LCRH_RX] = ZX_UART011_LCRH, 195 [REG_LCRH_TX] = ZX_UART011_LCRH, 196 [REG_IBRD] = ZX_UART011_IBRD, 197 [REG_FBRD] = ZX_UART011_FBRD, 198 [REG_CR] = ZX_UART011_CR, 199 [REG_IFLS] = ZX_UART011_IFLS, 200 [REG_IMSC] = ZX_UART011_IMSC, 201 [REG_RIS] = ZX_UART011_RIS, 202 [REG_MIS] = ZX_UART011_MIS, 203 [REG_ICR] = ZX_UART011_ICR, 204 [REG_DMACR] = ZX_UART011_DMACR, 205 }; 206 207 static unsigned int get_fifosize_zte(struct amba_device *dev) 208 { 209 return 16; 210 } 211 212 static struct vendor_data vendor_zte = { 213 .reg_offset = pl011_zte_offsets, 214 .access_32b = true, 215 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 216 .fr_busy = ZX_UART01x_FR_BUSY, 217 .fr_dsr = ZX_UART01x_FR_DSR, 218 .fr_cts = ZX_UART01x_FR_CTS, 219 .fr_ri = ZX_UART011_FR_RI, 220 .get_fifosize = get_fifosize_zte, 221 }; 222 223 /* Deals with DMA transactions */ 224 225 struct pl011_sgbuf { 226 struct scatterlist sg; 227 char *buf; 228 }; 229 230 struct pl011_dmarx_data { 231 struct dma_chan *chan; 232 struct completion complete; 233 bool use_buf_b; 234 struct pl011_sgbuf sgbuf_a; 235 struct pl011_sgbuf sgbuf_b; 236 dma_cookie_t cookie; 237 bool running; 238 struct timer_list timer; 239 unsigned int last_residue; 240 unsigned long last_jiffies; 241 bool auto_poll_rate; 242 unsigned int poll_rate; 243 unsigned int poll_timeout; 244 }; 245 246 struct pl011_dmatx_data { 247 struct dma_chan *chan; 248 struct scatterlist sg; 249 char *buf; 250 bool queued; 251 }; 252 253 /* 254 * We wrap our port structure around the generic uart_port. 255 */ 256 struct uart_amba_port { 257 struct uart_port port; 258 const u16 *reg_offset; 259 struct clk *clk; 260 const struct vendor_data *vendor; 261 unsigned int dmacr; /* dma control reg */ 262 unsigned int im; /* interrupt mask */ 263 unsigned int old_status; 264 unsigned int fifosize; /* vendor-specific */ 265 unsigned int old_cr; /* state during shutdown */ 266 unsigned int fixed_baud; /* vendor-set fixed baud rate */ 267 char type[12]; 268 #ifdef CONFIG_DMA_ENGINE 269 /* DMA stuff */ 270 bool using_tx_dma; 271 bool using_rx_dma; 272 struct pl011_dmarx_data dmarx; 273 struct pl011_dmatx_data dmatx; 274 bool dma_probed; 275 #endif 276 }; 277 278 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, 279 unsigned int reg) 280 { 281 return uap->reg_offset[reg]; 282 } 283 284 static unsigned int pl011_read(const struct uart_amba_port *uap, 285 unsigned int reg) 286 { 287 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 288 289 return (uap->port.iotype == UPIO_MEM32) ? 290 readl_relaxed(addr) : readw_relaxed(addr); 291 } 292 293 static void pl011_write(unsigned int val, const struct uart_amba_port *uap, 294 unsigned int reg) 295 { 296 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 297 298 if (uap->port.iotype == UPIO_MEM32) 299 writel_relaxed(val, addr); 300 else 301 writew_relaxed(val, addr); 302 } 303 304 /* 305 * Reads up to 256 characters from the FIFO or until it's empty and 306 * inserts them into the TTY layer. Returns the number of characters 307 * read from the FIFO. 308 */ 309 static int pl011_fifo_to_tty(struct uart_amba_port *uap) 310 { 311 unsigned int ch, flag, fifotaken; 312 int sysrq; 313 u16 status; 314 315 for (fifotaken = 0; fifotaken != 256; fifotaken++) { 316 status = pl011_read(uap, REG_FR); 317 if (status & UART01x_FR_RXFE) 318 break; 319 320 /* Take chars from the FIFO and update status */ 321 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; 322 flag = TTY_NORMAL; 323 uap->port.icount.rx++; 324 325 if (unlikely(ch & UART_DR_ERROR)) { 326 if (ch & UART011_DR_BE) { 327 ch &= ~(UART011_DR_FE | UART011_DR_PE); 328 uap->port.icount.brk++; 329 if (uart_handle_break(&uap->port)) 330 continue; 331 } else if (ch & UART011_DR_PE) 332 uap->port.icount.parity++; 333 else if (ch & UART011_DR_FE) 334 uap->port.icount.frame++; 335 if (ch & UART011_DR_OE) 336 uap->port.icount.overrun++; 337 338 ch &= uap->port.read_status_mask; 339 340 if (ch & UART011_DR_BE) 341 flag = TTY_BREAK; 342 else if (ch & UART011_DR_PE) 343 flag = TTY_PARITY; 344 else if (ch & UART011_DR_FE) 345 flag = TTY_FRAME; 346 } 347 348 spin_unlock(&uap->port.lock); 349 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255); 350 spin_lock(&uap->port.lock); 351 352 if (!sysrq) 353 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); 354 } 355 356 return fifotaken; 357 } 358 359 360 /* 361 * All the DMA operation mode stuff goes inside this ifdef. 362 * This assumes that you have a generic DMA device interface, 363 * no custom DMA interfaces are supported. 364 */ 365 #ifdef CONFIG_DMA_ENGINE 366 367 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE 368 369 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, 370 enum dma_data_direction dir) 371 { 372 dma_addr_t dma_addr; 373 374 sg->buf = dma_alloc_coherent(chan->device->dev, 375 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); 376 if (!sg->buf) 377 return -ENOMEM; 378 379 sg_init_table(&sg->sg, 1); 380 sg_set_page(&sg->sg, phys_to_page(dma_addr), 381 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); 382 sg_dma_address(&sg->sg) = dma_addr; 383 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; 384 385 return 0; 386 } 387 388 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, 389 enum dma_data_direction dir) 390 { 391 if (sg->buf) { 392 dma_free_coherent(chan->device->dev, 393 PL011_DMA_BUFFER_SIZE, sg->buf, 394 sg_dma_address(&sg->sg)); 395 } 396 } 397 398 static void pl011_dma_probe(struct uart_amba_port *uap) 399 { 400 /* DMA is the sole user of the platform data right now */ 401 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); 402 struct device *dev = uap->port.dev; 403 struct dma_slave_config tx_conf = { 404 .dst_addr = uap->port.mapbase + 405 pl011_reg_to_offset(uap, REG_DR), 406 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 407 .direction = DMA_MEM_TO_DEV, 408 .dst_maxburst = uap->fifosize >> 1, 409 .device_fc = false, 410 }; 411 struct dma_chan *chan; 412 dma_cap_mask_t mask; 413 414 uap->dma_probed = true; 415 chan = dma_request_chan(dev, "tx"); 416 if (IS_ERR(chan)) { 417 if (PTR_ERR(chan) == -EPROBE_DEFER) { 418 uap->dma_probed = false; 419 return; 420 } 421 422 /* We need platform data */ 423 if (!plat || !plat->dma_filter) { 424 dev_info(uap->port.dev, "no DMA platform data\n"); 425 return; 426 } 427 428 /* Try to acquire a generic DMA engine slave TX channel */ 429 dma_cap_zero(mask); 430 dma_cap_set(DMA_SLAVE, mask); 431 432 chan = dma_request_channel(mask, plat->dma_filter, 433 plat->dma_tx_param); 434 if (!chan) { 435 dev_err(uap->port.dev, "no TX DMA channel!\n"); 436 return; 437 } 438 } 439 440 dmaengine_slave_config(chan, &tx_conf); 441 uap->dmatx.chan = chan; 442 443 dev_info(uap->port.dev, "DMA channel TX %s\n", 444 dma_chan_name(uap->dmatx.chan)); 445 446 /* Optionally make use of an RX channel as well */ 447 chan = dma_request_slave_channel(dev, "rx"); 448 449 if (!chan && plat && plat->dma_rx_param) { 450 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); 451 452 if (!chan) { 453 dev_err(uap->port.dev, "no RX DMA channel!\n"); 454 return; 455 } 456 } 457 458 if (chan) { 459 struct dma_slave_config rx_conf = { 460 .src_addr = uap->port.mapbase + 461 pl011_reg_to_offset(uap, REG_DR), 462 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 463 .direction = DMA_DEV_TO_MEM, 464 .src_maxburst = uap->fifosize >> 2, 465 .device_fc = false, 466 }; 467 struct dma_slave_caps caps; 468 469 /* 470 * Some DMA controllers provide information on their capabilities. 471 * If the controller does, check for suitable residue processing 472 * otherwise assime all is well. 473 */ 474 if (0 == dma_get_slave_caps(chan, &caps)) { 475 if (caps.residue_granularity == 476 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { 477 dma_release_channel(chan); 478 dev_info(uap->port.dev, 479 "RX DMA disabled - no residue processing\n"); 480 return; 481 } 482 } 483 dmaengine_slave_config(chan, &rx_conf); 484 uap->dmarx.chan = chan; 485 486 uap->dmarx.auto_poll_rate = false; 487 if (plat && plat->dma_rx_poll_enable) { 488 /* Set poll rate if specified. */ 489 if (plat->dma_rx_poll_rate) { 490 uap->dmarx.auto_poll_rate = false; 491 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; 492 } else { 493 /* 494 * 100 ms defaults to poll rate if not 495 * specified. This will be adjusted with 496 * the baud rate at set_termios. 497 */ 498 uap->dmarx.auto_poll_rate = true; 499 uap->dmarx.poll_rate = 100; 500 } 501 /* 3 secs defaults poll_timeout if not specified. */ 502 if (plat->dma_rx_poll_timeout) 503 uap->dmarx.poll_timeout = 504 plat->dma_rx_poll_timeout; 505 else 506 uap->dmarx.poll_timeout = 3000; 507 } else if (!plat && dev->of_node) { 508 uap->dmarx.auto_poll_rate = of_property_read_bool( 509 dev->of_node, "auto-poll"); 510 if (uap->dmarx.auto_poll_rate) { 511 u32 x; 512 513 if (0 == of_property_read_u32(dev->of_node, 514 "poll-rate-ms", &x)) 515 uap->dmarx.poll_rate = x; 516 else 517 uap->dmarx.poll_rate = 100; 518 if (0 == of_property_read_u32(dev->of_node, 519 "poll-timeout-ms", &x)) 520 uap->dmarx.poll_timeout = x; 521 else 522 uap->dmarx.poll_timeout = 3000; 523 } 524 } 525 dev_info(uap->port.dev, "DMA channel RX %s\n", 526 dma_chan_name(uap->dmarx.chan)); 527 } 528 } 529 530 static void pl011_dma_remove(struct uart_amba_port *uap) 531 { 532 if (uap->dmatx.chan) 533 dma_release_channel(uap->dmatx.chan); 534 if (uap->dmarx.chan) 535 dma_release_channel(uap->dmarx.chan); 536 } 537 538 /* Forward declare these for the refill routine */ 539 static int pl011_dma_tx_refill(struct uart_amba_port *uap); 540 static void pl011_start_tx_pio(struct uart_amba_port *uap); 541 542 /* 543 * The current DMA TX buffer has been sent. 544 * Try to queue up another DMA buffer. 545 */ 546 static void pl011_dma_tx_callback(void *data) 547 { 548 struct uart_amba_port *uap = data; 549 struct pl011_dmatx_data *dmatx = &uap->dmatx; 550 unsigned long flags; 551 u16 dmacr; 552 553 spin_lock_irqsave(&uap->port.lock, flags); 554 if (uap->dmatx.queued) 555 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, 556 DMA_TO_DEVICE); 557 558 dmacr = uap->dmacr; 559 uap->dmacr = dmacr & ~UART011_TXDMAE; 560 pl011_write(uap->dmacr, uap, REG_DMACR); 561 562 /* 563 * If TX DMA was disabled, it means that we've stopped the DMA for 564 * some reason (eg, XOFF received, or we want to send an X-char.) 565 * 566 * Note: we need to be careful here of a potential race between DMA 567 * and the rest of the driver - if the driver disables TX DMA while 568 * a TX buffer completing, we must update the tx queued status to 569 * get further refills (hence we check dmacr). 570 */ 571 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || 572 uart_circ_empty(&uap->port.state->xmit)) { 573 uap->dmatx.queued = false; 574 spin_unlock_irqrestore(&uap->port.lock, flags); 575 return; 576 } 577 578 if (pl011_dma_tx_refill(uap) <= 0) 579 /* 580 * We didn't queue a DMA buffer for some reason, but we 581 * have data pending to be sent. Re-enable the TX IRQ. 582 */ 583 pl011_start_tx_pio(uap); 584 585 spin_unlock_irqrestore(&uap->port.lock, flags); 586 } 587 588 /* 589 * Try to refill the TX DMA buffer. 590 * Locking: called with port lock held and IRQs disabled. 591 * Returns: 592 * 1 if we queued up a TX DMA buffer. 593 * 0 if we didn't want to handle this by DMA 594 * <0 on error 595 */ 596 static int pl011_dma_tx_refill(struct uart_amba_port *uap) 597 { 598 struct pl011_dmatx_data *dmatx = &uap->dmatx; 599 struct dma_chan *chan = dmatx->chan; 600 struct dma_device *dma_dev = chan->device; 601 struct dma_async_tx_descriptor *desc; 602 struct circ_buf *xmit = &uap->port.state->xmit; 603 unsigned int count; 604 605 /* 606 * Try to avoid the overhead involved in using DMA if the 607 * transaction fits in the first half of the FIFO, by using 608 * the standard interrupt handling. This ensures that we 609 * issue a uart_write_wakeup() at the appropriate time. 610 */ 611 count = uart_circ_chars_pending(xmit); 612 if (count < (uap->fifosize >> 1)) { 613 uap->dmatx.queued = false; 614 return 0; 615 } 616 617 /* 618 * Bodge: don't send the last character by DMA, as this 619 * will prevent XON from notifying us to restart DMA. 620 */ 621 count -= 1; 622 623 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ 624 if (count > PL011_DMA_BUFFER_SIZE) 625 count = PL011_DMA_BUFFER_SIZE; 626 627 if (xmit->tail < xmit->head) 628 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); 629 else { 630 size_t first = UART_XMIT_SIZE - xmit->tail; 631 size_t second; 632 633 if (first > count) 634 first = count; 635 second = count - first; 636 637 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); 638 if (second) 639 memcpy(&dmatx->buf[first], &xmit->buf[0], second); 640 } 641 642 dmatx->sg.length = count; 643 644 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { 645 uap->dmatx.queued = false; 646 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); 647 return -EBUSY; 648 } 649 650 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, 651 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 652 if (!desc) { 653 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); 654 uap->dmatx.queued = false; 655 /* 656 * If DMA cannot be used right now, we complete this 657 * transaction via IRQ and let the TTY layer retry. 658 */ 659 dev_dbg(uap->port.dev, "TX DMA busy\n"); 660 return -EBUSY; 661 } 662 663 /* Some data to go along to the callback */ 664 desc->callback = pl011_dma_tx_callback; 665 desc->callback_param = uap; 666 667 /* All errors should happen at prepare time */ 668 dmaengine_submit(desc); 669 670 /* Fire the DMA transaction */ 671 dma_dev->device_issue_pending(chan); 672 673 uap->dmacr |= UART011_TXDMAE; 674 pl011_write(uap->dmacr, uap, REG_DMACR); 675 uap->dmatx.queued = true; 676 677 /* 678 * Now we know that DMA will fire, so advance the ring buffer 679 * with the stuff we just dispatched. 680 */ 681 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 682 uap->port.icount.tx += count; 683 684 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 685 uart_write_wakeup(&uap->port); 686 687 return 1; 688 } 689 690 /* 691 * We received a transmit interrupt without a pending X-char but with 692 * pending characters. 693 * Locking: called with port lock held and IRQs disabled. 694 * Returns: 695 * false if we want to use PIO to transmit 696 * true if we queued a DMA buffer 697 */ 698 static bool pl011_dma_tx_irq(struct uart_amba_port *uap) 699 { 700 if (!uap->using_tx_dma) 701 return false; 702 703 /* 704 * If we already have a TX buffer queued, but received a 705 * TX interrupt, it will be because we've just sent an X-char. 706 * Ensure the TX DMA is enabled and the TX IRQ is disabled. 707 */ 708 if (uap->dmatx.queued) { 709 uap->dmacr |= UART011_TXDMAE; 710 pl011_write(uap->dmacr, uap, REG_DMACR); 711 uap->im &= ~UART011_TXIM; 712 pl011_write(uap->im, uap, REG_IMSC); 713 return true; 714 } 715 716 /* 717 * We don't have a TX buffer queued, so try to queue one. 718 * If we successfully queued a buffer, mask the TX IRQ. 719 */ 720 if (pl011_dma_tx_refill(uap) > 0) { 721 uap->im &= ~UART011_TXIM; 722 pl011_write(uap->im, uap, REG_IMSC); 723 return true; 724 } 725 return false; 726 } 727 728 /* 729 * Stop the DMA transmit (eg, due to received XOFF). 730 * Locking: called with port lock held and IRQs disabled. 731 */ 732 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 733 { 734 if (uap->dmatx.queued) { 735 uap->dmacr &= ~UART011_TXDMAE; 736 pl011_write(uap->dmacr, uap, REG_DMACR); 737 } 738 } 739 740 /* 741 * Try to start a DMA transmit, or in the case of an XON/OFF 742 * character queued for send, try to get that character out ASAP. 743 * Locking: called with port lock held and IRQs disabled. 744 * Returns: 745 * false if we want the TX IRQ to be enabled 746 * true if we have a buffer queued 747 */ 748 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 749 { 750 u16 dmacr; 751 752 if (!uap->using_tx_dma) 753 return false; 754 755 if (!uap->port.x_char) { 756 /* no X-char, try to push chars out in DMA mode */ 757 bool ret = true; 758 759 if (!uap->dmatx.queued) { 760 if (pl011_dma_tx_refill(uap) > 0) { 761 uap->im &= ~UART011_TXIM; 762 pl011_write(uap->im, uap, REG_IMSC); 763 } else 764 ret = false; 765 } else if (!(uap->dmacr & UART011_TXDMAE)) { 766 uap->dmacr |= UART011_TXDMAE; 767 pl011_write(uap->dmacr, uap, REG_DMACR); 768 } 769 return ret; 770 } 771 772 /* 773 * We have an X-char to send. Disable DMA to prevent it loading 774 * the TX fifo, and then see if we can stuff it into the FIFO. 775 */ 776 dmacr = uap->dmacr; 777 uap->dmacr &= ~UART011_TXDMAE; 778 pl011_write(uap->dmacr, uap, REG_DMACR); 779 780 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { 781 /* 782 * No space in the FIFO, so enable the transmit interrupt 783 * so we know when there is space. Note that once we've 784 * loaded the character, we should just re-enable DMA. 785 */ 786 return false; 787 } 788 789 pl011_write(uap->port.x_char, uap, REG_DR); 790 uap->port.icount.tx++; 791 uap->port.x_char = 0; 792 793 /* Success - restore the DMA state */ 794 uap->dmacr = dmacr; 795 pl011_write(dmacr, uap, REG_DMACR); 796 797 return true; 798 } 799 800 /* 801 * Flush the transmit buffer. 802 * Locking: called with port lock held and IRQs disabled. 803 */ 804 static void pl011_dma_flush_buffer(struct uart_port *port) 805 __releases(&uap->port.lock) 806 __acquires(&uap->port.lock) 807 { 808 struct uart_amba_port *uap = 809 container_of(port, struct uart_amba_port, port); 810 811 if (!uap->using_tx_dma) 812 return; 813 814 dmaengine_terminate_async(uap->dmatx.chan); 815 816 if (uap->dmatx.queued) { 817 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 818 DMA_TO_DEVICE); 819 uap->dmatx.queued = false; 820 uap->dmacr &= ~UART011_TXDMAE; 821 pl011_write(uap->dmacr, uap, REG_DMACR); 822 } 823 } 824 825 static void pl011_dma_rx_callback(void *data); 826 827 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 828 { 829 struct dma_chan *rxchan = uap->dmarx.chan; 830 struct pl011_dmarx_data *dmarx = &uap->dmarx; 831 struct dma_async_tx_descriptor *desc; 832 struct pl011_sgbuf *sgbuf; 833 834 if (!rxchan) 835 return -EIO; 836 837 /* Start the RX DMA job */ 838 sgbuf = uap->dmarx.use_buf_b ? 839 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 840 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, 841 DMA_DEV_TO_MEM, 842 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 843 /* 844 * If the DMA engine is busy and cannot prepare a 845 * channel, no big deal, the driver will fall back 846 * to interrupt mode as a result of this error code. 847 */ 848 if (!desc) { 849 uap->dmarx.running = false; 850 dmaengine_terminate_all(rxchan); 851 return -EBUSY; 852 } 853 854 /* Some data to go along to the callback */ 855 desc->callback = pl011_dma_rx_callback; 856 desc->callback_param = uap; 857 dmarx->cookie = dmaengine_submit(desc); 858 dma_async_issue_pending(rxchan); 859 860 uap->dmacr |= UART011_RXDMAE; 861 pl011_write(uap->dmacr, uap, REG_DMACR); 862 uap->dmarx.running = true; 863 864 uap->im &= ~UART011_RXIM; 865 pl011_write(uap->im, uap, REG_IMSC); 866 867 return 0; 868 } 869 870 /* 871 * This is called when either the DMA job is complete, or 872 * the FIFO timeout interrupt occurred. This must be called 873 * with the port spinlock uap->port.lock held. 874 */ 875 static void pl011_dma_rx_chars(struct uart_amba_port *uap, 876 u32 pending, bool use_buf_b, 877 bool readfifo) 878 { 879 struct tty_port *port = &uap->port.state->port; 880 struct pl011_sgbuf *sgbuf = use_buf_b ? 881 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 882 int dma_count = 0; 883 u32 fifotaken = 0; /* only used for vdbg() */ 884 885 struct pl011_dmarx_data *dmarx = &uap->dmarx; 886 int dmataken = 0; 887 888 if (uap->dmarx.poll_rate) { 889 /* The data can be taken by polling */ 890 dmataken = sgbuf->sg.length - dmarx->last_residue; 891 /* Recalculate the pending size */ 892 if (pending >= dmataken) 893 pending -= dmataken; 894 } 895 896 /* Pick the remain data from the DMA */ 897 if (pending) { 898 899 /* 900 * First take all chars in the DMA pipe, then look in the FIFO. 901 * Note that tty_insert_flip_buf() tries to take as many chars 902 * as it can. 903 */ 904 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 905 pending); 906 907 uap->port.icount.rx += dma_count; 908 if (dma_count < pending) 909 dev_warn(uap->port.dev, 910 "couldn't insert all characters (TTY is full?)\n"); 911 } 912 913 /* Reset the last_residue for Rx DMA poll */ 914 if (uap->dmarx.poll_rate) 915 dmarx->last_residue = sgbuf->sg.length; 916 917 /* 918 * Only continue with trying to read the FIFO if all DMA chars have 919 * been taken first. 920 */ 921 if (dma_count == pending && readfifo) { 922 /* Clear any error flags */ 923 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 924 UART011_FEIS, uap, REG_ICR); 925 926 /* 927 * If we read all the DMA'd characters, and we had an 928 * incomplete buffer, that could be due to an rx error, or 929 * maybe we just timed out. Read any pending chars and check 930 * the error status. 931 * 932 * Error conditions will only occur in the FIFO, these will 933 * trigger an immediate interrupt and stop the DMA job, so we 934 * will always find the error in the FIFO, never in the DMA 935 * buffer. 936 */ 937 fifotaken = pl011_fifo_to_tty(uap); 938 } 939 940 dev_vdbg(uap->port.dev, 941 "Took %d chars from DMA buffer and %d chars from the FIFO\n", 942 dma_count, fifotaken); 943 tty_flip_buffer_push(port); 944 } 945 946 static void pl011_dma_rx_irq(struct uart_amba_port *uap) 947 { 948 struct pl011_dmarx_data *dmarx = &uap->dmarx; 949 struct dma_chan *rxchan = dmarx->chan; 950 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 951 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 952 size_t pending; 953 struct dma_tx_state state; 954 enum dma_status dmastat; 955 956 /* 957 * Pause the transfer so we can trust the current counter, 958 * do this before we pause the PL011 block, else we may 959 * overflow the FIFO. 960 */ 961 if (dmaengine_pause(rxchan)) 962 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 963 dmastat = rxchan->device->device_tx_status(rxchan, 964 dmarx->cookie, &state); 965 if (dmastat != DMA_PAUSED) 966 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 967 968 /* Disable RX DMA - incoming data will wait in the FIFO */ 969 uap->dmacr &= ~UART011_RXDMAE; 970 pl011_write(uap->dmacr, uap, REG_DMACR); 971 uap->dmarx.running = false; 972 973 pending = sgbuf->sg.length - state.residue; 974 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 975 /* Then we terminate the transfer - we now know our residue */ 976 dmaengine_terminate_all(rxchan); 977 978 /* 979 * This will take the chars we have so far and insert 980 * into the framework. 981 */ 982 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); 983 984 /* Switch buffer & re-trigger DMA job */ 985 dmarx->use_buf_b = !dmarx->use_buf_b; 986 if (pl011_dma_rx_trigger_dma(uap)) { 987 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 988 "fall back to interrupt mode\n"); 989 uap->im |= UART011_RXIM; 990 pl011_write(uap->im, uap, REG_IMSC); 991 } 992 } 993 994 static void pl011_dma_rx_callback(void *data) 995 { 996 struct uart_amba_port *uap = data; 997 struct pl011_dmarx_data *dmarx = &uap->dmarx; 998 struct dma_chan *rxchan = dmarx->chan; 999 bool lastbuf = dmarx->use_buf_b; 1000 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 1001 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 1002 size_t pending; 1003 struct dma_tx_state state; 1004 int ret; 1005 1006 /* 1007 * This completion interrupt occurs typically when the 1008 * RX buffer is totally stuffed but no timeout has yet 1009 * occurred. When that happens, we just want the RX 1010 * routine to flush out the secondary DMA buffer while 1011 * we immediately trigger the next DMA job. 1012 */ 1013 spin_lock_irq(&uap->port.lock); 1014 /* 1015 * Rx data can be taken by the UART interrupts during 1016 * the DMA irq handler. So we check the residue here. 1017 */ 1018 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1019 pending = sgbuf->sg.length - state.residue; 1020 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 1021 /* Then we terminate the transfer - we now know our residue */ 1022 dmaengine_terminate_all(rxchan); 1023 1024 uap->dmarx.running = false; 1025 dmarx->use_buf_b = !lastbuf; 1026 ret = pl011_dma_rx_trigger_dma(uap); 1027 1028 pl011_dma_rx_chars(uap, pending, lastbuf, false); 1029 spin_unlock_irq(&uap->port.lock); 1030 /* 1031 * Do this check after we picked the DMA chars so we don't 1032 * get some IRQ immediately from RX. 1033 */ 1034 if (ret) { 1035 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 1036 "fall back to interrupt mode\n"); 1037 uap->im |= UART011_RXIM; 1038 pl011_write(uap->im, uap, REG_IMSC); 1039 } 1040 } 1041 1042 /* 1043 * Stop accepting received characters, when we're shutting down or 1044 * suspending this port. 1045 * Locking: called with port lock held and IRQs disabled. 1046 */ 1047 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1048 { 1049 /* FIXME. Just disable the DMA enable */ 1050 uap->dmacr &= ~UART011_RXDMAE; 1051 pl011_write(uap->dmacr, uap, REG_DMACR); 1052 } 1053 1054 /* 1055 * Timer handler for Rx DMA polling. 1056 * Every polling, It checks the residue in the dma buffer and transfer 1057 * data to the tty. Also, last_residue is updated for the next polling. 1058 */ 1059 static void pl011_dma_rx_poll(struct timer_list *t) 1060 { 1061 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer); 1062 struct tty_port *port = &uap->port.state->port; 1063 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1064 struct dma_chan *rxchan = uap->dmarx.chan; 1065 unsigned long flags; 1066 unsigned int dmataken = 0; 1067 unsigned int size = 0; 1068 struct pl011_sgbuf *sgbuf; 1069 int dma_count; 1070 struct dma_tx_state state; 1071 1072 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 1073 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1074 if (likely(state.residue < dmarx->last_residue)) { 1075 dmataken = sgbuf->sg.length - dmarx->last_residue; 1076 size = dmarx->last_residue - state.residue; 1077 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 1078 size); 1079 if (dma_count == size) 1080 dmarx->last_residue = state.residue; 1081 dmarx->last_jiffies = jiffies; 1082 } 1083 tty_flip_buffer_push(port); 1084 1085 /* 1086 * If no data is received in poll_timeout, the driver will fall back 1087 * to interrupt mode. We will retrigger DMA at the first interrupt. 1088 */ 1089 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) 1090 > uap->dmarx.poll_timeout) { 1091 1092 spin_lock_irqsave(&uap->port.lock, flags); 1093 pl011_dma_rx_stop(uap); 1094 uap->im |= UART011_RXIM; 1095 pl011_write(uap->im, uap, REG_IMSC); 1096 spin_unlock_irqrestore(&uap->port.lock, flags); 1097 1098 uap->dmarx.running = false; 1099 dmaengine_terminate_all(rxchan); 1100 del_timer(&uap->dmarx.timer); 1101 } else { 1102 mod_timer(&uap->dmarx.timer, 1103 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); 1104 } 1105 } 1106 1107 static void pl011_dma_startup(struct uart_amba_port *uap) 1108 { 1109 int ret; 1110 1111 if (!uap->dma_probed) 1112 pl011_dma_probe(uap); 1113 1114 if (!uap->dmatx.chan) 1115 return; 1116 1117 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); 1118 if (!uap->dmatx.buf) { 1119 dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); 1120 uap->port.fifosize = uap->fifosize; 1121 return; 1122 } 1123 1124 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); 1125 1126 /* The DMA buffer is now the FIFO the TTY subsystem can use */ 1127 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; 1128 uap->using_tx_dma = true; 1129 1130 if (!uap->dmarx.chan) 1131 goto skip_rx; 1132 1133 /* Allocate and map DMA RX buffers */ 1134 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1135 DMA_FROM_DEVICE); 1136 if (ret) { 1137 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1138 "RX buffer A", ret); 1139 goto skip_rx; 1140 } 1141 1142 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, 1143 DMA_FROM_DEVICE); 1144 if (ret) { 1145 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1146 "RX buffer B", ret); 1147 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1148 DMA_FROM_DEVICE); 1149 goto skip_rx; 1150 } 1151 1152 uap->using_rx_dma = true; 1153 1154 skip_rx: 1155 /* Turn on DMA error (RX/TX will be enabled on demand) */ 1156 uap->dmacr |= UART011_DMAONERR; 1157 pl011_write(uap->dmacr, uap, REG_DMACR); 1158 1159 /* 1160 * ST Micro variants has some specific dma burst threshold 1161 * compensation. Set this to 16 bytes, so burst will only 1162 * be issued above/below 16 bytes. 1163 */ 1164 if (uap->vendor->dma_threshold) 1165 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, 1166 uap, REG_ST_DMAWM); 1167 1168 if (uap->using_rx_dma) { 1169 if (pl011_dma_rx_trigger_dma(uap)) 1170 dev_dbg(uap->port.dev, "could not trigger initial " 1171 "RX DMA job, fall back to interrupt mode\n"); 1172 if (uap->dmarx.poll_rate) { 1173 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0); 1174 mod_timer(&uap->dmarx.timer, 1175 jiffies + 1176 msecs_to_jiffies(uap->dmarx.poll_rate)); 1177 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1178 uap->dmarx.last_jiffies = jiffies; 1179 } 1180 } 1181 } 1182 1183 static void pl011_dma_shutdown(struct uart_amba_port *uap) 1184 { 1185 if (!(uap->using_tx_dma || uap->using_rx_dma)) 1186 return; 1187 1188 /* Disable RX and TX DMA */ 1189 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) 1190 cpu_relax(); 1191 1192 spin_lock_irq(&uap->port.lock); 1193 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); 1194 pl011_write(uap->dmacr, uap, REG_DMACR); 1195 spin_unlock_irq(&uap->port.lock); 1196 1197 if (uap->using_tx_dma) { 1198 /* In theory, this should already be done by pl011_dma_flush_buffer */ 1199 dmaengine_terminate_all(uap->dmatx.chan); 1200 if (uap->dmatx.queued) { 1201 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 1202 DMA_TO_DEVICE); 1203 uap->dmatx.queued = false; 1204 } 1205 1206 kfree(uap->dmatx.buf); 1207 uap->using_tx_dma = false; 1208 } 1209 1210 if (uap->using_rx_dma) { 1211 dmaengine_terminate_all(uap->dmarx.chan); 1212 /* Clean up the RX DMA */ 1213 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); 1214 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); 1215 if (uap->dmarx.poll_rate) 1216 del_timer_sync(&uap->dmarx.timer); 1217 uap->using_rx_dma = false; 1218 } 1219 } 1220 1221 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1222 { 1223 return uap->using_rx_dma; 1224 } 1225 1226 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1227 { 1228 return uap->using_rx_dma && uap->dmarx.running; 1229 } 1230 1231 #else 1232 /* Blank functions if the DMA engine is not available */ 1233 static inline void pl011_dma_remove(struct uart_amba_port *uap) 1234 { 1235 } 1236 1237 static inline void pl011_dma_startup(struct uart_amba_port *uap) 1238 { 1239 } 1240 1241 static inline void pl011_dma_shutdown(struct uart_amba_port *uap) 1242 { 1243 } 1244 1245 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) 1246 { 1247 return false; 1248 } 1249 1250 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 1251 { 1252 } 1253 1254 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 1255 { 1256 return false; 1257 } 1258 1259 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) 1260 { 1261 } 1262 1263 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1264 { 1265 } 1266 1267 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 1268 { 1269 return -EIO; 1270 } 1271 1272 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1273 { 1274 return false; 1275 } 1276 1277 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1278 { 1279 return false; 1280 } 1281 1282 #define pl011_dma_flush_buffer NULL 1283 #endif 1284 1285 static void pl011_stop_tx(struct uart_port *port) 1286 { 1287 struct uart_amba_port *uap = 1288 container_of(port, struct uart_amba_port, port); 1289 1290 uap->im &= ~UART011_TXIM; 1291 pl011_write(uap->im, uap, REG_IMSC); 1292 pl011_dma_tx_stop(uap); 1293 } 1294 1295 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); 1296 1297 /* Start TX with programmed I/O only (no DMA) */ 1298 static void pl011_start_tx_pio(struct uart_amba_port *uap) 1299 { 1300 if (pl011_tx_chars(uap, false)) { 1301 uap->im |= UART011_TXIM; 1302 pl011_write(uap->im, uap, REG_IMSC); 1303 } 1304 } 1305 1306 static void pl011_start_tx(struct uart_port *port) 1307 { 1308 struct uart_amba_port *uap = 1309 container_of(port, struct uart_amba_port, port); 1310 1311 if (!pl011_dma_tx_start(uap)) 1312 pl011_start_tx_pio(uap); 1313 } 1314 1315 static void pl011_stop_rx(struct uart_port *port) 1316 { 1317 struct uart_amba_port *uap = 1318 container_of(port, struct uart_amba_port, port); 1319 1320 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| 1321 UART011_PEIM|UART011_BEIM|UART011_OEIM); 1322 pl011_write(uap->im, uap, REG_IMSC); 1323 1324 pl011_dma_rx_stop(uap); 1325 } 1326 1327 static void pl011_enable_ms(struct uart_port *port) 1328 { 1329 struct uart_amba_port *uap = 1330 container_of(port, struct uart_amba_port, port); 1331 1332 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; 1333 pl011_write(uap->im, uap, REG_IMSC); 1334 } 1335 1336 static void pl011_rx_chars(struct uart_amba_port *uap) 1337 __releases(&uap->port.lock) 1338 __acquires(&uap->port.lock) 1339 { 1340 pl011_fifo_to_tty(uap); 1341 1342 spin_unlock(&uap->port.lock); 1343 tty_flip_buffer_push(&uap->port.state->port); 1344 /* 1345 * If we were temporarily out of DMA mode for a while, 1346 * attempt to switch back to DMA mode again. 1347 */ 1348 if (pl011_dma_rx_available(uap)) { 1349 if (pl011_dma_rx_trigger_dma(uap)) { 1350 dev_dbg(uap->port.dev, "could not trigger RX DMA job " 1351 "fall back to interrupt mode again\n"); 1352 uap->im |= UART011_RXIM; 1353 pl011_write(uap->im, uap, REG_IMSC); 1354 } else { 1355 #ifdef CONFIG_DMA_ENGINE 1356 /* Start Rx DMA poll */ 1357 if (uap->dmarx.poll_rate) { 1358 uap->dmarx.last_jiffies = jiffies; 1359 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1360 mod_timer(&uap->dmarx.timer, 1361 jiffies + 1362 msecs_to_jiffies(uap->dmarx.poll_rate)); 1363 } 1364 #endif 1365 } 1366 } 1367 spin_lock(&uap->port.lock); 1368 } 1369 1370 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, 1371 bool from_irq) 1372 { 1373 if (unlikely(!from_irq) && 1374 pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1375 return false; /* unable to transmit character */ 1376 1377 pl011_write(c, uap, REG_DR); 1378 uap->port.icount.tx++; 1379 1380 return true; 1381 } 1382 1383 /* Returns true if tx interrupts have to be (kept) enabled */ 1384 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) 1385 { 1386 struct circ_buf *xmit = &uap->port.state->xmit; 1387 int count = uap->fifosize >> 1; 1388 1389 if (uap->port.x_char) { 1390 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) 1391 return true; 1392 uap->port.x_char = 0; 1393 --count; 1394 } 1395 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { 1396 pl011_stop_tx(&uap->port); 1397 return false; 1398 } 1399 1400 /* If we are using DMA mode, try to send some characters. */ 1401 if (pl011_dma_tx_irq(uap)) 1402 return true; 1403 1404 do { 1405 if (likely(from_irq) && count-- == 0) 1406 break; 1407 1408 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) 1409 break; 1410 1411 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1412 } while (!uart_circ_empty(xmit)); 1413 1414 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1415 uart_write_wakeup(&uap->port); 1416 1417 if (uart_circ_empty(xmit)) { 1418 pl011_stop_tx(&uap->port); 1419 return false; 1420 } 1421 return true; 1422 } 1423 1424 static void pl011_modem_status(struct uart_amba_port *uap) 1425 { 1426 unsigned int status, delta; 1427 1428 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1429 1430 delta = status ^ uap->old_status; 1431 uap->old_status = status; 1432 1433 if (!delta) 1434 return; 1435 1436 if (delta & UART01x_FR_DCD) 1437 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 1438 1439 if (delta & uap->vendor->fr_dsr) 1440 uap->port.icount.dsr++; 1441 1442 if (delta & uap->vendor->fr_cts) 1443 uart_handle_cts_change(&uap->port, 1444 status & uap->vendor->fr_cts); 1445 1446 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 1447 } 1448 1449 static void check_apply_cts_event_workaround(struct uart_amba_port *uap) 1450 { 1451 if (!uap->vendor->cts_event_workaround) 1452 return; 1453 1454 /* workaround to make sure that all bits are unlocked.. */ 1455 pl011_write(0x00, uap, REG_ICR); 1456 1457 /* 1458 * WA: introduce 26ns(1 uart clk) delay before W1C; 1459 * single apb access will incur 2 pclk(133.12Mhz) delay, 1460 * so add 2 dummy reads 1461 */ 1462 pl011_read(uap, REG_ICR); 1463 pl011_read(uap, REG_ICR); 1464 } 1465 1466 static irqreturn_t pl011_int(int irq, void *dev_id) 1467 { 1468 struct uart_amba_port *uap = dev_id; 1469 unsigned long flags; 1470 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 1471 int handled = 0; 1472 1473 spin_lock_irqsave(&uap->port.lock, flags); 1474 status = pl011_read(uap, REG_RIS) & uap->im; 1475 if (status) { 1476 do { 1477 check_apply_cts_event_workaround(uap); 1478 1479 pl011_write(status & ~(UART011_TXIS|UART011_RTIS| 1480 UART011_RXIS), 1481 uap, REG_ICR); 1482 1483 if (status & (UART011_RTIS|UART011_RXIS)) { 1484 if (pl011_dma_rx_running(uap)) 1485 pl011_dma_rx_irq(uap); 1486 else 1487 pl011_rx_chars(uap); 1488 } 1489 if (status & (UART011_DSRMIS|UART011_DCDMIS| 1490 UART011_CTSMIS|UART011_RIMIS)) 1491 pl011_modem_status(uap); 1492 if (status & UART011_TXIS) 1493 pl011_tx_chars(uap, true); 1494 1495 if (pass_counter-- == 0) 1496 break; 1497 1498 status = pl011_read(uap, REG_RIS) & uap->im; 1499 } while (status != 0); 1500 handled = 1; 1501 } 1502 1503 spin_unlock_irqrestore(&uap->port.lock, flags); 1504 1505 return IRQ_RETVAL(handled); 1506 } 1507 1508 static unsigned int pl011_tx_empty(struct uart_port *port) 1509 { 1510 struct uart_amba_port *uap = 1511 container_of(port, struct uart_amba_port, port); 1512 1513 /* Allow feature register bits to be inverted to work around errata */ 1514 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; 1515 1516 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? 1517 0 : TIOCSER_TEMT; 1518 } 1519 1520 static unsigned int pl011_get_mctrl(struct uart_port *port) 1521 { 1522 struct uart_amba_port *uap = 1523 container_of(port, struct uart_amba_port, port); 1524 unsigned int result = 0; 1525 unsigned int status = pl011_read(uap, REG_FR); 1526 1527 #define TIOCMBIT(uartbit, tiocmbit) \ 1528 if (status & uartbit) \ 1529 result |= tiocmbit 1530 1531 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); 1532 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR); 1533 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS); 1534 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG); 1535 #undef TIOCMBIT 1536 return result; 1537 } 1538 1539 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) 1540 { 1541 struct uart_amba_port *uap = 1542 container_of(port, struct uart_amba_port, port); 1543 unsigned int cr; 1544 1545 cr = pl011_read(uap, REG_CR); 1546 1547 #define TIOCMBIT(tiocmbit, uartbit) \ 1548 if (mctrl & tiocmbit) \ 1549 cr |= uartbit; \ 1550 else \ 1551 cr &= ~uartbit 1552 1553 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); 1554 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); 1555 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); 1556 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); 1557 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); 1558 1559 if (port->status & UPSTAT_AUTORTS) { 1560 /* We need to disable auto-RTS if we want to turn RTS off */ 1561 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); 1562 } 1563 #undef TIOCMBIT 1564 1565 pl011_write(cr, uap, REG_CR); 1566 } 1567 1568 static void pl011_break_ctl(struct uart_port *port, int break_state) 1569 { 1570 struct uart_amba_port *uap = 1571 container_of(port, struct uart_amba_port, port); 1572 unsigned long flags; 1573 unsigned int lcr_h; 1574 1575 spin_lock_irqsave(&uap->port.lock, flags); 1576 lcr_h = pl011_read(uap, REG_LCRH_TX); 1577 if (break_state == -1) 1578 lcr_h |= UART01x_LCRH_BRK; 1579 else 1580 lcr_h &= ~UART01x_LCRH_BRK; 1581 pl011_write(lcr_h, uap, REG_LCRH_TX); 1582 spin_unlock_irqrestore(&uap->port.lock, flags); 1583 } 1584 1585 #ifdef CONFIG_CONSOLE_POLL 1586 1587 static void pl011_quiesce_irqs(struct uart_port *port) 1588 { 1589 struct uart_amba_port *uap = 1590 container_of(port, struct uart_amba_port, port); 1591 1592 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); 1593 /* 1594 * There is no way to clear TXIM as this is "ready to transmit IRQ", so 1595 * we simply mask it. start_tx() will unmask it. 1596 * 1597 * Note we can race with start_tx(), and if the race happens, the 1598 * polling user might get another interrupt just after we clear it. 1599 * But it should be OK and can happen even w/o the race, e.g. 1600 * controller immediately got some new data and raised the IRQ. 1601 * 1602 * And whoever uses polling routines assumes that it manages the device 1603 * (including tx queue), so we're also fine with start_tx()'s caller 1604 * side. 1605 */ 1606 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, 1607 REG_IMSC); 1608 } 1609 1610 static int pl011_get_poll_char(struct uart_port *port) 1611 { 1612 struct uart_amba_port *uap = 1613 container_of(port, struct uart_amba_port, port); 1614 unsigned int status; 1615 1616 /* 1617 * The caller might need IRQs lowered, e.g. if used with KDB NMI 1618 * debugger. 1619 */ 1620 pl011_quiesce_irqs(port); 1621 1622 status = pl011_read(uap, REG_FR); 1623 if (status & UART01x_FR_RXFE) 1624 return NO_POLL_CHAR; 1625 1626 return pl011_read(uap, REG_DR); 1627 } 1628 1629 static void pl011_put_poll_char(struct uart_port *port, 1630 unsigned char ch) 1631 { 1632 struct uart_amba_port *uap = 1633 container_of(port, struct uart_amba_port, port); 1634 1635 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1636 cpu_relax(); 1637 1638 pl011_write(ch, uap, REG_DR); 1639 } 1640 1641 #endif /* CONFIG_CONSOLE_POLL */ 1642 1643 static int pl011_hwinit(struct uart_port *port) 1644 { 1645 struct uart_amba_port *uap = 1646 container_of(port, struct uart_amba_port, port); 1647 int retval; 1648 1649 /* Optionaly enable pins to be muxed in and configured */ 1650 pinctrl_pm_select_default_state(port->dev); 1651 1652 /* 1653 * Try to enable the clock producer. 1654 */ 1655 retval = clk_prepare_enable(uap->clk); 1656 if (retval) 1657 return retval; 1658 1659 uap->port.uartclk = clk_get_rate(uap->clk); 1660 1661 /* Clear pending error and receive interrupts */ 1662 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 1663 UART011_FEIS | UART011_RTIS | UART011_RXIS, 1664 uap, REG_ICR); 1665 1666 /* 1667 * Save interrupts enable mask, and enable RX interrupts in case if 1668 * the interrupt is used for NMI entry. 1669 */ 1670 uap->im = pl011_read(uap, REG_IMSC); 1671 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); 1672 1673 if (dev_get_platdata(uap->port.dev)) { 1674 struct amba_pl011_data *plat; 1675 1676 plat = dev_get_platdata(uap->port.dev); 1677 if (plat->init) 1678 plat->init(); 1679 } 1680 return 0; 1681 } 1682 1683 static bool pl011_split_lcrh(const struct uart_amba_port *uap) 1684 { 1685 return pl011_reg_to_offset(uap, REG_LCRH_RX) != 1686 pl011_reg_to_offset(uap, REG_LCRH_TX); 1687 } 1688 1689 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) 1690 { 1691 pl011_write(lcr_h, uap, REG_LCRH_RX); 1692 if (pl011_split_lcrh(uap)) { 1693 int i; 1694 /* 1695 * Wait 10 PCLKs before writing LCRH_TX register, 1696 * to get this delay write read only register 10 times 1697 */ 1698 for (i = 0; i < 10; ++i) 1699 pl011_write(0xff, uap, REG_MIS); 1700 pl011_write(lcr_h, uap, REG_LCRH_TX); 1701 } 1702 } 1703 1704 static int pl011_allocate_irq(struct uart_amba_port *uap) 1705 { 1706 pl011_write(uap->im, uap, REG_IMSC); 1707 1708 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); 1709 } 1710 1711 /* 1712 * Enable interrupts, only timeouts when using DMA 1713 * if initial RX DMA job failed, start in interrupt mode 1714 * as well. 1715 */ 1716 static void pl011_enable_interrupts(struct uart_amba_port *uap) 1717 { 1718 unsigned int i; 1719 1720 spin_lock_irq(&uap->port.lock); 1721 1722 /* Clear out any spuriously appearing RX interrupts */ 1723 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); 1724 1725 /* 1726 * RXIS is asserted only when the RX FIFO transitions from below 1727 * to above the trigger threshold. If the RX FIFO is already 1728 * full to the threshold this can't happen and RXIS will now be 1729 * stuck off. Drain the RX FIFO explicitly to fix this: 1730 */ 1731 for (i = 0; i < uap->fifosize * 2; ++i) { 1732 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE) 1733 break; 1734 1735 pl011_read(uap, REG_DR); 1736 } 1737 1738 uap->im = UART011_RTIM; 1739 if (!pl011_dma_rx_running(uap)) 1740 uap->im |= UART011_RXIM; 1741 pl011_write(uap->im, uap, REG_IMSC); 1742 spin_unlock_irq(&uap->port.lock); 1743 } 1744 1745 static int pl011_startup(struct uart_port *port) 1746 { 1747 struct uart_amba_port *uap = 1748 container_of(port, struct uart_amba_port, port); 1749 unsigned int cr; 1750 int retval; 1751 1752 retval = pl011_hwinit(port); 1753 if (retval) 1754 goto clk_dis; 1755 1756 retval = pl011_allocate_irq(uap); 1757 if (retval) 1758 goto clk_dis; 1759 1760 pl011_write(uap->vendor->ifls, uap, REG_IFLS); 1761 1762 spin_lock_irq(&uap->port.lock); 1763 1764 /* restore RTS and DTR */ 1765 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); 1766 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; 1767 pl011_write(cr, uap, REG_CR); 1768 1769 spin_unlock_irq(&uap->port.lock); 1770 1771 /* 1772 * initialise the old status of the modem signals 1773 */ 1774 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1775 1776 /* Startup DMA */ 1777 pl011_dma_startup(uap); 1778 1779 pl011_enable_interrupts(uap); 1780 1781 return 0; 1782 1783 clk_dis: 1784 clk_disable_unprepare(uap->clk); 1785 return retval; 1786 } 1787 1788 static int sbsa_uart_startup(struct uart_port *port) 1789 { 1790 struct uart_amba_port *uap = 1791 container_of(port, struct uart_amba_port, port); 1792 int retval; 1793 1794 retval = pl011_hwinit(port); 1795 if (retval) 1796 return retval; 1797 1798 retval = pl011_allocate_irq(uap); 1799 if (retval) 1800 return retval; 1801 1802 /* The SBSA UART does not support any modem status lines. */ 1803 uap->old_status = 0; 1804 1805 pl011_enable_interrupts(uap); 1806 1807 return 0; 1808 } 1809 1810 static void pl011_shutdown_channel(struct uart_amba_port *uap, 1811 unsigned int lcrh) 1812 { 1813 unsigned long val; 1814 1815 val = pl011_read(uap, lcrh); 1816 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); 1817 pl011_write(val, uap, lcrh); 1818 } 1819 1820 /* 1821 * disable the port. It should not disable RTS and DTR. 1822 * Also RTS and DTR state should be preserved to restore 1823 * it during startup(). 1824 */ 1825 static void pl011_disable_uart(struct uart_amba_port *uap) 1826 { 1827 unsigned int cr; 1828 1829 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1830 spin_lock_irq(&uap->port.lock); 1831 cr = pl011_read(uap, REG_CR); 1832 uap->old_cr = cr; 1833 cr &= UART011_CR_RTS | UART011_CR_DTR; 1834 cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 1835 pl011_write(cr, uap, REG_CR); 1836 spin_unlock_irq(&uap->port.lock); 1837 1838 /* 1839 * disable break condition and fifos 1840 */ 1841 pl011_shutdown_channel(uap, REG_LCRH_RX); 1842 if (pl011_split_lcrh(uap)) 1843 pl011_shutdown_channel(uap, REG_LCRH_TX); 1844 } 1845 1846 static void pl011_disable_interrupts(struct uart_amba_port *uap) 1847 { 1848 spin_lock_irq(&uap->port.lock); 1849 1850 /* mask all interrupts and clear all pending ones */ 1851 uap->im = 0; 1852 pl011_write(uap->im, uap, REG_IMSC); 1853 pl011_write(0xffff, uap, REG_ICR); 1854 1855 spin_unlock_irq(&uap->port.lock); 1856 } 1857 1858 static void pl011_shutdown(struct uart_port *port) 1859 { 1860 struct uart_amba_port *uap = 1861 container_of(port, struct uart_amba_port, port); 1862 1863 pl011_disable_interrupts(uap); 1864 1865 pl011_dma_shutdown(uap); 1866 1867 free_irq(uap->port.irq, uap); 1868 1869 pl011_disable_uart(uap); 1870 1871 /* 1872 * Shut down the clock producer 1873 */ 1874 clk_disable_unprepare(uap->clk); 1875 /* Optionally let pins go into sleep states */ 1876 pinctrl_pm_select_sleep_state(port->dev); 1877 1878 if (dev_get_platdata(uap->port.dev)) { 1879 struct amba_pl011_data *plat; 1880 1881 plat = dev_get_platdata(uap->port.dev); 1882 if (plat->exit) 1883 plat->exit(); 1884 } 1885 1886 if (uap->port.ops->flush_buffer) 1887 uap->port.ops->flush_buffer(port); 1888 } 1889 1890 static void sbsa_uart_shutdown(struct uart_port *port) 1891 { 1892 struct uart_amba_port *uap = 1893 container_of(port, struct uart_amba_port, port); 1894 1895 pl011_disable_interrupts(uap); 1896 1897 free_irq(uap->port.irq, uap); 1898 1899 if (uap->port.ops->flush_buffer) 1900 uap->port.ops->flush_buffer(port); 1901 } 1902 1903 static void 1904 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) 1905 { 1906 port->read_status_mask = UART011_DR_OE | 255; 1907 if (termios->c_iflag & INPCK) 1908 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; 1909 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1910 port->read_status_mask |= UART011_DR_BE; 1911 1912 /* 1913 * Characters to ignore 1914 */ 1915 port->ignore_status_mask = 0; 1916 if (termios->c_iflag & IGNPAR) 1917 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; 1918 if (termios->c_iflag & IGNBRK) { 1919 port->ignore_status_mask |= UART011_DR_BE; 1920 /* 1921 * If we're ignoring parity and break indicators, 1922 * ignore overruns too (for real raw support). 1923 */ 1924 if (termios->c_iflag & IGNPAR) 1925 port->ignore_status_mask |= UART011_DR_OE; 1926 } 1927 1928 /* 1929 * Ignore all characters if CREAD is not set. 1930 */ 1931 if ((termios->c_cflag & CREAD) == 0) 1932 port->ignore_status_mask |= UART_DUMMY_DR_RX; 1933 } 1934 1935 static void 1936 pl011_set_termios(struct uart_port *port, struct ktermios *termios, 1937 struct ktermios *old) 1938 { 1939 struct uart_amba_port *uap = 1940 container_of(port, struct uart_amba_port, port); 1941 unsigned int lcr_h, old_cr; 1942 unsigned long flags; 1943 unsigned int baud, quot, clkdiv; 1944 1945 if (uap->vendor->oversampling) 1946 clkdiv = 8; 1947 else 1948 clkdiv = 16; 1949 1950 /* 1951 * Ask the core to calculate the divisor for us. 1952 */ 1953 baud = uart_get_baud_rate(port, termios, old, 0, 1954 port->uartclk / clkdiv); 1955 #ifdef CONFIG_DMA_ENGINE 1956 /* 1957 * Adjust RX DMA polling rate with baud rate if not specified. 1958 */ 1959 if (uap->dmarx.auto_poll_rate) 1960 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); 1961 #endif 1962 1963 if (baud > port->uartclk/16) 1964 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); 1965 else 1966 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); 1967 1968 switch (termios->c_cflag & CSIZE) { 1969 case CS5: 1970 lcr_h = UART01x_LCRH_WLEN_5; 1971 break; 1972 case CS6: 1973 lcr_h = UART01x_LCRH_WLEN_6; 1974 break; 1975 case CS7: 1976 lcr_h = UART01x_LCRH_WLEN_7; 1977 break; 1978 default: // CS8 1979 lcr_h = UART01x_LCRH_WLEN_8; 1980 break; 1981 } 1982 if (termios->c_cflag & CSTOPB) 1983 lcr_h |= UART01x_LCRH_STP2; 1984 if (termios->c_cflag & PARENB) { 1985 lcr_h |= UART01x_LCRH_PEN; 1986 if (!(termios->c_cflag & PARODD)) 1987 lcr_h |= UART01x_LCRH_EPS; 1988 if (termios->c_cflag & CMSPAR) 1989 lcr_h |= UART011_LCRH_SPS; 1990 } 1991 if (uap->fifosize > 1) 1992 lcr_h |= UART01x_LCRH_FEN; 1993 1994 spin_lock_irqsave(&port->lock, flags); 1995 1996 /* 1997 * Update the per-port timeout. 1998 */ 1999 uart_update_timeout(port, termios->c_cflag, baud); 2000 2001 pl011_setup_status_masks(port, termios); 2002 2003 if (UART_ENABLE_MS(port, termios->c_cflag)) 2004 pl011_enable_ms(port); 2005 2006 /* first, disable everything */ 2007 old_cr = pl011_read(uap, REG_CR); 2008 pl011_write(0, uap, REG_CR); 2009 2010 if (termios->c_cflag & CRTSCTS) { 2011 if (old_cr & UART011_CR_RTS) 2012 old_cr |= UART011_CR_RTSEN; 2013 2014 old_cr |= UART011_CR_CTSEN; 2015 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 2016 } else { 2017 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); 2018 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 2019 } 2020 2021 if (uap->vendor->oversampling) { 2022 if (baud > port->uartclk / 16) 2023 old_cr |= ST_UART011_CR_OVSFACT; 2024 else 2025 old_cr &= ~ST_UART011_CR_OVSFACT; 2026 } 2027 2028 /* 2029 * Workaround for the ST Micro oversampling variants to 2030 * increase the bitrate slightly, by lowering the divisor, 2031 * to avoid delayed sampling of start bit at high speeds, 2032 * else we see data corruption. 2033 */ 2034 if (uap->vendor->oversampling) { 2035 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) 2036 quot -= 1; 2037 else if ((baud > 3250000) && (quot > 2)) 2038 quot -= 2; 2039 } 2040 /* Set baud rate */ 2041 pl011_write(quot & 0x3f, uap, REG_FBRD); 2042 pl011_write(quot >> 6, uap, REG_IBRD); 2043 2044 /* 2045 * ----------v----------v----------v----------v----- 2046 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER 2047 * REG_FBRD & REG_IBRD. 2048 * ----------^----------^----------^----------^----- 2049 */ 2050 pl011_write_lcr_h(uap, lcr_h); 2051 pl011_write(old_cr, uap, REG_CR); 2052 2053 spin_unlock_irqrestore(&port->lock, flags); 2054 } 2055 2056 static void 2057 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, 2058 struct ktermios *old) 2059 { 2060 struct uart_amba_port *uap = 2061 container_of(port, struct uart_amba_port, port); 2062 unsigned long flags; 2063 2064 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); 2065 2066 /* The SBSA UART only supports 8n1 without hardware flow control. */ 2067 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 2068 termios->c_cflag &= ~(CMSPAR | CRTSCTS); 2069 termios->c_cflag |= CS8 | CLOCAL; 2070 2071 spin_lock_irqsave(&port->lock, flags); 2072 uart_update_timeout(port, CS8, uap->fixed_baud); 2073 pl011_setup_status_masks(port, termios); 2074 spin_unlock_irqrestore(&port->lock, flags); 2075 } 2076 2077 static const char *pl011_type(struct uart_port *port) 2078 { 2079 struct uart_amba_port *uap = 2080 container_of(port, struct uart_amba_port, port); 2081 return uap->port.type == PORT_AMBA ? uap->type : NULL; 2082 } 2083 2084 /* 2085 * Release the memory region(s) being used by 'port' 2086 */ 2087 static void pl011_release_port(struct uart_port *port) 2088 { 2089 release_mem_region(port->mapbase, SZ_4K); 2090 } 2091 2092 /* 2093 * Request the memory region(s) being used by 'port' 2094 */ 2095 static int pl011_request_port(struct uart_port *port) 2096 { 2097 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") 2098 != NULL ? 0 : -EBUSY; 2099 } 2100 2101 /* 2102 * Configure/autoconfigure the port. 2103 */ 2104 static void pl011_config_port(struct uart_port *port, int flags) 2105 { 2106 if (flags & UART_CONFIG_TYPE) { 2107 port->type = PORT_AMBA; 2108 pl011_request_port(port); 2109 } 2110 } 2111 2112 /* 2113 * verify the new serial_struct (for TIOCSSERIAL). 2114 */ 2115 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) 2116 { 2117 int ret = 0; 2118 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 2119 ret = -EINVAL; 2120 if (ser->irq < 0 || ser->irq >= nr_irqs) 2121 ret = -EINVAL; 2122 if (ser->baud_base < 9600) 2123 ret = -EINVAL; 2124 return ret; 2125 } 2126 2127 static const struct uart_ops amba_pl011_pops = { 2128 .tx_empty = pl011_tx_empty, 2129 .set_mctrl = pl011_set_mctrl, 2130 .get_mctrl = pl011_get_mctrl, 2131 .stop_tx = pl011_stop_tx, 2132 .start_tx = pl011_start_tx, 2133 .stop_rx = pl011_stop_rx, 2134 .enable_ms = pl011_enable_ms, 2135 .break_ctl = pl011_break_ctl, 2136 .startup = pl011_startup, 2137 .shutdown = pl011_shutdown, 2138 .flush_buffer = pl011_dma_flush_buffer, 2139 .set_termios = pl011_set_termios, 2140 .type = pl011_type, 2141 .release_port = pl011_release_port, 2142 .request_port = pl011_request_port, 2143 .config_port = pl011_config_port, 2144 .verify_port = pl011_verify_port, 2145 #ifdef CONFIG_CONSOLE_POLL 2146 .poll_init = pl011_hwinit, 2147 .poll_get_char = pl011_get_poll_char, 2148 .poll_put_char = pl011_put_poll_char, 2149 #endif 2150 }; 2151 2152 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 2153 { 2154 } 2155 2156 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) 2157 { 2158 return 0; 2159 } 2160 2161 static const struct uart_ops sbsa_uart_pops = { 2162 .tx_empty = pl011_tx_empty, 2163 .set_mctrl = sbsa_uart_set_mctrl, 2164 .get_mctrl = sbsa_uart_get_mctrl, 2165 .stop_tx = pl011_stop_tx, 2166 .start_tx = pl011_start_tx, 2167 .stop_rx = pl011_stop_rx, 2168 .startup = sbsa_uart_startup, 2169 .shutdown = sbsa_uart_shutdown, 2170 .set_termios = sbsa_uart_set_termios, 2171 .type = pl011_type, 2172 .release_port = pl011_release_port, 2173 .request_port = pl011_request_port, 2174 .config_port = pl011_config_port, 2175 .verify_port = pl011_verify_port, 2176 #ifdef CONFIG_CONSOLE_POLL 2177 .poll_init = pl011_hwinit, 2178 .poll_get_char = pl011_get_poll_char, 2179 .poll_put_char = pl011_put_poll_char, 2180 #endif 2181 }; 2182 2183 static struct uart_amba_port *amba_ports[UART_NR]; 2184 2185 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE 2186 2187 static void pl011_console_putchar(struct uart_port *port, int ch) 2188 { 2189 struct uart_amba_port *uap = 2190 container_of(port, struct uart_amba_port, port); 2191 2192 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 2193 cpu_relax(); 2194 pl011_write(ch, uap, REG_DR); 2195 } 2196 2197 static void 2198 pl011_console_write(struct console *co, const char *s, unsigned int count) 2199 { 2200 struct uart_amba_port *uap = amba_ports[co->index]; 2201 unsigned int old_cr = 0, new_cr; 2202 unsigned long flags; 2203 int locked = 1; 2204 2205 clk_enable(uap->clk); 2206 2207 local_irq_save(flags); 2208 if (uap->port.sysrq) 2209 locked = 0; 2210 else if (oops_in_progress) 2211 locked = spin_trylock(&uap->port.lock); 2212 else 2213 spin_lock(&uap->port.lock); 2214 2215 /* 2216 * First save the CR then disable the interrupts 2217 */ 2218 if (!uap->vendor->always_enabled) { 2219 old_cr = pl011_read(uap, REG_CR); 2220 new_cr = old_cr & ~UART011_CR_CTSEN; 2221 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 2222 pl011_write(new_cr, uap, REG_CR); 2223 } 2224 2225 uart_console_write(&uap->port, s, count, pl011_console_putchar); 2226 2227 /* 2228 * Finally, wait for transmitter to become empty and restore the 2229 * TCR. Allow feature register bits to be inverted to work around 2230 * errata. 2231 */ 2232 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) 2233 & uap->vendor->fr_busy) 2234 cpu_relax(); 2235 if (!uap->vendor->always_enabled) 2236 pl011_write(old_cr, uap, REG_CR); 2237 2238 if (locked) 2239 spin_unlock(&uap->port.lock); 2240 local_irq_restore(flags); 2241 2242 clk_disable(uap->clk); 2243 } 2244 2245 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud, 2246 int *parity, int *bits) 2247 { 2248 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) { 2249 unsigned int lcr_h, ibrd, fbrd; 2250 2251 lcr_h = pl011_read(uap, REG_LCRH_TX); 2252 2253 *parity = 'n'; 2254 if (lcr_h & UART01x_LCRH_PEN) { 2255 if (lcr_h & UART01x_LCRH_EPS) 2256 *parity = 'e'; 2257 else 2258 *parity = 'o'; 2259 } 2260 2261 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 2262 *bits = 7; 2263 else 2264 *bits = 8; 2265 2266 ibrd = pl011_read(uap, REG_IBRD); 2267 fbrd = pl011_read(uap, REG_FBRD); 2268 2269 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); 2270 2271 if (uap->vendor->oversampling) { 2272 if (pl011_read(uap, REG_CR) 2273 & ST_UART011_CR_OVSFACT) 2274 *baud *= 2; 2275 } 2276 } 2277 } 2278 2279 static int pl011_console_setup(struct console *co, char *options) 2280 { 2281 struct uart_amba_port *uap; 2282 int baud = 38400; 2283 int bits = 8; 2284 int parity = 'n'; 2285 int flow = 'n'; 2286 int ret; 2287 2288 /* 2289 * Check whether an invalid uart number has been specified, and 2290 * if so, search for the first available port that does have 2291 * console support. 2292 */ 2293 if (co->index >= UART_NR) 2294 co->index = 0; 2295 uap = amba_ports[co->index]; 2296 if (!uap) 2297 return -ENODEV; 2298 2299 /* Allow pins to be muxed in and configured */ 2300 pinctrl_pm_select_default_state(uap->port.dev); 2301 2302 ret = clk_prepare(uap->clk); 2303 if (ret) 2304 return ret; 2305 2306 if (dev_get_platdata(uap->port.dev)) { 2307 struct amba_pl011_data *plat; 2308 2309 plat = dev_get_platdata(uap->port.dev); 2310 if (plat->init) 2311 plat->init(); 2312 } 2313 2314 uap->port.uartclk = clk_get_rate(uap->clk); 2315 2316 if (uap->vendor->fixed_options) { 2317 baud = uap->fixed_baud; 2318 } else { 2319 if (options) 2320 uart_parse_options(options, 2321 &baud, &parity, &bits, &flow); 2322 else 2323 pl011_console_get_options(uap, &baud, &parity, &bits); 2324 } 2325 2326 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 2327 } 2328 2329 /** 2330 * pl011_console_match - non-standard console matching 2331 * @co: registering console 2332 * @name: name from console command line 2333 * @idx: index from console command line 2334 * @options: ptr to option string from console command line 2335 * 2336 * Only attempts to match console command lines of the form: 2337 * console=pl011,mmio|mmio32,<addr>[,<options>] 2338 * console=pl011,0x<addr>[,<options>] 2339 * This form is used to register an initial earlycon boot console and 2340 * replace it with the amba_console at pl011 driver init. 2341 * 2342 * Performs console setup for a match (as required by interface) 2343 * If no <options> are specified, then assume the h/w is already setup. 2344 * 2345 * Returns 0 if console matches; otherwise non-zero to use default matching 2346 */ 2347 static int pl011_console_match(struct console *co, char *name, int idx, 2348 char *options) 2349 { 2350 unsigned char iotype; 2351 resource_size_t addr; 2352 int i; 2353 2354 /* 2355 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum 2356 * have a distinct console name, so make sure we check for that. 2357 * The actual implementation of the erratum occurs in the probe 2358 * function. 2359 */ 2360 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0)) 2361 return -ENODEV; 2362 2363 if (uart_parse_earlycon(options, &iotype, &addr, &options)) 2364 return -ENODEV; 2365 2366 if (iotype != UPIO_MEM && iotype != UPIO_MEM32) 2367 return -ENODEV; 2368 2369 /* try to match the port specified on the command line */ 2370 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2371 struct uart_port *port; 2372 2373 if (!amba_ports[i]) 2374 continue; 2375 2376 port = &amba_ports[i]->port; 2377 2378 if (port->mapbase != addr) 2379 continue; 2380 2381 co->index = i; 2382 port->cons = co; 2383 return pl011_console_setup(co, options); 2384 } 2385 2386 return -ENODEV; 2387 } 2388 2389 static struct uart_driver amba_reg; 2390 static struct console amba_console = { 2391 .name = "ttyAMA", 2392 .write = pl011_console_write, 2393 .device = uart_console_device, 2394 .setup = pl011_console_setup, 2395 .match = pl011_console_match, 2396 .flags = CON_PRINTBUFFER | CON_ANYTIME, 2397 .index = -1, 2398 .data = &amba_reg, 2399 }; 2400 2401 #define AMBA_CONSOLE (&amba_console) 2402 2403 static void qdf2400_e44_putc(struct uart_port *port, int c) 2404 { 2405 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2406 cpu_relax(); 2407 writel(c, port->membase + UART01x_DR); 2408 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) 2409 cpu_relax(); 2410 } 2411 2412 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n) 2413 { 2414 struct earlycon_device *dev = con->data; 2415 2416 uart_console_write(&dev->port, s, n, qdf2400_e44_putc); 2417 } 2418 2419 static void pl011_putc(struct uart_port *port, int c) 2420 { 2421 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2422 cpu_relax(); 2423 if (port->iotype == UPIO_MEM32) 2424 writel(c, port->membase + UART01x_DR); 2425 else 2426 writeb(c, port->membase + UART01x_DR); 2427 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) 2428 cpu_relax(); 2429 } 2430 2431 static void pl011_early_write(struct console *con, const char *s, unsigned n) 2432 { 2433 struct earlycon_device *dev = con->data; 2434 2435 uart_console_write(&dev->port, s, n, pl011_putc); 2436 } 2437 2438 #ifdef CONFIG_CONSOLE_POLL 2439 static int pl011_getc(struct uart_port *port) 2440 { 2441 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE) 2442 return NO_POLL_CHAR; 2443 2444 if (port->iotype == UPIO_MEM32) 2445 return readl(port->membase + UART01x_DR); 2446 else 2447 return readb(port->membase + UART01x_DR); 2448 } 2449 2450 static int pl011_early_read(struct console *con, char *s, unsigned int n) 2451 { 2452 struct earlycon_device *dev = con->data; 2453 int ch, num_read = 0; 2454 2455 while (num_read < n) { 2456 ch = pl011_getc(&dev->port); 2457 if (ch == NO_POLL_CHAR) 2458 break; 2459 2460 s[num_read++] = ch; 2461 } 2462 2463 return num_read; 2464 } 2465 #else 2466 #define pl011_early_read NULL 2467 #endif 2468 2469 /* 2470 * On non-ACPI systems, earlycon is enabled by specifying 2471 * "earlycon=pl011,<address>" on the kernel command line. 2472 * 2473 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table, 2474 * by specifying only "earlycon" on the command line. Because it requires 2475 * SPCR, the console starts after ACPI is parsed, which is later than a 2476 * traditional early console. 2477 * 2478 * To get the traditional early console that starts before ACPI is parsed, 2479 * specify the full "earlycon=pl011,<address>" option. 2480 */ 2481 static int __init pl011_early_console_setup(struct earlycon_device *device, 2482 const char *opt) 2483 { 2484 if (!device->port.membase) 2485 return -ENODEV; 2486 2487 device->con->write = pl011_early_write; 2488 device->con->read = pl011_early_read; 2489 2490 return 0; 2491 } 2492 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); 2493 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup); 2494 2495 /* 2496 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by 2497 * Erratum 44, traditional earlycon can be enabled by specifying 2498 * "earlycon=qdf2400_e44,<address>". Any options are ignored. 2499 * 2500 * Alternatively, you can just specify "earlycon", and the early console 2501 * will be enabled with the information from the SPCR table. In this 2502 * case, the SPCR code will detect the need for the E44 work-around, 2503 * and set the console name to "qdf2400_e44". 2504 */ 2505 static int __init 2506 qdf2400_e44_early_console_setup(struct earlycon_device *device, 2507 const char *opt) 2508 { 2509 if (!device->port.membase) 2510 return -ENODEV; 2511 2512 device->con->write = qdf2400_e44_early_write; 2513 return 0; 2514 } 2515 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup); 2516 2517 #else 2518 #define AMBA_CONSOLE NULL 2519 #endif 2520 2521 static struct uart_driver amba_reg = { 2522 .owner = THIS_MODULE, 2523 .driver_name = "ttyAMA", 2524 .dev_name = "ttyAMA", 2525 .major = SERIAL_AMBA_MAJOR, 2526 .minor = SERIAL_AMBA_MINOR, 2527 .nr = UART_NR, 2528 .cons = AMBA_CONSOLE, 2529 }; 2530 2531 static int pl011_probe_dt_alias(int index, struct device *dev) 2532 { 2533 struct device_node *np; 2534 static bool seen_dev_with_alias = false; 2535 static bool seen_dev_without_alias = false; 2536 int ret = index; 2537 2538 if (!IS_ENABLED(CONFIG_OF)) 2539 return ret; 2540 2541 np = dev->of_node; 2542 if (!np) 2543 return ret; 2544 2545 ret = of_alias_get_id(np, "serial"); 2546 if (ret < 0) { 2547 seen_dev_without_alias = true; 2548 ret = index; 2549 } else { 2550 seen_dev_with_alias = true; 2551 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { 2552 dev_warn(dev, "requested serial port %d not available.\n", ret); 2553 ret = index; 2554 } 2555 } 2556 2557 if (seen_dev_with_alias && seen_dev_without_alias) 2558 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); 2559 2560 return ret; 2561 } 2562 2563 /* unregisters the driver also if no more ports are left */ 2564 static void pl011_unregister_port(struct uart_amba_port *uap) 2565 { 2566 int i; 2567 bool busy = false; 2568 2569 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2570 if (amba_ports[i] == uap) 2571 amba_ports[i] = NULL; 2572 else if (amba_ports[i]) 2573 busy = true; 2574 } 2575 pl011_dma_remove(uap); 2576 if (!busy) 2577 uart_unregister_driver(&amba_reg); 2578 } 2579 2580 static int pl011_find_free_port(void) 2581 { 2582 int i; 2583 2584 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2585 if (amba_ports[i] == NULL) 2586 return i; 2587 2588 return -EBUSY; 2589 } 2590 2591 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, 2592 struct resource *mmiobase, int index) 2593 { 2594 void __iomem *base; 2595 2596 base = devm_ioremap_resource(dev, mmiobase); 2597 if (IS_ERR(base)) 2598 return PTR_ERR(base); 2599 2600 index = pl011_probe_dt_alias(index, dev); 2601 2602 uap->old_cr = 0; 2603 uap->port.dev = dev; 2604 uap->port.mapbase = mmiobase->start; 2605 uap->port.membase = base; 2606 uap->port.fifosize = uap->fifosize; 2607 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE); 2608 uap->port.flags = UPF_BOOT_AUTOCONF; 2609 uap->port.line = index; 2610 2611 amba_ports[index] = uap; 2612 2613 return 0; 2614 } 2615 2616 static int pl011_register_port(struct uart_amba_port *uap) 2617 { 2618 int ret, i; 2619 2620 /* Ensure interrupts from this UART are masked and cleared */ 2621 pl011_write(0, uap, REG_IMSC); 2622 pl011_write(0xffff, uap, REG_ICR); 2623 2624 if (!amba_reg.state) { 2625 ret = uart_register_driver(&amba_reg); 2626 if (ret < 0) { 2627 dev_err(uap->port.dev, 2628 "Failed to register AMBA-PL011 driver\n"); 2629 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2630 if (amba_ports[i] == uap) 2631 amba_ports[i] = NULL; 2632 return ret; 2633 } 2634 } 2635 2636 ret = uart_add_one_port(&amba_reg, &uap->port); 2637 if (ret) 2638 pl011_unregister_port(uap); 2639 2640 return ret; 2641 } 2642 2643 static int pl011_probe(struct amba_device *dev, const struct amba_id *id) 2644 { 2645 struct uart_amba_port *uap; 2646 struct vendor_data *vendor = id->data; 2647 int portnr, ret; 2648 2649 portnr = pl011_find_free_port(); 2650 if (portnr < 0) 2651 return portnr; 2652 2653 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), 2654 GFP_KERNEL); 2655 if (!uap) 2656 return -ENOMEM; 2657 2658 uap->clk = devm_clk_get(&dev->dev, NULL); 2659 if (IS_ERR(uap->clk)) 2660 return PTR_ERR(uap->clk); 2661 2662 uap->reg_offset = vendor->reg_offset; 2663 uap->vendor = vendor; 2664 uap->fifosize = vendor->get_fifosize(dev); 2665 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 2666 uap->port.irq = dev->irq[0]; 2667 uap->port.ops = &amba_pl011_pops; 2668 2669 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); 2670 2671 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); 2672 if (ret) 2673 return ret; 2674 2675 amba_set_drvdata(dev, uap); 2676 2677 return pl011_register_port(uap); 2678 } 2679 2680 static void pl011_remove(struct amba_device *dev) 2681 { 2682 struct uart_amba_port *uap = amba_get_drvdata(dev); 2683 2684 uart_remove_one_port(&amba_reg, &uap->port); 2685 pl011_unregister_port(uap); 2686 } 2687 2688 #ifdef CONFIG_PM_SLEEP 2689 static int pl011_suspend(struct device *dev) 2690 { 2691 struct uart_amba_port *uap = dev_get_drvdata(dev); 2692 2693 if (!uap) 2694 return -EINVAL; 2695 2696 return uart_suspend_port(&amba_reg, &uap->port); 2697 } 2698 2699 static int pl011_resume(struct device *dev) 2700 { 2701 struct uart_amba_port *uap = dev_get_drvdata(dev); 2702 2703 if (!uap) 2704 return -EINVAL; 2705 2706 return uart_resume_port(&amba_reg, &uap->port); 2707 } 2708 #endif 2709 2710 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); 2711 2712 static int sbsa_uart_probe(struct platform_device *pdev) 2713 { 2714 struct uart_amba_port *uap; 2715 struct resource *r; 2716 int portnr, ret; 2717 int baudrate; 2718 2719 /* 2720 * Check the mandatory baud rate parameter in the DT node early 2721 * so that we can easily exit with the error. 2722 */ 2723 if (pdev->dev.of_node) { 2724 struct device_node *np = pdev->dev.of_node; 2725 2726 ret = of_property_read_u32(np, "current-speed", &baudrate); 2727 if (ret) 2728 return ret; 2729 } else { 2730 baudrate = 115200; 2731 } 2732 2733 portnr = pl011_find_free_port(); 2734 if (portnr < 0) 2735 return portnr; 2736 2737 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), 2738 GFP_KERNEL); 2739 if (!uap) 2740 return -ENOMEM; 2741 2742 ret = platform_get_irq(pdev, 0); 2743 if (ret < 0) 2744 return ret; 2745 uap->port.irq = ret; 2746 2747 #ifdef CONFIG_ACPI_SPCR_TABLE 2748 if (qdf2400_e44_present) { 2749 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n"); 2750 uap->vendor = &vendor_qdt_qdf2400_e44; 2751 } else 2752 #endif 2753 uap->vendor = &vendor_sbsa; 2754 2755 uap->reg_offset = uap->vendor->reg_offset; 2756 uap->fifosize = 32; 2757 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 2758 uap->port.ops = &sbsa_uart_pops; 2759 uap->fixed_baud = baudrate; 2760 2761 snprintf(uap->type, sizeof(uap->type), "SBSA"); 2762 2763 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2764 2765 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); 2766 if (ret) 2767 return ret; 2768 2769 platform_set_drvdata(pdev, uap); 2770 2771 return pl011_register_port(uap); 2772 } 2773 2774 static int sbsa_uart_remove(struct platform_device *pdev) 2775 { 2776 struct uart_amba_port *uap = platform_get_drvdata(pdev); 2777 2778 uart_remove_one_port(&amba_reg, &uap->port); 2779 pl011_unregister_port(uap); 2780 return 0; 2781 } 2782 2783 static const struct of_device_id sbsa_uart_of_match[] = { 2784 { .compatible = "arm,sbsa-uart", }, 2785 {}, 2786 }; 2787 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); 2788 2789 static const struct acpi_device_id __maybe_unused sbsa_uart_acpi_match[] = { 2790 { "ARMH0011", 0 }, 2791 {}, 2792 }; 2793 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); 2794 2795 static struct platform_driver arm_sbsa_uart_platform_driver = { 2796 .probe = sbsa_uart_probe, 2797 .remove = sbsa_uart_remove, 2798 .driver = { 2799 .name = "sbsa-uart", 2800 .pm = &pl011_dev_pm_ops, 2801 .of_match_table = of_match_ptr(sbsa_uart_of_match), 2802 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match), 2803 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), 2804 }, 2805 }; 2806 2807 static const struct amba_id pl011_ids[] = { 2808 { 2809 .id = 0x00041011, 2810 .mask = 0x000fffff, 2811 .data = &vendor_arm, 2812 }, 2813 { 2814 .id = 0x00380802, 2815 .mask = 0x00ffffff, 2816 .data = &vendor_st, 2817 }, 2818 { 2819 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe), 2820 .mask = 0x00ffffff, 2821 .data = &vendor_zte, 2822 }, 2823 { 0, 0 }, 2824 }; 2825 2826 MODULE_DEVICE_TABLE(amba, pl011_ids); 2827 2828 static struct amba_driver pl011_driver = { 2829 .drv = { 2830 .name = "uart-pl011", 2831 .pm = &pl011_dev_pm_ops, 2832 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), 2833 }, 2834 .id_table = pl011_ids, 2835 .probe = pl011_probe, 2836 .remove = pl011_remove, 2837 }; 2838 2839 static int __init pl011_init(void) 2840 { 2841 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); 2842 2843 if (platform_driver_register(&arm_sbsa_uart_platform_driver)) 2844 pr_warn("could not register SBSA UART platform driver\n"); 2845 return amba_driver_register(&pl011_driver); 2846 } 2847 2848 static void __exit pl011_exit(void) 2849 { 2850 platform_driver_unregister(&arm_sbsa_uart_platform_driver); 2851 amba_driver_unregister(&pl011_driver); 2852 } 2853 2854 /* 2855 * While this can be a module, if builtin it's most likely the console 2856 * So let's leave module_exit but move module_init to an earlier place 2857 */ 2858 arch_initcall(pl011_init); 2859 module_exit(pl011_exit); 2860 2861 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 2862 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 2863 MODULE_LICENSE("GPL"); 2864