1 /* 2 * Driver for AMBA serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright 1999 ARM Limited 7 * Copyright (C) 2000 Deep Blue Solutions Ltd. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 * This is a generic driver for ARM AMBA-type serial ports. They 24 * have a lot of 16550-like features, but are not register compatible. 25 * Note that although they do have CTS, DCD and DSR inputs, they do 26 * not have an RI input, nor do they have DTR or RTS outputs. If 27 * required, these have to be supplied via some other means (eg, GPIO) 28 * and hooked into this driver. 29 */ 30 31 #if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 32 #define SUPPORT_SYSRQ 33 #endif 34 35 #include <linux/module.h> 36 #include <linux/ioport.h> 37 #include <linux/init.h> 38 #include <linux/console.h> 39 #include <linux/sysrq.h> 40 #include <linux/device.h> 41 #include <linux/tty.h> 42 #include <linux/tty_flip.h> 43 #include <linux/serial_core.h> 44 #include <linux/serial.h> 45 #include <linux/amba/bus.h> 46 #include <linux/amba/serial.h> 47 #include <linux/clk.h> 48 #include <linux/slab.h> 49 50 #include <asm/io.h> 51 52 #define UART_NR 8 53 54 #define SERIAL_AMBA_MAJOR 204 55 #define SERIAL_AMBA_MINOR 16 56 #define SERIAL_AMBA_NR UART_NR 57 58 #define AMBA_ISR_PASS_LIMIT 256 59 60 #define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0) 61 #define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0) 62 63 #define UART_DUMMY_RSR_RX 256 64 #define UART_PORT_SIZE 64 65 66 /* 67 * We wrap our port structure around the generic uart_port. 68 */ 69 struct uart_amba_port { 70 struct uart_port port; 71 struct clk *clk; 72 struct amba_device *dev; 73 struct amba_pl010_data *data; 74 unsigned int old_status; 75 }; 76 77 static void pl010_stop_tx(struct uart_port *port) 78 { 79 struct uart_amba_port *uap = (struct uart_amba_port *)port; 80 unsigned int cr; 81 82 cr = readb(uap->port.membase + UART010_CR); 83 cr &= ~UART010_CR_TIE; 84 writel(cr, uap->port.membase + UART010_CR); 85 } 86 87 static void pl010_start_tx(struct uart_port *port) 88 { 89 struct uart_amba_port *uap = (struct uart_amba_port *)port; 90 unsigned int cr; 91 92 cr = readb(uap->port.membase + UART010_CR); 93 cr |= UART010_CR_TIE; 94 writel(cr, uap->port.membase + UART010_CR); 95 } 96 97 static void pl010_stop_rx(struct uart_port *port) 98 { 99 struct uart_amba_port *uap = (struct uart_amba_port *)port; 100 unsigned int cr; 101 102 cr = readb(uap->port.membase + UART010_CR); 103 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE); 104 writel(cr, uap->port.membase + UART010_CR); 105 } 106 107 static void pl010_enable_ms(struct uart_port *port) 108 { 109 struct uart_amba_port *uap = (struct uart_amba_port *)port; 110 unsigned int cr; 111 112 cr = readb(uap->port.membase + UART010_CR); 113 cr |= UART010_CR_MSIE; 114 writel(cr, uap->port.membase + UART010_CR); 115 } 116 117 static void pl010_rx_chars(struct uart_amba_port *uap) 118 { 119 unsigned int status, ch, flag, rsr, max_count = 256; 120 121 status = readb(uap->port.membase + UART01x_FR); 122 while (UART_RX_DATA(status) && max_count--) { 123 ch = readb(uap->port.membase + UART01x_DR); 124 flag = TTY_NORMAL; 125 126 uap->port.icount.rx++; 127 128 /* 129 * Note that the error handling code is 130 * out of the main execution path 131 */ 132 rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; 133 if (unlikely(rsr & UART01x_RSR_ANY)) { 134 writel(0, uap->port.membase + UART01x_ECR); 135 136 if (rsr & UART01x_RSR_BE) { 137 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); 138 uap->port.icount.brk++; 139 if (uart_handle_break(&uap->port)) 140 goto ignore_char; 141 } else if (rsr & UART01x_RSR_PE) 142 uap->port.icount.parity++; 143 else if (rsr & UART01x_RSR_FE) 144 uap->port.icount.frame++; 145 if (rsr & UART01x_RSR_OE) 146 uap->port.icount.overrun++; 147 148 rsr &= uap->port.read_status_mask; 149 150 if (rsr & UART01x_RSR_BE) 151 flag = TTY_BREAK; 152 else if (rsr & UART01x_RSR_PE) 153 flag = TTY_PARITY; 154 else if (rsr & UART01x_RSR_FE) 155 flag = TTY_FRAME; 156 } 157 158 if (uart_handle_sysrq_char(&uap->port, ch)) 159 goto ignore_char; 160 161 uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag); 162 163 ignore_char: 164 status = readb(uap->port.membase + UART01x_FR); 165 } 166 spin_unlock(&uap->port.lock); 167 tty_flip_buffer_push(&uap->port.state->port); 168 spin_lock(&uap->port.lock); 169 } 170 171 static void pl010_tx_chars(struct uart_amba_port *uap) 172 { 173 struct circ_buf *xmit = &uap->port.state->xmit; 174 int count; 175 176 if (uap->port.x_char) { 177 writel(uap->port.x_char, uap->port.membase + UART01x_DR); 178 uap->port.icount.tx++; 179 uap->port.x_char = 0; 180 return; 181 } 182 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { 183 pl010_stop_tx(&uap->port); 184 return; 185 } 186 187 count = uap->port.fifosize >> 1; 188 do { 189 writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); 190 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 191 uap->port.icount.tx++; 192 if (uart_circ_empty(xmit)) 193 break; 194 } while (--count > 0); 195 196 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 197 uart_write_wakeup(&uap->port); 198 199 if (uart_circ_empty(xmit)) 200 pl010_stop_tx(&uap->port); 201 } 202 203 static void pl010_modem_status(struct uart_amba_port *uap) 204 { 205 unsigned int status, delta; 206 207 writel(0, uap->port.membase + UART010_ICR); 208 209 status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; 210 211 delta = status ^ uap->old_status; 212 uap->old_status = status; 213 214 if (!delta) 215 return; 216 217 if (delta & UART01x_FR_DCD) 218 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 219 220 if (delta & UART01x_FR_DSR) 221 uap->port.icount.dsr++; 222 223 if (delta & UART01x_FR_CTS) 224 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); 225 226 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 227 } 228 229 static irqreturn_t pl010_int(int irq, void *dev_id) 230 { 231 struct uart_amba_port *uap = dev_id; 232 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 233 int handled = 0; 234 235 spin_lock(&uap->port.lock); 236 237 status = readb(uap->port.membase + UART010_IIR); 238 if (status) { 239 do { 240 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS)) 241 pl010_rx_chars(uap); 242 if (status & UART010_IIR_MIS) 243 pl010_modem_status(uap); 244 if (status & UART010_IIR_TIS) 245 pl010_tx_chars(uap); 246 247 if (pass_counter-- == 0) 248 break; 249 250 status = readb(uap->port.membase + UART010_IIR); 251 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS | 252 UART010_IIR_TIS)); 253 handled = 1; 254 } 255 256 spin_unlock(&uap->port.lock); 257 258 return IRQ_RETVAL(handled); 259 } 260 261 static unsigned int pl010_tx_empty(struct uart_port *port) 262 { 263 struct uart_amba_port *uap = (struct uart_amba_port *)port; 264 unsigned int status = readb(uap->port.membase + UART01x_FR); 265 return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT; 266 } 267 268 static unsigned int pl010_get_mctrl(struct uart_port *port) 269 { 270 struct uart_amba_port *uap = (struct uart_amba_port *)port; 271 unsigned int result = 0; 272 unsigned int status; 273 274 status = readb(uap->port.membase + UART01x_FR); 275 if (status & UART01x_FR_DCD) 276 result |= TIOCM_CAR; 277 if (status & UART01x_FR_DSR) 278 result |= TIOCM_DSR; 279 if (status & UART01x_FR_CTS) 280 result |= TIOCM_CTS; 281 282 return result; 283 } 284 285 static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl) 286 { 287 struct uart_amba_port *uap = (struct uart_amba_port *)port; 288 289 if (uap->data) 290 uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl); 291 } 292 293 static void pl010_break_ctl(struct uart_port *port, int break_state) 294 { 295 struct uart_amba_port *uap = (struct uart_amba_port *)port; 296 unsigned long flags; 297 unsigned int lcr_h; 298 299 spin_lock_irqsave(&uap->port.lock, flags); 300 lcr_h = readb(uap->port.membase + UART010_LCRH); 301 if (break_state == -1) 302 lcr_h |= UART01x_LCRH_BRK; 303 else 304 lcr_h &= ~UART01x_LCRH_BRK; 305 writel(lcr_h, uap->port.membase + UART010_LCRH); 306 spin_unlock_irqrestore(&uap->port.lock, flags); 307 } 308 309 static int pl010_startup(struct uart_port *port) 310 { 311 struct uart_amba_port *uap = (struct uart_amba_port *)port; 312 int retval; 313 314 /* 315 * Try to enable the clock producer. 316 */ 317 retval = clk_prepare_enable(uap->clk); 318 if (retval) 319 goto out; 320 321 uap->port.uartclk = clk_get_rate(uap->clk); 322 323 /* 324 * Allocate the IRQ 325 */ 326 retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap); 327 if (retval) 328 goto clk_dis; 329 330 /* 331 * initialise the old status of the modem signals 332 */ 333 uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; 334 335 /* 336 * Finally, enable interrupts 337 */ 338 writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE, 339 uap->port.membase + UART010_CR); 340 341 return 0; 342 343 clk_dis: 344 clk_disable_unprepare(uap->clk); 345 out: 346 return retval; 347 } 348 349 static void pl010_shutdown(struct uart_port *port) 350 { 351 struct uart_amba_port *uap = (struct uart_amba_port *)port; 352 353 /* 354 * Free the interrupt 355 */ 356 free_irq(uap->port.irq, uap); 357 358 /* 359 * disable all interrupts, disable the port 360 */ 361 writel(0, uap->port.membase + UART010_CR); 362 363 /* disable break condition and fifos */ 364 writel(readb(uap->port.membase + UART010_LCRH) & 365 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN), 366 uap->port.membase + UART010_LCRH); 367 368 /* 369 * Shut down the clock producer 370 */ 371 clk_disable_unprepare(uap->clk); 372 } 373 374 static void 375 pl010_set_termios(struct uart_port *port, struct ktermios *termios, 376 struct ktermios *old) 377 { 378 struct uart_amba_port *uap = (struct uart_amba_port *)port; 379 unsigned int lcr_h, old_cr; 380 unsigned long flags; 381 unsigned int baud, quot; 382 383 /* 384 * Ask the core to calculate the divisor for us. 385 */ 386 baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16); 387 quot = uart_get_divisor(port, baud); 388 389 switch (termios->c_cflag & CSIZE) { 390 case CS5: 391 lcr_h = UART01x_LCRH_WLEN_5; 392 break; 393 case CS6: 394 lcr_h = UART01x_LCRH_WLEN_6; 395 break; 396 case CS7: 397 lcr_h = UART01x_LCRH_WLEN_7; 398 break; 399 default: // CS8 400 lcr_h = UART01x_LCRH_WLEN_8; 401 break; 402 } 403 if (termios->c_cflag & CSTOPB) 404 lcr_h |= UART01x_LCRH_STP2; 405 if (termios->c_cflag & PARENB) { 406 lcr_h |= UART01x_LCRH_PEN; 407 if (!(termios->c_cflag & PARODD)) 408 lcr_h |= UART01x_LCRH_EPS; 409 } 410 if (uap->port.fifosize > 1) 411 lcr_h |= UART01x_LCRH_FEN; 412 413 spin_lock_irqsave(&uap->port.lock, flags); 414 415 /* 416 * Update the per-port timeout. 417 */ 418 uart_update_timeout(port, termios->c_cflag, baud); 419 420 uap->port.read_status_mask = UART01x_RSR_OE; 421 if (termios->c_iflag & INPCK) 422 uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; 423 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 424 uap->port.read_status_mask |= UART01x_RSR_BE; 425 426 /* 427 * Characters to ignore 428 */ 429 uap->port.ignore_status_mask = 0; 430 if (termios->c_iflag & IGNPAR) 431 uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; 432 if (termios->c_iflag & IGNBRK) { 433 uap->port.ignore_status_mask |= UART01x_RSR_BE; 434 /* 435 * If we're ignoring parity and break indicators, 436 * ignore overruns too (for real raw support). 437 */ 438 if (termios->c_iflag & IGNPAR) 439 uap->port.ignore_status_mask |= UART01x_RSR_OE; 440 } 441 442 /* 443 * Ignore all characters if CREAD is not set. 444 */ 445 if ((termios->c_cflag & CREAD) == 0) 446 uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX; 447 448 /* first, disable everything */ 449 old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE; 450 451 if (UART_ENABLE_MS(port, termios->c_cflag)) 452 old_cr |= UART010_CR_MSIE; 453 454 writel(0, uap->port.membase + UART010_CR); 455 456 /* Set baud rate */ 457 quot -= 1; 458 writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM); 459 writel(quot & 0xff, uap->port.membase + UART010_LCRL); 460 461 /* 462 * ----------v----------v----------v----------v----- 463 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L 464 * ----------^----------^----------^----------^----- 465 */ 466 writel(lcr_h, uap->port.membase + UART010_LCRH); 467 writel(old_cr, uap->port.membase + UART010_CR); 468 469 spin_unlock_irqrestore(&uap->port.lock, flags); 470 } 471 472 static void pl010_set_ldisc(struct uart_port *port, int new) 473 { 474 if (new == N_PPS) { 475 port->flags |= UPF_HARDPPS_CD; 476 pl010_enable_ms(port); 477 } else 478 port->flags &= ~UPF_HARDPPS_CD; 479 } 480 481 static const char *pl010_type(struct uart_port *port) 482 { 483 return port->type == PORT_AMBA ? "AMBA" : NULL; 484 } 485 486 /* 487 * Release the memory region(s) being used by 'port' 488 */ 489 static void pl010_release_port(struct uart_port *port) 490 { 491 release_mem_region(port->mapbase, UART_PORT_SIZE); 492 } 493 494 /* 495 * Request the memory region(s) being used by 'port' 496 */ 497 static int pl010_request_port(struct uart_port *port) 498 { 499 return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010") 500 != NULL ? 0 : -EBUSY; 501 } 502 503 /* 504 * Configure/autoconfigure the port. 505 */ 506 static void pl010_config_port(struct uart_port *port, int flags) 507 { 508 if (flags & UART_CONFIG_TYPE) { 509 port->type = PORT_AMBA; 510 pl010_request_port(port); 511 } 512 } 513 514 /* 515 * verify the new serial_struct (for TIOCSSERIAL). 516 */ 517 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) 518 { 519 int ret = 0; 520 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 521 ret = -EINVAL; 522 if (ser->irq < 0 || ser->irq >= nr_irqs) 523 ret = -EINVAL; 524 if (ser->baud_base < 9600) 525 ret = -EINVAL; 526 return ret; 527 } 528 529 static struct uart_ops amba_pl010_pops = { 530 .tx_empty = pl010_tx_empty, 531 .set_mctrl = pl010_set_mctrl, 532 .get_mctrl = pl010_get_mctrl, 533 .stop_tx = pl010_stop_tx, 534 .start_tx = pl010_start_tx, 535 .stop_rx = pl010_stop_rx, 536 .enable_ms = pl010_enable_ms, 537 .break_ctl = pl010_break_ctl, 538 .startup = pl010_startup, 539 .shutdown = pl010_shutdown, 540 .set_termios = pl010_set_termios, 541 .set_ldisc = pl010_set_ldisc, 542 .type = pl010_type, 543 .release_port = pl010_release_port, 544 .request_port = pl010_request_port, 545 .config_port = pl010_config_port, 546 .verify_port = pl010_verify_port, 547 }; 548 549 static struct uart_amba_port *amba_ports[UART_NR]; 550 551 #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE 552 553 static void pl010_console_putchar(struct uart_port *port, int ch) 554 { 555 struct uart_amba_port *uap = (struct uart_amba_port *)port; 556 unsigned int status; 557 558 do { 559 status = readb(uap->port.membase + UART01x_FR); 560 barrier(); 561 } while (!UART_TX_READY(status)); 562 writel(ch, uap->port.membase + UART01x_DR); 563 } 564 565 static void 566 pl010_console_write(struct console *co, const char *s, unsigned int count) 567 { 568 struct uart_amba_port *uap = amba_ports[co->index]; 569 unsigned int status, old_cr; 570 571 clk_enable(uap->clk); 572 573 /* 574 * First save the CR then disable the interrupts 575 */ 576 old_cr = readb(uap->port.membase + UART010_CR); 577 writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR); 578 579 uart_console_write(&uap->port, s, count, pl010_console_putchar); 580 581 /* 582 * Finally, wait for transmitter to become empty 583 * and restore the TCR 584 */ 585 do { 586 status = readb(uap->port.membase + UART01x_FR); 587 barrier(); 588 } while (status & UART01x_FR_BUSY); 589 writel(old_cr, uap->port.membase + UART010_CR); 590 591 clk_disable(uap->clk); 592 } 593 594 static void __init 595 pl010_console_get_options(struct uart_amba_port *uap, int *baud, 596 int *parity, int *bits) 597 { 598 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { 599 unsigned int lcr_h, quot; 600 lcr_h = readb(uap->port.membase + UART010_LCRH); 601 602 *parity = 'n'; 603 if (lcr_h & UART01x_LCRH_PEN) { 604 if (lcr_h & UART01x_LCRH_EPS) 605 *parity = 'e'; 606 else 607 *parity = 'o'; 608 } 609 610 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 611 *bits = 7; 612 else 613 *bits = 8; 614 615 quot = readb(uap->port.membase + UART010_LCRL) | 616 readb(uap->port.membase + UART010_LCRM) << 8; 617 *baud = uap->port.uartclk / (16 * (quot + 1)); 618 } 619 } 620 621 static int __init pl010_console_setup(struct console *co, char *options) 622 { 623 struct uart_amba_port *uap; 624 int baud = 38400; 625 int bits = 8; 626 int parity = 'n'; 627 int flow = 'n'; 628 int ret; 629 630 /* 631 * Check whether an invalid uart number has been specified, and 632 * if so, search for the first available port that does have 633 * console support. 634 */ 635 if (co->index >= UART_NR) 636 co->index = 0; 637 uap = amba_ports[co->index]; 638 if (!uap) 639 return -ENODEV; 640 641 ret = clk_prepare(uap->clk); 642 if (ret) 643 return ret; 644 645 uap->port.uartclk = clk_get_rate(uap->clk); 646 647 if (options) 648 uart_parse_options(options, &baud, &parity, &bits, &flow); 649 else 650 pl010_console_get_options(uap, &baud, &parity, &bits); 651 652 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 653 } 654 655 static struct uart_driver amba_reg; 656 static struct console amba_console = { 657 .name = "ttyAM", 658 .write = pl010_console_write, 659 .device = uart_console_device, 660 .setup = pl010_console_setup, 661 .flags = CON_PRINTBUFFER, 662 .index = -1, 663 .data = &amba_reg, 664 }; 665 666 #define AMBA_CONSOLE &amba_console 667 #else 668 #define AMBA_CONSOLE NULL 669 #endif 670 671 static struct uart_driver amba_reg = { 672 .owner = THIS_MODULE, 673 .driver_name = "ttyAM", 674 .dev_name = "ttyAM", 675 .major = SERIAL_AMBA_MAJOR, 676 .minor = SERIAL_AMBA_MINOR, 677 .nr = UART_NR, 678 .cons = AMBA_CONSOLE, 679 }; 680 681 static int pl010_probe(struct amba_device *dev, const struct amba_id *id) 682 { 683 struct uart_amba_port *uap; 684 void __iomem *base; 685 int i, ret; 686 687 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 688 if (amba_ports[i] == NULL) 689 break; 690 691 if (i == ARRAY_SIZE(amba_ports)) { 692 ret = -EBUSY; 693 goto out; 694 } 695 696 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL); 697 if (!uap) { 698 ret = -ENOMEM; 699 goto out; 700 } 701 702 base = ioremap(dev->res.start, resource_size(&dev->res)); 703 if (!base) { 704 ret = -ENOMEM; 705 goto free; 706 } 707 708 uap->clk = clk_get(&dev->dev, NULL); 709 if (IS_ERR(uap->clk)) { 710 ret = PTR_ERR(uap->clk); 711 goto unmap; 712 } 713 714 uap->port.dev = &dev->dev; 715 uap->port.mapbase = dev->res.start; 716 uap->port.membase = base; 717 uap->port.iotype = UPIO_MEM; 718 uap->port.irq = dev->irq[0]; 719 uap->port.fifosize = 16; 720 uap->port.ops = &amba_pl010_pops; 721 uap->port.flags = UPF_BOOT_AUTOCONF; 722 uap->port.line = i; 723 uap->dev = dev; 724 uap->data = dev_get_platdata(&dev->dev); 725 726 amba_ports[i] = uap; 727 728 amba_set_drvdata(dev, uap); 729 ret = uart_add_one_port(&amba_reg, &uap->port); 730 if (ret) { 731 amba_ports[i] = NULL; 732 clk_put(uap->clk); 733 unmap: 734 iounmap(base); 735 free: 736 kfree(uap); 737 } 738 out: 739 return ret; 740 } 741 742 static int pl010_remove(struct amba_device *dev) 743 { 744 struct uart_amba_port *uap = amba_get_drvdata(dev); 745 int i; 746 747 uart_remove_one_port(&amba_reg, &uap->port); 748 749 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 750 if (amba_ports[i] == uap) 751 amba_ports[i] = NULL; 752 753 iounmap(uap->port.membase); 754 clk_put(uap->clk); 755 kfree(uap); 756 return 0; 757 } 758 759 #ifdef CONFIG_PM_SLEEP 760 static int pl010_suspend(struct device *dev) 761 { 762 struct uart_amba_port *uap = dev_get_drvdata(dev); 763 764 if (uap) 765 uart_suspend_port(&amba_reg, &uap->port); 766 767 return 0; 768 } 769 770 static int pl010_resume(struct device *dev) 771 { 772 struct uart_amba_port *uap = dev_get_drvdata(dev); 773 774 if (uap) 775 uart_resume_port(&amba_reg, &uap->port); 776 777 return 0; 778 } 779 #endif 780 781 static SIMPLE_DEV_PM_OPS(pl010_dev_pm_ops, pl010_suspend, pl010_resume); 782 783 static struct amba_id pl010_ids[] = { 784 { 785 .id = 0x00041010, 786 .mask = 0x000fffff, 787 }, 788 { 0, 0 }, 789 }; 790 791 MODULE_DEVICE_TABLE(amba, pl010_ids); 792 793 static struct amba_driver pl010_driver = { 794 .drv = { 795 .name = "uart-pl010", 796 .pm = &pl010_dev_pm_ops, 797 }, 798 .id_table = pl010_ids, 799 .probe = pl010_probe, 800 .remove = pl010_remove, 801 }; 802 803 static int __init pl010_init(void) 804 { 805 int ret; 806 807 printk(KERN_INFO "Serial: AMBA driver\n"); 808 809 ret = uart_register_driver(&amba_reg); 810 if (ret == 0) { 811 ret = amba_driver_register(&pl010_driver); 812 if (ret) 813 uart_unregister_driver(&amba_reg); 814 } 815 return ret; 816 } 817 818 static void __exit pl010_exit(void) 819 { 820 amba_driver_unregister(&pl010_driver); 821 uart_unregister_driver(&amba_reg); 822 } 823 824 module_init(pl010_init); 825 module_exit(pl010_exit); 826 827 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 828 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 829 MODULE_LICENSE("GPL"); 830