1 /* 2 * Driver for AMBA serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright 1999 ARM Limited 7 * Copyright (C) 2000 Deep Blue Solutions Ltd. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 * This is a generic driver for ARM AMBA-type serial ports. They 24 * have a lot of 16550-like features, but are not register compatible. 25 * Note that although they do have CTS, DCD and DSR inputs, they do 26 * not have an RI input, nor do they have DTR or RTS outputs. If 27 * required, these have to be supplied via some other means (eg, GPIO) 28 * and hooked into this driver. 29 */ 30 31 #if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 32 #define SUPPORT_SYSRQ 33 #endif 34 35 #include <linux/module.h> 36 #include <linux/ioport.h> 37 #include <linux/init.h> 38 #include <linux/console.h> 39 #include <linux/sysrq.h> 40 #include <linux/device.h> 41 #include <linux/tty.h> 42 #include <linux/tty_flip.h> 43 #include <linux/serial_core.h> 44 #include <linux/serial.h> 45 #include <linux/amba/bus.h> 46 #include <linux/amba/serial.h> 47 #include <linux/clk.h> 48 #include <linux/slab.h> 49 50 #include <asm/io.h> 51 52 #define UART_NR 8 53 54 #define SERIAL_AMBA_MAJOR 204 55 #define SERIAL_AMBA_MINOR 16 56 #define SERIAL_AMBA_NR UART_NR 57 58 #define AMBA_ISR_PASS_LIMIT 256 59 60 #define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0) 61 #define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0) 62 63 #define UART_DUMMY_RSR_RX 256 64 #define UART_PORT_SIZE 64 65 66 /* 67 * We wrap our port structure around the generic uart_port. 68 */ 69 struct uart_amba_port { 70 struct uart_port port; 71 struct clk *clk; 72 struct amba_device *dev; 73 struct amba_pl010_data *data; 74 unsigned int old_status; 75 }; 76 77 static void pl010_stop_tx(struct uart_port *port) 78 { 79 struct uart_amba_port *uap = (struct uart_amba_port *)port; 80 unsigned int cr; 81 82 cr = readb(uap->port.membase + UART010_CR); 83 cr &= ~UART010_CR_TIE; 84 writel(cr, uap->port.membase + UART010_CR); 85 } 86 87 static void pl010_start_tx(struct uart_port *port) 88 { 89 struct uart_amba_port *uap = (struct uart_amba_port *)port; 90 unsigned int cr; 91 92 cr = readb(uap->port.membase + UART010_CR); 93 cr |= UART010_CR_TIE; 94 writel(cr, uap->port.membase + UART010_CR); 95 } 96 97 static void pl010_stop_rx(struct uart_port *port) 98 { 99 struct uart_amba_port *uap = (struct uart_amba_port *)port; 100 unsigned int cr; 101 102 cr = readb(uap->port.membase + UART010_CR); 103 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE); 104 writel(cr, uap->port.membase + UART010_CR); 105 } 106 107 static void pl010_enable_ms(struct uart_port *port) 108 { 109 struct uart_amba_port *uap = (struct uart_amba_port *)port; 110 unsigned int cr; 111 112 cr = readb(uap->port.membase + UART010_CR); 113 cr |= UART010_CR_MSIE; 114 writel(cr, uap->port.membase + UART010_CR); 115 } 116 117 static void pl010_rx_chars(struct uart_amba_port *uap) 118 { 119 struct tty_struct *tty = uap->port.state->port.tty; 120 unsigned int status, ch, flag, rsr, max_count = 256; 121 122 status = readb(uap->port.membase + UART01x_FR); 123 while (UART_RX_DATA(status) && max_count--) { 124 ch = readb(uap->port.membase + UART01x_DR); 125 flag = TTY_NORMAL; 126 127 uap->port.icount.rx++; 128 129 /* 130 * Note that the error handling code is 131 * out of the main execution path 132 */ 133 rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; 134 if (unlikely(rsr & UART01x_RSR_ANY)) { 135 writel(0, uap->port.membase + UART01x_ECR); 136 137 if (rsr & UART01x_RSR_BE) { 138 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); 139 uap->port.icount.brk++; 140 if (uart_handle_break(&uap->port)) 141 goto ignore_char; 142 } else if (rsr & UART01x_RSR_PE) 143 uap->port.icount.parity++; 144 else if (rsr & UART01x_RSR_FE) 145 uap->port.icount.frame++; 146 if (rsr & UART01x_RSR_OE) 147 uap->port.icount.overrun++; 148 149 rsr &= uap->port.read_status_mask; 150 151 if (rsr & UART01x_RSR_BE) 152 flag = TTY_BREAK; 153 else if (rsr & UART01x_RSR_PE) 154 flag = TTY_PARITY; 155 else if (rsr & UART01x_RSR_FE) 156 flag = TTY_FRAME; 157 } 158 159 if (uart_handle_sysrq_char(&uap->port, ch)) 160 goto ignore_char; 161 162 uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag); 163 164 ignore_char: 165 status = readb(uap->port.membase + UART01x_FR); 166 } 167 spin_unlock(&uap->port.lock); 168 tty_flip_buffer_push(tty); 169 spin_lock(&uap->port.lock); 170 } 171 172 static void pl010_tx_chars(struct uart_amba_port *uap) 173 { 174 struct circ_buf *xmit = &uap->port.state->xmit; 175 int count; 176 177 if (uap->port.x_char) { 178 writel(uap->port.x_char, uap->port.membase + UART01x_DR); 179 uap->port.icount.tx++; 180 uap->port.x_char = 0; 181 return; 182 } 183 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { 184 pl010_stop_tx(&uap->port); 185 return; 186 } 187 188 count = uap->port.fifosize >> 1; 189 do { 190 writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); 191 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 192 uap->port.icount.tx++; 193 if (uart_circ_empty(xmit)) 194 break; 195 } while (--count > 0); 196 197 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 198 uart_write_wakeup(&uap->port); 199 200 if (uart_circ_empty(xmit)) 201 pl010_stop_tx(&uap->port); 202 } 203 204 static void pl010_modem_status(struct uart_amba_port *uap) 205 { 206 unsigned int status, delta; 207 208 writel(0, uap->port.membase + UART010_ICR); 209 210 status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; 211 212 delta = status ^ uap->old_status; 213 uap->old_status = status; 214 215 if (!delta) 216 return; 217 218 if (delta & UART01x_FR_DCD) 219 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 220 221 if (delta & UART01x_FR_DSR) 222 uap->port.icount.dsr++; 223 224 if (delta & UART01x_FR_CTS) 225 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); 226 227 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 228 } 229 230 static irqreturn_t pl010_int(int irq, void *dev_id) 231 { 232 struct uart_amba_port *uap = dev_id; 233 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 234 int handled = 0; 235 236 spin_lock(&uap->port.lock); 237 238 status = readb(uap->port.membase + UART010_IIR); 239 if (status) { 240 do { 241 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS)) 242 pl010_rx_chars(uap); 243 if (status & UART010_IIR_MIS) 244 pl010_modem_status(uap); 245 if (status & UART010_IIR_TIS) 246 pl010_tx_chars(uap); 247 248 if (pass_counter-- == 0) 249 break; 250 251 status = readb(uap->port.membase + UART010_IIR); 252 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS | 253 UART010_IIR_TIS)); 254 handled = 1; 255 } 256 257 spin_unlock(&uap->port.lock); 258 259 return IRQ_RETVAL(handled); 260 } 261 262 static unsigned int pl010_tx_empty(struct uart_port *port) 263 { 264 struct uart_amba_port *uap = (struct uart_amba_port *)port; 265 unsigned int status = readb(uap->port.membase + UART01x_FR); 266 return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT; 267 } 268 269 static unsigned int pl010_get_mctrl(struct uart_port *port) 270 { 271 struct uart_amba_port *uap = (struct uart_amba_port *)port; 272 unsigned int result = 0; 273 unsigned int status; 274 275 status = readb(uap->port.membase + UART01x_FR); 276 if (status & UART01x_FR_DCD) 277 result |= TIOCM_CAR; 278 if (status & UART01x_FR_DSR) 279 result |= TIOCM_DSR; 280 if (status & UART01x_FR_CTS) 281 result |= TIOCM_CTS; 282 283 return result; 284 } 285 286 static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl) 287 { 288 struct uart_amba_port *uap = (struct uart_amba_port *)port; 289 290 if (uap->data) 291 uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl); 292 } 293 294 static void pl010_break_ctl(struct uart_port *port, int break_state) 295 { 296 struct uart_amba_port *uap = (struct uart_amba_port *)port; 297 unsigned long flags; 298 unsigned int lcr_h; 299 300 spin_lock_irqsave(&uap->port.lock, flags); 301 lcr_h = readb(uap->port.membase + UART010_LCRH); 302 if (break_state == -1) 303 lcr_h |= UART01x_LCRH_BRK; 304 else 305 lcr_h &= ~UART01x_LCRH_BRK; 306 writel(lcr_h, uap->port.membase + UART010_LCRH); 307 spin_unlock_irqrestore(&uap->port.lock, flags); 308 } 309 310 static int pl010_startup(struct uart_port *port) 311 { 312 struct uart_amba_port *uap = (struct uart_amba_port *)port; 313 int retval; 314 315 /* 316 * Try to enable the clock producer. 317 */ 318 retval = clk_prepare_enable(uap->clk); 319 if (retval) 320 goto out; 321 322 uap->port.uartclk = clk_get_rate(uap->clk); 323 324 /* 325 * Allocate the IRQ 326 */ 327 retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap); 328 if (retval) 329 goto clk_dis; 330 331 /* 332 * initialise the old status of the modem signals 333 */ 334 uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; 335 336 /* 337 * Finally, enable interrupts 338 */ 339 writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE, 340 uap->port.membase + UART010_CR); 341 342 return 0; 343 344 clk_dis: 345 clk_disable_unprepare(uap->clk); 346 out: 347 return retval; 348 } 349 350 static void pl010_shutdown(struct uart_port *port) 351 { 352 struct uart_amba_port *uap = (struct uart_amba_port *)port; 353 354 /* 355 * Free the interrupt 356 */ 357 free_irq(uap->port.irq, uap); 358 359 /* 360 * disable all interrupts, disable the port 361 */ 362 writel(0, uap->port.membase + UART010_CR); 363 364 /* disable break condition and fifos */ 365 writel(readb(uap->port.membase + UART010_LCRH) & 366 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN), 367 uap->port.membase + UART010_LCRH); 368 369 /* 370 * Shut down the clock producer 371 */ 372 clk_disable_unprepare(uap->clk); 373 } 374 375 static void 376 pl010_set_termios(struct uart_port *port, struct ktermios *termios, 377 struct ktermios *old) 378 { 379 struct uart_amba_port *uap = (struct uart_amba_port *)port; 380 unsigned int lcr_h, old_cr; 381 unsigned long flags; 382 unsigned int baud, quot; 383 384 /* 385 * Ask the core to calculate the divisor for us. 386 */ 387 baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16); 388 quot = uart_get_divisor(port, baud); 389 390 switch (termios->c_cflag & CSIZE) { 391 case CS5: 392 lcr_h = UART01x_LCRH_WLEN_5; 393 break; 394 case CS6: 395 lcr_h = UART01x_LCRH_WLEN_6; 396 break; 397 case CS7: 398 lcr_h = UART01x_LCRH_WLEN_7; 399 break; 400 default: // CS8 401 lcr_h = UART01x_LCRH_WLEN_8; 402 break; 403 } 404 if (termios->c_cflag & CSTOPB) 405 lcr_h |= UART01x_LCRH_STP2; 406 if (termios->c_cflag & PARENB) { 407 lcr_h |= UART01x_LCRH_PEN; 408 if (!(termios->c_cflag & PARODD)) 409 lcr_h |= UART01x_LCRH_EPS; 410 } 411 if (uap->port.fifosize > 1) 412 lcr_h |= UART01x_LCRH_FEN; 413 414 spin_lock_irqsave(&uap->port.lock, flags); 415 416 /* 417 * Update the per-port timeout. 418 */ 419 uart_update_timeout(port, termios->c_cflag, baud); 420 421 uap->port.read_status_mask = UART01x_RSR_OE; 422 if (termios->c_iflag & INPCK) 423 uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; 424 if (termios->c_iflag & (BRKINT | PARMRK)) 425 uap->port.read_status_mask |= UART01x_RSR_BE; 426 427 /* 428 * Characters to ignore 429 */ 430 uap->port.ignore_status_mask = 0; 431 if (termios->c_iflag & IGNPAR) 432 uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; 433 if (termios->c_iflag & IGNBRK) { 434 uap->port.ignore_status_mask |= UART01x_RSR_BE; 435 /* 436 * If we're ignoring parity and break indicators, 437 * ignore overruns too (for real raw support). 438 */ 439 if (termios->c_iflag & IGNPAR) 440 uap->port.ignore_status_mask |= UART01x_RSR_OE; 441 } 442 443 /* 444 * Ignore all characters if CREAD is not set. 445 */ 446 if ((termios->c_cflag & CREAD) == 0) 447 uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX; 448 449 /* first, disable everything */ 450 old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE; 451 452 if (UART_ENABLE_MS(port, termios->c_cflag)) 453 old_cr |= UART010_CR_MSIE; 454 455 writel(0, uap->port.membase + UART010_CR); 456 457 /* Set baud rate */ 458 quot -= 1; 459 writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM); 460 writel(quot & 0xff, uap->port.membase + UART010_LCRL); 461 462 /* 463 * ----------v----------v----------v----------v----- 464 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L 465 * ----------^----------^----------^----------^----- 466 */ 467 writel(lcr_h, uap->port.membase + UART010_LCRH); 468 writel(old_cr, uap->port.membase + UART010_CR); 469 470 spin_unlock_irqrestore(&uap->port.lock, flags); 471 } 472 473 static void pl010_set_ldisc(struct uart_port *port, int new) 474 { 475 if (new == N_PPS) { 476 port->flags |= UPF_HARDPPS_CD; 477 pl010_enable_ms(port); 478 } else 479 port->flags &= ~UPF_HARDPPS_CD; 480 } 481 482 static const char *pl010_type(struct uart_port *port) 483 { 484 return port->type == PORT_AMBA ? "AMBA" : NULL; 485 } 486 487 /* 488 * Release the memory region(s) being used by 'port' 489 */ 490 static void pl010_release_port(struct uart_port *port) 491 { 492 release_mem_region(port->mapbase, UART_PORT_SIZE); 493 } 494 495 /* 496 * Request the memory region(s) being used by 'port' 497 */ 498 static int pl010_request_port(struct uart_port *port) 499 { 500 return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010") 501 != NULL ? 0 : -EBUSY; 502 } 503 504 /* 505 * Configure/autoconfigure the port. 506 */ 507 static void pl010_config_port(struct uart_port *port, int flags) 508 { 509 if (flags & UART_CONFIG_TYPE) { 510 port->type = PORT_AMBA; 511 pl010_request_port(port); 512 } 513 } 514 515 /* 516 * verify the new serial_struct (for TIOCSSERIAL). 517 */ 518 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) 519 { 520 int ret = 0; 521 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 522 ret = -EINVAL; 523 if (ser->irq < 0 || ser->irq >= nr_irqs) 524 ret = -EINVAL; 525 if (ser->baud_base < 9600) 526 ret = -EINVAL; 527 return ret; 528 } 529 530 static struct uart_ops amba_pl010_pops = { 531 .tx_empty = pl010_tx_empty, 532 .set_mctrl = pl010_set_mctrl, 533 .get_mctrl = pl010_get_mctrl, 534 .stop_tx = pl010_stop_tx, 535 .start_tx = pl010_start_tx, 536 .stop_rx = pl010_stop_rx, 537 .enable_ms = pl010_enable_ms, 538 .break_ctl = pl010_break_ctl, 539 .startup = pl010_startup, 540 .shutdown = pl010_shutdown, 541 .set_termios = pl010_set_termios, 542 .set_ldisc = pl010_set_ldisc, 543 .type = pl010_type, 544 .release_port = pl010_release_port, 545 .request_port = pl010_request_port, 546 .config_port = pl010_config_port, 547 .verify_port = pl010_verify_port, 548 }; 549 550 static struct uart_amba_port *amba_ports[UART_NR]; 551 552 #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE 553 554 static void pl010_console_putchar(struct uart_port *port, int ch) 555 { 556 struct uart_amba_port *uap = (struct uart_amba_port *)port; 557 unsigned int status; 558 559 do { 560 status = readb(uap->port.membase + UART01x_FR); 561 barrier(); 562 } while (!UART_TX_READY(status)); 563 writel(ch, uap->port.membase + UART01x_DR); 564 } 565 566 static void 567 pl010_console_write(struct console *co, const char *s, unsigned int count) 568 { 569 struct uart_amba_port *uap = amba_ports[co->index]; 570 unsigned int status, old_cr; 571 572 clk_enable(uap->clk); 573 574 /* 575 * First save the CR then disable the interrupts 576 */ 577 old_cr = readb(uap->port.membase + UART010_CR); 578 writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR); 579 580 uart_console_write(&uap->port, s, count, pl010_console_putchar); 581 582 /* 583 * Finally, wait for transmitter to become empty 584 * and restore the TCR 585 */ 586 do { 587 status = readb(uap->port.membase + UART01x_FR); 588 barrier(); 589 } while (status & UART01x_FR_BUSY); 590 writel(old_cr, uap->port.membase + UART010_CR); 591 592 clk_disable(uap->clk); 593 } 594 595 static void __init 596 pl010_console_get_options(struct uart_amba_port *uap, int *baud, 597 int *parity, int *bits) 598 { 599 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { 600 unsigned int lcr_h, quot; 601 lcr_h = readb(uap->port.membase + UART010_LCRH); 602 603 *parity = 'n'; 604 if (lcr_h & UART01x_LCRH_PEN) { 605 if (lcr_h & UART01x_LCRH_EPS) 606 *parity = 'e'; 607 else 608 *parity = 'o'; 609 } 610 611 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 612 *bits = 7; 613 else 614 *bits = 8; 615 616 quot = readb(uap->port.membase + UART010_LCRL) | 617 readb(uap->port.membase + UART010_LCRM) << 8; 618 *baud = uap->port.uartclk / (16 * (quot + 1)); 619 } 620 } 621 622 static int __init pl010_console_setup(struct console *co, char *options) 623 { 624 struct uart_amba_port *uap; 625 int baud = 38400; 626 int bits = 8; 627 int parity = 'n'; 628 int flow = 'n'; 629 int ret; 630 631 /* 632 * Check whether an invalid uart number has been specified, and 633 * if so, search for the first available port that does have 634 * console support. 635 */ 636 if (co->index >= UART_NR) 637 co->index = 0; 638 uap = amba_ports[co->index]; 639 if (!uap) 640 return -ENODEV; 641 642 ret = clk_prepare(uap->clk); 643 if (ret) 644 return ret; 645 646 uap->port.uartclk = clk_get_rate(uap->clk); 647 648 if (options) 649 uart_parse_options(options, &baud, &parity, &bits, &flow); 650 else 651 pl010_console_get_options(uap, &baud, &parity, &bits); 652 653 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 654 } 655 656 static struct uart_driver amba_reg; 657 static struct console amba_console = { 658 .name = "ttyAM", 659 .write = pl010_console_write, 660 .device = uart_console_device, 661 .setup = pl010_console_setup, 662 .flags = CON_PRINTBUFFER, 663 .index = -1, 664 .data = &amba_reg, 665 }; 666 667 #define AMBA_CONSOLE &amba_console 668 #else 669 #define AMBA_CONSOLE NULL 670 #endif 671 672 static struct uart_driver amba_reg = { 673 .owner = THIS_MODULE, 674 .driver_name = "ttyAM", 675 .dev_name = "ttyAM", 676 .major = SERIAL_AMBA_MAJOR, 677 .minor = SERIAL_AMBA_MINOR, 678 .nr = UART_NR, 679 .cons = AMBA_CONSOLE, 680 }; 681 682 static int pl010_probe(struct amba_device *dev, const struct amba_id *id) 683 { 684 struct uart_amba_port *uap; 685 void __iomem *base; 686 int i, ret; 687 688 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 689 if (amba_ports[i] == NULL) 690 break; 691 692 if (i == ARRAY_SIZE(amba_ports)) { 693 ret = -EBUSY; 694 goto out; 695 } 696 697 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL); 698 if (!uap) { 699 ret = -ENOMEM; 700 goto out; 701 } 702 703 base = ioremap(dev->res.start, resource_size(&dev->res)); 704 if (!base) { 705 ret = -ENOMEM; 706 goto free; 707 } 708 709 uap->clk = clk_get(&dev->dev, NULL); 710 if (IS_ERR(uap->clk)) { 711 ret = PTR_ERR(uap->clk); 712 goto unmap; 713 } 714 715 uap->port.dev = &dev->dev; 716 uap->port.mapbase = dev->res.start; 717 uap->port.membase = base; 718 uap->port.iotype = UPIO_MEM; 719 uap->port.irq = dev->irq[0]; 720 uap->port.fifosize = 16; 721 uap->port.ops = &amba_pl010_pops; 722 uap->port.flags = UPF_BOOT_AUTOCONF; 723 uap->port.line = i; 724 uap->dev = dev; 725 uap->data = dev->dev.platform_data; 726 727 amba_ports[i] = uap; 728 729 amba_set_drvdata(dev, uap); 730 ret = uart_add_one_port(&amba_reg, &uap->port); 731 if (ret) { 732 amba_set_drvdata(dev, NULL); 733 amba_ports[i] = NULL; 734 clk_put(uap->clk); 735 unmap: 736 iounmap(base); 737 free: 738 kfree(uap); 739 } 740 out: 741 return ret; 742 } 743 744 static int pl010_remove(struct amba_device *dev) 745 { 746 struct uart_amba_port *uap = amba_get_drvdata(dev); 747 int i; 748 749 amba_set_drvdata(dev, NULL); 750 751 uart_remove_one_port(&amba_reg, &uap->port); 752 753 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 754 if (amba_ports[i] == uap) 755 amba_ports[i] = NULL; 756 757 iounmap(uap->port.membase); 758 clk_put(uap->clk); 759 kfree(uap); 760 return 0; 761 } 762 763 static int pl010_suspend(struct amba_device *dev, pm_message_t state) 764 { 765 struct uart_amba_port *uap = amba_get_drvdata(dev); 766 767 if (uap) 768 uart_suspend_port(&amba_reg, &uap->port); 769 770 return 0; 771 } 772 773 static int pl010_resume(struct amba_device *dev) 774 { 775 struct uart_amba_port *uap = amba_get_drvdata(dev); 776 777 if (uap) 778 uart_resume_port(&amba_reg, &uap->port); 779 780 return 0; 781 } 782 783 static struct amba_id pl010_ids[] = { 784 { 785 .id = 0x00041010, 786 .mask = 0x000fffff, 787 }, 788 { 0, 0 }, 789 }; 790 791 MODULE_DEVICE_TABLE(amba, pl010_ids); 792 793 static struct amba_driver pl010_driver = { 794 .drv = { 795 .name = "uart-pl010", 796 }, 797 .id_table = pl010_ids, 798 .probe = pl010_probe, 799 .remove = pl010_remove, 800 .suspend = pl010_suspend, 801 .resume = pl010_resume, 802 }; 803 804 static int __init pl010_init(void) 805 { 806 int ret; 807 808 printk(KERN_INFO "Serial: AMBA driver\n"); 809 810 ret = uart_register_driver(&amba_reg); 811 if (ret == 0) { 812 ret = amba_driver_register(&pl010_driver); 813 if (ret) 814 uart_unregister_driver(&amba_reg); 815 } 816 return ret; 817 } 818 819 static void __exit pl010_exit(void) 820 { 821 amba_driver_unregister(&pl010_driver); 822 uart_unregister_driver(&amba_reg); 823 } 824 825 module_init(pl010_init); 826 module_exit(pl010_exit); 827 828 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 829 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 830 MODULE_LICENSE("GPL"); 831