1 /* 2 * Driver for AMBA serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright 1999 ARM Limited 7 * Copyright (C) 2000 Deep Blue Solutions Ltd. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 * This is a generic driver for ARM AMBA-type serial ports. They 24 * have a lot of 16550-like features, but are not register compatible. 25 * Note that although they do have CTS, DCD and DSR inputs, they do 26 * not have an RI input, nor do they have DTR or RTS outputs. If 27 * required, these have to be supplied via some other means (eg, GPIO) 28 * and hooked into this driver. 29 */ 30 31 #if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 32 #define SUPPORT_SYSRQ 33 #endif 34 35 #include <linux/module.h> 36 #include <linux/ioport.h> 37 #include <linux/init.h> 38 #include <linux/console.h> 39 #include <linux/sysrq.h> 40 #include <linux/device.h> 41 #include <linux/tty.h> 42 #include <linux/tty_flip.h> 43 #include <linux/serial_core.h> 44 #include <linux/serial.h> 45 #include <linux/amba/bus.h> 46 #include <linux/amba/serial.h> 47 #include <linux/clk.h> 48 #include <linux/slab.h> 49 50 #include <asm/io.h> 51 52 #define UART_NR 8 53 54 #define SERIAL_AMBA_MAJOR 204 55 #define SERIAL_AMBA_MINOR 16 56 #define SERIAL_AMBA_NR UART_NR 57 58 #define AMBA_ISR_PASS_LIMIT 256 59 60 #define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0) 61 #define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0) 62 63 #define UART_DUMMY_RSR_RX 256 64 #define UART_PORT_SIZE 64 65 66 /* 67 * We wrap our port structure around the generic uart_port. 68 */ 69 struct uart_amba_port { 70 struct uart_port port; 71 struct clk *clk; 72 struct amba_device *dev; 73 struct amba_pl010_data *data; 74 unsigned int old_status; 75 }; 76 77 static void pl010_stop_tx(struct uart_port *port) 78 { 79 struct uart_amba_port *uap = (struct uart_amba_port *)port; 80 unsigned int cr; 81 82 cr = readb(uap->port.membase + UART010_CR); 83 cr &= ~UART010_CR_TIE; 84 writel(cr, uap->port.membase + UART010_CR); 85 } 86 87 static void pl010_start_tx(struct uart_port *port) 88 { 89 struct uart_amba_port *uap = (struct uart_amba_port *)port; 90 unsigned int cr; 91 92 cr = readb(uap->port.membase + UART010_CR); 93 cr |= UART010_CR_TIE; 94 writel(cr, uap->port.membase + UART010_CR); 95 } 96 97 static void pl010_stop_rx(struct uart_port *port) 98 { 99 struct uart_amba_port *uap = (struct uart_amba_port *)port; 100 unsigned int cr; 101 102 cr = readb(uap->port.membase + UART010_CR); 103 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE); 104 writel(cr, uap->port.membase + UART010_CR); 105 } 106 107 static void pl010_enable_ms(struct uart_port *port) 108 { 109 struct uart_amba_port *uap = (struct uart_amba_port *)port; 110 unsigned int cr; 111 112 cr = readb(uap->port.membase + UART010_CR); 113 cr |= UART010_CR_MSIE; 114 writel(cr, uap->port.membase + UART010_CR); 115 } 116 117 static void pl010_rx_chars(struct uart_amba_port *uap) 118 { 119 struct tty_struct *tty = uap->port.state->port.tty; 120 unsigned int status, ch, flag, rsr, max_count = 256; 121 122 status = readb(uap->port.membase + UART01x_FR); 123 while (UART_RX_DATA(status) && max_count--) { 124 ch = readb(uap->port.membase + UART01x_DR); 125 flag = TTY_NORMAL; 126 127 uap->port.icount.rx++; 128 129 /* 130 * Note that the error handling code is 131 * out of the main execution path 132 */ 133 rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; 134 if (unlikely(rsr & UART01x_RSR_ANY)) { 135 writel(0, uap->port.membase + UART01x_ECR); 136 137 if (rsr & UART01x_RSR_BE) { 138 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); 139 uap->port.icount.brk++; 140 if (uart_handle_break(&uap->port)) 141 goto ignore_char; 142 } else if (rsr & UART01x_RSR_PE) 143 uap->port.icount.parity++; 144 else if (rsr & UART01x_RSR_FE) 145 uap->port.icount.frame++; 146 if (rsr & UART01x_RSR_OE) 147 uap->port.icount.overrun++; 148 149 rsr &= uap->port.read_status_mask; 150 151 if (rsr & UART01x_RSR_BE) 152 flag = TTY_BREAK; 153 else if (rsr & UART01x_RSR_PE) 154 flag = TTY_PARITY; 155 else if (rsr & UART01x_RSR_FE) 156 flag = TTY_FRAME; 157 } 158 159 if (uart_handle_sysrq_char(&uap->port, ch)) 160 goto ignore_char; 161 162 uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag); 163 164 ignore_char: 165 status = readb(uap->port.membase + UART01x_FR); 166 } 167 spin_unlock(&uap->port.lock); 168 tty_flip_buffer_push(tty); 169 spin_lock(&uap->port.lock); 170 } 171 172 static void pl010_tx_chars(struct uart_amba_port *uap) 173 { 174 struct circ_buf *xmit = &uap->port.state->xmit; 175 int count; 176 177 if (uap->port.x_char) { 178 writel(uap->port.x_char, uap->port.membase + UART01x_DR); 179 uap->port.icount.tx++; 180 uap->port.x_char = 0; 181 return; 182 } 183 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { 184 pl010_stop_tx(&uap->port); 185 return; 186 } 187 188 count = uap->port.fifosize >> 1; 189 do { 190 writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); 191 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 192 uap->port.icount.tx++; 193 if (uart_circ_empty(xmit)) 194 break; 195 } while (--count > 0); 196 197 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 198 uart_write_wakeup(&uap->port); 199 200 if (uart_circ_empty(xmit)) 201 pl010_stop_tx(&uap->port); 202 } 203 204 static void pl010_modem_status(struct uart_amba_port *uap) 205 { 206 unsigned int status, delta; 207 208 writel(0, uap->port.membase + UART010_ICR); 209 210 status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; 211 212 delta = status ^ uap->old_status; 213 uap->old_status = status; 214 215 if (!delta) 216 return; 217 218 if (delta & UART01x_FR_DCD) 219 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 220 221 if (delta & UART01x_FR_DSR) 222 uap->port.icount.dsr++; 223 224 if (delta & UART01x_FR_CTS) 225 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); 226 227 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 228 } 229 230 static irqreturn_t pl010_int(int irq, void *dev_id) 231 { 232 struct uart_amba_port *uap = dev_id; 233 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 234 int handled = 0; 235 236 spin_lock(&uap->port.lock); 237 238 status = readb(uap->port.membase + UART010_IIR); 239 if (status) { 240 do { 241 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS)) 242 pl010_rx_chars(uap); 243 if (status & UART010_IIR_MIS) 244 pl010_modem_status(uap); 245 if (status & UART010_IIR_TIS) 246 pl010_tx_chars(uap); 247 248 if (pass_counter-- == 0) 249 break; 250 251 status = readb(uap->port.membase + UART010_IIR); 252 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS | 253 UART010_IIR_TIS)); 254 handled = 1; 255 } 256 257 spin_unlock(&uap->port.lock); 258 259 return IRQ_RETVAL(handled); 260 } 261 262 static unsigned int pl010_tx_empty(struct uart_port *port) 263 { 264 struct uart_amba_port *uap = (struct uart_amba_port *)port; 265 unsigned int status = readb(uap->port.membase + UART01x_FR); 266 return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT; 267 } 268 269 static unsigned int pl010_get_mctrl(struct uart_port *port) 270 { 271 struct uart_amba_port *uap = (struct uart_amba_port *)port; 272 unsigned int result = 0; 273 unsigned int status; 274 275 status = readb(uap->port.membase + UART01x_FR); 276 if (status & UART01x_FR_DCD) 277 result |= TIOCM_CAR; 278 if (status & UART01x_FR_DSR) 279 result |= TIOCM_DSR; 280 if (status & UART01x_FR_CTS) 281 result |= TIOCM_CTS; 282 283 return result; 284 } 285 286 static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl) 287 { 288 struct uart_amba_port *uap = (struct uart_amba_port *)port; 289 290 if (uap->data) 291 uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl); 292 } 293 294 static void pl010_break_ctl(struct uart_port *port, int break_state) 295 { 296 struct uart_amba_port *uap = (struct uart_amba_port *)port; 297 unsigned long flags; 298 unsigned int lcr_h; 299 300 spin_lock_irqsave(&uap->port.lock, flags); 301 lcr_h = readb(uap->port.membase + UART010_LCRH); 302 if (break_state == -1) 303 lcr_h |= UART01x_LCRH_BRK; 304 else 305 lcr_h &= ~UART01x_LCRH_BRK; 306 writel(lcr_h, uap->port.membase + UART010_LCRH); 307 spin_unlock_irqrestore(&uap->port.lock, flags); 308 } 309 310 static int pl010_startup(struct uart_port *port) 311 { 312 struct uart_amba_port *uap = (struct uart_amba_port *)port; 313 int retval; 314 315 retval = clk_prepare(uap->clk); 316 if (retval) 317 goto out; 318 319 /* 320 * Try to enable the clock producer. 321 */ 322 retval = clk_enable(uap->clk); 323 if (retval) 324 goto clk_unprep; 325 326 uap->port.uartclk = clk_get_rate(uap->clk); 327 328 /* 329 * Allocate the IRQ 330 */ 331 retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap); 332 if (retval) 333 goto clk_dis; 334 335 /* 336 * initialise the old status of the modem signals 337 */ 338 uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; 339 340 /* 341 * Finally, enable interrupts 342 */ 343 writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE, 344 uap->port.membase + UART010_CR); 345 346 return 0; 347 348 clk_dis: 349 clk_disable(uap->clk); 350 clk_unprep: 351 clk_unprepare(uap->clk); 352 out: 353 return retval; 354 } 355 356 static void pl010_shutdown(struct uart_port *port) 357 { 358 struct uart_amba_port *uap = (struct uart_amba_port *)port; 359 360 /* 361 * Free the interrupt 362 */ 363 free_irq(uap->port.irq, uap); 364 365 /* 366 * disable all interrupts, disable the port 367 */ 368 writel(0, uap->port.membase + UART010_CR); 369 370 /* disable break condition and fifos */ 371 writel(readb(uap->port.membase + UART010_LCRH) & 372 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN), 373 uap->port.membase + UART010_LCRH); 374 375 /* 376 * Shut down the clock producer 377 */ 378 clk_disable(uap->clk); 379 clk_unprepare(uap->clk); 380 } 381 382 static void 383 pl010_set_termios(struct uart_port *port, struct ktermios *termios, 384 struct ktermios *old) 385 { 386 struct uart_amba_port *uap = (struct uart_amba_port *)port; 387 unsigned int lcr_h, old_cr; 388 unsigned long flags; 389 unsigned int baud, quot; 390 391 /* 392 * Ask the core to calculate the divisor for us. 393 */ 394 baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16); 395 quot = uart_get_divisor(port, baud); 396 397 switch (termios->c_cflag & CSIZE) { 398 case CS5: 399 lcr_h = UART01x_LCRH_WLEN_5; 400 break; 401 case CS6: 402 lcr_h = UART01x_LCRH_WLEN_6; 403 break; 404 case CS7: 405 lcr_h = UART01x_LCRH_WLEN_7; 406 break; 407 default: // CS8 408 lcr_h = UART01x_LCRH_WLEN_8; 409 break; 410 } 411 if (termios->c_cflag & CSTOPB) 412 lcr_h |= UART01x_LCRH_STP2; 413 if (termios->c_cflag & PARENB) { 414 lcr_h |= UART01x_LCRH_PEN; 415 if (!(termios->c_cflag & PARODD)) 416 lcr_h |= UART01x_LCRH_EPS; 417 } 418 if (uap->port.fifosize > 1) 419 lcr_h |= UART01x_LCRH_FEN; 420 421 spin_lock_irqsave(&uap->port.lock, flags); 422 423 /* 424 * Update the per-port timeout. 425 */ 426 uart_update_timeout(port, termios->c_cflag, baud); 427 428 uap->port.read_status_mask = UART01x_RSR_OE; 429 if (termios->c_iflag & INPCK) 430 uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; 431 if (termios->c_iflag & (BRKINT | PARMRK)) 432 uap->port.read_status_mask |= UART01x_RSR_BE; 433 434 /* 435 * Characters to ignore 436 */ 437 uap->port.ignore_status_mask = 0; 438 if (termios->c_iflag & IGNPAR) 439 uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; 440 if (termios->c_iflag & IGNBRK) { 441 uap->port.ignore_status_mask |= UART01x_RSR_BE; 442 /* 443 * If we're ignoring parity and break indicators, 444 * ignore overruns too (for real raw support). 445 */ 446 if (termios->c_iflag & IGNPAR) 447 uap->port.ignore_status_mask |= UART01x_RSR_OE; 448 } 449 450 /* 451 * Ignore all characters if CREAD is not set. 452 */ 453 if ((termios->c_cflag & CREAD) == 0) 454 uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX; 455 456 /* first, disable everything */ 457 old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE; 458 459 if (UART_ENABLE_MS(port, termios->c_cflag)) 460 old_cr |= UART010_CR_MSIE; 461 462 writel(0, uap->port.membase + UART010_CR); 463 464 /* Set baud rate */ 465 quot -= 1; 466 writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM); 467 writel(quot & 0xff, uap->port.membase + UART010_LCRL); 468 469 /* 470 * ----------v----------v----------v----------v----- 471 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L 472 * ----------^----------^----------^----------^----- 473 */ 474 writel(lcr_h, uap->port.membase + UART010_LCRH); 475 writel(old_cr, uap->port.membase + UART010_CR); 476 477 spin_unlock_irqrestore(&uap->port.lock, flags); 478 } 479 480 static void pl010_set_ldisc(struct uart_port *port, int new) 481 { 482 if (new == N_PPS) { 483 port->flags |= UPF_HARDPPS_CD; 484 pl010_enable_ms(port); 485 } else 486 port->flags &= ~UPF_HARDPPS_CD; 487 } 488 489 static const char *pl010_type(struct uart_port *port) 490 { 491 return port->type == PORT_AMBA ? "AMBA" : NULL; 492 } 493 494 /* 495 * Release the memory region(s) being used by 'port' 496 */ 497 static void pl010_release_port(struct uart_port *port) 498 { 499 release_mem_region(port->mapbase, UART_PORT_SIZE); 500 } 501 502 /* 503 * Request the memory region(s) being used by 'port' 504 */ 505 static int pl010_request_port(struct uart_port *port) 506 { 507 return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010") 508 != NULL ? 0 : -EBUSY; 509 } 510 511 /* 512 * Configure/autoconfigure the port. 513 */ 514 static void pl010_config_port(struct uart_port *port, int flags) 515 { 516 if (flags & UART_CONFIG_TYPE) { 517 port->type = PORT_AMBA; 518 pl010_request_port(port); 519 } 520 } 521 522 /* 523 * verify the new serial_struct (for TIOCSSERIAL). 524 */ 525 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) 526 { 527 int ret = 0; 528 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 529 ret = -EINVAL; 530 if (ser->irq < 0 || ser->irq >= nr_irqs) 531 ret = -EINVAL; 532 if (ser->baud_base < 9600) 533 ret = -EINVAL; 534 return ret; 535 } 536 537 static struct uart_ops amba_pl010_pops = { 538 .tx_empty = pl010_tx_empty, 539 .set_mctrl = pl010_set_mctrl, 540 .get_mctrl = pl010_get_mctrl, 541 .stop_tx = pl010_stop_tx, 542 .start_tx = pl010_start_tx, 543 .stop_rx = pl010_stop_rx, 544 .enable_ms = pl010_enable_ms, 545 .break_ctl = pl010_break_ctl, 546 .startup = pl010_startup, 547 .shutdown = pl010_shutdown, 548 .set_termios = pl010_set_termios, 549 .set_ldisc = pl010_set_ldisc, 550 .type = pl010_type, 551 .release_port = pl010_release_port, 552 .request_port = pl010_request_port, 553 .config_port = pl010_config_port, 554 .verify_port = pl010_verify_port, 555 }; 556 557 static struct uart_amba_port *amba_ports[UART_NR]; 558 559 #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE 560 561 static void pl010_console_putchar(struct uart_port *port, int ch) 562 { 563 struct uart_amba_port *uap = (struct uart_amba_port *)port; 564 unsigned int status; 565 566 do { 567 status = readb(uap->port.membase + UART01x_FR); 568 barrier(); 569 } while (!UART_TX_READY(status)); 570 writel(ch, uap->port.membase + UART01x_DR); 571 } 572 573 static void 574 pl010_console_write(struct console *co, const char *s, unsigned int count) 575 { 576 struct uart_amba_port *uap = amba_ports[co->index]; 577 unsigned int status, old_cr; 578 579 clk_enable(uap->clk); 580 581 /* 582 * First save the CR then disable the interrupts 583 */ 584 old_cr = readb(uap->port.membase + UART010_CR); 585 writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR); 586 587 uart_console_write(&uap->port, s, count, pl010_console_putchar); 588 589 /* 590 * Finally, wait for transmitter to become empty 591 * and restore the TCR 592 */ 593 do { 594 status = readb(uap->port.membase + UART01x_FR); 595 barrier(); 596 } while (status & UART01x_FR_BUSY); 597 writel(old_cr, uap->port.membase + UART010_CR); 598 599 clk_disable(uap->clk); 600 } 601 602 static void __init 603 pl010_console_get_options(struct uart_amba_port *uap, int *baud, 604 int *parity, int *bits) 605 { 606 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { 607 unsigned int lcr_h, quot; 608 lcr_h = readb(uap->port.membase + UART010_LCRH); 609 610 *parity = 'n'; 611 if (lcr_h & UART01x_LCRH_PEN) { 612 if (lcr_h & UART01x_LCRH_EPS) 613 *parity = 'e'; 614 else 615 *parity = 'o'; 616 } 617 618 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 619 *bits = 7; 620 else 621 *bits = 8; 622 623 quot = readb(uap->port.membase + UART010_LCRL) | 624 readb(uap->port.membase + UART010_LCRM) << 8; 625 *baud = uap->port.uartclk / (16 * (quot + 1)); 626 } 627 } 628 629 static int __init pl010_console_setup(struct console *co, char *options) 630 { 631 struct uart_amba_port *uap; 632 int baud = 38400; 633 int bits = 8; 634 int parity = 'n'; 635 int flow = 'n'; 636 int ret; 637 638 /* 639 * Check whether an invalid uart number has been specified, and 640 * if so, search for the first available port that does have 641 * console support. 642 */ 643 if (co->index >= UART_NR) 644 co->index = 0; 645 uap = amba_ports[co->index]; 646 if (!uap) 647 return -ENODEV; 648 649 ret = clk_prepare(uap->clk); 650 if (ret) 651 return ret; 652 653 uap->port.uartclk = clk_get_rate(uap->clk); 654 655 if (options) 656 uart_parse_options(options, &baud, &parity, &bits, &flow); 657 else 658 pl010_console_get_options(uap, &baud, &parity, &bits); 659 660 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 661 } 662 663 static struct uart_driver amba_reg; 664 static struct console amba_console = { 665 .name = "ttyAM", 666 .write = pl010_console_write, 667 .device = uart_console_device, 668 .setup = pl010_console_setup, 669 .flags = CON_PRINTBUFFER, 670 .index = -1, 671 .data = &amba_reg, 672 }; 673 674 #define AMBA_CONSOLE &amba_console 675 #else 676 #define AMBA_CONSOLE NULL 677 #endif 678 679 static struct uart_driver amba_reg = { 680 .owner = THIS_MODULE, 681 .driver_name = "ttyAM", 682 .dev_name = "ttyAM", 683 .major = SERIAL_AMBA_MAJOR, 684 .minor = SERIAL_AMBA_MINOR, 685 .nr = UART_NR, 686 .cons = AMBA_CONSOLE, 687 }; 688 689 static int pl010_probe(struct amba_device *dev, const struct amba_id *id) 690 { 691 struct uart_amba_port *uap; 692 void __iomem *base; 693 int i, ret; 694 695 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 696 if (amba_ports[i] == NULL) 697 break; 698 699 if (i == ARRAY_SIZE(amba_ports)) { 700 ret = -EBUSY; 701 goto out; 702 } 703 704 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL); 705 if (!uap) { 706 ret = -ENOMEM; 707 goto out; 708 } 709 710 base = ioremap(dev->res.start, resource_size(&dev->res)); 711 if (!base) { 712 ret = -ENOMEM; 713 goto free; 714 } 715 716 uap->clk = clk_get(&dev->dev, NULL); 717 if (IS_ERR(uap->clk)) { 718 ret = PTR_ERR(uap->clk); 719 goto unmap; 720 } 721 722 uap->port.dev = &dev->dev; 723 uap->port.mapbase = dev->res.start; 724 uap->port.membase = base; 725 uap->port.iotype = UPIO_MEM; 726 uap->port.irq = dev->irq[0]; 727 uap->port.fifosize = 16; 728 uap->port.ops = &amba_pl010_pops; 729 uap->port.flags = UPF_BOOT_AUTOCONF; 730 uap->port.line = i; 731 uap->dev = dev; 732 uap->data = dev->dev.platform_data; 733 734 amba_ports[i] = uap; 735 736 amba_set_drvdata(dev, uap); 737 ret = uart_add_one_port(&amba_reg, &uap->port); 738 if (ret) { 739 amba_set_drvdata(dev, NULL); 740 amba_ports[i] = NULL; 741 clk_put(uap->clk); 742 unmap: 743 iounmap(base); 744 free: 745 kfree(uap); 746 } 747 out: 748 return ret; 749 } 750 751 static int pl010_remove(struct amba_device *dev) 752 { 753 struct uart_amba_port *uap = amba_get_drvdata(dev); 754 int i; 755 756 amba_set_drvdata(dev, NULL); 757 758 uart_remove_one_port(&amba_reg, &uap->port); 759 760 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 761 if (amba_ports[i] == uap) 762 amba_ports[i] = NULL; 763 764 iounmap(uap->port.membase); 765 clk_put(uap->clk); 766 kfree(uap); 767 return 0; 768 } 769 770 static int pl010_suspend(struct amba_device *dev, pm_message_t state) 771 { 772 struct uart_amba_port *uap = amba_get_drvdata(dev); 773 774 if (uap) 775 uart_suspend_port(&amba_reg, &uap->port); 776 777 return 0; 778 } 779 780 static int pl010_resume(struct amba_device *dev) 781 { 782 struct uart_amba_port *uap = amba_get_drvdata(dev); 783 784 if (uap) 785 uart_resume_port(&amba_reg, &uap->port); 786 787 return 0; 788 } 789 790 static struct amba_id pl010_ids[] = { 791 { 792 .id = 0x00041010, 793 .mask = 0x000fffff, 794 }, 795 { 0, 0 }, 796 }; 797 798 MODULE_DEVICE_TABLE(amba, pl010_ids); 799 800 static struct amba_driver pl010_driver = { 801 .drv = { 802 .name = "uart-pl010", 803 }, 804 .id_table = pl010_ids, 805 .probe = pl010_probe, 806 .remove = pl010_remove, 807 .suspend = pl010_suspend, 808 .resume = pl010_resume, 809 }; 810 811 static int __init pl010_init(void) 812 { 813 int ret; 814 815 printk(KERN_INFO "Serial: AMBA driver\n"); 816 817 ret = uart_register_driver(&amba_reg); 818 if (ret == 0) { 819 ret = amba_driver_register(&pl010_driver); 820 if (ret) 821 uart_unregister_driver(&amba_reg); 822 } 823 return ret; 824 } 825 826 static void __exit pl010_exit(void) 827 { 828 amba_driver_unregister(&pl010_driver); 829 uart_unregister_driver(&amba_reg); 830 } 831 832 module_init(pl010_init); 833 module_exit(pl010_exit); 834 835 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 836 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 837 MODULE_LICENSE("GPL"); 838