1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for AMBA serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright 1999 ARM Limited 8 * Copyright (C) 2000 Deep Blue Solutions Ltd. 9 * 10 * This is a generic driver for ARM AMBA-type serial ports. They 11 * have a lot of 16550-like features, but are not register compatible. 12 * Note that although they do have CTS, DCD and DSR inputs, they do 13 * not have an RI input, nor do they have DTR or RTS outputs. If 14 * required, these have to be supplied via some other means (eg, GPIO) 15 * and hooked into this driver. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/ioport.h> 20 #include <linux/init.h> 21 #include <linux/console.h> 22 #include <linux/sysrq.h> 23 #include <linux/device.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/serial_core.h> 27 #include <linux/serial.h> 28 #include <linux/amba/bus.h> 29 #include <linux/amba/serial.h> 30 #include <linux/clk.h> 31 #include <linux/slab.h> 32 #include <linux/io.h> 33 34 #define UART_NR 8 35 36 #define SERIAL_AMBA_MAJOR 204 37 #define SERIAL_AMBA_MINOR 16 38 #define SERIAL_AMBA_NR UART_NR 39 40 #define AMBA_ISR_PASS_LIMIT 256 41 42 #define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0) 43 #define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0) 44 45 #define UART_DUMMY_RSR_RX 256 46 #define UART_PORT_SIZE 64 47 48 /* 49 * We wrap our port structure around the generic uart_port. 50 */ 51 struct uart_amba_port { 52 struct uart_port port; 53 struct clk *clk; 54 struct amba_device *dev; 55 struct amba_pl010_data *data; 56 unsigned int old_status; 57 }; 58 59 static void pl010_stop_tx(struct uart_port *port) 60 { 61 struct uart_amba_port *uap = 62 container_of(port, struct uart_amba_port, port); 63 unsigned int cr; 64 65 cr = readb(uap->port.membase + UART010_CR); 66 cr &= ~UART010_CR_TIE; 67 writel(cr, uap->port.membase + UART010_CR); 68 } 69 70 static void pl010_start_tx(struct uart_port *port) 71 { 72 struct uart_amba_port *uap = 73 container_of(port, struct uart_amba_port, port); 74 unsigned int cr; 75 76 cr = readb(uap->port.membase + UART010_CR); 77 cr |= UART010_CR_TIE; 78 writel(cr, uap->port.membase + UART010_CR); 79 } 80 81 static void pl010_stop_rx(struct uart_port *port) 82 { 83 struct uart_amba_port *uap = 84 container_of(port, struct uart_amba_port, port); 85 unsigned int cr; 86 87 cr = readb(uap->port.membase + UART010_CR); 88 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE); 89 writel(cr, uap->port.membase + UART010_CR); 90 } 91 92 static void pl010_disable_ms(struct uart_port *port) 93 { 94 struct uart_amba_port *uap = (struct uart_amba_port *)port; 95 unsigned int cr; 96 97 cr = readb(uap->port.membase + UART010_CR); 98 cr &= ~UART010_CR_MSIE; 99 writel(cr, uap->port.membase + UART010_CR); 100 } 101 102 static void pl010_enable_ms(struct uart_port *port) 103 { 104 struct uart_amba_port *uap = 105 container_of(port, struct uart_amba_port, port); 106 unsigned int cr; 107 108 cr = readb(uap->port.membase + UART010_CR); 109 cr |= UART010_CR_MSIE; 110 writel(cr, uap->port.membase + UART010_CR); 111 } 112 113 static void pl010_rx_chars(struct uart_port *port) 114 { 115 unsigned int status, ch, flag, rsr, max_count = 256; 116 117 status = readb(port->membase + UART01x_FR); 118 while (UART_RX_DATA(status) && max_count--) { 119 ch = readb(port->membase + UART01x_DR); 120 flag = TTY_NORMAL; 121 122 port->icount.rx++; 123 124 /* 125 * Note that the error handling code is 126 * out of the main execution path 127 */ 128 rsr = readb(port->membase + UART01x_RSR) | UART_DUMMY_RSR_RX; 129 if (unlikely(rsr & UART01x_RSR_ANY)) { 130 writel(0, port->membase + UART01x_ECR); 131 132 if (rsr & UART01x_RSR_BE) { 133 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); 134 port->icount.brk++; 135 if (uart_handle_break(port)) 136 goto ignore_char; 137 } else if (rsr & UART01x_RSR_PE) 138 port->icount.parity++; 139 else if (rsr & UART01x_RSR_FE) 140 port->icount.frame++; 141 if (rsr & UART01x_RSR_OE) 142 port->icount.overrun++; 143 144 rsr &= port->read_status_mask; 145 146 if (rsr & UART01x_RSR_BE) 147 flag = TTY_BREAK; 148 else if (rsr & UART01x_RSR_PE) 149 flag = TTY_PARITY; 150 else if (rsr & UART01x_RSR_FE) 151 flag = TTY_FRAME; 152 } 153 154 if (uart_handle_sysrq_char(port, ch)) 155 goto ignore_char; 156 157 uart_insert_char(port, rsr, UART01x_RSR_OE, ch, flag); 158 159 ignore_char: 160 status = readb(port->membase + UART01x_FR); 161 } 162 tty_flip_buffer_push(&port->state->port); 163 } 164 165 static void pl010_tx_chars(struct uart_port *port) 166 { 167 u8 ch; 168 169 uart_port_tx_limited(port, ch, port->fifosize >> 1, 170 true, 171 writel(ch, port->membase + UART01x_DR), 172 ({})); 173 } 174 175 static void pl010_modem_status(struct uart_amba_port *uap) 176 { 177 struct uart_port *port = &uap->port; 178 unsigned int status, delta; 179 180 writel(0, port->membase + UART010_ICR); 181 182 status = readb(port->membase + UART01x_FR) & UART01x_FR_MODEM_ANY; 183 184 delta = status ^ uap->old_status; 185 uap->old_status = status; 186 187 if (!delta) 188 return; 189 190 if (delta & UART01x_FR_DCD) 191 uart_handle_dcd_change(port, status & UART01x_FR_DCD); 192 193 if (delta & UART01x_FR_DSR) 194 port->icount.dsr++; 195 196 if (delta & UART01x_FR_CTS) 197 uart_handle_cts_change(port, status & UART01x_FR_CTS); 198 199 wake_up_interruptible(&port->state->port.delta_msr_wait); 200 } 201 202 static irqreturn_t pl010_int(int irq, void *dev_id) 203 { 204 struct uart_amba_port *uap = dev_id; 205 struct uart_port *port = &uap->port; 206 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 207 int handled = 0; 208 209 spin_lock(&port->lock); 210 211 status = readb(port->membase + UART010_IIR); 212 if (status) { 213 do { 214 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS)) 215 pl010_rx_chars(port); 216 if (status & UART010_IIR_MIS) 217 pl010_modem_status(uap); 218 if (status & UART010_IIR_TIS) 219 pl010_tx_chars(port); 220 221 if (pass_counter-- == 0) 222 break; 223 224 status = readb(port->membase + UART010_IIR); 225 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS | 226 UART010_IIR_TIS)); 227 handled = 1; 228 } 229 230 spin_unlock(&port->lock); 231 232 return IRQ_RETVAL(handled); 233 } 234 235 static unsigned int pl010_tx_empty(struct uart_port *port) 236 { 237 unsigned int status = readb(port->membase + UART01x_FR); 238 239 return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT; 240 } 241 242 static unsigned int pl010_get_mctrl(struct uart_port *port) 243 { 244 unsigned int result = 0; 245 unsigned int status; 246 247 status = readb(port->membase + UART01x_FR); 248 if (status & UART01x_FR_DCD) 249 result |= TIOCM_CAR; 250 if (status & UART01x_FR_DSR) 251 result |= TIOCM_DSR; 252 if (status & UART01x_FR_CTS) 253 result |= TIOCM_CTS; 254 255 return result; 256 } 257 258 static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl) 259 { 260 struct uart_amba_port *uap = 261 container_of(port, struct uart_amba_port, port); 262 263 if (uap->data) 264 uap->data->set_mctrl(uap->dev, port->membase, mctrl); 265 } 266 267 static void pl010_break_ctl(struct uart_port *port, int break_state) 268 { 269 unsigned long flags; 270 unsigned int lcr_h; 271 272 spin_lock_irqsave(&port->lock, flags); 273 lcr_h = readb(port->membase + UART010_LCRH); 274 if (break_state == -1) 275 lcr_h |= UART01x_LCRH_BRK; 276 else 277 lcr_h &= ~UART01x_LCRH_BRK; 278 writel(lcr_h, port->membase + UART010_LCRH); 279 spin_unlock_irqrestore(&port->lock, flags); 280 } 281 282 static int pl010_startup(struct uart_port *port) 283 { 284 struct uart_amba_port *uap = 285 container_of(port, struct uart_amba_port, port); 286 int retval; 287 288 /* 289 * Try to enable the clock producer. 290 */ 291 retval = clk_prepare_enable(uap->clk); 292 if (retval) 293 goto out; 294 295 port->uartclk = clk_get_rate(uap->clk); 296 297 /* 298 * Allocate the IRQ 299 */ 300 retval = request_irq(port->irq, pl010_int, 0, "uart-pl010", uap); 301 if (retval) 302 goto clk_dis; 303 304 /* 305 * initialise the old status of the modem signals 306 */ 307 uap->old_status = readb(port->membase + UART01x_FR) & UART01x_FR_MODEM_ANY; 308 309 /* 310 * Finally, enable interrupts 311 */ 312 writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE, 313 port->membase + UART010_CR); 314 315 return 0; 316 317 clk_dis: 318 clk_disable_unprepare(uap->clk); 319 out: 320 return retval; 321 } 322 323 static void pl010_shutdown(struct uart_port *port) 324 { 325 struct uart_amba_port *uap = 326 container_of(port, struct uart_amba_port, port); 327 328 /* 329 * Free the interrupt 330 */ 331 free_irq(port->irq, uap); 332 333 /* 334 * disable all interrupts, disable the port 335 */ 336 writel(0, port->membase + UART010_CR); 337 338 /* disable break condition and fifos */ 339 writel(readb(port->membase + UART010_LCRH) & 340 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN), 341 port->membase + UART010_LCRH); 342 343 /* 344 * Shut down the clock producer 345 */ 346 clk_disable_unprepare(uap->clk); 347 } 348 349 static void 350 pl010_set_termios(struct uart_port *port, struct ktermios *termios, 351 const struct ktermios *old) 352 { 353 unsigned int lcr_h, old_cr; 354 unsigned long flags; 355 unsigned int baud, quot; 356 357 /* 358 * Ask the core to calculate the divisor for us. 359 */ 360 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 361 quot = uart_get_divisor(port, baud); 362 363 switch (termios->c_cflag & CSIZE) { 364 case CS5: 365 lcr_h = UART01x_LCRH_WLEN_5; 366 break; 367 case CS6: 368 lcr_h = UART01x_LCRH_WLEN_6; 369 break; 370 case CS7: 371 lcr_h = UART01x_LCRH_WLEN_7; 372 break; 373 default: // CS8 374 lcr_h = UART01x_LCRH_WLEN_8; 375 break; 376 } 377 if (termios->c_cflag & CSTOPB) 378 lcr_h |= UART01x_LCRH_STP2; 379 if (termios->c_cflag & PARENB) { 380 lcr_h |= UART01x_LCRH_PEN; 381 if (!(termios->c_cflag & PARODD)) 382 lcr_h |= UART01x_LCRH_EPS; 383 } 384 if (port->fifosize > 1) 385 lcr_h |= UART01x_LCRH_FEN; 386 387 spin_lock_irqsave(&port->lock, flags); 388 389 /* 390 * Update the per-port timeout. 391 */ 392 uart_update_timeout(port, termios->c_cflag, baud); 393 394 port->read_status_mask = UART01x_RSR_OE; 395 if (termios->c_iflag & INPCK) 396 port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; 397 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 398 port->read_status_mask |= UART01x_RSR_BE; 399 400 /* 401 * Characters to ignore 402 */ 403 port->ignore_status_mask = 0; 404 if (termios->c_iflag & IGNPAR) 405 port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; 406 if (termios->c_iflag & IGNBRK) { 407 port->ignore_status_mask |= UART01x_RSR_BE; 408 /* 409 * If we're ignoring parity and break indicators, 410 * ignore overruns too (for real raw support). 411 */ 412 if (termios->c_iflag & IGNPAR) 413 port->ignore_status_mask |= UART01x_RSR_OE; 414 } 415 416 /* 417 * Ignore all characters if CREAD is not set. 418 */ 419 if ((termios->c_cflag & CREAD) == 0) 420 port->ignore_status_mask |= UART_DUMMY_RSR_RX; 421 422 old_cr = readb(port->membase + UART010_CR) & ~UART010_CR_MSIE; 423 424 if (UART_ENABLE_MS(port, termios->c_cflag)) 425 old_cr |= UART010_CR_MSIE; 426 427 /* Set baud rate */ 428 quot -= 1; 429 writel((quot & 0xf00) >> 8, port->membase + UART010_LCRM); 430 writel(quot & 0xff, port->membase + UART010_LCRL); 431 432 /* 433 * ----------v----------v----------v----------v----- 434 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L 435 * ----------^----------^----------^----------^----- 436 */ 437 writel(lcr_h, port->membase + UART010_LCRH); 438 writel(old_cr, port->membase + UART010_CR); 439 440 spin_unlock_irqrestore(&port->lock, flags); 441 } 442 443 static void pl010_set_ldisc(struct uart_port *port, struct ktermios *termios) 444 { 445 if (termios->c_line == N_PPS) { 446 port->flags |= UPF_HARDPPS_CD; 447 spin_lock_irq(&port->lock); 448 pl010_enable_ms(port); 449 spin_unlock_irq(&port->lock); 450 } else { 451 port->flags &= ~UPF_HARDPPS_CD; 452 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 453 spin_lock_irq(&port->lock); 454 pl010_disable_ms(port); 455 spin_unlock_irq(&port->lock); 456 } 457 } 458 } 459 460 static const char *pl010_type(struct uart_port *port) 461 { 462 return port->type == PORT_AMBA ? "AMBA" : NULL; 463 } 464 465 /* 466 * Release the memory region(s) being used by 'port' 467 */ 468 static void pl010_release_port(struct uart_port *port) 469 { 470 release_mem_region(port->mapbase, UART_PORT_SIZE); 471 } 472 473 /* 474 * Request the memory region(s) being used by 'port' 475 */ 476 static int pl010_request_port(struct uart_port *port) 477 { 478 return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010") 479 != NULL ? 0 : -EBUSY; 480 } 481 482 /* 483 * Configure/autoconfigure the port. 484 */ 485 static void pl010_config_port(struct uart_port *port, int flags) 486 { 487 if (flags & UART_CONFIG_TYPE) { 488 port->type = PORT_AMBA; 489 pl010_request_port(port); 490 } 491 } 492 493 /* 494 * verify the new serial_struct (for TIOCSSERIAL). 495 */ 496 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) 497 { 498 int ret = 0; 499 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 500 ret = -EINVAL; 501 if (ser->irq < 0 || ser->irq >= nr_irqs) 502 ret = -EINVAL; 503 if (ser->baud_base < 9600) 504 ret = -EINVAL; 505 return ret; 506 } 507 508 static const struct uart_ops amba_pl010_pops = { 509 .tx_empty = pl010_tx_empty, 510 .set_mctrl = pl010_set_mctrl, 511 .get_mctrl = pl010_get_mctrl, 512 .stop_tx = pl010_stop_tx, 513 .start_tx = pl010_start_tx, 514 .stop_rx = pl010_stop_rx, 515 .enable_ms = pl010_enable_ms, 516 .break_ctl = pl010_break_ctl, 517 .startup = pl010_startup, 518 .shutdown = pl010_shutdown, 519 .set_termios = pl010_set_termios, 520 .set_ldisc = pl010_set_ldisc, 521 .type = pl010_type, 522 .release_port = pl010_release_port, 523 .request_port = pl010_request_port, 524 .config_port = pl010_config_port, 525 .verify_port = pl010_verify_port, 526 }; 527 528 static struct uart_amba_port *amba_ports[UART_NR]; 529 530 #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE 531 532 static void pl010_console_putchar(struct uart_port *port, unsigned char ch) 533 { 534 unsigned int status; 535 536 do { 537 status = readb(port->membase + UART01x_FR); 538 barrier(); 539 } while (!UART_TX_READY(status)); 540 writel(ch, port->membase + UART01x_DR); 541 } 542 543 static void 544 pl010_console_write(struct console *co, const char *s, unsigned int count) 545 { 546 struct uart_amba_port *uap = amba_ports[co->index]; 547 struct uart_port *port = &uap->port; 548 unsigned int status, old_cr; 549 550 clk_enable(uap->clk); 551 552 /* 553 * First save the CR then disable the interrupts 554 */ 555 old_cr = readb(port->membase + UART010_CR); 556 writel(UART01x_CR_UARTEN, port->membase + UART010_CR); 557 558 uart_console_write(port, s, count, pl010_console_putchar); 559 560 /* 561 * Finally, wait for transmitter to become empty 562 * and restore the TCR 563 */ 564 do { 565 status = readb(port->membase + UART01x_FR); 566 barrier(); 567 } while (status & UART01x_FR_BUSY); 568 writel(old_cr, port->membase + UART010_CR); 569 570 clk_disable(uap->clk); 571 } 572 573 static void __init 574 pl010_console_get_options(struct uart_amba_port *uap, int *baud, 575 int *parity, int *bits) 576 { 577 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { 578 unsigned int lcr_h, quot; 579 lcr_h = readb(uap->port.membase + UART010_LCRH); 580 581 *parity = 'n'; 582 if (lcr_h & UART01x_LCRH_PEN) { 583 if (lcr_h & UART01x_LCRH_EPS) 584 *parity = 'e'; 585 else 586 *parity = 'o'; 587 } 588 589 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 590 *bits = 7; 591 else 592 *bits = 8; 593 594 quot = readb(uap->port.membase + UART010_LCRL) | 595 readb(uap->port.membase + UART010_LCRM) << 8; 596 *baud = uap->port.uartclk / (16 * (quot + 1)); 597 } 598 } 599 600 static int __init pl010_console_setup(struct console *co, char *options) 601 { 602 struct uart_amba_port *uap; 603 int baud = 38400; 604 int bits = 8; 605 int parity = 'n'; 606 int flow = 'n'; 607 int ret; 608 609 /* 610 * Check whether an invalid uart number has been specified, and 611 * if so, search for the first available port that does have 612 * console support. 613 */ 614 if (co->index >= UART_NR) 615 co->index = 0; 616 uap = amba_ports[co->index]; 617 if (!uap) 618 return -ENODEV; 619 620 ret = clk_prepare(uap->clk); 621 if (ret) 622 return ret; 623 624 uap->port.uartclk = clk_get_rate(uap->clk); 625 626 if (options) 627 uart_parse_options(options, &baud, &parity, &bits, &flow); 628 else 629 pl010_console_get_options(uap, &baud, &parity, &bits); 630 631 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 632 } 633 634 static struct uart_driver amba_reg; 635 static struct console amba_console = { 636 .name = "ttyAM", 637 .write = pl010_console_write, 638 .device = uart_console_device, 639 .setup = pl010_console_setup, 640 .flags = CON_PRINTBUFFER, 641 .index = -1, 642 .data = &amba_reg, 643 }; 644 645 #define AMBA_CONSOLE &amba_console 646 #else 647 #define AMBA_CONSOLE NULL 648 #endif 649 650 static DEFINE_MUTEX(amba_reg_lock); 651 static struct uart_driver amba_reg = { 652 .owner = THIS_MODULE, 653 .driver_name = "ttyAM", 654 .dev_name = "ttyAM", 655 .major = SERIAL_AMBA_MAJOR, 656 .minor = SERIAL_AMBA_MINOR, 657 .nr = UART_NR, 658 .cons = AMBA_CONSOLE, 659 }; 660 661 static int pl010_probe(struct amba_device *dev, const struct amba_id *id) 662 { 663 struct uart_amba_port *uap; 664 void __iomem *base; 665 int i, ret; 666 667 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 668 if (amba_ports[i] == NULL) 669 break; 670 671 if (i == ARRAY_SIZE(amba_ports)) 672 return -EBUSY; 673 674 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), 675 GFP_KERNEL); 676 if (!uap) 677 return -ENOMEM; 678 679 base = devm_ioremap(&dev->dev, dev->res.start, 680 resource_size(&dev->res)); 681 if (!base) 682 return -ENOMEM; 683 684 uap->clk = devm_clk_get(&dev->dev, NULL); 685 if (IS_ERR(uap->clk)) 686 return PTR_ERR(uap->clk); 687 688 uap->port.dev = &dev->dev; 689 uap->port.mapbase = dev->res.start; 690 uap->port.membase = base; 691 uap->port.iotype = UPIO_MEM; 692 uap->port.irq = dev->irq[0]; 693 uap->port.fifosize = 16; 694 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL010_CONSOLE); 695 uap->port.ops = &amba_pl010_pops; 696 uap->port.flags = UPF_BOOT_AUTOCONF; 697 uap->port.line = i; 698 uap->dev = dev; 699 uap->data = dev_get_platdata(&dev->dev); 700 701 amba_ports[i] = uap; 702 703 amba_set_drvdata(dev, uap); 704 705 mutex_lock(&amba_reg_lock); 706 if (!amba_reg.state) { 707 ret = uart_register_driver(&amba_reg); 708 if (ret < 0) { 709 mutex_unlock(&amba_reg_lock); 710 dev_err(uap->port.dev, 711 "Failed to register AMBA-PL010 driver\n"); 712 return ret; 713 } 714 } 715 mutex_unlock(&amba_reg_lock); 716 717 ret = uart_add_one_port(&amba_reg, &uap->port); 718 if (ret) 719 amba_ports[i] = NULL; 720 721 return ret; 722 } 723 724 static void pl010_remove(struct amba_device *dev) 725 { 726 struct uart_amba_port *uap = amba_get_drvdata(dev); 727 int i; 728 bool busy = false; 729 730 uart_remove_one_port(&amba_reg, &uap->port); 731 732 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 733 if (amba_ports[i] == uap) 734 amba_ports[i] = NULL; 735 else if (amba_ports[i]) 736 busy = true; 737 738 if (!busy) 739 uart_unregister_driver(&amba_reg); 740 } 741 742 #ifdef CONFIG_PM_SLEEP 743 static int pl010_suspend(struct device *dev) 744 { 745 struct uart_amba_port *uap = dev_get_drvdata(dev); 746 747 if (uap) 748 uart_suspend_port(&amba_reg, &uap->port); 749 750 return 0; 751 } 752 753 static int pl010_resume(struct device *dev) 754 { 755 struct uart_amba_port *uap = dev_get_drvdata(dev); 756 757 if (uap) 758 uart_resume_port(&amba_reg, &uap->port); 759 760 return 0; 761 } 762 #endif 763 764 static SIMPLE_DEV_PM_OPS(pl010_dev_pm_ops, pl010_suspend, pl010_resume); 765 766 static const struct amba_id pl010_ids[] = { 767 { 768 .id = 0x00041010, 769 .mask = 0x000fffff, 770 }, 771 { 0, 0 }, 772 }; 773 774 MODULE_DEVICE_TABLE(amba, pl010_ids); 775 776 static struct amba_driver pl010_driver = { 777 .drv = { 778 .name = "uart-pl010", 779 .pm = &pl010_dev_pm_ops, 780 }, 781 .id_table = pl010_ids, 782 .probe = pl010_probe, 783 .remove = pl010_remove, 784 }; 785 786 static int __init pl010_init(void) 787 { 788 printk(KERN_INFO "Serial: AMBA driver\n"); 789 790 return amba_driver_register(&pl010_driver); 791 } 792 793 static void __exit pl010_exit(void) 794 { 795 amba_driver_unregister(&pl010_driver); 796 } 797 798 module_init(pl010_init); 799 module_exit(pl010_exit); 800 801 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 802 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 803 MODULE_LICENSE("GPL"); 804