1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Serial Port driver for Tegra devices
4  *
5  *  Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
6  */
7 
8 #include <linux/acpi.h>
9 #include <linux/clk.h>
10 #include <linux/console.h>
11 #include <linux/delay.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/reset.h>
15 #include <linux/slab.h>
16 
17 #include "8250.h"
18 
19 struct tegra_uart {
20 	struct clk *clk;
21 	struct reset_control *rst;
22 	int line;
23 };
24 
25 static void tegra_uart_handle_break(struct uart_port *p)
26 {
27 	unsigned int status, tmout = 10000;
28 
29 	while (1) {
30 		status = p->serial_in(p, UART_LSR);
31 		if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)))
32 			break;
33 
34 		p->serial_in(p, UART_RX);
35 
36 		if (--tmout == 0)
37 			break;
38 		udelay(1);
39 	}
40 }
41 
42 static int tegra_uart_probe(struct platform_device *pdev)
43 {
44 	struct uart_8250_port port8250;
45 	struct tegra_uart *uart;
46 	struct uart_port *port;
47 	struct resource *res;
48 	int ret;
49 
50 	uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL);
51 	if (!uart)
52 		return -ENOMEM;
53 
54 	memset(&port8250, 0, sizeof(port8250));
55 
56 	port = &port8250.port;
57 	spin_lock_init(&port->lock);
58 
59 	port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT |
60 		      UPF_FIXED_TYPE;
61 	port->iotype = UPIO_MEM32;
62 	port->regshift = 2;
63 	port->type = PORT_TEGRA;
64 	port->irqflags |= IRQF_SHARED;
65 	port->dev = &pdev->dev;
66 	port->handle_break = tegra_uart_handle_break;
67 
68 	ret = of_alias_get_id(pdev->dev.of_node, "serial");
69 	if (ret >= 0)
70 		port->line = ret;
71 
72 	ret = platform_get_irq(pdev, 0);
73 	if (ret < 0)
74 		return ret;
75 
76 	port->irq = ret;
77 
78 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
79 	if (!res)
80 		return -ENODEV;
81 
82 	port->membase = devm_ioremap(&pdev->dev, res->start,
83 				     resource_size(res));
84 	if (!port->membase)
85 		return -ENOMEM;
86 
87 	port->mapbase = res->start;
88 	port->mapsize = resource_size(res);
89 
90 	uart->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
91 	if (IS_ERR(uart->rst))
92 		return PTR_ERR(uart->rst);
93 
94 	if (device_property_read_u32(&pdev->dev, "clock-frequency",
95 				     &port->uartclk)) {
96 		uart->clk = devm_clk_get(&pdev->dev, NULL);
97 		if (IS_ERR(uart->clk)) {
98 			dev_err(&pdev->dev, "failed to get clock!\n");
99 			return -ENODEV;
100 		}
101 
102 		ret = clk_prepare_enable(uart->clk);
103 		if (ret < 0)
104 			return ret;
105 
106 		port->uartclk = clk_get_rate(uart->clk);
107 	}
108 
109 	ret = reset_control_deassert(uart->rst);
110 	if (ret)
111 		goto err_clkdisable;
112 
113 	ret = serial8250_register_8250_port(&port8250);
114 	if (ret < 0)
115 		goto err_clkdisable;
116 
117 	platform_set_drvdata(pdev, uart);
118 	uart->line = ret;
119 
120 	return 0;
121 
122 err_clkdisable:
123 	clk_disable_unprepare(uart->clk);
124 
125 	return ret;
126 }
127 
128 static int tegra_uart_remove(struct platform_device *pdev)
129 {
130 	struct tegra_uart *uart = platform_get_drvdata(pdev);
131 
132 	serial8250_unregister_port(uart->line);
133 	reset_control_assert(uart->rst);
134 	clk_disable_unprepare(uart->clk);
135 
136 	return 0;
137 }
138 
139 #ifdef CONFIG_PM_SLEEP
140 static int tegra_uart_suspend(struct device *dev)
141 {
142 	struct tegra_uart *uart = dev_get_drvdata(dev);
143 	struct uart_8250_port *port8250 = serial8250_get_port(uart->line);
144 	struct uart_port *port = &port8250->port;
145 
146 	serial8250_suspend_port(uart->line);
147 
148 	if (!uart_console(port) || console_suspend_enabled)
149 		clk_disable_unprepare(uart->clk);
150 
151 	return 0;
152 }
153 
154 static int tegra_uart_resume(struct device *dev)
155 {
156 	struct tegra_uart *uart = dev_get_drvdata(dev);
157 	struct uart_8250_port *port8250 = serial8250_get_port(uart->line);
158 	struct uart_port *port = &port8250->port;
159 
160 	if (!uart_console(port) || console_suspend_enabled)
161 		clk_prepare_enable(uart->clk);
162 
163 	serial8250_resume_port(uart->line);
164 
165 	return 0;
166 }
167 #endif
168 
169 static SIMPLE_DEV_PM_OPS(tegra_uart_pm_ops, tegra_uart_suspend,
170 			 tegra_uart_resume);
171 
172 static const struct of_device_id tegra_uart_of_match[] = {
173 	{ .compatible = "nvidia,tegra20-uart", },
174 	{ },
175 };
176 MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
177 
178 static const struct acpi_device_id tegra_uart_acpi_match[] = {
179 	{ "NVDA0100", 0 },
180 	{ },
181 };
182 MODULE_DEVICE_TABLE(acpi, tegra_uart_acpi_match);
183 
184 static struct platform_driver tegra_uart_driver = {
185 	.driver = {
186 		.name = "tegra-uart",
187 		.pm = &tegra_uart_pm_ops,
188 		.of_match_table = tegra_uart_of_match,
189 		.acpi_match_table = ACPI_PTR(tegra_uart_acpi_match),
190 	},
191 	.probe = tegra_uart_probe,
192 	.remove = tegra_uart_remove,
193 };
194 
195 module_platform_driver(tegra_uart_driver);
196 
197 MODULE_AUTHOR("Jeff Brasen <jbrasen@nvidia.com>");
198 MODULE_DESCRIPTION("NVIDIA Tegra 8250 Driver");
199 MODULE_LICENSE("GPL v2");
200